{
    "metadata": {
        "prompt_num_line": 5,
        "min_lines": 20
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    "data": {
        "static int __init cops_irq (int ioaddr, int board)\n{       /*\n         * This does not use the IRQ to determine where the IRQ is. We just\n         * assume that when we get a correct status response that it's the IRQ.\n         * This really just verifies the IO port but since we only have access": "static int __init cops_irq (int ioaddr, int board)\n{       /*\n         * This does not use the IRQ to determine where the IRQ is. We just\n         * assume that when we get a correct status response that it's the IRQ.\n         * This really just verifies the IO port but since we only have access\n         * to such a small number of IRQs (5, 4, 3) this is not bad.\n         * This will probably not work for more than one card.\n         */\n        int irqaddr=0;\n        int i, x, status;\n\n        if(board==DAYNA)\n        {\n                outb(0, ioaddr+DAYNA_RESET);\n                inb(ioaddr+DAYNA_RESET);\n                mdelay(333);\n        }\n        if(board==TANGENT)\n        {\n                inb(ioaddr);\n                outb(0, ioaddr);\n                outb(0, ioaddr+TANG_RESET);\n        }\n\n        for(i=0; cops_irqlist[i] !=0; i++)\n        {\n                irqaddr = cops_irqlist[i];\n                for(x = 0xFFFF; x>0; x --)    /* wait for response */\n                {\n                        if(board==DAYNA)\n                        {\n                                status = (inb(ioaddr+DAYNA_CARD_STATUS)&3);\n                                if(status == 1)\n                                        return irqaddr;\n                        }\n                        if(board==TANGENT)\n                        {\n                                if((inb(ioaddr+TANG_CARD_STATUS)& TANG_TX_READY) !=0)\n                                        return irqaddr;\n                        }\n                }\n        }\n        return 0;       /* no IRQ found */\n}",
        "static void HUF_sort(nodeElt* huffNode, const unsigned* count, U32 maxSymbolValue, rankPos* rankPosition)\n{\n    int n;\n    int const maxSymbolValue1 = (int)maxSymbolValue + 1;\n": "static void HUF_sort(nodeElt* huffNode, const unsigned* count, U32 maxSymbolValue, rankPos* rankPosition)\n{\n    int n;\n    int const maxSymbolValue1 = (int)maxSymbolValue + 1;\n\n    /* Compute base and set curr to base.\n     * For symbol s let lowerRank = BIT_highbit32(count[n]+1) and rank = lowerRank + 1.\n     * Then 2^lowerRank <= count[n]+1 <= 2^rank.\n     * We attribute each symbol to lowerRank's base value, because we want to know where\n     * each rank begins in the output, so for rank R we want to count ranks R+1 and above.\n     */\n    ZSTD_memset(rankPosition, 0, sizeof(*rankPosition) * RANK_POSITION_TABLE_SIZE);\n    for (n = 0; n < maxSymbolValue1; ++n) {\n        U32 lowerRank = BIT_highbit32(count[n] + 1);\n        rankPosition[lowerRank].base++;\n    }\n    assert(rankPosition[RANK_POSITION_TABLE_SIZE - 1].base == 0);\n    for (n = RANK_POSITION_TABLE_SIZE - 1; n > 0; --n) {\n        rankPosition[n-1].base += rankPosition[n].base;\n        rankPosition[n-1].curr = rankPosition[n-1].base;\n    }\n    /* Sort */\n    for (n = 0; n < maxSymbolValue1; ++n) {\n        U32 const c = count[n];\n        U32 const r = BIT_highbit32(c+1) + 1;\n        U32 pos = rankPosition[r].curr++;\n        /* Insert into the correct position in the rank.\n         * We have at most 256 symbols, so this insertion should be fine.\n         */\n        while ((pos > rankPosition[r].base) && (c > huffNode[pos-1].count)) {\n            huffNode[pos] = huffNode[pos-1];\n            pos--;\n        }\n        huffNode[pos].count = c;\n        huffNode[pos].byte  = (BYTE)n;\n    }\n}",
        "static void ae7_post_dsp_asi_setup(struct hda_codec *codec)\n{\n\tchipio_8051_write_direct(codec, 0x93, 0x10);\n\n\tchipio_8051_write_pll_pmu(codec, 0x44, 0xc2);": "static void ae7_post_dsp_asi_setup(struct hda_codec *codec)\n{\n\tchipio_8051_write_direct(codec, 0x93, 0x10);\n\n\tchipio_8051_write_pll_pmu(codec, 0x44, 0xc2);\n\n\tca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);\n\tca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);\n\n\tchipio_set_control_param(codec, 3, 3);\n\tchipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);\n\n\tsnd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);\n\tchipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);\n\tsnd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);\n\n\tchipio_8051_write_exram(codec, 0xfa92, 0x22);\n\n\tae7_post_dsp_pll_setup(codec);\n\tae7_post_dsp_asi_stream_setup(codec);\n\n\tchipio_8051_write_pll_pmu(codec, 0x43, 0xc7);\n\n\tae7_post_dsp_asi_setup_ports(codec);\n}",
        "static void show_usage(void)\n{\n\tprintf(\n\"Usage: %s [OPTION]...\\n\\n\"\n\"Collect closely occurring latencies from %s\\n\"": "static void show_usage(void)\n{\n\tprintf(\n\"Usage: %s [OPTION]...\\n\\n\"\n\"Collect closely occurring latencies from %s\\n\"\n\"with any of the following tracers: preemptirqsoff, preemptoff, irqsoff, \"\n\"wakeup,\\nwakeup_dl, or wakeup_rt.\\n\\n\"\n\n\"The occurrence of a latency is detected by monitoring the file\\n\"\n\"%s with inotify.\\n\\n\"\n\n\"The following options are supported:\\n\\n\"\n\n\"-l, --list\\t\\tList the latency tracers that are supported by the\\n\"\n\"\\t\\t\\tcurrently running Linux kernel. If you don't see the\\n\"\n\"\\t\\t\\ttracer that you want, you will probably need to\\n\"\n\"\\t\\t\\tchange your kernel config and build a new kernel.\\n\\n\"\n\n\"-t, --tracer TR\\t\\tUse the tracer TR. The default is to use the first\\n\"\n\"\\t\\t\\ttracer that is supported by the kernel in the following\\n\"\n\"\\t\\t\\torder of precedence:\\n\\n\"\n\"\\t\\t\\tpreemptirqsoff\\n\"\n\"\\t\\t\\tpreemptoff\\n\"\n\"\\t\\t\\tirqsoff\\n\"\n\"\\t\\t\\twakeup\\n\"\n\"\\t\\t\\twakeup_rt\\n\"\n\"\\t\\t\\twakeup_dl\\n\"\n\"\\n\"\n\"\\t\\t\\tIf TR is not on the list above, then a warning will be\\n\"\n\"\\t\\t\\tprinted.\\n\\n\"\n\n\"-F, --force\\t\\tProceed even if another ftrace tracer is active. Without\\n\"\n\"\\t\\t\\tthis option, the program will refuse to start tracing if\\n\"\n\"\\t\\t\\tany other tracer than the nop tracer is active.\\n\\n\"\n\n\"-s, --threshold TH\\tConfigure ftrace to use a threshold of TH microseconds\\n\"\n\"\\t\\t\\tfor the tracer. The default is 0, which means that\\n\"\n\"\\t\\t\\ttracing_max_latency will be used. tracing_max_latency is\\n\"\n\"\\t\\t\\tset to 0 when the program is started and contains the\\n\"\n\"\\t\\t\\tmaximum of the latencies that have been encountered.\\n\\n\"\n\n\"-f, --function\\t\\tEnable the function-trace option in trace_options. With\\n\"\n\"\\t\\t\\tthis option, ftrace will trace the functions that are\\n\"\n\"\\t\\t\\texecuted during a latency, without it we only get the\\n\"\n\"\\t\\t\\tbeginning, end, and backtrace.\\n\\n\"\n\n\"-g, --graph\\t\\tEnable the display-graph option in trace_option. This\\n\"\n\"\\t\\t\\toption causes ftrace to show the graph of how functions\\n\"\n\"\\t\\t\\tare calling other functions.\\n\\n\"\n\n\"-c, --policy POL\\tRun the program with scheduling policy POL. POL can be\\n\"\n\"\\t\\t\\tother, batch, idle, rr or fifo. The default is rr. When\\n\"\n\"\\t\\t\\tusing rr or fifo, remember that these policies may cause\\n\"\n\"\\t\\t\\tother tasks to experience latencies.\\n\\n\"\n\n\"-p, --priority PRI\\tRun the program with priority PRI. The acceptable range\\n\"\n\"\\t\\t\\tof PRI depends on the scheduling policy.\\n\\n\"\n\n\"-n, --notrace\\t\\tIf latency is detected, do not print out the content of\\n\"\n\"\\t\\t\\tthe trace file to standard output\\n\\n\"\n\n\"-t, --threads NRTHR\\tRun NRTHR threads for printing. Default is %d.\\n\\n\"\n\n\"-r, --random\\t\\tArbitrarily sleep a certain amount of time, default\\n\"\n\"\\t\\t\\t%ld ms, before reading the trace file. The\\n\"\n\"\\t\\t\\tprobabilities for sleep are chosen so that the\\n\"\n\"\\t\\t\\tprobability of obtaining any of a cluster of closely\\n\"\n\"\\t\\t\\toccurring latencies are equal, i.e. we will randomly\\n\"\n\"\\t\\t\\tchoose which one we collect from the trace file.\\n\\n\"\n\"\\t\\t\\tThis option is probably only useful with the irqsoff,\\n\"\n\"\\t\\t\\tpreemptoff, and preemptirqsoff tracers.\\n\\n\"\n\n\"-a, --nrlat NRLAT\\tFor the purpose of arbitrary delay, assume that there\\n\"\n\"\\t\\t\\tare no more than NRLAT clustered latencies. If NRLAT\\n\"\n\"\\t\\t\\tlatencies are detected during a run, this value will\\n\"\n\"\\t\\t\\tautomatically be increased to NRLAT + 1 and then to\\n\"\n\"\\t\\t\\tNRLAT + 2 and so on. The default is %d. This option\\n\"\n\"\\t\\t\\timplies -r. We need to know this number in order to\\n\"\n\"\\t\\t\\tbe able to calculate the probabilities of sleeping.\\n\"\n\"\\t\\t\\tSpecifically, the probabilities of not sleeping, i.e. to\\n\"\n\"\\t\\t\\tdo an immediate printout will be:\\n\\n\"\n\"\\t\\t\\t1/NRLAT  1/(NRLAT - 1) ... 1/3  1/2  1\\n\\n\"\n\"\\t\\t\\tThe probability of sleeping will be:\\n\\n\"\n\"\\t\\t\\t1 - P, where P is from the series above\\n\\n\"\n\"\\t\\t\\tThis descending probability will cause us to choose\\n\"\n\"\\t\\t\\tan occurrence at random. Observe that the final\\n\"\n\"\\t\\t\\tprobability is 0, it is when we reach this probability\\n\"\n\"\\t\\t\\tthat we increase NRLAT automatically. As an example,\\n\"\n\"\\t\\t\\twith the default value of 2, the probabilities will be:\\n\\n\"\n\"\\t\\t\\t1/2  0\\n\\n\"\n\"\\t\\t\\tThis means, when a latency is detected we will sleep\\n\"\n\"\\t\\t\\twith 50%% probability. If we ever detect another latency\\n\"\n\"\\t\\t\\tduring the sleep period, then the probability of sleep\\n\"\n\"\\t\\t\\twill be 0%% and the table will be expanded to:\\n\\n\"\n\"\\t\\t\\t1/3  1/2  0\\n\\n\"\n\n\"-v, --verbose\\t\\tIncrease the verbosity. If this option is given once,\\n\"\n\"\\t\\t\\tthen print a message every time that the NRLAT value\\n\"\n\"\\t\\t\\tis automatically increased. It also causes a message to\\n\"\n\"\\t\\t\\tbe printed when the ftrace settings are changed. If this\\n\"\n\"\\t\\t\\toption is given at least twice, then also print a\\n\"\n\"\\t\\t\\twarning for lost events.\\n\\n\"\n\n\"-u, --time TIME\\t\\tArbitrarily sleep for a specified time TIME ms before\\n\"\n\"\\t\\t\\tprinting out the trace from the trace file. The default\\n\"\n\"\\t\\t\\tis %ld ms. This option implies -r.\\n\\n\"\n\n\"-x, --no-ftrace\\t\\tDo not configure ftrace. This assume that the user\\n\"\n\"\\t\\t\\tconfigures the ftrace files in sysfs such as\\n\"\n\"\\t\\t\\t/sys/kernel/tracing/current_tracer or equivalent.\\n\\n\"\n\n\"-i, --tracefile FILE\\tUse FILE as trace file. The default is\\n\"\n\"\\t\\t\\t%s.\\n\"\n\"\\t\\t\\tThis options implies -x\\n\\n\"\n\n\"-m, --max-lat FILE\\tUse FILE as tracing_max_latency file. The default is\\n\"\n\"\\t\\t\\t%s.\\n\"\n\"\\t\\t\\tThis options implies -x\\n\\n\"\n,\nprg_name, debug_tracefile_dflt, debug_maxlat_dflt, DEFAULT_NR_PRINTER_THREADS,\nSLEEP_TIME_MS_DEFAULT, DEFAULT_TABLE_SIZE, SLEEP_TIME_MS_DEFAULT,\ndebug_tracefile_dflt, debug_maxlat_dflt);\n}",
        "static int cake_config_diffserv4(struct Qdisc *sch)\n{\n/*  Further pruned list of traffic classes for four-class system:\n *\n *\t    Latency Sensitive  (CS7, CS6, EF, VA, CS5, CS4)": "static int cake_config_diffserv4(struct Qdisc *sch)\n{\n/*  Further pruned list of traffic classes for four-class system:\n *\n *\t    Latency Sensitive  (CS7, CS6, EF, VA, CS5, CS4)\n *\t    Streaming Media    (AF4x, AF3x, CS3, AF2x, TOS4, CS2)\n *\t    Best Effort        (DF, AF1x, TOS2, and those not specified)\n *\t    Background Traffic (LE, CS1)\n *\n *\t\tTotal 4 traffic classes.\n */\n\n\tstruct cake_sched_data *q = qdisc_priv(sch);\n\tu32 mtu = psched_mtu(qdisc_dev(sch));\n\tu64 rate = q->rate_bps;\n\tu32 quantum = 1024;\n\n\tq->tin_cnt = 4;\n\n\t/* codepoint to class mapping */\n\tq->tin_index = diffserv4;\n\tq->tin_order = bulk_order;\n\n\t/* class characteristics */\n\tcake_set_rate(&q->tins[0], rate, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\tcake_set_rate(&q->tins[1], rate >> 4, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\tcake_set_rate(&q->tins[2], rate >> 1, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\tcake_set_rate(&q->tins[3], rate >> 2, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\n\t/* bandwidth-sharing weights */\n\tq->tins[0].tin_quantum = quantum;\n\tq->tins[1].tin_quantum = quantum >> 4;\n\tq->tins[2].tin_quantum = quantum >> 1;\n\tq->tins[3].tin_quantum = quantum >> 2;\n\n\treturn 0;\n}",
        "static int scan_header(partition_t *part)\n{\n    erase_unit_header_t header;\n    loff_t offset, max_offset;\n    size_t ret;": "static int scan_header(partition_t *part)\n{\n    erase_unit_header_t header;\n    loff_t offset, max_offset;\n    size_t ret;\n    int err;\n    part->header.FormattedSize = 0;\n    max_offset = (0x100000<part->mbd.mtd->size)?0x100000:part->mbd.mtd->size;\n    /* Search first megabyte for a valid FTL header */\n    for (offset = 0;\n\t (offset + sizeof(header)) < max_offset;\n\t offset += part->mbd.mtd->erasesize ? : 0x2000) {\n\n\terr = mtd_read(part->mbd.mtd, offset, sizeof(header), &ret,\n                       (unsigned char *)&header);\n\n\tif (err)\n\t    return err;\n\n\tif (strcmp(header.DataOrgTuple+3, \"FTL100\") == 0) break;\n    }\n\n    if (offset == max_offset) {\n\tprintk(KERN_NOTICE \"ftl_cs: FTL header not found.\\n\");\n\treturn -ENOENT;\n    }\n    if (header.BlockSize != 9 ||\n\t(header.EraseUnitSize < 10) || (header.EraseUnitSize > 31) ||\n\t(header.NumTransferUnits >= le16_to_cpu(header.NumEraseUnits))) {\n\tprintk(KERN_NOTICE \"ftl_cs: FTL header corrupt!\\n\");\n\treturn -1;\n    }\n    if ((1 << header.EraseUnitSize) != part->mbd.mtd->erasesize) {\n\tprintk(KERN_NOTICE \"ftl: FTL EraseUnitSize %x != MTD erasesize %x\\n\",\n\t       1 << header.EraseUnitSize,part->mbd.mtd->erasesize);\n\treturn -1;\n    }\n    part->header = header;\n    return 0;\n}",
        "static void zram_accessed(struct zram *zram, u32 index)\n{\n\tzram_clear_flag(zram, index, ZRAM_IDLE);\n};\nstatic void zram_debugfs_register(struct zram *zram) {};": "static void zram_accessed(struct zram *zram, u32 index)\n{\n\tzram_clear_flag(zram, index, ZRAM_IDLE);\n};\nstatic void zram_debugfs_register(struct zram *zram) {};\nstatic void zram_debugfs_unregister(struct zram *zram) {};\n#endif\n\n/*\n * We switched to per-cpu streams and this attr is not needed anymore.\n * However, we will keep it around for some time, because:\n * a) we may revert per-cpu streams in the future\n * b) it's visible to user space and we need to follow our 2 years\n *    retirement rule; but we already have a number of 'soon to be\n *    altered' attrs, so max_comp_streams need to wait for the next\n *    layoff cycle.\n */\nstatic ssize_t max_comp_streams_show(struct device *dev,\n\t\tstruct device_attribute *attr, char *buf)\n{\n\treturn scnprintf(buf, PAGE_SIZE, \"%d\\n\", num_online_cpus());\n}",
        "static int dib8096p_get_best_sampling(struct dvb_frontend *fe, struct dibx090p_best_adc *adc)\n{\n\tu8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;\n\tu16 xtal = 12000;\n\tu16 fcp_min = 1900;  /* PLL, Minimum Frequency of phase comparator (KHz) */": "static int dib8096p_get_best_sampling(struct dvb_frontend *fe, struct dibx090p_best_adc *adc)\n{\n\tu8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;\n\tu16 xtal = 12000;\n\tu16 fcp_min = 1900;  /* PLL, Minimum Frequency of phase comparator (KHz) */\n\tu16 fcp_max = 20000; /* PLL, Maximum Frequency of phase comparator (KHz) */\n\tu32 fmem_max = 140000; /* 140MHz max SDRAM freq */\n\tu32 fdem_min = 66000;\n\tu32 fcp = 0, fs = 0, fdem = 0, fmem = 0;\n\tu32 harmonic_id = 0;\n\n\tadc->timf = 0;\n\tadc->pll_loopdiv = loopdiv;\n\tadc->pll_prediv = prediv;\n\n\tdeb_info(\"bandwidth = %d\", fe->dtv_property_cache.bandwidth_hz);\n\n\t/* Find Min and Max prediv */\n\twhile ((xtal / max_prediv) >= fcp_min)\n\t\tmax_prediv++;\n\n\tmax_prediv--;\n\tmin_prediv = max_prediv;\n\twhile ((xtal / min_prediv) <= fcp_max) {\n\t\tmin_prediv--;\n\t\tif (min_prediv == 1)\n\t\t\tbreak;\n\t}\n\tdeb_info(\"MIN prediv = %d : MAX prediv = %d\", min_prediv, max_prediv);\n\n\tmin_prediv = 1;\n\n\tfor (prediv = min_prediv; prediv < max_prediv; prediv++) {\n\t\tfcp = xtal / prediv;\n\t\tif (fcp > fcp_min && fcp < fcp_max) {\n\t\t\tfor (loopdiv = 1; loopdiv < 64; loopdiv++) {\n\t\t\t\tfmem = ((xtal/prediv) * loopdiv);\n\t\t\t\tfdem = fmem / 2;\n\t\t\t\tfs   = fdem / 4;\n\n\t\t\t\t/* test min/max system restrictions */\n\t\t\t\tif ((fdem >= fdem_min) && (fmem <= fmem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz / 1000)) {\n\t\t\t\t\tspur = 0;\n\t\t\t\t\t/* test fs harmonics positions */\n\t\t\t\t\tfor (harmonic_id = (fe->dtv_property_cache.frequency / (1000 * fs));  harmonic_id <= ((fe->dtv_property_cache.frequency / (1000 * fs)) + 1); harmonic_id++) {\n\t\t\t\t\t\tif (((fs * harmonic_id) >= (fe->dtv_property_cache.frequency / 1000 - (fe->dtv_property_cache.bandwidth_hz / 2000))) &&  ((fs * harmonic_id) <= (fe->dtv_property_cache.frequency / 1000 + (fe->dtv_property_cache.bandwidth_hz / 2000)))) {\n\t\t\t\t\t\t\tspur = 1;\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif (!spur) {\n\t\t\t\t\t\tadc->pll_loopdiv = loopdiv;\n\t\t\t\t\t\tadc->pll_prediv = prediv;\n\t\t\t\t\t\tadc->timf = (4260880253U / fdem) * (1 << 8);\n\t\t\t\t\t\tadc->timf += ((4260880253U % fdem) << 8) / fdem;\n\n\t\t\t\t\t\tdeb_info(\"RF %6d; BW %6d; Xtal %6d; Fmem %6d; Fdem %6d; Fs %6d; Prediv %2d; Loopdiv %2d; Timf %8d;\", fe->dtv_property_cache.frequency, fe->dtv_property_cache.bandwidth_hz, xtal, fmem, fdem, fs, prediv, loopdiv, adc->timf);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (!spur)\n\t\t\tbreak;\n\t}\n\n\tif (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)\n\t\treturn -EINVAL;\n\treturn 0;\n}",
        "static void ZSTD_copyBlockSequences(ZSTD_CCtx* zc)\n{\n    const seqStore_t* seqStore = ZSTD_getSeqStore(zc);\n    const seqDef* seqStoreSeqs = seqStore->sequencesStart;\n    size_t seqStoreSeqSize = seqStore->sequences - seqStoreSeqs;": "static void ZSTD_copyBlockSequences(ZSTD_CCtx* zc)\n{\n    const seqStore_t* seqStore = ZSTD_getSeqStore(zc);\n    const seqDef* seqStoreSeqs = seqStore->sequencesStart;\n    size_t seqStoreSeqSize = seqStore->sequences - seqStoreSeqs;\n    size_t seqStoreLiteralsSize = (size_t)(seqStore->lit - seqStore->litStart);\n    size_t literalsRead = 0;\n    size_t lastLLSize;\n\n    ZSTD_Sequence* outSeqs = &zc->seqCollector.seqStart[zc->seqCollector.seqIndex];\n    size_t i;\n    repcodes_t updatedRepcodes;\n\n    assert(zc->seqCollector.seqIndex + 1 < zc->seqCollector.maxSequences);\n    /* Ensure we have enough space for last literals \"sequence\" */\n    assert(zc->seqCollector.maxSequences >= seqStoreSeqSize + 1);\n    ZSTD_memcpy(updatedRepcodes.rep, zc->blockState.prevCBlock->rep, sizeof(repcodes_t));\n    for (i = 0; i < seqStoreSeqSize; ++i) {\n        U32 rawOffset = seqStoreSeqs[i].offset - ZSTD_REP_NUM;\n        outSeqs[i].litLength = seqStoreSeqs[i].litLength;\n        outSeqs[i].matchLength = seqStoreSeqs[i].matchLength + MINMATCH;\n        outSeqs[i].rep = 0;\n\n        if (i == seqStore->longLengthPos) {\n            if (seqStore->longLengthID == 1) {\n                outSeqs[i].litLength += 0x10000;\n            } else if (seqStore->longLengthID == 2) {\n                outSeqs[i].matchLength += 0x10000;\n            }\n        }\n\n        if (seqStoreSeqs[i].offset <= ZSTD_REP_NUM) {\n            /* Derive the correct offset corresponding to a repcode */\n            outSeqs[i].rep = seqStoreSeqs[i].offset;\n            if (outSeqs[i].litLength != 0) {\n                rawOffset = updatedRepcodes.rep[outSeqs[i].rep - 1];\n            } else {\n                if (outSeqs[i].rep == 3) {\n                    rawOffset = updatedRepcodes.rep[0] - 1;\n                } else {\n                    rawOffset = updatedRepcodes.rep[outSeqs[i].rep];\n                }\n            }\n        }\n        outSeqs[i].offset = rawOffset;\n        /* seqStoreSeqs[i].offset == offCode+1, and ZSTD_updateRep() expects offCode\n           so we provide seqStoreSeqs[i].offset - 1 */\n        updatedRepcodes = ZSTD_updateRep(updatedRepcodes.rep,\n                                         seqStoreSeqs[i].offset - 1,\n                                         seqStoreSeqs[i].litLength == 0);\n        literalsRead += outSeqs[i].litLength;\n    }\n    /* Insert last literals (if any exist) in the block as a sequence with ml == off == 0.\n     * If there are no last literals, then we'll emit (of: 0, ml: 0, ll: 0), which is a marker\n     * for the block boundary, according to the API.\n     */\n    assert(seqStoreLiteralsSize >= literalsRead);\n    lastLLSize = seqStoreLiteralsSize - literalsRead;\n    outSeqs[i].litLength = (U32)lastLLSize;\n    outSeqs[i].matchLength = outSeqs[i].offset = outSeqs[i].rep = 0;\n    seqStoreSeqSize++;\n    zc->seqCollector.seqIndex += seqStoreSeqSize;\n}",
        "static void ae7_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x18, 0);\n\tchipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);\n\tchipio_set_stream_channels(codec, 0x21, 0);": "static void ae7_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x18, 0);\n\tchipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);\n\tchipio_set_stream_channels(codec, 0x21, 0);\n\tchipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);\n\tchipio_set_control_param(codec, 0x20, 0x01);\n\n\tchipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);\n\n\tchipio_set_stream_control(codec, 0x18, 0);\n\tchipio_set_stream_control(codec, 0x0c, 0);\n\n\tca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);\n\tsnd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);\n\tca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);\n\tca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);\n\tca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);\n\tca0113_mmio_gpio_set(codec, 0, false);\n\tca0113_mmio_gpio_set(codec, 1, false);\n\tca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);\n\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);\n}",
        "static void ZSTD_ldm_gear_init(ldmRollingHashState_t* state, ldmParams_t const* params)\n{\n    unsigned maxBitsInMask = MIN(params->minMatchLength, 64);\n    unsigned hashRateLog = params->hashRateLog;\n": "static void ZSTD_ldm_gear_init(ldmRollingHashState_t* state, ldmParams_t const* params)\n{\n    unsigned maxBitsInMask = MIN(params->minMatchLength, 64);\n    unsigned hashRateLog = params->hashRateLog;\n\n    state->rolling = ~(U32)0;\n\n    /* The choice of the splitting criterion is subject to two conditions:\n     *   1. it has to trigger on average every 2^(hashRateLog) bytes;\n     *   2. ideally, it has to depend on a window of minMatchLength bytes.\n     *\n     * In the gear hash algorithm, bit n depends on the last n bytes;\n     * so in order to obtain a good quality splitting criterion it is\n     * preferable to use bits with high weight.\n     *\n     * To match condition 1 we use a mask with hashRateLog bits set\n     * and, because of the previous remark, we make sure these bits\n     * have the highest possible weight while still respecting\n     * condition 2.\n     */\n    if (hashRateLog > 0 && hashRateLog <= maxBitsInMask) {\n        state->stopMask = (((U64)1 << hashRateLog) - 1) << (maxBitsInMask - hashRateLog);\n    } else {\n        /* In this degenerate case we simply honor the hash rate. */\n        state->stopMask = ((U64)1 << hashRateLog) - 1;\n    }\n}",
        "static int build_maps(partition_t *part)\n{\n    erase_unit_header_t header;\n    uint16_t xvalid, xtrans, i;\n    unsigned blocks, j;": "static int build_maps(partition_t *part)\n{\n    erase_unit_header_t header;\n    uint16_t xvalid, xtrans, i;\n    unsigned blocks, j;\n    int hdr_ok, ret = -1;\n    ssize_t retval;\n    loff_t offset;\n\n    /* Set up erase unit maps */\n    part->DataUnits = le16_to_cpu(part->header.NumEraseUnits) -\n\tpart->header.NumTransferUnits;\n    part->EUNInfo = kmalloc_array(part->DataUnits, sizeof(struct eun_info_t),\n                                  GFP_KERNEL);\n    if (!part->EUNInfo)\n\t    goto out;\n    for (i = 0; i < part->DataUnits; i++)\n\tpart->EUNInfo[i].Offset = 0xffffffff;\n    part->XferInfo =\n\tkmalloc_array(part->header.NumTransferUnits,\n                      sizeof(struct xfer_info_t),\n                      GFP_KERNEL);\n    if (!part->XferInfo)\n\t    goto out_EUNInfo;\n\n    xvalid = xtrans = 0;\n    for (i = 0; i < le16_to_cpu(part->header.NumEraseUnits); i++) {\n\toffset = ((i + le16_to_cpu(part->header.FirstPhysicalEUN))\n\t\t      << part->header.EraseUnitSize);\n\tret = mtd_read(part->mbd.mtd, offset, sizeof(header), &retval,\n                       (unsigned char *)&header);\n\n\tif (ret)\n\t    goto out_XferInfo;\n\n\tret = -1;\n\t/* Is this a transfer partition? */\n\thdr_ok = (strcmp(header.DataOrgTuple+3, \"FTL100\") == 0);\n\tif (hdr_ok && (le16_to_cpu(header.LogicalEUN) < part->DataUnits) &&\n\t    (part->EUNInfo[le16_to_cpu(header.LogicalEUN)].Offset == 0xffffffff)) {\n\t    part->EUNInfo[le16_to_cpu(header.LogicalEUN)].Offset = offset;\n\t    part->EUNInfo[le16_to_cpu(header.LogicalEUN)].EraseCount =\n\t\tle32_to_cpu(header.EraseCount);\n\t    xvalid++;\n\t} else {\n\t    if (xtrans == part->header.NumTransferUnits) {\n\t\tprintk(KERN_NOTICE \"ftl_cs: format error: too many \"\n\t\t       \"transfer units!\\n\");\n\t\tgoto out_XferInfo;\n\t    }\n\t    if (hdr_ok && (le16_to_cpu(header.LogicalEUN) == 0xffff)) {\n\t\tpart->XferInfo[xtrans].state = XFER_PREPARED;\n\t\tpart->XferInfo[xtrans].EraseCount = le32_to_cpu(header.EraseCount);\n\t    } else {\n\t\tpart->XferInfo[xtrans].state = XFER_UNKNOWN;\n\t\t/* Pick anything reasonable for the erase count */\n\t\tpart->XferInfo[xtrans].EraseCount =\n\t\t    le32_to_cpu(part->header.EraseCount);\n\t    }\n\t    part->XferInfo[xtrans].Offset = offset;\n\t    xtrans++;\n\t}\n    }\n    /* Check for format trouble */\n    header = part->header;\n    if ((xtrans != header.NumTransferUnits) ||\n\t(xvalid+xtrans != le16_to_cpu(header.NumEraseUnits))) {\n\tprintk(KERN_NOTICE \"ftl_cs: format error: erase units \"\n\t       \"don't add up!\\n\");\n\tgoto out_XferInfo;\n    }\n\n    /* Set up virtual page map */\n    blocks = le32_to_cpu(header.FormattedSize) >> header.BlockSize;\n    part->VirtualBlockMap = vmalloc(array_size(blocks, sizeof(uint32_t)));\n    if (!part->VirtualBlockMap)\n\t    goto out_XferInfo;\n\n    memset(part->VirtualBlockMap, 0xff, blocks * sizeof(uint32_t));\n    part->BlocksPerUnit = (1 << header.EraseUnitSize) >> header.BlockSize;\n\n    part->bam_cache = kmalloc_array(part->BlocksPerUnit, sizeof(uint32_t),\n                                    GFP_KERNEL);\n    if (!part->bam_cache)\n\t    goto out_VirtualBlockMap;\n\n    part->bam_index = 0xffff;\n    part->FreeTotal = 0;\n\n    for (i = 0; i < part->DataUnits; i++) {\n\tpart->EUNInfo[i].Free = 0;\n\tpart->EUNInfo[i].Deleted = 0;\n\toffset = part->EUNInfo[i].Offset + le32_to_cpu(header.BAMOffset);\n\n\tret = mtd_read(part->mbd.mtd, offset,\n                       part->BlocksPerUnit * sizeof(uint32_t), &retval,\n                       (unsigned char *)part->bam_cache);\n\n\tif (ret)\n\t\tgoto out_bam_cache;\n\n\tfor (j = 0; j < part->BlocksPerUnit; j++) {\n\t    if (BLOCK_FREE(le32_to_cpu(part->bam_cache[j]))) {\n\t\tpart->EUNInfo[i].Free++;\n\t\tpart->FreeTotal++;\n\t    } else if ((BLOCK_TYPE(le32_to_cpu(part->bam_cache[j])) == BLOCK_DATA) &&\n\t\t     (BLOCK_NUMBER(le32_to_cpu(part->bam_cache[j])) < blocks))\n\t\tpart->VirtualBlockMap[BLOCK_NUMBER(le32_to_cpu(part->bam_cache[j]))] =\n\t\t    (i << header.EraseUnitSize) + (j << header.BlockSize);\n\t    else if (BLOCK_DELETED(le32_to_cpu(part->bam_cache[j])))\n\t\tpart->EUNInfo[i].Deleted++;\n\t}\n    }\n\n    ret = 0;\n    goto out;\n\nout_bam_cache:\n    kfree(part->bam_cache);\nout_VirtualBlockMap:\n    vfree(part->VirtualBlockMap);\nout_XferInfo:\n    kfree(part->XferInfo);\nout_EUNInfo:\n    kfree(part->EUNInfo);\nout:\n    return ret;\n} /* build_maps */\n\n/*======================================================================\n\n    Erase_xfer() schedules an asynchronous erase operation for a\n    transfer unit.\n\n======================================================================*/\n\nstatic int erase_xfer(partition_t *part,\n\t\t      uint16_t xfernum)\n{\n    int ret;\n    struct xfer_info_t *xfer;\n    struct erase_info *erase;\n\n    xfer = &part->XferInfo[xfernum];\n    pr_debug(\"ftl_cs: erasing xfer unit at 0x%x\\n\", xfer->Offset);\n    xfer->state = XFER_ERASING;\n\n    /* Is there a free erase slot? Always in MTD. */\n\n\n    erase=kmalloc(sizeof(struct erase_info), GFP_KERNEL);\n    if (!erase)\n            return -ENOMEM;\n\n    erase->addr = xfer->Offset;\n    erase->len = 1 << part->header.EraseUnitSize;\n\n    ret = mtd_erase(part->mbd.mtd, erase);\n    if (!ret) {\n\txfer->state = XFER_ERASED;\n\txfer->EraseCount++;\n    } else {\n\txfer->state = XFER_FAILED;\n\tpr_notice(\"ftl_cs: erase failed: err = %d\\n\", ret);\n    }\n\n    kfree(erase);\n\n    return ret;\n} /* erase_xfer */\n\n/*======================================================================\n\n    Prepare_xfer() takes a freshly erased transfer unit and gives\n    it an appropriate header.\n\n======================================================================*/\n\nstatic int prepare_xfer(partition_t *part, int i)\n{\n    erase_unit_header_t header;\n    struct xfer_info_t *xfer;\n    int nbam, ret;\n    uint32_t ctl;\n    ssize_t retlen;\n    loff_t offset;\n\n    xfer = &part->XferInfo[i];\n    xfer->state = XFER_FAILED;\n\n    pr_debug(\"ftl_cs: preparing xfer unit at 0x%x\\n\", xfer->Offset);\n\n    /* Write the transfer unit header */\n    header = part->header;\n    header.LogicalEUN = cpu_to_le16(0xffff);\n    header.EraseCount = cpu_to_le32(xfer->EraseCount);\n\n    ret = mtd_write(part->mbd.mtd, xfer->Offset, sizeof(header), &retlen,\n                    (u_char *)&header);\n\n    if (ret) {\n\treturn ret;\n    }\n\n    /* Write the BAM stub */\n    nbam = DIV_ROUND_UP(part->BlocksPerUnit * sizeof(uint32_t) +\n\t\t\tle32_to_cpu(part->header.BAMOffset), SECTOR_SIZE);\n\n    offset = xfer->Offset + le32_to_cpu(part->header.BAMOffset);\n    ctl = cpu_to_le32(BLOCK_CONTROL);\n\n    for (i = 0; i < nbam; i++, offset += sizeof(uint32_t)) {\n\n\tret = mtd_write(part->mbd.mtd, offset, sizeof(uint32_t), &retlen,\n                        (u_char *)&ctl);\n\n\tif (ret)\n\t    return ret;\n    }\n    xfer->state = XFER_PREPARED;\n    return 0;\n\n} /* prepare_xfer */\n\n/*======================================================================\n\n    Copy_erase_unit() takes a full erase block and a transfer unit,\n    copies everything to the transfer unit, then swaps the block\n    pointers.\n\n    All data blocks are copied to the corresponding blocks in the\n    target unit, so the virtual block map does not need to be\n    updated.\n\n======================================================================*/\n\nstatic int copy_erase_unit(partition_t *part, uint16_t srcunit,\n\t\t\t   uint16_t xferunit)\n{\n    u_char buf[SECTOR_SIZE];\n    struct eun_info_t *eun;\n    struct xfer_info_t *xfer;\n    uint32_t src, dest, free, i;\n    uint16_t unit;\n    int ret;\n    ssize_t retlen;\n    loff_t offset;\n    uint16_t srcunitswap = cpu_to_le16(srcunit);\n\n    eun = &part->EUNInfo[srcunit];\n    xfer = &part->XferInfo[xferunit];\n    pr_debug(\"ftl_cs: copying block 0x%x to 0x%x\\n\",\n\t  eun->Offset, xfer->Offset);\n\n\n    /* Read current BAM */\n    if (part->bam_index != srcunit) {\n\n\toffset = eun->Offset + le32_to_cpu(part->header.BAMOffset);\n\n\tret = mtd_read(part->mbd.mtd, offset,\n                       part->BlocksPerUnit * sizeof(uint32_t), &retlen,\n                       (u_char *)(part->bam_cache));\n\n\t/* mark the cache bad, in case we get an error later */\n\tpart->bam_index = 0xffff;\n\n\tif (ret) {\n\t    printk( KERN_WARNING \"ftl: Failed to read BAM cache in copy_erase_unit()!\\n\");\n\t    return ret;\n\t}\n    }\n\n    /* Write the LogicalEUN for the transfer unit */\n    xfer->state = XFER_UNKNOWN;\n    offset = xfer->Offset + 20; /* Bad! */\n    unit = cpu_to_le16(0x7fff);\n\n    ret = mtd_write(part->mbd.mtd, offset, sizeof(uint16_t), &retlen,\n                    (u_char *)&unit);\n\n    if (ret) {\n\tprintk( KERN_WARNING \"ftl: Failed to write back to BAM cache in copy_erase_unit()!\\n\");\n\treturn ret;\n    }\n\n    /* Copy all data blocks from source unit to transfer unit */\n    src = eun->Offset; dest = xfer->Offset;\n\n    free = 0;\n    ret = 0;\n    for (i = 0; i < part->BlocksPerUnit; i++) {\n\tswitch (BLOCK_TYPE(le32_to_cpu(part->bam_cache[i]))) {\n\tcase BLOCK_CONTROL:\n\t    /* This gets updated later */\n\t    break;\n\tcase BLOCK_DATA:\n\tcase BLOCK_REPLACEMENT:\n\t    ret = mtd_read(part->mbd.mtd, src, SECTOR_SIZE, &retlen,\n                           (u_char *)buf);\n\t    if (ret) {\n\t\tprintk(KERN_WARNING \"ftl: Error reading old xfer unit in copy_erase_unit\\n\");\n\t\treturn ret;\n            }\n\n\n\t    ret = mtd_write(part->mbd.mtd, dest, SECTOR_SIZE, &retlen,\n                            (u_char *)buf);\n\t    if (ret)  {\n\t\tprintk(KERN_WARNING \"ftl: Error writing new xfer unit in copy_erase_unit\\n\");\n\t\treturn ret;\n            }\n\n\t    break;\n\tdefault:\n\t    /* All other blocks must be free */\n\t    part->bam_cache[i] = cpu_to_le32(0xffffffff);\n\t    free++;\n\t    break;\n\t}\n\tsrc += SECTOR_SIZE;\n\tdest += SECTOR_SIZE;\n    }\n\n    /* Write the BAM to the transfer unit */\n    ret = mtd_write(part->mbd.mtd,\n                    xfer->Offset + le32_to_cpu(part->header.BAMOffset),\n                    part->BlocksPerUnit * sizeof(int32_t),\n                    &retlen,\n                    (u_char *)part->bam_cache);\n    if (ret) {\n\tprintk( KERN_WARNING \"ftl: Error writing BAM in copy_erase_unit\\n\");\n\treturn ret;\n    }\n\n\n    /* All clear? Then update the LogicalEUN again */\n    ret = mtd_write(part->mbd.mtd, xfer->Offset + 20, sizeof(uint16_t),\n                    &retlen, (u_char *)&srcunitswap);\n\n    if (ret) {\n\tprintk(KERN_WARNING \"ftl: Error writing new LogicalEUN in copy_erase_unit\\n\");\n\treturn ret;\n    }\n\n\n    /* Update the maps and usage stats*/\n    swap(xfer->EraseCount, eun->EraseCount);\n    swap(xfer->Offset, eun->Offset);\n    part->FreeTotal -= eun->Free;\n    part->FreeTotal += free;\n    eun->Free = free;\n    eun->Deleted = 0;\n\n    /* Now, the cache should be valid for the new block */\n    part->bam_index = srcunit;\n\n    return 0;\n} /* copy_erase_unit */\n\n/*======================================================================\n\n    reclaim_block() picks a full erase unit and a transfer unit and\n    then calls copy_erase_unit() to copy one to the other.  Then, it\n    schedules an erase on the expired block.\n\n    What's a good way to decide which transfer unit and which erase\n    unit to use?  Beats me.  My way is to always pick the transfer\n    unit with the fewest erases, and usually pick the data unit with\n    the most deleted blocks.  But with a small probability, pick the\n    oldest data unit instead.  This means that we generally postpone\n    the next reclamation as long as possible, but shuffle static\n    stuff around a bit for wear leveling.\n\n======================================================================*/\n\nstatic int reclaim_block(partition_t *part)\n{\n    uint16_t i, eun, xfer;\n    uint32_t best;\n    int queued, ret;\n\n    pr_debug(\"ftl_cs: reclaiming space...\\n\");\n    pr_debug(\"NumTransferUnits == %x\\n\", part->header.NumTransferUnits);\n    /* Pick the least erased transfer unit */\n    best = 0xffffffff; xfer = 0xffff;\n    do {\n\tqueued = 0;\n\tfor (i = 0; i < part->header.NumTransferUnits; i++) {\n\t    int n=0;\n\t    if (part->XferInfo[i].state == XFER_UNKNOWN) {\n\t\tpr_debug(\"XferInfo[%d].state == XFER_UNKNOWN\\n\",i);\n\t\tn=1;\n\t\terase_xfer(part, i);\n\t    }\n\t    if (part->XferInfo[i].state == XFER_ERASING) {\n\t\tpr_debug(\"XferInfo[%d].state == XFER_ERASING\\n\",i);\n\t\tn=1;\n\t\tqueued = 1;\n\t    }\n\t    else if (part->XferInfo[i].state == XFER_ERASED) {\n\t\tpr_debug(\"XferInfo[%d].state == XFER_ERASED\\n\",i);\n\t\tn=1;\n\t\tprepare_xfer(part, i);\n\t    }\n\t    if (part->XferInfo[i].state == XFER_PREPARED) {\n\t\tpr_debug(\"XferInfo[%d].state == XFER_PREPARED\\n\",i);\n\t\tn=1;\n\t\tif (part->XferInfo[i].EraseCount <= best) {\n\t\t    best = part->XferInfo[i].EraseCount;\n\t\t    xfer = i;\n\t\t}\n\t    }\n\t\tif (!n)\n\t\t    pr_debug(\"XferInfo[%d].state == %x\\n\",i, part->XferInfo[i].state);\n\n\t}\n\tif (xfer == 0xffff) {\n\t    if (queued) {\n\t\tpr_debug(\"ftl_cs: waiting for transfer \"\n\t\t      \"unit to be prepared...\\n\");\n\t\tmtd_sync(part->mbd.mtd);\n\t    } else {\n\t\tstatic int ne = 0;\n\t\tif (++ne < 5)\n\t\t    printk(KERN_NOTICE \"ftl_cs: reclaim failed: no \"\n\t\t\t   \"suitable transfer units!\\n\");\n\t\telse\n\t\t    pr_debug(\"ftl_cs: reclaim failed: no \"\n\t\t\t  \"suitable transfer units!\\n\");\n\n\t\treturn -EIO;\n\t    }\n\t}\n    } while (xfer == 0xffff);\n\n    eun = 0;\n    if ((jiffies % shuffle_freq) == 0) {\n\tpr_debug(\"ftl_cs: recycling freshest block...\\n\");\n\tbest = 0xffffffff;\n\tfor (i = 0; i < part->DataUnits; i++)\n\t    if (part->EUNInfo[i].EraseCount <= best) {\n\t\tbest = part->EUNInfo[i].EraseCount;\n\t\teun = i;\n\t    }\n    } else {\n\tbest = 0;\n\tfor (i = 0; i < part->DataUnits; i++)\n\t    if (part->EUNInfo[i].Deleted >= best) {\n\t\tbest = part->EUNInfo[i].Deleted;\n\t\teun = i;\n\t    }\n\tif (best == 0) {\n\t    static int ne = 0;\n\t    if (++ne < 5)\n\t\tprintk(KERN_NOTICE \"ftl_cs: reclaim failed: \"\n\t\t       \"no free blocks!\\n\");\n\t    else\n\t\tpr_debug(\"ftl_cs: reclaim failed: \"\n\t\t       \"no free blocks!\\n\");\n\n\t    return -EIO;\n\t}\n    }\n    ret = copy_erase_unit(part, eun, xfer);\n    if (!ret)\n\terase_xfer(part, xfer);\n    else\n\tprintk(KERN_NOTICE \"ftl_cs: copy_erase_unit failed!\\n\");\n    return ret;\n} /* reclaim_block */\n\n/*======================================================================\n\n    Find_free() searches for a free block.  If necessary, it updates\n    the BAM cache for the erase unit containing the free block.  It\n    returns the block index -- the erase unit is just the currently\n    cached unit.  If there are no free blocks, it returns 0 -- this\n    is never a valid data block because it contains the header.\n\n======================================================================*/\n\n#ifdef PSYCHO_DEBUG\nstatic void dump_lists(partition_t *part)\n{\n    int i;\n    printk(KERN_DEBUG \"ftl_cs: Free total = %d\\n\", part->FreeTotal);\n    for (i = 0; i < part->DataUnits; i++)\n\tprintk(KERN_DEBUG \"ftl_cs:   unit %d: %d phys, %d free, \"\n\t       \"%d deleted\\n\", i,\n\t       part->EUNInfo[i].Offset >> part->header.EraseUnitSize,\n\t       part->EUNInfo[i].Free, part->EUNInfo[i].Deleted);\n}",
        "static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);": "static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);\n\n\tsnd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);\n\tca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);\n\n\tchipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);\n\n\tchipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);\n\tchipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);\n\n\tchipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);\n\tchipio_set_stream_channels(codec, 0x18, 6);\n\tchipio_set_stream_control(codec, 0x18, 1);\n\n\tchipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);\n\n\tmutex_unlock(&spec->chipio_mutex);\n}",
        "static void alc_headset_mode_unplugged(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x1b, 0x0c0b), /* LDO and MISC control */": "static void alc_headset_mode_unplugged(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x1b, 0x0c0b), /* LDO and MISC control */\n\t\tWRITE_COEF(0x45, 0xd089), /* UAJ function set to menual mode */\n\t\tUPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/\n\t\tWRITE_COEF(0x06, 0x6104), /* Set MIC2 Vref gate with HP */\n\t\tWRITE_COEFEX(0x57, 0x03, 0x8aa6), /* Direct Drive HP Amp control */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0256[] = {\n\t\tWRITE_COEF(0x1b, 0x0c4b), /* LDO and MISC control */\n\t\tWRITE_COEF(0x45, 0xd089), /* UAJ function set to menual mode */\n\t\tWRITE_COEF(0x06, 0x6104), /* Set MIC2 Vref gate with HP */\n\t\tWRITE_COEFEX(0x57, 0x03, 0x09a3), /* Direct Drive HP Amp control */\n\t\tUPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0233[] = {\n\t\tWRITE_COEF(0x1b, 0x0c0b),\n\t\tWRITE_COEF(0x45, 0xc429),\n\t\tUPDATE_COEF(0x35, 0x4000, 0),\n\t\tWRITE_COEF(0x06, 0x2104),\n\t\tWRITE_COEF(0x1a, 0x0001),\n\t\tWRITE_COEF(0x26, 0x0004),\n\t\tWRITE_COEF(0x32, 0x42a3),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0288[] = {\n\t\tUPDATE_COEF(0x4f, 0xfcc0, 0xc400),\n\t\tUPDATE_COEF(0x50, 0x2000, 0x2000),\n\t\tUPDATE_COEF(0x56, 0x0006, 0x0006),\n\t\tUPDATE_COEF(0x66, 0x0008, 0),\n\t\tUPDATE_COEF(0x67, 0x2000, 0),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0298[] = {\n\t\tUPDATE_COEF(0x19, 0x1300, 0x0300),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0292[] = {\n\t\tWRITE_COEF(0x76, 0x000e),\n\t\tWRITE_COEF(0x6c, 0x2400),\n\t\tWRITE_COEF(0x18, 0x7308),\n\t\tWRITE_COEF(0x6b, 0xc429),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0293[] = {\n\t\tUPDATE_COEF(0x10, 7<<8, 6<<8), /* SET Line1 JD to 0 */\n\t\tUPDATE_COEFEX(0x57, 0x05, 1<<15|1<<13, 0x0), /* SET charge pump by verb */\n\t\tUPDATE_COEFEX(0x57, 0x03, 1<<10, 1<<10), /* SET EN_OSW to 1 */\n\t\tUPDATE_COEF(0x1a, 1<<3, 1<<3), /* Combo JD gating with LINE1-VREFO */\n\t\tWRITE_COEF(0x45, 0xc429), /* Set to TRS type */\n\t\tUPDATE_COEF(0x4a, 0x000f, 0x000e), /* Combo Jack auto detect */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0668[] = {\n\t\tWRITE_COEF(0x15, 0x0d40),\n\t\tWRITE_COEF(0xb7, 0x802b),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0225[] = {\n\t\tUPDATE_COEF(0x63, 3<<14, 0),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0274[] = {\n\t\tUPDATE_COEF(0x4a, 0x0100, 0),\n\t\tUPDATE_COEFEX(0x57, 0x05, 0x4000, 0),\n\t\tUPDATE_COEF(0x6b, 0xf000, 0x5000),\n\t\tUPDATE_COEF(0x4a, 0x0010, 0),\n\t\tUPDATE_COEF(0x4a, 0x0c00, 0x0c00),\n\t\tWRITE_COEF(0x45, 0x5289),\n\t\tUPDATE_COEF(0x4a, 0x0c00, 0),\n\t\t{}\n\t};\n\n\tif (spec->no_internal_mic_pin) {\n\t\talc_update_coef_idx(codec, 0x45, 0xf<<12 | 1<<10, 5<<12);\n\t\treturn;\n\t}\n\n\tswitch (codec->core.vendor_id) {\n\tcase 0x10ec0255:\n\t\talc_process_coef_fw(codec, coef0255);\n\t\tbreak;\n\tcase 0x10ec0230:\n\tcase 0x10ec0236:\n\tcase 0x10ec0256:\n\t\talc_process_coef_fw(codec, coef0256);\n\t\tbreak;\n\tcase 0x10ec0234:\n\tcase 0x10ec0274:\n\tcase 0x10ec0294:\n\t\talc_process_coef_fw(codec, coef0274);\n\t\tbreak;\n\tcase 0x10ec0233:\n\tcase 0x10ec0283:\n\t\talc_process_coef_fw(codec, coef0233);\n\t\tbreak;\n\tcase 0x10ec0286:\n\tcase 0x10ec0288:\n\t\talc_process_coef_fw(codec, coef0288);\n\t\tbreak;\n\tcase 0x10ec0298:\n\t\talc_process_coef_fw(codec, coef0298);\n\t\talc_process_coef_fw(codec, coef0288);\n\t\tbreak;\n\tcase 0x10ec0292:\n\t\talc_process_coef_fw(codec, coef0292);\n\t\tbreak;\n\tcase 0x10ec0293:\n\t\talc_process_coef_fw(codec, coef0293);\n\t\tbreak;\n\tcase 0x10ec0668:\n\t\talc_process_coef_fw(codec, coef0668);\n\t\tbreak;\n\tcase 0x10ec0215:\n\tcase 0x10ec0225:\n\tcase 0x10ec0285:\n\tcase 0x10ec0295:\n\tcase 0x10ec0289:\n\tcase 0x10ec0299:\n\t\talc_process_coef_fw(codec, alc225_pre_hsmode);\n\t\talc_process_coef_fw(codec, coef0225);\n\t\tbreak;\n\tcase 0x10ec0867:\n\t\talc_update_coefex_idx(codec, 0x57, 0x5, 1<<14, 0);\n\t\tbreak;\n\t}\n\tcodec_dbg(codec, \"Headset jack set to unplugged mode.\\n\");\n}",
        "static int HUF_buildTree(nodeElt* huffNode, U32 maxSymbolValue)\n{\n    nodeElt* const huffNode0 = huffNode - 1;\n    int nonNullRank;\n    int lowS, lowN;": "static int HUF_buildTree(nodeElt* huffNode, U32 maxSymbolValue)\n{\n    nodeElt* const huffNode0 = huffNode - 1;\n    int nonNullRank;\n    int lowS, lowN;\n    int nodeNb = STARTNODE;\n    int n, nodeRoot;\n    /* init for parents */\n    nonNullRank = (int)maxSymbolValue;\n    while(huffNode[nonNullRank].count == 0) nonNullRank--;\n    lowS = nonNullRank; nodeRoot = nodeNb + lowS - 1; lowN = nodeNb;\n    huffNode[nodeNb].count = huffNode[lowS].count + huffNode[lowS-1].count;\n    huffNode[lowS].parent = huffNode[lowS-1].parent = (U16)nodeNb;\n    nodeNb++; lowS-=2;\n    for (n=nodeNb; n<=nodeRoot; n++) huffNode[n].count = (U32)(1U<<30);\n    huffNode0[0].count = (U32)(1U<<31);  /* fake entry, strong barrier */\n\n    /* create parents */\n    while (nodeNb <= nodeRoot) {\n        int const n1 = (huffNode[lowS].count < huffNode[lowN].count) ? lowS-- : lowN++;\n        int const n2 = (huffNode[lowS].count < huffNode[lowN].count) ? lowS-- : lowN++;\n        huffNode[nodeNb].count = huffNode[n1].count + huffNode[n2].count;\n        huffNode[n1].parent = huffNode[n2].parent = (U16)nodeNb;\n        nodeNb++;\n    }\n\n    /* distribute weights (unlimited tree height) */\n    huffNode[nodeRoot].nbBits = 0;\n    for (n=nodeRoot-1; n>=STARTNODE; n--)\n        huffNode[n].nbBits = huffNode[ huffNode[n].parent ].nbBits + 1;\n    for (n=0; n<=nonNullRank; n++)\n        huffNode[n].nbBits = huffNode[ huffNode[n].parent ].nbBits + 1;\n\n    return nonNullRank;\n}",
        "static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc)\n{\n\t/* state variables */\n\tstatic bool fsp_for_next_freq;\n\t/* constant configuration parameters */": "static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc)\n{\n\t/* state variables */\n\tstatic bool fsp_for_next_freq;\n\t/* constant configuration parameters */\n\tconst bool save_restore_clkstop_pd = true;\n\tconst u32 zqcal_before_cc_cutoff = 2400;\n\tconst bool cya_allow_ref_cc = false;\n\tconst bool cya_issue_pc_ref = false;\n\tconst bool opt_cc_short_zcal = true;\n\tconst bool ref_b4_sref_en = false;\n\tconst u32 tZQCAL_lpddr4 = 1000000;\n\tconst bool opt_short_zcal = true;\n\tconst bool opt_do_sw_qrst = true;\n\tconst u32 opt_dvfs_mode = MAN_SR;\n\t/*\n\t * This is the timing table for the source frequency. It does _not_\n\t * necessarily correspond to the actual timing values in the EMC at the\n\t * moment. If the boot BCT differs from the table then this can happen.\n\t * However, we need it for accessing the dram_timings (which are not\n\t * really registers) array for the current frequency.\n\t */\n\tstruct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next;\n\tu32 tRTM, RP_war, R2P_war, TRPab_war, deltaTWATM, W2P_war, tRPST;\n\tu32 mr13_flip_fspwr, mr13_flip_fspop, ramp_up_wait, ramp_down_wait;\n\tu32 zq_wait_long, zq_latch_dvfs_wait_time, tZQCAL_lpddr4_fc_adj;\n\tu32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl;\n\tu32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4];\n\tu32 bg_reg_mode_change, enable_bglp_reg, enable_bg_reg;\n\tbool opt_zcal_en_cc = false, is_lpddr3 = false;\n\tbool compensate_trimmer_applicable = false;\n\tu32 emc_dbg, emc_cfg_pipe_clk, emc_pin;\n\tu32 src_clk_period, dst_clk_period; /* in picoseconds */\n\tbool shared_zq_resistor = false;\n\tu32 value, dram_type;\n\tu32 opt_dll_mode = 0;\n\tunsigned long delay;\n\tunsigned int i;\n\n\temc_dbg(emc, INFO, \"Running clock change.\\n\");\n\n\t/* XXX fake == last */\n\tfake = tegra210_emc_find_timing(emc, last->rate * 1000UL);\n\tfsp_for_next_freq = !fsp_for_next_freq;\n\n\tvalue = emc_readl(emc, EMC_FBIO_CFG5) & EMC_FBIO_CFG5_DRAM_TYPE_MASK;\n\tdram_type = value >> EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;\n\n\tif (last->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX] & BIT(31))\n\t\tshared_zq_resistor = true;\n\n\tif ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 &&\n\t     last->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0) ||\n\t    dram_type == DRAM_TYPE_LPDDR4)\n\t\topt_zcal_en_cc = true;\n\n\tif (dram_type == DRAM_TYPE_DDR3)\n\t\topt_dll_mode = tegra210_emc_get_dll_state(next);\n\n\tif ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) &&\n\t    (dram_type == DRAM_TYPE_LPDDR2))\n\t\tis_lpddr3 = true;\n\n\temc_readl(emc, EMC_CFG);\n\temc_readl(emc, EMC_AUTO_CAL_CONFIG);\n\n\tsrc_clk_period = 1000000000 / last->rate;\n\tdst_clk_period = 1000000000 / next->rate;\n\n\tif (dst_clk_period <= zqcal_before_cc_cutoff)\n\t\ttZQCAL_lpddr4_fc_adj = tZQCAL_lpddr4 - tFC_lpddr4;\n\telse\n\t\ttZQCAL_lpddr4_fc_adj = tZQCAL_lpddr4;\n\n\ttZQCAL_lpddr4_fc_adj /= dst_clk_period;\n\n\temc_dbg = emc_readl(emc, EMC_DBG);\n\temc_pin = emc_readl(emc, EMC_PIN);\n\temc_cfg_pipe_clk = emc_readl(emc, EMC_CFG_PIPE_CLK);\n\n\temc_cfg = next->burst_regs[EMC_CFG_INDEX];\n\temc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD |\n\t\t     EMC_CFG_DRAM_CLKSTOP_SR | EMC_CFG_DRAM_CLKSTOP_PD);\n\temc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl;\n\temc_sel_dpd_ctrl &= ~(EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN |\n\t\t\t      EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN |\n\t\t\t      EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN |\n\t\t\t      EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN |\n\t\t\t      EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN);\n\n\temc_dbg(emc, INFO, \"Clock change version: %d\\n\",\n\t\tDVFS_CLOCK_CHANGE_VERSION);\n\temc_dbg(emc, INFO, \"DRAM type = %d\\n\", dram_type);\n\temc_dbg(emc, INFO, \"DRAM dev #: %u\\n\", emc->num_devices);\n\temc_dbg(emc, INFO, \"Next EMC clksrc: 0x%08x\\n\", clksrc);\n\temc_dbg(emc, INFO, \"DLL clksrc:      0x%08x\\n\", next->dll_clk_src);\n\temc_dbg(emc, INFO, \"last rate: %u, next rate %u\\n\", last->rate,\n\t\tnext->rate);\n\temc_dbg(emc, INFO, \"last period: %u, next period: %u\\n\",\n\t\tsrc_clk_period, dst_clk_period);\n\temc_dbg(emc, INFO, \"  shared_zq_resistor: %d\\n\", !!shared_zq_resistor);\n\temc_dbg(emc, INFO, \"  num_channels: %u\\n\", emc->num_channels);\n\temc_dbg(emc, INFO, \"  opt_dll_mode: %d\\n\", opt_dll_mode);\n\n\t/*\n\t * Step 1:\n\t *   Pre DVFS SW sequence.\n\t */\n\temc_dbg(emc, STEPS, \"Step 1\\n\");\n\temc_dbg(emc, STEPS, \"Step 1.1: Disable DLL temporarily.\\n\");\n\n\tvalue = emc_readl(emc, EMC_CFG_DIG_DLL);\n\tvalue &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;\n\temc_writel(emc, value, EMC_CFG_DIG_DLL);\n\n\ttegra210_emc_timing_update(emc);\n\n\tfor (i = 0; i < emc->num_channels; i++)\n\t\ttegra210_emc_wait_for_update(emc, i, EMC_CFG_DIG_DLL,\n\t\t\t\t\t     EMC_CFG_DIG_DLL_CFG_DLL_EN, 0);\n\n\temc_dbg(emc, STEPS, \"Step 1.2: Disable AUTOCAL temporarily.\\n\");\n\n\temc_auto_cal_config = next->emc_auto_cal_config;\n\tauto_cal_en = emc_auto_cal_config & EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;\n\temc_auto_cal_config &= ~EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;\n\temc_auto_cal_config |= EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL;\n\temc_auto_cal_config |= EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL;\n\temc_auto_cal_config |= auto_cal_en;\n\temc_writel(emc, emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);\n\temc_readl(emc, EMC_AUTO_CAL_CONFIG); /* Flush write. */\n\n\temc_dbg(emc, STEPS, \"Step 1.3: Disable other power features.\\n\");\n\n\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\temc_writel(emc, emc_cfg, EMC_CFG);\n\temc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);\n\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\n\tif (next->periodic_training) {\n\t\ttegra210_emc_reset_dram_clktree_values(next);\n\n\t\tfor (i = 0; i < emc->num_channels; i++)\n\t\t\ttegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,\n\t\t\t\t\t\t     EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK,\n\t\t\t\t\t\t     0);\n\n\t\tfor (i = 0; i < emc->num_channels; i++)\n\t\t\ttegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,\n\t\t\t\t\t\t     EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK,\n\t\t\t\t\t\t     0);\n\n\t\ttegra210_emc_start_periodic_compensation(emc);\n\n\t\tdelay = 1000 * tegra210_emc_actual_osc_clocks(last->run_clocks);\n\t\tudelay((delay / last->rate) + 2);\n\n\t\tvalue = periodic_compensation_handler(emc, DVFS_SEQUENCE, fake,\n\t\t\t\t\t\t      next);\n\t\tvalue = (value * 128 * next->rate / 1000) / 1000000;\n\n\t\tif (next->periodic_training && value > next->tree_margin)\n\t\t\tcompensate_trimmer_applicable = true;\n\t}\n\n\temc_writel(emc, EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS);\n\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\temc_writel(emc, emc_cfg, EMC_CFG);\n\temc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);\n\temc_writel(emc, emc_cfg_pipe_clk | EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON,\n\t\t   EMC_CFG_PIPE_CLK);\n\temc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp &\n\t\t\t~EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE,\n\t\t   EMC_FDPD_CTRL_CMD_NO_RAMP);\n\n\tbg_reg_mode_change =\n\t\t((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t  EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD) ^\n\t\t (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t  EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD)) ||\n\t\t((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t  EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD) ^\n\t\t (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t  EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD));\n\tenable_bglp_reg =\n\t\t(next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD) == 0;\n\tenable_bg_reg =\n\t\t(next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD) == 0;\n\n\tif (bg_reg_mode_change) {\n\t\tif (enable_bg_reg)\n\t\t\temc_writel(emc, last->burst_regs\n\t\t\t\t   [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t\t\t   ~EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD,\n\t\t\t\t   EMC_PMACRO_BG_BIAS_CTRL_0);\n\n\t\tif (enable_bglp_reg)\n\t\t\temc_writel(emc, last->burst_regs\n\t\t\t\t   [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t\t\t   ~EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD,\n\t\t\t\t   EMC_PMACRO_BG_BIAS_CTRL_0);\n\t}\n\n\t/* Check if we need to turn on VREF generator. */\n\tif ((((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &\n\t       EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF) == 0) &&\n\t     ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &\n\t       EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF) == 1)) ||\n\t    (((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &\n\t       EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) == 0) &&\n\t     ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &\n\t       EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) != 0))) {\n\t\tu32 pad_tx_ctrl =\n\t\t    next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];\n\t\tu32 last_pad_tx_ctrl =\n\t\t    last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];\n\t\tu32 next_dq_e_ivref, next_dqs_e_ivref;\n\n\t\tnext_dqs_e_ivref = pad_tx_ctrl &\n\t\t\t\t   EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF;\n\t\tnext_dq_e_ivref = pad_tx_ctrl &\n\t\t\t\t  EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF;\n\t\tvalue = (last_pad_tx_ctrl &\n\t\t\t\t~EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF &\n\t\t\t\t~EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) |\n\t\t\tnext_dq_e_ivref | next_dqs_e_ivref;\n\t\temc_writel(emc, value, EMC_PMACRO_DATA_PAD_TX_CTRL);\n\t\tudelay(1);\n\t} else if (bg_reg_mode_change) {\n\t\tudelay(1);\n\t}\n\n\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\n\t/*\n\t * Step 2:\n\t *   Prelock the DLL.\n\t */\n\temc_dbg(emc, STEPS, \"Step 2\\n\");\n\n\tif (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] &\n\t    EMC_CFG_DIG_DLL_CFG_DLL_EN) {\n\t\temc_dbg(emc, INFO, \"Prelock enabled for target frequency.\\n\");\n\t\tvalue = tegra210_emc_dll_prelock(emc, clksrc);\n\t\temc_dbg(emc, INFO, \"DLL out: 0x%03x\\n\", value);\n\t} else {\n\t\temc_dbg(emc, INFO, \"Disabling DLL for target frequency.\\n\");\n\t\ttegra210_emc_dll_disable(emc);\n\t}\n\n\t/*\n\t * Step 3:\n\t *   Prepare autocal for the clock change.\n\t */\n\temc_dbg(emc, STEPS, \"Step 3\\n\");\n\n\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\temc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2);\n\temc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3);\n\temc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4);\n\temc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5);\n\temc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6);\n\temc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7);\n\temc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8);\n\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\n\temc_auto_cal_config |= (EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START |\n\t\t\t\tauto_cal_en);\n\temc_writel(emc, emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);\n\n\t/*\n\t * Step 4:\n\t *   Update EMC_CFG. (??)\n\t */\n\temc_dbg(emc, STEPS, \"Step 4\\n\");\n\n\tif (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4)\n\t\tccfifo_writel(emc, 1, EMC_SELF_REF, 0);\n\telse\n\t\temc_writel(emc, next->emc_cfg_2, EMC_CFG_2);\n\n\t/*\n\t * Step 5:\n\t *   Prepare reference variables for ZQCAL regs.\n\t */\n\temc_dbg(emc, STEPS, \"Step 5\\n\");\n\n\tif (dram_type == DRAM_TYPE_LPDDR4)\n\t\tzq_wait_long = max((u32)1, div_o3(1000000, dst_clk_period));\n\telse if (dram_type == DRAM_TYPE_LPDDR2 || is_lpddr3)\n\t\tzq_wait_long = max(next->min_mrs_wait,\n\t\t\t\t   div_o3(360000, dst_clk_period)) + 4;\n\telse if (dram_type == DRAM_TYPE_DDR3)\n\t\tzq_wait_long = max((u32)256,\n\t\t\t\t   div_o3(320000, dst_clk_period) + 2);\n\telse\n\t\tzq_wait_long = 0;\n\n\t/*\n\t * Step 6:\n\t *   Training code - removed.\n\t */\n\temc_dbg(emc, STEPS, \"Step 6\\n\");\n\n\t/*\n\t * Step 7:\n\t *   Program FSP reference registers and send MRWs to new FSPWR.\n\t */\n\temc_dbg(emc, STEPS, \"Step 7\\n\");\n\temc_dbg(emc, SUB_STEPS, \"Step 7.1: Bug 200024907 - Patch RP R2P\");\n\n\t/* WAR 200024907 */\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\tu32 nRTP = 16;\n\n\t\tif (src_clk_period >= 1000000 / 1866) /* 535.91 ps */\n\t\t\tnRTP = 14;\n\n\t\tif (src_clk_period >= 1000000 / 1600) /* 625.00 ps */\n\t\t\tnRTP = 12;\n\n\t\tif (src_clk_period >= 1000000 / 1333) /* 750.19 ps */\n\t\t\tnRTP = 10;\n\n\t\tif (src_clk_period >= 1000000 / 1066) /* 938.09 ps */\n\t\t\tnRTP = 8;\n\n\t\tdeltaTWATM = max_t(u32, div_o3(7500, src_clk_period), 8);\n\n\t\t/*\n\t\t * Originally there was a + .5 in the tRPST calculation.\n\t\t * However since we can't do FP in the kernel and the tRTM\n\t\t * computation was in a floating point ceiling function, adding\n\t\t * one to tRTP should be ok. There is no other source of non\n\t\t * integer values, so the result was always going to be\n\t\t * something for the form: f_ceil(N + .5) = N + 1;\n\t\t */\n\t\ttRPST = (last->emc_mrw & 0x80) >> 7;\n\t\ttRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) +\n\t\t\tmax_t(u32, div_o3(7500, src_clk_period), 8) + tRPST +\n\t\t\t1 + nRTP;\n\n\t\temc_dbg(emc, INFO, \"tRTM = %u, EMC_RP = %u\\n\", tRTM,\n\t\t\tnext->burst_regs[EMC_RP_INDEX]);\n\n\t\tif (last->burst_regs[EMC_RP_INDEX] < tRTM) {\n\t\t\tif (tRTM > (last->burst_regs[EMC_R2P_INDEX] +\n\t\t\t\t    last->burst_regs[EMC_RP_INDEX])) {\n\t\t\t\tR2P_war = tRTM - last->burst_regs[EMC_RP_INDEX];\n\t\t\t\tRP_war = last->burst_regs[EMC_RP_INDEX];\n\t\t\t\tTRPab_war = last->burst_regs[EMC_TRPAB_INDEX];\n\n\t\t\t\tif (R2P_war > 63) {\n\t\t\t\t\tRP_war = R2P_war +\n\t\t\t\t\t\t last->burst_regs[EMC_RP_INDEX] - 63;\n\n\t\t\t\t\tif (TRPab_war < RP_war)\n\t\t\t\t\t\tTRPab_war = RP_war;\n\n\t\t\t\t\tR2P_war = 63;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tR2P_war = last->burst_regs[EMC_R2P_INDEX];\n\t\t\t\tRP_war = last->burst_regs[EMC_RP_INDEX];\n\t\t\t\tTRPab_war = last->burst_regs[EMC_TRPAB_INDEX];\n\t\t\t}\n\n\t\t\tif (RP_war < deltaTWATM) {\n\t\t\t\tW2P_war = last->burst_regs[EMC_W2P_INDEX]\n\t\t\t\t\t  + deltaTWATM - RP_war;\n\t\t\t\tif (W2P_war > 63) {\n\t\t\t\t\tRP_war = RP_war + W2P_war - 63;\n\t\t\t\t\tif (TRPab_war < RP_war)\n\t\t\t\t\t\tTRPab_war = RP_war;\n\t\t\t\t\tW2P_war = 63;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tW2P_war = last->burst_regs[\n\t\t\t\t\t  EMC_W2P_INDEX];\n\t\t\t}\n\n\t\t\tif ((last->burst_regs[EMC_W2P_INDEX] ^ W2P_war) ||\n\t\t\t    (last->burst_regs[EMC_R2P_INDEX] ^ R2P_war) ||\n\t\t\t    (last->burst_regs[EMC_RP_INDEX] ^ RP_war) ||\n\t\t\t    (last->burst_regs[EMC_TRPAB_INDEX] ^ TRPab_war)) {\n\t\t\t\temc_writel(emc, RP_war, EMC_RP);\n\t\t\t\temc_writel(emc, R2P_war, EMC_R2P);\n\t\t\t\temc_writel(emc, W2P_war, EMC_W2P);\n\t\t\t\temc_writel(emc, TRPab_war, EMC_TRPAB);\n\t\t\t}\n\n\t\t\ttegra210_emc_timing_update(emc);\n\t\t} else {\n\t\t\temc_dbg(emc, INFO, \"Skipped WAR\\n\");\n\t\t}\n\t}\n\n\tif (!fsp_for_next_freq) {\n\t\tmr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80;\n\t\tmr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00;\n\t} else {\n\t\tmr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40;\n\t\tmr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0;\n\t}\n\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\temc_writel(emc, mr13_flip_fspwr, EMC_MRW3);\n\t\temc_writel(emc, next->emc_mrw, EMC_MRW);\n\t\temc_writel(emc, next->emc_mrw2, EMC_MRW2);\n\t}\n\n\t/*\n\t * Step 8:\n\t *   Program the shadow registers.\n\t */\n\temc_dbg(emc, STEPS, \"Step 8\\n\");\n\temc_dbg(emc, SUB_STEPS, \"Writing burst_regs\\n\");\n\n\tfor (i = 0; i < next->num_burst; i++) {\n\t\tconst u16 *offsets = emc->offsets->burst;\n\t\tu16 offset;\n\n\t\tif (!offsets[i])\n\t\t\tcontinue;\n\n\t\tvalue = next->burst_regs[i];\n\t\toffset = offsets[i];\n\n\t\tif (dram_type != DRAM_TYPE_LPDDR4 &&\n\t\t    (offset == EMC_MRW6 || offset == EMC_MRW7 ||\n\t\t     offset == EMC_MRW8 || offset == EMC_MRW9 ||\n\t\t     offset == EMC_MRW10 || offset == EMC_MRW11 ||\n\t\t     offset == EMC_MRW12 || offset == EMC_MRW13 ||\n\t\t     offset == EMC_MRW14 || offset == EMC_MRW15 ||\n\t\t     offset == EMC_TRAINING_CTRL))\n\t\t\tcontinue;\n\n\t\t/* Pain... And suffering. */\n\t\tif (offset == EMC_CFG) {\n\t\t\tvalue &= ~EMC_CFG_DRAM_ACPD;\n\t\t\tvalue &= ~EMC_CFG_DYN_SELF_REF;\n\n\t\t\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\t\t\tvalue &= ~EMC_CFG_DRAM_CLKSTOP_SR;\n\t\t\t\tvalue &= ~EMC_CFG_DRAM_CLKSTOP_PD;\n\t\t\t}\n\t\t} else if (offset == EMC_MRS_WAIT_CNT &&\n\t\t\t   dram_type == DRAM_TYPE_LPDDR2 &&\n\t\t\t   opt_zcal_en_cc && !opt_cc_short_zcal &&\n\t\t\t   opt_short_zcal) {\n\t\t\tvalue = (value & ~(EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK <<\n\t\t\t\t\t   EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)) |\n\t\t\t\t((zq_wait_long & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) <<\n\t\t\t\t\t\t EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT);\n\t\t} else if (offset == EMC_ZCAL_WAIT_CNT &&\n\t\t\t   dram_type == DRAM_TYPE_DDR3 && opt_zcal_en_cc &&\n\t\t\t   !opt_cc_short_zcal && opt_short_zcal) {\n\t\t\tvalue = (value & ~(EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK <<\n\t\t\t\t\t   EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT)) |\n\t\t\t\t((zq_wait_long & EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK) <<\n\t\t\t\t\t\t EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT);\n\t\t} else if (offset == EMC_ZCAL_INTERVAL && opt_zcal_en_cc) {\n\t\t\tvalue = 0; /* EMC_ZCAL_INTERVAL reset value. */\n\t\t} else if (offset == EMC_PMACRO_AUTOCAL_CFG_COMMON) {\n\t\t\tvalue |= EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS;\n\t\t} else if (offset == EMC_PMACRO_DATA_PAD_TX_CTRL) {\n\t\t\tvalue &= ~(EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC |\n\t\t\t\t   EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC |\n\t\t\t\t   EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC |\n\t\t\t\t   EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC);\n\t\t} else if (offset == EMC_PMACRO_CMD_PAD_TX_CTRL) {\n\t\t\tvalue |= EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON;\n\t\t\tvalue &= ~(EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC |\n\t\t\t\t   EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC |\n\t\t\t\t   EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC |\n\t\t\t\t   EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC);\n\t\t} else if (offset == EMC_PMACRO_BRICK_CTRL_RFU1) {\n\t\t\tvalue &= 0xf800f800;\n\t\t} else if (offset == EMC_PMACRO_COMMON_PAD_TX_CTRL) {\n\t\t\tvalue &= 0xfffffff0;\n\t\t}\n\n\t\temc_writel(emc, value, offset);\n\t}\n\n\t/* SW addition: do EMC refresh adjustment here. */\n\ttegra210_emc_adjust_timing(emc, next);\n\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\tvalue = (23 << EMC_MRW_MRW_MA_SHIFT) |\n\t\t\t(next->run_clocks & EMC_MRW_MRW_OP_MASK);\n\t\temc_writel(emc, value, EMC_MRW);\n\t}\n\n\t/* Per channel burst registers. */\n\temc_dbg(emc, SUB_STEPS, \"Writing burst_regs_per_ch\\n\");\n\n\tfor (i = 0; i < next->num_burst_per_ch; i++) {\n\t\tconst struct tegra210_emc_per_channel_regs *burst =\n\t\t\t\temc->offsets->burst_per_channel;\n\n\t\tif (!burst[i].offset)\n\t\t\tcontinue;\n\n\t\tif (dram_type != DRAM_TYPE_LPDDR4 &&\n\t\t    (burst[i].offset == EMC_MRW6 ||\n\t\t     burst[i].offset == EMC_MRW7 ||\n\t\t     burst[i].offset == EMC_MRW8 ||\n\t\t     burst[i].offset == EMC_MRW9 ||\n\t\t     burst[i].offset == EMC_MRW10 ||\n\t\t     burst[i].offset == EMC_MRW11 ||\n\t\t     burst[i].offset == EMC_MRW12 ||\n\t\t     burst[i].offset == EMC_MRW13 ||\n\t\t     burst[i].offset == EMC_MRW14 ||\n\t\t     burst[i].offset == EMC_MRW15))\n\t\t\tcontinue;\n\n\t\t/* Filter out second channel if not in DUAL_CHANNEL mode. */\n\t\tif (emc->num_channels < 2 && burst[i].bank >= 1)\n\t\t\tcontinue;\n\n\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\tnext->burst_reg_per_ch[i], burst[i].offset);\n\t\temc_channel_writel(emc, burst[i].bank,\n\t\t\t\t   next->burst_reg_per_ch[i],\n\t\t\t\t   burst[i].offset);\n\t}\n\n\t/* Vref regs. */\n\temc_dbg(emc, SUB_STEPS, \"Writing vref_regs\\n\");\n\n\tfor (i = 0; i < next->vref_num; i++) {\n\t\tconst struct tegra210_emc_per_channel_regs *vref =\n\t\t\t\t\temc->offsets->vref_per_channel;\n\n\t\tif (!vref[i].offset)\n\t\t\tcontinue;\n\n\t\tif (emc->num_channels < 2 && vref[i].bank >= 1)\n\t\t\tcontinue;\n\n\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\tnext->vref_perch_regs[i], vref[i].offset);\n\t\temc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i],\n\t\t\t\t   vref[i].offset);\n\t}\n\n\t/* Trimmers. */\n\temc_dbg(emc, SUB_STEPS, \"Writing trim_regs\\n\");\n\n\tfor (i = 0; i < next->num_trim; i++) {\n\t\tconst u16 *offsets = emc->offsets->trim;\n\n\t\tif (!offsets[i])\n\t\t\tcontinue;\n\n\t\tif (compensate_trimmer_applicable &&\n\t\t    (offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 ||\n\t\t     offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 ||\n\t\t     offsets[i] == EMC_DATA_BRLSHFT_0 ||\n\t\t     offsets[i] == EMC_DATA_BRLSHFT_1)) {\n\t\t\tvalue = tegra210_emc_compensate(next, offsets[i]);\n\t\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\t\tvalue, offsets[i]);\n\t\t\temc_dbg(emc, EMA_WRITES, \"0x%08x <= 0x%08x\\n\",\n\t\t\t\t(u32)(u64)offsets[i], value);\n\t\t\temc_writel(emc, value, offsets[i]);\n\t\t} else {\n\t\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\t\tnext->trim_regs[i], offsets[i]);\n\t\t\temc_writel(emc, next->trim_regs[i], offsets[i]);\n\t\t}\n\t}\n\n\t/* Per channel trimmers. */\n\temc_dbg(emc, SUB_STEPS, \"Writing trim_regs_per_ch\\n\");\n\n\tfor (i = 0; i < next->num_trim_per_ch; i++) {\n\t\tconst struct tegra210_emc_per_channel_regs *trim =\n\t\t\t\t&emc->offsets->trim_per_channel[0];\n\t\tunsigned int offset;\n\n\t\tif (!trim[i].offset)\n\t\t\tcontinue;\n\n\t\tif (emc->num_channels < 2 && trim[i].bank >= 1)\n\t\t\tcontinue;\n\n\t\toffset = trim[i].offset;\n\n\t\tif (compensate_trimmer_applicable &&\n\t\t    (offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 ||\n\t\t     offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 ||\n\t\t     offset == EMC_DATA_BRLSHFT_0 ||\n\t\t     offset == EMC_DATA_BRLSHFT_1)) {\n\t\t\tvalue = tegra210_emc_compensate(next, offset);\n\t\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\t\tvalue, offset);\n\t\t\temc_dbg(emc, EMA_WRITES, \"0x%08x <= 0x%08x\\n\", offset,\n\t\t\t\tvalue);\n\t\t\temc_channel_writel(emc, trim[i].bank, value, offset);\n\t\t} else {\n\t\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\t\tnext->trim_perch_regs[i], offset);\n\t\t\temc_channel_writel(emc, trim[i].bank,\n\t\t\t\t\t   next->trim_perch_regs[i], offset);\n\t\t}\n\t}\n\n\temc_dbg(emc, SUB_STEPS, \"Writing burst_mc_regs\\n\");\n\n\tfor (i = 0; i < next->num_mc_regs; i++) {\n\t\tconst u16 *offsets = emc->offsets->burst_mc;\n\t\tu32 *values = next->burst_mc_regs;\n\n\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\tvalues[i], offsets[i]);\n\t\tmc_writel(emc->mc, values[i], offsets[i]);\n\t}\n\n\t/* Registers to be programmed on the faster clock. */\n\tif (next->rate < last->rate) {\n\t\tconst u16 *la = emc->offsets->la_scale;\n\n\t\temc_dbg(emc, SUB_STEPS, \"Writing la_scale_regs\\n\");\n\n\t\tfor (i = 0; i < next->num_up_down; i++) {\n\t\t\temc_dbg(emc, REG_LISTS, \"(%u) 0x%08x => 0x%08x\\n\", i,\n\t\t\t\tnext->la_scale_regs[i], la[i]);\n\t\t\tmc_writel(emc->mc, next->la_scale_regs[i], la[i]);\n\t\t}\n\t}\n\n\t/* Flush all the burst register writes. */\n\tmc_readl(emc->mc, MC_EMEM_ADR_CFG);\n\n\t/*\n\t * Step 9:\n\t *   LPDDR4 section A.\n\t */\n\temc_dbg(emc, STEPS, \"Step 9\\n\");\n\n\tvalue = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX];\n\tvalue &= ~EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK;\n\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\temc_writel(emc, 0, EMC_ZCAL_INTERVAL);\n\t\temc_writel(emc, value, EMC_ZCAL_WAIT_CNT);\n\n\t\tvalue = emc_dbg | (EMC_DBG_WRITE_MUX_ACTIVE |\n\t\t\t\t   EMC_DBG_WRITE_ACTIVE_ONLY);\n\n\t\temc_writel(emc, value, EMC_DBG);\n\t\temc_writel(emc, 0, EMC_ZCAL_INTERVAL);\n\t\temc_writel(emc, emc_dbg, EMC_DBG);\n\t}\n\n\t/*\n\t * Step 10:\n\t *   LPDDR4 and DDR3 common section.\n\t */\n\temc_dbg(emc, STEPS, \"Step 10\\n\");\n\n\tif (opt_dvfs_mode == MAN_SR || dram_type == DRAM_TYPE_LPDDR4) {\n\t\tif (dram_type == DRAM_TYPE_LPDDR4)\n\t\t\tccfifo_writel(emc, 0x101, EMC_SELF_REF, 0);\n\t\telse\n\t\t\tccfifo_writel(emc, 0x1, EMC_SELF_REF, 0);\n\n\t\tif (dram_type == DRAM_TYPE_LPDDR4 &&\n\t\t    dst_clk_period <= zqcal_before_cc_cutoff) {\n\t\t\tccfifo_writel(emc, mr13_flip_fspwr ^ 0x40, EMC_MRW3, 0);\n\t\t\tccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] &\n\t\t\t\t\t\t0xFFFF3F3F) |\n\t\t\t\t\t   (last->burst_regs[EMC_MRW6_INDEX] &\n\t\t\t\t\t\t0x0000C0C0), EMC_MRW6, 0);\n\t\t\tccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] &\n\t\t\t\t\t\t0xFFFF0707) |\n\t\t\t\t\t   (last->burst_regs[EMC_MRW14_INDEX] &\n\t\t\t\t\t\t0x00003838), EMC_MRW14, 0);\n\n\t\t\tif (emc->num_devices > 1) {\n\t\t\t\tccfifo_writel(emc,\n\t\t\t\t      (next->burst_regs[EMC_MRW7_INDEX] &\n\t\t\t\t       0xFFFF3F3F) |\n\t\t\t\t      (last->burst_regs[EMC_MRW7_INDEX] &\n\t\t\t\t       0x0000C0C0), EMC_MRW7, 0);\n\t\t\t\tccfifo_writel(emc,\n\t\t\t\t     (next->burst_regs[EMC_MRW15_INDEX] &\n\t\t\t\t      0xFFFF0707) |\n\t\t\t\t     (last->burst_regs[EMC_MRW15_INDEX] &\n\t\t\t\t      0x00003838), EMC_MRW15, 0);\n\t\t\t}\n\n\t\t\tif (opt_zcal_en_cc) {\n\t\t\t\tif (emc->num_devices < 2)\n\t\t\t\t\tccfifo_writel(emc,\n\t\t\t\t\t\t2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT\n\t\t\t\t\t\t| EMC_ZQ_CAL_ZQ_CAL_CMD,\n\t\t\t\t\t\tEMC_ZQ_CAL, 0);\n\t\t\t\telse if (shared_zq_resistor)\n\t\t\t\t\tccfifo_writel(emc,\n\t\t\t\t\t\t2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT\n\t\t\t\t\t\t| EMC_ZQ_CAL_ZQ_CAL_CMD,\n\t\t\t\t\t\tEMC_ZQ_CAL, 0);\n\t\t\t\telse\n\t\t\t\t\tccfifo_writel(emc,\n\t\t\t\t\t\t      EMC_ZQ_CAL_ZQ_CAL_CMD,\n\t\t\t\t\t\t      EMC_ZQ_CAL, 0);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\tvalue = (1000 * fake->dram_timings[T_RP]) / src_clk_period;\n\t\tccfifo_writel(emc, mr13_flip_fspop | 0x8, EMC_MRW3, value);\n\t\tccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period);\n\t}\n\n\tif (dram_type == DRAM_TYPE_LPDDR4 || opt_dvfs_mode != MAN_SR) {\n\t\tdelay = 30;\n\n\t\tif (cya_allow_ref_cc) {\n\t\t\tdelay += (1000 * fake->dram_timings[T_RP]) /\n\t\t\t\t\tsrc_clk_period;\n\t\t\tdelay += 4000 * fake->dram_timings[T_RFC];\n\t\t}\n\n\t\tccfifo_writel(emc, emc_pin & ~(EMC_PIN_PIN_CKE_PER_DEV |\n\t\t\t\t\t       EMC_PIN_PIN_CKEB |\n\t\t\t\t\t       EMC_PIN_PIN_CKE),\n\t\t\t      EMC_PIN, delay);\n\t}\n\n\t/* calculate reference delay multiplier */\n\tvalue = 1;\n\n\tif (ref_b4_sref_en)\n\t\tvalue++;\n\n\tif (cya_allow_ref_cc)\n\t\tvalue++;\n\n\tif (cya_issue_pc_ref)\n\t\tvalue++;\n\n\tif (dram_type != DRAM_TYPE_LPDDR4) {\n\t\tdelay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) +\n\t\t\t (1000 * fake->dram_timings[T_RFC] / src_clk_period));\n\t\tdelay = value * delay + 20;\n\t} else {\n\t\tdelay = 0;\n\t}\n\n\t/*\n\t * Step 11:\n\t *   Ramp down.\n\t */\n\temc_dbg(emc, STEPS, \"Step 11\\n\");\n\n\tccfifo_writel(emc, 0x0, EMC_CFG_SYNC, delay);\n\n\tvalue = emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE | EMC_DBG_WRITE_ACTIVE_ONLY;\n\tccfifo_writel(emc, value, EMC_DBG, 0);\n\n\tramp_down_wait = tegra210_emc_dvfs_power_ramp_down(emc, src_clk_period,\n\t\t\t\t\t\t\t   0);\n\n\t/*\n\t * Step 12:\n\t *   And finally - trigger the clock change.\n\t */\n\temc_dbg(emc, STEPS, \"Step 12\\n\");\n\n\tccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE, 0);\n\tvalue &= ~EMC_DBG_WRITE_ACTIVE_ONLY;\n\tccfifo_writel(emc, value, EMC_DBG, 0);\n\n\t/*\n\t * Step 13:\n\t *   Ramp up.\n\t */\n\temc_dbg(emc, STEPS, \"Step 13\\n\");\n\n\tramp_up_wait = tegra210_emc_dvfs_power_ramp_up(emc, dst_clk_period, 0);\n\tccfifo_writel(emc, emc_dbg, EMC_DBG, 0);\n\n\t/*\n\t * Step 14:\n\t *   Bringup CKE pins.\n\t */\n\temc_dbg(emc, STEPS, \"Step 14\\n\");\n\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\tvalue = emc_pin | EMC_PIN_PIN_CKE;\n\n\t\tif (emc->num_devices <= 1)\n\t\t\tvalue &= ~(EMC_PIN_PIN_CKEB | EMC_PIN_PIN_CKE_PER_DEV);\n\t\telse\n\t\t\tvalue |= EMC_PIN_PIN_CKEB | EMC_PIN_PIN_CKE_PER_DEV;\n\n\t\tccfifo_writel(emc, value, EMC_PIN, 0);\n\t}\n\n\t/*\n\t * Step 15: (two step 15s ??)\n\t *   Calculate zqlatch wait time; has dependency on ramping times.\n\t */\n\temc_dbg(emc, STEPS, \"Step 15\\n\");\n\n\tif (dst_clk_period <= zqcal_before_cc_cutoff) {\n\t\ts32 t = (s32)(ramp_up_wait + ramp_down_wait) /\n\t\t\t(s32)dst_clk_period;\n\t\tzq_latch_dvfs_wait_time = (s32)tZQCAL_lpddr4_fc_adj - t;\n\t} else {\n\t\tzq_latch_dvfs_wait_time = tZQCAL_lpddr4_fc_adj -\n\t\t\tdiv_o3(1000 * next->dram_timings[T_PDEX],\n\t\t\t       dst_clk_period);\n\t}\n\n\temc_dbg(emc, INFO, \"tZQCAL_lpddr4_fc_adj = %u\\n\", tZQCAL_lpddr4_fc_adj);\n\temc_dbg(emc, INFO, \"dst_clk_period = %u\\n\",\n\t\tdst_clk_period);\n\temc_dbg(emc, INFO, \"next->dram_timings[T_PDEX] = %u\\n\",\n\t\tnext->dram_timings[T_PDEX]);\n\temc_dbg(emc, INFO, \"zq_latch_dvfs_wait_time = %d\\n\",\n\t\tmax_t(s32, 0, zq_latch_dvfs_wait_time));\n\n\tif (dram_type == DRAM_TYPE_LPDDR4 && opt_zcal_en_cc) {\n\t\tdelay = div_o3(1000 * next->dram_timings[T_PDEX],\n\t\t\t       dst_clk_period);\n\n\t\tif (emc->num_devices < 2) {\n\t\t\tif (dst_clk_period > zqcal_before_cc_cutoff)\n\t\t\t\tccfifo_writel(emc,\n\t\t\t\t\t      2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t\t      EMC_ZQ_CAL_ZQ_CAL_CMD, EMC_ZQ_CAL,\n\t\t\t\t\t      delay);\n\n\t\t\tvalue = (mr13_flip_fspop & 0xfffffff7) | 0x0c000000;\n\t\t\tccfifo_writel(emc, value, EMC_MRW3, delay);\n\t\t\tccfifo_writel(emc, 0, EMC_SELF_REF, 0);\n\t\t\tccfifo_writel(emc, 0, EMC_REF, 0);\n\t\t\tccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t      EMC_ZQ_CAL_ZQ_LATCH_CMD,\n\t\t\t\t      EMC_ZQ_CAL,\n\t\t\t\t      max_t(s32, 0, zq_latch_dvfs_wait_time));\n\t\t} else if (shared_zq_resistor) {\n\t\t\tif (dst_clk_period > zqcal_before_cc_cutoff)\n\t\t\t\tccfifo_writel(emc,\n\t\t\t\t\t      2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t\t      EMC_ZQ_CAL_ZQ_CAL_CMD, EMC_ZQ_CAL,\n\t\t\t\t\t      delay);\n\n\t\t\tccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t      EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,\n\t\t\t\t      max_t(s32, 0, zq_latch_dvfs_wait_time) +\n\t\t\t\t\tdelay);\n\t\t\tccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t      EMC_ZQ_CAL_ZQ_LATCH_CMD,\n\t\t\t\t      EMC_ZQ_CAL, 0);\n\n\t\t\tvalue = (mr13_flip_fspop & 0xfffffff7) | 0x0c000000;\n\t\t\tccfifo_writel(emc, value, EMC_MRW3, 0);\n\t\t\tccfifo_writel(emc, 0, EMC_SELF_REF, 0);\n\t\t\tccfifo_writel(emc, 0, EMC_REF, 0);\n\n\t\t\tccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t      EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,\n\t\t\t\t      tZQCAL_lpddr4 / dst_clk_period);\n\t\t} else {\n\t\t\tif (dst_clk_period > zqcal_before_cc_cutoff)\n\t\t\t\tccfifo_writel(emc, EMC_ZQ_CAL_ZQ_CAL_CMD,\n\t\t\t\t\t      EMC_ZQ_CAL, delay);\n\n\t\t\tvalue = (mr13_flip_fspop & 0xfffffff7) | 0x0c000000;\n\t\t\tccfifo_writel(emc, value, EMC_MRW3, delay);\n\t\t\tccfifo_writel(emc, 0, EMC_SELF_REF, 0);\n\t\t\tccfifo_writel(emc, 0, EMC_REF, 0);\n\n\t\t\tccfifo_writel(emc, EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,\n\t\t\t\t      max_t(s32, 0, zq_latch_dvfs_wait_time));\n\t\t}\n\t}\n\n\t/* WAR: delay for zqlatch */\n\tccfifo_writel(emc, 0, 0, 10);\n\n\t/*\n\t * Step 16:\n\t *   LPDDR4 Conditional Training Kickoff. Removed.\n\t */\n\n\t/*\n\t * Step 17:\n\t *   MANSR exit self refresh.\n\t */\n\temc_dbg(emc, STEPS, \"Step 17\\n\");\n\n\tif (opt_dvfs_mode == MAN_SR && dram_type != DRAM_TYPE_LPDDR4)\n\t\tccfifo_writel(emc, 0, EMC_SELF_REF, 0);\n\n\t/*\n\t * Step 18:\n\t *   Send MRWs to LPDDR3/DDR3.\n\t */\n\temc_dbg(emc, STEPS, \"Step 18\\n\");\n\n\tif (dram_type == DRAM_TYPE_LPDDR2) {\n\t\tccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0);\n\t\tccfifo_writel(emc, next->emc_mrw,  EMC_MRW,  0);\n\t\tif (is_lpddr3)\n\t\t\tccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0);\n\t} else if (dram_type == DRAM_TYPE_DDR3) {\n\t\tif (opt_dll_mode)\n\t\t\tccfifo_writel(emc, next->emc_emrs &\n\t\t\t\t      ~EMC_EMRS_USE_EMRS_LONG_CNT, EMC_EMRS, 0);\n\t\tccfifo_writel(emc, next->emc_emrs2 &\n\t\t\t      ~EMC_EMRS2_USE_EMRS2_LONG_CNT, EMC_EMRS2, 0);\n\t\tccfifo_writel(emc, next->emc_mrs |\n\t\t\t      EMC_EMRS_USE_EMRS_LONG_CNT, EMC_MRS, 0);\n\t}\n\n\t/*\n\t * Step 19:\n\t *   ZQCAL for LPDDR3/DDR3\n\t */\n\temc_dbg(emc, STEPS, \"Step 19\\n\");\n\n\tif (opt_zcal_en_cc) {\n\t\tif (dram_type == DRAM_TYPE_LPDDR2) {\n\t\t\tvalue = opt_cc_short_zcal ? 90000 : 360000;\n\t\t\tvalue = div_o3(value, dst_clk_period);\n\t\t\tvalue = value <<\n\t\t\t\tEMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT |\n\t\t\t\tvalue <<\n\t\t\t\tEMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT;\n\t\t\tccfifo_writel(emc, value, EMC_MRS_WAIT_CNT2, 0);\n\n\t\t\tvalue = opt_cc_short_zcal ? 0x56 : 0xab;\n\t\t\tccfifo_writel(emc, 2 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |\n\t\t\t\t\t   EMC_MRW_USE_MRW_EXT_CNT |\n\t\t\t\t\t   10 << EMC_MRW_MRW_MA_SHIFT |\n\t\t\t\t\t   value << EMC_MRW_MRW_OP_SHIFT,\n\t\t\t\t      EMC_MRW, 0);\n\n\t\t\tif (emc->num_devices > 1) {\n\t\t\t\tvalue = 1 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |\n\t\t\t\t\tEMC_MRW_USE_MRW_EXT_CNT |\n\t\t\t\t\t10 << EMC_MRW_MRW_MA_SHIFT |\n\t\t\t\t\tvalue << EMC_MRW_MRW_OP_SHIFT;\n\t\t\t\tccfifo_writel(emc, value, EMC_MRW, 0);\n\t\t\t}\n\t\t} else if (dram_type == DRAM_TYPE_DDR3) {\n\t\t\tvalue = opt_cc_short_zcal ? 0 : EMC_ZQ_CAL_LONG;\n\n\t\t\tccfifo_writel(emc, value |\n\t\t\t\t\t   2 << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t\t   EMC_ZQ_CAL_ZQ_CAL_CMD, EMC_ZQ_CAL,\n\t\t\t\t\t   0);\n\n\t\t\tif (emc->num_devices > 1) {\n\t\t\t\tvalue = value | 1 << EMC_ZQ_CAL_DEV_SEL_SHIFT |\n\t\t\t\t\t\tEMC_ZQ_CAL_ZQ_CAL_CMD;\n\t\t\t\tccfifo_writel(emc, value, EMC_ZQ_CAL, 0);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (bg_reg_mode_change) {\n\t\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\n\t\tif (ramp_up_wait <= 1250000)\n\t\t\tdelay = (1250000 - ramp_up_wait) / dst_clk_period;\n\t\telse\n\t\t\tdelay = 0;\n\n\t\tccfifo_writel(emc,\n\t\t\t      next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX],\n\t\t\t      EMC_PMACRO_BG_BIAS_CTRL_0, delay);\n\t\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\t}\n\n\t/*\n\t * Step 20:\n\t *   Issue ref and optional QRST.\n\t */\n\temc_dbg(emc, STEPS, \"Step 20\\n\");\n\n\tif (dram_type != DRAM_TYPE_LPDDR4)\n\t\tccfifo_writel(emc, 0, EMC_REF, 0);\n\n\tif (opt_do_sw_qrst) {\n\t\tccfifo_writel(emc, 1, EMC_ISSUE_QRST, 0);\n\t\tccfifo_writel(emc, 0, EMC_ISSUE_QRST, 2);\n\t}\n\n\t/*\n\t * Step 21:\n\t *   Restore ZCAL and ZCAL interval.\n\t */\n\temc_dbg(emc, STEPS, \"Step 21\\n\");\n\n\tif (save_restore_clkstop_pd || opt_zcal_en_cc) {\n\t\tccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,\n\t\t\t      EMC_DBG, 0);\n\t\tif (opt_zcal_en_cc && dram_type != DRAM_TYPE_LPDDR4)\n\t\t\tccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],\n\t\t\t\t      EMC_ZCAL_INTERVAL, 0);\n\n\t\tif (save_restore_clkstop_pd)\n\t\t\tccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] &\n\t\t\t\t\t\t~EMC_CFG_DYN_SELF_REF,\n\t\t\t\t      EMC_CFG, 0);\n\t\tccfifo_writel(emc, emc_dbg, EMC_DBG, 0);\n\t}\n\n\t/*\n\t * Step 22:\n\t *   Restore EMC_CFG_PIPE_CLK.\n\t */\n\temc_dbg(emc, STEPS, \"Step 22\\n\");\n\n\tccfifo_writel(emc, emc_cfg_pipe_clk, EMC_CFG_PIPE_CLK, 0);\n\n\tif (bg_reg_mode_change) {\n\t\tif (enable_bg_reg)\n\t\t\temc_writel(emc,\n\t\t\t\t   next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t\t\t\t~EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD,\n\t\t\t\t   EMC_PMACRO_BG_BIAS_CTRL_0);\n\t\telse\n\t\t\temc_writel(emc,\n\t\t\t\t   next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &\n\t\t\t\t\t~EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD,\n\t\t\t\t   EMC_PMACRO_BG_BIAS_CTRL_0);\n\t}\n\n\t/*\n\t * Step 23:\n\t */\n\temc_dbg(emc, STEPS, \"Step 23\\n\");\n\n\tvalue = emc_readl(emc, EMC_CFG_DIG_DLL);\n\tvalue |= EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC;\n\tvalue &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK;\n\tvalue &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK;\n\tvalue &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;\n\tvalue = (value & ~EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK) |\n\t\t(2 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT);\n\temc_writel(emc, value, EMC_CFG_DIG_DLL);\n\n\ttegra210_emc_do_clock_change(emc, clksrc);\n\n\t/*\n\t * Step 24:\n\t *   Save training results. Removed.\n\t */\n\n\t/*\n\t * Step 25:\n\t *   Program MC updown registers.\n\t */\n\temc_dbg(emc, STEPS, \"Step 25\\n\");\n\n\tif (next->rate > last->rate) {\n\t\tfor (i = 0; i < next->num_up_down; i++)\n\t\t\tmc_writel(emc->mc, next->la_scale_regs[i],\n\t\t\t\t  emc->offsets->la_scale[i]);\n\n\t\ttegra210_emc_timing_update(emc);\n\t}\n\n\t/*\n\t * Step 26:\n\t *   Restore ZCAL registers.\n\t */\n\temc_dbg(emc, STEPS, \"Step 26\\n\");\n\n\tif (dram_type == DRAM_TYPE_LPDDR4) {\n\t\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\t\temc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX],\n\t\t\t   EMC_ZCAL_WAIT_CNT);\n\t\temc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],\n\t\t\t   EMC_ZCAL_INTERVAL);\n\t\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\t}\n\n\tif (dram_type != DRAM_TYPE_LPDDR4 && opt_zcal_en_cc &&\n\t    !opt_short_zcal && opt_cc_short_zcal) {\n\t\tudelay(2);\n\n\t\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\t\tif (dram_type == DRAM_TYPE_LPDDR2)\n\t\t\temc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX],\n\t\t\t\t   EMC_MRS_WAIT_CNT);\n\t\telse if (dram_type == DRAM_TYPE_DDR3)\n\t\t\temc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX],\n\t\t\t\t   EMC_ZCAL_WAIT_CNT);\n\t\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\t}\n\n\t/*\n\t * Step 27:\n\t *   Restore EMC_CFG, FDPD registers.\n\t */\n\temc_dbg(emc, STEPS, \"Step 27\\n\");\n\n\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\temc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG);\n\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\temc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp,\n\t\t   EMC_FDPD_CTRL_CMD_NO_RAMP);\n\temc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);\n\n\t/*\n\t * Step 28:\n\t *   Training recover. Removed.\n\t */\n\temc_dbg(emc, STEPS, \"Step 28\\n\");\n\n\ttegra210_emc_set_shadow_bypass(emc, ACTIVE);\n\temc_writel(emc,\n\t\t   next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX],\n\t\t   EMC_PMACRO_AUTOCAL_CFG_COMMON);\n\ttegra210_emc_set_shadow_bypass(emc, ASSEMBLY);\n\n\t/*\n\t * Step 29:\n\t *   Power fix WAR.\n\t */\n\temc_dbg(emc, STEPS, \"Step 29\\n\");\n\n\temc_writel(emc, EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 |\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7,\n\t\t   EMC_PMACRO_CFG_PM_GLOBAL_0);\n\temc_writel(emc, EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR,\n\t\t   EMC_PMACRO_TRAINING_CTRL_0);\n\temc_writel(emc, EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR,\n\t\t   EMC_PMACRO_TRAINING_CTRL_1);\n\temc_writel(emc, 0, EMC_PMACRO_CFG_PM_GLOBAL_0);\n\n\t/*\n\t * Step 30:\n\t *   Re-enable autocal.\n\t */\n\temc_dbg(emc, STEPS, \"Step 30: Re-enable DLL and AUTOCAL\\n\");\n\n\tif (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) {\n\t\tvalue = emc_readl(emc, EMC_CFG_DIG_DLL);\n\t\tvalue |=  EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC;\n\t\tvalue |=  EMC_CFG_DIG_DLL_CFG_DLL_EN;\n\t\tvalue &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK;\n\t\tvalue &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK;\n\t\tvalue = (value & ~EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK) |\n\t\t\t(2 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT);\n\t\temc_writel(emc, value, EMC_CFG_DIG_DLL);\n\t\ttegra210_emc_timing_update(emc);\n\t}\n\n\temc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);\n\n\t/* Done! Yay. */\n}",
        "static void update_rq_clock_task(struct rq *rq, s64 delta)\n{\n/*\n * In theory, the compile should just see 0 here, and optimize out the call\n * to sched_rt_avg_update. But I don't trust it...": "static void update_rq_clock_task(struct rq *rq, s64 delta)\n{\n/*\n * In theory, the compile should just see 0 here, and optimize out the call\n * to sched_rt_avg_update. But I don't trust it...\n */\n\ts64 __maybe_unused steal = 0, irq_delta = 0;\n\n#ifdef CONFIG_IRQ_TIME_ACCOUNTING\n\tirq_delta = irq_time_read(cpu_of(rq)) - rq->prev_irq_time;\n\n\t/*\n\t * Since irq_time is only updated on {soft,}irq_exit, we might run into\n\t * this case when a previous update_rq_clock() happened inside a\n\t * {soft,}irq region.\n\t *\n\t * When this happens, we stop ->clock_task and only update the\n\t * prev_irq_time stamp to account for the part that fit, so that a next\n\t * update will consume the rest. This ensures ->clock_task is\n\t * monotonic.\n\t *\n\t * It does however cause some slight miss-attribution of {soft,}irq\n\t * time, a more accurate solution would be to update the irq_time using\n\t * the current rq->clock timestamp, except that would require using\n\t * atomic ops.\n\t */\n\tif (irq_delta > delta)\n\t\tirq_delta = delta;\n\n\trq->prev_irq_time += irq_delta;\n\tdelta -= irq_delta;\n#endif\n#ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING\n\tif (static_key_false((&paravirt_steal_rq_enabled))) {\n\t\tsteal = paravirt_steal_clock(cpu_of(rq));\n\t\tsteal -= rq->prev_steal_time_rq;\n\n\t\tif (unlikely(steal > delta))\n\t\t\tsteal = delta;\n\n\t\trq->prev_steal_time_rq += steal;\n\t\tdelta -= steal;\n\t}\n#endif\n\n\trq->clock_task += delta;\n\n#ifdef CONFIG_HAVE_SCHED_AVG_IRQ\n\tif ((irq_delta + steal) && sched_feat(NONTASK_CAPACITY))\n\t\tupdate_irq_load_avg(rq, irq_delta + steal);\n#endif\n\tupdate_rq_clock_pelt(rq, delta);\n}",
        "static int set_flicker(struct gspca_dev *gspca_dev, int on, int apply)\n{\n\t/* Everything in here is from the Windows driver */\n/* define for compgain calculation */\n#if 0": "static int set_flicker(struct gspca_dev *gspca_dev, int on, int apply)\n{\n\t/* Everything in here is from the Windows driver */\n/* define for compgain calculation */\n#if 0\n#define COMPGAIN(base, curexp, newexp) \\\n    (u8) ((((float) base - 128.0) * ((float) curexp / (float) newexp)) + 128.5)\n#define EXP_FROM_COMP(basecomp, curcomp, curexp) \\\n    (u16)((float)curexp * (float)(u8)(curcomp + 128) / \\\n    (float)(u8)(basecomp - 128))\n#else\n  /* equivalent functions without floating point math */\n#define COMPGAIN(base, curexp, newexp) \\\n    (u8)(128 + (((u32)(2*(base-128)*curexp + newexp)) / (2 * newexp)))\n#define EXP_FROM_COMP(basecomp, curcomp, curexp) \\\n    (u16)(((u32)(curexp * (u8)(curcomp + 128)) / (u8)(basecomp - 128)))\n#endif\n\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint currentexp = sd->params.exposure.coarseExpLo +\n\t\t\t sd->params.exposure.coarseExpHi * 256;\n\tint ret, startexp;\n\n\tif (on) {\n\t\tint cj = sd->params.flickerControl.coarseJump;\n\t\tsd->params.flickerControl.flickerMode = 1;\n\t\tsd->params.flickerControl.disabled = 0;\n\t\tif (sd->params.exposure.expMode != 2) {\n\t\t\tsd->params.exposure.expMode = 2;\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t}\n\t\tcurrentexp = currentexp << sd->params.exposure.gain;\n\t\tsd->params.exposure.gain = 0;\n\t\t/* round down current exposure to nearest value */\n\t\tstartexp = (currentexp + ROUND_UP_EXP_FOR_FLICKER) / cj;\n\t\tif (startexp < 1)\n\t\t\tstartexp = 1;\n\t\tstartexp = (startexp * cj) - 1;\n\t\tif (FIRMWARE_VERSION(1, 2))\n\t\t\twhile (startexp > MAX_EXP_102)\n\t\t\t\tstartexp -= cj;\n\t\telse\n\t\t\twhile (startexp > MAX_EXP)\n\t\t\t\tstartexp -= cj;\n\t\tsd->params.exposure.coarseExpLo = startexp & 0xff;\n\t\tsd->params.exposure.coarseExpHi = startexp >> 8;\n\t\tif (currentexp > startexp) {\n\t\t\tif (currentexp > (2 * startexp))\n\t\t\t\tcurrentexp = 2 * startexp;\n\t\t\tsd->params.exposure.redComp =\n\t\t\t\tCOMPGAIN(COMP_RED, currentexp, startexp);\n\t\t\tsd->params.exposure.green1Comp =\n\t\t\t\tCOMPGAIN(COMP_GREEN1, currentexp, startexp);\n\t\t\tsd->params.exposure.green2Comp =\n\t\t\t\tCOMPGAIN(COMP_GREEN2, currentexp, startexp);\n\t\t\tsd->params.exposure.blueComp =\n\t\t\t\tCOMPGAIN(COMP_BLUE, currentexp, startexp);\n\t\t} else {\n\t\t\tsd->params.exposure.redComp = COMP_RED;\n\t\t\tsd->params.exposure.green1Comp = COMP_GREEN1;\n\t\t\tsd->params.exposure.green2Comp = COMP_GREEN2;\n\t\t\tsd->params.exposure.blueComp = COMP_BLUE;\n\t\t}\n\t\tif (FIRMWARE_VERSION(1, 2))\n\t\t\tsd->params.exposure.compMode = 0;\n\t\telse\n\t\t\tsd->params.exposure.compMode = 1;\n\n\t\tsd->params.apcor.gain1 = 0x18;\n\t\tsd->params.apcor.gain2 = 0x18;\n\t\tsd->params.apcor.gain4 = 0x16;\n\t\tsd->params.apcor.gain8 = 0x14;\n\t} else {\n\t\tsd->params.flickerControl.flickerMode = 0;\n\t\tsd->params.flickerControl.disabled = 1;\n\t\t/* Average equivalent coarse for each comp channel */\n\t\tstartexp = EXP_FROM_COMP(COMP_RED,\n\t\t\t\tsd->params.exposure.redComp, currentexp);\n\t\tstartexp += EXP_FROM_COMP(COMP_GREEN1,\n\t\t\t\tsd->params.exposure.green1Comp, currentexp);\n\t\tstartexp += EXP_FROM_COMP(COMP_GREEN2,\n\t\t\t\tsd->params.exposure.green2Comp, currentexp);\n\t\tstartexp += EXP_FROM_COMP(COMP_BLUE,\n\t\t\t\tsd->params.exposure.blueComp, currentexp);\n\t\tstartexp = startexp >> 2;\n\t\twhile (startexp > MAX_EXP && sd->params.exposure.gain <\n\t\t       sd->params.exposure.gainMode - 1) {\n\t\t\tstartexp = startexp >> 1;\n\t\t\t++sd->params.exposure.gain;\n\t\t}\n\t\tif (FIRMWARE_VERSION(1, 2) && startexp > MAX_EXP_102)\n\t\t\tstartexp = MAX_EXP_102;\n\t\tif (startexp > MAX_EXP)\n\t\t\tstartexp = MAX_EXP;\n\t\tsd->params.exposure.coarseExpLo = startexp & 0xff;\n\t\tsd->params.exposure.coarseExpHi = startexp >> 8;\n\t\tsd->params.exposure.redComp = COMP_RED;\n\t\tsd->params.exposure.green1Comp = COMP_GREEN1;\n\t\tsd->params.exposure.green2Comp = COMP_GREEN2;\n\t\tsd->params.exposure.blueComp = COMP_BLUE;\n\t\tsd->params.exposure.compMode = 1;\n\t\tsd->params.apcor.gain1 = 0x18;\n\t\tsd->params.apcor.gain2 = 0x16;\n\t\tsd->params.apcor.gain4 = 0x24;\n\t\tsd->params.apcor.gain8 = 0x34;\n\t}\n\tsd->params.vlOffset.gain1 = 20;\n\tsd->params.vlOffset.gain2 = 24;\n\tsd->params.vlOffset.gain4 = 26;\n\tsd->params.vlOffset.gain8 = 26;\n\n\tif (apply) {\n\t\tret = command_setexposure(gspca_dev);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = command_setapcor(gspca_dev);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = command_setvloffset(gspca_dev);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = command_setflickerctrl(gspca_dev);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n#undef EXP_FROM_COMP\n#undef COMPGAIN\n}",
        "static void rtl_hw_start_8106(struct rtl8169_private *tp)\n{\n\trtl_hw_aspm_clkreq_enable(tp, false);\n\n\t/* Force LAN exit from ASPM if Rx/Tx are not idle */": "static void rtl_hw_start_8106(struct rtl8169_private *tp)\n{\n\trtl_hw_aspm_clkreq_enable(tp, false);\n\n\t/* Force LAN exit from ASPM if Rx/Tx are not idle */\n\tRTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);\n\n\tRTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);\n\tRTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);\n\tRTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);\n\n\t/* L0 7us, L1 32us - needed to avoid issues with link-up detection */\n\trtl_set_aspm_entry_latency(tp, 0x2f);\n\n\trtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);\n\n\t/* disable EEE */\n\trtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);\n\n\trtl_pcie_state_l2l3_disable(tp);\n\trtl_hw_aspm_clkreq_enable(tp, true);\n}",
        "static inline int write_dword (__u32 offset,__u32 x)\n{\n   __u32 status;\n\n#ifdef LART_DEBUG": "static inline int write_dword (__u32 offset,__u32 x)\n{\n   __u32 status;\n\n#ifdef LART_DEBUG\n   printk (KERN_DEBUG \"%s(): 0x%.8x <- 0x%.8x\\n\", __func__, offset, x);\n#endif\n\n   /* setup writing */\n   write32 (DATA_TO_FLASH (PGM_SETUP),offset);\n\n   /* write the data */\n   write32 (x,offset);\n\n   /* wait for the write to finish */\n   do\n\t {\n\t\twrite32 (DATA_TO_FLASH (STATUS_READ),offset);\n\t\tstatus = FLASH_TO_DATA (read32 (offset));\n\t }\n   while ((~status & STATUS_BUSY) != 0);\n\n   /* put the flash back into command mode */\n   write32 (DATA_TO_FLASH (READ_ARRAY),offset);\n\n   /* was the write successful? */\n   if ((status & STATUS_PGM_ERR) || read32 (offset) != x)\n\t {\n\t\tprintk (KERN_WARNING \"%s: write error at address 0x%.8x.\\n\",module_name,offset);\n\t\treturn (0);\n\t }\n\n   return (1);\n}",
        "static void rtl_hw_start_8168g(struct rtl8169_private *tp)\n{\n\trtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);\n\trtl8168g_set_pause_thresholds(tp, 0x38, 0x48);\n": "static void rtl_hw_start_8168g(struct rtl8169_private *tp)\n{\n\trtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);\n\trtl8168g_set_pause_thresholds(tp, 0x38, 0x48);\n\n\trtl_set_def_aspm_entry_latency(tp);\n\n\trtl_reset_packet_filter(tp);\n\trtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);\n\n\tRTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);\n\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);\n\trtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);\n\n\trtl8168_config_eee_mac(tp);\n\n\trtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);\n\trtl_eri_clear_bits(tp, 0x1b0, BIT(12));\n\n\trtl_pcie_state_l2l3_disable(tp);\n}",
        "static void measure(int fd)\n{\n    time_t start_time;\n    int last_state;\n    time_t last_time;": "static void measure(int fd)\n{\n    time_t start_time;\n    int last_state;\n    time_t last_time;\n    int curr_state;\n    time_t curr_time = 0;\n    time_t time_diff;\n    time_t active_time = 0;\n    time_t sleep_time = 0;\n    time_t unknown_time = 0;\n    time_t total_time = 0;\n    int changes = 0;\n    float tmp;\n\n    printf(\"Starting measurements\\n\");\n\n    last_state = check_powermode(fd);\n    start_time = last_time = time(0);\n    printf(\"  System is in state %s\\n\\n\", state_name(last_state));\n\n    while(!endit) {\n\tsleep(1);\n\tcurr_state = check_powermode(fd);\n\n\tif (curr_state != last_state || endit) {\n\t    changes++;\n\t    curr_time = time(0);\n\t    time_diff = curr_time - last_time;\n\n\t    if (last_state == 1) active_time += time_diff;\n\t    else if (last_state == 0) sleep_time += time_diff;\n\t    else unknown_time += time_diff;\n\n\t    last_state = curr_state;\n\t    last_time = curr_time;\n\n\t    printf(\"%s: State-change to %s\\n\", myctime(curr_time),\n\t\t   state_name(curr_state));\n\t}\n    }\n    changes--; /* Compensate for SIGINT */\n\n    total_time = time(0) - start_time;\n    printf(\"\\nTotal running time:  %lus\\n\", curr_time - start_time);\n    printf(\" State changed %d times\\n\", changes);\n\n    tmp = (float)sleep_time / (float)total_time * 100;\n    printf(\" Time in sleep state:   %lus (%.2f%%)\\n\", sleep_time, tmp);\n    tmp = (float)active_time / (float)total_time * 100;\n    printf(\" Time in active state:  %lus (%.2f%%)\\n\", active_time, tmp);\n    tmp = (float)unknown_time / (float)total_time * 100;\n    printf(\" Time in unknown state: %lus (%.2f%%)\\n\", unknown_time, tmp);\n}",
        "static void test_reuseport_array(void)\n{\n#define REUSEPORT_FD_IDX(err, last) ({ (err) ? last : !last; })\n\n\tconst __u32 array_size = 4, index0 = 0, index3 = 3;": "static void test_reuseport_array(void)\n{\n#define REUSEPORT_FD_IDX(err, last) ({ (err) ? last : !last; })\n\n\tconst __u32 array_size = 4, index0 = 0, index3 = 3;\n\tint types[2] = { SOCK_STREAM, SOCK_DGRAM }, type;\n\t__u64 grpa_cookies[2], sk_cookie, map_cookie;\n\t__s64 grpa_fds64[2] = { -1, -1 }, fd64 = -1;\n\tconst __u32 bad_index = array_size;\n\tint map_fd, err, t, f;\n\t__u32 fds_idx = 0;\n\tint fd;\n\n\tmap_fd = bpf_map_create(BPF_MAP_TYPE_REUSEPORT_SOCKARRAY, NULL,\n\t\t\t\tsizeof(__u32), sizeof(__u64), array_size, NULL);\n\tCHECK(map_fd < 0, \"reuseport array create\",\n\t      \"map_fd:%d, errno:%d\\n\", map_fd, errno);\n\n\t/* Test lookup/update/delete with invalid index */\n\terr = bpf_map_delete_elem(map_fd, &bad_index);\n\tCHECK(err >= 0 || errno != E2BIG, \"reuseport array del >=max_entries\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\n\terr = bpf_map_update_elem(map_fd, &bad_index, &fd64, BPF_ANY);\n\tCHECK(err >= 0 || errno != E2BIG,\n\t      \"reuseport array update >=max_entries\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\n\terr = bpf_map_lookup_elem(map_fd, &bad_index, &map_cookie);\n\tCHECK(err >= 0 || errno != ENOENT,\n\t      \"reuseport array update >=max_entries\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\n\t/* Test lookup/delete non existence elem */\n\terr = bpf_map_lookup_elem(map_fd, &index3, &map_cookie);\n\tCHECK(err >= 0 || errno != ENOENT,\n\t      \"reuseport array lookup not-exist elem\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\terr = bpf_map_delete_elem(map_fd, &index3);\n\tCHECK(err >= 0 || errno != ENOENT,\n\t      \"reuseport array del not-exist elem\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\n\tfor (t = 0; t < ARRAY_SIZE(types); t++) {\n\t\ttype = types[t];\n\n\t\tprepare_reuseport_grp(type, map_fd, sizeof(__u64), grpa_fds64,\n\t\t\t\t      grpa_cookies, ARRAY_SIZE(grpa_fds64));\n\n\t\t/* Test BPF_* update flags */\n\t\t/* BPF_EXIST failure case */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &grpa_fds64[fds_idx],\n\t\t\t\t\t  BPF_EXIST);\n\t\tCHECK(err >= 0 || errno != ENOENT,\n\t\t      \"reuseport array update empty elem BPF_EXIST\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\t\tfds_idx = REUSEPORT_FD_IDX(err, fds_idx);\n\n\t\t/* BPF_NOEXIST success case */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &grpa_fds64[fds_idx],\n\t\t\t\t\t  BPF_NOEXIST);\n\t\tCHECK(err < 0,\n\t\t      \"reuseport array update empty elem BPF_NOEXIST\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\t\tfds_idx = REUSEPORT_FD_IDX(err, fds_idx);\n\n\t\t/* BPF_EXIST success case. */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &grpa_fds64[fds_idx],\n\t\t\t\t\t  BPF_EXIST);\n\t\tCHECK(err < 0,\n\t\t      \"reuseport array update same elem BPF_EXIST\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\", type, err, errno);\n\t\tfds_idx = REUSEPORT_FD_IDX(err, fds_idx);\n\n\t\t/* BPF_NOEXIST failure case */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &grpa_fds64[fds_idx],\n\t\t\t\t\t  BPF_NOEXIST);\n\t\tCHECK(err >= 0 || errno != EEXIST,\n\t\t      \"reuseport array update non-empty elem BPF_NOEXIST\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\t\tfds_idx = REUSEPORT_FD_IDX(err, fds_idx);\n\n\t\t/* BPF_ANY case (always succeed) */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &grpa_fds64[fds_idx],\n\t\t\t\t\t  BPF_ANY);\n\t\tCHECK(err < 0,\n\t\t      \"reuseport array update same sk with BPF_ANY\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\", type, err, errno);\n\n\t\tfd64 = grpa_fds64[fds_idx];\n\t\tsk_cookie = grpa_cookies[fds_idx];\n\n\t\t/* The same sk cannot be added to reuseport_array twice */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &fd64, BPF_ANY);\n\t\tCHECK(err >= 0 || errno != EBUSY,\n\t\t      \"reuseport array update same sk with same index\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\n\t\terr = bpf_map_update_elem(map_fd, &index0, &fd64, BPF_ANY);\n\t\tCHECK(err >= 0 || errno != EBUSY,\n\t\t      \"reuseport array update same sk with different index\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\n\t\t/* Test delete elem */\n\t\terr = bpf_map_delete_elem(map_fd, &index3);\n\t\tCHECK(err < 0, \"reuseport array delete sk\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\n\t\t/* Add it back with BPF_NOEXIST */\n\t\terr = bpf_map_update_elem(map_fd, &index3, &fd64, BPF_NOEXIST);\n\t\tCHECK(err < 0,\n\t\t      \"reuseport array re-add with BPF_NOEXIST after del\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\", type, err, errno);\n\n\t\t/* Test cookie */\n\t\terr = bpf_map_lookup_elem(map_fd, &index3, &map_cookie);\n\t\tCHECK(err < 0 || sk_cookie != map_cookie,\n\t\t      \"reuseport array lookup re-added sk\",\n\t\t      \"sock_type:%d err:%d errno:%d sk_cookie:0x%llx map_cookie:0x%llxn\",\n\t\t      type, err, errno, sk_cookie, map_cookie);\n\n\t\t/* Test elem removed by close() */\n\t\tfor (f = 0; f < ARRAY_SIZE(grpa_fds64); f++)\n\t\t\tclose(grpa_fds64[f]);\n\t\terr = bpf_map_lookup_elem(map_fd, &index3, &map_cookie);\n\t\tCHECK(err >= 0 || errno != ENOENT,\n\t\t      \"reuseport array lookup after close()\",\n\t\t      \"sock_type:%d err:%d errno:%d\\n\",\n\t\t      type, err, errno);\n\t}\n\n\t/* Test SOCK_RAW */\n\tfd64 = socket(AF_INET6, SOCK_RAW, IPPROTO_UDP);\n\tCHECK(fd64 == -1, \"socket(SOCK_RAW)\", \"err:%d errno:%d\\n\",\n\t      err, errno);\n\terr = bpf_map_update_elem(map_fd, &index3, &fd64, BPF_NOEXIST);\n\tCHECK(err >= 0 || errno != ENOTSUPP, \"reuseport array update SOCK_RAW\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\tclose(fd64);\n\n\t/* Close the 64 bit value map */\n\tclose(map_fd);\n\n\t/* Test 32 bit fd */\n\tmap_fd = bpf_map_create(BPF_MAP_TYPE_REUSEPORT_SOCKARRAY, NULL,\n\t\t\t\tsizeof(__u32), sizeof(__u32), array_size, NULL);\n\tCHECK(map_fd < 0, \"reuseport array create\",\n\t      \"map_fd:%d, errno:%d\\n\", map_fd, errno);\n\tprepare_reuseport_grp(SOCK_STREAM, map_fd, sizeof(__u32), &fd64,\n\t\t\t      &sk_cookie, 1);\n\tfd = fd64;\n\terr = bpf_map_update_elem(map_fd, &index3, &fd, BPF_NOEXIST);\n\tCHECK(err < 0, \"reuseport array update 32 bit fd\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\terr = bpf_map_lookup_elem(map_fd, &index3, &map_cookie);\n\tCHECK(err >= 0 || errno != ENOSPC,\n\t      \"reuseport array lookup 32 bit fd\",\n\t      \"err:%d errno:%d\\n\", err, errno);\n\tclose(fd);\n\tclose(map_fd);\n}",
        "static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)\n{\n\tunsigned long flags;\n\tunsigned int phiIncr, coeffIncr, tmp1, tmp2;\n\tunsigned int correctionPerGOF, correctionPerSec, initialDelay;": "static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)\n{\n\tunsigned long flags;\n\tunsigned int phiIncr, coeffIncr, tmp1, tmp2;\n\tunsigned int correctionPerGOF, correctionPerSec, initialDelay;\n\tunsigned int frameGroupLength, cnt;\n\n\t/*\n\t *  We can only decimate by up to a factor of 1/9th the hardware rate.\n\t *  Correct the value if an attempt is made to stray outside that limit.\n\t */\n\tif ((rate * 9) < 48000)\n\t\trate = 48000 / 9;\n\n\t/*\n\t *  We can not capture at a rate greater than the Input Rate (48000).\n\t *  Return an error if an attempt is made to stray outside that limit.\n\t */\n\tif (rate > 48000)\n\t\trate = 48000;\n\n\t/*\n\t *  Compute the values used to drive the actual sample rate conversion.\n\t *  The following formulas are being computed, using inline assembly\n\t *  since we need to use 64 bit arithmetic to compute the values:\n\t *\n\t *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)\n\t *     phiIncr = floor((Fs,in * 2^26) / Fs,out)\n\t *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /\n\t *                                GOF_PER_SEC)\n\t *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -\n\t *                          GOF_PER_SEC * correctionPerGOF\n\t *     initialDelay = ceil((24 * Fs,in) / Fs,out)\n\t *\n\t * i.e.\n\t *\n\t *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))\n\t *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)\n\t *     correctionPerGOF:correctionPerSec =\n\t * \t    dividend:remainder(ulOther / GOF_PER_SEC)\n\t *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)\n\t */\n\n\ttmp1 = rate << 16;\n\tcoeffIncr = tmp1 / 48000;\n\ttmp1 -= coeffIncr * 48000;\n\ttmp1 <<= 7;\n\tcoeffIncr <<= 7;\n\tcoeffIncr += tmp1 / 48000;\n\tcoeffIncr ^= 0xFFFFFFFF;\n\tcoeffIncr++;\n\ttmp1 = 48000 << 16;\n\tphiIncr = tmp1 / rate;\n\ttmp1 -= phiIncr * rate;\n\ttmp1 <<= 10;\n\tphiIncr <<= 10;\n\ttmp2 = tmp1 / rate;\n\tphiIncr += tmp2;\n\ttmp1 -= tmp2 * rate;\n\tcorrectionPerGOF = tmp1 / GOF_PER_SEC;\n\ttmp1 -= correctionPerGOF * GOF_PER_SEC;\n\tcorrectionPerSec = tmp1;\n\tinitialDelay = DIV_ROUND_UP(48000 * 24, rate);\n\n\t/*\n\t *  Fill in the VariDecimate control block.\n\t */\n\tspin_lock_irqsave(&chip->reg_lock, flags);\n\tsnd_cs46xx_poke(chip, BA1_CSRC,\n\t\t((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));\n\tsnd_cs46xx_poke(chip, BA1_CCI, coeffIncr);\n\tsnd_cs46xx_poke(chip, BA1_CD,\n\t\t(((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);\n\tsnd_cs46xx_poke(chip, BA1_CPI, phiIncr);\n\tspin_unlock_irqrestore(&chip->reg_lock, flags);\n\n\t/*\n\t *  Figure out the frame group length for the write back task.  Basically,\n\t *  this is just the factors of 24000 (2^6*3*5^3) that are not present in\n\t *  the output sample rate.\n\t */\n\tframeGroupLength = 1;\n\tfor (cnt = 2; cnt <= 64; cnt *= 2) {\n\t\tif (((rate / cnt) * cnt) != rate)\n\t\t\tframeGroupLength *= 2;\n\t}\n\tif (((rate / 3) * 3) != rate) {\n\t\tframeGroupLength *= 3;\n\t}\n\tfor (cnt = 5; cnt <= 125; cnt *= 5) {\n\t\tif (((rate / cnt) * cnt) != rate) \n\t\t\tframeGroupLength *= 5;\n        }\n\n\t/*\n\t * Fill in the WriteBack control block.\n\t */\n\tspin_lock_irqsave(&chip->reg_lock, flags);\n\tsnd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);\n\tsnd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));\n\tsnd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);\n\tsnd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));\n\tsnd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);\n\tspin_unlock_irqrestore(&chip->reg_lock, flags);\n}",
        "static int cake_config_diffserv8(struct Qdisc *sch)\n{\n/*\tPruned list of traffic classes for typical applications:\n *\n *\t\tNetwork Control          (CS6, CS7)": "static int cake_config_diffserv8(struct Qdisc *sch)\n{\n/*\tPruned list of traffic classes for typical applications:\n *\n *\t\tNetwork Control          (CS6, CS7)\n *\t\tMinimum Latency          (EF, VA, CS5, CS4)\n *\t\tInteractive Shell        (CS2)\n *\t\tLow Latency Transactions (AF2x, TOS4)\n *\t\tVideo Streaming          (AF4x, AF3x, CS3)\n *\t\tBog Standard             (DF etc.)\n *\t\tHigh Throughput          (AF1x, TOS2, CS1)\n *\t\tBackground Traffic       (LE)\n *\n *\t\tTotal 8 traffic classes.\n */\n\n\tstruct cake_sched_data *q = qdisc_priv(sch);\n\tu32 mtu = psched_mtu(qdisc_dev(sch));\n\tu64 rate = q->rate_bps;\n\tu32 quantum = 256;\n\tu32 i;\n\n\tq->tin_cnt = 8;\n\n\t/* codepoint to class mapping */\n\tq->tin_index = diffserv8;\n\tq->tin_order = normal_order;\n\n\t/* class characteristics */\n\tfor (i = 0; i < q->tin_cnt; i++) {\n\t\tstruct cake_tin_data *b = &q->tins[i];\n\n\t\tcake_set_rate(b, rate, mtu, us_to_ns(q->target),\n\t\t\t      us_to_ns(q->interval));\n\n\t\tb->tin_quantum = max_t(u16, 1U, quantum);\n\n\t\t/* calculate next class's parameters */\n\t\trate  *= 7;\n\t\trate >>= 3;\n\n\t\tquantum  *= 7;\n\t\tquantum >>= 3;\n\t}\n\n\treturn 0;\n}",
        "static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)\n{\n\tint err, i, z, gpr, nctl;\n\tint bit_shifter16;\n\tconst int playback = 10;": "static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)\n{\n\tint err, i, z, gpr, nctl;\n\tint bit_shifter16;\n\tconst int playback = 10;\n\tconst int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */\n\tconst int stereo_mix = capture + 2;\n\tconst int tmp = 0x88;\n\tu32 ptr;\n\tstruct snd_emu10k1_fx8010_code *icode = NULL;\n\tstruct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;\n\tu32 *gpr_map;\n\n\terr = -ENOMEM;\n\ticode = kzalloc(sizeof(*icode), GFP_KERNEL);\n\tif (!icode)\n\t\treturn err;\n\n\ticode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024,\n\t\t\t\t sizeof(u_int32_t), GFP_KERNEL);\n\tif (!icode->gpr_map)\n\t\tgoto __err_gpr;\n\tcontrols = kcalloc(SND_EMU10K1_GPR_CONTROLS,\n\t\t\t   sizeof(*controls), GFP_KERNEL);\n\tif (!controls)\n\t\tgoto __err_ctrls;\n\n\tgpr_map = icode->gpr_map;\n\n\ticode->tram_data_map = icode->gpr_map + 512;\n\ticode->tram_addr_map = icode->tram_data_map + 256;\n\ticode->code = icode->tram_addr_map + 256;\n\n\t/* clear free GPRs */\n\tfor (i = 0; i < 512; i++)\n\t\tset_bit(i, icode->gpr_valid);\n\t\t\n\t/* clear TRAM data & address lines */\n\tfor (i = 0; i < 256; i++)\n\t\tset_bit(i, icode->tram_valid);\n\n\tstrcpy(icode->name, \"Audigy DSP code for ALSA\");\n\tptr = 0;\n\tnctl = 0;\n\tgpr = stereo_mix + 10;\n\tgpr_map[gpr++] = 0x00007fff;\n\tgpr_map[gpr++] = 0x00008000;\n\tgpr_map[gpr++] = 0x0000ffff;\n\tbit_shifter16 = gpr;\n\n\t/* stop FX processor */\n\tsnd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);\n\n#if 1\n\t/* PCM front Playback Volume (independent from stereo mix)\n\t * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)\n\t * where gpr contains attenuation from corresponding mixer control\n\t * (snd_emu10k1_init_stereo_control)\n\t */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"PCM Front Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* PCM Surround Playback (independent from stereo mix) */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"PCM Surround Playback Volume\", gpr, 100);\n\tgpr += 2;\n\t\n\t/* PCM Side Playback (independent from stereo mix) */\n\tif (emu->card_capabilities->spk71) {\n\t\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));\n\t\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));\n\t\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"PCM Side Playback Volume\", gpr, 100);\n\t\tgpr += 2;\n\t}\n\n\t/* PCM Center Playback (independent from stereo mix) */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));\n\tsnd_emu10k1_init_mono_control(&controls[nctl++], \"PCM Center Playback Volume\", gpr, 100);\n\tgpr++;\n\n\t/* PCM LFE Playback (independent from stereo mix) */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));\n\tsnd_emu10k1_init_mono_control(&controls[nctl++], \"PCM LFE Playback Volume\", gpr, 100);\n\tgpr++;\n\t\n\t/*\n\t * Stereo Mix\n\t */\n\t/* Wave (PCM) Playback Volume (will be renamed later) */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Wave Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* Synth Playback */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Synth Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* Wave (PCM) Capture */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"PCM Capture Volume\", gpr, 0);\n\tgpr += 2;\n\n\t/* Synth Capture */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Synth Capture Volume\", gpr, 0);\n\tgpr += 2;\n      \n\t/*\n\t * inputs\n\t */\n#define A_ADD_VOLUME_IN(var,vol,input) \\\nA_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))\n\n\t/* emu1212 DSP 0 and DSP 1 Capture */\n\tif (emu->card_capabilities->emu_model) {\n\t\tif (emu->card_capabilities->ca0108_chip) {\n\t\t\t/* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */\n\t\t\tA_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);\n\t\t\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));\n\t\t\tA_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);\n\t\t\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));\n\t\t} else {\n\t\t\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));\n\t\t\tA_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"EMU Capture Volume\", gpr, 0);\n\t\tgpr += 2;\n\t}\n\t/* AC'97 Playback Volume - used only for mic (renamed later) */\n\tA_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);\n\tA_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"AMic Playback Volume\", gpr, 0);\n\tgpr += 2;\n\t/* AC'97 Capture Volume - used only for mic */\n\tA_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);\n\tA_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Mic Capture Volume\", gpr, 0);\n\tgpr += 2;\n\n\t/* mic capture buffer */\t\n\tA_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));\n\n\t/* Audigy CD Playback Volume */\n\tA_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);\n\tA_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++],\n\t\t\t\t\temu->card_capabilities->ac97_chip ? \"Audigy CD Playback Volume\" : \"CD Playback Volume\",\n\t\t\t\t\tgpr, 0);\n\tgpr += 2;\n\t/* Audigy CD Capture Volume */\n\tA_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);\n\tA_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++],\n\t\t\t\t\temu->card_capabilities->ac97_chip ? \"Audigy CD Capture Volume\" : \"CD Capture Volume\",\n\t\t\t\t\tgpr, 0);\n\tgpr += 2;\n\n \t/* Optical SPDIF Playback Volume */\n\tA_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);\n\tA_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958(\"Optical \",PLAYBACK,VOLUME), gpr, 0);\n\tgpr += 2;\n\t/* Optical SPDIF Capture Volume */\n\tA_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);\n\tA_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958(\"Optical \",CAPTURE,VOLUME), gpr, 0);\n\tgpr += 2;\n\n\t/* Line2 Playback Volume */\n\tA_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);\n\tA_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++],\n\t\t\t\t\temu->card_capabilities->ac97_chip ? \"Line2 Playback Volume\" : \"Line Playback Volume\",\n\t\t\t\t\tgpr, 0);\n\tgpr += 2;\n\t/* Line2 Capture Volume */\n\tA_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);\n\tA_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++],\n\t\t\t\t\temu->card_capabilities->ac97_chip ? \"Line2 Capture Volume\" : \"Line Capture Volume\",\n\t\t\t\t\tgpr, 0);\n\tgpr += 2;\n        \n\t/* Philips ADC Playback Volume */\n\tA_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);\n\tA_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Analog Mix Playback Volume\", gpr, 0);\n\tgpr += 2;\n\t/* Philips ADC Capture Volume */\n\tA_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);\n\tA_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Analog Mix Capture Volume\", gpr, 0);\n\tgpr += 2;\n\n\t/* Aux2 Playback Volume */\n\tA_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);\n\tA_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++],\n\t\t\t\t\temu->card_capabilities->ac97_chip ? \"Aux2 Playback Volume\" : \"Aux Playback Volume\",\n\t\t\t\t\tgpr, 0);\n\tgpr += 2;\n\t/* Aux2 Capture Volume */\n\tA_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);\n\tA_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++],\n\t\t\t\t\temu->card_capabilities->ac97_chip ? \"Aux2 Capture Volume\" : \"Aux Capture Volume\",\n\t\t\t\t\tgpr, 0);\n\tgpr += 2;\n\t\n\t/* Stereo Mix Front Playback Volume */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Front Playback Volume\", gpr, 100);\n\tgpr += 2;\n\t\n\t/* Stereo Mix Surround Playback */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));\n\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Surround Playback Volume\", gpr, 0);\n\tgpr += 2;\n\n\t/* Stereo Mix Center Playback */\n\t/* Center = sub = Left/2 + Right/2 */\n\tA_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));\n\tsnd_emu10k1_init_mono_control(&controls[nctl++], \"Center Playback Volume\", gpr, 0);\n\tgpr++;\n\n\t/* Stereo Mix LFE Playback */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));\n\tsnd_emu10k1_init_mono_control(&controls[nctl++], \"LFE Playback Volume\", gpr, 0);\n\tgpr++;\n\t\n\tif (emu->card_capabilities->spk71) {\n\t\t/* Stereo Mix Side Playback */\n\t\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));\n\t\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));\n\t\tsnd_emu10k1_init_stereo_control(&controls[nctl++], \"Side Playback Volume\", gpr, 0);\n\t\tgpr += 2;\n\t}\n\n\t/*\n\t * outputs\n\t */\n#define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))\n#define A_PUT_STEREO_OUTPUT(out1,out2,src) \\\n\t{A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}\n\n#define _A_SWITCH(icode, ptr, dst, src, sw) \\\n\tA_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);\n#define A_SWITCH(icode, ptr, dst, src, sw) \\\n\t\t_A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))\n#define _A_SWITCH_NEG(icode, ptr, dst, src) \\\n\tA_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);\n#define A_SWITCH_NEG(icode, ptr, dst, src) \\\n\t\t_A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))\n\n\n\t/*\n\t *  Process tone control\n\t */\n\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */\n\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */\n\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */\n\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */\n\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */\n\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */\n\tif (emu->card_capabilities->spk71) {\n\t\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */\n\t\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */\n\t}\n\t\n\n\tctl = &controls[nctl + 0];\n\tctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;\n\tstrcpy(ctl->id.name, \"Tone Control - Bass\");\n\tctl->vcount = 2;\n\tctl->count = 10;\n\tctl->min = 0;\n\tctl->max = 40;\n\tctl->value[0] = ctl->value[1] = 20;\n\tctl->translation = EMU10K1_GPR_TRANSLATION_BASS;\n\tctl = &controls[nctl + 1];\n\tctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;\n\tstrcpy(ctl->id.name, \"Tone Control - Treble\");\n\tctl->vcount = 2;\n\tctl->count = 10;\n\tctl->min = 0;\n\tctl->max = 40;\n\tctl->value[0] = ctl->value[1] = 20;\n\tctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;\n\n#define BASS_GPR\t0x8c\n#define TREBLE_GPR\t0x96\n\n\tfor (z = 0; z < 5; z++) {\n\t\tint j;\n\t\tfor (j = 0; j < 2; j++) {\n\t\t\tcontrols[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;\n\t\t\tcontrols[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;\n\t\t}\n\t}\n\tfor (z = 0; z < 4; z++) {\t\t/* front/rear/center-lfe/side */\n\t\tint j, k, l, d;\n\t\tfor (j = 0; j < 2; j++) {\t/* left/right */\n\t\t\tk = 0xb0 + (z * 8) + (j * 4);\n\t\t\tl = 0xe0 + (z * 8) + (j * 4);\n\t\t\td = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;\n\n\t\t\tA_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));\n\t\t\tA_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));\n\t\t\tA_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));\n\t\t\tA_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));\n\t\t\tA_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);\n\n\t\t\tA_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));\n\t\t\tA_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));\n\t\t\tA_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));\n\t\t\tA_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));\n\t\t\tA_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));\n\t\t\tA_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);\n\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);\n\n\t\t\tif (z == 2)\t/* center */\n\t\t\t\tbreak;\n\t\t}\n\t}\n\tnctl += 2;\n\n#undef BASS_GPR\n#undef TREBLE_GPR\n\n\tfor (z = 0; z < 8; z++) {\n\t\tA_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);\n\t\tA_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);\n\t\tA_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);\n\t\tA_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);\n\t}\n\tsnd_emu10k1_init_stereo_onoff_control(controls + nctl++, \"Tone Control - Switch\", gpr, 0);\n\tgpr += 2;\n\n\t/* Master volume (will be renamed later) */\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tA_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));\n\tsnd_emu10k1_init_mono_control(&controls[nctl++], \"Wave Master Playback Volume\", gpr, 0);\n\tgpr += 2;\n\n\t/* analog speakers */\n\tA_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);\n\tA_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\tA_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\tA_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\tif (emu->card_capabilities->spk71)\n\t\tA_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\n\t/* headphone */\n\tA_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);\n\n\t/* digital outputs */\n\t/* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */\n\tif (emu->card_capabilities->emu_model) {\n\t\t/* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */\n\t\tdev_info(emu->card->dev, \"EMU outputs on\\n\");\n\t\tfor (z = 0; z < 8; z++) {\n\t\t\tif (emu->card_capabilities->ca0108_chip) {\n\t\t\t\tA_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);\n\t\t\t} else {\n\t\t\t\tA_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* IEC958 Optical Raw Playback Switch */ \n\tgpr_map[gpr++] = 0;\n\tgpr_map[gpr++] = 0x1008;\n\tgpr_map[gpr++] = 0xffff0000;\n\tfor (z = 0; z < 2; z++) {\n\t\tA_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);\n\t\tA_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);\n\t\tA_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));\n\t\tA_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);\n\t\tA_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);\n\t\tA_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);\n\t\tA_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);\n\t\tif ((z==1) && (emu->card_capabilities->spdif_bug)) {\n\t\t\t/* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */\n\t\t\tdev_info(emu->card->dev,\n\t\t\t\t \"Installing spdif_bug patch: %s\\n\",\n\t\t\t\t emu->card_capabilities->name);\n\t\t\tA_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);\n\t\t} else {\n\t\t\tA_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);\n\t\t}\n\t}\n\tsnd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958(\"Optical Raw \",PLAYBACK,SWITCH), gpr, 0);\n\tgpr += 2;\n\t\n\tA_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\tA_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\tA_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);\n\n\t/* ADC buffer */\n#ifdef EMU10K1_CAPTURE_DIGITAL_OUT\n\tA_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);\n#else\n\tA_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);\n\tA_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);\n#endif\n\n\tif (emu->card_capabilities->emu_model) {\n\t\tif (emu->card_capabilities->ca0108_chip) {\n\t\t\tdev_info(emu->card->dev, \"EMU2 inputs on\\n\");\n\t\t\tfor (z = 0; z < 0x10; z++) {\n\t\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, \n\t\t\t\t\t\t\t\t\tbit_shifter16,\n\t\t\t\t\t\t\t\t\tA3_EMU32IN(z),\n\t\t\t\t\t\t\t\t\tA_FXBUS2(z*2) );\n\t\t\t}\n\t\t} else {\n\t\t\tdev_info(emu->card->dev, \"EMU inputs on\\n\");\n\t\t\t/* Capture 16 (originally 8) channels of S32_LE sound */\n\n\t\t\t/*\n\t\t\tdev_dbg(emu->card->dev, \"emufx.c: gpr=0x%x, tmp=0x%x\\n\",\n\t\t\t       gpr, tmp);\n\t\t\t*/\n\t\t\t/* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */\n\t\t\t/* A_P16VIN(0) is delayed by one sample,\n\t\t\t * so all other A_P16VIN channels will need to also be delayed\n\t\t\t */\n\t\t\t/* Left ADC in. 1 of 2 */\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );\n\t\t\t/* Right ADC in 1 of 2 */\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\t/* Delaying by one sample: instead of copying the input\n\t\t\t * value A_P16VIN to output A_FXBUS2 as in the first channel,\n\t\t\t * we use an auxiliary register, delaying the value by one\n\t\t\t * sample\n\t\t\t */\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);\n\t\t\t/* For 96kHz mode */\n\t\t\t/* Left ADC in. 2 of 2 */\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);\n\t\t\t/* Right ADC in 2 of 2 */\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);\n\t\t\t/* Pavel Hofman - we still have voices, A_FXBUS2s, and\n\t\t\t * A_P16VINs available -\n\t\t\t * let's add 8 more capture channels - total of 16\n\t\t\t */\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x10));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x12));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x14));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x16));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x18));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x1a));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x1c));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t\tgpr_map[gpr++] = 0x00000000;\n\t\t\tsnd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,\n\t\t\t\t\t\t\t\t  bit_shifter16,\n\t\t\t\t\t\t\t\t  A_GPR(gpr - 1),\n\t\t\t\t\t\t\t\t  A_FXBUS2(0x1e));\n\t\t\tA_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),\n\t\t\t     A_C_00000000, A_C_00000000);\n\t\t}\n\n#if 0\n\t\tfor (z = 4; z < 8; z++) {\n\t\t\tA_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);\n\t\t}\n\t\tfor (z = 0xc; z < 0x10; z++) {\n\t\t\tA_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);\n\t\t}\n#endif\n\t} else {\n\t\t/* EFX capture - capture the 16 EXTINs */\n\t\t/* Capture 16 channels of S16_LE sound */\n\t\tfor (z = 0; z < 16; z++) {\n\t\t\tA_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));\n\t\t}\n\t}\n\t\n#endif /* JCD test */\n\t/*\n\t * ok, set up done..\n\t */\n\n\tif (gpr > tmp) {\n\t\tsnd_BUG();\n\t\terr = -EIO;\n\t\tgoto __err;\n\t}\n\t/* clear remaining instruction memory */\n\twhile (ptr < 0x400)\n\t\tA_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);\n\n\ticode->gpr_add_control_count = nctl;\n\ticode->gpr_add_controls = controls;\n\temu->support_tlv = 1; /* support TLV */\n\terr = snd_emu10k1_icode_poke(emu, icode, true);\n\temu->support_tlv = 0; /* clear again */\n\n__err:\n\tkfree(controls);\n__err_ctrls:\n\tkfree(icode->gpr_map);\n__err_gpr:\n\tkfree(icode);\n\treturn err;\n}",
        "static int __init czc_p10t_init(void)\n{\n\t/*\n\t * The device boots up in \"Windows 7\" mode, when the home button sends a\n\t * Windows specific key sequence (Left Meta + D) and the second button": "static int __init czc_p10t_init(void)\n{\n\t/*\n\t * The device boots up in \"Windows 7\" mode, when the home button sends a\n\t * Windows specific key sequence (Left Meta + D) and the second button\n\t * sends an unknown one while also toggling the Radio Kill Switch.\n\t * This is a surprising behavior when the second button is labeled \"Back\".\n\t *\n\t * The vendor-supplied Android-x86 build switches the device to a \"Android\"\n\t * mode by writing value 0x63 to the I/O port 0x68. This just seems to just\n\t * set bit 6 on address 0x96 in the EC region; switching the bit directly\n\t * seems to achieve the same result. It uses a \"p10t_switcher\" to do the\n\t * job. It doesn't seem to be able to do anything else, and no other use\n\t * of the port 0x68 is known.\n\t *\n\t * In the Android mode, the home button sends just a single scancode,\n\t * which can be handled in Linux userspace more reasonably and the back\n\t * button only sends a scancode without toggling the kill switch.\n\t * The scancode can then be mapped either to Back or RF Kill functionality\n\t * in userspace, depending on how the button is labeled on that particular\n\t * model.\n\t */\n\toutb(CZC_EC_ANDROID_KEYS, CZC_EC_EXTRA_PORT);\n\treturn 0;\n}",
        "static int aic_init_cpu(unsigned int cpu)\n{\n\t/* Mask all hard-wired per-CPU IRQ/FIQ sources */\n\n\t/* Pending Fast IPI FIQs */": "static int aic_init_cpu(unsigned int cpu)\n{\n\t/* Mask all hard-wired per-CPU IRQ/FIQ sources */\n\n\t/* Pending Fast IPI FIQs */\n\twrite_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1);\n\n\t/* Timer FIQs */\n\tsysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);\n\tsysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);\n\n\t/* EL2-only (VHE mode) IRQ sources */\n\tif (is_kernel_in_hyp_mode()) {\n\t\t/* Guest timers */\n\t\tsysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2,\n\t\t\t\t   VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);\n\n\t\t/* vGIC maintenance IRQ */\n\t\tsysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);\n\t}\n\n\t/* PMC FIQ */\n\tsysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,\n\t\t\t   FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF));\n\n\t/* Uncore PMC FIQ */\n\tsysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE,\n\t\t\t   FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF));\n\n\t/* Commit all of the above */\n\tisb();\n\n\tif (aic_irqc->info.version == 1) {\n\t\t/*\n\t\t * Make sure the kernel's idea of logical CPU order is the same as AIC's\n\t\t * If we ever end up with a mismatch here, we will have to introduce\n\t\t * a mapping table similar to what other irqchip drivers do.\n\t\t */\n\t\tWARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id());\n\n\t\t/*\n\t\t * Always keep IPIs unmasked at the hardware level (except auto-masking\n\t\t * by AIC during processing). We manage masks at the vIPI level.\n\t\t * These registers only exist on AICv1, AICv2 always uses fast IPIs.\n\t\t */\n\t\taic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_SELF | AIC_IPI_OTHER);\n\t\tif (static_branch_likely(&use_fast_ipi)) {\n\t\t\taic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER);\n\t\t} else {\n\t\t\taic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF);\n\t\t\taic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER);\n\t\t}\n\t}\n\n\t/* Initialize the local mask state */\n\t__this_cpu_write(aic_fiq_unmasked, 0);\n\n\treturn 0;\n}",
        "static inline int erase_block (__u32 offset)\n{\n   __u32 status;\n\n#ifdef LART_DEBUG": "static inline int erase_block (__u32 offset)\n{\n   __u32 status;\n\n#ifdef LART_DEBUG\n   printk (KERN_DEBUG \"%s(): 0x%.8x\\n\", __func__, offset);\n#endif\n\n   /* erase and confirm */\n   write32 (DATA_TO_FLASH (ERASE_SETUP),offset);\n   write32 (DATA_TO_FLASH (ERASE_CONFIRM),offset);\n\n   /* wait for block erase to finish */\n   do\n\t {\n\t\twrite32 (DATA_TO_FLASH (STATUS_READ),offset);\n\t\tstatus = FLASH_TO_DATA (read32 (offset));\n\t }\n   while ((~status & STATUS_BUSY) != 0);\n\n   /* put the flash back into command mode */\n   write32 (DATA_TO_FLASH (READ_ARRAY),offset);\n\n   /* was the erase successful? */\n   if ((status & STATUS_ERASE_ERR))\n\t {\n\t\tprintk (KERN_WARNING \"%s: erase error at address 0x%.8x.\\n\",module_name,offset);\n\t\treturn (0);\n\t }\n\n   return (1);\n}",
        "static void ae5_post_dsp_stream_setup(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);": "static void ae5_post_dsp_stream_setup(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);\n\n\tsnd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);\n\n\tchipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);\n\n\tchipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);\n\n\tchipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);\n\tchipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);\n\tchipio_set_stream_channels(codec, 0x18, 6);\n\tchipio_set_stream_control(codec, 0x18, 1);\n\n\tchipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);\n\n\tchipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);\n\n\tca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);\n\n\tmutex_unlock(&spec->chipio_mutex);\n}",
        "static int ni_expand_mft_list(struct ntfs_inode *ni)\n{\n\tint err = 0;\n\tstruct runs_tree *run = &ni->file.run;\n\tu32 asize, run_size, done = 0;": "static int ni_expand_mft_list(struct ntfs_inode *ni)\n{\n\tint err = 0;\n\tstruct runs_tree *run = &ni->file.run;\n\tu32 asize, run_size, done = 0;\n\tstruct ATTRIB *attr;\n\tstruct rb_node *node;\n\tCLST mft_min, mft_new, svcn, evcn, plen;\n\tstruct mft_inode *mi, *mi_min, *mi_new;\n\tstruct ntfs_sb_info *sbi = ni->mi.sbi;\n\n\t/* Find the nearest MFT. */\n\tmft_min = 0;\n\tmft_new = 0;\n\tmi_min = NULL;\n\n\tfor (node = rb_first(&ni->mi_tree); node; node = rb_next(node)) {\n\t\tmi = rb_entry(node, struct mft_inode, node);\n\n\t\tattr = mi_enum_attr(mi, NULL);\n\n\t\tif (!attr) {\n\t\t\tmft_min = mi->rno;\n\t\t\tmi_min = mi;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (ntfs_look_free_mft(sbi, &mft_new, true, ni, &mi_new)) {\n\t\tmft_new = 0;\n\t\t/* Really this is not critical. */\n\t} else if (mft_min > mft_new) {\n\t\tmft_min = mft_new;\n\t\tmi_min = mi_new;\n\t} else {\n\t\tntfs_mark_rec_free(sbi, mft_new);\n\t\tmft_new = 0;\n\t\tni_remove_mi(ni, mi_new);\n\t}\n\n\tattr = mi_find_attr(&ni->mi, NULL, ATTR_DATA, NULL, 0, NULL);\n\tif (!attr) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tasize = le32_to_cpu(attr->size);\n\n\tevcn = le64_to_cpu(attr->nres.evcn);\n\tsvcn = bytes_to_cluster(sbi, (u64)(mft_min + 1) << sbi->record_bits);\n\tif (evcn + 1 >= svcn) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * Split primary attribute [0 evcn] in two parts [0 svcn) + [svcn evcn].\n\t *\n\t * Update first part of ATTR_DATA in 'primary MFT.\n\t */\n\terr = run_pack(run, 0, svcn, Add2Ptr(attr, SIZEOF_NONRESIDENT),\n\t\t       asize - SIZEOF_NONRESIDENT, &plen);\n\tif (err < 0)\n\t\tgoto out;\n\n\trun_size = ALIGN(err, 8);\n\terr = 0;\n\n\tif (plen < svcn) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tattr->nres.evcn = cpu_to_le64(svcn - 1);\n\tattr->size = cpu_to_le32(run_size + SIZEOF_NONRESIDENT);\n\t/* 'done' - How many bytes of primary MFT becomes free. */\n\tdone = asize - run_size - SIZEOF_NONRESIDENT;\n\tle32_sub_cpu(&ni->mi.mrec->used, done);\n\n\t/* Estimate the size of second part: run_buf=NULL. */\n\terr = run_pack(run, svcn, evcn + 1 - svcn, NULL, sbi->record_size,\n\t\t       &plen);\n\tif (err < 0)\n\t\tgoto out;\n\n\trun_size = ALIGN(err, 8);\n\terr = 0;\n\n\tif (plen < evcn + 1 - svcn) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * This function may implicitly call expand attr_list.\n\t * Insert second part of ATTR_DATA in 'mi_min'.\n\t */\n\tattr = ni_ins_new_attr(ni, mi_min, NULL, ATTR_DATA, NULL, 0,\n\t\t\t       SIZEOF_NONRESIDENT + run_size,\n\t\t\t       SIZEOF_NONRESIDENT, svcn, NULL);\n\tif (!attr) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tattr->non_res = 1;\n\tattr->name_off = SIZEOF_NONRESIDENT_LE;\n\tattr->flags = 0;\n\n\trun_pack(run, svcn, evcn + 1 - svcn, Add2Ptr(attr, SIZEOF_NONRESIDENT),\n\t\t run_size, &plen);\n\n\tattr->nres.svcn = cpu_to_le64(svcn);\n\tattr->nres.evcn = cpu_to_le64(evcn);\n\tattr->nres.run_off = cpu_to_le16(SIZEOF_NONRESIDENT);\n\nout:\n\tif (mft_new) {\n\t\tntfs_mark_rec_free(sbi, mft_new);\n\t\tni_remove_mi(ni, mi_new);\n\t}\n\n\treturn !err && !done ? -EOPNOTSUPP : err;\n}",
        "static int ca0132_prepare_verbs(struct hda_codec *codec)\n{\n/* Verbs + terminator (an empty element) */\n#define NUM_SPEC_VERBS 2\n\tstruct ca0132_spec *spec = codec->spec;": "static int ca0132_prepare_verbs(struct hda_codec *codec)\n{\n/* Verbs + terminator (an empty element) */\n#define NUM_SPEC_VERBS 2\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tspec->chip_init_verbs = ca0132_init_verbs0;\n\t/*\n\t * Since desktop cards use pci_mmio, this can be used to determine\n\t * whether or not to use these verbs instead of a separate bool.\n\t */\n\tif (ca0132_use_pci_mmio(spec))\n\t\tspec->desktop_init_verbs = ca0132_init_verbs1;\n\tspec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,\n\t\t\t\t\tsizeof(struct hda_verb),\n\t\t\t\t\tGFP_KERNEL);\n\tif (!spec->spec_init_verbs)\n\t\treturn -ENOMEM;\n\n\t/* config EAPD */\n\tspec->spec_init_verbs[0].nid = 0x0b;\n\tspec->spec_init_verbs[0].param = 0x78D;\n\tspec->spec_init_verbs[0].verb = 0x00;\n\n\t/* Previously commented configuration */\n\t/*\n\tspec->spec_init_verbs[2].nid = 0x0b;\n\tspec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;\n\tspec->spec_init_verbs[2].verb = 0x02;\n\n\tspec->spec_init_verbs[3].nid = 0x10;\n\tspec->spec_init_verbs[3].param = 0x78D;\n\tspec->spec_init_verbs[3].verb = 0x02;\n\n\tspec->spec_init_verbs[4].nid = 0x10;\n\tspec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;\n\tspec->spec_init_verbs[4].verb = 0x02;\n\t*/\n\n\t/* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */\n\treturn 0;\n}",
        "static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dibx090p_best_adc *adc)\n{\n\tu8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;\n\n\tu16 xtal = 12000;": "static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dibx090p_best_adc *adc)\n{\n\tu8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;\n\n\tu16 xtal = 12000;\n\tu32 fcp_min = 1900;  /* PLL Minimum Frequency comparator KHz */\n\tu32 fcp_max = 20000; /* PLL Maximum Frequency comparator KHz */\n\tu32 fdem_max = 76000;\n\tu32 fdem_min = 69500;\n\tu32 fcp = 0, fs = 0, fdem = 0;\n\tu32 harmonic_id = 0;\n\n\tadc->pll_loopdiv = loopdiv;\n\tadc->pll_prediv = prediv;\n\tadc->timf = 0;\n\n\tdeb_info(\"bandwidth = %d fdem_min =%d\", fe->dtv_property_cache.bandwidth_hz, fdem_min);\n\n\t/* Find Min and Max prediv */\n\twhile ((xtal/max_prediv) >= fcp_min)\n\t\tmax_prediv++;\n\n\tmax_prediv--;\n\tmin_prediv = max_prediv;\n\twhile ((xtal/min_prediv) <= fcp_max) {\n\t\tmin_prediv--;\n\t\tif (min_prediv == 1)\n\t\t\tbreak;\n\t}\n\tdeb_info(\"MIN prediv = %d : MAX prediv = %d\", min_prediv, max_prediv);\n\n\tmin_prediv = 2;\n\n\tfor (prediv = min_prediv ; prediv < max_prediv; prediv++) {\n\t\tfcp = xtal / prediv;\n\t\tif (fcp > fcp_min && fcp < fcp_max) {\n\t\t\tfor (loopdiv = 1 ; loopdiv < 64 ; loopdiv++) {\n\t\t\t\tfdem = ((xtal/prediv) * loopdiv);\n\t\t\t\tfs   = fdem / 4;\n\t\t\t\t/* test min/max system restrictions */\n\n\t\t\t\tif ((fdem >= fdem_min) && (fdem <= fdem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz/1000)) {\n\t\t\t\t\tspur = 0;\n\t\t\t\t\t/* test fs harmonics positions */\n\t\t\t\t\tfor (harmonic_id = (fe->dtv_property_cache.frequency / (1000*fs)) ;  harmonic_id <= ((fe->dtv_property_cache.frequency / (1000*fs))+1) ; harmonic_id++) {\n\t\t\t\t\t\tif (((fs*harmonic_id) >= ((fe->dtv_property_cache.frequency/1000) - (fe->dtv_property_cache.bandwidth_hz/2000))) &&  ((fs*harmonic_id) <= ((fe->dtv_property_cache.frequency/1000) + (fe->dtv_property_cache.bandwidth_hz/2000)))) {\n\t\t\t\t\t\t\tspur = 1;\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif (!spur) {\n\t\t\t\t\t\tadc->pll_loopdiv = loopdiv;\n\t\t\t\t\t\tadc->pll_prediv = prediv;\n\t\t\t\t\t\tadc->timf = 2396745143UL/fdem*(1 << 9);\n\t\t\t\t\t\tadc->timf += ((2396745143UL%fdem) << 9)/fdem;\n\t\t\t\t\t\tdeb_info(\"loopdiv=%i prediv=%i timf=%i\", loopdiv, prediv, adc->timf);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (!spur)\n\t\t\tbreak;\n\t}\n\n\n\tif (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)\n\t\treturn -EINVAL;\n\telse\n\t\treturn 0;\n}",
        "static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, int id)\n{\n\tstruct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;\n\tu32 values[HDA_MAX_COMPONENTS];\n\tstruct acpi_device *adev;": "static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, int id)\n{\n\tstruct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;\n\tu32 values[HDA_MAX_COMPONENTS];\n\tstruct acpi_device *adev;\n\tstruct device *physdev;\n\tchar *property;\n\tsize_t nval;\n\tint i, ret;\n\n\tadev = acpi_dev_get_first_match_dev(hid, NULL, -1);\n\tif (!adev) {\n\t\tdev_err(cs35l41->dev, \"Failed to find an ACPI device for %s\\n\", hid);\n\t\treturn -ENODEV;\n\t}\n\n\tphysdev = get_device(acpi_get_first_physical_node(adev));\n\tacpi_dev_put(adev);\n\n\tproperty = \"cirrus,dev-index\";\n\tret = device_property_count_u32(physdev, property);\n\tif (ret <= 0)\n\t\tgoto no_acpi_dsd;\n\n\tif (ret > ARRAY_SIZE(values)) {\n\t\tret = -EINVAL;\n\t\tgoto err;\n\t}\n\tnval = ret;\n\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret)\n\t\tgoto err;\n\n\tcs35l41->index = -1;\n\tfor (i = 0; i < nval; i++) {\n\t\tif (values[i] == id) {\n\t\t\tcs35l41->index = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (cs35l41->index == -1) {\n\t\tdev_err(cs35l41->dev, \"No index found in %s\\n\", property);\n\t\tret = -ENODEV;\n\t\tgoto err;\n\t}\n\n\t/* To use the same release code for all laptop variants we can't use devm_ version of\n\t * gpiod_get here, as CLSA010* don't have a fully functional bios with an _DSD node\n\t */\n\tcs35l41->reset_gpio = fwnode_gpiod_get_index(&adev->fwnode, \"reset\", cs35l41->index,\n\t\t\t\t\t\t     GPIOD_OUT_LOW, \"cs35l41-reset\");\n\n\tproperty = \"cirrus,speaker-position\";\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret)\n\t\tgoto err;\n\thw_cfg->spk_pos = values[cs35l41->index];\n\n\tcs35l41->channel_index = 0;\n\tfor (i = 0; i < cs35l41->index; i++)\n\t\tif (values[i] == hw_cfg->spk_pos)\n\t\t\tcs35l41->channel_index++;\n\n\tproperty = \"cirrus,gpio1-func\";\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret)\n\t\tgoto err;\n\thw_cfg->gpio1.func = values[cs35l41->index];\n\thw_cfg->gpio1.valid = true;\n\n\tproperty = \"cirrus,gpio2-func\";\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret)\n\t\tgoto err;\n\thw_cfg->gpio2.func = values[cs35l41->index];\n\thw_cfg->gpio2.valid = true;\n\n\tproperty = \"cirrus,boost-peak-milliamp\";\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret == 0)\n\t\thw_cfg->bst_ipk = values[cs35l41->index];\n\telse\n\t\thw_cfg->bst_ipk = -1;\n\n\tproperty = \"cirrus,boost-ind-nanohenry\";\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret == 0)\n\t\thw_cfg->bst_ind = values[cs35l41->index];\n\telse\n\t\thw_cfg->bst_ind = -1;\n\n\tproperty = \"cirrus,boost-cap-microfarad\";\n\tret = device_property_read_u32_array(physdev, property, values, nval);\n\tif (ret == 0)\n\t\thw_cfg->bst_cap = values[cs35l41->index];\n\telse\n\t\thw_cfg->bst_cap = -1;\n\n\tif (hw_cfg->bst_ind > 0 || hw_cfg->bst_cap > 0 || hw_cfg->bst_ipk > 0)\n\t\thw_cfg->bst_type = CS35L41_INT_BOOST;\n\telse\n\t\thw_cfg->bst_type = CS35L41_EXT_BOOST;\n\n\thw_cfg->valid = true;\n\tput_device(physdev);\n\n\treturn 0;\n\nerr:\n\tput_device(physdev);\n\tdev_err(cs35l41->dev, \"Failed property %s: %d\\n\", property, ret);\n\n\treturn ret;\n\nno_acpi_dsd:\n\t/*\n\t * Device CLSA0100 doesn't have _DSD so a gpiod_get by the label reset won't work.\n\t * And devices created by i2c-multi-instantiate don't have their device struct pointing to\n\t * the correct fwnode, so acpi_dev must be used here.\n\t * And devm functions expect that the device requesting the resource has the correct\n\t * fwnode.\n\t */\n\tif (strncmp(hid, \"CLSA0100\", 8) != 0)\n\t\treturn -EINVAL;\n\n\t/* check I2C address to assign the index */\n\tcs35l41->index = id == 0x40 ? 0 : 1;\n\tcs35l41->hw_cfg.spk_pos = cs35l41->index;\n\tcs35l41->channel_index = 0;\n\tcs35l41->reset_gpio = gpiod_get_index(physdev, NULL, 0, GPIOD_OUT_HIGH);\n\tcs35l41->hw_cfg.bst_type = CS35L41_EXT_BOOST_NO_VSPK_SWITCH;\n\thw_cfg->gpio2.func = CS35L41_GPIO2_INT_OPEN_DRAIN;\n\thw_cfg->gpio2.valid = true;\n\tcs35l41->hw_cfg.valid = true;\n\tput_device(physdev);\n\n\treturn 0;\n}",
        "static int smcr_serv_conf_first_link(struct smc_sock *smc)\n{\n\tstruct smc_link *link = smc->conn.lnk;\n\tstruct smc_llc_qentry *qentry;\n\tint rc;": "static int smcr_serv_conf_first_link(struct smc_sock *smc)\n{\n\tstruct smc_link *link = smc->conn.lnk;\n\tstruct smc_llc_qentry *qentry;\n\tint rc;\n\n\tif (smcr_link_reg_rmb(link, smc->conn.rmb_desc))\n\t\treturn SMC_CLC_DECL_ERR_REGRMB;\n\n\t/* send CONFIRM LINK request to client over the RoCE fabric */\n\trc = smc_llc_send_confirm_link(link, SMC_LLC_REQ);\n\tif (rc < 0)\n\t\treturn SMC_CLC_DECL_TIMEOUT_CL;\n\n\t/* receive CONFIRM LINK response from client over the RoCE fabric */\n\tqentry = smc_llc_wait(link->lgr, link, SMC_LLC_WAIT_TIME,\n\t\t\t      SMC_LLC_CONFIRM_LINK);\n\tif (!qentry) {\n\t\tstruct smc_clc_msg_decline dclc;\n\n\t\trc = smc_clc_wait_msg(smc, &dclc, sizeof(dclc),\n\t\t\t\t      SMC_CLC_DECLINE, CLC_WAIT_TIME_SHORT);\n\t\treturn rc == -EAGAIN ? SMC_CLC_DECL_TIMEOUT_CL : rc;\n\t}\n\tsmc_llc_save_peer_uid(qentry);\n\trc = smc_llc_eval_conf_link(qentry, SMC_LLC_RESP);\n\tsmc_llc_flow_qentry_del(&link->lgr->llc_flow_lcl);\n\tif (rc)\n\t\treturn SMC_CLC_DECL_RMBE_EC;\n\n\t/* confirm_rkey is implicit on 1st contact */\n\tsmc->conn.rmb_desc->is_conf_rkey = true;\n\n\tsmc_llc_link_active(link);\n\tsmcr_lgr_set_type(link->lgr, SMC_LGR_SINGLE);\n\n\t/* initial contact - try to establish second link */\n\tsmc_llc_srv_add_link(link, NULL);\n\treturn 0;\n}",
        "static int jt8ew9_post_poweron(struct ccs_sensor *sensor)\n{\n\tstatic const struct ccs_reg_8 regs[] = {\n\t\t{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */\n\t\t{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */": "static int jt8ew9_post_poweron(struct ccs_sensor *sensor)\n{\n\tstatic const struct ccs_reg_8 regs[] = {\n\t\t{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */\n\t\t{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */\n\t\t{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */\n\t\t{ 0x322d, 0x04 }, /* Adjusting Processing Image Size to Scaler Toshiba Recommendation Setting */\n\t\t{ 0x3255, 0x0f }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */\n\t\t{ 0x3256, 0x15 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */\n\t\t{ 0x3258, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */\n\t\t{ 0x3259, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */\n\t\t{ 0x325f, 0x7c }, /* Analog Gain Control Toshiba Recommendation Setting */\n\t\t{ 0x3302, 0x06 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */\n\t\t{ 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */\n\t\t{ 0x3307, 0x22 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */\n\t\t{ 0x3308, 0x8d }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */\n\t\t{ 0x331e, 0x0f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */\n\t\t{ 0x3320, 0x30 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */\n\t\t{ 0x3321, 0x11 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */\n\t\t{ 0x3322, 0x98 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */\n\t\t{ 0x3323, 0x64 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */\n\t\t{ 0x3325, 0x83 }, /* Read Out Timing Control Toshiba Recommendation Setting */\n\t\t{ 0x3330, 0x18 }, /* Read Out Timing Control Toshiba Recommendation Setting */\n\t\t{ 0x333c, 0x01 }, /* Read Out Timing Control Toshiba Recommendation Setting */\n\t\t{ 0x3345, 0x2f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */\n\t\t{ 0x33de, 0x38 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */\n\t\t/* Taken from v03. No idea what the rest are. */\n\t\t{ 0x32e0, 0x05 },\n\t\t{ 0x32e1, 0x05 },\n\t\t{ 0x32e2, 0x04 },\n\t\t{ 0x32e5, 0x04 },\n\t\t{ 0x32e6, 0x04 },\n\n\t};\n\n\treturn ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));\n}",
        "static int receive_protocol(struct drbd_connection *connection, struct packet_info *pi)\n{\n\tstruct p_protocol *p = pi->data;\n\tenum drbd_after_sb_p p_after_sb_0p, p_after_sb_1p, p_after_sb_2p;\n\tint p_proto, p_discard_my_data, p_two_primaries, cf;": "static int receive_protocol(struct drbd_connection *connection, struct packet_info *pi)\n{\n\tstruct p_protocol *p = pi->data;\n\tenum drbd_after_sb_p p_after_sb_0p, p_after_sb_1p, p_after_sb_2p;\n\tint p_proto, p_discard_my_data, p_two_primaries, cf;\n\tstruct net_conf *nc, *old_net_conf, *new_net_conf = NULL;\n\tchar integrity_alg[SHARED_SECRET_MAX] = \"\";\n\tstruct crypto_shash *peer_integrity_tfm = NULL;\n\tvoid *int_dig_in = NULL, *int_dig_vv = NULL;\n\n\tp_proto\t\t= be32_to_cpu(p->protocol);\n\tp_after_sb_0p\t= be32_to_cpu(p->after_sb_0p);\n\tp_after_sb_1p\t= be32_to_cpu(p->after_sb_1p);\n\tp_after_sb_2p\t= be32_to_cpu(p->after_sb_2p);\n\tp_two_primaries = be32_to_cpu(p->two_primaries);\n\tcf\t\t= be32_to_cpu(p->conn_flags);\n\tp_discard_my_data = cf & CF_DISCARD_MY_DATA;\n\n\tif (connection->agreed_pro_version >= 87) {\n\t\tint err;\n\n\t\tif (pi->size > sizeof(integrity_alg))\n\t\t\treturn -EIO;\n\t\terr = drbd_recv_all(connection, integrity_alg, pi->size);\n\t\tif (err)\n\t\t\treturn err;\n\t\tintegrity_alg[SHARED_SECRET_MAX - 1] = 0;\n\t}\n\n\tif (pi->cmd != P_PROTOCOL_UPDATE) {\n\t\tclear_bit(CONN_DRY_RUN, &connection->flags);\n\n\t\tif (cf & CF_DRY_RUN)\n\t\t\tset_bit(CONN_DRY_RUN, &connection->flags);\n\n\t\trcu_read_lock();\n\t\tnc = rcu_dereference(connection->net_conf);\n\n\t\tif (p_proto != nc->wire_protocol) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"protocol\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\tif (convert_after_sb(p_after_sb_0p) != nc->after_sb_0p) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"after-sb-0pri\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\tif (convert_after_sb(p_after_sb_1p) != nc->after_sb_1p) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"after-sb-1pri\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\tif (convert_after_sb(p_after_sb_2p) != nc->after_sb_2p) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"after-sb-2pri\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\tif (p_discard_my_data && nc->discard_my_data) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"discard-my-data\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\tif (p_two_primaries != nc->two_primaries) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"allow-two-primaries\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\tif (strcmp(integrity_alg, nc->integrity_alg)) {\n\t\t\tdrbd_err(connection, \"incompatible %s settings\\n\", \"data-integrity-alg\");\n\t\t\tgoto disconnect_rcu_unlock;\n\t\t}\n\n\t\trcu_read_unlock();\n\t}\n\n\tif (integrity_alg[0]) {\n\t\tint hash_size;\n\n\t\t/*\n\t\t * We can only change the peer data integrity algorithm\n\t\t * here.  Changing our own data integrity algorithm\n\t\t * requires that we send a P_PROTOCOL_UPDATE packet at\n\t\t * the same time; otherwise, the peer has no way to\n\t\t * tell between which packets the algorithm should\n\t\t * change.\n\t\t */\n\n\t\tpeer_integrity_tfm = crypto_alloc_shash(integrity_alg, 0, 0);\n\t\tif (IS_ERR(peer_integrity_tfm)) {\n\t\t\tpeer_integrity_tfm = NULL;\n\t\t\tdrbd_err(connection, \"peer data-integrity-alg %s not supported\\n\",\n\t\t\t\t integrity_alg);\n\t\t\tgoto disconnect;\n\t\t}\n\n\t\thash_size = crypto_shash_digestsize(peer_integrity_tfm);\n\t\tint_dig_in = kmalloc(hash_size, GFP_KERNEL);\n\t\tint_dig_vv = kmalloc(hash_size, GFP_KERNEL);\n\t\tif (!(int_dig_in && int_dig_vv)) {\n\t\t\tdrbd_err(connection, \"Allocation of buffers for data integrity checking failed\\n\");\n\t\t\tgoto disconnect;\n\t\t}\n\t}\n\n\tnew_net_conf = kmalloc(sizeof(struct net_conf), GFP_KERNEL);\n\tif (!new_net_conf)\n\t\tgoto disconnect;\n\n\tmutex_lock(&connection->data.mutex);\n\tmutex_lock(&connection->resource->conf_update);\n\told_net_conf = connection->net_conf;\n\t*new_net_conf = *old_net_conf;\n\n\tnew_net_conf->wire_protocol = p_proto;\n\tnew_net_conf->after_sb_0p = convert_after_sb(p_after_sb_0p);\n\tnew_net_conf->after_sb_1p = convert_after_sb(p_after_sb_1p);\n\tnew_net_conf->after_sb_2p = convert_after_sb(p_after_sb_2p);\n\tnew_net_conf->two_primaries = p_two_primaries;\n\n\trcu_assign_pointer(connection->net_conf, new_net_conf);\n\tmutex_unlock(&connection->resource->conf_update);\n\tmutex_unlock(&connection->data.mutex);\n\n\tcrypto_free_shash(connection->peer_integrity_tfm);\n\tkfree(connection->int_dig_in);\n\tkfree(connection->int_dig_vv);\n\tconnection->peer_integrity_tfm = peer_integrity_tfm;\n\tconnection->int_dig_in = int_dig_in;\n\tconnection->int_dig_vv = int_dig_vv;\n\n\tif (strcmp(old_net_conf->integrity_alg, integrity_alg))\n\t\tdrbd_info(connection, \"peer data-integrity-alg: %s\\n\",\n\t\t\t  integrity_alg[0] ? integrity_alg : \"(none)\");\n\n\tkvfree_rcu(old_net_conf);\n\treturn 0;\n\ndisconnect_rcu_unlock:\n\trcu_read_unlock();\ndisconnect:\n\tcrypto_free_shash(peer_integrity_tfm);\n\tkfree(int_dig_in);\n\tkfree(int_dig_vv);\n\tconn_request_state(connection, NS(conn, C_DISCONNECTING), CS_HARD);\n\treturn -EIO;\n}",
        "static int helene_x_pon(struct helene_priv *priv)\n{\n\t/* RFIN matching in power save (terrestrial) = ACTIVE */\n\t/* RFIN matching in power save (satellite) = ACTIVE */\n\tu8 dataT[] = { 0x06, 0x00, 0x02, 0x00 };": "static int helene_x_pon(struct helene_priv *priv)\n{\n\t/* RFIN matching in power save (terrestrial) = ACTIVE */\n\t/* RFIN matching in power save (satellite) = ACTIVE */\n\tu8 dataT[] = { 0x06, 0x00, 0x02, 0x00 };\n\t/* SAT_RF_ACTIVE = true, lnaOff = false, terrRfActive = true */\n\tu8 dataS[] = { 0x05, 0x06 };\n\tu8 cdata[] = {0x7A, 0x01};\n\tu8 data[20];\n\tu8 rdata[2];\n\n\t/* mode select */\n\thelene_write_reg(priv, 0x01, 0x00);\n\n\thelene_write_reg(priv, 0x67, dataT[3]);\n\thelene_write_reg(priv, 0x43, dataS[1]);\n\thelene_write_regs(priv, 0x5E, dataT, 3);\n\thelene_write_reg(priv, 0x0C, dataS[0]);\n\n\t/* Initial setting for internal logic block */\n\thelene_write_regs(priv, 0x99, cdata, sizeof(cdata));\n\n\t/* 0x81 - 0x94 */\n\tif (priv->xtal == SONY_HELENE_XTAL_16000)\n\t\tdata[0] = 0x10; /* xtal 16 MHz */\n\telse\n\t\tdata[0] = 0x18; /* xtal 24 MHz */\n\tdata[1] = (uint8_t)(0x80 | (0x04 & 0x1F)); /* 4 x 25 = 100uA */\n\tdata[2] = (uint8_t)(0x80 | (0x26 & 0x7F)); /* 38 x 0.25 = 9.5pF */\n\tdata[3] = 0x80; /* REFOUT signal output 500mVpp */\n\tdata[4] = 0x00; /* GPIO settings */\n\tdata[5] = 0x00; /* GPIO settings */\n\tdata[6] = 0xC4; /* Clock enable for internal logic block */\n\tdata[7] = 0x40; /* Start CPU boot-up */\n\tdata[8] = 0x10; /* For burst-write */\n\n\t/* Setting for internal RFAGC */\n\tdata[9] = 0x00;\n\tdata[10] = 0x45;\n\tdata[11] = 0x75;\n\n\tdata[12] = 0x07; /* Setting for analog block */\n\n\t/* Initial setting for internal analog block */\n\tdata[13] = 0x1C;\n\tdata[14] = 0x3F;\n\tdata[15] = 0x02;\n\tdata[16] = 0x10;\n\tdata[17] = 0x20;\n\tdata[18] = 0x0A;\n\tdata[19] = 0x00;\n\n\thelene_write_regs(priv, 0x81, data, sizeof(data));\n\n\t/* Setting for internal RFAGC */\n\thelene_write_reg(priv, 0x9B, 0x00);\n\n\tmsleep(20);\n\n\t/* Check CPU_STT/CPU_ERR */\n\thelene_read_regs(priv, 0x1A, rdata, sizeof(rdata));\n\n\tif (rdata[0] != 0x00) {\n\t\tdev_err(&priv->i2c->dev,\n\t\t\t\t\"HELENE tuner CPU error 0x%x\\n\", rdata[0]);\n\t\treturn -EIO;\n\t}\n\n\t/* VCO current setting */\n\tcdata[0] = 0x90;\n\tcdata[1] = 0x06;\n\thelene_write_regs(priv, 0x17, cdata, sizeof(cdata));\n\tmsleep(20);\n\thelene_read_reg(priv, 0x19, data);\n\thelene_write_reg(priv, 0x95, (uint8_t)((data[0] >> 4) & 0x0F));\n\n\t/* Disable IF signal output */\n\thelene_write_reg(priv, 0x74, 0x02);\n\n\t/* Standby setting for CPU */\n\thelene_write_reg(priv, 0x88, 0x00);\n\n\t/* Standby setting for internal logic block */\n\thelene_write_reg(priv, 0x87, 0xC0);\n\n\t/* Load capacitance control setting for crystal oscillator */\n\thelene_write_reg(priv, 0x80, 0x01);\n\n\t/* Satellite initial setting */\n\tcdata[0] = 0x07;\n\tcdata[1] = 0x00;\n\thelene_write_regs(priv, 0x41, cdata, sizeof(cdata));\n\n\tdev_info(&priv->i2c->dev,\n\t\t\t\"HELENE tuner x_pon done\\n\");\n\n\treturn 0;\n}",
        "static int blinkm_transfer_hw(struct i2c_client *client, int cmd)\n{\n\t/* the protocol is simple but non-standard:\n\t * e.g.  cmd 'g' (= 0x67) for \"get device address\"\n\t * - which defaults to 0x09 - would be the sequence:": "static int blinkm_transfer_hw(struct i2c_client *client, int cmd)\n{\n\t/* the protocol is simple but non-standard:\n\t * e.g.  cmd 'g' (= 0x67) for \"get device address\"\n\t * - which defaults to 0x09 - would be the sequence:\n\t *   a) write 0x67 to the device (byte write)\n\t *   b) read the value (0x09) back right after (byte read)\n\t *\n\t * Watch out for \"unfinished\" sequences (i.e. not enough reads\n\t * or writes after a command. It will make the blinkM misbehave.\n\t * Sequence is key here.\n\t */\n\n\t/* args / return are in private data struct */\n\tstruct blinkm_data *data = i2c_get_clientdata(client);\n\n\t/* We start hardware transfers which are not to be\n\t * mixed with other commands. Aquire a lock now. */\n\tif (mutex_lock_interruptible(&data->update_lock) < 0)\n\t\treturn -EAGAIN;\n\n\t/* switch cmd - usually write before reads */\n\tswitch (cmd) {\n\tcase BLM_FADE_RAND_RGB:\n\tcase BLM_GO_RGB:\n\tcase BLM_FADE_RGB:\n\t\tdata->args[0] = data->next_red;\n\t\tdata->args[1] = data->next_green;\n\t\tdata->args[2] = data->next_blue;\n\t\tblinkm_write(client, cmd, data->args);\n\t\tdata->red = data->args[0];\n\t\tdata->green = data->args[1];\n\t\tdata->blue = data->args[2];\n\t\tbreak;\n\tcase BLM_FADE_HSB:\n\tcase BLM_FADE_RAND_HSB:\n\t\tdata->args[0] = data->next_hue;\n\t\tdata->args[1] = data->next_saturation;\n\t\tdata->args[2] = data->next_brightness;\n\t\tblinkm_write(client, cmd, data->args);\n\t\tdata->hue = data->next_hue;\n\t\tdata->saturation = data->next_saturation;\n\t\tdata->brightness = data->next_brightness;\n\t\tbreak;\n\tcase BLM_PLAY_SCRIPT:\n\t\tdata->args[0] = data->script_id;\n\t\tdata->args[1] = data->script_repeats;\n\t\tdata->args[2] = data->script_startline;\n\t\tblinkm_write(client, cmd, data->args);\n\t\tbreak;\n\tcase BLM_STOP_SCRIPT:\n\t\tblinkm_write(client, cmd, NULL);\n\t\tbreak;\n\tcase BLM_GET_CUR_RGB:\n\t\tdata->args[0] = data->red;\n\t\tdata->args[1] = data->green;\n\t\tdata->args[2] = data->blue;\n\t\tblinkm_write(client, cmd, NULL);\n\t\tblinkm_read(client, cmd, data->args);\n\t\tdata->red = data->args[0];\n\t\tdata->green = data->args[1];\n\t\tdata->blue = data->args[2];\n\t\tbreak;\n\tcase BLM_GET_ADDR:\n\t\tdata->args[0] = data->i2c_addr;\n\t\tblinkm_write(client, cmd, NULL);\n\t\tblinkm_read(client, cmd, data->args);\n\t\tdata->i2c_addr = data->args[0];\n\t\tbreak;\n\tcase BLM_SET_TIME_ADJ:\n\tcase BLM_SET_FADE_SPEED:\n\tcase BLM_READ_SCRIPT_LINE:\n\tcase BLM_WRITE_SCRIPT_LINE:\n\tcase BLM_SET_SCRIPT_LR:\n\tcase BLM_SET_ADDR:\n\tcase BLM_GET_FW_VER:\n\tcase BLM_SET_STARTUP_PARAM:\n\t\tdev_err(&client->dev,\n\t\t\t\t\"BlinkM: cmd %d not implemented yet.\\n\", cmd);\n\t\tbreak;\n\tdefault:\n\t\tdev_err(&client->dev, \"BlinkM: unknown command %d\\n\", cmd);\n\t\tmutex_unlock(&data->update_lock);\n\t\treturn -EINVAL;\n\t}\t\t\t/* end switch(cmd) */\n\n\t/* transfers done, unlock */\n\tmutex_unlock(&data->update_lock);\n\treturn 0;\n}",
        "static void atmel_pmecc_substitute(struct atmel_pmecc_user *user)\n{\n\tint degree = get_sectorsize(user) == 512 ? 13 : 14;\n\tint cw_len = BIT(degree) - 1;\n\tint strength = get_strength(user);": "static void atmel_pmecc_substitute(struct atmel_pmecc_user *user)\n{\n\tint degree = get_sectorsize(user) == 512 ? 13 : 14;\n\tint cw_len = BIT(degree) - 1;\n\tint strength = get_strength(user);\n\ts16 *alpha_to = user->gf_tables->alpha_to;\n\ts16 *index_of = user->gf_tables->index_of;\n\ts16 *partial_syn = user->partial_syn;\n\ts16 *si;\n\tint i, j;\n\n\t/*\n\t * si[] is a table that holds the current syndrome value,\n\t * an element of that table belongs to the field\n\t */\n\tsi = user->si;\n\n\tmemset(&si[1], 0, sizeof(s16) * ((2 * strength) - 1));\n\n\t/* Computation 2t syndromes based on S(x) */\n\t/* Odd syndromes */\n\tfor (i = 1; i < 2 * strength; i += 2) {\n\t\tfor (j = 0; j < degree; j++) {\n\t\t\tif (partial_syn[i] & BIT(j))\n\t\t\t\tsi[i] = alpha_to[i * j] ^ si[i];\n\t\t}\n\t}\n\t/* Even syndrome = (Odd syndrome) ** 2 */\n\tfor (i = 2, j = 1; j <= strength; i = ++j << 1) {\n\t\tif (si[j] == 0) {\n\t\t\tsi[i] = 0;\n\t\t} else {\n\t\t\ts16 tmp;\n\n\t\t\ttmp = index_of[si[j]];\n\t\t\ttmp = (tmp * 2) % cw_len;\n\t\t\tsi[i] = alpha_to[tmp];\n\t\t}\n\t}\n}",
        "static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)\n{\n\tint caps;\n\n\t/* CS8409 is simple HDA bridge and intended to be used with a remote": "static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)\n{\n\tint caps;\n\n\t/* CS8409 is simple HDA bridge and intended to be used with a remote\n\t * companion codec. Most of input/output PIN(s) have only basic\n\t * capabilities. Receive and Transmit NID(s) have only OUTC and INC\n\t * capabilities and no presence detect capable (PDC) and call to\n\t * snd_hda_gen_build_controls() will mark them as non detectable\n\t * phantom jacks. However, a companion codec may be\n\t * connected to these pins which supports jack detect\n\t * capabilities. We have to override pin capabilities,\n\t * otherwise they will not be created as input devices.\n\t */\n\tcaps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);\n\tif (caps >= 0)\n\t\tsnd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,\n\t\t\t\t       (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));\n\n\tsnd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));\n}",
        "static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tstruct drxj_data *ext_attr = demod->my_ext_attr;\n\tint rc;": "static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tstruct drxj_data *ext_attr = demod->my_ext_attr;\n\tint rc;\n\tu32 iqm_fs_rate_ofs = 0;\n\tu32 iqm_fs_rate_lo = 0;\n\tu16 qam_ctl_ena = 0;\n\tu16 data = 0;\n\tu16 equ_mode = 0;\n\tu16 fsm_state = 0;\n\tint i = 0;\n\tint ofsofs = 0;\n\n\t/* Silence the controlling of lc, equ, and the acquisition state machine */\n\trc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* freeze the frequency control loop */\n\trc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;\n\tiqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;\n\tiqm_fs_rate_ofs -= 2 * ofsofs;\n\n\t/* freeze dq/fq updating */\n\trc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tdata = (data & 0xfff9);\n\trc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* lc_cp / _ci / _ca */\n\trc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* flip the spec */\n\trc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\text_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;\n\text_attr->pos_image = (ext_attr->pos_image) ? false : true;\n\n\t/* freeze dq/fq updating */\n\trc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tequ_mode = data;\n\tdata = (data & 0xfff9);\n\trc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\tfor (i = 0; i < 28; i++) {\n\t\trc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\tfor (i = 0; i < 24; i++) {\n\t\trc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\tdata = equ_mode;\n\trc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\ti = 0;\n\twhile ((fsm_state != 4) && (i++ < 100)) {\n\t\trc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n\n}",
        "static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp;\n": "static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp;\n\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n\n\tchipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);\n\tchipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);\n\n\ttmp = FLOAT_THREE;\n\tdspio_set_uint_param(codec, 0x80, 0x00, tmp);\n\n\tchipio_set_stream_control(codec, 0x03, 1);\n\tchipio_set_stream_control(codec, 0x04, 1);\n\n\tswitch (ca0132_quirk(spec)) {\n\tcase QUIRK_SBZ:\n\t\tchipio_write(codec, 0x18b098, 0x0000000c);\n\t\tchipio_write(codec, 0x18b09C, 0x0000000c);\n\t\tbreak;\n\tcase QUIRK_AE5:\n\t\tchipio_write(codec, 0x18b098, 0x0000000c);\n\t\tchipio_write(codec, 0x18b09c, 0x0000004c);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}",
        "static int pvr2_enumaudio(struct file *file, void *priv, struct v4l2_audio *vin)\n{\n\t/* pkt: FIXME: We are returning one \"fake\" input here\n\t   which could very well be called \"whatever_we_like\".\n\t   This is for apps that want to see an audio input": "static int pvr2_enumaudio(struct file *file, void *priv, struct v4l2_audio *vin)\n{\n\t/* pkt: FIXME: We are returning one \"fake\" input here\n\t   which could very well be called \"whatever_we_like\".\n\t   This is for apps that want to see an audio input\n\t   just to feel comfortable, as well as to test if\n\t   it can do stereo or sth. There is actually no guarantee\n\t   that the actual audio input cannot change behind the app's\n\t   back, but most applications should not mind that either.\n\n\t   Hopefully, mplayer people will work with us on this (this\n\t   whole mess is to support mplayer pvr://), or Hans will come\n\t   up with a more standard way to say \"we have inputs but we\n\t   don 't want you to change them independent of video\" which\n\t   will sort this mess.\n\t */\n\n\tif (vin->index > 0)\n\t\treturn -EINVAL;\n\tstrscpy(vin->name, \"PVRUSB2 Audio\", sizeof(vin->name));\n\tvin->capability = V4L2_AUDCAP_STEREO;\n\treturn 0;\n}",
        "static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)\n{\n\tstruct mxic_ecc_engine *mxic = nand_to_mxic(nand);\n\tstruct nand_ecc_props *conf = &nand->ecc.ctx.conf;\n\tstruct nand_ecc_props *reqs = &nand->ecc.requirements;": "static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)\n{\n\tstruct mxic_ecc_engine *mxic = nand_to_mxic(nand);\n\tstruct nand_ecc_props *conf = &nand->ecc.ctx.conf;\n\tstruct nand_ecc_props *reqs = &nand->ecc.requirements;\n\tstruct nand_ecc_props *user = &nand->ecc.user_conf;\n\tstruct mtd_info *mtd = nanddev_to_mtd(nand);\n\tint step_size = 0, strength = 0, desired_correction = 0, steps, idx;\n\tstatic const int possible_strength[] = {4, 8, 40, 48};\n\tstatic const int spare_size[] = {32, 32, 96, 96};\n\tstruct mxic_ecc_ctx *ctx;\n\tu32 spare_reg;\n\tint ret;\n\n\tctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);\n\tif (!ctx)\n\t\treturn -ENOMEM;\n\n\tnand->ecc.ctx.priv = ctx;\n\n\t/* Only large page NAND chips may use BCH */\n\tif (mtd->oobsize < 64) {\n\t\tpr_err(\"BCH cannot be used with small page NAND chips\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tmtd_set_ooblayout(mtd, &mxic_ecc_ooblayout_ops);\n\n\t/* Enable all status bits */\n\twritel(TRANS_CMPLT | SDMA_MAIN | SDMA_SPARE | ECC_ERR |\n\t       TO_SPARE | TO_MAIN, mxic->regs + INTRPT_STS_EN);\n\n\t/* Configure the correction depending on the NAND device topology */\n\tif (user->step_size && user->strength) {\n\t\tstep_size = user->step_size;\n\t\tstrength = user->strength;\n\t} else if (reqs->step_size && reqs->strength) {\n\t\tstep_size = reqs->step_size;\n\t\tstrength = reqs->strength;\n\t}\n\n\tif (step_size && strength) {\n\t\tsteps = mtd->writesize / step_size;\n\t\tdesired_correction = steps * strength;\n\t}\n\n\t/* Step size is fixed to 1kiB, strength may vary (4 possible values) */\n\tconf->step_size = SZ_1K;\n\tsteps = mtd->writesize / conf->step_size;\n\n\tctx->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);\n\tif (!ctx->status)\n\t\treturn -ENOMEM;\n\n\tif (desired_correction) {\n\t\tstrength = desired_correction / steps;\n\n\t\tfor (idx = 0; idx < ARRAY_SIZE(possible_strength); idx++)\n\t\t\tif (possible_strength[idx] >= strength)\n\t\t\t\tbreak;\n\n\t\tidx = min_t(unsigned int, idx,\n\t\t\t    ARRAY_SIZE(possible_strength) - 1);\n\t} else {\n\t\t/* Missing data, maximize the correction */\n\t\tidx = ARRAY_SIZE(possible_strength) - 1;\n\t}\n\n\t/* Tune the selected strength until it fits in the OOB area */\n\tfor (; idx >= 0; idx--) {\n\t\tif (spare_size[idx] * steps <= mtd->oobsize)\n\t\t\tbreak;\n\t}\n\n\t/* This engine cannot be used with this NAND device */\n\tif (idx < 0)\n\t\treturn -EINVAL;\n\n\t/* Configure the engine for the desired strength */\n\twritel(ECC_TYP(idx), mxic->regs + DP_CONFIG);\n\tconf->strength = possible_strength[idx];\n\tspare_reg = readl(mxic->regs + SPARE_SIZE);\n\n\tctx->steps = steps;\n\tctx->data_step_sz = mtd->writesize / steps;\n\tctx->oob_step_sz = mtd->oobsize / steps;\n\tctx->parity_sz = PARITY_SZ(spare_reg);\n\tctx->meta_sz = META_SZ(spare_reg);\n\n\t/* Ensure buffers will contain enough bytes to store the STAT_BYTES */\n\tctx->req_ctx.oob_buffer_size = nanddev_per_page_oobsize(nand) +\n\t\t\t\t\t(ctx->steps * STAT_BYTES);\n\tret = nand_ecc_init_req_tweaking(&ctx->req_ctx, nand);\n\tif (ret)\n\t\treturn ret;\n\n\tctx->oobwithstat = kmalloc(mtd->oobsize + (ctx->steps * STAT_BYTES),\n\t\t\t\t   GFP_KERNEL);\n\tif (!ctx->oobwithstat) {\n\t\tret = -ENOMEM;\n\t\tgoto cleanup_req_tweak;\n\t}\n\n\tsg_init_table(ctx->sg, 2);\n\n\t/* Configuration dump and sanity checks */\n\tdev_err(dev, \"DPE version number: %d\\n\",\n\t\treadl(mxic->regs + DP_VER) >> DP_VER_OFFSET);\n\tdev_err(dev, \"Chunk size: %d\\n\", readl(mxic->regs + CHUNK_SIZE));\n\tdev_err(dev, \"Main size: %d\\n\", readl(mxic->regs + MAIN_SIZE));\n\tdev_err(dev, \"Spare size: %d\\n\", SPARE_SZ(spare_reg));\n\tdev_err(dev, \"Rsv size: %ld\\n\", RSV_SZ(spare_reg));\n\tdev_err(dev, \"Parity size: %d\\n\", ctx->parity_sz);\n\tdev_err(dev, \"Meta size: %d\\n\", ctx->meta_sz);\n\n\tif ((ctx->meta_sz + ctx->parity_sz + RSV_SZ(spare_reg)) !=\n\t    SPARE_SZ(spare_reg)) {\n\t\tdev_err(dev, \"Wrong OOB configuration: %d + %d + %ld != %d\\n\",\n\t\t\tctx->meta_sz, ctx->parity_sz, RSV_SZ(spare_reg),\n\t\t\tSPARE_SZ(spare_reg));\n\t\tret = -EINVAL;\n\t\tgoto free_oobwithstat;\n\t}\n\n\tif (ctx->oob_step_sz != SPARE_SZ(spare_reg)) {\n\t\tdev_err(dev, \"Wrong OOB configuration: %d != %d\\n\",\n\t\t\tctx->oob_step_sz, SPARE_SZ(spare_reg));\n\t\tret = -EINVAL;\n\t\tgoto free_oobwithstat;\n\t}\n\n\treturn 0;\n\nfree_oobwithstat:\n\tkfree(ctx->oobwithstat);\ncleanup_req_tweak:\n\tnand_ecc_cleanup_req_tweaking(&ctx->req_ctx);\n\n\treturn ret;\n}",
        "static int t7xx_dpmaif_rx_alloc(struct dpmaif_rx_queue *rxq)\n{\n\trxq->pit_size_cnt = DPMAIF_PIT_COUNT;\n\trxq->pit_rd_idx = 0;\n\trxq->pit_wr_idx = 0;": "static int t7xx_dpmaif_rx_alloc(struct dpmaif_rx_queue *rxq)\n{\n\trxq->pit_size_cnt = DPMAIF_PIT_COUNT;\n\trxq->pit_rd_idx = 0;\n\trxq->pit_wr_idx = 0;\n\trxq->pit_release_rd_idx = 0;\n\trxq->expect_pit_seq = 0;\n\trxq->pit_remain_release_cnt = 0;\n\tmemset(&rxq->rx_data_info, 0, sizeof(rxq->rx_data_info));\n\n\trxq->pit_base = dma_alloc_coherent(rxq->dpmaif_ctrl->dev,\n\t\t\t\t\t   rxq->pit_size_cnt * sizeof(struct dpmaif_pit),\n\t\t\t\t\t   &rxq->pit_bus_addr, GFP_KERNEL | __GFP_ZERO);\n\tif (!rxq->pit_base)\n\t\treturn -ENOMEM;\n\n\trxq->bat_req = &rxq->dpmaif_ctrl->bat_req;\n\tatomic_inc(&rxq->bat_req->refcnt);\n\n\trxq->bat_frag = &rxq->dpmaif_ctrl->bat_frag;\n\tatomic_inc(&rxq->bat_frag->refcnt);\n\treturn 0;\n}",
        "static int get_device_capabilities(struct drx_demod_instance *demod)\n{\n\tstruct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);\n\tstruct drxj_data *ext_attr = (struct drxj_data *) NULL;\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);": "static int get_device_capabilities(struct drx_demod_instance *demod)\n{\n\tstruct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);\n\tstruct drxj_data *ext_attr = (struct drxj_data *) NULL;\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tu16 sio_pdr_ohw_cfg = 0;\n\tu32 sio_top_jtagid_lo = 0;\n\tu16 bid = 0;\n\tint rc;\n\n\tcommon_attr = (struct drx_common_attr *) demod->my_common_attr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\tdev_addr = demod->my_i2c_dev_addr;\n\n\trc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\tswitch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {\n\tcase 0:\n\t\t/* ignore (bypass ?) */\n\t\tbreak;\n\tcase 1:\n\t\t/* 27 MHz */\n\t\tcommon_attr->osc_clock_freq = 27000;\n\t\tbreak;\n\tcase 2:\n\t\t/* 20.25 MHz */\n\t\tcommon_attr->osc_clock_freq = 20250;\n\t\tbreak;\n\tcase 3:\n\t\t/* 4 MHz */\n\t\tcommon_attr->osc_clock_freq = 4000;\n\t\tbreak;\n\tdefault:\n\t\treturn -EIO;\n\t}\n\n\t/*\n\t   Determine device capabilities\n\t   Based on pinning v47\n\t */\n\trc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\text_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);\n\n\tswitch ((sio_top_jtagid_lo >> 12) & 0xFF) {\n\tcase 0x31:\n\t\trc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tbid = (bid >> 10) & 0xf;\n\t\trc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\n\t\text_attr->has_lna = true;\n\t\text_attr->has_ntsc = false;\n\t\text_attr->has_btsc = false;\n\t\text_attr->has_oob = false;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = false;\n\t\text_attr->has_gpio = false;\n\t\text_attr->has_irqn = false;\n\t\tbreak;\n\tcase 0x33:\n\t\text_attr->has_lna = false;\n\t\text_attr->has_ntsc = false;\n\t\text_attr->has_btsc = false;\n\t\text_attr->has_oob = false;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = false;\n\t\text_attr->has_gpio = false;\n\t\text_attr->has_irqn = false;\n\t\tbreak;\n\tcase 0x45:\n\t\text_attr->has_lna = true;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = false;\n\t\text_attr->has_oob = false;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = false;\n\t\tbreak;\n\tcase 0x46:\n\t\text_attr->has_lna = false;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = false;\n\t\text_attr->has_oob = false;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = false;\n\t\tbreak;\n\tcase 0x41:\n\t\text_attr->has_lna = true;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = true;\n\t\text_attr->has_oob = false;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = false;\n\t\tbreak;\n\tcase 0x43:\n\t\text_attr->has_lna = false;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = true;\n\t\text_attr->has_oob = false;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = false;\n\t\tbreak;\n\tcase 0x32:\n\t\text_attr->has_lna = true;\n\t\text_attr->has_ntsc = false;\n\t\text_attr->has_btsc = false;\n\t\text_attr->has_oob = true;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = true;\n\t\tbreak;\n\tcase 0x34:\n\t\text_attr->has_lna = false;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = true;\n\t\text_attr->has_oob = true;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = true;\n\t\tbreak;\n\tcase 0x42:\n\t\text_attr->has_lna = true;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = true;\n\t\text_attr->has_oob = true;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = true;\n\t\tbreak;\n\tcase 0x44:\n\t\text_attr->has_lna = false;\n\t\text_attr->has_ntsc = true;\n\t\text_attr->has_btsc = true;\n\t\text_attr->has_oob = true;\n\t\text_attr->has_smatx = true;\n\t\text_attr->has_smarx = true;\n\t\text_attr->has_gpio = true;\n\t\text_attr->has_irqn = true;\n\t\tbreak;\n\tdefault:\n\t\t/* Unknown device variant */\n\t\treturn -EIO;\n\t\tbreak;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void csd_lock_print_extended(struct __call_single_data *csd, int cpu)\n{\n\tstruct cfd_seq_local *seq = &per_cpu(cfd_seq_local, cpu);\n\tunsigned int srccpu = csd->node.src;\n\tstruct call_function_data *cfd = per_cpu_ptr(&cfd_data, srccpu);": "static void csd_lock_print_extended(struct __call_single_data *csd, int cpu)\n{\n\tstruct cfd_seq_local *seq = &per_cpu(cfd_seq_local, cpu);\n\tunsigned int srccpu = csd->node.src;\n\tstruct call_function_data *cfd = per_cpu_ptr(&cfd_data, srccpu);\n\tstruct cfd_percpu *pcpu = per_cpu_ptr(cfd->pcpu, cpu);\n\tunsigned int now;\n\tunion cfd_seq_cnt data[2 * ARRAY_SIZE(seq_type)];\n\tunsigned int n_data = 0, i;\n\n\tdata[0].val = READ_ONCE(cfd_seq);\n\tnow = data[0].u.cnt;\n\n\tcfd_seq_data_add(pcpu->seq_queue,\t\t\tsrccpu, cpu,\t       CFD_SEQ_QUEUE,  data, &n_data, now);\n\tcfd_seq_data_add(pcpu->seq_ipi,\t\t\t\tsrccpu, cpu,\t       CFD_SEQ_IPI,    data, &n_data, now);\n\tcfd_seq_data_add(pcpu->seq_noipi,\t\t\tsrccpu, cpu,\t       CFD_SEQ_NOIPI,  data, &n_data, now);\n\n\tcfd_seq_data_add(per_cpu(cfd_seq_local.ping, srccpu),\tsrccpu, CFD_SEQ_NOCPU, CFD_SEQ_PING,   data, &n_data, now);\n\tcfd_seq_data_add(per_cpu(cfd_seq_local.pinged, srccpu), srccpu, CFD_SEQ_NOCPU, CFD_SEQ_PINGED, data, &n_data, now);\n\n\tcfd_seq_data_add(seq->idle,    CFD_SEQ_NOCPU, cpu, CFD_SEQ_IDLE,    data, &n_data, now);\n\tcfd_seq_data_add(seq->gotipi,  CFD_SEQ_NOCPU, cpu, CFD_SEQ_GOTIPI,  data, &n_data, now);\n\tcfd_seq_data_add(seq->handle,  CFD_SEQ_NOCPU, cpu, CFD_SEQ_HANDLE,  data, &n_data, now);\n\tcfd_seq_data_add(seq->dequeue, CFD_SEQ_NOCPU, cpu, CFD_SEQ_DEQUEUE, data, &n_data, now);\n\tcfd_seq_data_add(seq->hdlend,  CFD_SEQ_NOCPU, cpu, CFD_SEQ_HDLEND,  data, &n_data, now);\n\n\tfor (i = 0; i < n_data; i++) {\n\t\tpr_alert(\"\\tcsd: cnt(%07x): %04x->%04x %s\\n\",\n\t\t\t data[i].u.cnt & ~0x80000000U, data[i].u.src,\n\t\t\t data[i].u.dst, csd_lock_get_type(data[i].u.type));\n\t}\n\tpr_alert(\"\\tcsd: cnt now: %07x\\n\", now);\n}",
        "static void rxrpc_set_rto(struct rxrpc_peer *peer)\n{\n\tu32 rto;\n\n\t/* 1. If rtt variance happened to be less 50msec, it is hallucination.": "static void rxrpc_set_rto(struct rxrpc_peer *peer)\n{\n\tu32 rto;\n\n\t/* 1. If rtt variance happened to be less 50msec, it is hallucination.\n\t *    It cannot be less due to utterly erratic ACK generation made\n\t *    at least by solaris and freebsd. \"Erratic ACKs\" has _nothing_\n\t *    to do with delayed acks, because at cwnd>2 true delack timeout\n\t *    is invisible. Actually, Linux-2.4 also generates erratic\n\t *    ACKs in some circumstances.\n\t */\n\trto = __rxrpc_set_rto(peer);\n\n\t/* 2. Fixups made earlier cannot be right.\n\t *    If we do not estimate RTO correctly without them,\n\t *    all the algo is pure shit and should be replaced\n\t *    with correct one. It is exactly, which we pretend to do.\n\t */\n\n\t/* NOTE: clamping at RXRPC_RTO_MIN is not required, current algo\n\t * guarantees that rto is higher.\n\t */\n\tpeer->rto_j = rxrpc_bound_rto(rto);\n}",
        "static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)\n{\n\tstruct cs8409_spec *spec = codec->spec;\n\tstruct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];\n\tstruct hda_jack_tbl *jk;": "static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)\n{\n\tstruct cs8409_spec *spec = codec->spec;\n\tstruct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];\n\tstruct hda_jack_tbl *jk;\n\n\t/* jack_unsol_event() will be called every time gpio line changing state.\n\t * In this case gpio4 line goes up as a result of reading interrupt status\n\t * registers in previous cs8409_jack_unsol_event() call.\n\t * We don't need to handle this event, ignoring...\n\t */\n\tif (res & cs42l42->irq_mask)\n\t\treturn;\n\n\tif (cs42l42_jack_unsol_event(cs42l42)) {\n\t\tsnd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,\n\t\t\t\t    cs42l42->hp_jack_in ? 0 : PIN_OUT);\n\t\t/* Report jack*/\n\t\tjk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);\n\t\tif (jk)\n\t\t\tsnd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &\n\t\t\t\t\t\t\tAC_UNSOL_RES_TAG);\n\t\t/* Report jack*/\n\t\tjk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);\n\t\tif (jk)\n\t\t\tsnd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &\n\t\t\t\t\t\t\t AC_UNSOL_RES_TAG);\n\t}\n}",
        "static void *syscall__augmented_args(struct syscall *sc, struct perf_sample *sample, int *augmented_args_size, int raw_augmented_args_size)\n{\n\tvoid *augmented_args = NULL;\n\t/*\n\t * For now with BPF raw_augmented we hook into raw_syscalls:sys_enter": "static void *syscall__augmented_args(struct syscall *sc, struct perf_sample *sample, int *augmented_args_size, int raw_augmented_args_size)\n{\n\tvoid *augmented_args = NULL;\n\t/*\n\t * For now with BPF raw_augmented we hook into raw_syscalls:sys_enter\n\t * and there we get all 6 syscall args plus the tracepoint common fields\n\t * that gets calculated at the start and the syscall_nr (another long).\n\t * So we check if that is the case and if so don't look after the\n\t * sc->args_size but always after the full raw_syscalls:sys_enter payload,\n\t * which is fixed.\n\t *\n\t * We'll revisit this later to pass s->args_size to the BPF augmenter\n\t * (now tools/perf/examples/bpf/augmented_raw_syscalls.c, so that it\n\t * copies only what we need for each syscall, like what happens when we\n\t * use syscalls:sys_enter_NAME, so that we reduce the kernel/userspace\n\t * traffic to just what is needed for each syscall.\n\t */\n\tint args_size = raw_augmented_args_size ?: sc->args_size;\n\n\t*augmented_args_size = sample->raw_size - args_size;\n\tif (*augmented_args_size > 0)\n\t\taugmented_args = sample->raw_data + args_size;\n\n\treturn augmented_args;\n}",
        "static void ca0132_alt_init_analog_mics(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp;\n": "static void ca0132_alt_init_analog_mics(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp;\n\n\t/* Mic 1 Setup */\n\tchipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);\n\tchipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);\n\tif (ca0132_quirk(spec) == QUIRK_R3DI) {\n\t\tchipio_set_conn_rate(codec, 0x0F, SR_96_000);\n\t\ttmp = FLOAT_ONE;\n\t} else\n\t\ttmp = FLOAT_THREE;\n\tdspio_set_uint_param(codec, 0x80, 0x00, tmp);\n\n\t/* Mic 2 setup (not present on desktop cards) */\n\tchipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);\n\tchipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);\n\tif (ca0132_quirk(spec) == QUIRK_R3DI)\n\t\tchipio_set_conn_rate(codec, 0x0F, SR_96_000);\n\ttmp = FLOAT_ZERO;\n\tdspio_set_uint_param(codec, 0x80, 0x01, tmp);\n}",
        "static void tcp_set_rto(struct sock *sk)\n{\n\tconst struct tcp_sock *tp = tcp_sk(sk);\n\t/* Old crap is replaced with new one. 8)\n\t *": "static void tcp_set_rto(struct sock *sk)\n{\n\tconst struct tcp_sock *tp = tcp_sk(sk);\n\t/* Old crap is replaced with new one. 8)\n\t *\n\t * More seriously:\n\t * 1. If rtt variance happened to be less 50msec, it is hallucination.\n\t *    It cannot be less due to utterly erratic ACK generation made\n\t *    at least by solaris and freebsd. \"Erratic ACKs\" has _nothing_\n\t *    to do with delayed acks, because at cwnd>2 true delack timeout\n\t *    is invisible. Actually, Linux-2.4 also generates erratic\n\t *    ACKs in some circumstances.\n\t */\n\tinet_csk(sk)->icsk_rto = __tcp_set_rto(tp);\n\n\t/* 2. Fixups made earlier cannot be right.\n\t *    If we do not estimate RTO correctly without them,\n\t *    all the algo is pure shit and should be replaced\n\t *    with correct one. It is exactly, which we pretend to do.\n\t */\n\n\t/* NOTE: clamping at TCP_RTO_MIN is not required, current algo\n\t * guarantees that rto is higher.\n\t */\n\ttcp_bound_rto(sk);\n}",
        "static int runtestsingle(int readwriteflag, int exclude_user, int arraytest)\n{\n\tint i,j;\n\tsize_t res;\n\tunsigned long long breaks, needed;": "static int runtestsingle(int readwriteflag, int exclude_user, int arraytest)\n{\n\tint i,j;\n\tsize_t res;\n\tunsigned long long breaks, needed;\n\tint readint;\n\tint readintarraybig[2*DAWR_LENGTH_MAX/sizeof(int)];\n\tint *readintalign;\n\tvolatile int *ptr;\n\tint break_fd;\n\tint loop_num = MAX_LOOPS - (rand() % 100); /* provide some variability */\n\tvolatile int *k;\n\t__u64 len;\n\n\t/* align to 0x400 boundary as required by DAWR */\n\treadintalign = (int *)(((unsigned long)readintarraybig + 0x7ff) &\n\t\t\t       0xfffffffffffff800);\n\n\tptr = &readint;\n\tif (arraytest)\n\t\tptr = &readintalign[0];\n\n\tlen = arraytest ? DAWR_LENGTH_MAX : sizeof(int);\n\tbreak_fd = perf_process_event_open_exclude_user(readwriteflag, (__u64)ptr,\n\t\t\t\t\t\t\tlen, exclude_user);\n\tif (break_fd < 0) {\n\t\tperror(\"perf_process_event_open_exclude_user\");\n\t\texit(1);\n\t}\n\n\t/* start counters */\n\tioctl(break_fd, PERF_EVENT_IOC_ENABLE);\n\n\t/* Test a bunch of reads and writes */\n\tk = &readint;\n\tfor (i = 0; i < loop_num; i++) {\n\t\tif (arraytest)\n\t\t\tk = &(readintalign[i % (DAWR_LENGTH_MAX/sizeof(int))]);\n\n\t\tj = *k;\n\t\t*k = j;\n\t}\n\n\t/* stop counters */\n\tioctl(break_fd, PERF_EVENT_IOC_DISABLE);\n\n\t/* read and check counters */\n\tres = read(break_fd, &breaks, sizeof(unsigned long long));\n\tassert(res == sizeof(unsigned long long));\n\t/* we read and write each loop, so subtract the ones we are counting */\n\tneeded = 0;\n\tif (readwriteflag & HW_BREAKPOINT_R)\n\t\tneeded += loop_num;\n\tif (readwriteflag & HW_BREAKPOINT_W)\n\t\tneeded += loop_num;\n\tneeded = needed * (1 - exclude_user);\n\tprintf(\"TESTED: addr:0x%lx brks:% 8lld loops:% 8i rw:%i !user:%i array:%i\\n\",\n\t       (unsigned long int)ptr, breaks, loop_num, readwriteflag, exclude_user, arraytest);\n\tif (breaks != needed) {\n\t\tprintf(\"FAILED: 0x%lx brks:%lld needed:%lli %i %i %i\\n\\n\",\n\t\t       (unsigned long int)ptr, breaks, needed, loop_num, readwriteflag, exclude_user);\n\t\treturn 1;\n\t}\n\tclose(break_fd);\n\n\treturn 0;\n}",
        "static bool rt1316_readable_register(struct device *dev, unsigned int reg)\n{\n\tswitch (reg) {\n\tcase 0x2f0a:\n\tcase 0x2f36:": "static bool rt1316_readable_register(struct device *dev, unsigned int reg)\n{\n\tswitch (reg) {\n\tcase 0x2f0a:\n\tcase 0x2f36:\n\tcase 0x3203 ... 0x320e:\n\tcase 0xc000 ... 0xc7b4:\n\tcase 0xcf00 ... 0xcf03:\n\tcase 0xd101 ... 0xd103:\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L):\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R):\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):\n\tcase SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):\n\t\treturn true;\n\tdefault:\n\t\treturn false;\n\t}\n}",
        "static int btf_dump_order_type(struct btf_dump *d, __u32 id, bool through_ptr)\n{\n\t/*\n\t * Order state is used to detect strong link cycles, but only for BTF\n\t * kinds that are or could be an independent definition (i.e.,": "static int btf_dump_order_type(struct btf_dump *d, __u32 id, bool through_ptr)\n{\n\t/*\n\t * Order state is used to detect strong link cycles, but only for BTF\n\t * kinds that are or could be an independent definition (i.e.,\n\t * stand-alone fwd decl, enum, typedef, struct, union). Ptrs, arrays,\n\t * func_protos, modifiers are just means to get to these definitions.\n\t * Int/void don't need definitions, they are assumed to be always\n\t * properly defined.  We also ignore datasec, var, and funcs for now.\n\t * So for all non-defining kinds, we never even set ordering state,\n\t * for defining kinds we set ORDERING and subsequently ORDERED if it\n\t * forms a strong link.\n\t */\n\tstruct btf_dump_type_aux_state *tstate = &d->type_states[id];\n\tconst struct btf_type *t;\n\t__u16 vlen;\n\tint err, i;\n\n\t/* return true, letting typedefs know that it's ok to be emitted */\n\tif (tstate->order_state == ORDERED)\n\t\treturn 1;\n\n\tt = btf__type_by_id(d->btf, id);\n\n\tif (tstate->order_state == ORDERING) {\n\t\t/* type loop, but resolvable through fwd declaration */\n\t\tif (btf_is_composite(t) && through_ptr && t->name_off != 0)\n\t\t\treturn 0;\n\t\tpr_warn(\"unsatisfiable type cycle, id:[%u]\\n\", id);\n\t\treturn -ELOOP;\n\t}\n\n\tswitch (btf_kind(t)) {\n\tcase BTF_KIND_INT:\n\tcase BTF_KIND_FLOAT:\n\t\ttstate->order_state = ORDERED;\n\t\treturn 0;\n\n\tcase BTF_KIND_PTR:\n\t\terr = btf_dump_order_type(d, t->type, true);\n\t\ttstate->order_state = ORDERED;\n\t\treturn err;\n\n\tcase BTF_KIND_ARRAY:\n\t\treturn btf_dump_order_type(d, btf_array(t)->type, false);\n\n\tcase BTF_KIND_STRUCT:\n\tcase BTF_KIND_UNION: {\n\t\tconst struct btf_member *m = btf_members(t);\n\t\t/*\n\t\t * struct/union is part of strong link, only if it's embedded\n\t\t * (so no ptr in a path) or it's anonymous (so has to be\n\t\t * defined inline, even if declared through ptr)\n\t\t */\n\t\tif (through_ptr && t->name_off != 0)\n\t\t\treturn 0;\n\n\t\ttstate->order_state = ORDERING;\n\n\t\tvlen = btf_vlen(t);\n\t\tfor (i = 0; i < vlen; i++, m++) {\n\t\t\terr = btf_dump_order_type(d, m->type, false);\n\t\t\tif (err < 0)\n\t\t\t\treturn err;\n\t\t}\n\n\t\tif (t->name_off != 0) {\n\t\t\terr = btf_dump_add_emit_queue_id(d, id);\n\t\t\tif (err < 0)\n\t\t\t\treturn err;\n\t\t}\n\n\t\ttstate->order_state = ORDERED;\n\t\treturn 1;\n\t}\n\tcase BTF_KIND_ENUM:\n\tcase BTF_KIND_FWD:\n\t\t/*\n\t\t * non-anonymous or non-referenced enums are top-level\n\t\t * declarations and should be emitted. Same logic can be\n\t\t * applied to FWDs, it won't hurt anyways.\n\t\t */\n\t\tif (t->name_off != 0 || !tstate->referenced) {\n\t\t\terr = btf_dump_add_emit_queue_id(d, id);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\t\ttstate->order_state = ORDERED;\n\t\treturn 1;\n\n\tcase BTF_KIND_TYPEDEF: {\n\t\tint is_strong;\n\n\t\tis_strong = btf_dump_order_type(d, t->type, through_ptr);\n\t\tif (is_strong < 0)\n\t\t\treturn is_strong;\n\n\t\t/* typedef is similar to struct/union w.r.t. fwd-decls */\n\t\tif (through_ptr && !is_strong)\n\t\t\treturn 0;\n\n\t\t/* typedef is always a named definition */\n\t\terr = btf_dump_add_emit_queue_id(d, id);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\td->type_states[id].order_state = ORDERED;\n\t\treturn 1;\n\t}\n\tcase BTF_KIND_VOLATILE:\n\tcase BTF_KIND_CONST:\n\tcase BTF_KIND_RESTRICT:\n\tcase BTF_KIND_TYPE_TAG:\n\t\treturn btf_dump_order_type(d, t->type, through_ptr);\n\n\tcase BTF_KIND_FUNC_PROTO: {\n\t\tconst struct btf_param *p = btf_params(t);\n\t\tbool is_strong;\n\n\t\terr = btf_dump_order_type(d, t->type, through_ptr);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\tis_strong = err > 0;\n\n\t\tvlen = btf_vlen(t);\n\t\tfor (i = 0; i < vlen; i++, p++) {\n\t\t\terr = btf_dump_order_type(d, p->type, through_ptr);\n\t\t\tif (err < 0)\n\t\t\t\treturn err;\n\t\t\tif (err > 0)\n\t\t\t\tis_strong = true;\n\t\t}\n\t\treturn is_strong;\n\t}\n\tcase BTF_KIND_FUNC:\n\tcase BTF_KIND_VAR:\n\tcase BTF_KIND_DATASEC:\n\tcase BTF_KIND_DECL_TAG:\n\t\td->type_states[id].order_state = ORDERED;\n\t\treturn 0;\n\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n}",
        "static void pr_ibs_op_data3(union ibs_op_data3 reg)\n{\n\tchar l2_miss_str[sizeof(\" L2Miss _\")] = \"\";\n\tchar op_mem_width_str[sizeof(\" OpMemWidth _____ bytes\")] = \"\";\n\tchar op_dc_miss_open_mem_reqs_str[sizeof(\" OpDcMissOpenMemReqs __\")] = \"\";": "static void pr_ibs_op_data3(union ibs_op_data3 reg)\n{\n\tchar l2_miss_str[sizeof(\" L2Miss _\")] = \"\";\n\tchar op_mem_width_str[sizeof(\" OpMemWidth _____ bytes\")] = \"\";\n\tchar op_dc_miss_open_mem_reqs_str[sizeof(\" OpDcMissOpenMemReqs __\")] = \"\";\n\n\t/*\n\t * Erratum #1293\n\t * Ignore L2Miss and OpDcMissOpenMemReqs (and opdata2) if DcMissNoMabAlloc or SwPf set\n\t */\n\tif (!(cpu_family == 0x19 && cpu_model < 0x10 && (reg.dc_miss_no_mab_alloc || reg.sw_pf))) {\n\t\tsnprintf(l2_miss_str, sizeof(l2_miss_str), \" L2Miss %d\", reg.l2_miss);\n\t\tsnprintf(op_dc_miss_open_mem_reqs_str, sizeof(op_dc_miss_open_mem_reqs_str),\n\t\t\t \" OpDcMissOpenMemReqs %2d\", reg.op_dc_miss_open_mem_reqs);\n\t}\n\n\tif (reg.op_mem_width)\n\t\tsnprintf(op_mem_width_str, sizeof(op_mem_width_str),\n\t\t\t \" OpMemWidth %2d bytes\", 1 << (reg.op_mem_width - 1));\n\n\tprintf(\"ibs_op_data3:\\t%016llx LdOp %d StOp %d DcL1TlbMiss %d DcL2TlbMiss %d \"\n\t\t\"DcL1TlbHit2M %d DcL1TlbHit1G %d DcL2TlbHit2M %d DcMiss %d DcMisAcc %d \"\n\t\t\"DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d \"\n\t\t\"DcPhyAddrValid %d DcL2TlbHit1G %d%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d\\n\",\n\t\treg.val, reg.ld_op, reg.st_op, reg.dc_l1tlb_miss, reg.dc_l2tlb_miss,\n\t\treg.dc_l1tlb_hit_2m, reg.dc_l1tlb_hit_1g, reg.dc_l2tlb_hit_2m, reg.dc_miss,\n\t\treg.dc_mis_acc, reg.dc_wc_mem_acc, reg.dc_uc_mem_acc, reg.dc_locked_op,\n\t\treg.dc_miss_no_mab_alloc, reg.dc_lin_addr_valid, reg.dc_phy_addr_valid,\n\t\treg.dc_l2_tlb_hit_1g, l2_miss_str, reg.sw_pf, op_mem_width_str,\n\t\top_dc_miss_open_mem_reqs_str, reg.dc_miss_lat, reg.tlb_refill_lat);\n}",
        "static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)\n{\n\tint ret = _SUCCESS;\n\n\tu32 blockSize_p1 = 4; /*  (Default) Phase #1 : PCI muse use 4-byte write to download FW */": "static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)\n{\n\tint ret = _SUCCESS;\n\n\tu32 blockSize_p1 = 4; /*  (Default) Phase #1 : PCI muse use 4-byte write to download FW */\n\tu32 blockSize_p2 = 8; /*  Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */\n\tu32 blockSize_p3 = 1; /*  Phase #3 : Use 1-byte, the remnant of FW image. */\n\tu32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;\n\tu32 remainSize_p1 = 0, remainSize_p2 = 0;\n\tu8 *bufferPtr = buffer;\n\tu32 i = 0, offset = 0;\n\n/* \tprintk(\"====>%s %d\\n\", __func__, __LINE__); */\n\n\t/* 3 Phase #1 */\n\tblockCount_p1 = buffSize / blockSize_p1;\n\tremainSize_p1 = buffSize % blockSize_p1;\n\n\tfor (i = 0; i < blockCount_p1; i++) {\n\t\tret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1)));\n\t\tif (ret == _FAIL) {\n\t\t\tprintk(\"====>%s %d i:%d\\n\", __func__, __LINE__, i);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t/* 3 Phase #2 */\n\tif (remainSize_p1) {\n\t\toffset = blockCount_p1 * blockSize_p1;\n\n\t\tblockCount_p2 = remainSize_p1/blockSize_p2;\n\t\tremainSize_p2 = remainSize_p1%blockSize_p2;\n\t}\n\n\t/* 3 Phase #3 */\n\tif (remainSize_p2) {\n\t\toffset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);\n\n\t\tblockCount_p3 = remainSize_p2 / blockSize_p3;\n\n\t\tfor (i = 0; i < blockCount_p3; i++) {\n\t\t\tret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));\n\n\t\t\tif (ret == _FAIL) {\n\t\t\t\tprintk(\"====>%s %d i:%d\\n\", __func__, __LINE__, i);\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\nexit:\n\treturn ret;\n}",
        "static void amp_voyetra(struct snd_cs46xx *chip, int change)\n{\n\t/* Manage the EAPD bit on the Crystal 4297 \n\t   and the Analog AD1885 */\n\t   ": "static void amp_voyetra(struct snd_cs46xx *chip, int change)\n{\n\t/* Manage the EAPD bit on the Crystal 4297 \n\t   and the Analog AD1885 */\n\t   \n#ifdef CONFIG_SND_CS46XX_NEW_DSP\n\tint old = chip->amplifier;\n#endif\n\tint oval, val;\n\t\n\tchip->amplifier += change;\n\toval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,\n\t\t\t\t     CS46XX_PRIMARY_CODEC_INDEX);\n\tval = oval;\n\tif (chip->amplifier) {\n\t\t/* Turn the EAPD amp on */\n\t\tval |= 0x8000;\n\t} else {\n\t\t/* Turn the EAPD amp off */\n\t\tval &= ~0x8000;\n\t}\n\tif (val != oval) {\n\t\tsnd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,\n\t\t\t\t       CS46XX_PRIMARY_CODEC_INDEX);\n\t\tif (chip->eapd_switch)\n\t\t\tsnd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,\n\t\t\t\t       &chip->eapd_switch->id);\n\t}\n\n#ifdef CONFIG_SND_CS46XX_NEW_DSP\n\tif (chip->amplifier && !old) {\n\t\tvoyetra_setup_eapd_slot(chip);\n\t}\n#endif\n}",
        "static int t7xx_dpmaif_init_intr(struct dpmaif_hw_info *hw_info)\n{\n\tstruct dpmaif_isr_en_mask *isr_en_msk = &hw_info->isr_en_mask;\n\tu32 value, ul_intr_enable, dl_intr_enable;\n\tint ret;": "static int t7xx_dpmaif_init_intr(struct dpmaif_hw_info *hw_info)\n{\n\tstruct dpmaif_isr_en_mask *isr_en_msk = &hw_info->isr_en_mask;\n\tu32 value, ul_intr_enable, dl_intr_enable;\n\tint ret;\n\n\tul_intr_enable = DP_UL_INT_ERR_MSK | DP_UL_INT_QDONE_MSK;\n\tisr_en_msk->ap_ul_l2intr_en_msk = ul_intr_enable;\n\tiowrite32(DPMAIF_AP_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_L2TISAR0);\n\n\t/* Set interrupt enable mask */\n\tiowrite32(ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMCR0);\n\tiowrite32(~ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMSR0);\n\n\t/* Check mask status */\n\tret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0,\n\t\t\t\t\t   value, (value & ul_intr_enable) != ul_intr_enable, 0,\n\t\t\t\t\t   DPMAIF_CHECK_INIT_TIMEOUT_US);\n\tif (ret)\n\t\treturn ret;\n\n\tdl_intr_enable = DP_DL_INT_PITCNT_LEN_ERR | DP_DL_INT_BATCNT_LEN_ERR;\n\tisr_en_msk->ap_dl_l2intr_err_en_msk = dl_intr_enable;\n\tul_intr_enable = DPMAIF_DL_INT_DLQ0_QDONE | DPMAIF_DL_INT_DLQ0_PITCNT_LEN |\n\t\t    DPMAIF_DL_INT_DLQ1_QDONE | DPMAIF_DL_INT_DLQ1_PITCNT_LEN;\n\tisr_en_msk->ap_ul_l2intr_en_msk = ul_intr_enable;\n\tiowrite32(DPMAIF_AP_APDL_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0);\n\n\t/* Set DL ISR PD enable mask */\n\tiowrite32(~ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0);\n\tret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMR0,\n\t\t\t\t\t   value, (value & ul_intr_enable) != ul_intr_enable, 0,\n\t\t\t\t\t   DPMAIF_CHECK_INIT_TIMEOUT_US);\n\tif (ret)\n\t\treturn ret;\n\n\tisr_en_msk->ap_udl_ip_busy_en_msk = DPMAIF_UDL_IP_BUSY;\n\tiowrite32(DPMAIF_AP_IP_BUSY_MASK, hw_info->pcie_base + DPMAIF_AP_IP_BUSY);\n\tiowrite32(isr_en_msk->ap_udl_ip_busy_en_msk,\n\t\t  hw_info->pcie_base + DPMAIF_AO_AP_DLUL_IP_BUSY_MASK);\n\tvalue = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0);\n\tvalue |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1;\n\tiowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0);\n\tiowrite32(DPMA_HPC_ALL_INT_MASK, hw_info->pcie_base + DPMAIF_HPC_INTR_MASK);\n\n\treturn 0;\n}",
        "static int hwlat_mode_open(struct inode *inode, struct file *file)\n{\n\treturn seq_open(file, &thread_mode_seq_ops);\n};\n": "static int hwlat_mode_open(struct inode *inode, struct file *file)\n{\n\treturn seq_open(file, &thread_mode_seq_ops);\n};\n\nstatic void hwlat_tracer_start(struct trace_array *tr);\nstatic void hwlat_tracer_stop(struct trace_array *tr);\n\n/**\n * hwlat_mode_write - Write function for \"mode\" entry\n * @filp: The active open file structure\n * @ubuf: The user buffer that contains the value to write\n * @cnt: The maximum number of bytes to write to \"file\"\n * @ppos: The current position in @file\n *\n * This function provides a write implementation for the \"mode\" interface\n * to the hardware latency detector. hwlatd has different operation modes.\n * The \"none\" sets the allowed cpumask for a single hwlatd thread at the\n * startup and lets the scheduler handle the migration. The default mode is\n * the \"round-robin\" one, in which a single hwlatd thread runs, migrating\n * among the allowed CPUs in a round-robin fashion. The \"per-cpu\" mode\n * creates one hwlatd thread per allowed CPU.\n */\nstatic ssize_t hwlat_mode_write(struct file *filp, const char __user *ubuf,\n\t\t\t\t size_t cnt, loff_t *ppos)\n{\n\tstruct trace_array *tr = hwlat_trace;\n\tconst char *mode;\n\tchar buf[64];\n\tint ret, i;\n\n\tif (cnt >= sizeof(buf))\n\t\treturn -EINVAL;\n\n\tif (copy_from_user(buf, ubuf, cnt))\n\t\treturn -EFAULT;\n\n\tbuf[cnt] = 0;\n\n\tmode = strstrip(buf);\n\n\tret = -EINVAL;\n\n\t/*\n\t * trace_types_lock is taken to avoid concurrency on start/stop\n\t * and hwlat_busy.\n\t */\n\tmutex_lock(&trace_types_lock);\n\tif (hwlat_busy)\n\t\thwlat_tracer_stop(tr);\n\n\tmutex_lock(&hwlat_data.lock);\n\n\tfor (i = 0; i < MODE_MAX; i++) {\n\t\tif (strcmp(mode, thread_mode_str[i]) == 0) {\n\t\t\thwlat_data.thread_mode = i;\n\t\t\tret = cnt;\n\t\t}\n\t}\n\n\tmutex_unlock(&hwlat_data.lock);\n\n\tif (hwlat_busy)\n\t\thwlat_tracer_start(tr);\n\tmutex_unlock(&trace_types_lock);\n\n\t*ppos += cnt;\n\n\n\n\treturn ret;\n}",
        "static void ae5_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n": "static void ae5_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n\n\tca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);\n\tca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);\n\tca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);\n\tca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);\n\tca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);\n\tca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);\n\tca0113_mmio_gpio_set(codec, 0, false);\n\tca0113_mmio_gpio_set(codec, 1, false);\n\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);\n\n\tchipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);\n\n\tchipio_set_stream_control(codec, 0x18, 0);\n\tchipio_set_stream_control(codec, 0x0c, 0);\n\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);\n}",
        "static void config_probs(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)\n{\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tstruct hantro_aux_buf *misc = &vp9_ctx->misc;\n\tstruct hantro_g2_all_probs *all_probs = misc->cpu;": "static void config_probs(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)\n{\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tstruct hantro_aux_buf *misc = &vp9_ctx->misc;\n\tstruct hantro_g2_all_probs *all_probs = misc->cpu;\n\tstruct hantro_g2_probs *adaptive;\n\tstruct hantro_g2_mv_probs *mv;\n\tconst struct v4l2_vp9_segmentation *seg = &dec_params->seg;\n\tconst struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables;\n\tint i, j, k, l, m;\n\n\tfor (i = 0; i < ARRAY_SIZE(all_probs->kf_y_mode_prob); ++i)\n\t\tfor (j = 0; j < ARRAY_SIZE(all_probs->kf_y_mode_prob[0]); ++j) {\n\t\t\tmemcpy(all_probs->kf_y_mode_prob[i][j],\n\t\t\t       v4l2_vp9_kf_y_mode_prob[i][j],\n\t\t\t       ARRAY_SIZE(all_probs->kf_y_mode_prob[i][j]));\n\n\t\t\tall_probs->kf_y_mode_prob_tail[i][j][0] =\n\t\t\t\tv4l2_vp9_kf_y_mode_prob[i][j][8];\n\t\t}\n\n\tmemcpy(all_probs->mb_segment_tree_probs, seg->tree_probs,\n\t       sizeof(all_probs->mb_segment_tree_probs));\n\n\tmemcpy(all_probs->segment_pred_probs, seg->pred_probs,\n\t       sizeof(all_probs->segment_pred_probs));\n\n\tfor (i = 0; i < ARRAY_SIZE(all_probs->kf_uv_mode_prob); ++i) {\n\t\tmemcpy(all_probs->kf_uv_mode_prob[i], v4l2_vp9_kf_uv_mode_prob[i],\n\t\t       ARRAY_SIZE(all_probs->kf_uv_mode_prob[i]));\n\n\t\tall_probs->kf_uv_mode_prob_tail[i][0] = v4l2_vp9_kf_uv_mode_prob[i][8];\n\t}\n\n\tadaptive = &all_probs->probs;\n\n\tfor (i = 0; i < ARRAY_SIZE(adaptive->inter_mode); ++i) {\n\t\tmemcpy(adaptive->inter_mode[i], probs->inter_mode[i],\n\t\t       ARRAY_SIZE(probs->inter_mode[i]));\n\n\t\tadaptive->inter_mode[i][3] = 0;\n\t}\n\n\tmemcpy(adaptive->is_inter, probs->is_inter, sizeof(adaptive->is_inter));\n\n\tfor (i = 0; i < ARRAY_SIZE(adaptive->uv_mode); ++i) {\n\t\tmemcpy(adaptive->uv_mode[i], probs->uv_mode[i],\n\t\t       sizeof(adaptive->uv_mode[i]));\n\t\tadaptive->uv_mode_tail[i][0] = probs->uv_mode[i][8];\n\t}\n\n\tmemcpy(adaptive->tx8, probs->tx8, sizeof(adaptive->tx8));\n\tmemcpy(adaptive->tx16, probs->tx16, sizeof(adaptive->tx16));\n\tmemcpy(adaptive->tx32, probs->tx32, sizeof(adaptive->tx32));\n\n\tfor (i = 0; i < ARRAY_SIZE(adaptive->y_mode); ++i) {\n\t\tmemcpy(adaptive->y_mode[i], probs->y_mode[i],\n\t\t       ARRAY_SIZE(adaptive->y_mode[i]));\n\n\t\tadaptive->y_mode_tail[i][0] = probs->y_mode[i][8];\n\t}\n\n\tfor (i = 0; i < ARRAY_SIZE(adaptive->partition[0]); ++i) {\n\t\tmemcpy(adaptive->partition[0][i], v4l2_vp9_kf_partition_probs[i],\n\t\t       sizeof(v4l2_vp9_kf_partition_probs[i]));\n\n\t\tadaptive->partition[0][i][3] = 0;\n\t}\n\n\tfor (i = 0; i < ARRAY_SIZE(adaptive->partition[1]); ++i) {\n\t\tmemcpy(adaptive->partition[1][i], probs->partition[i],\n\t\t       sizeof(probs->partition[i]));\n\n\t\tadaptive->partition[1][i][3] = 0;\n\t}\n\n\tmemcpy(adaptive->interp_filter, probs->interp_filter,\n\t       sizeof(adaptive->interp_filter));\n\n\tmemcpy(adaptive->comp_mode, probs->comp_mode, sizeof(adaptive->comp_mode));\n\n\tmemcpy(adaptive->skip, probs->skip, sizeof(adaptive->skip));\n\n\tmv = &adaptive->mv;\n\n\tmemcpy(mv->joint, probs->mv.joint, sizeof(mv->joint));\n\tmemcpy(mv->sign, probs->mv.sign, sizeof(mv->sign));\n\tmemcpy(mv->class0_bit, probs->mv.class0_bit, sizeof(mv->class0_bit));\n\tmemcpy(mv->fr, probs->mv.fr, sizeof(mv->fr));\n\tmemcpy(mv->class0_hp, probs->mv.class0_hp, sizeof(mv->class0_hp));\n\tmemcpy(mv->hp, probs->mv.hp, sizeof(mv->hp));\n\tmemcpy(mv->classes, probs->mv.classes, sizeof(mv->classes));\n\tmemcpy(mv->class0_fr, probs->mv.class0_fr, sizeof(mv->class0_fr));\n\tmemcpy(mv->bits, probs->mv.bits, sizeof(mv->bits));\n\n\tmemcpy(adaptive->single_ref, probs->single_ref, sizeof(adaptive->single_ref));\n\n\tmemcpy(adaptive->comp_ref, probs->comp_ref, sizeof(adaptive->comp_ref));\n\n\tfor (i = 0; i < ARRAY_SIZE(adaptive->coef); ++i)\n\t\tfor (j = 0; j < ARRAY_SIZE(adaptive->coef[0]); ++j)\n\t\t\tfor (k = 0; k < ARRAY_SIZE(adaptive->coef[0][0]); ++k)\n\t\t\t\tfor (l = 0; l < ARRAY_SIZE(adaptive->coef[0][0][0]); ++l)\n\t\t\t\t\tINNER_LOOP;\n\n\thantro_write_addr(ctx->dev, G2_VP9_PROBS_ADDR, misc->dma);\n}",
        "static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)\n{\n\t/* Reconfig pool mac ram */\n\tdib9000_write_word(state, 1225, 0x02);\t/* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */\n\tdib9000_write_word(state, 1226, 0x05);": "static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)\n{\n\t/* Reconfig pool mac ram */\n\tdib9000_write_word(state, 1225, 0x02);\t/* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */\n\tdib9000_write_word(state, 1226, 0x05);\n\n\t/* Toggles IP crypto to Host APB interface. */\n\tdib9000_write_word(state, 1542, 1);\n\n\t/* Set jump and no jump in the dma box */\n\tdib9000_write_word(state, 1074, 0);\n\tdib9000_write_word(state, 1075, 0);\n\n\t/* Set MAC as APB Master. */\n\tdib9000_write_word(state, 1237, 0);\n\n\t/* Reset the RISCs */\n\tif (codeA != NULL)\n\t\tdib9000_write_word(state, 1024, 2);\n\telse\n\t\tdib9000_write_word(state, 1024, 15);\n\tif (codeB != NULL)\n\t\tdib9000_write_word(state, 1040, 2);\n\n\tif (codeA != NULL)\n\t\tdib9000_firmware_download(state, 0, 0x1234, codeA, lenA);\n\tif (codeB != NULL)\n\t\tdib9000_firmware_download(state, 1, 0x1234, codeB, lenB);\n\n\t/* Run the RISCs */\n\tif (codeA != NULL)\n\t\tdib9000_write_word(state, 1024, 0);\n\tif (codeB != NULL)\n\t\tdib9000_write_word(state, 1040, 0);\n\n\tif (codeA != NULL)\n\t\tif (dib9000_mbx_host_init(state, 0) != 0)\n\t\t\treturn -EIO;\n\tif (codeB != NULL)\n\t\tif (dib9000_mbx_host_init(state, 1) != 0)\n\t\t\treturn -EIO;\n\n\tmsleep(100);\n\tstate->platform.risc.fw_is_running = 1;\n\n\tif (dib9000_risc_check_version(state) != 0)\n\t\treturn -EINVAL;\n\n\tstate->platform.risc.memcmd = 0xff;\n\treturn 0;\n}",
        "static void test_sockmap(unsigned int tasks, void *data)\n{\n\tstruct bpf_map *bpf_map_rx, *bpf_map_tx, *bpf_map_msg, *bpf_map_break;\n\tint map_fd_msg = 0, map_fd_rx = 0, map_fd_tx = 0, map_fd_break;\n\tint ports[] = {50200, 50201, 50202, 50204};": "static void test_sockmap(unsigned int tasks, void *data)\n{\n\tstruct bpf_map *bpf_map_rx, *bpf_map_tx, *bpf_map_msg, *bpf_map_break;\n\tint map_fd_msg = 0, map_fd_rx = 0, map_fd_tx = 0, map_fd_break;\n\tint ports[] = {50200, 50201, 50202, 50204};\n\tint err, i, fd, udp, sfd[6] = {0xdeadbeef};\n\tu8 buf[20] = {0x0, 0x5, 0x3, 0x2, 0x1, 0x0};\n\tint parse_prog, verdict_prog, msg_prog;\n\tstruct sockaddr_in addr;\n\tint one = 1, s, sc, rc;\n\tstruct bpf_object *obj;\n\tstruct timeval to;\n\t__u32 key, value;\n\tpid_t pid[tasks];\n\tfd_set w;\n\n\t/* Create some sockets to use with sockmap */\n\tfor (i = 0; i < 2; i++) {\n\t\tsfd[i] = socket(AF_INET, SOCK_STREAM, 0);\n\t\tif (sfd[i] < 0)\n\t\t\tgoto out;\n\t\terr = setsockopt(sfd[i], SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t (char *)&one, sizeof(one));\n\t\tif (err) {\n\t\t\tprintf(\"failed to setsockopt\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\terr = ioctl(sfd[i], FIONBIO, (char *)&one);\n\t\tif (err < 0) {\n\t\t\tprintf(\"failed to ioctl\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tmemset(&addr, 0, sizeof(struct sockaddr_in));\n\t\taddr.sin_family = AF_INET;\n\t\taddr.sin_addr.s_addr = inet_addr(\"127.0.0.1\");\n\t\taddr.sin_port = htons(ports[i]);\n\t\terr = bind(sfd[i], (struct sockaddr *)&addr, sizeof(addr));\n\t\tif (err < 0) {\n\t\t\tprintf(\"failed to bind: err %i: %i:%i\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out;\n\t\t}\n\t\terr = listen(sfd[i], 32);\n\t\tif (err < 0) {\n\t\t\tprintf(\"failed to listen\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tfor (i = 2; i < 4; i++) {\n\t\tsfd[i] = socket(AF_INET, SOCK_STREAM, 0);\n\t\tif (sfd[i] < 0)\n\t\t\tgoto out;\n\t\terr = setsockopt(sfd[i], SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t (char *)&one, sizeof(one));\n\t\tif (err) {\n\t\t\tprintf(\"set sock opt\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tmemset(&addr, 0, sizeof(struct sockaddr_in));\n\t\taddr.sin_family = AF_INET;\n\t\taddr.sin_addr.s_addr = inet_addr(\"127.0.0.1\");\n\t\taddr.sin_port = htons(ports[i - 2]);\n\t\terr = connect(sfd[i], (struct sockaddr *)&addr, sizeof(addr));\n\t\tif (err) {\n\t\t\tprintf(\"failed to connect\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\n\tfor (i = 4; i < 6; i++) {\n\t\tsfd[i] = accept(sfd[i - 4], NULL, NULL);\n\t\tif (sfd[i] < 0) {\n\t\t\tprintf(\"accept failed\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/* Test sockmap with connected sockets */\n\tfd = bpf_map_create(BPF_MAP_TYPE_SOCKMAP, NULL,\n\t\t\t    sizeof(key), sizeof(value),\n\t\t\t    6, NULL);\n\tif (fd < 0) {\n\t\tif (!libbpf_probe_bpf_map_type(BPF_MAP_TYPE_SOCKMAP, NULL)) {\n\t\t\tprintf(\"%s SKIP (unsupported map type BPF_MAP_TYPE_SOCKMAP)\\n\",\n\t\t\t       __func__);\n\t\t\tskips++;\n\t\t\tfor (i = 0; i < 6; i++)\n\t\t\t\tclose(sfd[i]);\n\t\t\treturn;\n\t\t}\n\n\t\tprintf(\"Failed to create sockmap %i\\n\", fd);\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Test update with unsupported UDP socket */\n\tudp = socket(AF_INET, SOCK_DGRAM, 0);\n\ti = 0;\n\terr = bpf_map_update_elem(fd, &i, &udp, BPF_ANY);\n\tif (err) {\n\t\tprintf(\"Failed socket update SOCK_DGRAM '%i:%i'\\n\",\n\t\t       i, udp);\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Test update without programs */\n\tfor (i = 0; i < 6; i++) {\n\t\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_ANY);\n\t\tif (err) {\n\t\t\tprintf(\"Failed noprog update sockmap '%i:%i'\\n\",\n\t\t\t       i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t}\n\n\t/* Test attaching/detaching bad fds */\n\terr = bpf_prog_attach(-1, fd, BPF_SK_SKB_STREAM_PARSER, 0);\n\tif (!err) {\n\t\tprintf(\"Failed invalid parser prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(-1, fd, BPF_SK_SKB_STREAM_VERDICT, 0);\n\tif (!err) {\n\t\tprintf(\"Failed invalid verdict prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(-1, fd, BPF_SK_MSG_VERDICT, 0);\n\tif (!err) {\n\t\tprintf(\"Failed invalid msg verdict prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(-1, fd, __MAX_BPF_ATTACH_TYPE, 0);\n\tif (!err) {\n\t\tprintf(\"Failed unknown prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_detach(fd, BPF_SK_SKB_STREAM_PARSER);\n\tif (!err) {\n\t\tprintf(\"Failed empty parser prog detach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_detach(fd, BPF_SK_SKB_STREAM_VERDICT);\n\tif (!err) {\n\t\tprintf(\"Failed empty verdict prog detach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_detach(fd, BPF_SK_MSG_VERDICT);\n\tif (!err) {\n\t\tprintf(\"Failed empty msg verdict prog detach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_detach(fd, __MAX_BPF_ATTACH_TYPE);\n\tif (!err) {\n\t\tprintf(\"Detach invalid prog successful\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Load SK_SKB program and Attach */\n\terr = bpf_prog_test_load(SOCKMAP_PARSE_PROG,\n\t\t\t    BPF_PROG_TYPE_SK_SKB, &obj, &parse_prog);\n\tif (err) {\n\t\tprintf(\"Failed to load SK_SKB parse prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_test_load(SOCKMAP_TCP_MSG_PROG,\n\t\t\t    BPF_PROG_TYPE_SK_MSG, &obj, &msg_prog);\n\tif (err) {\n\t\tprintf(\"Failed to load SK_SKB msg prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_test_load(SOCKMAP_VERDICT_PROG,\n\t\t\t    BPF_PROG_TYPE_SK_SKB, &obj, &verdict_prog);\n\tif (err) {\n\t\tprintf(\"Failed to load SK_SKB verdict prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tbpf_map_rx = bpf_object__find_map_by_name(obj, \"sock_map_rx\");\n\tif (!bpf_map_rx) {\n\t\tprintf(\"Failed to load map rx from verdict prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tmap_fd_rx = bpf_map__fd(bpf_map_rx);\n\tif (map_fd_rx < 0) {\n\t\tprintf(\"Failed to get map rx fd\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tbpf_map_tx = bpf_object__find_map_by_name(obj, \"sock_map_tx\");\n\tif (!bpf_map_tx) {\n\t\tprintf(\"Failed to load map tx from verdict prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tmap_fd_tx = bpf_map__fd(bpf_map_tx);\n\tif (map_fd_tx < 0) {\n\t\tprintf(\"Failed to get map tx fd\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tbpf_map_msg = bpf_object__find_map_by_name(obj, \"sock_map_msg\");\n\tif (!bpf_map_msg) {\n\t\tprintf(\"Failed to load map msg from msg_verdict prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tmap_fd_msg = bpf_map__fd(bpf_map_msg);\n\tif (map_fd_msg < 0) {\n\t\tprintf(\"Failed to get map msg fd\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tbpf_map_break = bpf_object__find_map_by_name(obj, \"sock_map_break\");\n\tif (!bpf_map_break) {\n\t\tprintf(\"Failed to load map tx from verdict prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tmap_fd_break = bpf_map__fd(bpf_map_break);\n\tif (map_fd_break < 0) {\n\t\tprintf(\"Failed to get map tx fd\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(parse_prog, map_fd_break,\n\t\t\t      BPF_SK_SKB_STREAM_PARSER, 0);\n\tif (!err) {\n\t\tprintf(\"Allowed attaching SK_SKB program to invalid map\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(parse_prog, map_fd_rx,\n\t\t      BPF_SK_SKB_STREAM_PARSER, 0);\n\tif (err) {\n\t\tprintf(\"Failed stream parser bpf prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(verdict_prog, map_fd_rx,\n\t\t\t      BPF_SK_SKB_STREAM_VERDICT, 0);\n\tif (err) {\n\t\tprintf(\"Failed stream verdict bpf prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(msg_prog, map_fd_msg, BPF_SK_MSG_VERDICT, 0);\n\tif (err) {\n\t\tprintf(\"Failed msg verdict bpf prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_attach(verdict_prog, map_fd_rx,\n\t\t\t      __MAX_BPF_ATTACH_TYPE, 0);\n\tif (!err) {\n\t\tprintf(\"Attached unknown bpf prog\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Test map update elem afterwards fd lives in fd and map_fd */\n\tfor (i = 2; i < 6; i++) {\n\t\terr = bpf_map_update_elem(map_fd_rx, &i, &sfd[i], BPF_ANY);\n\t\tif (err) {\n\t\t\tprintf(\"Failed map_fd_rx update sockmap %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t\terr = bpf_map_update_elem(map_fd_tx, &i, &sfd[i], BPF_ANY);\n\t\tif (err) {\n\t\t\tprintf(\"Failed map_fd_tx update sockmap %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t}\n\n\t/* Test map delete elem and remove send/recv sockets */\n\tfor (i = 2; i < 4; i++) {\n\t\terr = bpf_map_delete_elem(map_fd_rx, &i);\n\t\tif (err) {\n\t\t\tprintf(\"Failed delete sockmap rx %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t\terr = bpf_map_delete_elem(map_fd_tx, &i);\n\t\tif (err) {\n\t\t\tprintf(\"Failed delete sockmap tx %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t}\n\n\t/* Put sfd[2] (sending fd below) into msg map to test sendmsg bpf */\n\ti = 0;\n\terr = bpf_map_update_elem(map_fd_msg, &i, &sfd[2], BPF_ANY);\n\tif (err) {\n\t\tprintf(\"Failed map_fd_msg update sockmap %i\\n\", err);\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Test map send/recv */\n\tfor (i = 0; i < 2; i++) {\n\t\tbuf[0] = i;\n\t\tbuf[1] = 0x5;\n\t\tsc = send(sfd[2], buf, 20, 0);\n\t\tif (sc < 0) {\n\t\t\tprintf(\"Failed sockmap send\\n\");\n\t\t\tgoto out_sockmap;\n\t\t}\n\n\t\tFD_ZERO(&w);\n\t\tFD_SET(sfd[3], &w);\n\t\tto.tv_sec = 30;\n\t\tto.tv_usec = 0;\n\t\ts = select(sfd[3] + 1, &w, NULL, NULL, &to);\n\t\tif (s == -1) {\n\t\t\tperror(\"Failed sockmap select()\");\n\t\t\tgoto out_sockmap;\n\t\t} else if (!s) {\n\t\t\tprintf(\"Failed sockmap unexpected timeout\\n\");\n\t\t\tgoto out_sockmap;\n\t\t}\n\n\t\tif (!FD_ISSET(sfd[3], &w)) {\n\t\t\tprintf(\"Failed sockmap select/recv\\n\");\n\t\t\tgoto out_sockmap;\n\t\t}\n\n\t\trc = recv(sfd[3], buf, sizeof(buf), 0);\n\t\tif (rc < 0) {\n\t\t\tprintf(\"Failed sockmap recv\\n\");\n\t\t\tgoto out_sockmap;\n\t\t}\n\t}\n\n\t/* Negative null entry lookup from datapath should be dropped */\n\tbuf[0] = 1;\n\tbuf[1] = 12;\n\tsc = send(sfd[2], buf, 20, 0);\n\tif (sc < 0) {\n\t\tprintf(\"Failed sockmap send\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Push fd into same slot */\n\ti = 2;\n\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_NOEXIST);\n\tif (!err) {\n\t\tprintf(\"Failed allowed sockmap dup slot BPF_NOEXIST\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_ANY);\n\tif (err) {\n\t\tprintf(\"Failed sockmap update new slot BPF_ANY\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_EXIST);\n\tif (err) {\n\t\tprintf(\"Failed sockmap update new slot BPF_EXIST\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Delete the elems without programs */\n\tfor (i = 2; i < 6; i++) {\n\t\terr = bpf_map_delete_elem(fd, &i);\n\t\tif (err) {\n\t\t\tprintf(\"Failed delete sockmap %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t}\n\t}\n\n\t/* Test having multiple maps open and set with programs on same fds */\n\terr = bpf_prog_attach(parse_prog, fd,\n\t\t\t      BPF_SK_SKB_STREAM_PARSER, 0);\n\tif (err) {\n\t\tprintf(\"Failed fd bpf parse prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\terr = bpf_prog_attach(verdict_prog, fd,\n\t\t\t      BPF_SK_SKB_STREAM_VERDICT, 0);\n\tif (err) {\n\t\tprintf(\"Failed fd bpf verdict prog attach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\tfor (i = 4; i < 6; i++) {\n\t\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_ANY);\n\t\tif (!err) {\n\t\t\tprintf(\"Failed allowed duplicate programs in update ANY sockmap %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_NOEXIST);\n\t\tif (!err) {\n\t\t\tprintf(\"Failed allowed duplicate program in update NOEXIST sockmap  %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t\terr = bpf_map_update_elem(fd, &i, &sfd[i], BPF_EXIST);\n\t\tif (!err) {\n\t\t\tprintf(\"Failed allowed duplicate program in update EXIST sockmap  %i '%i:%i'\\n\",\n\t\t\t       err, i, sfd[i]);\n\t\t\tgoto out_sockmap;\n\t\t}\n\t}\n\n\t/* Test tasks number of forked operations */\n\tfor (i = 0; i < tasks; i++) {\n\t\tpid[i] = fork();\n\t\tif (pid[i] == 0) {\n\t\t\tfor (i = 0; i < 6; i++) {\n\t\t\t\tbpf_map_delete_elem(map_fd_tx, &i);\n\t\t\t\tbpf_map_delete_elem(map_fd_rx, &i);\n\t\t\t\tbpf_map_update_elem(map_fd_tx, &i,\n\t\t\t\t\t\t    &sfd[i], BPF_ANY);\n\t\t\t\tbpf_map_update_elem(map_fd_rx, &i,\n\t\t\t\t\t\t    &sfd[i], BPF_ANY);\n\t\t\t}\n\t\t\texit(0);\n\t\t} else if (pid[i] == -1) {\n\t\t\tprintf(\"Couldn't spawn #%d process!\\n\", i);\n\t\t\texit(1);\n\t\t}\n\t}\n\n\tfor (i = 0; i < tasks; i++) {\n\t\tint status;\n\n\t\tassert(waitpid(pid[i], &status, 0) == pid[i]);\n\t\tassert(status == 0);\n\t}\n\n\terr = bpf_prog_detach2(parse_prog, map_fd_rx, __MAX_BPF_ATTACH_TYPE);\n\tif (!err) {\n\t\tprintf(\"Detached an invalid prog type.\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_detach2(parse_prog, map_fd_rx, BPF_SK_SKB_STREAM_PARSER);\n\tif (err) {\n\t\tprintf(\"Failed parser prog detach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\terr = bpf_prog_detach2(verdict_prog, map_fd_rx, BPF_SK_SKB_STREAM_VERDICT);\n\tif (err) {\n\t\tprintf(\"Failed parser prog detach\\n\");\n\t\tgoto out_sockmap;\n\t}\n\n\t/* Test map close sockets and empty maps */\n\tfor (i = 0; i < 6; i++) {\n\t\tbpf_map_delete_elem(map_fd_tx, &i);\n\t\tbpf_map_delete_elem(map_fd_rx, &i);\n\t\tclose(sfd[i]);\n\t}\n\tclose(fd);\n\tclose(map_fd_rx);\n\tbpf_object__close(obj);\n\treturn;\nout:\n\tfor (i = 0; i < 6; i++)\n\t\tclose(sfd[i]);\n\tprintf(\"Failed to create sockmap '%i:%s'!\\n\", i, strerror(errno));\n\texit(1);\nout_sockmap:\n\tfor (i = 0; i < 6; i++) {\n\t\tif (map_fd_tx)\n\t\t\tbpf_map_delete_elem(map_fd_tx, &i);\n\t\tif (map_fd_rx)\n\t\t\tbpf_map_delete_elem(map_fd_rx, &i);\n\t\tclose(sfd[i]);\n\t}\n\tclose(fd);\n\texit(1);\n}",
        "static int INIT gunzip(void)\n{\n    uch flags;\n    unsigned char magic[2]; /* magic header */\n    char method;": "static int INIT gunzip(void)\n{\n    uch flags;\n    unsigned char magic[2]; /* magic header */\n    char method;\n    ulg orig_crc = 0;       /* original crc */\n    ulg orig_len = 0;       /* original uncompressed length */\n    int res;\n\n    magic[0] = NEXTBYTE();\n    magic[1] = NEXTBYTE();\n    method   = NEXTBYTE();\n\n    if (magic[0] != 037 ||\n\t((magic[1] != 0213) && (magic[1] != 0236))) {\n\t    error(\"bad gzip magic numbers\");\n\t    return -1;\n    }\n\n    /* We only support method #8, DEFLATED */\n    if (method != 8)  {\n\t    error(\"internal error, invalid method\");\n\t    return -1;\n    }\n\n    flags  = (uch)get_byte();\n    if ((flags & ENCRYPTED) != 0) {\n\t    error(\"Input is encrypted\");\n\t    return -1;\n    }\n    if ((flags & CONTINUATION) != 0) {\n\t    error(\"Multi part input\");\n\t    return -1;\n    }\n    if ((flags & RESERVED) != 0) {\n\t    error(\"Input has invalid flags\");\n\t    return -1;\n    }\n    NEXTBYTE();\t/* Get timestamp */\n    NEXTBYTE();\n    NEXTBYTE();\n    NEXTBYTE();\n\n    (void)NEXTBYTE();  /* Ignore extra flags for the moment */\n    (void)NEXTBYTE();  /* Ignore OS type for the moment */\n\n    if ((flags & EXTRA_FIELD) != 0) {\n\t    unsigned len = (unsigned)NEXTBYTE();\n\t    len |= ((unsigned)NEXTBYTE())<<8;\n\t    while (len--) (void)NEXTBYTE();\n    }\n\n    /* Get original file name if it was truncated */\n    if ((flags & ORIG_NAME) != 0) {\n\t    /* Discard the old name */\n\t    while (NEXTBYTE() != 0) /* null */ ;\n    } \n\n    /* Discard file comment if any */\n    if ((flags & COMMENT) != 0) {\n\t    while (NEXTBYTE() != 0) /* null */ ;\n    }\n\n    /* Decompress */\n    if ((res = inflate())) {\n\t    switch (res) {\n\t    case 0:\n\t\t    break;\n\t    case 1:\n\t\t    error(\"invalid compressed format (err=1)\");\n\t\t    break;\n\t    case 2:\n\t\t    error(\"invalid compressed format (err=2)\");\n\t\t    break;\n\t    case 3:\n\t\t    error(\"out of memory\");\n\t\t    break;\n\t    case 4:\n\t\t    error(\"out of input data\");\n\t\t    break;\n\t    default:\n\t\t    error(\"invalid compressed format (other)\");\n\t    }\n\t    return -1;\n    }\n\t    \n    /* Get the crc and original length */\n    /* crc32  (see algorithm.doc)\n     * uncompressed input size modulo 2^32\n     */\n    orig_crc = (ulg) NEXTBYTE();\n    orig_crc |= (ulg) NEXTBYTE() << 8;\n    orig_crc |= (ulg) NEXTBYTE() << 16;\n    orig_crc |= (ulg) NEXTBYTE() << 24;\n    \n    orig_len = (ulg) NEXTBYTE();\n    orig_len |= (ulg) NEXTBYTE() << 8;\n    orig_len |= (ulg) NEXTBYTE() << 16;\n    orig_len |= (ulg) NEXTBYTE() << 24;\n    \n    /* Validate decompression */\n    if (orig_crc != CRC_VALUE) {\n\t    error(\"crc error\");\n\t    return -1;\n    }\n    if (orig_len != bytes_out) {\n\t    error(\"length error\");\n\t    return -1;\n    }\n    return 0;\n\n underrun:\t\t\t/* NEXTBYTE() goto's here if needed */\n    error(\"out of input data\");\n    return -1;\n}",
        "static void gre_err(struct sk_buff *skb, u32 info)\n{\n\t/* All the routers (except for Linux) return only\n\t * 8 bytes of packet payload. It means, that precise relaying of\n\t * ICMP in the real Internet is absolutely infeasible.": "static void gre_err(struct sk_buff *skb, u32 info)\n{\n\t/* All the routers (except for Linux) return only\n\t * 8 bytes of packet payload. It means, that precise relaying of\n\t * ICMP in the real Internet is absolutely infeasible.\n\t *\n\t * Moreover, Cisco \"wise men\" put GRE key to the third word\n\t * in GRE header. It makes impossible maintaining even soft\n\t * state for keyed\n\t * GRE tunnels with enabled checksum. Tell them \"thank you\".\n\t *\n\t * Well, I wonder, rfc1812 was written by Cisco employee,\n\t * what the hell these idiots break standards established\n\t * by themselves???\n\t */\n\n\tconst struct iphdr *iph = (struct iphdr *)skb->data;\n\tconst int type = icmp_hdr(skb)->type;\n\tconst int code = icmp_hdr(skb)->code;\n\tstruct tnl_ptk_info tpi;\n\n\tif (gre_parse_header(skb, &tpi, NULL, htons(ETH_P_IP),\n\t\t\t     iph->ihl * 4) < 0)\n\t\treturn;\n\n\tif (type == ICMP_DEST_UNREACH && code == ICMP_FRAG_NEEDED) {\n\t\tipv4_update_pmtu(skb, dev_net(skb->dev), info,\n\t\t\t\t skb->dev->ifindex, IPPROTO_GRE);\n\t\treturn;\n\t}\n\tif (type == ICMP_REDIRECT) {\n\t\tipv4_redirect(skb, dev_net(skb->dev), skb->dev->ifindex,\n\t\t\t      IPPROTO_GRE);\n\t\treturn;\n\t}\n\n\tipgre_err(skb, info, &tpi);\n}",
        "static void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)\n{\n\tfd_fltr_ctx->comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;\n\tfd_fltr_ctx->comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;\n\tfd_fltr_ctx->fd_space = ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST;": "static void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)\n{\n\tfd_fltr_ctx->comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;\n\tfd_fltr_ctx->comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;\n\tfd_fltr_ctx->fd_space = ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST;\n\tfd_fltr_ctx->cnt_ena = ICE_FXD_FLTR_QW0_STAT_ENA_PKTS;\n\tfd_fltr_ctx->evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE;\n\tfd_fltr_ctx->toq = ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX;\n\tfd_fltr_ctx->toq_prio = ICE_FXD_FLTR_QW0_TO_Q_PRIO1;\n\tfd_fltr_ctx->dpu_recipe = ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT;\n\tfd_fltr_ctx->drop = ICE_FXD_FLTR_QW0_DROP_NO;\n\tfd_fltr_ctx->flex_prio = ICE_FXD_FLTR_QW0_FLEX_PRI_NONE;\n\tfd_fltr_ctx->flex_mdid = ICE_FXD_FLTR_QW0_FLEX_MDID0;\n\tfd_fltr_ctx->flex_val = ICE_FXD_FLTR_QW0_FLEX_VAL0;\n\tfd_fltr_ctx->dtype = ICE_TX_DESC_DTYPE_FLTR_PROG;\n\tfd_fltr_ctx->desc_prof_prio = ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO;\n\tfd_fltr_ctx->desc_prof = ICE_FXD_FLTR_QW1_PROF_ZERO;\n\tfd_fltr_ctx->swap = ICE_FXD_FLTR_QW1_SWAP_SET;\n\tfd_fltr_ctx->fdid_prio = ICE_FXD_FLTR_QW1_FDID_PRI_ONE;\n\tfd_fltr_ctx->fdid_mdid = ICE_FXD_FLTR_QW1_FDID_MDID_FD;\n\tfd_fltr_ctx->fdid = ICE_FXD_FLTR_QW1_FDID_ZERO;\n}",
        "static void rtl_hw_start_8168f(struct rtl8169_private *tp)\n{\n\trtl_set_def_aspm_entry_latency(tp);\n\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);": "static void rtl_hw_start_8168f(struct rtl8169_private *tp)\n{\n\trtl_set_def_aspm_entry_latency(tp);\n\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);\n\trtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);\n\trtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);\n\trtl_reset_packet_filter(tp);\n\trtl_eri_set_bits(tp, 0x1b0, BIT(4));\n\trtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));\n\trtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);\n\trtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);\n\n\trtl_disable_clock_request(tp);\n\n\tRTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);\n\tRTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);\n\tRTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);\n\tRTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);\n\n\trtl8168_config_eee_mac(tp);\n}",
        "static void sw_i2c_wait(void)\n{\n\t/* find a bug:\n\t * peekIO method works well before suspend/resume\n\t * but after suspend, peekIO(0x3ce,0x61) & 0x10": "static void sw_i2c_wait(void)\n{\n\t/* find a bug:\n\t * peekIO method works well before suspend/resume\n\t * but after suspend, peekIO(0x3ce,0x61) & 0x10\n\t * always be non-zero,which makes the while loop\n\t * never finish.\n\t * use non-ultimate for loop below is safe\n\t */\n\n    /* Change wait algorithm to use PCI bus clock,\n     * it's more reliable than counter loop ..\n     * write 0x61 to 0x3ce and read from 0x3cf\n     */\n\tint i, tmp;\n\n\tfor (i = 0; i < 600; i++) {\n\t\ttmp = i;\n\t\ttmp += i;\n\t}\n}",
        "static bool i40e_is_total_port_shutdown_enabled(struct i40e_pf *pf)\n{\n#define I40E_TOTAL_PORT_SHUTDOWN_ENABLED\tBIT(4)\n#define I40E_FEATURES_ENABLE_PTR\t\t0x2A\n#define I40E_CURRENT_SETTING_PTR\t\t0x2B": "static bool i40e_is_total_port_shutdown_enabled(struct i40e_pf *pf)\n{\n#define I40E_TOTAL_PORT_SHUTDOWN_ENABLED\tBIT(4)\n#define I40E_FEATURES_ENABLE_PTR\t\t0x2A\n#define I40E_CURRENT_SETTING_PTR\t\t0x2B\n#define I40E_LINK_BEHAVIOR_WORD_OFFSET\t\t0x2D\n#define I40E_LINK_BEHAVIOR_WORD_LENGTH\t\t0x1\n#define I40E_LINK_BEHAVIOR_OS_FORCED_ENABLED\tBIT(0)\n#define I40E_LINK_BEHAVIOR_PORT_BIT_LENGTH\t4\n\ti40e_status read_status = I40E_SUCCESS;\n\tu16 sr_emp_sr_settings_ptr = 0;\n\tu16 features_enable = 0;\n\tu16 link_behavior = 0;\n\tbool ret = false;\n\n\tread_status = i40e_read_nvm_word(&pf->hw,\n\t\t\t\t\t I40E_SR_EMP_SR_SETTINGS_PTR,\n\t\t\t\t\t &sr_emp_sr_settings_ptr);\n\tif (read_status)\n\t\tgoto err_nvm;\n\tread_status = i40e_read_nvm_word(&pf->hw,\n\t\t\t\t\t sr_emp_sr_settings_ptr +\n\t\t\t\t\t I40E_FEATURES_ENABLE_PTR,\n\t\t\t\t\t &features_enable);\n\tif (read_status)\n\t\tgoto err_nvm;\n\tif (I40E_TOTAL_PORT_SHUTDOWN_ENABLED & features_enable) {\n\t\tread_status = i40e_read_nvm_module_data(&pf->hw,\n\t\t\t\t\t\t\tI40E_SR_EMP_SR_SETTINGS_PTR,\n\t\t\t\t\t\t\tI40E_CURRENT_SETTING_PTR,\n\t\t\t\t\t\t\tI40E_LINK_BEHAVIOR_WORD_OFFSET,\n\t\t\t\t\t\t\tI40E_LINK_BEHAVIOR_WORD_LENGTH,\n\t\t\t\t\t\t\t&link_behavior);\n\t\tif (read_status)\n\t\t\tgoto err_nvm;\n\t\tlink_behavior >>= (pf->hw.port * I40E_LINK_BEHAVIOR_PORT_BIT_LENGTH);\n\t\tret = I40E_LINK_BEHAVIOR_OS_FORCED_ENABLED & link_behavior;\n\t}\n\treturn ret;\n\nerr_nvm:\n\tdev_warn(&pf->pdev->dev,\n\t\t \"total-port-shutdown feature is off due to read nvm error: %s\\n\",\n\t\t i40e_stat_str(&pf->hw, read_status));\n\treturn ret;\n}",
        "static void alc_determine_headset_type(struct hda_codec *codec)\n{\n\tint val;\n\tbool is_ctia = false;\n\tstruct alc_spec *spec = codec->spec;": "static void alc_determine_headset_type(struct hda_codec *codec)\n{\n\tint val;\n\tbool is_ctia = false;\n\tstruct alc_spec *spec = codec->spec;\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x45, 0xd089), /* combo jack auto switch control(Check type)*/\n\t\tWRITE_COEF(0x49, 0x0149), /* combo jack auto switch control(Vref\n conteol) */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0288[] = {\n\t\tUPDATE_COEF(0x4f, 0xfcc0, 0xd400), /* Check Type */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0298[] = {\n\t\tUPDATE_COEF(0x50, 0x2000, 0x2000),\n\t\tUPDATE_COEF(0x56, 0x0006, 0x0006),\n\t\tUPDATE_COEF(0x66, 0x0008, 0),\n\t\tUPDATE_COEF(0x67, 0x2000, 0),\n\t\tUPDATE_COEF(0x19, 0x1300, 0x1300),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0293[] = {\n\t\tUPDATE_COEF(0x4a, 0x000f, 0x0008), /* Combo Jack auto detect */\n\t\tWRITE_COEF(0x45, 0xD429), /* Set to ctia type */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0688[] = {\n\t\tWRITE_COEF(0x11, 0x0001),\n\t\tWRITE_COEF(0xb7, 0x802b),\n\t\tWRITE_COEF(0x15, 0x0d60),\n\t\tWRITE_COEF(0xc3, 0x0c00),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0274[] = {\n\t\tUPDATE_COEF(0x4a, 0x0010, 0),\n\t\tUPDATE_COEF(0x4a, 0x8000, 0),\n\t\tWRITE_COEF(0x45, 0xd289),\n\t\tUPDATE_COEF(0x49, 0x0300, 0x0300),\n\t\t{}\n\t};\n\n\tif (spec->no_internal_mic_pin) {\n\t\talc_update_coef_idx(codec, 0x45, 0xf<<12 | 1<<10, 5<<12);\n\t\treturn;\n\t}\n\n\tswitch (codec->core.vendor_id) {\n\tcase 0x10ec0255:\n\t\talc_process_coef_fw(codec, coef0255);\n\t\tmsleep(300);\n\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\tis_ctia = (val & 0x0070) == 0x0070;\n\t\tbreak;\n\tcase 0x10ec0230:\n\tcase 0x10ec0236:\n\tcase 0x10ec0256:\n\t\talc_write_coef_idx(codec, 0x1b, 0x0e4b);\n\t\talc_write_coef_idx(codec, 0x06, 0x6104);\n\t\talc_write_coefex_idx(codec, 0x57, 0x3, 0x09a3);\n\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);\n\t\tmsleep(80);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);\n\n\t\talc_process_coef_fw(codec, coef0255);\n\t\tmsleep(300);\n\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\tis_ctia = (val & 0x0070) == 0x0070;\n\n\t\talc_write_coefex_idx(codec, 0x57, 0x3, 0x0da3);\n\t\talc_update_coefex_idx(codec, 0x57, 0x5, 1<<14, 0);\n\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);\n\t\tmsleep(80);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);\n\t\tbreak;\n\tcase 0x10ec0234:\n\tcase 0x10ec0274:\n\tcase 0x10ec0294:\n\t\talc_process_coef_fw(codec, coef0274);\n\t\tmsleep(850);\n\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\tis_ctia = (val & 0x00f0) == 0x00f0;\n\t\tbreak;\n\tcase 0x10ec0233:\n\tcase 0x10ec0283:\n\t\talc_write_coef_idx(codec, 0x45, 0xd029);\n\t\tmsleep(300);\n\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\tis_ctia = (val & 0x0070) == 0x0070;\n\t\tbreak;\n\tcase 0x10ec0298:\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);\n\t\tmsleep(100);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);\n\t\tmsleep(200);\n\n\t\tval = alc_read_coef_idx(codec, 0x50);\n\t\tif (val & (1 << 12)) {\n\t\t\talc_update_coef_idx(codec, 0x8e, 0x0070, 0x0020);\n\t\t\talc_process_coef_fw(codec, coef0288);\n\t\t\tmsleep(350);\n\t\t\tval = alc_read_coef_idx(codec, 0x50);\n\t\t\tis_ctia = (val & 0x0070) == 0x0070;\n\t\t} else {\n\t\t\talc_update_coef_idx(codec, 0x8e, 0x0070, 0x0010);\n\t\t\talc_process_coef_fw(codec, coef0288);\n\t\t\tmsleep(350);\n\t\t\tval = alc_read_coef_idx(codec, 0x50);\n\t\t\tis_ctia = (val & 0x0070) == 0x0070;\n\t\t}\n\t\talc_process_coef_fw(codec, coef0298);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);\n\t\tmsleep(75);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);\n\t\tbreak;\n\tcase 0x10ec0286:\n\tcase 0x10ec0288:\n\t\talc_process_coef_fw(codec, coef0288);\n\t\tmsleep(350);\n\t\tval = alc_read_coef_idx(codec, 0x50);\n\t\tis_ctia = (val & 0x0070) == 0x0070;\n\t\tbreak;\n\tcase 0x10ec0292:\n\t\talc_write_coef_idx(codec, 0x6b, 0xd429);\n\t\tmsleep(300);\n\t\tval = alc_read_coef_idx(codec, 0x6c);\n\t\tis_ctia = (val & 0x001c) == 0x001c;\n\t\tbreak;\n\tcase 0x10ec0293:\n\t\talc_process_coef_fw(codec, coef0293);\n\t\tmsleep(300);\n\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\tis_ctia = (val & 0x0070) == 0x0070;\n\t\tbreak;\n\tcase 0x10ec0668:\n\t\talc_process_coef_fw(codec, coef0688);\n\t\tmsleep(300);\n\t\tval = alc_read_coef_idx(codec, 0xbe);\n\t\tis_ctia = (val & 0x1c02) == 0x1c02;\n\t\tbreak;\n\tcase 0x10ec0215:\n\tcase 0x10ec0225:\n\tcase 0x10ec0285:\n\tcase 0x10ec0295:\n\tcase 0x10ec0289:\n\tcase 0x10ec0299:\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);\n\t\tmsleep(80);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);\n\n\t\talc_process_coef_fw(codec, alc225_pre_hsmode);\n\t\talc_update_coef_idx(codec, 0x67, 0xf000, 0x1000);\n\t\tval = alc_read_coef_idx(codec, 0x45);\n\t\tif (val & (1 << 9)) {\n\t\t\talc_update_coef_idx(codec, 0x45, 0x3f<<10, 0x34<<10);\n\t\t\talc_update_coef_idx(codec, 0x49, 3<<8, 2<<8);\n\t\t\tmsleep(800);\n\t\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\t\tis_ctia = (val & 0x00f0) == 0x00f0;\n\t\t} else {\n\t\t\talc_update_coef_idx(codec, 0x45, 0x3f<<10, 0x34<<10);\n\t\t\talc_update_coef_idx(codec, 0x49, 3<<8, 1<<8);\n\t\t\tmsleep(800);\n\t\t\tval = alc_read_coef_idx(codec, 0x46);\n\t\t\tis_ctia = (val & 0x00f0) == 0x00f0;\n\t\t}\n\t\talc_update_coef_idx(codec, 0x4a, 7<<6, 7<<6);\n\t\talc_update_coef_idx(codec, 0x4a, 3<<4, 3<<4);\n\t\talc_update_coef_idx(codec, 0x67, 0xf000, 0x3000);\n\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);\n\t\tmsleep(80);\n\t\tsnd_hda_codec_write(codec, 0x21, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);\n\t\tbreak;\n\tcase 0x10ec0867:\n\t\tis_ctia = true;\n\t\tbreak;\n\t}\n\n\tcodec_dbg(codec, \"Headset jack detected iPhone-style headset: %s\\n\",\n\t\t    is_ctia ? \"yes\" : \"no\");\n\tspec->current_headset_type = is_ctia ? ALC_HEADSET_TYPE_CTIA : ALC_HEADSET_TYPE_OMTP;\n}",
        "static int rvu_map_cgx_lmac_pf(struct rvu *rvu)\n{\n\tstruct npc_pkind *pkind = &rvu->hw->pkind;\n\tint cgx_cnt_max = rvu->cgx_cnt_max;\n\tint pf = PF_CGXMAP_BASE;": "static int rvu_map_cgx_lmac_pf(struct rvu *rvu)\n{\n\tstruct npc_pkind *pkind = &rvu->hw->pkind;\n\tint cgx_cnt_max = rvu->cgx_cnt_max;\n\tint pf = PF_CGXMAP_BASE;\n\tunsigned long lmac_bmap;\n\tint size, free_pkind;\n\tint cgx, lmac, iter;\n\tint numvfs, hwvfs;\n\n\tif (!cgx_cnt_max)\n\t\treturn 0;\n\n\tif (cgx_cnt_max > 0xF || MAX_LMAC_PER_CGX > 0xF)\n\t\treturn -EINVAL;\n\n\t/* Alloc map table\n\t * An additional entry is required since PF id starts from 1 and\n\t * hence entry at offset 0 is invalid.\n\t */\n\tsize = (cgx_cnt_max * MAX_LMAC_PER_CGX + 1) * sizeof(u8);\n\trvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);\n\tif (!rvu->pf2cgxlmac_map)\n\t\treturn -ENOMEM;\n\n\t/* Initialize all entries with an invalid cgx and lmac id */\n\tmemset(rvu->pf2cgxlmac_map, 0xFF, size);\n\n\t/* Reverse map table */\n\trvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,\n\t\t\t\t  cgx_cnt_max * MAX_LMAC_PER_CGX * sizeof(u16),\n\t\t\t\t  GFP_KERNEL);\n\tif (!rvu->cgxlmac2pf_map)\n\t\treturn -ENOMEM;\n\n\trvu->cgx_mapped_pfs = 0;\n\tfor (cgx = 0; cgx < cgx_cnt_max; cgx++) {\n\t\tif (!rvu_cgx_pdata(cgx, rvu))\n\t\t\tcontinue;\n\t\tlmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));\n\t\tfor_each_set_bit(iter, &lmac_bmap, MAX_LMAC_PER_CGX) {\n\t\t\tlmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),\n\t\t\t\t\t      iter);\n\t\t\trvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);\n\t\t\trvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;\n\t\t\tfree_pkind = rvu_alloc_rsrc(&pkind->rsrc);\n\t\t\tpkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;\n\t\t\trvu_map_cgx_nix_block(rvu, pf, cgx, lmac);\n\t\t\trvu->cgx_mapped_pfs++;\n\t\t\trvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);\n\t\t\trvu->cgx_mapped_vfs += numvfs;\n\t\t\tpf++;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int set_mpegtei_handling(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tint rc;": "static int set_mpegtei_handling(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tint rc;\n\tu16 fec_oc_dpr_mode = 0;\n\tu16 fec_oc_snc_mode = 0;\n\tu16 fec_oc_ems_mode = 0;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* reset to default, allow TEI bit to be changed */\n\tfec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);\n\tfec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |\n\t\t\t   FEC_OC_SNC_MODE_CORR_DISABLE__M));\n\tfec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);\n\n\tif (ext_attr->disable_te_ihandling) {\n\t\t/* do not change TEI bit */\n\t\tfec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;\n\t\tfec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |\n\t\t    ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));\n\t\tfec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int ntfs_extend_mft(struct ntfs_sb_info *sbi)\n{\n\tint err;\n\tstruct ntfs_inode *ni = sbi->mft.ni;\n\tsize_t new_mft_total;": "static int ntfs_extend_mft(struct ntfs_sb_info *sbi)\n{\n\tint err;\n\tstruct ntfs_inode *ni = sbi->mft.ni;\n\tsize_t new_mft_total;\n\tu64 new_mft_bytes, new_bitmap_bytes;\n\tstruct ATTRIB *attr;\n\tstruct wnd_bitmap *wnd = &sbi->mft.bitmap;\n\n\tnew_mft_total = (wnd->nbits + MFT_INCREASE_CHUNK + 127) & (CLST)~127;\n\tnew_mft_bytes = (u64)new_mft_total << sbi->record_bits;\n\n\t/* Step 1: Resize $MFT::DATA. */\n\tdown_write(&ni->file.run_lock);\n\terr = attr_set_size(ni, ATTR_DATA, NULL, 0, &ni->file.run,\n\t\t\t    new_mft_bytes, NULL, false, &attr);\n\n\tif (err) {\n\t\tup_write(&ni->file.run_lock);\n\t\tgoto out;\n\t}\n\n\tattr->nres.valid_size = attr->nres.data_size;\n\tnew_mft_total = le64_to_cpu(attr->nres.alloc_size) >> sbi->record_bits;\n\tni->mi.dirty = true;\n\n\t/* Step 2: Resize $MFT::BITMAP. */\n\tnew_bitmap_bytes = bitmap_size(new_mft_total);\n\n\terr = attr_set_size(ni, ATTR_BITMAP, NULL, 0, &sbi->mft.bitmap.run,\n\t\t\t    new_bitmap_bytes, &new_bitmap_bytes, true, NULL);\n\n\t/* Refresh MFT Zone if necessary. */\n\tdown_write_nested(&sbi->used.bitmap.rw_lock, BITMAP_MUTEX_CLUSTERS);\n\n\tntfs_refresh_zone(sbi);\n\n\tup_write(&sbi->used.bitmap.rw_lock);\n\tup_write(&ni->file.run_lock);\n\n\tif (err)\n\t\tgoto out;\n\n\terr = wnd_extend(wnd, new_mft_total);\n\n\tif (err)\n\t\tgoto out;\n\n\tntfs_clear_mft_tail(sbi, sbi->mft.used, new_mft_total);\n\n\terr = _ni_write_inode(&ni->vfs_inode, 0);\nout:\n\treturn err;\n}",
        "static int __init test_f5(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 w[32] = {\n\t\t\t0x98, 0xa6, 0xbf, 0x73, 0xf3, 0x34, 0x8d, 0x86,\n\t\t\t0xf1, 0x66, 0xf8, 0xb4, 0x13, 0x6b, 0x79, 0x99,": "static int __init test_f5(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 w[32] = {\n\t\t\t0x98, 0xa6, 0xbf, 0x73, 0xf3, 0x34, 0x8d, 0x86,\n\t\t\t0xf1, 0x66, 0xf8, 0xb4, 0x13, 0x6b, 0x79, 0x99,\n\t\t\t0x9b, 0x7d, 0x39, 0x0a, 0xa6, 0x10, 0x10, 0x34,\n\t\t\t0x05, 0xad, 0xc8, 0x57, 0xa3, 0x34, 0x02, 0xec };\n\tconst u8 n1[16] = {\n\t\t\t0xab, 0xae, 0x2b, 0x71, 0xec, 0xb2, 0xff, 0xff,\n\t\t\t0x3e, 0x73, 0x77, 0xd1, 0x54, 0x84, 0xcb, 0xd5 };\n\tconst u8 n2[16] = {\n\t\t\t0xcf, 0xc4, 0x3d, 0xff, 0xf7, 0x83, 0x65, 0x21,\n\t\t\t0x6e, 0x5f, 0xa7, 0x25, 0xcc, 0xe7, 0xe8, 0xa6 };\n\tconst u8 a1[7] = { 0xce, 0xbf, 0x37, 0x37, 0x12, 0x56, 0x00 };\n\tconst u8 a2[7] = { 0xc1, 0xcf, 0x2d, 0x70, 0x13, 0xa7, 0x00 };\n\tconst u8 exp_ltk[16] = {\n\t\t\t0x38, 0x0a, 0x75, 0x94, 0xb5, 0x22, 0x05, 0x98,\n\t\t\t0x23, 0xcd, 0xd7, 0x69, 0x11, 0x79, 0x86, 0x69 };\n\tconst u8 exp_mackey[16] = {\n\t\t\t0x20, 0x6e, 0x63, 0xce, 0x20, 0x6a, 0x3f, 0xfd,\n\t\t\t0x02, 0x4a, 0x08, 0xa1, 0x76, 0xf1, 0x65, 0x29 };\n\tu8 mackey[16], ltk[16];\n\tint err;\n\n\terr = smp_f5(tfm_cmac, w, n1, n2, a1, a2, mackey, ltk);\n\tif (err)\n\t\treturn err;\n\n\tif (crypto_memneq(mackey, exp_mackey, 16))\n\t\treturn -EINVAL;\n\n\tif (crypto_memneq(ltk, exp_ltk, 16))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static int hdsp_external_sample_rate(struct hdsp *hdsp)\n{\n\tunsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);\n\tunsigned int rate_bits = status2 & HDSP_systemFrequencyMask;\n": "static int hdsp_external_sample_rate(struct hdsp *hdsp)\n{\n\tunsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);\n\tunsigned int rate_bits = status2 & HDSP_systemFrequencyMask;\n\n\t/* For the 9632 card, there seems to be no bit for indicating external\n\t * sample rate greater than 96kHz. The card reports the corresponding\n\t * single speed. So the best means seems to get spdif rate when\n\t * autosync reference is spdif */\n\tif (hdsp->io_type == H9632 &&\n\t    hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)\n\t\t return hdsp_spdif_sample_rate(hdsp);\n\n\tswitch (rate_bits) {\n\tcase HDSP_systemFrequency32:   return 32000;\n\tcase HDSP_systemFrequency44_1: return 44100;\n\tcase HDSP_systemFrequency48:   return 48000;\n\tcase HDSP_systemFrequency64:   return 64000;\n\tcase HDSP_systemFrequency88_2: return 88200;\n\tcase HDSP_systemFrequency96:   return 96000;\n\tdefault:\n\t\treturn 0;\n\t}\n}",
        "static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tu8 lid, lt, ld, bitnr;\n\tu8 key_nibble = 0;": "static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tu8 lid, lt, ld, bitnr;\n\tu8 key_nibble = 0;\n\tu64 cfg;\n\n\t/* Scan and note how parse result is going to be in key.\n\t * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from\n\t * parse result in the key. The enabled nibbles from parse result\n\t * will be concatenated in key.\n\t */\n\tcfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf));\n\tcfg &= NPC_PARSE_NIBBLE;\n\tfor_each_set_bit(bitnr, (unsigned long *)&cfg, 31) {\n\t\tnpc_scan_parse_result(mcam, bitnr, key_nibble, intf);\n\t\tkey_nibble++;\n\t}\n\n\t/* Scan and note how layer data is going to be in key */\n\tfor (lid = 0; lid < NPC_MAX_LID; lid++) {\n\t\tfor (lt = 0; lt < NPC_MAX_LT; lt++) {\n\t\t\tfor (ld = 0; ld < NPC_MAX_LD; ld++) {\n\t\t\t\tcfg = rvu_read64(rvu, blkaddr,\n\t\t\t\t\t\t NPC_AF_INTFX_LIDX_LTX_LDX_CFG\n\t\t\t\t\t\t (intf, lid, lt, ld));\n\t\t\t\tif (!FIELD_GET(NPC_LDATA_EN, cfg))\n\t\t\t\t\tcontinue;\n\t\t\t\tnpc_scan_ldata(rvu, blkaddr, lid, lt, cfg,\n\t\t\t\t\t       intf);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static void serial_out(struct uart_sunsu_port *up, int offset, int value)\n{\n#ifndef CONFIG_SPARC64\n\t/*\n\t * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are": "static void serial_out(struct uart_sunsu_port *up, int offset, int value)\n{\n#ifndef CONFIG_SPARC64\n\t/*\n\t * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are\n\t * connected with a gate then go to SlavIO. When IRQ4 goes tristated\n\t * gate outputs a logical one. Since we use level triggered interrupts\n\t * we have lockup and watchdog reset. We cannot mask IRQ because\n\t * keyboard shares IRQ with us (Word has it as Bob Smelik's design).\n\t * This problem is similar to what Alpha people suffer, see\n\t * 8250_alpha.c.\n\t */\n\tif (offset == UART_MCR)\n\t\tvalue |= UART_MCR_OUT2;\n#endif\n\toffset <<= up->port.regshift;\n\n\tswitch (up->port.iotype) {\n\tcase UPIO_HUB6:\n\t\toutb(up->port.hub6 - 1 + offset, up->port.iobase);\n\t\toutb(value, up->port.iobase + 1);\n\t\tbreak;\n\n\tcase UPIO_MEM:\n\t\twriteb(value, up->port.membase + offset);\n\t\tbreak;\n\n\tdefault:\n\t\toutb(value, up->port.iobase + offset);\n\t}\n}",
        "static int __init test_f6(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 w[16] = {\n\t\t\t0x20, 0x6e, 0x63, 0xce, 0x20, 0x6a, 0x3f, 0xfd,\n\t\t\t0x02, 0x4a, 0x08, 0xa1, 0x76, 0xf1, 0x65, 0x29 };": "static int __init test_f6(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 w[16] = {\n\t\t\t0x20, 0x6e, 0x63, 0xce, 0x20, 0x6a, 0x3f, 0xfd,\n\t\t\t0x02, 0x4a, 0x08, 0xa1, 0x76, 0xf1, 0x65, 0x29 };\n\tconst u8 n1[16] = {\n\t\t\t0xab, 0xae, 0x2b, 0x71, 0xec, 0xb2, 0xff, 0xff,\n\t\t\t0x3e, 0x73, 0x77, 0xd1, 0x54, 0x84, 0xcb, 0xd5 };\n\tconst u8 n2[16] = {\n\t\t\t0xcf, 0xc4, 0x3d, 0xff, 0xf7, 0x83, 0x65, 0x21,\n\t\t\t0x6e, 0x5f, 0xa7, 0x25, 0xcc, 0xe7, 0xe8, 0xa6 };\n\tconst u8 r[16] = {\n\t\t\t0xc8, 0x0f, 0x2d, 0x0c, 0xd2, 0x42, 0xda, 0x08,\n\t\t\t0x54, 0xbb, 0x53, 0xb4, 0x3b, 0x34, 0xa3, 0x12 };\n\tconst u8 io_cap[3] = { 0x02, 0x01, 0x01 };\n\tconst u8 a1[7] = { 0xce, 0xbf, 0x37, 0x37, 0x12, 0x56, 0x00 };\n\tconst u8 a2[7] = { 0xc1, 0xcf, 0x2d, 0x70, 0x13, 0xa7, 0x00 };\n\tconst u8 exp[16] = {\n\t\t\t0x61, 0x8f, 0x95, 0xda, 0x09, 0x0b, 0x6c, 0xd2,\n\t\t\t0xc5, 0xe8, 0xd0, 0x9c, 0x98, 0x73, 0xc4, 0xe3 };\n\tu8 res[16];\n\tint err;\n\n\terr = smp_f6(tfm_cmac, w, n1, n2, r, io_cap, a1, a2, res);\n\tif (err)\n\t\treturn err;\n\n\tif (crypto_memneq(res, exp, 16))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static int INIT get_next_block(struct bunzip_data *bd)\n{\n\tstruct group_data *hufGroup = NULL;\n\tint *base = NULL;\n\tint *limit = NULL;": "static int INIT get_next_block(struct bunzip_data *bd)\n{\n\tstruct group_data *hufGroup = NULL;\n\tint *base = NULL;\n\tint *limit = NULL;\n\tint dbufCount, nextSym, dbufSize, groupCount, selector,\n\t\ti, j, k, t, runPos, symCount, symTotal, nSelectors, *byteCount;\n\tunsigned char uc, *symToByte, *mtfSymbol, *selectors;\n\tunsigned int *dbuf, origPtr;\n\n\tdbuf = bd->dbuf;\n\tdbufSize = bd->dbufSize;\n\tselectors = bd->selectors;\n\tbyteCount = bd->byteCount;\n\tsymToByte = bd->symToByte;\n\tmtfSymbol = bd->mtfSymbol;\n\n\t/* Read in header signature and CRC, then validate signature.\n\t   (last block signature means CRC is for whole file, return now) */\n\ti = get_bits(bd, 24);\n\tj = get_bits(bd, 24);\n\tbd->headerCRC = get_bits(bd, 32);\n\tif ((i == 0x177245) && (j == 0x385090))\n\t\treturn RETVAL_LAST_BLOCK;\n\tif ((i != 0x314159) || (j != 0x265359))\n\t\treturn RETVAL_NOT_BZIP_DATA;\n\t/* We can add support for blockRandomised if anybody complains.\n\t   There was some code for this in busybox 1.0.0-pre3, but nobody ever\n\t   noticed that it didn't actually work. */\n\tif (get_bits(bd, 1))\n\t\treturn RETVAL_OBSOLETE_INPUT;\n\torigPtr = get_bits(bd, 24);\n\tif (origPtr >= dbufSize)\n\t\treturn RETVAL_DATA_ERROR;\n\t/* mapping table: if some byte values are never used (encoding things\n\t   like ascii text), the compression code removes the gaps to have fewer\n\t   symbols to deal with, and writes a sparse bitfield indicating which\n\t   values were present.  We make a translation table to convert the\n\t   symbols back to the corresponding bytes. */\n\tt = get_bits(bd, 16);\n\tsymTotal = 0;\n\tfor (i = 0; i < 16; i++) {\n\t\tif (t&(1 << (15-i))) {\n\t\t\tk = get_bits(bd, 16);\n\t\t\tfor (j = 0; j < 16; j++)\n\t\t\t\tif (k&(1 << (15-j)))\n\t\t\t\t\tsymToByte[symTotal++] = (16*i)+j;\n\t\t}\n\t}\n\t/* How many different Huffman coding groups does this block use? */\n\tgroupCount = get_bits(bd, 3);\n\tif (groupCount < 2 || groupCount > MAX_GROUPS)\n\t\treturn RETVAL_DATA_ERROR;\n\t/* nSelectors: Every GROUP_SIZE many symbols we select a new\n\t   Huffman coding group.  Read in the group selector list,\n\t   which is stored as MTF encoded bit runs.  (MTF = Move To\n\t   Front, as each value is used it's moved to the start of the\n\t   list.) */\n\tnSelectors = get_bits(bd, 15);\n\tif (!nSelectors)\n\t\treturn RETVAL_DATA_ERROR;\n\tfor (i = 0; i < groupCount; i++)\n\t\tmtfSymbol[i] = i;\n\tfor (i = 0; i < nSelectors; i++) {\n\t\t/* Get next value */\n\t\tfor (j = 0; get_bits(bd, 1); j++)\n\t\t\tif (j >= groupCount)\n\t\t\t\treturn RETVAL_DATA_ERROR;\n\t\t/* Decode MTF to get the next selector */\n\t\tuc = mtfSymbol[j];\n\t\tfor (; j; j--)\n\t\t\tmtfSymbol[j] = mtfSymbol[j-1];\n\t\tmtfSymbol[0] = selectors[i] = uc;\n\t}\n\t/* Read the Huffman coding tables for each group, which code\n\t   for symTotal literal symbols, plus two run symbols (RUNA,\n\t   RUNB) */\n\tsymCount = symTotal+2;\n\tfor (j = 0; j < groupCount; j++) {\n\t\tunsigned char length[MAX_SYMBOLS], temp[MAX_HUFCODE_BITS+1];\n\t\tint\tminLen,\tmaxLen, pp;\n\t\t/* Read Huffman code lengths for each symbol.  They're\n\t\t   stored in a way similar to mtf; record a starting\n\t\t   value for the first symbol, and an offset from the\n\t\t   previous value for everys symbol after that.\n\t\t   (Subtracting 1 before the loop and then adding it\n\t\t   back at the end is an optimization that makes the\n\t\t   test inside the loop simpler: symbol length 0\n\t\t   becomes negative, so an unsigned inequality catches\n\t\t   it.) */\n\t\tt = get_bits(bd, 5)-1;\n\t\tfor (i = 0; i < symCount; i++) {\n\t\t\tfor (;;) {\n\t\t\t\tif (((unsigned)t) > (MAX_HUFCODE_BITS-1))\n\t\t\t\t\treturn RETVAL_DATA_ERROR;\n\n\t\t\t\t/* If first bit is 0, stop.  Else\n\t\t\t\t   second bit indicates whether to\n\t\t\t\t   increment or decrement the value.\n\t\t\t\t   Optimization: grab 2 bits and unget\n\t\t\t\t   the second if the first was 0. */\n\n\t\t\t\tk = get_bits(bd, 2);\n\t\t\t\tif (k < 2) {\n\t\t\t\t\tbd->inbufBitCount++;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\t/* Add one if second bit 1, else\n\t\t\t\t * subtract 1.  Avoids if/else */\n\t\t\t\tt += (((k+1)&2)-1);\n\t\t\t}\n\t\t\t/* Correct for the initial -1, to get the\n\t\t\t * final symbol length */\n\t\t\tlength[i] = t+1;\n\t\t}\n\t\t/* Find largest and smallest lengths in this group */\n\t\tminLen = maxLen = length[0];\n\n\t\tfor (i = 1; i < symCount; i++) {\n\t\t\tif (length[i] > maxLen)\n\t\t\t\tmaxLen = length[i];\n\t\t\telse if (length[i] < minLen)\n\t\t\t\tminLen = length[i];\n\t\t}\n\n\t\t/* Calculate permute[], base[], and limit[] tables from\n\t\t * length[].\n\t\t *\n\t\t * permute[] is the lookup table for converting\n\t\t * Huffman coded symbols into decoded symbols.  base[]\n\t\t * is the amount to subtract from the value of a\n\t\t * Huffman symbol of a given length when using\n\t\t * permute[].\n\t\t *\n\t\t * limit[] indicates the largest numerical value a\n\t\t * symbol with a given number of bits can have.  This\n\t\t * is how the Huffman codes can vary in length: each\n\t\t * code with a value > limit[length] needs another\n\t\t * bit.\n\t\t */\n\t\thufGroup = bd->groups+j;\n\t\thufGroup->minLen = minLen;\n\t\thufGroup->maxLen = maxLen;\n\t\t/* Note that minLen can't be smaller than 1, so we\n\t\t   adjust the base and limit array pointers so we're\n\t\t   not always wasting the first entry.  We do this\n\t\t   again when using them (during symbol decoding).*/\n\t\tbase = hufGroup->base-1;\n\t\tlimit = hufGroup->limit-1;\n\t\t/* Calculate permute[].  Concurrently, initialize\n\t\t * temp[] and limit[]. */\n\t\tpp = 0;\n\t\tfor (i = minLen; i <= maxLen; i++) {\n\t\t\ttemp[i] = limit[i] = 0;\n\t\t\tfor (t = 0; t < symCount; t++)\n\t\t\t\tif (length[t] == i)\n\t\t\t\t\thufGroup->permute[pp++] = t;\n\t\t}\n\t\t/* Count symbols coded for at each bit length */\n\t\tfor (i = 0; i < symCount; i++)\n\t\t\ttemp[length[i]]++;\n\t\t/* Calculate limit[] (the largest symbol-coding value\n\t\t *at each bit length, which is (previous limit <<\n\t\t *1)+symbols at this level), and base[] (number of\n\t\t *symbols to ignore at each bit length, which is limit\n\t\t *minus the cumulative count of symbols coded for\n\t\t *already). */\n\t\tpp = t = 0;\n\t\tfor (i = minLen; i < maxLen; i++) {\n\t\t\tpp += temp[i];\n\t\t\t/* We read the largest possible symbol size\n\t\t\t   and then unget bits after determining how\n\t\t\t   many we need, and those extra bits could be\n\t\t\t   set to anything.  (They're noise from\n\t\t\t   future symbols.)  At each level we're\n\t\t\t   really only interested in the first few\n\t\t\t   bits, so here we set all the trailing\n\t\t\t   to-be-ignored bits to 1 so they don't\n\t\t\t   affect the value > limit[length]\n\t\t\t   comparison. */\n\t\t\tlimit[i] = (pp << (maxLen - i)) - 1;\n\t\t\tpp <<= 1;\n\t\t\tbase[i+1] = pp-(t += temp[i]);\n\t\t}\n\t\tlimit[maxLen+1] = INT_MAX; /* Sentinel value for\n\t\t\t\t\t    * reading next sym. */\n\t\tlimit[maxLen] = pp+temp[maxLen]-1;\n\t\tbase[minLen] = 0;\n\t}\n\t/* We've finished reading and digesting the block header.  Now\n\t   read this block's Huffman coded symbols from the file and\n\t   undo the Huffman coding and run length encoding, saving the\n\t   result into dbuf[dbufCount++] = uc */\n\n\t/* Initialize symbol occurrence counters and symbol Move To\n\t * Front table */\n\tfor (i = 0; i < 256; i++) {\n\t\tbyteCount[i] = 0;\n\t\tmtfSymbol[i] = (unsigned char)i;\n\t}\n\t/* Loop through compressed symbols. */\n\trunPos = dbufCount = symCount = selector = 0;\n\tfor (;;) {\n\t\t/* Determine which Huffman coding group to use. */\n\t\tif (!(symCount--)) {\n\t\t\tsymCount = GROUP_SIZE-1;\n\t\t\tif (selector >= nSelectors)\n\t\t\t\treturn RETVAL_DATA_ERROR;\n\t\t\thufGroup = bd->groups+selectors[selector++];\n\t\t\tbase = hufGroup->base-1;\n\t\t\tlimit = hufGroup->limit-1;\n\t\t}\n\t\t/* Read next Huffman-coded symbol. */\n\t\t/* Note: It is far cheaper to read maxLen bits and\n\t\t   back up than it is to read minLen bits and then an\n\t\t   additional bit at a time, testing as we go.\n\t\t   Because there is a trailing last block (with file\n\t\t   CRC), there is no danger of the overread causing an\n\t\t   unexpected EOF for a valid compressed file.  As a\n\t\t   further optimization, we do the read inline\n\t\t   (falling back to a call to get_bits if the buffer\n\t\t   runs dry).  The following (up to got_huff_bits:) is\n\t\t   equivalent to j = get_bits(bd, hufGroup->maxLen);\n\t\t */\n\t\twhile (bd->inbufBitCount < hufGroup->maxLen) {\n\t\t\tif (bd->inbufPos == bd->inbufCount) {\n\t\t\t\tj = get_bits(bd, hufGroup->maxLen);\n\t\t\t\tgoto got_huff_bits;\n\t\t\t}\n\t\t\tbd->inbufBits =\n\t\t\t\t(bd->inbufBits << 8)|bd->inbuf[bd->inbufPos++];\n\t\t\tbd->inbufBitCount += 8;\n\t\t}\n\t\tbd->inbufBitCount -= hufGroup->maxLen;\n\t\tj = (bd->inbufBits >> bd->inbufBitCount)&\n\t\t\t((1 << hufGroup->maxLen)-1);\ngot_huff_bits:\n\t\t/* Figure how many bits are in next symbol and\n\t\t * unget extras */\n\t\ti = hufGroup->minLen;\n\t\twhile (j > limit[i])\n\t\t\t++i;\n\t\tbd->inbufBitCount += (hufGroup->maxLen - i);\n\t\t/* Huffman decode value to get nextSym (with bounds checking) */\n\t\tif ((i > hufGroup->maxLen)\n\t\t\t|| (((unsigned)(j = (j>>(hufGroup->maxLen-i))-base[i]))\n\t\t\t\t>= MAX_SYMBOLS))\n\t\t\treturn RETVAL_DATA_ERROR;\n\t\tnextSym = hufGroup->permute[j];\n\t\t/* We have now decoded the symbol, which indicates\n\t\t   either a new literal byte, or a repeated run of the\n\t\t   most recent literal byte.  First, check if nextSym\n\t\t   indicates a repeated run, and if so loop collecting\n\t\t   how many times to repeat the last literal. */\n\t\tif (((unsigned)nextSym) <= SYMBOL_RUNB) { /* RUNA or RUNB */\n\t\t\t/* If this is the start of a new run, zero out\n\t\t\t * counter */\n\t\t\tif (!runPos) {\n\t\t\t\trunPos = 1;\n\t\t\t\tt = 0;\n\t\t\t}\n\t\t\t/* Neat trick that saves 1 symbol: instead of\n\t\t\t   or-ing 0 or 1 at each bit position, add 1\n\t\t\t   or 2 instead.  For example, 1011 is 1 << 0\n\t\t\t   + 1 << 1 + 2 << 2.  1010 is 2 << 0 + 2 << 1\n\t\t\t   + 1 << 2.  You can make any bit pattern\n\t\t\t   that way using 1 less symbol than the basic\n\t\t\t   or 0/1 method (except all bits 0, which\n\t\t\t   would use no symbols, but a run of length 0\n\t\t\t   doesn't mean anything in this context).\n\t\t\t   Thus space is saved. */\n\t\t\tt += (runPos << nextSym);\n\t\t\t/* +runPos if RUNA; +2*runPos if RUNB */\n\n\t\t\trunPos <<= 1;\n\t\t\tcontinue;\n\t\t}\n\t\t/* When we hit the first non-run symbol after a run,\n\t\t   we now know how many times to repeat the last\n\t\t   literal, so append that many copies to our buffer\n\t\t   of decoded symbols (dbuf) now.  (The last literal\n\t\t   used is the one at the head of the mtfSymbol\n\t\t   array.) */\n\t\tif (runPos) {\n\t\t\trunPos = 0;\n\t\t\tif (dbufCount+t >= dbufSize)\n\t\t\t\treturn RETVAL_DATA_ERROR;\n\n\t\t\tuc = symToByte[mtfSymbol[0]];\n\t\t\tbyteCount[uc] += t;\n\t\t\twhile (t--)\n\t\t\t\tdbuf[dbufCount++] = uc;\n\t\t}\n\t\t/* Is this the terminating symbol? */\n\t\tif (nextSym > symTotal)\n\t\t\tbreak;\n\t\t/* At this point, nextSym indicates a new literal\n\t\t   character.  Subtract one to get the position in the\n\t\t   MTF array at which this literal is currently to be\n\t\t   found.  (Note that the result can't be -1 or 0,\n\t\t   because 0 and 1 are RUNA and RUNB.  But another\n\t\t   instance of the first symbol in the mtf array,\n\t\t   position 0, would have been handled as part of a\n\t\t   run above.  Therefore 1 unused mtf position minus 2\n\t\t   non-literal nextSym values equals -1.) */\n\t\tif (dbufCount >= dbufSize)\n\t\t\treturn RETVAL_DATA_ERROR;\n\t\ti = nextSym - 1;\n\t\tuc = mtfSymbol[i];\n\t\t/* Adjust the MTF array.  Since we typically expect to\n\t\t *move only a small number of symbols, and are bound\n\t\t *by 256 in any case, using memmove here would\n\t\t *typically be bigger and slower due to function call\n\t\t *overhead and other assorted setup costs. */\n\t\tdo {\n\t\t\tmtfSymbol[i] = mtfSymbol[i-1];\n\t\t} while (--i);\n\t\tmtfSymbol[0] = uc;\n\t\tuc = symToByte[uc];\n\t\t/* We have our literal byte.  Save it into dbuf. */\n\t\tbyteCount[uc]++;\n\t\tdbuf[dbufCount++] = (unsigned int)uc;\n\t}\n\t/* At this point, we've read all the Huffman-coded symbols\n\t   (and repeated runs) for this block from the input stream,\n\t   and decoded them into the intermediate buffer.  There are\n\t   dbufCount many decoded bytes in dbuf[].  Now undo the\n\t   Burrows-Wheeler transform on dbuf.  See\n\t   http://dogma.net/markn/articles/bwt/bwt.htm\n\t */\n\t/* Turn byteCount into cumulative occurrence counts of 0 to n-1. */\n\tj = 0;\n\tfor (i = 0; i < 256; i++) {\n\t\tk = j+byteCount[i];\n\t\tbyteCount[i] = j;\n\t\tj = k;\n\t}\n\t/* Figure out what order dbuf would be in if we sorted it. */\n\tfor (i = 0; i < dbufCount; i++) {\n\t\tuc = (unsigned char)(dbuf[i] & 0xff);\n\t\tdbuf[byteCount[uc]] |= (i << 8);\n\t\tbyteCount[uc]++;\n\t}\n\t/* Decode first byte by hand to initialize \"previous\" byte.\n\t   Note that it doesn't get output, and if the first three\n\t   characters are identical it doesn't qualify as a run (hence\n\t   writeRunCountdown = 5). */\n\tif (dbufCount) {\n\t\tif (origPtr >= dbufCount)\n\t\t\treturn RETVAL_DATA_ERROR;\n\t\tbd->writePos = dbuf[origPtr];\n\t\tbd->writeCurrent = (unsigned char)(bd->writePos&0xff);\n\t\tbd->writePos >>= 8;\n\t\tbd->writeRunCountdown = 5;\n\t}\n\tbd->writeCount = dbufCount;\n\n\treturn RETVAL_OK;\n}",
        "static int io_splice(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_splice *sp = &req->splice;\n\tstruct file *out = sp->file_out;\n\tunsigned int flags = sp->flags & ~SPLICE_F_FD_IN_FIXED;": "static int io_splice(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_splice *sp = &req->splice;\n\tstruct file *out = sp->file_out;\n\tunsigned int flags = sp->flags & ~SPLICE_F_FD_IN_FIXED;\n\tloff_t *poff_in, *poff_out;\n\tstruct file *in;\n\tlong ret = 0;\n\n\tif (issue_flags & IO_URING_F_NONBLOCK)\n\t\treturn -EAGAIN;\n\n\tif (sp->flags & SPLICE_F_FD_IN_FIXED)\n\t\tin = io_file_get_fixed(req, sp->splice_fd_in, issue_flags);\n\telse\n\t\tin = io_file_get_normal(req, sp->splice_fd_in);\n\tif (!in) {\n\t\tret = -EBADF;\n\t\tgoto done;\n\t}\n\n\tpoff_in = (sp->off_in == -1) ? NULL : &sp->off_in;\n\tpoff_out = (sp->off_out == -1) ? NULL : &sp->off_out;\n\n\tif (sp->len)\n\t\tret = do_splice(in, poff_in, out, poff_out, sp->len, flags);\n\n\tif (!(sp->flags & SPLICE_F_FD_IN_FIXED))\n\t\tio_put_file(in);\ndone:\n\tif (ret != sp->len)\n\t\treq_set_fail(req);\n\t__io_req_complete(req, 0, ret, 0);\n\treturn 0;\n}",
        "static void test_copy_key(void)\n{\n\tstruct test_default t = test_default_init(guest_copy_key);\n\n\tHOST_SYNC(t.vcpu, STAGE_SKEYS_SET);": "static void test_copy_key(void)\n{\n\tstruct test_default t = test_default_init(guest_copy_key);\n\n\tHOST_SYNC(t.vcpu, STAGE_SKEYS_SET);\n\n\t/* vm, no key */\n\tDEFAULT_WRITE_READ(t.vcpu, t.vm, ABSOLUTE, t.size);\n\n\t/* vm/vcpu, machting key or key 0 */\n\tDEFAULT_WRITE_READ(t.vcpu, t.vcpu, LOGICAL, t.size, KEY(0));\n\tDEFAULT_WRITE_READ(t.vcpu, t.vcpu, LOGICAL, t.size, KEY(9));\n\tDEFAULT_WRITE_READ(t.vcpu, t.vm, ABSOLUTE, t.size, KEY(0));\n\tDEFAULT_WRITE_READ(t.vcpu, t.vm, ABSOLUTE, t.size, KEY(9));\n\t/*\n\t * There used to be different code paths for key handling depending on\n\t * if the region crossed a page boundary.\n\t * There currently are not, but the more tests the merrier.\n\t */\n\tDEFAULT_WRITE_READ(t.vcpu, t.vcpu, LOGICAL, 1, KEY(0));\n\tDEFAULT_WRITE_READ(t.vcpu, t.vcpu, LOGICAL, 1, KEY(9));\n\tDEFAULT_WRITE_READ(t.vcpu, t.vm, ABSOLUTE, 1, KEY(0));\n\tDEFAULT_WRITE_READ(t.vcpu, t.vm, ABSOLUTE, 1, KEY(9));\n\n\t/* vm/vcpu, mismatching keys on read, but no fetch protection */\n\tDEFAULT_READ(t.vcpu, t.vcpu, LOGICAL, t.size, GADDR_V(mem2), KEY(2));\n\tDEFAULT_READ(t.vcpu, t.vm, ABSOLUTE, t.size, GADDR_V(mem1), KEY(2));\n\n\tkvm_vm_free(t.kvm_vm);\n}",
        "static void bpf_fill_jump_around_ld_abs(struct bpf_test *self)\n{\n\tstruct bpf_insn *insn = self->fill_insns;\n\t/* jump range is limited to 16 bit. every ld_abs is replaced by 6 insns,\n\t * but on arches like arm, ppc etc, there will be one BPF_ZEXT inserted": "static void bpf_fill_jump_around_ld_abs(struct bpf_test *self)\n{\n\tstruct bpf_insn *insn = self->fill_insns;\n\t/* jump range is limited to 16 bit. every ld_abs is replaced by 6 insns,\n\t * but on arches like arm, ppc etc, there will be one BPF_ZEXT inserted\n\t * to extend the error value of the inlined ld_abs sequence which then\n\t * contains 7 insns. so, set the dividend to 7 so the testcase could\n\t * work on all arches.\n\t */\n\tunsigned int len = (1 << 15) / 7;\n\tint i = 0;\n\n\tinsn[i++] = BPF_MOV64_REG(BPF_REG_6, BPF_REG_1);\n\tinsn[i++] = BPF_LD_ABS(BPF_B, 0);\n\tinsn[i] = BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 10, len - i - 2);\n\ti++;\n\twhile (i < len - 1)\n\t\tinsn[i++] = BPF_LD_ABS(BPF_B, 1);\n\tinsn[i] = BPF_EXIT_INSN();\n\tself->prog_len = i + 1;\n}",
        "static int __init thermal_init(struct ibm_init_struct *iibm)\n{\n\tu8 t, ta1, ta2, ver = 0;\n\tint i;\n\tint acpi_tmp7;": "static int __init thermal_init(struct ibm_init_struct *iibm)\n{\n\tu8 t, ta1, ta2, ver = 0;\n\tint i;\n\tint acpi_tmp7;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing thermal subdriver\\n\");\n\n\tacpi_tmp7 = acpi_evalf(ec_handle, NULL, \"TMP7\", \"qv\");\n\n\tif (thinkpad_id.ec_model) {\n\t\t/*\n\t\t * Direct EC access mode: sensors at registers\n\t\t * 0x78-0x7F, 0xC0-0xC7.  Registers return 0x00 for\n\t\t * non-implemented, thermal sensors return 0x80 when\n\t\t * not available\n\t\t * The above rule is unfortunately flawed. This has been seen with\n\t\t * 0xC2 (power supply ID) causing thermal control problems.\n\t\t * The EC version can be determined by offset 0xEF and at least for\n\t\t * version 3 the Lenovo firmware team confirmed that registers 0xC0-0xC7\n\t\t * are not thermal registers.\n\t\t */\n\t\tif (!acpi_ec_read(TP_EC_FUNCREV, &ver))\n\t\t\tpr_warn(\"Thinkpad ACPI EC unable to access EC version\\n\");\n\n\t\tta1 = ta2 = 0;\n\t\tfor (i = 0; i < 8; i++) {\n\t\t\tif (acpi_ec_read(TP_EC_THERMAL_TMP0 + i, &t)) {\n\t\t\t\tta1 |= t;\n\t\t\t} else {\n\t\t\t\tta1 = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (ver < 3) {\n\t\t\t\tif (acpi_ec_read(TP_EC_THERMAL_TMP8 + i, &t)) {\n\t\t\t\t\tta2 |= t;\n\t\t\t\t} else {\n\t\t\t\t\tta1 = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (ta1 == 0) {\n\t\t\t/* This is sheer paranoia, but we handle it anyway */\n\t\t\tif (acpi_tmp7) {\n\t\t\t\tpr_err(\"ThinkPad ACPI EC access misbehaving, falling back to ACPI TMPx access mode\\n\");\n\t\t\t\tthermal_read_mode = TPACPI_THERMAL_ACPI_TMP07;\n\t\t\t} else {\n\t\t\t\tpr_err(\"ThinkPad ACPI EC access misbehaving, disabling thermal sensors access\\n\");\n\t\t\t\tthermal_read_mode = TPACPI_THERMAL_NONE;\n\t\t\t}\n\t\t} else {\n\t\t\tif (ver >= 3) {\n\t\t\t\tthermal_read_mode = TPACPI_THERMAL_TPEC_8;\n\t\t\t\tthermal_use_labels = true;\n\t\t\t} else {\n\t\t\t\tthermal_read_mode =\n\t\t\t\t\t(ta2 != 0) ?\n\t\t\t\t\tTPACPI_THERMAL_TPEC_16 : TPACPI_THERMAL_TPEC_8;\n\t\t\t}\n\t\t}\n\t} else if (acpi_tmp7) {\n\t\tif (tpacpi_is_ibm() &&\n\t\t    acpi_evalf(ec_handle, NULL, \"UPDT\", \"qv\")) {\n\t\t\t/* 600e/x, 770e, 770x */\n\t\t\tthermal_read_mode = TPACPI_THERMAL_ACPI_UPDT;\n\t\t} else {\n\t\t\t/* IBM/LENOVO DSDT EC.TMPx access, max 8 sensors */\n\t\t\tthermal_read_mode = TPACPI_THERMAL_ACPI_TMP07;\n\t\t}\n\t} else {\n\t\t/* temperatures not supported on 570, G4x, R30, R31, R32 */\n\t\tthermal_read_mode = TPACPI_THERMAL_NONE;\n\t}\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"thermal is %s, mode %d\\n\",\n\t\tstr_supported(thermal_read_mode != TPACPI_THERMAL_NONE),\n\t\tthermal_read_mode);\n\n\treturn thermal_read_mode != TPACPI_THERMAL_NONE ? 0 : -ENODEV;\n}",
        "static void bpf_tramp_image_put(struct bpf_tramp_image *im)\n{\n\t/* The trampoline image that calls original function is using:\n\t * rcu_read_lock_trace to protect sleepable bpf progs\n\t * rcu_read_lock to protect normal bpf progs": "static void bpf_tramp_image_put(struct bpf_tramp_image *im)\n{\n\t/* The trampoline image that calls original function is using:\n\t * rcu_read_lock_trace to protect sleepable bpf progs\n\t * rcu_read_lock to protect normal bpf progs\n\t * percpu_ref to protect trampoline itself\n\t * rcu tasks to protect trampoline asm not covered by percpu_ref\n\t * (which are few asm insns before __bpf_tramp_enter and\n\t *  after __bpf_tramp_exit)\n\t *\n\t * The trampoline is unreachable before bpf_tramp_image_put().\n\t *\n\t * First, patch the trampoline to avoid calling into fexit progs.\n\t * The progs will be freed even if the original function is still\n\t * executing or sleeping.\n\t * In case of CONFIG_PREEMPT=y use call_rcu_tasks() to wait on\n\t * first few asm instructions to execute and call into\n\t * __bpf_tramp_enter->percpu_ref_get.\n\t * Then use percpu_ref_kill to wait for the trampoline and the original\n\t * function to finish.\n\t * Then use call_rcu_tasks() to make sure few asm insns in\n\t * the trampoline epilogue are done as well.\n\t *\n\t * In !PREEMPT case the task that got interrupted in the first asm\n\t * insns won't go through an RCU quiescent state which the\n\t * percpu_ref_kill will be waiting for. Hence the first\n\t * call_rcu_tasks() is not necessary.\n\t */\n\tif (im->ip_after_call) {\n\t\tint err = bpf_arch_text_poke(im->ip_after_call, BPF_MOD_JUMP,\n\t\t\t\t\t     NULL, im->ip_epilogue);\n\t\tWARN_ON(err);\n\t\tif (IS_ENABLED(CONFIG_PREEMPTION))\n\t\t\tcall_rcu_tasks(&im->rcu, __bpf_tramp_image_put_rcu_tasks);\n\t\telse\n\t\t\tpercpu_ref_kill(&im->pcref);\n\t\treturn;\n\t}\n\n\t/* The trampoline without fexit and fmod_ret progs doesn't call original\n\t * function and doesn't use percpu_ref.\n\t * Use call_rcu_tasks_trace() to wait for sleepable progs to finish.\n\t * Then use call_rcu_tasks() to wait for the rest of trampoline asm\n\t * and normal progs.\n\t */\n\tcall_rcu_tasks_trace(&im->rcu, __bpf_tramp_image_put_rcu_tasks);\n}",
        "static int __init hotkey_init(struct ibm_init_struct *iibm)\n{\n\t/* Requirements for changing the default keymaps:\n\t *\n\t * 1. Many of the keys are mapped to KEY_RESERVED for very": "static int __init hotkey_init(struct ibm_init_struct *iibm)\n{\n\t/* Requirements for changing the default keymaps:\n\t *\n\t * 1. Many of the keys are mapped to KEY_RESERVED for very\n\t *    good reasons.  Do not change them unless you have deep\n\t *    knowledge on the IBM and Lenovo ThinkPad firmware for\n\t *    the various ThinkPad models.  The driver behaves\n\t *    differently for KEY_RESERVED: such keys have their\n\t *    hot key mask *unset* in mask_recommended, and also\n\t *    in the initial hot key mask programmed into the\n\t *    firmware at driver load time, which means the firm-\n\t *    ware may react very differently if you change them to\n\t *    something else;\n\t *\n\t * 2. You must be subscribed to the linux-thinkpad and\n\t *    ibm-acpi-devel mailing lists, and you should read the\n\t *    list archives since 2007 if you want to change the\n\t *    keymaps.  This requirement exists so that you will\n\t *    know the past history of problems with the thinkpad-\n\t *    acpi driver keymaps, and also that you will be\n\t *    listening to any bug reports;\n\t *\n\t * 3. Do not send thinkpad-acpi specific patches directly to\n\t *    for merging, *ever*.  Send them to the linux-acpi\n\t *    mailinglist for comments.  Merging is to be done only\n\t *    through acpi-test and the ACPI maintainer.\n\t *\n\t * If the above is too much to ask, don't change the keymap.\n\t * Ask the thinkpad-acpi maintainer to do it, instead.\n\t */\n\n\tenum keymap_index {\n\t\tTPACPI_KEYMAP_IBM_GENERIC = 0,\n\t\tTPACPI_KEYMAP_LENOVO_GENERIC,\n\t};\n\n\tstatic const tpacpi_keymap_t tpacpi_keymaps[] __initconst = {\n\t/* Generic keymap for IBM ThinkPads */\n\t[TPACPI_KEYMAP_IBM_GENERIC] = {\n\t\t/* Scan Codes 0x00 to 0x0B: ACPI HKEY FN+F1..F12 */\n\t\tKEY_FN_F1,\tKEY_BATTERY,\tKEY_COFFEE,\tKEY_SLEEP,\n\t\tKEY_WLAN,\tKEY_FN_F6, KEY_SWITCHVIDEOMODE, KEY_FN_F8,\n\t\tKEY_FN_F9,\tKEY_FN_F10,\tKEY_FN_F11,\tKEY_SUSPEND,\n\n\t\t/* Scan codes 0x0C to 0x1F: Other ACPI HKEY hot keys */\n\t\tKEY_UNKNOWN,\t/* 0x0C: FN+BACKSPACE */\n\t\tKEY_UNKNOWN,\t/* 0x0D: FN+INSERT */\n\t\tKEY_UNKNOWN,\t/* 0x0E: FN+DELETE */\n\n\t\t/* brightness: firmware always reacts to them */\n\t\tKEY_RESERVED,\t/* 0x0F: FN+HOME (brightness up) */\n\t\tKEY_RESERVED,\t/* 0x10: FN+END (brightness down) */\n\n\t\t/* Thinklight: firmware always react to it */\n\t\tKEY_RESERVED,\t/* 0x11: FN+PGUP (thinklight toggle) */\n\n\t\tKEY_UNKNOWN,\t/* 0x12: FN+PGDOWN */\n\t\tKEY_ZOOM,\t/* 0x13: FN+SPACE (zoom) */\n\n\t\t/* Volume: firmware always react to it and reprograms\n\t\t * the built-in *extra* mixer.  Never map it to control\n\t\t * another mixer by default. */\n\t\tKEY_RESERVED,\t/* 0x14: VOLUME UP */\n\t\tKEY_RESERVED,\t/* 0x15: VOLUME DOWN */\n\t\tKEY_RESERVED,\t/* 0x16: MUTE */\n\n\t\tKEY_VENDOR,\t/* 0x17: Thinkpad/AccessIBM/Lenovo */\n\n\t\t/* (assignments unknown, please report if found) */\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\n\t\t/* No assignments, only used for Adaptive keyboards. */\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\n\t\t/* No assignment, used for newer Lenovo models */\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN\n\n\t\t},\n\n\t/* Generic keymap for Lenovo ThinkPads */\n\t[TPACPI_KEYMAP_LENOVO_GENERIC] = {\n\t\t/* Scan Codes 0x00 to 0x0B: ACPI HKEY FN+F1..F12 */\n\t\tKEY_FN_F1,\tKEY_COFFEE,\tKEY_BATTERY,\tKEY_SLEEP,\n\t\tKEY_WLAN,\tKEY_CAMERA, KEY_SWITCHVIDEOMODE, KEY_FN_F8,\n\t\tKEY_FN_F9,\tKEY_FN_F10,\tKEY_FN_F11,\tKEY_SUSPEND,\n\n\t\t/* Scan codes 0x0C to 0x1F: Other ACPI HKEY hot keys */\n\t\tKEY_UNKNOWN,\t/* 0x0C: FN+BACKSPACE */\n\t\tKEY_UNKNOWN,\t/* 0x0D: FN+INSERT */\n\t\tKEY_UNKNOWN,\t/* 0x0E: FN+DELETE */\n\n\t\t/* These should be enabled --only-- when ACPI video\n\t\t * is disabled (i.e. in \"vendor\" mode), and are handled\n\t\t * in a special way by the init code */\n\t\tKEY_BRIGHTNESSUP,\t/* 0x0F: FN+HOME (brightness up) */\n\t\tKEY_BRIGHTNESSDOWN,\t/* 0x10: FN+END (brightness down) */\n\n\t\tKEY_RESERVED,\t/* 0x11: FN+PGUP (thinklight toggle) */\n\n\t\tKEY_UNKNOWN,\t/* 0x12: FN+PGDOWN */\n\t\tKEY_ZOOM,\t/* 0x13: FN+SPACE (zoom) */\n\n\t\t/* Volume: z60/z61, T60 (BIOS version?): firmware always\n\t\t * react to it and reprograms the built-in *extra* mixer.\n\t\t * Never map it to control another mixer by default.\n\t\t *\n\t\t * T60?, T61, R60?, R61: firmware and EC tries to send\n\t\t * these over the regular keyboard, so these are no-ops,\n\t\t * but there are still weird bugs re. MUTE, so do not\n\t\t * change unless you get test reports from all Lenovo\n\t\t * models.  May cause the BIOS to interfere with the\n\t\t * HDA mixer.\n\t\t */\n\t\tKEY_RESERVED,\t/* 0x14: VOLUME UP */\n\t\tKEY_RESERVED,\t/* 0x15: VOLUME DOWN */\n\t\tKEY_RESERVED,\t/* 0x16: MUTE */\n\n\t\tKEY_VENDOR,\t/* 0x17: Thinkpad/AccessIBM/Lenovo */\n\n\t\t/* (assignments unknown, please report if found) */\n\t\tKEY_UNKNOWN, KEY_UNKNOWN,\n\n\t\t/*\n\t\t * The mic mute button only sends 0x1a.  It does not\n\t\t * automatically mute the mic or change the mute light.\n\t\t */\n\t\tKEY_MICMUTE,\t/* 0x1a: Mic mute (since ?400 or so) */\n\n\t\t/* (assignments unknown, please report if found) */\n\t\tKEY_UNKNOWN,\n\n\t\t/* Extra keys in use since the X240 / T440 / T540 */\n\t\tKEY_CONFIG, KEY_SEARCH, KEY_SCALE, KEY_FILE,\n\n\t\t/*\n\t\t * These are the adaptive keyboard keycodes for Carbon X1 2014.\n\t\t * The first item in this list is the Mute button which is\n\t\t * emitted with 0x103 through\n\t\t * adaptive_keyboard_hotkey_notify_hotkey() when the sound\n\t\t * symbol is held.\n\t\t * We'll need to offset those by 0x20.\n\t\t */\n\t\tKEY_RESERVED,        /* Mute held, 0x103 */\n\t\tKEY_BRIGHTNESS_MIN,  /* Backlight off */\n\t\tKEY_RESERVED,        /* Clipping tool */\n\t\tKEY_RESERVED,        /* Cloud */\n\t\tKEY_RESERVED,\n\t\tKEY_VOICECOMMAND,    /* Voice */\n\t\tKEY_RESERVED,\n\t\tKEY_RESERVED,        /* Gestures */\n\t\tKEY_RESERVED,\n\t\tKEY_RESERVED,\n\t\tKEY_RESERVED,\n\t\tKEY_CONFIG,          /* Settings */\n\t\tKEY_RESERVED,        /* New tab */\n\t\tKEY_REFRESH,         /* Reload */\n\t\tKEY_BACK,            /* Back */\n\t\tKEY_RESERVED,        /* Microphone down */\n\t\tKEY_RESERVED,        /* Microphone up */\n\t\tKEY_RESERVED,        /* Microphone cancellation */\n\t\tKEY_RESERVED,        /* Camera mode */\n\t\tKEY_RESERVED,        /* Rotate display, 0x116 */\n\n\t\t/*\n\t\t * These are found in 2017 models (e.g. T470s, X270).\n\t\t * The lowest known value is 0x311, which according to\n\t\t * the manual should launch a user defined favorite\n\t\t * application.\n\t\t *\n\t\t * The offset for these is TP_ACPI_HOTKEYSCAN_EXTENDED_START,\n\t\t * corresponding to 0x34.\n\t\t */\n\n\t\t/* (assignments unknown, please report if found) */\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,\n\t\tKEY_UNKNOWN,\n\n\t\tKEY_BOOKMARKS,\t\t\t/* Favorite app, 0x311 */\n\t\tKEY_SELECTIVE_SCREENSHOT,\t/* Clipping tool */\n\t\tKEY_CALC,\t\t\t/* Calculator (above numpad, P52) */\n\t\tKEY_BLUETOOTH,\t\t\t/* Bluetooth */\n\t\tKEY_KEYBOARD,\t\t\t/* Keyboard, 0x315 */\n\t\tKEY_FN_RIGHT_SHIFT,\t\t/* Fn + right Shift */\n\t\tKEY_NOTIFICATION_CENTER,\t/* Notification Center */\n\t\tKEY_PICKUP_PHONE,\t\t/* Answer incoming call */\n\t\tKEY_HANGUP_PHONE,\t\t/* Decline incoming call */\n\t\t},\n\t};\n\n\tstatic const struct tpacpi_quirk tpacpi_keymap_qtable[] __initconst = {\n\t\t/* Generic maps (fallback) */\n\t\t{\n\t\t  .vendor = PCI_VENDOR_ID_IBM,\n\t\t  .bios = TPACPI_MATCH_ANY, .ec = TPACPI_MATCH_ANY,\n\t\t  .quirks = TPACPI_KEYMAP_IBM_GENERIC,\n\t\t},\n\t\t{\n\t\t  .vendor = PCI_VENDOR_ID_LENOVO,\n\t\t  .bios = TPACPI_MATCH_ANY, .ec = TPACPI_MATCH_ANY,\n\t\t  .quirks = TPACPI_KEYMAP_LENOVO_GENERIC,\n\t\t},\n\t};\n\n#define TPACPI_HOTKEY_MAP_SIZE\t\tsizeof(tpacpi_keymap_t)\n#define TPACPI_HOTKEY_MAP_TYPESIZE\tsizeof(tpacpi_keymap_entry_t)\n\n\tint res, i;\n\tint status;\n\tint hkeyv;\n\tbool radiosw_state  = false;\n\tbool tabletsw_state = false;\n\n\tunsigned long quirks;\n\tunsigned long keymap_id;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t\t\"initializing hotkey subdriver\\n\");\n\n\tBUG_ON(!tpacpi_inputdev);\n\tBUG_ON(tpacpi_inputdev->open != NULL ||\n\t       tpacpi_inputdev->close != NULL);\n\n\tTPACPI_ACPIHANDLE_INIT(hkey);\n\tmutex_init(&hotkey_mutex);\n\n#ifdef CONFIG_THINKPAD_ACPI_HOTKEY_POLL\n\tmutex_init(&hotkey_thread_data_mutex);\n#endif\n\n\t/* hotkey not supported on 570 */\n\ttp_features.hotkey = hkey_handle != NULL;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t\"hotkeys are %s\\n\",\n\t\tstr_supported(tp_features.hotkey));\n\n\tif (!tp_features.hotkey)\n\t\treturn -ENODEV;\n\n\tquirks = tpacpi_check_quirks(tpacpi_hotkey_qtable,\n\t\t\t\t     ARRAY_SIZE(tpacpi_hotkey_qtable));\n\n\ttpacpi_disable_brightness_delay();\n\n\t/* mask not supported on 600e/x, 770e, 770x, A21e, A2xm/p,\n\t   A30, R30, R31, T20-22, X20-21, X22-24.  Detected by checking\n\t   for HKEY interface version 0x100 */\n\tif (acpi_evalf(hkey_handle, &hkeyv, \"MHKV\", \"qd\")) {\n\t\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t\t    \"firmware HKEY interface version: 0x%x\\n\",\n\t\t\t    hkeyv);\n\n\t\tswitch (hkeyv >> 8) {\n\t\tcase 1:\n\t\t\t/*\n\t\t\t * MHKV 0x100 in A31, R40, R40e,\n\t\t\t * T4x, X31, and later\n\t\t\t */\n\n\t\t\t/* Paranoia check AND init hotkey_all_mask */\n\t\t\tif (!acpi_evalf(hkey_handle, &hotkey_all_mask,\n\t\t\t\t\t\"MHKA\", \"qd\")) {\n\t\t\t\tpr_err(\"missing MHKA handler, please report this to %s\\n\",\n\t\t\t\t       TPACPI_MAIL);\n\t\t\t\t/* Fallback: pre-init for FN+F3,F4,F12 */\n\t\t\t\thotkey_all_mask = 0x080cU;\n\t\t\t} else {\n\t\t\t\ttp_features.hotkey_mask = 1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 2:\n\t\t\t/*\n\t\t\t * MHKV 0x200 in X1, T460s, X260, T560, X1 Tablet (2016)\n\t\t\t */\n\n\t\t\t/* Paranoia check AND init hotkey_all_mask */\n\t\t\tif (!acpi_evalf(hkey_handle, &hotkey_all_mask,\n\t\t\t\t\t\"MHKA\", \"dd\", 1)) {\n\t\t\t\tpr_err(\"missing MHKA handler, please report this to %s\\n\",\n\t\t\t\t       TPACPI_MAIL);\n\t\t\t\t/* Fallback: pre-init for FN+F3,F4,F12 */\n\t\t\t\thotkey_all_mask = 0x080cU;\n\t\t\t} else {\n\t\t\t\ttp_features.hotkey_mask = 1;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Check if we have an adaptive keyboard, like on the\n\t\t\t * Lenovo Carbon X1 2014 (2nd Gen).\n\t\t\t */\n\t\t\tif (acpi_evalf(hkey_handle, &hotkey_adaptive_all_mask,\n\t\t\t\t       \"MHKA\", \"dd\", 2)) {\n\t\t\t\tif (hotkey_adaptive_all_mask != 0)\n\t\t\t\t\ttp_features.has_adaptive_kbd = true;\n\t\t\t} else {\n\t\t\t\ttp_features.has_adaptive_kbd = false;\n\t\t\t\thotkey_adaptive_all_mask = 0x0U;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tpr_err(\"unknown version of the HKEY interface: 0x%x\\n\",\n\t\t\t       hkeyv);\n\t\t\tpr_err(\"please report this to %s\\n\", TPACPI_MAIL);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t\"hotkey masks are %s\\n\",\n\t\tstr_supported(tp_features.hotkey_mask));\n\n\t/* Init hotkey_all_mask if not initialized yet */\n\tif (!tp_features.hotkey_mask && !hotkey_all_mask &&\n\t    (quirks & TPACPI_HK_Q_INIMASK))\n\t\thotkey_all_mask = 0x080cU;  /* FN+F12, FN+F4, FN+F3 */\n\n\t/* Init hotkey_acpi_mask and hotkey_orig_mask */\n\tif (tp_features.hotkey_mask) {\n\t\t/* hotkey_source_mask *must* be zero for\n\t\t * the first hotkey_mask_get to return hotkey_orig_mask */\n\t\tres = hotkey_mask_get();\n\t\tif (res)\n\t\t\treturn res;\n\n\t\thotkey_orig_mask = hotkey_acpi_mask;\n\t} else {\n\t\thotkey_orig_mask = hotkey_all_mask;\n\t\thotkey_acpi_mask = hotkey_all_mask;\n\t}\n\n#ifdef CONFIG_THINKPAD_ACPI_DEBUGFACILITIES\n\tif (dbg_wlswemul) {\n\t\ttp_features.hotkey_wlsw = 1;\n\t\tradiosw_state = !!tpacpi_wlsw_emulstate;\n\t\tpr_info(\"radio switch emulation enabled\\n\");\n\t} else\n#endif\n\t/* Not all thinkpads have a hardware radio switch */\n\tif (acpi_evalf(hkey_handle, &status, \"WLSW\", \"qd\")) {\n\t\ttp_features.hotkey_wlsw = 1;\n\t\tradiosw_state = !!status;\n\t\tpr_info(\"radio switch found; radios are %s\\n\",\n\t\t\tenabled(status, 0));\n\t}\n\n\ttabletsw_state = hotkey_init_tablet_mode();\n\n\t/* Set up key map */\n\tkeymap_id = tpacpi_check_quirks(tpacpi_keymap_qtable,\n\t\t\t\t\tARRAY_SIZE(tpacpi_keymap_qtable));\n\tBUG_ON(keymap_id >= ARRAY_SIZE(tpacpi_keymaps));\n\tdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t   \"using keymap number %lu\\n\", keymap_id);\n\n\thotkey_keycode_map = kmemdup(&tpacpi_keymaps[keymap_id],\n\t\t\tTPACPI_HOTKEY_MAP_SIZE,\tGFP_KERNEL);\n\tif (!hotkey_keycode_map) {\n\t\tpr_err(\"failed to allocate memory for key map\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tinput_set_capability(tpacpi_inputdev, EV_MSC, MSC_SCAN);\n\ttpacpi_inputdev->keycodesize = TPACPI_HOTKEY_MAP_TYPESIZE;\n\ttpacpi_inputdev->keycodemax = TPACPI_HOTKEY_MAP_LEN;\n\ttpacpi_inputdev->keycode = hotkey_keycode_map;\n\tfor (i = 0; i < TPACPI_HOTKEY_MAP_LEN; i++) {\n\t\tif (hotkey_keycode_map[i] != KEY_RESERVED) {\n\t\t\tinput_set_capability(tpacpi_inputdev, EV_KEY,\n\t\t\t\t\t\thotkey_keycode_map[i]);\n\t\t} else {\n\t\t\tif (i < sizeof(hotkey_reserved_mask)*8)\n\t\t\t\thotkey_reserved_mask |= 1 << i;\n\t\t}\n\t}\n\n\tif (tp_features.hotkey_wlsw) {\n\t\tinput_set_capability(tpacpi_inputdev, EV_SW, SW_RFKILL_ALL);\n\t\tinput_report_switch(tpacpi_inputdev,\n\t\t\t\t    SW_RFKILL_ALL, radiosw_state);\n\t}\n\tif (tp_features.hotkey_tablet) {\n\t\tinput_set_capability(tpacpi_inputdev, EV_SW, SW_TABLET_MODE);\n\t\tinput_report_switch(tpacpi_inputdev,\n\t\t\t\t    SW_TABLET_MODE, tabletsw_state);\n\t}\n\n\t/* Do not issue duplicate brightness change events to\n\t * userspace. tpacpi_detect_brightness_capabilities() must have\n\t * been called before this point  */\n\tif (acpi_video_get_backlight_type() != acpi_backlight_vendor) {\n\t\tpr_info(\"This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver\\n\");\n\t\tpr_notice(\"Disabling thinkpad-acpi brightness events by default...\\n\");\n\n\t\t/* Disable brightness up/down on Lenovo thinkpads when\n\t\t * ACPI is handling them, otherwise it is plain impossible\n\t\t * for userspace to do something even remotely sane */\n\t\thotkey_reserved_mask |=\n\t\t\t(1 << TP_ACPI_HOTKEYSCAN_FNHOME)\n\t\t\t| (1 << TP_ACPI_HOTKEYSCAN_FNEND);\n\t\thotkey_unmap(TP_ACPI_HOTKEYSCAN_FNHOME);\n\t\thotkey_unmap(TP_ACPI_HOTKEYSCAN_FNEND);\n\t}\n\n#ifdef CONFIG_THINKPAD_ACPI_HOTKEY_POLL\n\thotkey_source_mask = TPACPI_HKEY_NVRAM_GOOD_MASK\n\t\t\t\t& ~hotkey_all_mask\n\t\t\t\t& ~hotkey_reserved_mask;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t    \"hotkey source mask 0x%08x, polling freq %u\\n\",\n\t\t    hotkey_source_mask, hotkey_poll_freq);\n#endif\n\n\tdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t\t\"enabling firmware HKEY event interface...\\n\");\n\tres = hotkey_status_set(true);\n\tif (res) {\n\t\thotkey_exit();\n\t\treturn res;\n\t}\n\tres = hotkey_mask_set(((hotkey_all_mask & ~hotkey_reserved_mask)\n\t\t\t       | hotkey_driver_mask)\n\t\t\t      & ~hotkey_source_mask);\n\tif (res < 0 && res != -ENXIO) {\n\t\thotkey_exit();\n\t\treturn res;\n\t}\n\thotkey_user_mask = (hotkey_acpi_mask | hotkey_source_mask)\n\t\t\t\t& ~hotkey_reserved_mask;\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_HKEY,\n\t\t\"initial masks: user=0x%08x, fw=0x%08x, poll=0x%08x\\n\",\n\t\thotkey_user_mask, hotkey_acpi_mask, hotkey_source_mask);\n\n\ttpacpi_inputdev->open = &hotkey_inputdev_open;\n\ttpacpi_inputdev->close = &hotkey_inputdev_close;\n\n\thotkey_poll_setup_safe(true);\n\n\treturn 0;\n}",
        "static void __simple_estab(bool exprm)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n": "static void __simple_estab(bool exprm)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n\n\thdr_stg_map_fd = bpf_map__fd(skel->maps.hdr_stg_map);\n\tlport_linum_map_fd = bpf_map__fd(skel->maps.lport_linum_map);\n\n\texp_passive_estab_in.flags = OPTION_F_RAND | OPTION_F_MAX_DELACK_MS;\n\texp_passive_estab_in.rand = 0xfa;\n\texp_passive_estab_in.max_delack_ms = 11;\n\n\texp_active_estab_in.flags = OPTION_F_RAND | OPTION_F_MAX_DELACK_MS;\n\texp_active_estab_in.rand = 0xce;\n\texp_active_estab_in.max_delack_ms = 22;\n\n\tprepare_out();\n\n\tif (!exprm) {\n\t\tskel->data->test_kind = 0xB9;\n\t\tskel->data->test_magic = 0;\n\t}\n\n\tif (write_sysctl(\"/proc/sys/net/ipv4/tcp_syncookies\", \"1\"))\n\t\treturn;\n\n\tlink = bpf_program__attach_cgroup(skel->progs.estab, cg_fd);\n\tif (!ASSERT_OK_PTR(link, \"attach_cgroup(estab)\"))\n\t\treturn;\n\n\tif (sk_fds_connect(&sk_fds, false)) {\n\t\tbpf_link__destroy(link);\n\t\treturn;\n\t}\n\n\tcheck_hdr_and_close_fds(&sk_fds);\n\tbpf_link__destroy(link);\n}",
        "static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)\n{\n\t/* Reset */\n\n\t/* after checking the datasheets for SST, MACRONIX and ATMEL": "static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)\n{\n\t/* Reset */\n\n\t/* after checking the datasheets for SST, MACRONIX and ATMEL\n\t * (oh and incidentaly the jedec spec - 3.5.3.3) the reset\n\t * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at\n\t * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips\n\t * as they will ignore the writes and don't care what address\n\t * the F0 is written to */\n\tif (cfi->addr_unlock1) {\n\t\tpr_debug( \"reset unlock called %x %x \\n\",\n\t\t       cfi->addr_unlock1,cfi->addr_unlock2);\n\t\tcfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);\n\t\tcfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);\n\t}\n\n\tcfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);\n\t/* Some misdesigned Intel chips do not respond for 0xF0 for a reset,\n\t * so ensure we're in read mode.  Send both the Intel and the AMD command\n\t * for this.  Intel uses 0xff for this, AMD uses 0xff for NOP, so\n\t * this should be safe.\n\t */\n\tcfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);\n\t/* FIXME - should have reset delay before continuing */\n}",
        "static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr)\n{\n\tstruct npc_lt_def_cfg defs, *ltdefs;\n\n\tltdefs = &defs;": "static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr)\n{\n\tstruct npc_lt_def_cfg defs, *ltdefs;\n\n\tltdefs = &defs;\n\tmemcpy(ltdefs, rvu->kpu.lt_def, sizeof(struct npc_lt_def_cfg));\n\n\t/* Extract PCP and DEI fields from outer VLAN from byte offset\n\t * 2 from the start of LB_PTR (ie TAG).\n\t * VLAN0 is Outer VLAN and VLAN1 is Inner VLAN. Inner VLAN\n\t * fields are considered when 'Tunnel enable' is set in profile.\n\t */\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN0_PCP_DEI,\n\t\t    (2UL << 12) | (ltdefs->ovlan.lid << 8) |\n\t\t    (ltdefs->ovlan.ltype_match << 4) |\n\t\t    ltdefs->ovlan.ltype_mask);\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN1_PCP_DEI,\n\t\t    (2UL << 12) | (ltdefs->ivlan.lid << 8) |\n\t\t    (ltdefs->ivlan.ltype_match << 4) |\n\t\t    ltdefs->ivlan.ltype_mask);\n\n\t/* DSCP field in outer and tunneled IPv4 packets */\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4_DSCP,\n\t\t    (1UL << 12) | (ltdefs->rx_oip4.lid << 8) |\n\t\t    (ltdefs->rx_oip4.ltype_match << 4) |\n\t\t    ltdefs->rx_oip4.ltype_mask);\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4_DSCP,\n\t\t    (1UL << 12) | (ltdefs->rx_iip4.lid << 8) |\n\t\t    (ltdefs->rx_iip4.ltype_match << 4) |\n\t\t    ltdefs->rx_iip4.ltype_mask);\n\n\t/* DSCP field (traffic class) in outer and tunneled IPv6 packets */\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6_DSCP,\n\t\t    (1UL << 11) | (ltdefs->rx_oip6.lid << 8) |\n\t\t    (ltdefs->rx_oip6.ltype_match << 4) |\n\t\t    ltdefs->rx_oip6.ltype_mask);\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6_DSCP,\n\t\t    (1UL << 11) | (ltdefs->rx_iip6.lid << 8) |\n\t\t    (ltdefs->rx_iip6.ltype_match << 4) |\n\t\t    ltdefs->rx_iip6.ltype_mask);\n}",
        "static int __smc_buf_create(struct smc_sock *smc, bool is_smcd, bool is_rmb)\n{\n\tstruct smc_buf_desc *buf_desc = ERR_PTR(-ENOMEM);\n\tstruct smc_connection *conn = &smc->conn;\n\tstruct smc_link_group *lgr = conn->lgr;": "static int __smc_buf_create(struct smc_sock *smc, bool is_smcd, bool is_rmb)\n{\n\tstruct smc_buf_desc *buf_desc = ERR_PTR(-ENOMEM);\n\tstruct smc_connection *conn = &smc->conn;\n\tstruct smc_link_group *lgr = conn->lgr;\n\tstruct list_head *buf_list;\n\tint bufsize, bufsize_short;\n\tbool is_dgraded = false;\n\tstruct mutex *lock;\t/* lock buffer list */\n\tint sk_buf_size;\n\n\tif (is_rmb)\n\t\t/* use socket recv buffer size (w/o overhead) as start value */\n\t\tsk_buf_size = smc->sk.sk_rcvbuf / 2;\n\telse\n\t\t/* use socket send buffer size (w/o overhead) as start value */\n\t\tsk_buf_size = smc->sk.sk_sndbuf / 2;\n\n\tfor (bufsize_short = smc_compress_bufsize(sk_buf_size, is_smcd, is_rmb);\n\t     bufsize_short >= 0; bufsize_short--) {\n\t\tif (is_rmb) {\n\t\t\tlock = &lgr->rmbs_lock;\n\t\t\tbuf_list = &lgr->rmbs[bufsize_short];\n\t\t} else {\n\t\t\tlock = &lgr->sndbufs_lock;\n\t\t\tbuf_list = &lgr->sndbufs[bufsize_short];\n\t\t}\n\t\tbufsize = smc_uncompress_bufsize(bufsize_short);\n\n\t\t/* check for reusable slot in the link group */\n\t\tbuf_desc = smc_buf_get_slot(bufsize_short, lock, buf_list);\n\t\tif (buf_desc) {\n\t\t\tSMC_STAT_RMB_SIZE(smc, is_smcd, is_rmb, bufsize);\n\t\t\tSMC_STAT_BUF_REUSE(smc, is_smcd, is_rmb);\n\t\t\tbreak; /* found reusable slot */\n\t\t}\n\n\t\tif (is_smcd)\n\t\t\tbuf_desc = smcd_new_buf_create(lgr, is_rmb, bufsize);\n\t\telse\n\t\t\tbuf_desc = smcr_new_buf_create(lgr, is_rmb, bufsize);\n\n\t\tif (PTR_ERR(buf_desc) == -ENOMEM)\n\t\t\tbreak;\n\t\tif (IS_ERR(buf_desc)) {\n\t\t\tif (!is_dgraded) {\n\t\t\t\tis_dgraded = true;\n\t\t\t\tSMC_STAT_RMB_DOWNGRADED(smc, is_smcd, is_rmb);\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\n\t\tSMC_STAT_RMB_ALLOC(smc, is_smcd, is_rmb);\n\t\tSMC_STAT_RMB_SIZE(smc, is_smcd, is_rmb, bufsize);\n\t\tbuf_desc->used = 1;\n\t\tmutex_lock(lock);\n\t\tlist_add(&buf_desc->list, buf_list);\n\t\tmutex_unlock(lock);\n\t\tbreak; /* found */\n\t}\n\n\tif (IS_ERR(buf_desc))\n\t\treturn PTR_ERR(buf_desc);\n\n\tif (!is_smcd) {\n\t\tif (smcr_buf_map_usable_links(lgr, buf_desc, is_rmb)) {\n\t\t\tsmcr_buf_unuse(buf_desc, lgr);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\n\tif (is_rmb) {\n\t\tconn->rmb_desc = buf_desc;\n\t\tconn->rmbe_size_short = bufsize_short;\n\t\tsmc->sk.sk_rcvbuf = bufsize * 2;\n\t\tatomic_set(&conn->bytes_to_rcv, 0);\n\t\tconn->rmbe_update_limit =\n\t\t\tsmc_rmb_wnd_update_limit(buf_desc->len);\n\t\tif (is_smcd)\n\t\t\tsmc_ism_set_conn(conn); /* map RMB/smcd_dev to conn */\n\t} else {\n\t\tconn->sndbuf_desc = buf_desc;\n\t\tsmc->sk.sk_sndbuf = bufsize * 2;\n\t\tatomic_set(&conn->sndbuf_space, bufsize);\n\t}\n\treturn 0;\n}",
        "static void rtl_hw_start_8168ep(struct rtl8169_private *tp)\n{\n\trtl8168ep_stop_cmac(tp);\n\n\trtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);": "static void rtl_hw_start_8168ep(struct rtl8169_private *tp)\n{\n\trtl8168ep_stop_cmac(tp);\n\n\trtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);\n\trtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);\n\n\trtl_set_def_aspm_entry_latency(tp);\n\n\trtl_reset_packet_filter(tp);\n\n\trtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);\n\n\tRTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);\n\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);\n\trtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);\n\n\trtl8168_config_eee_mac(tp);\n\n\trtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);\n\n\tRTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);\n\n\trtl_pcie_state_l2l3_disable(tp);\n}",
        "static int video_start(struct ia_css_pipe *pipe)\n{\n\tint err = 0;\n\tstruct ia_css_pipe *copy_pipe, *capture_pipe;\n\tenum sh_css_pipe_config_override copy_ovrd;": "static int video_start(struct ia_css_pipe *pipe)\n{\n\tint err = 0;\n\tstruct ia_css_pipe *copy_pipe, *capture_pipe;\n\tenum sh_css_pipe_config_override copy_ovrd;\n\tenum ia_css_input_mode video_pipe_input_mode;\n\tunsigned int thread_id;\n\n\tIA_CSS_ENTER_PRIVATE(\"pipe = %p\", pipe);\n\tif ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(-EINVAL);\n\t\treturn -EINVAL;\n\t}\n\n\tvideo_pipe_input_mode = pipe->stream->config.mode;\n\n\tcopy_pipe    = pipe->pipe_settings.video.copy_pipe;\n\tcapture_pipe = pipe->pipe_settings.video.capture_pipe;\n\n\tsh_css_metrics_start_frame();\n\n\t/* multi stream video needs mipi buffers */\n\n\terr = send_mipi_frames(pipe);\n\tif (err)\n\t\treturn err;\n\n\tsend_raw_frames(pipe);\n\n\tia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);\n\tcopy_ovrd = 1 << thread_id;\n\n\tif (pipe->stream->cont_capt) {\n\t\tia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe),\n\t\t\t\t\t\t    &thread_id);\n\t\tcopy_ovrd |= 1 << thread_id;\n\t}\n\n\t/* Construct and load the copy pipe */\n\tif (pipe->stream->config.continuous) {\n\t\tsh_css_sp_init_pipeline(&copy_pipe->pipeline,\n\t\t\t\t\tIA_CSS_PIPE_ID_COPY,\n\t\t\t\t\t(uint8_t)ia_css_pipe_get_pipe_num(copy_pipe),\n\t\t\t\t\tfalse,\n\t\t\t\t\tpipe->stream->config.pixels_per_clock == 2, false,\n\t\t\t\t\tfalse, pipe->required_bds_factor,\n\t\t\t\t\tcopy_ovrd,\n\t\t\t\t\tpipe->stream->config.mode,\n\t\t\t\t\t&pipe->stream->config.metadata_config,\n\t\t\t\t\t&pipe->stream->info.metadata_info,\n\t\t\t\t\tpipe->stream->config.source.port.port);\n\n\t\t/*\n\t\t * make the video pipe start with mem mode input, copy handles\n\t\t * the actual mode\n\t\t */\n\t\tvideo_pipe_input_mode = IA_CSS_INPUT_MODE_MEMORY;\n\t}\n\n\t/* Construct and load the capture pipe */\n\tif (pipe->stream->cont_capt) {\n\t\tsh_css_sp_init_pipeline(&capture_pipe->pipeline,\n\t\t\t\t\tIA_CSS_PIPE_ID_CAPTURE,\n\t\t\t\t\t(uint8_t)ia_css_pipe_get_pipe_num(capture_pipe),\n\t\t\t\t\tcapture_pipe->config.default_capture_config.enable_xnr != 0,\n\t\t\t\t\tcapture_pipe->stream->config.pixels_per_clock == 2,\n\t\t\t\t\ttrue, /* continuous */\n\t\t\t\t\tfalse, /* offline */\n\t\t\t\t\tcapture_pipe->required_bds_factor,\n\t\t\t\t\t0,\n\t\t\t\t\tIA_CSS_INPUT_MODE_MEMORY,\n\t\t\t\t\t&pipe->stream->config.metadata_config,\n\t\t\t\t\t&pipe->stream->info.metadata_info,\n\t\t\t\t\t(enum mipi_port_id)0);\n\t}\n\n\tstart_pipe(pipe, copy_ovrd, video_pipe_input_mode);\n\n\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\treturn err;\n}",
        "static int cs42l42_manual_hs_det(struct sub_codec *cs42l42)\n{\n\tunsigned int hs_det_status;\n\tunsigned int hs_det_comp1;\n\tunsigned int hs_det_comp2;": "static int cs42l42_manual_hs_det(struct sub_codec *cs42l42)\n{\n\tunsigned int hs_det_status;\n\tunsigned int hs_det_comp1;\n\tunsigned int hs_det_comp2;\n\tunsigned int hs_det_sw;\n\tunsigned int hs_type;\n\n\t/* Set hs detect to manual, active mode */\n\tcs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,\n\t\t\t (1 << CS42L42_HSDET_CTRL_SHIFT) |\n\t\t\t (0 << CS42L42_HSDET_SET_SHIFT) |\n\t\t\t (0 << CS42L42_HSBIAS_REF_SHIFT) |\n\t\t\t (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));\n\n\t/* Configure HS DET comparator reference levels. */\n\tcs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,\n\t\t\t (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |\n\t\t\t (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));\n\n\t/* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */\n\tcs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);\n\n\tmsleep(100);\n\n\ths_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);\n\n\ths_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>\n\t\t\tCS42L42_HSDET_COMP1_OUT_SHIFT;\n\ths_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>\n\t\t\tCS42L42_HSDET_COMP2_OUT_SHIFT;\n\n\t/* Close the SW_HSB_HS3 switch for a Type 2 headset. */\n\tcs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);\n\n\tmsleep(100);\n\n\ths_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);\n\n\ths_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>\n\t\t\tCS42L42_HSDET_COMP1_OUT_SHIFT) << 1;\n\ths_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>\n\t\t\tCS42L42_HSDET_COMP2_OUT_SHIFT) << 1;\n\n\t/* Use Comparator 1 with 1.25V Threshold. */\n\tswitch (hs_det_comp1) {\n\tcase CS42L42_HSDET_COMP_TYPE1:\n\t\ths_type = CS42L42_PLUG_CTIA;\n\t\ths_det_sw = CS42L42_HSDET_SW_TYPE1;\n\t\tbreak;\n\tcase CS42L42_HSDET_COMP_TYPE2:\n\t\ths_type = CS42L42_PLUG_OMTP;\n\t\ths_det_sw = CS42L42_HSDET_SW_TYPE2;\n\t\tbreak;\n\tdefault:\n\t\t/* Fallback to Comparator 2 with 1.75V Threshold. */\n\t\tswitch (hs_det_comp2) {\n\t\tcase CS42L42_HSDET_COMP_TYPE1:\n\t\t\ths_type = CS42L42_PLUG_CTIA;\n\t\t\ths_det_sw = CS42L42_HSDET_SW_TYPE1;\n\t\t\tbreak;\n\t\tcase CS42L42_HSDET_COMP_TYPE2:\n\t\t\ths_type = CS42L42_PLUG_OMTP;\n\t\t\ths_det_sw = CS42L42_HSDET_SW_TYPE2;\n\t\t\tbreak;\n\t\tcase CS42L42_HSDET_COMP_TYPE3:\n\t\t\ths_type = CS42L42_PLUG_HEADPHONE;\n\t\t\ths_det_sw = CS42L42_HSDET_SW_TYPE3;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\ths_type = CS42L42_PLUG_INVALID;\n\t\t\ths_det_sw = CS42L42_HSDET_SW_TYPE4;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Set Switches */\n\tcs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw);\n\n\t/* Set HSDET mode to Manual\u2014Disabled */\n\tcs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,\n\t\t\t (0 << CS42L42_HSDET_CTRL_SHIFT) |\n\t\t\t (0 << CS42L42_HSDET_SET_SHIFT) |\n\t\t\t (0 << CS42L42_HSBIAS_REF_SHIFT) |\n\t\t\t (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));\n\n\t/* Configure HS DET comparator reference levels. */\n\tcs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,\n\t\t\t (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |\n\t\t\t (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));\n\n\treturn hs_type;\n}",
        "static void service_done_flag(struct dim2_hdm *dev, int ch_idx)\n{\n\tstruct hdm_channel *hdm_ch = dev->hch + ch_idx;\n\tstruct dim_ch_state_t st;\n\tstruct list_head *head;": "static void service_done_flag(struct dim2_hdm *dev, int ch_idx)\n{\n\tstruct hdm_channel *hdm_ch = dev->hch + ch_idx;\n\tstruct dim_ch_state_t st;\n\tstruct list_head *head;\n\tstruct mbo *mbo;\n\tint done_buffers;\n\tunsigned long flags;\n\tu8 *data;\n\n\tBUG_ON(!hdm_ch);\n\tBUG_ON(!hdm_ch->is_initialized);\n\n\tspin_lock_irqsave(&dim_lock, flags);\n\n\tdone_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers;\n\tif (!done_buffers) {\n\t\tspin_unlock_irqrestore(&dim_lock, flags);\n\t\treturn;\n\t}\n\n\tif (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) {\n\t\tspin_unlock_irqrestore(&dim_lock, flags);\n\t\treturn;\n\t}\n\tspin_unlock_irqrestore(&dim_lock, flags);\n\n\thead = &hdm_ch->started_list;\n\n\twhile (done_buffers) {\n\t\tspin_lock_irqsave(&dim_lock, flags);\n\t\tif (list_empty(head)) {\n\t\t\tspin_unlock_irqrestore(&dim_lock, flags);\n\t\t\tpr_crit(\"hard error: started_mbo list is empty whereas DIM2 has sent buffers\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\tmbo = list_first_entry(head, struct mbo, list);\n\t\tlist_del(head->next);\n\t\tspin_unlock_irqrestore(&dim_lock, flags);\n\n\t\tdata = mbo->virt_address;\n\n\t\tif (hdm_ch->data_type == MOST_CH_ASYNC &&\n\t\t    hdm_ch->direction == MOST_CH_RX &&\n\t\t    PACKET_IS_NET_INFO(data)) {\n\t\t\tretrieve_netinfo(dev, mbo);\n\n\t\t\tspin_lock_irqsave(&dim_lock, flags);\n\t\t\tlist_add_tail(&mbo->list, &hdm_ch->pending_list);\n\t\t\tspin_unlock_irqrestore(&dim_lock, flags);\n\t\t} else {\n\t\t\tif (hdm_ch->data_type == MOST_CH_CONTROL ||\n\t\t\t    hdm_ch->data_type == MOST_CH_ASYNC) {\n\t\t\t\tu32 const data_size =\n\t\t\t\t\t(u32)data[0] * 256 + data[1] + 2;\n\n\t\t\t\tmbo->processed_length =\n\t\t\t\t\tmin_t(u32, data_size,\n\t\t\t\t\t      mbo->buffer_length);\n\t\t\t} else {\n\t\t\t\tmbo->processed_length = mbo->buffer_length;\n\t\t\t}\n\t\t\tmbo->status = MBO_SUCCESS;\n\t\t\tmbo->complete(mbo);\n\t\t}\n\n\t\tdone_buffers--;\n\t}\n}",
        "static bool HTIOTActIsDisableMCS15(struct ieee80211_device *ieee)\n{\n\tbool retValue = false;\n\n#ifdef TODO": "static bool HTIOTActIsDisableMCS15(struct ieee80211_device *ieee)\n{\n\tbool retValue = false;\n\n#ifdef TODO\n\t// Apply for 819u only\n#if (HAL_CODE_BASE == RTL8192)\n\n#if (DEV_BUS_TYPE == USB_INTERFACE)\n\t// Alway disable MCS15 by Jerry Chang's request.by Emily, 2008.04.15\n\tretValue = true;\n#elif (DEV_BUS_TYPE == PCI_INTERFACE)\n\t// Enable MCS15 if the peer is Cisco AP. by Emily, 2008.05.12\n//\tif(pBssDesc->bCiscoCapExist)\n//\t\tretValue = false;\n//\telse\n\t\tretValue = false;\n#endif\n#endif\n#endif\n\t// Jerry Chang suggest that 8190 1x2 does not need to disable MCS15\n\n\treturn retValue;\n}",
        "static void rtl_enable_exit_l1(struct rtl8169_private *tp)\n{\n\t/* Bits control which events trigger ASPM L1 exit:\n\t * Bit 12: rxdv\n\t * Bit 11: ltr_msg": "static void rtl_enable_exit_l1(struct rtl8169_private *tp)\n{\n\t/* Bits control which events trigger ASPM L1 exit:\n\t * Bit 12: rxdv\n\t * Bit 11: ltr_msg\n\t * Bit 10: txdma_poll\n\t * Bit  9: xadm\n\t * Bit  8: pktavi\n\t * Bit  7: txpla\n\t */\n\tswitch (tp->mac_version) {\n\tcase RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:\n\t\trtl_eri_set_bits(tp, 0xd4, 0x1f00);\n\t\tbreak;\n\tcase RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:\n\t\trtl_eri_set_bits(tp, 0xd4, 0x0c00);\n\t\tbreak;\n\tcase RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:\n\t\tr8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}",
        "static int tls_clone_plaintext_msg(struct sock *sk, int required)\n{\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tstruct tls_sw_context_tx *ctx = tls_sw_ctx_tx(tls_ctx);": "static int tls_clone_plaintext_msg(struct sock *sk, int required)\n{\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tstruct tls_sw_context_tx *ctx = tls_sw_ctx_tx(tls_ctx);\n\tstruct tls_rec *rec = ctx->open_rec;\n\tstruct sk_msg *msg_pl = &rec->msg_plaintext;\n\tstruct sk_msg *msg_en = &rec->msg_encrypted;\n\tint skip, len;\n\n\t/* We add page references worth len bytes from encrypted sg\n\t * at the end of plaintext sg. It is guaranteed that msg_en\n\t * has enough required room (ensured by caller).\n\t */\n\tlen = required - msg_pl->sg.size;\n\n\t/* Skip initial bytes in msg_en's data to be able to use\n\t * same offset of both plain and encrypted data.\n\t */\n\tskip = prot->prepend_size + msg_pl->sg.size;\n\n\treturn sk_msg_clone(sk, msg_pl, msg_en, skip, len);\n}",
        "static void _prb_commit(struct prb_reserved_entry *e, unsigned long state_val)\n{\n\tstruct prb_desc_ring *desc_ring = &e->rb->desc_ring;\n\tstruct prb_desc *d = to_desc(desc_ring, e->id);\n\tunsigned long prev_state_val = DESC_SV(e->id, desc_reserved);": "static void _prb_commit(struct prb_reserved_entry *e, unsigned long state_val)\n{\n\tstruct prb_desc_ring *desc_ring = &e->rb->desc_ring;\n\tstruct prb_desc *d = to_desc(desc_ring, e->id);\n\tunsigned long prev_state_val = DESC_SV(e->id, desc_reserved);\n\n\t/* Now the writer has finished all writing: LMM(_prb_commit:A) */\n\n\t/*\n\t * Set the descriptor as committed. See \"ABA Issues\" about why\n\t * cmpxchg() instead of set() is used.\n\t *\n\t * 1  Guarantee all record data is stored before the descriptor state\n\t *    is stored as committed. A write memory barrier is sufficient\n\t *    for this. This pairs with desc_read:B and desc_reopen_last:A.\n\t *\n\t * 2. Guarantee the descriptor state is stored as committed before\n\t *    re-checking the head ID in order to possibly finalize this\n\t *    descriptor. This pairs with desc_reserve:D.\n\t *\n\t *    Memory barrier involvement:\n\t *\n\t *    If prb_commit:A reads from desc_reserve:D, then\n\t *    desc_make_final:A reads from _prb_commit:B.\n\t *\n\t *    Relies on:\n\t *\n\t *    MB _prb_commit:B to prb_commit:A\n\t *       matching\n\t *    MB desc_reserve:D to desc_make_final:A\n\t */\n\tif (!atomic_long_try_cmpxchg(&d->state_var, &prev_state_val,\n\t\t\tDESC_SV(e->id, state_val))) { /* LMM(_prb_commit:B) */\n\t\tWARN_ON_ONCE(1);\n\t}\n\n\t/* Restore interrupts, the reserve/commit window is finished. */\n\tlocal_irq_restore(e->irqflags);\n}",
        "static int t7xx_port_proxy_recv_skb(struct cldma_queue *queue, struct sk_buff *skb)\n{\n\tstruct ccci_header *ccci_h = (struct ccci_header *)skb->data;\n\tstruct t7xx_pci_dev *t7xx_dev = queue->md_ctrl->t7xx_dev;\n\tstruct t7xx_fsm_ctl *ctl = t7xx_dev->md->fsm_ctl;": "static int t7xx_port_proxy_recv_skb(struct cldma_queue *queue, struct sk_buff *skb)\n{\n\tstruct ccci_header *ccci_h = (struct ccci_header *)skb->data;\n\tstruct t7xx_pci_dev *t7xx_dev = queue->md_ctrl->t7xx_dev;\n\tstruct t7xx_fsm_ctl *ctl = t7xx_dev->md->fsm_ctl;\n\tstruct device *dev = queue->md_ctrl->dev;\n\tconst struct t7xx_port_conf *port_conf;\n\tstruct t7xx_port *port;\n\tu16 seq_num, channel;\n\tint ret;\n\n\tchannel = FIELD_GET(CCCI_H_CHN_FLD, le32_to_cpu(ccci_h->status));\n\tif (t7xx_fsm_get_md_state(ctl) == MD_STATE_INVALID) {\n\t\tdev_err_ratelimited(dev, \"Packet drop on channel 0x%x, modem not ready\\n\", channel);\n\t\tgoto drop_skb;\n\t}\n\n\tport = t7xx_port_proxy_find_port(t7xx_dev, queue, channel);\n\tif (!port) {\n\t\tdev_err_ratelimited(dev, \"Packet drop on channel 0x%x, port not found\\n\", channel);\n\t\tgoto drop_skb;\n\t}\n\n\tseq_num = t7xx_port_next_rx_seq_num(port, ccci_h);\n\tport_conf = port->port_conf;\n\tskb_pull(skb, sizeof(*ccci_h));\n\n\tret = port_conf->ops->recv_skb(port, skb);\n\t/* Error indicates to try again later */\n\tif (ret) {\n\t\tskb_push(skb, sizeof(*ccci_h));\n\t\treturn ret;\n\t}\n\n\tport->seq_nums[MTK_RX] = seq_num;\n\treturn 0;\n\ndrop_skb:\n\tdev_kfree_skb_any(skb);\n\treturn 0;\n}",
        "static int graph_callback(struct gpr_resp_pkt *data, void *priv, int op)\n{\n\tstruct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 *rd_done;\n\tstruct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 *done;\n\tstruct apm_cmd_rsp_shared_mem_map_regions *rsp;": "static int graph_callback(struct gpr_resp_pkt *data, void *priv, int op)\n{\n\tstruct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 *rd_done;\n\tstruct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 *done;\n\tstruct apm_cmd_rsp_shared_mem_map_regions *rsp;\n\tstruct gpr_ibasic_rsp_result_t *result;\n\tstruct q6apm_graph *graph = priv;\n\tstruct gpr_hdr *hdr = &data->hdr;\n\tstruct device *dev = graph->dev;\n\tuint32_t client_event;\n\tphys_addr_t phys;\n\tint token;\n\n\tresult = data->payload;\n\n\tswitch (hdr->opcode) {\n\tcase DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2:\n\t\tclient_event = APM_CLIENT_EVENT_DATA_WRITE_DONE;\n\t\tmutex_lock(&graph->lock);\n\t\ttoken = hdr->token & APM_WRITE_TOKEN_MASK;\n\n\t\tdone = data->payload;\n\t\tphys = graph->rx_data.buf[token].phys;\n\t\tmutex_unlock(&graph->lock);\n\n\t\tif (lower_32_bits(phys) == done->buf_addr_lsw &&\n\t\t    upper_32_bits(phys) == done->buf_addr_msw) {\n\t\t\tgraph->result.opcode = hdr->opcode;\n\t\t\tgraph->result.status = done->status;\n\t\t\tif (graph->cb)\n\t\t\t\tgraph->cb(client_event, hdr->token, data->payload, graph->priv);\n\t\t} else {\n\t\t\tdev_err(dev, \"WR BUFF Unexpected addr %08x-%08x\\n\", done->buf_addr_lsw,\n\t\t\t\tdone->buf_addr_msw);\n\t\t}\n\n\t\tbreak;\n\tcase APM_CMD_RSP_SHARED_MEM_MAP_REGIONS:\n\t\tgraph->result.opcode = hdr->opcode;\n\t\tgraph->result.status = 0;\n\t\trsp = data->payload;\n\n\t\tif (hdr->token == SNDRV_PCM_STREAM_PLAYBACK)\n\t\t\tgraph->rx_data.mem_map_handle = rsp->mem_map_handle;\n\t\telse\n\t\t\tgraph->tx_data.mem_map_handle = rsp->mem_map_handle;\n\n\t\twake_up(&graph->cmd_wait);\n\t\tbreak;\n\tcase DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2:\n\t\tclient_event = APM_CLIENT_EVENT_DATA_READ_DONE;\n\t\tmutex_lock(&graph->lock);\n\t\trd_done = data->payload;\n\t\tphys = graph->tx_data.buf[hdr->token].phys;\n\t\tmutex_unlock(&graph->lock);\n\n\t\tif (upper_32_bits(phys) == rd_done->buf_addr_msw &&\n\t\t    lower_32_bits(phys) == rd_done->buf_addr_lsw) {\n\t\t\tgraph->result.opcode = hdr->opcode;\n\t\t\tgraph->result.status = rd_done->status;\n\t\t\tif (graph->cb)\n\t\t\t\tgraph->cb(client_event, hdr->token, data->payload, graph->priv);\n\t\t} else {\n\t\t\tdev_err(dev, \"RD BUFF Unexpected addr %08x-%08x\\n\", rd_done->buf_addr_lsw,\n\t\t\t\trd_done->buf_addr_msw);\n\t\t}\n\t\tbreak;\n\tcase DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED:\n\t\tbreak;\n\tcase GPR_BASIC_RSP_RESULT:\n\t\tswitch (result->opcode) {\n\t\tcase APM_CMD_SHARED_MEM_UNMAP_REGIONS:\n\t\t\tgraph->result.opcode = result->opcode;\n\t\t\tgraph->result.status = 0;\n\t\t\tif (hdr->token == SNDRV_PCM_STREAM_PLAYBACK)\n\t\t\t\tgraph->rx_data.mem_map_handle = 0;\n\t\t\telse\n\t\t\t\tgraph->tx_data.mem_map_handle = 0;\n\n\t\t\twake_up(&graph->cmd_wait);\n\t\t\tbreak;\n\t\tcase APM_CMD_SHARED_MEM_MAP_REGIONS:\n\t\tcase DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT:\n\t\tcase APM_CMD_SET_CFG:\n\t\t\tgraph->result.opcode = result->opcode;\n\t\t\tgraph->result.status = result->status;\n\t\t\tif (result->status)\n\t\t\t\tdev_err(dev, \"Error (%d) Processing 0x%08x cmd\\n\",\n\t\t\t\t\tresult->status, result->opcode);\n\t\t\twake_up(&graph->cmd_wait);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn 0;\n}",
        "static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)\n{\n\t/* This is technically race-y.\n\t *\n\t * In an ideal world, we could atomically assert both resets at the": "static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)\n{\n\t/* This is technically race-y.\n\t *\n\t * In an ideal world, we could atomically assert both resets at the\n\t * same time, through an atomic bulk reset API. This API however does\n\t * not exist, so what the downstream vendor code used to do was\n\t * implement half a reset controller here and require the CRU to be\n\t * passed to the driver as a device tree node. Violating abstractions\n\t * like that is bad, especially when it influences something like the\n\t * bindings which are supposed to describe the hardware, not whatever\n\t * workarounds the driver needs, so it was dropped.\n\t *\n\t * In practice, asserting the resets one by one appears to work just\n\t * fine for playback. During duplex (playback + capture) operation,\n\t * this might become an issue, but that should be solved by the\n\t * implementation of the aforementioned API, not by shoving a reset\n\t * controller into an audio driver.\n\t */\n\n\treset_control_assert(i2s_tdm->tx_reset);\n\treset_control_assert(i2s_tdm->rx_reset);\n\tudelay(10);\n\treset_control_deassert(i2s_tdm->tx_reset);\n\treset_control_deassert(i2s_tdm->rx_reset);\n\tudelay(10);\n}",
        "static int nx_wait_for_csb(struct nx_gzip_crb_cpb_t *cmdp)\n{\n\tlong poll = 0;\n\tuint64_t t;\n": "static int nx_wait_for_csb(struct nx_gzip_crb_cpb_t *cmdp)\n{\n\tlong poll = 0;\n\tuint64_t t;\n\n\t/* Save power and let other threads use the h/w. top may show\n\t * 100% but only because OS doesn't know we slowed the this\n\t * h/w thread while polling. We're letting other threads have\n\t * higher throughput on the core.\n\t */\n\tcpu_pri_low();\n\n#define CSB_MAX_POLL 200000000UL\n#define USLEEP_TH     300000UL\n\n\tt = __ppc_get_timebase();\n\n\twhile (getnn(cmdp->crb.csb, csb_v) == 0) {\n\t\t++poll;\n\t\thwsync();\n\n\t\tcpu_pri_low();\n\n\t\t/* usleep(0) takes around 29000 ticks ~60 us.\n\t\t * 300000 is spinning for about 600 us then\n\t\t * start sleeping.\n\t\t */\n\t\tif ((__ppc_get_timebase() - t) > USLEEP_TH) {\n\t\t\tcpu_pri_default();\n\t\t\tusleep(1);\n\t\t}\n\n\t\tif (poll > CSB_MAX_POLL)\n\t\t\tbreak;\n\n\t\t/* Fault address from signal handler */\n\t\tif (nx_fault_storage_address) {\n\t\t\tcpu_pri_default();\n\t\t\treturn -EAGAIN;\n\t\t}\n\n\t}\n\n\tcpu_pri_default();\n\n\t/* hw has updated csb and output buffer */\n\thwsync();\n\n\t/* Check CSB flags. */\n\tif (getnn(cmdp->crb.csb, csb_v) == 0) {\n\t\tfprintf(stderr, \"CSB still not valid after %d polls.\\n\",\n\t\t\t(int) poll);\n\t\tprt_err(\"CSB still not valid after %d polls, giving up.\\n\",\n\t\t\t(int) poll);\n\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}",
        "static void smc_llc_send_request_add_link(struct smc_link *link)\n{\n\tstruct smc_llc_msg_req_add_link_v2 *llc;\n\tstruct smc_wr_tx_pend_priv *pend;\n\tstruct smc_wr_v2_buf *wr_buf;": "static void smc_llc_send_request_add_link(struct smc_link *link)\n{\n\tstruct smc_llc_msg_req_add_link_v2 *llc;\n\tstruct smc_wr_tx_pend_priv *pend;\n\tstruct smc_wr_v2_buf *wr_buf;\n\tstruct smc_gidlist gidlist;\n\tint rc, len, i;\n\n\tif (!smc_wr_tx_link_hold(link))\n\t\treturn;\n\tif (link->lgr->type == SMC_LGR_SYMMETRIC ||\n\t    link->lgr->type == SMC_LGR_ASYMMETRIC_PEER)\n\t\tgoto put_out;\n\n\tsmc_fill_gid_list(link->lgr, &gidlist, link->smcibdev, link->gid);\n\tif (gidlist.len <= 1)\n\t\tgoto put_out;\n\n\trc = smc_llc_add_pending_send_v2(link, &wr_buf, &pend);\n\tif (rc)\n\t\tgoto put_out;\n\tllc = (struct smc_llc_msg_req_add_link_v2 *)wr_buf;\n\tmemset(llc, 0, SMC_WR_TX_SIZE);\n\n\tllc->hd.common.llc_type = SMC_LLC_REQ_ADD_LINK;\n\tfor (i = 0; i < gidlist.len; i++)\n\t\tmemcpy(llc->gid[i], gidlist.list[i], sizeof(gidlist.list[0]));\n\tllc->gid_cnt = gidlist.len;\n\tlen = sizeof(*llc) + (gidlist.len * sizeof(gidlist.list[0]));\n\tsmc_llc_init_msg_hdr(&llc->hd, link->lgr, len);\n\trc = smc_wr_tx_v2_send(link, pend, len);\n\tif (!rc)\n\t\t/* set REQ_ADD_LINK flow and wait for response from peer */\n\t\tlink->lgr->llc_flow_lcl.type = SMC_LLC_FLOW_REQ_ADD_LINK;\nput_out:\n\tsmc_wr_tx_link_put(link);\n}",
        "static void sample_print_help(int mask)\n{\n\tprintf(\"Output format description\\n\\n\"\n\t       \"By default, redirect success statistics are disabled, use -s to enable.\\n\"\n\t       \"The terse output mode is default, verbose mode can be activated using -v\\n\"": "static void sample_print_help(int mask)\n{\n\tprintf(\"Output format description\\n\\n\"\n\t       \"By default, redirect success statistics are disabled, use -s to enable.\\n\"\n\t       \"The terse output mode is default, verbose mode can be activated using -v\\n\"\n\t       \"Use SIGQUIT (Ctrl + \\\\) to switch the mode dynamically at runtime\\n\\n\"\n\t       \"Terse mode displays at most the following fields:\\n\"\n\t       \"  rx/s        Number of packets received per second\\n\"\n\t       \"  redir/s     Number of packets successfully redirected per second\\n\"\n\t       \"  err,drop/s  Aggregated count of errors per second (including dropped packets)\\n\"\n\t       \"  xmit/s      Number of packets transmitted on the output device per second\\n\\n\"\n\t       \"Output description for verbose mode:\\n\"\n\t       \"  FIELD                 DESCRIPTION\\n\");\n\n\tif (mask & SAMPLE_RX_CNT) {\n\t\tprintf(\"  receive\\t\\tDisplays the number of packets received & errors encountered\\n\"\n\t\t       \" \\t\\t\\tWhenever an error or packet drop occurs, details of per CPU error\\n\"\n\t\t       \" \\t\\t\\tand drop statistics will be expanded inline in terse mode.\\n\"\n\t\t       \" \\t\\t\\t\\tpkt/s     - Packets received per second\\n\"\n\t\t       \" \\t\\t\\t\\tdrop/s    - Packets dropped per second\\n\"\n\t\t       \" \\t\\t\\t\\terror/s   - Errors encountered per second\\n\\n\");\n\t}\n\tif (mask & (SAMPLE_REDIRECT_CNT | SAMPLE_REDIRECT_ERR_CNT)) {\n\t\tprintf(\"  redirect\\t\\tDisplays the number of packets successfully redirected\\n\"\n\t\t       \"  \\t\\t\\tErrors encountered are expanded under redirect_err field\\n\"\n\t\t       \"  \\t\\t\\tNote that passing -s to enable it has a per packet overhead\\n\"\n\t\t       \"  \\t\\t\\t\\tredir/s   - Packets redirected successfully per second\\n\\n\"\n\t\t       \"  redirect_err\\t\\tDisplays the number of packets that failed redirection\\n\"\n\t\t       \"  \\t\\t\\tThe errno is expanded under this field with per CPU count\\n\"\n\t\t       \"  \\t\\t\\tThe recognized errors are:\\n\");\n\n\t\tfor (int i = 2; i < XDP_REDIRECT_ERR_MAX; i++)\n\t\t\tprintf(\"\\t\\t\\t  %s: %s\\n\", xdp_redirect_err_names[i],\n\t\t\t       xdp_redirect_err_help[i - 1]);\n\n\t\tprintf(\"  \\n\\t\\t\\t\\terror/s   - Packets that failed redirection per second\\n\\n\");\n\t}\n\n\tif (mask & SAMPLE_CPUMAP_ENQUEUE_CNT) {\n\t\tprintf(\"  enqueue to cpu N\\tDisplays the number of packets enqueued to bulk queue of CPU N\\n\"\n\t\t       \"  \\t\\t\\tExpands to cpu:FROM->N to display enqueue stats for each CPU enqueuing to CPU N\\n\"\n\t\t       \"  \\t\\t\\tReceived packets can be associated with the CPU redirect program is enqueuing \\n\"\n\t\t       \"  \\t\\t\\tpackets to.\\n\"\n\t\t       \"  \\t\\t\\t\\tpkt/s    - Packets enqueued per second from other CPU to CPU N\\n\"\n\t\t       \"  \\t\\t\\t\\tdrop/s   - Packets dropped when trying to enqueue to CPU N\\n\"\n\t\t       \"  \\t\\t\\t\\tbulk-avg - Average number of packets processed for each event\\n\\n\");\n\t}\n\n\tif (mask & SAMPLE_CPUMAP_KTHREAD_CNT) {\n\t\tprintf(\"  kthread\\t\\tDisplays the number of packets processed in CPUMAP kthread for each CPU\\n\"\n\t\t       \"  \\t\\t\\tPackets consumed from ptr_ring in kthread, and its xdp_stats (after calling \\n\"\n\t\t       \"  \\t\\t\\tCPUMAP bpf prog) are expanded below this. xdp_stats are expanded as a total and\\n\"\n\t\t       \"  \\t\\t\\tthen per-CPU to associate it to each CPU's pinned CPUMAP kthread.\\n\"\n\t\t       \"  \\t\\t\\t\\tpkt/s    - Packets consumed per second from ptr_ring\\n\"\n\t\t       \"  \\t\\t\\t\\tdrop/s   - Packets dropped per second in kthread\\n\"\n\t\t       \"  \\t\\t\\t\\tsched    - Number of times kthread called schedule()\\n\\n\"\n\t\t       \"  \\t\\t\\txdp_stats (also expands to per-CPU counts)\\n\"\n\t\t       \"  \\t\\t\\t\\tpass/s  - XDP_PASS count for CPUMAP program execution\\n\"\n\t\t       \"  \\t\\t\\t\\tdrop/s  - XDP_DROP count for CPUMAP program execution\\n\"\n\t\t       \"  \\t\\t\\t\\tredir/s - XDP_REDIRECT count for CPUMAP program execution\\n\\n\");\n\t}\n\n\tif (mask & SAMPLE_EXCEPTION_CNT) {\n\t\tprintf(\"  xdp_exception\\t\\tDisplays xdp_exception tracepoint events\\n\"\n\t\t       \"  \\t\\t\\tThis can occur due to internal driver errors, unrecognized\\n\"\n\t\t       \"  \\t\\t\\tXDP actions and due to explicit user trigger by use of XDP_ABORTED\\n\"\n\t\t       \"  \\t\\t\\tEach action is expanded below this field with its count\\n\"\n\t\t       \"  \\t\\t\\t\\thit/s     - Number of times the tracepoint was hit per second\\n\\n\");\n\t}\n\n\tif (mask & SAMPLE_DEVMAP_XMIT_CNT) {\n\t\tprintf(\"  devmap_xmit\\t\\tDisplays devmap_xmit tracepoint events\\n\"\n\t\t       \"  \\t\\t\\tThis tracepoint is invoked for successful transmissions on output\\n\"\n\t\t       \"  \\t\\t\\tdevice but these statistics are not available for generic XDP mode,\\n\"\n\t\t       \"  \\t\\t\\thence they will be omitted from the output when using SKB mode\\n\"\n\t\t       \"  \\t\\t\\t\\txmit/s    - Number of packets that were transmitted per second\\n\"\n\t\t       \"  \\t\\t\\t\\tdrop/s    - Number of packets that failed transmissions per second\\n\"\n\t\t       \"  \\t\\t\\t\\tdrv_err/s - Number of internal driver errors per second\\n\"\n\t\t       \"  \\t\\t\\t\\tbulk-avg  - Average number of packets processed for each event\\n\\n\");\n\t}\n}",
        "static void sbz_chipio_startup_data(struct hda_codec *codec)\n{\n\tconst struct chipio_stream_remap_data *dsp_out_remap_data;\n\tstruct ca0132_spec *spec = codec->spec;\n": "static void sbz_chipio_startup_data(struct hda_codec *codec)\n{\n\tconst struct chipio_stream_remap_data *dsp_out_remap_data;\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);\n\tcodec_dbg(codec, \"Startup Data entered, mutex locked and loaded.\\n\");\n\n\t/* Remap DAC0's output ports. */\n\tchipio_remap_stream(codec, &stream_remap_data[0]);\n\n\t/* Remap DSP audio output stream ports. */\n\tswitch (ca0132_quirk(spec)) {\n\tcase QUIRK_SBZ:\n\t\tdsp_out_remap_data = &stream_remap_data[1];\n\t\tbreak;\n\n\tcase QUIRK_ZXR:\n\t\tdsp_out_remap_data = &stream_remap_data[2];\n\t\tbreak;\n\n\tdefault:\n\t\tdsp_out_remap_data = NULL;\n\t\tbreak;\n\t}\n\n\tif (dsp_out_remap_data)\n\t\tchipio_remap_stream(codec, dsp_out_remap_data);\n\n\tcodec_dbg(codec, \"Startup Data exited, mutex released.\\n\");\n\tmutex_unlock(&spec->chipio_mutex);\n}",
        "static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg)\n{\n\tint idx, nr_field, key_off, field_marker, keyoff_marker;\n\tint max_key_off, max_bit_pos, group_member;\n\tstruct nix_rx_flowkey_alg *field;": "static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg)\n{\n\tint idx, nr_field, key_off, field_marker, keyoff_marker;\n\tint max_key_off, max_bit_pos, group_member;\n\tstruct nix_rx_flowkey_alg *field;\n\tstruct nix_rx_flowkey_alg tmp;\n\tu32 key_type, valid_key;\n\tint l4_key_offset = 0;\n\n\tif (!alg)\n\t\treturn -EINVAL;\n\n#define FIELDS_PER_ALG  5\n#define MAX_KEY_OFF\t40\n\t/* Clear all fields */\n\tmemset(alg, 0, sizeof(uint64_t) * FIELDS_PER_ALG);\n\n\t/* Each of the 32 possible flow key algorithm definitions should\n\t * fall into above incremental config (except ALG0). Otherwise a\n\t * single NPC MCAM entry is not sufficient for supporting RSS.\n\t *\n\t * If a different definition or combination needed then NPC MCAM\n\t * has to be programmed to filter such pkts and it's action should\n\t * point to this definition to calculate flowtag or hash.\n\t *\n\t * The `for loop` goes over _all_ protocol field and the following\n\t * variables depicts the state machine forward progress logic.\n\t *\n\t * keyoff_marker - Enabled when hash byte length needs to be accounted\n\t * in field->key_offset update.\n\t * field_marker - Enabled when a new field needs to be selected.\n\t * group_member - Enabled when protocol is part of a group.\n\t */\n\n\tkeyoff_marker = 0; max_key_off = 0; group_member = 0;\n\tnr_field = 0; key_off = 0; field_marker = 1;\n\tfield = &tmp; max_bit_pos = fls(flow_cfg);\n\tfor (idx = 0;\n\t     idx < max_bit_pos && nr_field < FIELDS_PER_ALG &&\n\t     key_off < MAX_KEY_OFF; idx++) {\n\t\tkey_type = BIT(idx);\n\t\tvalid_key = flow_cfg & key_type;\n\t\t/* Found a field marker, reset the field values */\n\t\tif (field_marker)\n\t\t\tmemset(&tmp, 0, sizeof(tmp));\n\n\t\tfield_marker = true;\n\t\tkeyoff_marker = true;\n\t\tswitch (key_type) {\n\t\tcase NIX_FLOW_KEY_TYPE_PORT:\n\t\t\tfield->sel_chan = true;\n\t\t\t/* This should be set to 1, when SEL_CHAN is set */\n\t\t\tfield->bytesm1 = 1;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_IPV4_PROTO:\n\t\t\tfield->lid = NPC_LID_LC;\n\t\t\tfield->hdr_offset = 9; /* offset */\n\t\t\tfield->bytesm1 = 0; /* 1 byte */\n\t\t\tfield->ltype_match = NPC_LT_LC_IP;\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_IPV4:\n\t\tcase NIX_FLOW_KEY_TYPE_INNR_IPV4:\n\t\t\tfield->lid = NPC_LID_LC;\n\t\t\tfield->ltype_match = NPC_LT_LC_IP;\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV4) {\n\t\t\t\tfield->lid = NPC_LID_LG;\n\t\t\t\tfield->ltype_match = NPC_LT_LG_TU_IP;\n\t\t\t}\n\t\t\tfield->hdr_offset = 12; /* SIP offset */\n\t\t\tfield->bytesm1 = 7; /* SIP + DIP, 8 bytes */\n\t\t\tfield->ltype_mask = 0xF; /* Match only IPv4 */\n\t\t\tkeyoff_marker = false;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_IPV6:\n\t\tcase NIX_FLOW_KEY_TYPE_INNR_IPV6:\n\t\t\tfield->lid = NPC_LID_LC;\n\t\t\tfield->ltype_match = NPC_LT_LC_IP6;\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV6) {\n\t\t\t\tfield->lid = NPC_LID_LG;\n\t\t\t\tfield->ltype_match = NPC_LT_LG_TU_IP6;\n\t\t\t}\n\t\t\tfield->hdr_offset = 8; /* SIP offset */\n\t\t\tfield->bytesm1 = 31; /* SIP + DIP, 32 bytes */\n\t\t\tfield->ltype_mask = 0xF; /* Match only IPv6 */\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_TCP:\n\t\tcase NIX_FLOW_KEY_TYPE_UDP:\n\t\tcase NIX_FLOW_KEY_TYPE_SCTP:\n\t\tcase NIX_FLOW_KEY_TYPE_INNR_TCP:\n\t\tcase NIX_FLOW_KEY_TYPE_INNR_UDP:\n\t\tcase NIX_FLOW_KEY_TYPE_INNR_SCTP:\n\t\t\tfield->lid = NPC_LID_LD;\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_INNR_TCP ||\n\t\t\t    key_type == NIX_FLOW_KEY_TYPE_INNR_UDP ||\n\t\t\t    key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP)\n\t\t\t\tfield->lid = NPC_LID_LH;\n\t\t\tfield->bytesm1 = 3; /* Sport + Dport, 4 bytes */\n\n\t\t\t/* Enum values for NPC_LID_LD and NPC_LID_LG are same,\n\t\t\t * so no need to change the ltype_match, just change\n\t\t\t * the lid for inner protocols\n\t\t\t */\n\t\t\tBUILD_BUG_ON((int)NPC_LT_LD_TCP !=\n\t\t\t\t     (int)NPC_LT_LH_TU_TCP);\n\t\t\tBUILD_BUG_ON((int)NPC_LT_LD_UDP !=\n\t\t\t\t     (int)NPC_LT_LH_TU_UDP);\n\t\t\tBUILD_BUG_ON((int)NPC_LT_LD_SCTP !=\n\t\t\t\t     (int)NPC_LT_LH_TU_SCTP);\n\n\t\t\tif ((key_type == NIX_FLOW_KEY_TYPE_TCP ||\n\t\t\t     key_type == NIX_FLOW_KEY_TYPE_INNR_TCP) &&\n\t\t\t    valid_key) {\n\t\t\t\tfield->ltype_match |= NPC_LT_LD_TCP;\n\t\t\t\tgroup_member = true;\n\t\t\t} else if ((key_type == NIX_FLOW_KEY_TYPE_UDP ||\n\t\t\t\t    key_type == NIX_FLOW_KEY_TYPE_INNR_UDP) &&\n\t\t\t\t   valid_key) {\n\t\t\t\tfield->ltype_match |= NPC_LT_LD_UDP;\n\t\t\t\tgroup_member = true;\n\t\t\t} else if ((key_type == NIX_FLOW_KEY_TYPE_SCTP ||\n\t\t\t\t    key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) &&\n\t\t\t\t   valid_key) {\n\t\t\t\tfield->ltype_match |= NPC_LT_LD_SCTP;\n\t\t\t\tgroup_member = true;\n\t\t\t}\n\t\t\tfield->ltype_mask = ~field->ltype_match;\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_SCTP ||\n\t\t\t    key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) {\n\t\t\t\t/* Handle the case where any of the group item\n\t\t\t\t * is enabled in the group but not the final one\n\t\t\t\t */\n\t\t\t\tif (group_member) {\n\t\t\t\t\tvalid_key = true;\n\t\t\t\t\tgroup_member = false;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tfield_marker = false;\n\t\t\t\tkeyoff_marker = false;\n\t\t\t}\n\n\t\t\t/* TCP/UDP/SCTP and ESP/AH falls at same offset so\n\t\t\t * remember the TCP key offset of 40 byte hash key.\n\t\t\t */\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_TCP)\n\t\t\t\tl4_key_offset = key_off;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_NVGRE:\n\t\t\tfield->lid = NPC_LID_LD;\n\t\t\tfield->hdr_offset = 4; /* VSID offset */\n\t\t\tfield->bytesm1 = 2;\n\t\t\tfield->ltype_match = NPC_LT_LD_NVGRE;\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_VXLAN:\n\t\tcase NIX_FLOW_KEY_TYPE_GENEVE:\n\t\t\tfield->lid = NPC_LID_LE;\n\t\t\tfield->bytesm1 = 2;\n\t\t\tfield->hdr_offset = 4;\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tfield_marker = false;\n\t\t\tkeyoff_marker = false;\n\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_VXLAN && valid_key) {\n\t\t\t\tfield->ltype_match |= NPC_LT_LE_VXLAN;\n\t\t\t\tgroup_member = true;\n\t\t\t}\n\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_GENEVE && valid_key) {\n\t\t\t\tfield->ltype_match |= NPC_LT_LE_GENEVE;\n\t\t\t\tgroup_member = true;\n\t\t\t}\n\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_GENEVE) {\n\t\t\t\tif (group_member) {\n\t\t\t\t\tfield->ltype_mask = ~field->ltype_match;\n\t\t\t\t\tfield_marker = true;\n\t\t\t\t\tkeyoff_marker = true;\n\t\t\t\t\tvalid_key = true;\n\t\t\t\t\tgroup_member = false;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_ETH_DMAC:\n\t\tcase NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC:\n\t\t\tfield->lid = NPC_LID_LA;\n\t\t\tfield->ltype_match = NPC_LT_LA_ETHER;\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC) {\n\t\t\t\tfield->lid = NPC_LID_LF;\n\t\t\t\tfield->ltype_match = NPC_LT_LF_TU_ETHER;\n\t\t\t}\n\t\t\tfield->hdr_offset = 0;\n\t\t\tfield->bytesm1 = 5; /* DMAC 6 Byte */\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_IPV6_EXT:\n\t\t\tfield->lid = NPC_LID_LC;\n\t\t\tfield->hdr_offset = 40; /* IPV6 hdr */\n\t\t\tfield->bytesm1 = 0; /* 1 Byte ext hdr*/\n\t\t\tfield->ltype_match = NPC_LT_LC_IP6_EXT;\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_GTPU:\n\t\t\tfield->lid = NPC_LID_LE;\n\t\t\tfield->hdr_offset = 4;\n\t\t\tfield->bytesm1 = 3; /* 4 bytes TID*/\n\t\t\tfield->ltype_match = NPC_LT_LE_GTPU;\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_VLAN:\n\t\t\tfield->lid = NPC_LID_LB;\n\t\t\tfield->hdr_offset = 2; /* Skip TPID (2-bytes) */\n\t\t\tfield->bytesm1 = 1; /* 2 Bytes (Actually 12 bits) */\n\t\t\tfield->ltype_match = NPC_LT_LB_CTAG;\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tfield->fn_mask = 1; /* Mask out the first nibble */\n\t\t\tbreak;\n\t\tcase NIX_FLOW_KEY_TYPE_AH:\n\t\tcase NIX_FLOW_KEY_TYPE_ESP:\n\t\t\tfield->hdr_offset = 0;\n\t\t\tfield->bytesm1 = 7; /* SPI + sequence number */\n\t\t\tfield->ltype_mask = 0xF;\n\t\t\tfield->lid = NPC_LID_LE;\n\t\t\tfield->ltype_match = NPC_LT_LE_ESP;\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_AH) {\n\t\t\t\tfield->lid = NPC_LID_LD;\n\t\t\t\tfield->ltype_match = NPC_LT_LD_AH;\n\t\t\t\tfield->hdr_offset = 4;\n\t\t\t\tkeyoff_marker = false;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tfield->ena = 1;\n\n\t\t/* Found a valid flow key type */\n\t\tif (valid_key) {\n\t\t\t/* Use the key offset of TCP/UDP/SCTP fields\n\t\t\t * for ESP/AH fields.\n\t\t\t */\n\t\t\tif (key_type == NIX_FLOW_KEY_TYPE_ESP ||\n\t\t\t    key_type == NIX_FLOW_KEY_TYPE_AH)\n\t\t\t\tkey_off = l4_key_offset;\n\t\t\tfield->key_offset = key_off;\n\t\t\tmemcpy(&alg[nr_field], field, sizeof(*field));\n\t\t\tmax_key_off = max(max_key_off, field->bytesm1 + 1);\n\n\t\t\t/* Found a field marker, get the next field */\n\t\t\tif (field_marker)\n\t\t\t\tnr_field++;\n\t\t}\n\n\t\t/* Found a keyoff marker, update the new key_off */\n\t\tif (keyoff_marker) {\n\t\t\tkey_off += max_key_off;\n\t\t\tmax_key_off = 0;\n\t\t}\n\t}\n\t/* Processed all the flow key types */\n\tif (idx == max_bit_pos && key_off <= MAX_KEY_OFF)\n\t\treturn 0;\n\telse\n\t\treturn NIX_AF_ERR_RSS_NOSPC_FIELD;\n}",
        "static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)\n{\n\t/*\n\t * Disable PCI Bus Parking and PCI Master read caching on CX700\n\t * which causes unspecified timing errors with a VT6212L on the PCI": "static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)\n{\n\t/*\n\t * Disable PCI Bus Parking and PCI Master read caching on CX700\n\t * which causes unspecified timing errors with a VT6212L on the PCI\n\t * bus leading to USB2.0 packet loss.\n\t *\n\t * This quirk is only enabled if a second (on the external PCI bus)\n\t * VT6212L is found -- the CX700 core itself also contains a USB\n\t * host controller with the same PCI ID as the VT6212L.\n\t */\n\n\t/* Count VT6212L instances */\n\tstruct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,\n\t\tPCI_DEVICE_ID_VIA_8235_USB_2, NULL);\n\tuint8_t b;\n\n\t/*\n\t * p should contain the first (internal) VT6212L -- see if we have\n\t * an external one by searching again.\n\t */\n\tp = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);\n\tif (!p)\n\t\treturn;\n\tpci_dev_put(p);\n\n\tif (pci_read_config_byte(dev, 0x76, &b) == 0) {\n\t\tif (b & 0x40) {\n\t\t\t/* Turn off PCI Bus Parking */\n\t\t\tpci_write_config_byte(dev, 0x76, b ^ 0x40);\n\n\t\t\tpci_info(dev, \"Disabling VIA CX700 PCI parking\\n\");\n\t\t}\n\t}\n\n\tif (pci_read_config_byte(dev, 0x72, &b) == 0) {\n\t\tif (b != 0) {\n\t\t\t/* Turn off PCI Master read caching */\n\t\t\tpci_write_config_byte(dev, 0x72, 0x0);\n\n\t\t\t/* Set PCI Master Bus time-out to \"1x16 PCLK\" */\n\t\t\tpci_write_config_byte(dev, 0x75, 0x1);\n\n\t\t\t/* Disable \"Read FIFO Timer\" */\n\t\t\tpci_write_config_byte(dev, 0x77, 0x0);\n\n\t\t\tpci_info(dev, \"Disabling VIA CX700 PCI caching\\n\");\n\t\t}\n\t}\n}",
        "static void ae5_register_set(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);\n\tconst unsigned int *addr = ca0132_ae5_register_set_addresses;": "static void ae5_register_set(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);\n\tconst unsigned int *addr = ca0132_ae5_register_set_addresses;\n\tconst unsigned char *data = ca0132_ae5_register_set_data;\n\tunsigned int i, cur_addr;\n\tunsigned char tmp[3];\n\n\tif (ca0132_quirk(spec) == QUIRK_AE7)\n\t\tchipio_8051_write_pll_pmu(codec, 0x41, 0xc8);\n\n\tchipio_8051_write_direct(codec, 0x93, 0x10);\n\tchipio_8051_write_pll_pmu(codec, 0x44, 0xc2);\n\n\tif (ca0132_quirk(spec) == QUIRK_AE7) {\n\t\ttmp[0] = 0x03;\n\t\ttmp[1] = 0x03;\n\t\ttmp[2] = 0x07;\n\t} else {\n\t\ttmp[0] = 0x0f;\n\t\ttmp[1] = 0x0f;\n\t\ttmp[2] = 0x0f;\n\t}\n\n\tfor (i = cur_addr = 0; i < 3; i++, cur_addr++)\n\t\twriteb(tmp[i], spec->mem_base + addr[cur_addr]);\n\n\t/*\n\t * First writes are in single bytes, final are in 4 bytes. So, we use\n\t * writeb, then writel.\n\t */\n\tfor (i = 0; cur_addr < 12; i++, cur_addr++)\n\t\twriteb(data[i], spec->mem_base + addr[cur_addr]);\n\n\tfor (; cur_addr < count; i++, cur_addr++)\n\t\twritel(data[i], spec->mem_base + addr[cur_addr]);\n\n\twritel(0x00800001, spec->mem_base + 0x20c);\n\n\tif (ca0132_quirk(spec) == QUIRK_AE7) {\n\t\tca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);\n\t\tca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);\n\t} else {\n\t\tca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);\n\t}\n\n\tchipio_8051_write_direct(codec, 0x90, 0x00);\n\tchipio_8051_write_direct(codec, 0x90, 0x10);\n\n\tif (ca0132_quirk(spec) == QUIRK_AE5)\n\t\tca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);\n}",
        "static int get_empty_pcm_device(struct hda_bus *bus, unsigned int type)\n{\n\t/* audio device indices; not linear to keep compatibility */\n\t/* assigned to static slots up to dev#10; if more needed, assign\n\t * the later slot dynamically (when CONFIG_SND_DYNAMIC_MINORS=y)": "static int get_empty_pcm_device(struct hda_bus *bus, unsigned int type)\n{\n\t/* audio device indices; not linear to keep compatibility */\n\t/* assigned to static slots up to dev#10; if more needed, assign\n\t * the later slot dynamically (when CONFIG_SND_DYNAMIC_MINORS=y)\n\t */\n\tstatic const int audio_idx[HDA_PCM_NTYPES][5] = {\n\t\t[HDA_PCM_TYPE_AUDIO] = { 0, 2, 4, 5, -1 },\n\t\t[HDA_PCM_TYPE_SPDIF] = { 1, -1 },\n\t\t[HDA_PCM_TYPE_HDMI]  = { 3, 7, 8, 9, -1 },\n\t\t[HDA_PCM_TYPE_MODEM] = { 6, -1 },\n\t};\n\tint i;\n\n\tif (type >= HDA_PCM_NTYPES) {\n\t\tdev_err(bus->card->dev, \"Invalid PCM type %d\\n\", type);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; audio_idx[type][i] >= 0; i++) {\n#ifndef CONFIG_SND_DYNAMIC_MINORS\n\t\tif (audio_idx[type][i] >= 8)\n\t\t\tbreak;\n#endif\n\t\tif (!test_and_set_bit(audio_idx[type][i], bus->pcm_dev_bits))\n\t\t\treturn audio_idx[type][i];\n\t}\n\n#ifdef CONFIG_SND_DYNAMIC_MINORS\n\t/* non-fixed slots starting from 10 */\n\tfor (i = 10; i < 32; i++) {\n\t\tif (!test_and_set_bit(i, bus->pcm_dev_bits))\n\t\t\treturn i;\n\t}\n#endif\n\n\tdev_warn(bus->card->dev, \"Too many %s devices\\n\",\n\t\tsnd_hda_pcm_type_name[type]);\n#ifndef CONFIG_SND_DYNAMIC_MINORS\n\tdev_warn(bus->card->dev,\n\t\t \"Consider building the kernel with CONFIG_SND_DYNAMIC_MINORS=y\\n\");\n#endif\n\treturn -EAGAIN;\n}",
        "static void replay_journal(struct dm_integrity_c *ic)\n{\n\tunsigned i, j;\n\tbool used_commit_ids[N_COMMIT_IDS];\n\tunsigned max_commit_id_sections[N_COMMIT_IDS];": "static void replay_journal(struct dm_integrity_c *ic)\n{\n\tunsigned i, j;\n\tbool used_commit_ids[N_COMMIT_IDS];\n\tunsigned max_commit_id_sections[N_COMMIT_IDS];\n\tunsigned write_start, write_sections;\n\tunsigned continue_section;\n\tbool journal_empty;\n\tunsigned char unused, last_used, want_commit_seq;\n\n\tif (ic->mode == 'R')\n\t\treturn;\n\n\tif (ic->journal_uptodate)\n\t\treturn;\n\n\tlast_used = 0;\n\twrite_start = 0;\n\n\tif (!ic->just_formatted) {\n\t\tDEBUG_print(\"reading journal\\n\");\n\t\trw_journal(ic, REQ_OP_READ, 0, 0, ic->journal_sections, NULL);\n\t\tif (ic->journal_io)\n\t\t\tDEBUG_bytes(lowmem_page_address(ic->journal_io[0].page), 64, \"read journal\");\n\t\tif (ic->journal_io) {\n\t\t\tstruct journal_completion crypt_comp;\n\t\t\tcrypt_comp.ic = ic;\n\t\t\tinit_completion(&crypt_comp.comp);\n\t\t\tcrypt_comp.in_flight = (atomic_t)ATOMIC_INIT(0);\n\t\t\tencrypt_journal(ic, false, 0, ic->journal_sections, &crypt_comp);\n\t\t\twait_for_completion(&crypt_comp.comp);\n\t\t}\n\t\tDEBUG_bytes(lowmem_page_address(ic->journal[0].page), 64, \"decrypted journal\");\n\t}\n\n\tif (dm_integrity_failed(ic))\n\t\tgoto clear_journal;\n\n\tjournal_empty = true;\n\tmemset(used_commit_ids, 0, sizeof used_commit_ids);\n\tmemset(max_commit_id_sections, 0, sizeof max_commit_id_sections);\n\tfor (i = 0; i < ic->journal_sections; i++) {\n\t\tfor (j = 0; j < ic->journal_section_sectors; j++) {\n\t\t\tint k;\n\t\t\tstruct journal_sector *js = access_journal(ic, i, j);\n\t\t\tk = find_commit_seq(ic, i, j, js->commit_id);\n\t\t\tif (k < 0)\n\t\t\t\tgoto clear_journal;\n\t\t\tused_commit_ids[k] = true;\n\t\t\tmax_commit_id_sections[k] = i;\n\t\t}\n\t\tif (journal_empty) {\n\t\t\tfor (j = 0; j < ic->journal_section_entries; j++) {\n\t\t\t\tstruct journal_entry *je = access_journal_entry(ic, i, j);\n\t\t\t\tif (!journal_entry_is_unused(je)) {\n\t\t\t\t\tjournal_empty = false;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tif (!used_commit_ids[N_COMMIT_IDS - 1]) {\n\t\tunused = N_COMMIT_IDS - 1;\n\t\twhile (unused && !used_commit_ids[unused - 1])\n\t\t\tunused--;\n\t} else {\n\t\tfor (unused = 0; unused < N_COMMIT_IDS; unused++)\n\t\t\tif (!used_commit_ids[unused])\n\t\t\t\tbreak;\n\t\tif (unused == N_COMMIT_IDS) {\n\t\t\tdm_integrity_io_error(ic, \"journal commit ids\", -EIO);\n\t\t\tgoto clear_journal;\n\t\t}\n\t}\n\tDEBUG_print(\"first unused commit seq %d [%d,%d,%d,%d]\\n\",\n\t\t    unused, used_commit_ids[0], used_commit_ids[1],\n\t\t    used_commit_ids[2], used_commit_ids[3]);\n\n\tlast_used = prev_commit_seq(unused);\n\twant_commit_seq = prev_commit_seq(last_used);\n\n\tif (!used_commit_ids[want_commit_seq] && used_commit_ids[prev_commit_seq(want_commit_seq)])\n\t\tjournal_empty = true;\n\n\twrite_start = max_commit_id_sections[last_used] + 1;\n\tif (unlikely(write_start >= ic->journal_sections))\n\t\twant_commit_seq = next_commit_seq(want_commit_seq);\n\twraparound_section(ic, &write_start);\n\n\ti = write_start;\n\tfor (write_sections = 0; write_sections < ic->journal_sections; write_sections++) {\n\t\tfor (j = 0; j < ic->journal_section_sectors; j++) {\n\t\t\tstruct journal_sector *js = access_journal(ic, i, j);\n\n\t\t\tif (js->commit_id != dm_integrity_commit_id(ic, i, j, want_commit_seq)) {\n\t\t\t\t/*\n\t\t\t\t * This could be caused by crash during writing.\n\t\t\t\t * We won't replay the inconsistent part of the\n\t\t\t\t * journal.\n\t\t\t\t */\n\t\t\t\tDEBUG_print(\"commit id mismatch at position (%u, %u): %d != %d\\n\",\n\t\t\t\t\t    i, j, find_commit_seq(ic, i, j, js->commit_id), want_commit_seq);\n\t\t\t\tgoto brk;\n\t\t\t}\n\t\t}\n\t\ti++;\n\t\tif (unlikely(i >= ic->journal_sections))\n\t\t\twant_commit_seq = next_commit_seq(want_commit_seq);\n\t\twraparound_section(ic, &i);\n\t}\nbrk:\n\n\tif (!journal_empty) {\n\t\tDEBUG_print(\"replaying %u sections, starting at %u, commit seq %d\\n\",\n\t\t\t    write_sections, write_start, want_commit_seq);\n\t\tdo_journal_write(ic, write_start, write_sections, true);\n\t}\n\n\tif (write_sections == ic->journal_sections && (ic->mode == 'J' || journal_empty)) {\n\t\tcontinue_section = write_start;\n\t\tic->commit_seq = want_commit_seq;\n\t\tDEBUG_print(\"continuing from section %u, commit seq %d\\n\", write_start, ic->commit_seq);\n\t} else {\n\t\tunsigned s;\n\t\tunsigned char erase_seq;\nclear_journal:\n\t\tDEBUG_print(\"clearing journal\\n\");\n\n\t\terase_seq = prev_commit_seq(prev_commit_seq(last_used));\n\t\ts = write_start;\n\t\tinit_journal(ic, s, 1, erase_seq);\n\t\ts++;\n\t\twraparound_section(ic, &s);\n\t\tif (ic->journal_sections >= 2) {\n\t\t\tinit_journal(ic, s, ic->journal_sections - 2, erase_seq);\n\t\t\ts += ic->journal_sections - 2;\n\t\t\twraparound_section(ic, &s);\n\t\t\tinit_journal(ic, s, 1, erase_seq);\n\t\t}\n\n\t\tcontinue_section = 0;\n\t\tic->commit_seq = next_commit_seq(erase_seq);\n\t}\n\n\tic->committed_section = continue_section;\n\tic->n_committed_sections = 0;\n\n\tic->uncommitted_section = continue_section;\n\tic->n_uncommitted_sections = 0;\n\n\tic->free_section = continue_section;\n\tic->free_section_entry = 0;\n\tic->free_sectors = ic->journal_entries;\n\n\tic->journal_tree_root = RB_ROOT;\n\tfor (i = 0; i < ic->journal_entries; i++)\n\t\tinit_journal_node(&ic->journal_tree[i]);\n}",
        "static void flyvideo_gpio(struct bttv *btv)\n{\n\tint gpio, has_remote, has_radio, is_capture_only;\n\tint is_lr90, has_tda9820_tda9821;\n\tint tuner_type = UNSET, ttype;": "static void flyvideo_gpio(struct bttv *btv)\n{\n\tint gpio, has_remote, has_radio, is_capture_only;\n\tint is_lr90, has_tda9820_tda9821;\n\tint tuner_type = UNSET, ttype;\n\n\tgpio_inout(0xffffff, 0);\n\tudelay(8);  /* without this we would see the 0x1800 mask */\n\tgpio = gpio_read();\n\t/* FIXME: must restore OUR_EN ??? */\n\n\t/* all cards provide GPIO info, some have an additional eeprom\n\t * LR50: GPIO coding can be found lower right CP1 .. CP9\n\t *       CP9=GPIO23 .. CP1=GPIO15; when OPEN, the corresponding GPIO reads 1.\n\t *       GPIO14-12: n.c.\n\t * LR90: GP9=GPIO23 .. GP1=GPIO15 (right above the bt878)\n\n\t * lowest 3 bytes are remote control codes (no handshake needed)\n\t * xxxFFF: No remote control chip soldered\n\t * xxxF00(LR26/LR50), xxxFE0(LR90): Remote control chip (LVA001 or CF45) soldered\n\t * Note: Some bits are Audio_Mask !\n\t */\n\tttype = (gpio & 0x0f0000) >> 16;\n\tswitch (ttype) {\n\tcase 0x0:\n\t\ttuner_type = 2;  /* NTSC, e.g. TPI8NSR11P */\n\t\tbreak;\n\tcase 0x2:\n\t\ttuner_type = 39; /* LG NTSC (newer TAPC series) TAPC-H701P */\n\t\tbreak;\n\tcase 0x4:\n\t\ttuner_type = 5;  /* Philips PAL TPI8PSB02P, TPI8PSB12P, TPI8PSB12D or FI1216, FM1216 */\n\t\tbreak;\n\tcase 0x6:\n\t\ttuner_type = 37; /* LG PAL (newer TAPC series) TAPC-G702P */\n\t\tbreak;\n\tcase 0xC:\n\t\ttuner_type = 3;  /* Philips SECAM(+PAL) FQ1216ME or FI1216MF */\n\t\tbreak;\n\tdefault:\n\t\tpr_info(\"%d: FlyVideo_gpio: unknown tuner type\\n\", btv->c.nr);\n\t\tbreak;\n\t}\n\n\thas_remote          =   gpio & 0x800000;\n\thas_radio\t    =   gpio & 0x400000;\n\t/*   unknown                   0x200000;\n\t *   unknown2                  0x100000; */\n\tis_capture_only     = !(gpio & 0x008000); /* GPIO15 */\n\thas_tda9820_tda9821 = !(gpio & 0x004000);\n\tis_lr90             = !(gpio & 0x002000); /* else LR26/LR50 (LR38/LR51 f. capture only) */\n\t/*\n\t * gpio & 0x001000    output bit for audio routing */\n\n\tif (is_capture_only)\n\t\ttuner_type = TUNER_ABSENT; /* No tuner present */\n\n\tpr_info(\"%d: FlyVideo Radio=%s RemoteControl=%s Tuner=%d gpio=0x%06x\\n\",\n\t\tbtv->c.nr, has_radio ? \"yes\" : \"no\",\n\t\thas_remote ? \"yes\" : \"no\", tuner_type, gpio);\n\tpr_info(\"%d: FlyVideo  LR90=%s tda9821/tda9820=%s capture_only=%s\\n\",\n\t\tbtv->c.nr, is_lr90 ? \"yes\" : \"no\",\n\t\thas_tda9820_tda9821 ? \"yes\" : \"no\",\n\t\tis_capture_only ? \"yes\" : \"no\");\n\n\tif (tuner_type != UNSET) /* only set if known tuner autodetected, else let insmod option through */\n\t\tbtv->tuner_type = tuner_type;\n\tbtv->has_radio = has_radio;\n\n\t/* LR90 Audio Routing is done by 2 hef4052, so Audio_Mask has 4 bits: 0x001c80\n\t * LR26/LR50 only has 1 hef4052, Audio_Mask 0x000c00\n\t * Audio options: from tuner, from tda9821/tda9821(mono,stereo,sap), from tda9874, ext., mute */\n\tif (has_tda9820_tda9821)\n\t\tbtv->audio_mode_gpio = lt9415_audio;\n\t/* todo: if(has_tda9874) btv->audio_mode_gpio = fv2000s_audio; */\n}",
        "static int mn88443x_t_set_freq(struct mn88443x_priv *chip)\n{\n\tstruct device *dev = &chip->client_s->dev;\n\tstruct regmap *r_t = chip->regmap_t;\n\ts64 adckt, nco, ad_t;": "static int mn88443x_t_set_freq(struct mn88443x_priv *chip)\n{\n\tstruct device *dev = &chip->client_s->dev;\n\tstruct regmap *r_t = chip->regmap_t;\n\ts64 adckt, nco, ad_t;\n\tu32 m, v;\n\n\t/* Clock buffer (but not supported) or XTAL */\n\tif (chip->clk_freq >= CLK_LOW && chip->clk_freq < CLK_DIRECT) {\n\t\tchip->use_clkbuf = true;\n\t\tregmap_write(r_t, CLKSET1_T, 0x07);\n\n\t\tadckt = 0;\n\t} else {\n\t\tchip->use_clkbuf = false;\n\t\tregmap_write(r_t, CLKSET1_T, 0x00);\n\n\t\tadckt = chip->clk_freq;\n\t}\n\tif (!mn88443x_t_is_valid_clk(adckt, chip->if_freq)) {\n\t\tdev_err(dev, \"Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\\n\",\n\t\t\tchip->clk_freq, adckt, chip->if_freq);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Direct IF or Low IF */\n\tif (chip->if_freq == DIRECT_IF_57MHZ ||\n\t    chip->if_freq == DIRECT_IF_44MHZ)\n\t\tnco = adckt * 2 - chip->if_freq;\n\telse\n\t\tnco = -((s64)chip->if_freq);\n\tnco = div_s64(nco << 24, adckt);\n\tad_t = div_s64(adckt << 22, S_T_FREQ);\n\n\tregmap_write(r_t, NCOFREQU_T, nco >> 16);\n\tregmap_write(r_t, NCOFREQM_T, nco >> 8);\n\tregmap_write(r_t, NCOFREQL_T, nco);\n\tregmap_write(r_t, FADU_T, ad_t >> 16);\n\tregmap_write(r_t, FADM_T, ad_t >> 8);\n\tregmap_write(r_t, FADL_T, ad_t);\n\n\t/* Level of IF */\n\tm = ADCSET1_T_REFSEL_MASK;\n\tv = ADCSET1_T_REFSEL_1_5V;\n\tregmap_update_bits(r_t, ADCSET1_T, m, v);\n\n\t/* Polarity of AGC */\n\tv = AGCSET2_T_IFPOLINV_INC | AGCSET2_T_RFPOLINV_INC;\n\tregmap_update_bits(r_t, AGCSET2_T, v, v);\n\n\t/* Lower output level of AGC */\n\tregmap_write(r_t, AGCV3_T, 0x00);\n\n\tregmap_write(r_t, MDSET_T, 0xfa);\n\n\treturn 0;\n}",
        "static int tg3_rx(struct tg3_napi *tnapi, int budget)\n{\n\tstruct tg3 *tp = tnapi->tp;\n\tu32 work_mask, rx_std_posted = 0;\n\tu32 std_prod_idx, jmb_prod_idx;": "static int tg3_rx(struct tg3_napi *tnapi, int budget)\n{\n\tstruct tg3 *tp = tnapi->tp;\n\tu32 work_mask, rx_std_posted = 0;\n\tu32 std_prod_idx, jmb_prod_idx;\n\tu32 sw_idx = tnapi->rx_rcb_ptr;\n\tu16 hw_idx;\n\tint received;\n\tstruct tg3_rx_prodring_set *tpr = &tnapi->prodring;\n\n\thw_idx = *(tnapi->rx_rcb_prod_idx);\n\t/*\n\t * We need to order the read of hw_idx and the read of\n\t * the opaque cookie.\n\t */\n\trmb();\n\twork_mask = 0;\n\treceived = 0;\n\tstd_prod_idx = tpr->rx_std_prod_idx;\n\tjmb_prod_idx = tpr->rx_jmb_prod_idx;\n\twhile (sw_idx != hw_idx && budget > 0) {\n\t\tstruct ring_info *ri;\n\t\tstruct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];\n\t\tunsigned int len;\n\t\tstruct sk_buff *skb;\n\t\tdma_addr_t dma_addr;\n\t\tu32 opaque_key, desc_idx, *post_ptr;\n\t\tu8 *data;\n\t\tu64 tstamp = 0;\n\n\t\tdesc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;\n\t\topaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;\n\t\tif (opaque_key == RXD_OPAQUE_RING_STD) {\n\t\t\tri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];\n\t\t\tdma_addr = dma_unmap_addr(ri, mapping);\n\t\t\tdata = ri->data;\n\t\t\tpost_ptr = &std_prod_idx;\n\t\t\trx_std_posted++;\n\t\t} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {\n\t\t\tri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];\n\t\t\tdma_addr = dma_unmap_addr(ri, mapping);\n\t\t\tdata = ri->data;\n\t\t\tpost_ptr = &jmb_prod_idx;\n\t\t} else\n\t\t\tgoto next_pkt_nopost;\n\n\t\twork_mask |= opaque_key;\n\n\t\tif (desc->err_vlan & RXD_ERR_MASK) {\n\t\tdrop_it:\n\t\t\ttg3_recycle_rx(tnapi, tpr, opaque_key,\n\t\t\t\t       desc_idx, *post_ptr);\n\t\tdrop_it_no_recycle:\n\t\t\t/* Other statistics kept track of by card. */\n\t\t\ttp->rx_dropped++;\n\t\t\tgoto next_pkt;\n\t\t}\n\n\t\tprefetch(data + TG3_RX_OFFSET(tp));\n\t\tlen = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -\n\t\t      ETH_FCS_LEN;\n\n\t\tif ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==\n\t\t     RXD_FLAG_PTPSTAT_PTPV1 ||\n\t\t    (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==\n\t\t     RXD_FLAG_PTPSTAT_PTPV2) {\n\t\t\ttstamp = tr32(TG3_RX_TSTAMP_LSB);\n\t\t\ttstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;\n\t\t}\n\n\t\tif (len > TG3_RX_COPY_THRESH(tp)) {\n\t\t\tint skb_size;\n\t\t\tunsigned int frag_size;\n\n\t\t\tskb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,\n\t\t\t\t\t\t    *post_ptr, &frag_size);\n\t\t\tif (skb_size < 0)\n\t\t\t\tgoto drop_it;\n\n\t\t\tdma_unmap_single(&tp->pdev->dev, dma_addr, skb_size,\n\t\t\t\t\t DMA_FROM_DEVICE);\n\n\t\t\t/* Ensure that the update to the data happens\n\t\t\t * after the usage of the old DMA mapping.\n\t\t\t */\n\t\t\tsmp_wmb();\n\n\t\t\tri->data = NULL;\n\n\t\t\tskb = build_skb(data, frag_size);\n\t\t\tif (!skb) {\n\t\t\t\ttg3_frag_free(frag_size != 0, data);\n\t\t\t\tgoto drop_it_no_recycle;\n\t\t\t}\n\t\t\tskb_reserve(skb, TG3_RX_OFFSET(tp));\n\t\t} else {\n\t\t\ttg3_recycle_rx(tnapi, tpr, opaque_key,\n\t\t\t\t       desc_idx, *post_ptr);\n\n\t\t\tskb = netdev_alloc_skb(tp->dev,\n\t\t\t\t\t       len + TG3_RAW_IP_ALIGN);\n\t\t\tif (skb == NULL)\n\t\t\t\tgoto drop_it_no_recycle;\n\n\t\t\tskb_reserve(skb, TG3_RAW_IP_ALIGN);\n\t\t\tdma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len,\n\t\t\t\t\t\tDMA_FROM_DEVICE);\n\t\t\tmemcpy(skb->data,\n\t\t\t       data + TG3_RX_OFFSET(tp),\n\t\t\t       len);\n\t\t\tdma_sync_single_for_device(&tp->pdev->dev, dma_addr,\n\t\t\t\t\t\t   len, DMA_FROM_DEVICE);\n\t\t}\n\n\t\tskb_put(skb, len);\n\t\tif (tstamp)\n\t\t\ttg3_hwclock_to_timestamp(tp, tstamp,\n\t\t\t\t\t\t skb_hwtstamps(skb));\n\n\t\tif ((tp->dev->features & NETIF_F_RXCSUM) &&\n\t\t    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&\n\t\t    (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)\n\t\t      >> RXD_TCPCSUM_SHIFT) == 0xffff))\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t\telse\n\t\t\tskb_checksum_none_assert(skb);\n\n\t\tskb->protocol = eth_type_trans(skb, tp->dev);\n\n\t\tif (len > (tp->dev->mtu + ETH_HLEN) &&\n\t\t    skb->protocol != htons(ETH_P_8021Q) &&\n\t\t    skb->protocol != htons(ETH_P_8021AD)) {\n\t\t\tdev_kfree_skb_any(skb);\n\t\t\tgoto drop_it_no_recycle;\n\t\t}\n\n\t\tif (desc->type_flags & RXD_FLAG_VLAN &&\n\t\t    !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))\n\t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),\n\t\t\t\t\t       desc->err_vlan & RXD_VLAN_MASK);\n\n\t\tnapi_gro_receive(&tnapi->napi, skb);\n\n\t\treceived++;\n\t\tbudget--;\n\nnext_pkt:\n\t\t(*post_ptr)++;\n\n\t\tif (unlikely(rx_std_posted >= tp->rx_std_max_post)) {\n\t\t\ttpr->rx_std_prod_idx = std_prod_idx &\n\t\t\t\t\t       tp->rx_std_ring_mask;\n\t\t\ttw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,\n\t\t\t\t     tpr->rx_std_prod_idx);\n\t\t\twork_mask &= ~RXD_OPAQUE_RING_STD;\n\t\t\trx_std_posted = 0;\n\t\t}\nnext_pkt_nopost:\n\t\tsw_idx++;\n\t\tsw_idx &= tp->rx_ret_ring_mask;\n\n\t\t/* Refresh hw_idx to see if there is new work */\n\t\tif (sw_idx == hw_idx) {\n\t\t\thw_idx = *(tnapi->rx_rcb_prod_idx);\n\t\t\trmb();\n\t\t}\n\t}\n\n\t/* ACK the status ring. */\n\ttnapi->rx_rcb_ptr = sw_idx;\n\ttw32_rx_mbox(tnapi->consmbox, sw_idx);\n\n\t/* Refill RX ring(s). */\n\tif (!tg3_flag(tp, ENABLE_RSS)) {\n\t\t/* Sync BD data before updating mailbox */\n\t\twmb();\n\n\t\tif (work_mask & RXD_OPAQUE_RING_STD) {\n\t\t\ttpr->rx_std_prod_idx = std_prod_idx &\n\t\t\t\t\t       tp->rx_std_ring_mask;\n\t\t\ttw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,\n\t\t\t\t     tpr->rx_std_prod_idx);\n\t\t}\n\t\tif (work_mask & RXD_OPAQUE_RING_JUMBO) {\n\t\t\ttpr->rx_jmb_prod_idx = jmb_prod_idx &\n\t\t\t\t\t       tp->rx_jmb_ring_mask;\n\t\t\ttw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,\n\t\t\t\t     tpr->rx_jmb_prod_idx);\n\t\t}\n\t} else if (work_mask) {\n\t\t/* rx_std_buffers[] and rx_jmb_buffers[] entries must be\n\t\t * updated before the producer indices can be updated.\n\t\t */\n\t\tsmp_wmb();\n\n\t\ttpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;\n\t\ttpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;\n\n\t\tif (tnapi != &tp->napi[1]) {\n\t\t\ttp->rx_refill = true;\n\t\t\tnapi_schedule(&tp->napi[1].napi);\n\t\t}\n\t}\n\n\treturn received;\n}",
        "static int test_syswide_multi_diff_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));": "static int test_syswide_multi_diff_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));\n\tchar *desc = \"Systemwide, Two events, diff addr, one is RO, other is WO\";\n\tint ret;\n\n\tret = perf_systemwide_event_open(fd1, HW_BREAKPOINT_W, (__u64)&a, (__u64)sizeof(a));\n\tif (ret) {\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tret = perf_systemwide_event_open(fd2, HW_BREAKPOINT_R, (__u64)&b, (__u64)sizeof(b));\n\tif (ret) {\n\t\tclose_fds(fd1, nprocs);\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\treset_fds(fd1, nprocs);\n\treset_fds(fd2, nprocs);\n\tenable_fds(fd1, nprocs);\n\tenable_fds(fd2, nprocs);\n\tmulti_dawr_workload();\n\tdisable_fds(fd1, nprocs);\n\tdisable_fds(fd2, nprocs);\n\n\tbreaks1 = read_fds(fd1, nprocs);\n\tbreaks2 = read_fds(fd2, nprocs);\n\n\tclose_fds(fd1, nprocs);\n\tclose_fds(fd2, nprocs);\n\n\tfree(fd1);\n\tfree(fd2);\n\n\tif (breaks1 != 1 || breaks2 != 1) {\n\t\tprintf(\"FAILED: %s: %lld != 1 || %lld != 1\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static void localtime_3(struct xtm *r, time64_t time)\n{\n\tunsigned int year, i, w = r->dse;\n\n\t/*": "static void localtime_3(struct xtm *r, time64_t time)\n{\n\tunsigned int year, i, w = r->dse;\n\n\t/*\n\t * In each year, a certain number of days-since-the-epoch have passed.\n\t * Find the year that is closest to said days.\n\t *\n\t * Consider, for example, w=21612 (2029-03-04). Loop will abort on\n\t * dse[i] <= w, which happens when dse[i] == 21550. This implies\n\t * year == 2009. w will then be 62.\n\t */\n\tfor (i = 0, year = DSE_FIRST; days_since_epoch[i] > w;\n\t    ++i, --year)\n\t\t/* just loop */;\n\n\tw -= days_since_epoch[i];\n\n\t/*\n\t * By now we have the current year, and the day of the year.\n\t * r->yearday = w;\n\t *\n\t * On to finding the month (like above). In each month, a certain\n\t * number of days-since-New Year have passed, and find the closest\n\t * one.\n\t *\n\t * Consider w=62 (in a non-leap year). Loop will abort on\n\t * dsy[i] < w, which happens when dsy[i] == 31+28 (i == 2).\n\t * Concludes i == 2, i.e. 3rd month => March.\n\t *\n\t * (A different approach to use would be to subtract a monthlength\n\t * from w repeatedly while counting.)\n\t */\n\tif (is_leap(year)) {\n\t\t/* use days_since_leapyear[] in a leap year */\n\t\tfor (i = ARRAY_SIZE(days_since_leapyear) - 1;\n\t\t    i > 0 && days_since_leapyear[i] > w; --i)\n\t\t\t/* just loop */;\n\t\tr->monthday = w - days_since_leapyear[i] + 1;\n\t} else {\n\t\tfor (i = ARRAY_SIZE(days_since_year) - 1;\n\t\t    i > 0 && days_since_year[i] > w; --i)\n\t\t\t/* just loop */;\n\t\tr->monthday = w - days_since_year[i] + 1;\n\t}\n\n\tr->month    = i + 1;\n}",
        "static void ae5_post_dsp_startup_data(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);": "static void ae5_post_dsp_startup_data(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);\n\n\tchipio_write_no_mutex(codec, 0x189000, 0x0001f101);\n\tchipio_write_no_mutex(codec, 0x189004, 0x0001f101);\n\tchipio_write_no_mutex(codec, 0x189024, 0x00014004);\n\tchipio_write_no_mutex(codec, 0x189028, 0x0002000f);\n\n\tca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);\n\tchipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);\n\tca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);\n\tca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);\n\tca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);\n\tca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);\n\tca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);\n\tca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);\n\tca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);\n\tca0113_mmio_gpio_set(codec, 0, true);\n\tca0113_mmio_gpio_set(codec, 1, true);\n\tca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);\n\n\tchipio_write_no_mutex(codec, 0x18b03c, 0x00000012);\n\n\tca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);\n\tca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);\n\n\tmutex_unlock(&spec->chipio_mutex);\n}",
        "static void reset_fim(struct imx_media_fim *fim, bool curval)\n{\n\tstruct v4l2_ctrl *icap_chan = fim->icap_ctrl[FIM_CL_ICAP_CHANNEL];\n\tstruct v4l2_ctrl *icap_edge = fim->icap_ctrl[FIM_CL_ICAP_EDGE];\n\tstruct v4l2_ctrl *en = fim->ctrl[FIM_CL_ENABLE];": "static void reset_fim(struct imx_media_fim *fim, bool curval)\n{\n\tstruct v4l2_ctrl *icap_chan = fim->icap_ctrl[FIM_CL_ICAP_CHANNEL];\n\tstruct v4l2_ctrl *icap_edge = fim->icap_ctrl[FIM_CL_ICAP_EDGE];\n\tstruct v4l2_ctrl *en = fim->ctrl[FIM_CL_ENABLE];\n\tstruct v4l2_ctrl *num = fim->ctrl[FIM_CL_NUM];\n\tstruct v4l2_ctrl *skip = fim->ctrl[FIM_CL_NUM_SKIP];\n\tstruct v4l2_ctrl *tol_min = fim->ctrl[FIM_CL_TOLERANCE_MIN];\n\tstruct v4l2_ctrl *tol_max = fim->ctrl[FIM_CL_TOLERANCE_MAX];\n\n\tif (curval) {\n\t\tfim->enabled = en->cur.val;\n\t\tfim->icap_flags = icap_edge->cur.val;\n\t\tfim->icap_channel = icap_chan->cur.val;\n\t\tfim->num_avg = num->cur.val;\n\t\tfim->num_skip = skip->cur.val;\n\t\tfim->tolerance_min = tol_min->cur.val;\n\t\tfim->tolerance_max = tol_max->cur.val;\n\t} else {\n\t\tfim->enabled = en->val;\n\t\tfim->icap_flags = icap_edge->val;\n\t\tfim->icap_channel = icap_chan->val;\n\t\tfim->num_avg = num->val;\n\t\tfim->num_skip = skip->val;\n\t\tfim->tolerance_min = tol_min->val;\n\t\tfim->tolerance_max = tol_max->val;\n\t}\n\n\t/* disable tolerance range if max <= min */\n\tif (fim->tolerance_max <= fim->tolerance_min)\n\t\tfim->tolerance_max = 0;\n\n\t/* num_skip must be >= 1 if input capture not used */\n\tif (!icap_enabled(fim))\n\t\tfim->num_skip = max_t(int, fim->num_skip, 1);\n\n\tfim->counter = -fim->num_skip;\n\tfim->sum = 0;\n}",
        "static int imgu_css_binary_setup(struct imgu_css *css, unsigned int pipe)\n{\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tstruct imgu_fw_info *bi = &css->fwp->binary_header[css_pipe->bindex];\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);": "static int imgu_css_binary_setup(struct imgu_css *css, unsigned int pipe)\n{\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tstruct imgu_fw_info *bi = &css->fwp->binary_header[css_pipe->bindex];\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);\n\tint i, j, size;\n\tstatic const int BYPC = 2;\t/* Bytes per component */\n\tunsigned int w, h;\n\n\t/* Allocate parameter memory blocks for this binary */\n\n\tfor (j = IMGU_ABI_PARAM_CLASS_CONFIG; j < IMGU_ABI_PARAM_CLASS_NUM; j++)\n\t\tfor (i = 0; i < IMGU_ABI_NUM_MEMORIES; i++) {\n\t\t\tif (imgu_css_dma_buffer_resize(\n\t\t\t    imgu,\n\t\t\t    &css_pipe->binary_params_cs[j - 1][i],\n\t\t\t    bi->info.isp.sp.mem_initializers.params[j][i].size))\n\t\t\t\tgoto out_of_memory;\n\t\t}\n\n\t/* Allocate internal frame buffers */\n\n\t/* Reference frames for DVS, FRAME_FORMAT_YUV420_16 */\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].bytesperpixel = BYPC;\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].width =\n\t\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_BDS].width;\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].height =\n\t\t\t\tALIGN(css_pipe->rect[IPU3_CSS_RECT_BDS].height,\n\t\t\t\t      IMGU_DVS_BLOCK_H) + 2 * IMGU_GDC_BUF_Y;\n\th = css_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].height;\n\tw = ALIGN(css_pipe->rect[IPU3_CSS_RECT_BDS].width,\n\t\t  2 * IPU3_UAPI_ISP_VEC_ELEMS) + 2 * IMGU_GDC_BUF_X;\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].bytesperline =\n\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].bytesperpixel * w;\n\tsize = w * h * BYPC + (w / 2) * (h / 2) * BYPC * 2;\n\tfor (i = 0; i < IPU3_CSS_AUX_FRAMES; i++)\n\t\tif (imgu_css_dma_buffer_resize(\n\t\t\timgu,\n\t\t\t&css_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].mem[i],\n\t\t\tsize))\n\t\t\tgoto out_of_memory;\n\n\t/* TNR frames for temporal noise reduction, FRAME_FORMAT_YUV_LINE */\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].bytesperpixel = 1;\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].width =\n\t\t\troundup(css_pipe->rect[IPU3_CSS_RECT_GDC].width,\n\t\t\t\tbi->info.isp.sp.block.block_width *\n\t\t\t\tIPU3_UAPI_ISP_VEC_ELEMS);\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].height =\n\t\t\troundup(css_pipe->rect[IPU3_CSS_RECT_GDC].height,\n\t\t\t\tbi->info.isp.sp.block.output_block_height);\n\n\tw = css_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].width;\n\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].bytesperline = w;\n\th = css_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].height;\n\tsize = w * ALIGN(h * 3 / 2 + 3, 2);\t/* +3 for vf_pp prefetch */\n\tfor (i = 0; i < IPU3_CSS_AUX_FRAMES; i++)\n\t\tif (imgu_css_dma_buffer_resize(\n\t\t\timgu,\n\t\t\t&css_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].mem[i],\n\t\t\tsize))\n\t\t\tgoto out_of_memory;\n\n\treturn 0;\n\nout_of_memory:\n\timgu_css_binary_cleanup(css, pipe);\n\treturn -ENOMEM;\n}",
        "static void lpss_iosf_enter_d3_state(void)\n{\n\tu32 value1 = 0;\n\tu32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;\n\tu32 value2 = LPSS_PMCSR_D3hot;": "static void lpss_iosf_enter_d3_state(void)\n{\n\tu32 value1 = 0;\n\tu32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;\n\tu32 value2 = LPSS_PMCSR_D3hot;\n\tu32 mask2 = LPSS_PMCSR_Dx_MASK;\n\t/*\n\t * PMC provides an information about actual status of the LPSS devices.\n\t * Here we read the values related to LPSS power island, i.e. LPSS\n\t * devices, excluding both LPSS DMA controllers, along with SCC domain.\n\t */\n\tu32 func_dis, d3_sts_0, pmc_status;\n\tint ret;\n\n\tret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);\n\tif (ret)\n\t\treturn;\n\n\tmutex_lock(&lpss_iosf_mutex);\n\n\tret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);\n\tif (ret)\n\t\tgoto exit;\n\n\t/*\n\t * Get the status of entire LPSS power island per device basis.\n\t * Shutdown both LPSS DMA controllers if and only if all other devices\n\t * are already in D3hot.\n\t */\n\tpmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;\n\tif (pmc_status)\n\t\tgoto exit;\n\n\tiosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,\n\t\t\tLPSS_IOSF_PMCSR, value2, mask2);\n\n\tiosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,\n\t\t\tLPSS_IOSF_PMCSR, value2, mask2);\n\n\tiosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,\n\t\t\tLPSS_IOSF_GPIODEF0, value1, mask1);\n\n\tlpss_iosf_d3_entered = true;\n\nexit:\n\tmutex_unlock(&lpss_iosf_mutex);\n}",
        "static int smc_llc_send_test_link(struct smc_link *link, u8 user_data[16])\n{\n\tstruct smc_llc_msg_test_link *testllc;\n\tstruct smc_wr_tx_pend_priv *pend;\n\tstruct smc_wr_buf *wr_buf;": "static int smc_llc_send_test_link(struct smc_link *link, u8 user_data[16])\n{\n\tstruct smc_llc_msg_test_link *testllc;\n\tstruct smc_wr_tx_pend_priv *pend;\n\tstruct smc_wr_buf *wr_buf;\n\tint rc;\n\n\tif (!smc_wr_tx_link_hold(link))\n\t\treturn -ENOLINK;\n\trc = smc_llc_add_pending_send(link, &wr_buf, &pend);\n\tif (rc)\n\t\tgoto put_out;\n\ttestllc = (struct smc_llc_msg_test_link *)wr_buf;\n\tmemset(testllc, 0, sizeof(*testllc));\n\ttestllc->hd.common.llc_type = SMC_LLC_TEST_LINK;\n\tsmc_llc_init_msg_hdr(&testllc->hd, link->lgr, sizeof(*testllc));\n\tmemcpy(testllc->user_data, user_data, sizeof(testllc->user_data));\n\t/* send llc message */\n\trc = smc_wr_tx_send(link, pend);\nput_out:\n\tsmc_wr_tx_link_put(link);\n\treturn rc;\n}",
        "static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)\n{\n\ttg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);\n\ttg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);\n\ttg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);": "static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)\n{\n\ttg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);\n\ttg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);\n\ttg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);\n\ttg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);\n\ttg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);\n\ttg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);\n\ttg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);\n\ttg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);\n\ttg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);\n\ttg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);\n\ttg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);\n\ttg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);\n\ttg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);\n\ttg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);\n\ttg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);\n\ttg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);\n\ttg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);\n\ttg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);\n\ttg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);\n\n\tif (tg3_flag(tp, SUPPORT_MSIX))\n\t\ttg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);\n\n\ttg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);\n\ttg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);\n\ttg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);\n\ttg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);\n\ttg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);\n\ttg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);\n\ttg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);\n\ttg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);\n\n\tif (!tg3_flag(tp, 5705_PLUS)) {\n\t\ttg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);\n\t\ttg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);\n\t\ttg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);\n\t}\n\n\ttg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);\n\ttg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);\n\ttg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);\n\ttg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);\n\ttg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);\n\n\tif (tg3_flag(tp, NVRAM))\n\t\ttg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);\n}",
        "static int __init test_h6(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 w[16] = {\n\t\t\t0x9b, 0x7d, 0x39, 0x0a, 0xa6, 0x10, 0x10, 0x34,\n\t\t\t0x05, 0xad, 0xc8, 0x57, 0xa3, 0x34, 0x02, 0xec };": "static int __init test_h6(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 w[16] = {\n\t\t\t0x9b, 0x7d, 0x39, 0x0a, 0xa6, 0x10, 0x10, 0x34,\n\t\t\t0x05, 0xad, 0xc8, 0x57, 0xa3, 0x34, 0x02, 0xec };\n\tconst u8 key_id[4] = { 0x72, 0x62, 0x65, 0x6c };\n\tconst u8 exp[16] = {\n\t\t\t0x99, 0x63, 0xb1, 0x80, 0xe2, 0xa9, 0xd3, 0xe8,\n\t\t\t0x1c, 0xc9, 0x6d, 0xe7, 0x02, 0xe1, 0x9a, 0x2d };\n\tu8 res[16];\n\tint err;\n\n\terr = smp_h6(tfm_cmac, w, key_id, res);\n\tif (err)\n\t\treturn err;\n\n\tif (crypto_memneq(res, exp, 16))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static int cpt_eng_sts_display(struct seq_file *filp, u8 eng_type)\n{\n\tstruct cpt_ctx *ctx = filp->private;\n\tu64 busy_sts = 0, free_sts = 0;\n\tu32 e_min = 0, e_max = 0, e, i;": "static int cpt_eng_sts_display(struct seq_file *filp, u8 eng_type)\n{\n\tstruct cpt_ctx *ctx = filp->private;\n\tu64 busy_sts = 0, free_sts = 0;\n\tu32 e_min = 0, e_max = 0, e, i;\n\tu16 max_ses, max_ies, max_aes;\n\tstruct rvu *rvu = ctx->rvu;\n\tint blkaddr = ctx->blkaddr;\n\tu64 reg;\n\n\treg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1);\n\tmax_ses = reg & 0xffff;\n\tmax_ies = (reg >> 16) & 0xffff;\n\tmax_aes = (reg >> 32) & 0xffff;\n\n\tswitch (eng_type) {\n\tcase CPT_AE_TYPE:\n\t\te_min = max_ses + max_ies;\n\t\te_max = max_ses + max_ies + max_aes;\n\t\tbreak;\n\tcase CPT_SE_TYPE:\n\t\te_min = 0;\n\t\te_max = max_ses;\n\t\tbreak;\n\tcase CPT_IE_TYPE:\n\t\te_min = max_ses;\n\t\te_max = max_ses + max_ies;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tfor (e = e_min, i = 0; e < e_max; e++, i++) {\n\t\treg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e));\n\t\tif (reg & 0x1)\n\t\t\tbusy_sts |= 1ULL << i;\n\n\t\tif (reg & 0x2)\n\t\t\tfree_sts |= 1ULL << i;\n\t}\n\tseq_printf(filp, \"FREE STS : 0x%016llx\\n\", free_sts);\n\tseq_printf(filp, \"BUSY STS : 0x%016llx\\n\", busy_sts);\n\n\treturn 0;\n}",
        "static int test_syswide_multi_same_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));": "static int test_syswide_multi_same_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));\n\tchar *desc = \"Systemwide, Two events, same addr, one is RO, other is WO\";\n\tint ret;\n\n\tret = perf_systemwide_event_open(fd1, HW_BREAKPOINT_W, (__u64)&a, (__u64)sizeof(a));\n\tif (ret) {\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tret = perf_systemwide_event_open(fd2, HW_BREAKPOINT_R, (__u64)&a, (__u64)sizeof(a));\n\tif (ret) {\n\t\tclose_fds(fd1, nprocs);\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\treset_fds(fd1, nprocs);\n\treset_fds(fd2, nprocs);\n\tenable_fds(fd1, nprocs);\n\tenable_fds(fd2, nprocs);\n\tmulti_dawr_workload();\n\tdisable_fds(fd1, nprocs);\n\tdisable_fds(fd2, nprocs);\n\n\tbreaks1 = read_fds(fd1, nprocs);\n\tbreaks2 = read_fds(fd2, nprocs);\n\n\tclose_fds(fd1, nprocs);\n\tclose_fds(fd2, nprocs);\n\n\tfree(fd1);\n\tfree(fd2);\n\n\tif (breaks1 != 1 || breaks2 != 1) {\n\t\tprintf(\"FAILED: %s: %lld != 1 || %lld != 1\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot)\n{\n\tint i = 0, hard_lp_ctr = 100000;\n\tu64 inprog, grp_ptr;\n\tu16 nq_ptr, dq_ptr;": "static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot)\n{\n\tint i = 0, hard_lp_ctr = 100000;\n\tu64 inprog, grp_ptr;\n\tu16 nq_ptr, dq_ptr;\n\n\t/* Disable instructions enqueuing */\n\trvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0);\n\n\t/* Disable executions in the LF's queue */\n\tinprog = rvu_read64(rvu, blkaddr,\n\t\t\t    CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));\n\tinprog &= ~BIT_ULL(16);\n\trvu_write64(rvu, blkaddr,\n\t\t    CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), inprog);\n\n\t/* Wait for CPT queue to become execution-quiescent */\n\tdo {\n\t\tinprog = rvu_read64(rvu, blkaddr,\n\t\t\t\t    CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));\n\t\tif (INPROG_GRB_PARTIAL(inprog)) {\n\t\t\ti = 0;\n\t\t\thard_lp_ctr--;\n\t\t} else {\n\t\t\ti++;\n\t\t}\n\n\t\tgrp_ptr = rvu_read64(rvu, blkaddr,\n\t\t\t\t     CPT_AF_BAR2_ALIASX(slot,\n\t\t\t\t\t\t\tCPT_LF_Q_GRP_PTR));\n\t\tnq_ptr = (grp_ptr >> 32) & 0x7FFF;\n\t\tdq_ptr = grp_ptr & 0x7FFF;\n\n\t} while (hard_lp_ctr && (i < 10) && (nq_ptr != dq_ptr));\n\n\tif (hard_lp_ctr == 0)\n\t\tdev_warn(rvu->dev, \"CPT FLR hits hard loop counter\\n\");\n\n\ti = 0;\n\thard_lp_ctr = 100000;\n\tdo {\n\t\tinprog = rvu_read64(rvu, blkaddr,\n\t\t\t\t    CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));\n\n\t\tif ((INPROG_INFLIGHT(inprog) == 0) &&\n\t\t    (INPROG_GWB(inprog) < 40) &&\n\t\t    ((INPROG_GRB(inprog) == 0) ||\n\t\t     (INPROG_GRB((inprog)) == 40))) {\n\t\t\ti++;\n\t\t} else {\n\t\t\ti = 0;\n\t\t\thard_lp_ctr--;\n\t\t}\n\t} while (hard_lp_ctr && (i < 10));\n\n\tif (hard_lp_ctr == 0)\n\t\tdev_warn(rvu->dev, \"CPT FLR hits hard loop counter\\n\");\n}",
        "static int san_events_register(struct platform_device *pdev)\n{\n\tstruct san_data *d = platform_get_drvdata(pdev);\n\tint status;\n": "static int san_events_register(struct platform_device *pdev)\n{\n\tstruct san_data *d = platform_get_drvdata(pdev);\n\tint status;\n\n\td->nf_bat.base.priority = 1;\n\td->nf_bat.base.fn = san_evt_bat_nf;\n\td->nf_bat.event.reg = SSAM_EVENT_REGISTRY_SAM;\n\td->nf_bat.event.id.target_category = SSAM_SSH_TC_BAT;\n\td->nf_bat.event.id.instance = 0;\n\td->nf_bat.event.mask = SSAM_EVENT_MASK_TARGET;\n\td->nf_bat.event.flags = SSAM_EVENT_SEQUENCED;\n\n\td->nf_tmp.base.priority = 1;\n\td->nf_tmp.base.fn = san_evt_tmp_nf;\n\td->nf_tmp.event.reg = SSAM_EVENT_REGISTRY_SAM;\n\td->nf_tmp.event.id.target_category = SSAM_SSH_TC_TMP;\n\td->nf_tmp.event.id.instance = 0;\n\td->nf_tmp.event.mask = SSAM_EVENT_MASK_TARGET;\n\td->nf_tmp.event.flags = SSAM_EVENT_SEQUENCED;\n\n\tstatus = ssam_notifier_register(d->ctrl, &d->nf_bat);\n\tif (status)\n\t\treturn status;\n\n\tstatus = ssam_notifier_register(d->ctrl, &d->nf_tmp);\n\tif (status)\n\t\tssam_notifier_unregister(d->ctrl, &d->nf_bat);\n\n\treturn status;\n}",
        "static void bpf_fill_ld_abs_vlan_push_pop(struct bpf_test *self)\n{\n\t/* test: {skb->data[0], vlan_push} x 51 + {skb->data[0], vlan_pop} x 51 */\n#define PUSH_CNT 51\n\t/* jump range is limited to 16 bit. PUSH_CNT of ld_abs needs room */": "static void bpf_fill_ld_abs_vlan_push_pop(struct bpf_test *self)\n{\n\t/* test: {skb->data[0], vlan_push} x 51 + {skb->data[0], vlan_pop} x 51 */\n#define PUSH_CNT 51\n\t/* jump range is limited to 16 bit. PUSH_CNT of ld_abs needs room */\n\tunsigned int len = (1 << 15) - PUSH_CNT * 2 * 5 * 6;\n\tstruct bpf_insn *insn = self->fill_insns;\n\tint i = 0, j, k = 0;\n\n\tinsn[i++] = BPF_MOV64_REG(BPF_REG_6, BPF_REG_1);\nloop:\n\tfor (j = 0; j < PUSH_CNT; j++) {\n\t\tinsn[i++] = BPF_LD_ABS(BPF_B, 0);\n\t\t/* jump to error label */\n\t\tinsn[i] = BPF_JMP32_IMM(BPF_JNE, BPF_REG_0, 0x34, len - i - 3);\n\t\ti++;\n\t\tinsn[i++] = BPF_MOV64_REG(BPF_REG_1, BPF_REG_6);\n\t\tinsn[i++] = BPF_MOV64_IMM(BPF_REG_2, 1);\n\t\tinsn[i++] = BPF_MOV64_IMM(BPF_REG_3, 2);\n\t\tinsn[i++] = BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0,\n\t\t\t\t\t BPF_FUNC_skb_vlan_push),\n\t\tinsn[i] = BPF_JMP_IMM(BPF_JNE, BPF_REG_0, 0, len - i - 3);\n\t\ti++;\n\t}\n\n\tfor (j = 0; j < PUSH_CNT; j++) {\n\t\tinsn[i++] = BPF_LD_ABS(BPF_B, 0);\n\t\tinsn[i] = BPF_JMP32_IMM(BPF_JNE, BPF_REG_0, 0x34, len - i - 3);\n\t\ti++;\n\t\tinsn[i++] = BPF_MOV64_REG(BPF_REG_1, BPF_REG_6);\n\t\tinsn[i++] = BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0,\n\t\t\t\t\t BPF_FUNC_skb_vlan_pop),\n\t\tinsn[i] = BPF_JMP_IMM(BPF_JNE, BPF_REG_0, 0, len - i - 3);\n\t\ti++;\n\t}\n\tif (++k < 5)\n\t\tgoto loop;\n\n\tfor (; i < len - 3; i++)\n\t\tinsn[i] = BPF_ALU64_IMM(BPF_MOV, BPF_REG_0, 0xbef);\n\tinsn[len - 3] = BPF_JMP_A(1);\n\t/* error label */\n\tinsn[len - 2] = BPF_MOV32_IMM(BPF_REG_0, 0);\n\tinsn[len - 1] = BPF_EXIT_INSN();\n\tself->prog_len = len;\n}",
        "static int smcr_tx_sndbuf_nonempty(struct smc_connection *conn)\n{\n\tstruct smc_cdc_producer_flags *pflags = &conn->local_tx_ctrl.prod_flags;\n\tstruct smc_link *link = conn->lnk;\n\tstruct smc_rdma_wr *wr_rdma_buf;": "static int smcr_tx_sndbuf_nonempty(struct smc_connection *conn)\n{\n\tstruct smc_cdc_producer_flags *pflags = &conn->local_tx_ctrl.prod_flags;\n\tstruct smc_link *link = conn->lnk;\n\tstruct smc_rdma_wr *wr_rdma_buf;\n\tstruct smc_cdc_tx_pend *pend;\n\tstruct smc_wr_buf *wr_buf;\n\tint rc;\n\n\tif (!link || !smc_wr_tx_link_hold(link))\n\t\treturn -ENOLINK;\n\trc = smc_cdc_get_free_slot(conn, link, &wr_buf, &wr_rdma_buf, &pend);\n\tif (rc < 0) {\n\t\tsmc_wr_tx_link_put(link);\n\t\tif (rc == -EBUSY) {\n\t\t\tstruct smc_sock *smc =\n\t\t\t\tcontainer_of(conn, struct smc_sock, conn);\n\n\t\t\tif (smc->sk.sk_err == ECONNABORTED)\n\t\t\t\treturn sock_error(&smc->sk);\n\t\t\tif (conn->killed)\n\t\t\t\treturn -EPIPE;\n\t\t\trc = 0;\n\t\t\tmod_delayed_work(conn->lgr->tx_wq, &conn->tx_work,\n\t\t\t\t\t SMC_TX_WORK_DELAY);\n\t\t}\n\t\treturn rc;\n\t}\n\n\tspin_lock_bh(&conn->send_lock);\n\tif (link != conn->lnk) {\n\t\t/* link of connection changed, tx_work will restart */\n\t\tsmc_wr_tx_put_slot(link,\n\t\t\t\t   (struct smc_wr_tx_pend_priv *)pend);\n\t\trc = -ENOLINK;\n\t\tgoto out_unlock;\n\t}\n\tif (!pflags->urg_data_present) {\n\t\trc = smc_tx_rdma_writes(conn, wr_rdma_buf);\n\t\tif (rc) {\n\t\t\tsmc_wr_tx_put_slot(link,\n\t\t\t\t\t   (struct smc_wr_tx_pend_priv *)pend);\n\t\t\tgoto out_unlock;\n\t\t}\n\t}\n\n\trc = smc_cdc_msg_send(conn, wr_buf, pend);\n\tif (!rc && pflags->urg_data_present) {\n\t\tpflags->urg_data_pending = 0;\n\t\tpflags->urg_data_present = 0;\n\t}\n\nout_unlock:\n\tspin_unlock_bh(&conn->send_lock);\n\tsmc_wr_tx_link_put(link);\n\treturn rc;\n}",
        "static bool __hci_update_interleaved_scan(struct hci_dev *hdev)\n{\n\t/* Do interleaved scan only if all of the following are true:\n\t * - There is at least one ADV monitor\n\t * - At least one pending LE connection or one device to be scanned for": "static bool __hci_update_interleaved_scan(struct hci_dev *hdev)\n{\n\t/* Do interleaved scan only if all of the following are true:\n\t * - There is at least one ADV monitor\n\t * - At least one pending LE connection or one device to be scanned for\n\t * - Monitor offloading is not supported\n\t * If so, we should alternate between allowlist scan and one without\n\t * any filters to save power.\n\t */\n\tbool use_interleaving = hci_is_adv_monitoring(hdev) &&\n\t\t\t\t!(list_empty(&hdev->pend_le_conns) &&\n\t\t\t\t  list_empty(&hdev->pend_le_reports)) &&\n\t\t\t\thci_get_adv_monitor_offload_ext(hdev) ==\n\t\t\t\t    HCI_ADV_MONITOR_EXT_NONE;\n\tbool is_interleaving = is_interleave_scanning(hdev);\n\n\tif (use_interleaving && !is_interleaving) {\n\t\tstart_interleave_scan(hdev);\n\t\tbt_dev_dbg(hdev, \"starting interleave scan\");\n\t\treturn true;\n\t}\n\n\tif (!use_interleaving && is_interleaving)\n\t\tcancel_interleave_scan(hdev);\n\n\treturn false;\n}",
        "static int yuvpp_start(struct ia_css_pipe *pipe)\n{\n\tint err = 0;\n\tenum sh_css_pipe_config_override copy_ovrd;\n\tenum ia_css_input_mode yuvpp_pipe_input_mode;": "static int yuvpp_start(struct ia_css_pipe *pipe)\n{\n\tint err = 0;\n\tenum sh_css_pipe_config_override copy_ovrd;\n\tenum ia_css_input_mode yuvpp_pipe_input_mode;\n\tunsigned int thread_id;\n\n\tIA_CSS_ENTER_PRIVATE(\"pipe = %p\", pipe);\n\tif ((!pipe) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(-EINVAL);\n\t\treturn -EINVAL;\n\t}\n\n\tyuvpp_pipe_input_mode = pipe->stream->config.mode;\n\n\tsh_css_metrics_start_frame();\n\n\t/* multi stream video needs mipi buffers */\n\n\terr = send_mipi_frames(pipe);\n\tif (err) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\treturn err;\n\t}\n\n\tia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);\n\tcopy_ovrd = 1 << thread_id;\n\n\tstart_pipe(pipe, copy_ovrd, yuvpp_pipe_input_mode);\n\n\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\treturn err;\n}",
        "static int set_vsb(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n\tstruct drx_common_attr *common_attr = NULL;": "static int set_vsb(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n\tstruct drx_common_attr *common_attr = NULL;\n\tstruct drxjscu_cmd cmd_scu;\n\tstruct drxj_data *ext_attr = NULL;\n\tu16 cmd_result = 0;\n\tu16 cmd_param = 0;\n\tstatic const u8 vsb_taps_re[] = {\n\t\tDRXJ_16TO8(-2),\t/* re0  */\n\t\tDRXJ_16TO8(4),\t/* re1  */\n\t\tDRXJ_16TO8(1),\t/* re2  */\n\t\tDRXJ_16TO8(-4),\t/* re3  */\n\t\tDRXJ_16TO8(1),\t/* re4  */\n\t\tDRXJ_16TO8(4),\t/* re5  */\n\t\tDRXJ_16TO8(-3),\t/* re6  */\n\t\tDRXJ_16TO8(-3),\t/* re7  */\n\t\tDRXJ_16TO8(6),\t/* re8  */\n\t\tDRXJ_16TO8(1),\t/* re9  */\n\t\tDRXJ_16TO8(-9),\t/* re10 */\n\t\tDRXJ_16TO8(3),\t/* re11 */\n\t\tDRXJ_16TO8(12),\t/* re12 */\n\t\tDRXJ_16TO8(-9),\t/* re13 */\n\t\tDRXJ_16TO8(-15),\t/* re14 */\n\t\tDRXJ_16TO8(17),\t/* re15 */\n\t\tDRXJ_16TO8(19),\t/* re16 */\n\t\tDRXJ_16TO8(-29),\t/* re17 */\n\t\tDRXJ_16TO8(-22),\t/* re18 */\n\t\tDRXJ_16TO8(45),\t/* re19 */\n\t\tDRXJ_16TO8(25),\t/* re20 */\n\t\tDRXJ_16TO8(-70),\t/* re21 */\n\t\tDRXJ_16TO8(-28),\t/* re22 */\n\t\tDRXJ_16TO8(111),\t/* re23 */\n\t\tDRXJ_16TO8(30),\t/* re24 */\n\t\tDRXJ_16TO8(-201),\t/* re25 */\n\t\tDRXJ_16TO8(-31),\t/* re26 */\n\t\tDRXJ_16TO8(629)\t/* re27 */\n\t};\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\tcommon_attr = (struct drx_common_attr *) demod->my_common_attr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\t/* stop all comm_exec */\n\trc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* reset demodulator */\n\tcmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_RESET;\n\tcmd_scu.parameter_len = 0;\n\tcmd_scu.result_len = 1;\n\tcmd_scu.parameter = NULL;\n\tcmd_scu.result = &cmd_result;\n\trc = scu_command(dev_addr, &cmd_scu);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\text_attr->iqm_rc_rate_ofs = 0x00AD0D79;\n\trc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* set higher threshold */\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* burst detection on   */\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* drop thresholds by 1 dB */\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* drop thresholds by 2 dB */\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* cma on               */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* GPIO               */\n\n\t/* Initialize the FEC Subsystem */\n\trc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t{\n\t\tu16 fec_oc_snc_mode = 0;\n\t\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\t/* output data even when not locked */\n\t\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\t/* set clip */\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t/* no transparent, no A&C framing; parity is set in mpegoutput */\n\t{\n\t\tu16 fec_oc_reg_mode = 0;\n\t\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* timeout counter for restarting */\n\trc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* bypass disabled */\n\t/* initialize RS packet error measurement parameters */\n\trc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* init measurement period of MER/SER */\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t/* B-Input to ADC, PGA+filter in standby */\n\tif (!ext_attr->has_lna) {\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\t/* turn on IQMAF. It has to be in front of setAgc**() */\n\trc = set_iqm_af(demod, true);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = adc_synchronization(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = init_agc(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t{\n\t\t/* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead\n\t\t   of only the gain */\n\t\tstruct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };\n\n\t\tvsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;\n\t\trc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\trc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Mpeg output has to be in front of FEC active */\n\trc = set_mpegtei_handling(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = bit_reverse_mpeg_output(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = set_mpeg_start_width(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t{\n\t\t/* TODO: move to set_standard after hardware reset value problem is solved */\n\t\t/* Configure initial MPEG output */\n\t\tstruct drx_cfg_mpeg_output cfg_mpeg_output;\n\n\t\tmemcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));\n\t\tcfg_mpeg_output.enable_mpeg_output = true;\n\n\t\trc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\t/* TBD: what parameters should be set */\n\tcmd_param = 0x00;\t/* Default mode AGC on, etc */\n\tcmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;\n\tcmd_scu.parameter_len = 1;\n\tcmd_scu.result_len = 1;\n\tcmd_scu.parameter = &cmd_param;\n\tcmd_scu.result = &cmd_result;\n\trc = scu_command(dev_addr, &cmd_scu);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* start demodulator */\n\tcmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_START;\n\tcmd_scu.parameter_len = 0;\n\tcmd_scu.result_len = 1;\n\tcmd_scu.parameter = NULL;\n\tcmd_scu.result = &cmd_result;\n\trc = scu_command(dev_addr, &cmd_scu);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int s2io_enable_msi_x(struct s2io_nic *nic)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tu64 rx_mat;\n\tu16 msi_control; /* Temp variable */": "static int s2io_enable_msi_x(struct s2io_nic *nic)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tu64 rx_mat;\n\tu16 msi_control; /* Temp variable */\n\tint ret, i, j, msix_indx = 1;\n\tint size;\n\tstruct stat_block *stats = nic->mac_control.stats_info;\n\tstruct swStat *swstats = &stats->sw_stat;\n\n\tsize = nic->num_entries * sizeof(struct msix_entry);\n\tnic->entries = kzalloc(size, GFP_KERNEL);\n\tif (!nic->entries) {\n\t\tDBG_PRINT(INFO_DBG, \"%s: Memory allocation failed\\n\",\n\t\t\t  __func__);\n\t\tswstats->mem_alloc_fail_cnt++;\n\t\treturn -ENOMEM;\n\t}\n\tswstats->mem_allocated += size;\n\n\tsize = nic->num_entries * sizeof(struct s2io_msix_entry);\n\tnic->s2io_entries = kzalloc(size, GFP_KERNEL);\n\tif (!nic->s2io_entries) {\n\t\tDBG_PRINT(INFO_DBG, \"%s: Memory allocation failed\\n\",\n\t\t\t  __func__);\n\t\tswstats->mem_alloc_fail_cnt++;\n\t\tkfree(nic->entries);\n\t\tswstats->mem_freed\n\t\t\t+= (nic->num_entries * sizeof(struct msix_entry));\n\t\treturn -ENOMEM;\n\t}\n\tswstats->mem_allocated += size;\n\n\tnic->entries[0].entry = 0;\n\tnic->s2io_entries[0].entry = 0;\n\tnic->s2io_entries[0].in_use = MSIX_FLG;\n\tnic->s2io_entries[0].type = MSIX_ALARM_TYPE;\n\tnic->s2io_entries[0].arg = &nic->mac_control.fifos;\n\n\tfor (i = 1; i < nic->num_entries; i++) {\n\t\tnic->entries[i].entry = ((i - 1) * 8) + 1;\n\t\tnic->s2io_entries[i].entry = ((i - 1) * 8) + 1;\n\t\tnic->s2io_entries[i].arg = NULL;\n\t\tnic->s2io_entries[i].in_use = 0;\n\t}\n\n\trx_mat = readq(&bar0->rx_mat);\n\tfor (j = 0; j < nic->config.rx_ring_num; j++) {\n\t\trx_mat |= RX_MAT_SET(j, msix_indx);\n\t\tnic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];\n\t\tnic->s2io_entries[j+1].type = MSIX_RING_TYPE;\n\t\tnic->s2io_entries[j+1].in_use = MSIX_FLG;\n\t\tmsix_indx += 8;\n\t}\n\twriteq(rx_mat, &bar0->rx_mat);\n\treadq(&bar0->rx_mat);\n\n\tret = pci_enable_msix_range(nic->pdev, nic->entries,\n\t\t\t\t    nic->num_entries, nic->num_entries);\n\t/* We fail init if error or we get less vectors than min required */\n\tif (ret < 0) {\n\t\tDBG_PRINT(ERR_DBG, \"Enabling MSI-X failed\\n\");\n\t\tkfree(nic->entries);\n\t\tswstats->mem_freed += nic->num_entries *\n\t\t\tsizeof(struct msix_entry);\n\t\tkfree(nic->s2io_entries);\n\t\tswstats->mem_freed += nic->num_entries *\n\t\t\tsizeof(struct s2io_msix_entry);\n\t\tnic->entries = NULL;\n\t\tnic->s2io_entries = NULL;\n\t\treturn -ENOMEM;\n\t}\n\n\t/*\n\t * To enable MSI-X, MSI also needs to be enabled, due to a bug\n\t * in the herc NIC. (Temp change, needs to be removed later)\n\t */\n\tpci_read_config_word(nic->pdev, 0x42, &msi_control);\n\tmsi_control |= 0x1; /* Enable MSI */\n\tpci_write_config_word(nic->pdev, 0x42, msi_control);\n\n\treturn 0;\n}",
        "static void sh_css_setup_queues(void)\n{\n\tconst struct ia_css_fw_info *fw;\n\tunsigned int HIVE_ADDR_host_sp_queues_initialized;\n": "static void sh_css_setup_queues(void)\n{\n\tconst struct ia_css_fw_info *fw;\n\tunsigned int HIVE_ADDR_host_sp_queues_initialized;\n\n\tsh_css_hmm_buffer_record_init();\n\n\tsh_css_event_init_irq_mask();\n\n\tfw = &sh_css_sp_fw;\n\tHIVE_ADDR_host_sp_queues_initialized =\n\t    fw->info.sp.host_sp_queues_initialized;\n\n\tia_css_bufq_init();\n\n\t/* set \"host_sp_queues_initialized\" to \"true\" */\n\tsp_dmem_store_uint32(SP0_ID,\n\t\t\t     (unsigned int)sp_address_of(host_sp_queues_initialized),\n\t\t\t     (uint32_t)(1));\n\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"sh_css_setup_queues() leave:\\n\");\n}",
        "static void do_test_pprint(int test_num)\n{\n\tconst struct btf_raw_test *test = &pprint_test_template[test_num];\n\tenum pprint_mapv_kind_t mapv_kind = test->mapv_kind;\n\tLIBBPF_OPTS(bpf_map_create_opts, opts);": "static void do_test_pprint(int test_num)\n{\n\tconst struct btf_raw_test *test = &pprint_test_template[test_num];\n\tenum pprint_mapv_kind_t mapv_kind = test->mapv_kind;\n\tLIBBPF_OPTS(bpf_map_create_opts, opts);\n\tbool ordered_map, lossless_map, percpu_map;\n\tint err, ret, num_cpus, rounded_value_size;\n\tunsigned int key, nr_read_elems;\n\tint map_fd = -1, btf_fd = -1;\n\tunsigned int raw_btf_size;\n\tchar expected_line[255];\n\tFILE *pin_file = NULL;\n\tchar pin_path[255];\n\tsize_t line_len = 0;\n\tchar *line = NULL;\n\tvoid *mapv = NULL;\n\tuint8_t *raw_btf;\n\tssize_t nread;\n\n\tif (!test__start_subtest(test->descr))\n\t\treturn;\n\n\traw_btf = btf_raw_create(&hdr_tmpl, test->raw_types,\n\t\t\t\t test->str_sec, test->str_sec_size,\n\t\t\t\t &raw_btf_size, NULL);\n\n\tif (!raw_btf)\n\t\treturn;\n\n\t*btf_log_buf = '\\0';\n\tbtf_fd = load_raw_btf(raw_btf, raw_btf_size);\n\tfree(raw_btf);\n\n\tif (CHECK(btf_fd < 0, \"errno:%d\\n\", errno)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\topts.btf_fd = btf_fd;\n\topts.btf_key_type_id = test->key_type_id;\n\topts.btf_value_type_id = test->value_type_id;\n\tmap_fd = bpf_map_create(test->map_type, test->map_name,\n\t\t\t\ttest->key_size, test->value_size, test->max_entries, &opts);\n\tif (CHECK(map_fd < 0, \"errno:%d\", errno)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tret = snprintf(pin_path, sizeof(pin_path), \"%s/%s\",\n\t\t       \"/sys/fs/bpf\", test->map_name);\n\n\tif (CHECK(ret == sizeof(pin_path), \"pin_path %s/%s is too long\",\n\t\t  \"/sys/fs/bpf\", test->map_name)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\terr = bpf_obj_pin(map_fd, pin_path);\n\tif (CHECK(err, \"bpf_obj_pin(%s): errno:%d.\", pin_path, errno))\n\t\tgoto done;\n\n\tpercpu_map = test->percpu_map;\n\tnum_cpus = percpu_map ? bpf_num_possible_cpus() : 1;\n\trounded_value_size = round_up(get_pprint_mapv_size(mapv_kind), 8);\n\tmapv = calloc(num_cpus, rounded_value_size);\n\tif (CHECK(!mapv, \"mapv allocation failure\")) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tfor (key = 0; key < test->max_entries; key++) {\n\t\tset_pprint_mapv(mapv_kind, mapv, key, num_cpus, rounded_value_size);\n\t\tbpf_map_update_elem(map_fd, &key, mapv, 0);\n\t}\n\n\tpin_file = fopen(pin_path, \"r\");\n\tif (CHECK(!pin_file, \"fopen(%s): errno:%d\", pin_path, errno)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\t/* Skip lines start with '#' */\n\twhile ((nread = getline(&line, &line_len, pin_file)) > 0 &&\n\t       *line == '#')\n\t\t;\n\n\tif (CHECK(nread <= 0, \"Unexpected EOF\")) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tnr_read_elems = 0;\n\tordered_map = test->ordered_map;\n\tlossless_map = test->lossless_map;\n\tdo {\n\t\tssize_t nexpected_line;\n\t\tunsigned int next_key;\n\t\tvoid *cmapv;\n\t\tint cpu;\n\n\t\tnext_key = ordered_map ? nr_read_elems : atoi(line);\n\t\tset_pprint_mapv(mapv_kind, mapv, next_key, num_cpus, rounded_value_size);\n\t\tcmapv = mapv;\n\n\t\tfor (cpu = 0; cpu < num_cpus; cpu++) {\n\t\t\tif (percpu_map) {\n\t\t\t\t/* for percpu map, the format looks like:\n\t\t\t\t * <key>: {\n\t\t\t\t *\tcpu0: <value_on_cpu0>\n\t\t\t\t *\tcpu1: <value_on_cpu1>\n\t\t\t\t *\t...\n\t\t\t\t *\tcpun: <value_on_cpun>\n\t\t\t\t * }\n\t\t\t\t *\n\t\t\t\t * let us verify the line containing the key here.\n\t\t\t\t */\n\t\t\t\tif (cpu == 0) {\n\t\t\t\t\tnexpected_line = snprintf(expected_line,\n\t\t\t\t\t\t\t\t  sizeof(expected_line),\n\t\t\t\t\t\t\t\t  \"%u: {\\n\",\n\t\t\t\t\t\t\t\t  next_key);\n\n\t\t\t\t\terr = check_line(expected_line, nexpected_line,\n\t\t\t\t\t\t\t sizeof(expected_line), line);\n\t\t\t\t\tif (err < 0)\n\t\t\t\t\t\tgoto done;\n\t\t\t\t}\n\n\t\t\t\t/* read value@cpu */\n\t\t\t\tnread = getline(&line, &line_len, pin_file);\n\t\t\t\tif (nread < 0)\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tnexpected_line = get_pprint_expected_line(mapv_kind, expected_line,\n\t\t\t\t\t\t\t\t  sizeof(expected_line),\n\t\t\t\t\t\t\t\t  percpu_map, next_key,\n\t\t\t\t\t\t\t\t  cpu, cmapv);\n\t\t\terr = check_line(expected_line, nexpected_line,\n\t\t\t\t\t sizeof(expected_line), line);\n\t\t\tif (err < 0)\n\t\t\t\tgoto done;\n\n\t\t\tcmapv = cmapv + rounded_value_size;\n\t\t}\n\n\t\tif (percpu_map) {\n\t\t\t/* skip the last bracket for the percpu map */\n\t\t\tnread = getline(&line, &line_len, pin_file);\n\t\t\tif (nread < 0)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tnread = getline(&line, &line_len, pin_file);\n\t} while (++nr_read_elems < test->max_entries && nread > 0);\n\n\tif (lossless_map &&\n\t    CHECK(nr_read_elems < test->max_entries,\n\t\t  \"Unexpected EOF. nr_read_elems:%u test->max_entries:%u\",\n\t\t  nr_read_elems, test->max_entries)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tif (CHECK(nread > 0, \"Unexpected extra pprint output: %s\", line)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\terr = 0;\n\ndone:\n\tif (mapv)\n\t\tfree(mapv);\n\tif (!err)\n\t\tfprintf(stderr, \"OK\");\n\tif (*btf_log_buf && (err || always_log))\n\t\tfprintf(stderr, \"\\n%s\", btf_log_buf);\n\tif (btf_fd >= 0)\n\t\tclose(btf_fd);\n\tif (map_fd >= 0)\n\t\tclose(map_fd);\n\tif (pin_file)\n\t\tfclose(pin_file);\n\tunlink(pin_path);\n\tfree(line);\n}",
        "static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)\n{\n\tconst struct pm8xxx_chan_info *ch;\n\tu16 read_1250v;\n\tu16 read_0625v;": "static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)\n{\n\tconst struct pm8xxx_chan_info *ch;\n\tu16 read_1250v;\n\tu16 read_0625v;\n\tu16 read_nomux_rsv5;\n\tu16 read_nomux_rsv4;\n\tint ret;\n\n\tadc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;\n\tadc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;\n\n\t/* Common reference channel calibration */\n\tch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);\n\tif (!ch)\n\t\treturn -ENODEV;\n\tret = pm8xxx_read_channel(adc, ch, &read_1250v);\n\tif (ret) {\n\t\tdev_err(adc->dev, \"could not read 1.25V reference channel\\n\");\n\t\treturn -ENODEV;\n\t}\n\tch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);\n\tif (!ch)\n\t\treturn -ENODEV;\n\tret = pm8xxx_read_channel(adc, ch, &read_0625v);\n\tif (ret) {\n\t\tdev_err(adc->dev, \"could not read 0.625V reference channel\\n\");\n\t\treturn -ENODEV;\n\t}\n\tif (read_1250v == read_0625v) {\n\t\tdev_err(adc->dev, \"read same ADC code for 1.25V and 0.625V\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tadc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v;\n\tadc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v;\n\n\tdev_info(adc->dev, \"absolute calibration dx = %d uV, dy = %d units\\n\",\n\t\t VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy);\n\n\t/* Ratiometric calibration */\n\tch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);\n\tif (!ch)\n\t\treturn -ENODEV;\n\tret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5,\n\t\t\t\t      &read_nomux_rsv5, true);\n\tif (ret) {\n\t\tdev_err(adc->dev, \"could not read MUXOFF reference channel\\n\");\n\t\treturn -ENODEV;\n\t}\n\tret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4,\n\t\t\t\t      &read_nomux_rsv4, true);\n\tif (ret) {\n\t\tdev_err(adc->dev, \"could not read MUXOFF reference channel\\n\");\n\t\treturn -ENODEV;\n\t}\n\tadc->graph[VADC_CALIB_RATIOMETRIC].dy =\n\t\tread_nomux_rsv5 - read_nomux_rsv4;\n\tadc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4;\n\n\tdev_info(adc->dev, \"ratiometric calibration dx = %d, dy = %d units\\n\",\n\t\t VADC_RATIOMETRIC_RANGE,\n\t\t adc->graph[VADC_CALIB_RATIOMETRIC].dy);\n\n\treturn 0;\n}",
        "static void stk1135_configure_mt9m112(struct gspca_dev *gspca_dev)\n{\n\tstatic const struct sensor_val cfg[] = {\n\t\t/* restart&reset, chip enable, reserved */\n\t\t{ 0x00d, 0x000b }, { 0x00d, 0x0008 }, { 0x035, 0x0022 },": "static void stk1135_configure_mt9m112(struct gspca_dev *gspca_dev)\n{\n\tstatic const struct sensor_val cfg[] = {\n\t\t/* restart&reset, chip enable, reserved */\n\t\t{ 0x00d, 0x000b }, { 0x00d, 0x0008 }, { 0x035, 0x0022 },\n\t\t/* mode ctl: AWB on, AE both, clip aper corr, defect corr, AE */\n\t\t{ 0x106, 0x700e },\n\n\t\t{ 0x2dd, 0x18e0 }, /* B-R thresholds, */\n\n\t\t/* AWB */\n\t\t{ 0x21f, 0x0180 }, /* Cb and Cr limits */\n\t\t{ 0x220, 0xc814 }, { 0x221, 0x8080 }, /* lum limits, RGB gain */\n\t\t{ 0x222, 0xa078 }, { 0x223, 0xa078 }, /* R, B limit */\n\t\t{ 0x224, 0x5f20 }, { 0x228, 0xea02 }, /* mtx adj lim, adv ctl */\n\t\t{ 0x229, 0x867a }, /* wide gates */\n\n\t\t/* Color correction */\n\t\t/* imager gains base, delta, delta signs */\n\t\t{ 0x25e, 0x594c }, { 0x25f, 0x4d51 }, { 0x260, 0x0002 },\n\t\t/* AWB adv ctl 2, gain offs */\n\t\t{ 0x2ef, 0x0008 }, { 0x2f2, 0x0000 },\n\t\t/* base matrix signs, scale K1-5, K6-9 */\n\t\t{ 0x202, 0x00ee }, { 0x203, 0x3923 }, { 0x204, 0x0724 },\n\t\t/* base matrix coef */\n\t\t{ 0x209, 0x00cd }, { 0x20a, 0x0093 }, { 0x20b, 0x0004 },/*K1-3*/\n\t\t{ 0x20c, 0x005c }, { 0x20d, 0x00d9 }, { 0x20e, 0x0053 },/*K4-6*/\n\t\t{ 0x20f, 0x0008 }, { 0x210, 0x0091 }, { 0x211, 0x00cf },/*K7-9*/\n\t\t{ 0x215, 0x0000 }, /* delta mtx signs */\n\t\t/* delta matrix coef */\n\t\t{ 0x216, 0x0000 }, { 0x217, 0x0000 }, { 0x218, 0x0000 },/*D1-3*/\n\t\t{ 0x219, 0x0000 }, { 0x21a, 0x0000 }, { 0x21b, 0x0000 },/*D4-6*/\n\t\t{ 0x21c, 0x0000 }, { 0x21d, 0x0000 }, { 0x21e, 0x0000 },/*D7-9*/\n\t\t/* enable & disable manual WB to apply color corr. settings */\n\t\t{ 0x106, 0xf00e }, { 0x106, 0x700e },\n\n\t\t/* Lens shading correction */\n\t\t{ 0x180, 0x0007 }, /* control */\n\t\t/* vertical knee 0, 2+1, 4+3 */\n\t\t{ 0x181, 0xde13 }, { 0x182, 0xebe2 }, { 0x183, 0x00f6 }, /* R */\n\t\t{ 0x184, 0xe114 }, { 0x185, 0xeadd }, { 0x186, 0xfdf6 }, /* G */\n\t\t{ 0x187, 0xe511 }, { 0x188, 0xede6 }, { 0x189, 0xfbf7 }, /* B */\n\t\t/* horizontal knee 0, 2+1, 4+3, 5 */\n\t\t{ 0x18a, 0xd613 }, { 0x18b, 0xedec }, /* R .. */\n\t\t{ 0x18c, 0xf9f2 }, { 0x18d, 0x0000 }, /* .. R */\n\t\t{ 0x18e, 0xd815 }, { 0x18f, 0xe9ea }, /* G .. */\n\t\t{ 0x190, 0xf9f1 }, { 0x191, 0x0002 }, /* .. G */\n\t\t{ 0x192, 0xde10 }, { 0x193, 0xefef }, /* B .. */\n\t\t{ 0x194, 0xfbf4 }, { 0x195, 0x0002 }, /* .. B */\n\t\t/* vertical knee 6+5, 8+7 */\n\t\t{ 0x1b6, 0x0e06 }, { 0x1b7, 0x2713 }, /* R */\n\t\t{ 0x1b8, 0x1106 }, { 0x1b9, 0x2713 }, /* G */\n\t\t{ 0x1ba, 0x0c03 }, { 0x1bb, 0x2a0f }, /* B */\n\t\t/* horizontal knee 7+6, 9+8, 10 */\n\t\t{ 0x1bc, 0x1208 }, { 0x1bd, 0x1a16 }, { 0x1be, 0x0022 }, /* R */\n\t\t{ 0x1bf, 0x150a }, { 0x1c0, 0x1c1a }, { 0x1c1, 0x002d }, /* G */\n\t\t{ 0x1c2, 0x1109 }, { 0x1c3, 0x1414 }, { 0x1c4, 0x002a }, /* B */\n\t\t{ 0x106, 0x740e }, /* enable lens shading correction */\n\n\t\t/* Gamma correction - context A */\n\t\t{ 0x153, 0x0b03 }, { 0x154, 0x4722 }, { 0x155, 0xac82 },\n\t\t{ 0x156, 0xdac7 }, { 0x157, 0xf5e9 }, { 0x158, 0xff00 },\n\t\t/* Gamma correction - context B */\n\t\t{ 0x1dc, 0x0b03 }, { 0x1dd, 0x4722 }, { 0x1de, 0xac82 },\n\t\t{ 0x1df, 0xdac7 }, { 0x1e0, 0xf5e9 }, { 0x1e1, 0xff00 },\n\n\t\t/* output format: RGB, invert output pixclock, output bayer */\n\t\t{ 0x13a, 0x4300 }, { 0x19b, 0x4300 }, /* for context A, B */\n\t\t{ 0x108, 0x0180 }, /* format control - enable bayer row flip */\n\n\t\t{ 0x22f, 0xd100 }, { 0x29c, 0xd100 }, /* AE A, B */\n\n\t\t/* default prg conf, prg ctl - by 0x2d2, prg advance - PA1 */\n\t\t{ 0x2d2, 0x0000 }, { 0x2cc, 0x0004 }, { 0x2cb, 0x0001 },\n\n\t\t{ 0x22e, 0x0c3c }, { 0x267, 0x1010 }, /* AE tgt ctl, gain lim */\n\n\t\t/* PLL */\n\t\t{ 0x065, 0xa000 }, /* clk ctl - enable PLL (clear bit 14) */\n\t\t{ 0x066, 0x2003 }, { 0x067, 0x0501 }, /* PLL M=128, N=3, P=1 */\n\t\t{ 0x065, 0x2000 }, /* disable PLL bypass (clear bit 15) */\n\n\t\t{ 0x005, 0x01b8 }, { 0x007, 0x00d8 }, /* horiz blanking B, A */\n\n\t\t/* AE line size, shutter delay limit */\n\t\t{ 0x239, 0x06c0 }, { 0x23b, 0x040e }, /* for context A */\n\t\t{ 0x23a, 0x06c0 }, { 0x23c, 0x0564 }, /* for context B */\n\t\t/* shutter width basis 60Hz, 50Hz */\n\t\t{ 0x257, 0x0208 }, { 0x258, 0x0271 }, /* for context A */\n\t\t{ 0x259, 0x0209 }, { 0x25a, 0x0271 }, /* for context B */\n\n\t\t{ 0x25c, 0x120d }, { 0x25d, 0x1712 }, /* flicker 60Hz, 50Hz */\n\t\t{ 0x264, 0x5e1c }, /* reserved */\n\t\t/* flicker, AE gain limits, gain zone limits */\n\t\t{ 0x25b, 0x0003 }, { 0x236, 0x7810 }, { 0x237, 0x8304 },\n\n\t\t{ 0x008, 0x0021 }, /* vert blanking A */\n\t};\n\tint i;\n\tu16 width, height;\n\n\tfor (i = 0; i < ARRAY_SIZE(cfg); i++)\n\t\tsensor_write(gspca_dev, cfg[i].reg, cfg[i].val);\n\n\t/* set output size */\n\twidth = gspca_dev->pixfmt.width;\n\theight = gspca_dev->pixfmt.height;\n\tif (width <= 640 && height <= 512) { /* context A (half readout speed)*/\n\t\tsensor_write(gspca_dev, 0x1a7, width);\n\t\tsensor_write(gspca_dev, 0x1aa, height);\n\t\t/* set read mode context A */\n\t\tsensor_write(gspca_dev, 0x0c8, 0x0000);\n\t\t/* set resize, read mode, vblank, hblank context A */\n\t\tsensor_write(gspca_dev, 0x2c8, 0x0000);\n\t} else { /* context B (full readout speed) */\n\t\tsensor_write(gspca_dev, 0x1a1, width);\n\t\tsensor_write(gspca_dev, 0x1a4, height);\n\t\t/* set read mode context B */\n\t\tsensor_write(gspca_dev, 0x0c8, 0x0008);\n\t\t/* set resize, read mode, vblank, hblank context B */\n\t\tsensor_write(gspca_dev, 0x2c8, 0x040b);\n\t}\n}",
        "static int patch_alc850(struct snd_ac97 *ac97)\n{\n\tac97->build_ops = &patch_alc850_ops;\n\n\tac97->spec.dev_flags = 0; /* for IEC958 playback route - ALC655 compatible */": "static int patch_alc850(struct snd_ac97 *ac97)\n{\n\tac97->build_ops = &patch_alc850_ops;\n\n\tac97->spec.dev_flags = 0; /* for IEC958 playback route - ALC655 compatible */\n\tac97->flags |= AC97_HAS_8CH;\n\n\t/* assume only page 0 for writing cache */\n\tsnd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_VENDOR);\n\n\t/* adjust default values */\n\t/* set default: spdif-in enabled,\n\t   spdif-in monitor off, spdif-in PCM off\n\t   center on mic off, surround on line-in off\n\t   duplicate front off\n\t   NB default bit 10=0 = Aux is Capture, not Back Surround\n\t*/\n\tsnd_ac97_write_cache(ac97, AC97_ALC650_MULTICH, 1<<15);\n\t/* SURR_OUT: on, Surr 1kOhm: on, Surr Amp: off, Front 1kOhm: off\n\t * Front Amp: on, Vref: enable, Center 1kOhm: on, Mix: on\n\t */\n\tsnd_ac97_write_cache(ac97, 0x7a, (1<<1)|(1<<4)|(0<<5)|(1<<6)|\n\t\t\t     (1<<7)|(0<<12)|(1<<13)|(0<<14));\n\t/* detection UIO2,3: all path floating, UIO3: MIC, Vref2: disable,\n\t * UIO1: FRONT, Vref3: disable, UIO3: LINE, Front-Mic: mute\n\t */\n\tsnd_ac97_write_cache(ac97, 0x76, (0<<0)|(0<<2)|(1<<4)|(1<<7)|(2<<8)|\n\t\t\t     (1<<11)|(0<<12)|(1<<15));\n\n\t/* full DAC volume */\n\tsnd_ac97_write_cache(ac97, AC97_ALC650_SURR_DAC_VOL, 0x0808);\n\tsnd_ac97_write_cache(ac97, AC97_ALC650_LFE_DAC_VOL, 0x0808);\n\treturn 0;\n}",
        "static int __init stnic_probe(void)\n{\n  struct net_device *dev;\n  struct ei_device *ei_local;\n  int err;": "static int __init stnic_probe(void)\n{\n  struct net_device *dev;\n  struct ei_device *ei_local;\n  int err;\n\n  /* If we are not running on a SolutionEngine, give up now */\n  if (! MACH_SE)\n    return -ENODEV;\n\n  /* New style probing API */\n  dev = alloc_ei_netdev();\n  if (!dev)\n\treturn -ENOMEM;\n\n#ifdef CONFIG_SH_STANDARD_BIOS\n  sh_bios_get_node_addr (stnic_eadr);\n#endif\n  eth_hw_addr_set(dev, stnic_eadr);\n\n  /* Set the base address to point to the NIC, not the \"real\" base! */\n  dev->base_addr = 0x1000;\n  dev->irq = IRQ_STNIC;\n  dev->netdev_ops = &ei_netdev_ops;\n\n  /* Snarf the interrupt now.  There's no point in waiting since we cannot\n     share and the board will usually be enabled. */\n  err = request_irq (dev->irq, ei_interrupt, 0, DRV_NAME, dev);\n  if (err)  {\n\tnetdev_emerg(dev, \" unable to get IRQ %d.\\n\", dev->irq);\n\tfree_netdev(dev);\n\treturn err;\n  }\n\n  ei_status.name = dev->name;\n  ei_status.word16 = 1;\n#ifdef __LITTLE_ENDIAN__\n  ei_status.bigendian = 0;\n#else\n  ei_status.bigendian = 1;\n#endif\n  ei_status.tx_start_page = START_PG;\n  ei_status.rx_start_page = START_PG + TX_PAGES;\n  ei_status.stop_page = STOP_PG;\n\n  ei_status.reset_8390 = &stnic_reset;\n  ei_status.get_8390_hdr = &stnic_get_hdr;\n  ei_status.block_input = &stnic_block_input;\n  ei_status.block_output = &stnic_block_output;\n\n  stnic_init (dev);\n  ei_local = netdev_priv(dev);\n  ei_local->msg_enable = stnic_msg_enable;\n\n  err = register_netdev(dev);\n  if (err) {\n    free_irq(dev->irq, dev);\n    free_netdev(dev);\n    return err;\n  }\n  stnic_dev = dev;\n\n  netdev_info(dev, \"NS ST-NIC 83902A\\n\");\n\n  return 0;\n}",
        "static void tr_static_init(void)\n{\n    static int static_init_done;\n    int n;        /* iterates over tree elements */\n    int bits;     /* bit counter */": "static void tr_static_init(void)\n{\n    static int static_init_done;\n    int n;        /* iterates over tree elements */\n    int bits;     /* bit counter */\n    int length;   /* length value */\n    int code;     /* code value */\n    int dist;     /* distance index */\n    ush bl_count[MAX_BITS+1];\n    /* number of codes at each bit length for an optimal tree */\n\n    if (static_init_done) return;\n\n    /* Initialize the mapping length (0..255) -> length code (0..28) */\n    length = 0;\n    for (code = 0; code < LENGTH_CODES-1; code++) {\n        base_length[code] = length;\n        for (n = 0; n < (1<<extra_lbits[code]); n++) {\n            length_code[length++] = (uch)code;\n        }\n    }\n    Assert (length == 256, \"tr_static_init: length != 256\");\n    /* Note that the length 255 (match length 258) can be represented\n     * in two different ways: code 284 + 5 bits or code 285, so we\n     * overwrite length_code[255] to use the best encoding:\n     */\n    length_code[length-1] = (uch)code;\n\n    /* Initialize the mapping dist (0..32K) -> dist code (0..29) */\n    dist = 0;\n    for (code = 0 ; code < 16; code++) {\n        base_dist[code] = dist;\n        for (n = 0; n < (1<<extra_dbits[code]); n++) {\n            dist_code[dist++] = (uch)code;\n        }\n    }\n    Assert (dist == 256, \"tr_static_init: dist != 256\");\n    dist >>= 7; /* from now on, all distances are divided by 128 */\n    for ( ; code < D_CODES; code++) {\n        base_dist[code] = dist << 7;\n        for (n = 0; n < (1<<(extra_dbits[code]-7)); n++) {\n            dist_code[256 + dist++] = (uch)code;\n        }\n    }\n    Assert (dist == 256, \"tr_static_init: 256+dist != 512\");\n\n    /* Construct the codes of the static literal tree */\n    for (bits = 0; bits <= MAX_BITS; bits++) bl_count[bits] = 0;\n    n = 0;\n    while (n <= 143) static_ltree[n++].Len = 8, bl_count[8]++;\n    while (n <= 255) static_ltree[n++].Len = 9, bl_count[9]++;\n    while (n <= 279) static_ltree[n++].Len = 7, bl_count[7]++;\n    while (n <= 287) static_ltree[n++].Len = 8, bl_count[8]++;\n    /* Codes 286 and 287 do not exist, but we must include them in the\n     * tree construction to get a canonical Huffman tree (longest code\n     * all ones)\n     */\n    gen_codes((ct_data *)static_ltree, L_CODES+1, bl_count);\n\n    /* The static distance tree is trivial: */\n    for (n = 0; n < D_CODES; n++) {\n        static_dtree[n].Len = 5;\n        static_dtree[n].Code = bitrev32((u32)n) >> (32 - 5);\n    }\n    static_init_done = 1;\n}",
        "static bool hci_update_interleaved_scan_sync(struct hci_dev *hdev)\n{\n\t/* Do interleaved scan only if all of the following are true:\n\t * - There is at least one ADV monitor\n\t * - At least one pending LE connection or one device to be scanned for": "static bool hci_update_interleaved_scan_sync(struct hci_dev *hdev)\n{\n\t/* Do interleaved scan only if all of the following are true:\n\t * - There is at least one ADV monitor\n\t * - At least one pending LE connection or one device to be scanned for\n\t * - Monitor offloading is not supported\n\t * If so, we should alternate between allowlist scan and one without\n\t * any filters to save power.\n\t */\n\tbool use_interleaving = hci_is_adv_monitoring(hdev) &&\n\t\t\t\t!(list_empty(&hdev->pend_le_conns) &&\n\t\t\t\t  list_empty(&hdev->pend_le_reports)) &&\n\t\t\t\thci_get_adv_monitor_offload_ext(hdev) ==\n\t\t\t\t    HCI_ADV_MONITOR_EXT_NONE;\n\tbool is_interleaving = is_interleave_scanning(hdev);\n\n\tif (use_interleaving && !is_interleaving) {\n\t\thci_start_interleave_scan(hdev);\n\t\tbt_dev_dbg(hdev, \"starting interleave scan\");\n\t\treturn true;\n\t}\n\n\tif (!use_interleaving && is_interleaving)\n\t\tcancel_interleave_scan(hdev);\n\n\treturn false;\n}",
        "static void cpu_up_down_serialize_trainwrecks(bool tasks_frozen)\n{\n\t/*\n\t * cpusets delegate hotplug operations to a worker to \"solve\" the\n\t * lock order problems. Wait for the worker, but only if tasks are": "static void cpu_up_down_serialize_trainwrecks(bool tasks_frozen)\n{\n\t/*\n\t * cpusets delegate hotplug operations to a worker to \"solve\" the\n\t * lock order problems. Wait for the worker, but only if tasks are\n\t * _not_ frozen (suspend, hibernate) as that would wait forever.\n\t *\n\t * The wait is required because otherwise the hotplug operation\n\t * returns with inconsistent state, which could even be observed in\n\t * user space when a new CPU is brought up. The CPU plug uevent\n\t * would be delivered and user space reacting on it would fail to\n\t * move tasks to the newly plugged CPU up to the point where the\n\t * work has finished because up to that point the newly plugged CPU\n\t * is not assignable in cpusets/cgroups. On unplug that's not\n\t * necessarily a visible issue, but it is still inconsistent state,\n\t * which is the real problem which needs to be \"fixed\". This can't\n\t * prevent the transient state between scheduling the work and\n\t * returning from waiting for it.\n\t */\n\tif (!tasks_frozen)\n\t\tcpuset_wait_for_hotplug();\n}",
        "static void die_usage(void)\n{\n\tfprintf(stderr, \"Usage: mptcp_connect [-6] [-c cmsg] [-i file] [-I num] [-j] [-l] \"\n\t\t\"[-m mode] [-M mark] [-o option] [-p port] [-P mode] [-j] [-l] [-r num] \"\n\t\t\"[-s MPTCP|TCP] [-S num] [-r num] [-t num] [-T num] [-u] [-w sec] connect_address\\n\");": "static void die_usage(void)\n{\n\tfprintf(stderr, \"Usage: mptcp_connect [-6] [-c cmsg] [-i file] [-I num] [-j] [-l] \"\n\t\t\"[-m mode] [-M mark] [-o option] [-p port] [-P mode] [-j] [-l] [-r num] \"\n\t\t\"[-s MPTCP|TCP] [-S num] [-r num] [-t num] [-T num] [-u] [-w sec] connect_address\\n\");\n\tfprintf(stderr, \"\\t-6 use ipv6\\n\");\n\tfprintf(stderr, \"\\t-c cmsg -- test cmsg type <cmsg>\\n\");\n\tfprintf(stderr, \"\\t-i file -- read the data to send from the given file instead of stdin\");\n\tfprintf(stderr, \"\\t-I num -- repeat the transfer 'num' times. In listen mode accepts num \"\n\t\t\"incoming connections, in client mode, disconnect and reconnect to the server\\n\");\n\tfprintf(stderr, \"\\t-j     -- add additional sleep at connection start and tear down \"\n\t\t\"-- for MPJ tests\\n\");\n\tfprintf(stderr, \"\\t-l     -- listens mode, accepts incoming connection\\n\");\n\tfprintf(stderr, \"\\t-m [poll|mmap|sendfile] -- use poll(default)/mmap+write/sendfile\\n\");\n\tfprintf(stderr, \"\\t-M mark -- set socket packet mark\\n\");\n\tfprintf(stderr, \"\\t-o option -- test sockopt <option>\\n\");\n\tfprintf(stderr, \"\\t-p num -- use port num\\n\");\n\tfprintf(stderr,\n\t\t\"\\t-P [saveWithPeek|saveAfterPeek] -- save data with/after MSG_PEEK form tcp socket\\n\");\n\tfprintf(stderr, \"\\t-t num -- set poll timeout to num\\n\");\n\tfprintf(stderr, \"\\t-T num -- set expected runtime to num ms\\n\");\n\tfprintf(stderr, \"\\t-r num -- enable slow mode, limiting each write to num bytes \"\n\t\t\"-- for remove addr tests\\n\");\n\tfprintf(stderr, \"\\t-R num -- set SO_RCVBUF to num\\n\");\n\tfprintf(stderr, \"\\t-s [MPTCP|TCP] -- use mptcp(default) or tcp sockets\\n\");\n\tfprintf(stderr, \"\\t-S num -- set SO_SNDBUF to num\\n\");\n\tfprintf(stderr, \"\\t-w num -- wait num sec before closing the socket\\n\");\n\texit(1);\n}",
        "static int __smc_connect(struct smc_sock *smc)\n{\n\tu8 version = smc_ism_is_v2_capable() ? SMC_V2 : SMC_V1;\n\tstruct smc_clc_msg_accept_confirm_v2 *aclc2;\n\tstruct smc_clc_msg_accept_confirm *aclc;": "static int __smc_connect(struct smc_sock *smc)\n{\n\tu8 version = smc_ism_is_v2_capable() ? SMC_V2 : SMC_V1;\n\tstruct smc_clc_msg_accept_confirm_v2 *aclc2;\n\tstruct smc_clc_msg_accept_confirm *aclc;\n\tstruct smc_init_info *ini = NULL;\n\tu8 *buf = NULL;\n\tint rc = 0;\n\n\tif (smc->use_fallback)\n\t\treturn smc_connect_fallback(smc, smc->fallback_rsn);\n\n\t/* if peer has not signalled SMC-capability, fall back */\n\tif (!tcp_sk(smc->clcsock->sk)->syn_smc)\n\t\treturn smc_connect_fallback(smc, SMC_CLC_DECL_PEERNOSMC);\n\n\t/* IPSec connections opt out of SMC optimizations */\n\tif (using_ipsec(smc))\n\t\treturn smc_connect_decline_fallback(smc, SMC_CLC_DECL_IPSEC,\n\t\t\t\t\t\t    version);\n\n\tini = kzalloc(sizeof(*ini), GFP_KERNEL);\n\tif (!ini)\n\t\treturn smc_connect_decline_fallback(smc, SMC_CLC_DECL_MEM,\n\t\t\t\t\t\t    version);\n\n\tini->smcd_version = SMC_V1 | SMC_V2;\n\tini->smcr_version = SMC_V1 | SMC_V2;\n\tini->smc_type_v1 = SMC_TYPE_B;\n\tini->smc_type_v2 = SMC_TYPE_B;\n\n\t/* get vlan id from IP device */\n\tif (smc_vlan_by_tcpsk(smc->clcsock, ini)) {\n\t\tini->smcd_version &= ~SMC_V1;\n\t\tini->smcr_version = 0;\n\t\tini->smc_type_v1 = SMC_TYPE_N;\n\t\tif (!ini->smcd_version) {\n\t\t\trc = SMC_CLC_DECL_GETVLANERR;\n\t\t\tgoto fallback;\n\t\t}\n\t}\n\n\trc = smc_find_proposal_devices(smc, ini);\n\tif (rc)\n\t\tgoto fallback;\n\n\tbuf = kzalloc(SMC_CLC_MAX_ACCEPT_LEN, GFP_KERNEL);\n\tif (!buf) {\n\t\trc = SMC_CLC_DECL_MEM;\n\t\tgoto fallback;\n\t}\n\taclc2 = (struct smc_clc_msg_accept_confirm_v2 *)buf;\n\taclc = (struct smc_clc_msg_accept_confirm *)aclc2;\n\n\t/* perform CLC handshake */\n\trc = smc_connect_clc(smc, aclc2, ini);\n\tif (rc) {\n\t\t/* -EAGAIN on timeout, see tcp_recvmsg() */\n\t\tif (rc == -EAGAIN) {\n\t\t\trc = -ETIMEDOUT;\n\t\t\tsmc->sk.sk_err = ETIMEDOUT;\n\t\t}\n\t\tgoto vlan_cleanup;\n\t}\n\n\t/* check if smc modes and versions of CLC proposal and accept match */\n\trc = smc_connect_check_aclc(ini, aclc);\n\tversion = aclc->hdr.version == SMC_V1 ? SMC_V1 : SMC_V2;\n\tif (rc)\n\t\tgoto vlan_cleanup;\n\n\t/* depending on previous steps, connect using rdma or ism */\n\tif (aclc->hdr.typev1 == SMC_TYPE_R) {\n\t\tini->smcr_version = version;\n\t\trc = smc_connect_rdma(smc, aclc, ini);\n\t} else if (aclc->hdr.typev1 == SMC_TYPE_D) {\n\t\tini->smcd_version = version;\n\t\trc = smc_connect_ism(smc, aclc, ini);\n\t}\n\tif (rc)\n\t\tgoto vlan_cleanup;\n\n\tSMC_STAT_CLNT_SUCC_INC(sock_net(smc->clcsock->sk), aclc);\n\tsmc_connect_ism_vlan_cleanup(smc, ini);\n\tkfree(buf);\n\tkfree(ini);\n\treturn 0;\n\nvlan_cleanup:\n\tsmc_connect_ism_vlan_cleanup(smc, ini);\n\tkfree(buf);\nfallback:\n\tkfree(ini);\n\treturn smc_connect_decline_fallback(smc, rc, version);\n}",
        "static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)\n{\n\tint cnt;\n\n\t/*": "static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)\n{\n\tint cnt;\n\n\t/*\n\t *  Set the frame timer to reflect the number of cycles per frame.\n\t */\n\tsnd_cs46xx_poke(chip, BA1_FRMT, 0xadf);\n\t/*\n\t *  Turn on the run, run at frame, and DMA enable bits in the local copy of\n\t *  the SP control register.\n\t */\n\tsnd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);\n\t/*\n\t *  Wait until the run at frame bit resets itself in the SP control\n\t *  register.\n\t */\n\tfor (cnt = 0; cnt < 25; cnt++) {\n\t\tudelay(50);\n\t\tif (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))\n\t\t\tbreak;\n\t}\n\n\tif (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)\n\t\tdev_err(chip->card->dev, \"SPCR_RUNFR never reset\\n\");\n}",
        "static void fastopen_estab(void)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n": "static void fastopen_estab(void)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n\n\thdr_stg_map_fd = bpf_map__fd(skel->maps.hdr_stg_map);\n\tlport_linum_map_fd = bpf_map__fd(skel->maps.lport_linum_map);\n\n\texp_passive_estab_in.flags = OPTION_F_RAND | OPTION_F_MAX_DELACK_MS;\n\texp_passive_estab_in.rand = 0xfa;\n\texp_passive_estab_in.max_delack_ms = 11;\n\n\texp_active_estab_in.flags = OPTION_F_RAND | OPTION_F_MAX_DELACK_MS;\n\texp_active_estab_in.rand = 0xce;\n\texp_active_estab_in.max_delack_ms = 22;\n\n\texp_passive_hdr_stg.fastopen = true;\n\n\tprepare_out();\n\n\t/* Allow fastopen without fastopen cookie */\n\tif (write_sysctl(\"/proc/sys/net/ipv4/tcp_fastopen\", \"1543\"))\n\t\treturn;\n\n\tlink = bpf_program__attach_cgroup(skel->progs.estab, cg_fd);\n\tif (!ASSERT_OK_PTR(link, \"attach_cgroup(estab)\"))\n\t\treturn;\n\n\tif (sk_fds_connect(&sk_fds, true)) {\n\t\tbpf_link__destroy(link);\n\t\treturn;\n\t}\n\n\tcheck_hdr_and_close_fds(&sk_fds);\n\tbpf_link__destroy(link);\n}",
        "static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)\n{\n\tint rc;\n\ts32 freq = 0;\t/* KHz */\n\tstruct i2c_device_addr *dev_addr = NULL;": "static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)\n{\n\tint rc;\n\ts32 freq = 0;\t/* KHz */\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxj_data *ext_attr = NULL;\n\tu16 i = 0;\n\tbool mirror_freq_spect_oob = false;\n\tu16 trk_filter_value = 0;\n\tstruct drxjscu_cmd scu_cmd;\n\tu16 set_param_parameters[3];\n\tu16 cmd_result[2] = { 0, 0 };\n\ts16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {\n\t\tIMPULSE_COSINE_ALPHA_0_3,\t/* Target Mode 0 */\n\t\tIMPULSE_COSINE_ALPHA_0_3,\t/* Target Mode 1 */\n\t\tIMPULSE_COSINE_ALPHA_0_5,\t/* Target Mode 2 */\n\t\tIMPULSE_COSINE_ALPHA_RO_0_5\t/* Target Mode 3 */\n\t};\n\tu8 mode_val[4] = { 2, 2, 0, 1 };\n\tu8 pfi_coeffs[4][6] = {\n\t\t{DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)},\t/* TARGET_MODE = 0:     PFI_A = -23/32; PFI_B = -54/32;  PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */\n\t\t{DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)},\t/* TARGET_MODE = 1:     PFI_A = -16/32; PFI_B = -40/32;  PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */\n\t\t{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)},\t/* TARGET_MODE = 2, 3:  PFI_A = -20/32; PFI_B = -49/32;  PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */\n\t\t{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}\t/* TARGET_MODE = 2, 3:  PFI_A = -20/32; PFI_B = -49/32;  PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */\n\t};\n\tu16 mode_index;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\tmirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;\n\n\t/* Check parameters */\n\tif (oob_param == NULL) {\n\t\t/* power off oob module  */\n\t\tscu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB\n\t\t    | SCU_RAM_COMMAND_CMD_DEMOD_STOP;\n\t\tscu_cmd.parameter_len = 0;\n\t\tscu_cmd.result_len = 1;\n\t\tscu_cmd.result = cmd_result;\n\t\trc = scu_command(dev_addr, &scu_cmd);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = set_orx_nsu_aox(demod, false);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\n\t\text_attr->oob_power_on = false;\n\t\treturn 0;\n\t}\n\n\tfreq = oob_param->frequency;\n\tif ((freq < 70000) || (freq > 130000))\n\t\treturn -EIO;\n\tfreq = (freq - 50000) / 50;\n\n\t{\n\t\tu16 index = 0;\n\t\tu16 remainder = 0;\n\t\tu16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;\n\n\t\tindex = (u16) ((freq - 400) / 200);\n\t\tremainder = (u16) ((freq - 400) % 200);\n\t\ttrk_filter_value =\n\t\t    trk_filtercfg[index] - (trk_filtercfg[index] -\n\t\t\t\t\t   trk_filtercfg[index +\n\t\t\t\t\t\t\t1]) / 10 * remainder /\n\t\t    20;\n\t}\n\n   /********/\n\t/* Stop  */\n   /********/\n\trc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tscu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_STOP;\n\tscu_cmd.parameter_len = 0;\n\tscu_cmd.result_len = 1;\n\tscu_cmd.result = cmd_result;\n\trc = scu_command(dev_addr, &scu_cmd);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n   /********/\n\t/* Reset */\n   /********/\n\tscu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_RESET;\n\tscu_cmd.parameter_len = 0;\n\tscu_cmd.result_len = 1;\n\tscu_cmd.result = cmd_result;\n\trc = scu_command(dev_addr, &scu_cmd);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n   /**********/\n\t/* SET_ENV */\n   /**********/\n\t/* set frequency, spectrum inversion and data rate */\n\tscu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;\n\tscu_cmd.parameter_len = 3;\n\t/* 1-data rate;2-frequency */\n\tswitch (oob_param->standard) {\n\tcase DRX_OOB_MODE_A:\n\t\tif (\n\t\t\t   /* signal is transmitted inverted */\n\t\t\t   ((oob_param->spectrum_inverted == true) &&\n\t\t\t    /* and tuner is not mirroring the signal */\n\t\t\t    (!mirror_freq_spect_oob)) |\n\t\t\t   /* or */\n\t\t\t   /* signal is transmitted noninverted */\n\t\t\t   ((oob_param->spectrum_inverted == false) &&\n\t\t\t    /* and tuner is mirroring the signal */\n\t\t\t    (mirror_freq_spect_oob))\n\t\t    )\n\t\t\tset_param_parameters[0] =\n\t\t\t    SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;\n\t\telse\n\t\t\tset_param_parameters[0] =\n\t\t\t    SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;\n\t\tbreak;\n\tcase DRX_OOB_MODE_B_GRADE_A:\n\t\tif (\n\t\t\t   /* signal is transmitted inverted */\n\t\t\t   ((oob_param->spectrum_inverted == true) &&\n\t\t\t    /* and tuner is not mirroring the signal */\n\t\t\t    (!mirror_freq_spect_oob)) |\n\t\t\t   /* or */\n\t\t\t   /* signal is transmitted noninverted */\n\t\t\t   ((oob_param->spectrum_inverted == false) &&\n\t\t\t    /* and tuner is mirroring the signal */\n\t\t\t    (mirror_freq_spect_oob))\n\t\t    )\n\t\t\tset_param_parameters[0] =\n\t\t\t    SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;\n\t\telse\n\t\t\tset_param_parameters[0] =\n\t\t\t    SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;\n\t\tbreak;\n\tcase DRX_OOB_MODE_B_GRADE_B:\n\tdefault:\n\t\tif (\n\t\t\t   /* signal is transmitted inverted */\n\t\t\t   ((oob_param->spectrum_inverted == true) &&\n\t\t\t    /* and tuner is not mirroring the signal */\n\t\t\t    (!mirror_freq_spect_oob)) |\n\t\t\t   /* or */\n\t\t\t   /* signal is transmitted noninverted */\n\t\t\t   ((oob_param->spectrum_inverted == false) &&\n\t\t\t    /* and tuner is mirroring the signal */\n\t\t\t    (mirror_freq_spect_oob))\n\t\t    )\n\t\t\tset_param_parameters[0] =\n\t\t\t    SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;\n\t\telse\n\t\t\tset_param_parameters[0] =\n\t\t\t    SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;\n\t\tbreak;\n\t}\n\tset_param_parameters[1] = (u16) (freq & 0xFFFF);\n\tset_param_parameters[2] = trk_filter_value;\n\tscu_cmd.parameter = set_param_parameters;\n\tscu_cmd.result_len = 1;\n\tscu_cmd.result = cmd_result;\n\tmode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];\n\trc = scu_command(dev_addr, &scu_cmd);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/*  Write magic word to enable pdr reg write  */\n\trc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/*  Write magic word to disable pdr reg write */\n\n\trc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* ddc */\n\trc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* nsu */\n\trc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* initialization for target mode */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Reset bits for timing and freq. recovery */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* TIM_LOCK = {300,      -2048, 8, -8, 0, 1<<4}; */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* EQU_LOCK = {20,      -2048, 8, -8, 0, 1<<5}; */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* PRE-Filter coefficients (PFI) */\n\trc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* NYQUIST-Filter coefficients (NYQ) */\n\tfor (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {\n\t\trc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t/********/\n\t/* Start */\n\t/********/\n\tscu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB\n\t    | SCU_RAM_COMMAND_CMD_DEMOD_START;\n\tscu_cmd.parameter_len = 0;\n\tscu_cmd.result_len = 1;\n\tscu_cmd.result = cmd_result;\n\trc = scu_command(dev_addr, &scu_cmd);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = set_orx_nsu_aox(demod, true);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\text_attr->oob_power_on = true;\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int madera_fllhj_apply(struct madera_fll *fll, int fin)\n{\n\tstruct madera *madera = fll->madera;\n\tint refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd;\n\tbool frac = false;": "static int madera_fllhj_apply(struct madera_fll *fll, int fin)\n{\n\tstruct madera *madera = fll->madera;\n\tint refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd;\n\tbool frac = false;\n\tunsigned int fll_n, min_n, max_n, ratio, theta, lambda;\n\tunsigned int gains, val, num;\n\n\tmadera_fll_dbg(fll, \"fin=%d, fout=%d\\n\", fin, fll->fout);\n\n\tfor (refdiv = 0; refdiv < 4; refdiv++)\n\t\tif ((fin / (1 << refdiv)) <= MADERA_FLLHJ_MAX_THRESH)\n\t\t\tbreak;\n\n\tfref = fin / (1 << refdiv);\n\n\t/* Use simple heuristic approach to find a configuration that\n\t * should work for most input clocks.\n\t */\n\tfast_clk = 0;\n\tfout = fll->fout;\n\tfrac = fout % fref;\n\n\tif (fref < MADERA_FLLHJ_LOW_THRESH) {\n\t\tlockdet_thr = 2;\n\t\tgains = MADERA_FLLHJ_LOW_GAINS;\n\t\tif (frac)\n\t\t\tfbdiv = 256;\n\t\telse\n\t\t\tfbdiv = 4;\n\t} else if (fref < MADERA_FLLHJ_MID_THRESH) {\n\t\tlockdet_thr = 8;\n\t\tgains = MADERA_FLLHJ_MID_GAINS;\n\t\tfbdiv = 1;\n\t} else {\n\t\tlockdet_thr = 8;\n\t\tgains = MADERA_FLLHJ_HIGH_GAINS;\n\t\tfbdiv = 1;\n\t\t/* For high speed input clocks, enable 300MHz fast oscillator\n\t\t * when we're in fractional divider mode.\n\t\t */\n\t\tif (frac) {\n\t\t\tfast_clk = 0x3;\n\t\t\tfout = fll->fout * 6;\n\t\t}\n\t}\n\t/* Use high performance mode for fractional configurations. */\n\tif (frac) {\n\t\thp = 0x3;\n\t\tmin_n = MADERA_FLLHJ_FRAC_MIN_N;\n\t\tmax_n = MADERA_FLLHJ_FRAC_MAX_N;\n\t} else {\n\t\thp = 0x0;\n\t\tmin_n = MADERA_FLLHJ_INT_MIN_N;\n\t\tmax_n = MADERA_FLLHJ_INT_MAX_N;\n\t}\n\n\tratio = fout / fref;\n\n\tmadera_fll_dbg(fll, \"refdiv=%d, fref=%d, frac:%d\\n\",\n\t\t       refdiv, fref, frac);\n\n\twhile (ratio / fbdiv < min_n) {\n\t\tfbdiv /= 2;\n\t\tif (fbdiv < 1) {\n\t\t\tmadera_fll_err(fll, \"FBDIV (%d) must be >= 1\\n\", fbdiv);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\twhile (frac && (ratio / fbdiv > max_n)) {\n\t\tfbdiv *= 2;\n\t\tif (fbdiv >= 1024) {\n\t\t\tmadera_fll_err(fll, \"FBDIV (%u) >= 1024\\n\", fbdiv);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tmadera_fll_dbg(fll, \"lockdet=%d, hp=0x%x, fbdiv:%d\\n\",\n\t\t       lockdet_thr, hp, fbdiv);\n\n\t/* Calculate N.K values */\n\tfllgcd = gcd(fout, fbdiv * fref);\n\tnum = fout / fllgcd;\n\tlambda = (fref * fbdiv) / fllgcd;\n\tfll_n = num / lambda;\n\ttheta = num % lambda;\n\n\tmadera_fll_dbg(fll, \"fll_n=%d, gcd=%d, theta=%d, lambda=%d\\n\",\n\t\t       fll_n, fllgcd, theta, lambda);\n\n\t/* Some sanity checks before any registers are written. */\n\tif (fll_n < min_n || fll_n > max_n) {\n\t\tmadera_fll_err(fll, \"N not in valid %s mode range %d-%d: %d\\n\",\n\t\t\t       frac ? \"fractional\" : \"integer\", min_n, max_n,\n\t\t\t       fll_n);\n\t\treturn -EINVAL;\n\t}\n\tif (fbdiv < 1 || (frac && fbdiv >= 1024) || (!frac && fbdiv >= 256)) {\n\t\tmadera_fll_err(fll, \"Invalid fbdiv for %s mode (%u)\\n\",\n\t\t\t       frac ? \"fractional\" : \"integer\", fbdiv);\n\t\treturn -EINVAL;\n\t}\n\n\t/* clear the ctrl_upd bit to guarantee we write to it later. */\n\tregmap_write(madera->regmap,\n\t\t     fll->base + MADERA_FLL_CONTROL_2_OFFS,\n\t\t     fll_n << MADERA_FLL1_N_SHIFT);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_3_OFFS,\n\t\t\t   MADERA_FLL1_THETA_MASK,\n\t\t\t   theta << MADERA_FLL1_THETA_SHIFT);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_4_OFFS,\n\t\t\t   MADERA_FLL1_LAMBDA_MASK,\n\t\t\t   lambda << MADERA_FLL1_LAMBDA_SHIFT);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_5_OFFS,\n\t\t\t   MADERA_FLL1_FB_DIV_MASK,\n\t\t\t   fbdiv << MADERA_FLL1_FB_DIV_SHIFT);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_6_OFFS,\n\t\t\t   MADERA_FLL1_REFCLK_DIV_MASK,\n\t\t\t   refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_GAIN_OFFS,\n\t\t\t   0xffff,\n\t\t\t   gains);\n\tval = hp << MADERA_FLL1_HP_SHIFT;\n\tval |= 1 << MADERA_FLL1_PHASEDET_ENA_SHIFT;\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_10_OFFS,\n\t\t\t   MADERA_FLL1_HP_MASK | MADERA_FLL1_PHASEDET_ENA_MASK,\n\t\t\t   val);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_11_OFFS,\n\t\t\t   MADERA_FLL1_LOCKDET_THR_MASK,\n\t\t\t   lockdet_thr << MADERA_FLL1_LOCKDET_THR_SHIFT);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL1_DIGITAL_TEST_1_OFFS,\n\t\t\t   MADERA_FLL1_SYNC_EFS_ENA_MASK |\n\t\t\t   MADERA_FLL1_CLK_VCO_FAST_SRC_MASK,\n\t\t\t   fast_clk);\n\n\treturn 0;\n}",
        "static void syncookie_estab(void)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n": "static void syncookie_estab(void)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n\n\thdr_stg_map_fd = bpf_map__fd(skel->maps.hdr_stg_map);\n\tlport_linum_map_fd = bpf_map__fd(skel->maps.lport_linum_map);\n\n\texp_passive_estab_in.flags = OPTION_F_RAND | OPTION_F_MAX_DELACK_MS;\n\texp_passive_estab_in.rand = 0xfa;\n\texp_passive_estab_in.max_delack_ms = 11;\n\n\texp_active_estab_in.flags = OPTION_F_RAND | OPTION_F_MAX_DELACK_MS |\n\t\t\t\t\tOPTION_F_RESEND;\n\texp_active_estab_in.rand = 0xce;\n\texp_active_estab_in.max_delack_ms = 22;\n\n\texp_passive_hdr_stg.syncookie = true;\n\texp_active_hdr_stg.resend_syn = true,\n\n\tprepare_out();\n\n\t/* Clear the RESEND to ensure the bpf prog can learn\n\t * want_cookie and set the RESEND by itself.\n\t */\n\tskel->bss->passive_synack_out.flags &= ~OPTION_F_RESEND;\n\n\t/* Enforce syncookie mode */\n\tif (write_sysctl(\"/proc/sys/net/ipv4/tcp_syncookies\", \"2\"))\n\t\treturn;\n\n\tlink = bpf_program__attach_cgroup(skel->progs.estab, cg_fd);\n\tif (!ASSERT_OK_PTR(link, \"attach_cgroup(estab)\"))\n\t\treturn;\n\n\tif (sk_fds_connect(&sk_fds, false)) {\n\t\tbpf_link__destroy(link);\n\t\treturn;\n\t}\n\n\tcheck_hdr_and_close_fds(&sk_fds);\n\tbpf_link__destroy(link);\n}",
        "static unsigned int drbd_al_extents_max(struct drbd_backing_dev *bdev)\n{\n\t/* This is limited by 16 bit \"slot\" numbers,\n\t * and by available on-disk context storage.\n\t *": "static unsigned int drbd_al_extents_max(struct drbd_backing_dev *bdev)\n{\n\t/* This is limited by 16 bit \"slot\" numbers,\n\t * and by available on-disk context storage.\n\t *\n\t * Also (u16)~0 is special (denotes a \"free\" extent).\n\t *\n\t * One transaction occupies one 4kB on-disk block,\n\t * we have n such blocks in the on disk ring buffer,\n\t * the \"current\" transaction may fail (n-1),\n\t * and there is 919 slot numbers context information per transaction.\n\t *\n\t * 72 transaction blocks amounts to more than 2**16 context slots,\n\t * so cap there first.\n\t */\n\tconst unsigned int max_al_nr = DRBD_AL_EXTENTS_MAX;\n\tconst unsigned int sufficient_on_disk =\n\t\t(max_al_nr + AL_CONTEXT_PER_TRANSACTION -1)\n\t\t/AL_CONTEXT_PER_TRANSACTION;\n\n\tunsigned int al_size_4k = bdev->md.al_size_4k;\n\n\tif (al_size_4k > sufficient_on_disk)\n\t\treturn max_al_nr;\n\n\treturn (al_size_4k - 1) * AL_CONTEXT_PER_TRANSACTION;\n}",
        "static void help(char *name)\n{\n\tputs(\"\");\n\tprintf(\"usage: %s [-h] [-m vm_mode] [-u uffd_mode] [-d uffd_delay_usec]\\n\"\n\t       \"          [-b memory] [-s type] [-v vcpus] [-o]\\n\", name);": "static void help(char *name)\n{\n\tputs(\"\");\n\tprintf(\"usage: %s [-h] [-m vm_mode] [-u uffd_mode] [-d uffd_delay_usec]\\n\"\n\t       \"          [-b memory] [-s type] [-v vcpus] [-o]\\n\", name);\n\tguest_modes_help();\n\tprintf(\" -u: use userfaultfd to handle vCPU page faults. Mode is a\\n\"\n\t       \"     UFFD registration mode: 'MISSING' or 'MINOR'.\\n\");\n\tprintf(\" -d: add a delay in usec to the User Fault\\n\"\n\t       \"     FD handler to simulate demand paging\\n\"\n\t       \"     overheads. Ignored without -u.\\n\");\n\tprintf(\" -b: specify the size of the memory region which should be\\n\"\n\t       \"     demand paged by each vCPU. e.g. 10M or 3G.\\n\"\n\t       \"     Default: 1G\\n\");\n\tbacking_src_help(\"-s\");\n\tprintf(\" -v: specify the number of vCPUs to run.\\n\");\n\tprintf(\" -o: Overlap guest memory accesses instead of partitioning\\n\"\n\t       \"     them into a separate region of memory for each vCPU.\\n\");\n\tputs(\"\");\n\texit(0);\n}",
        "static void config_segment(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)\n{\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tconst struct v4l2_vp9_segmentation *seg;\n\ts16 feat_val;": "static void config_segment(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)\n{\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tconst struct v4l2_vp9_segmentation *seg;\n\ts16 feat_val;\n\tunsigned char feat_id;\n\tunsigned int segid;\n\tbool segment_enabled, absolute, update_data;\n\n\tstatic const struct hantro_reg seg_regs[8][V4L2_VP9_SEG_LVL_MAX] = {\n\t\t{ vp9_quant_seg0, vp9_filt_level_seg0, vp9_refpic_seg0, vp9_skip_seg0 },\n\t\t{ vp9_quant_seg1, vp9_filt_level_seg1, vp9_refpic_seg1, vp9_skip_seg1 },\n\t\t{ vp9_quant_seg2, vp9_filt_level_seg2, vp9_refpic_seg2, vp9_skip_seg2 },\n\t\t{ vp9_quant_seg3, vp9_filt_level_seg3, vp9_refpic_seg3, vp9_skip_seg3 },\n\t\t{ vp9_quant_seg4, vp9_filt_level_seg4, vp9_refpic_seg4, vp9_skip_seg4 },\n\t\t{ vp9_quant_seg5, vp9_filt_level_seg5, vp9_refpic_seg5, vp9_skip_seg5 },\n\t\t{ vp9_quant_seg6, vp9_filt_level_seg6, vp9_refpic_seg6, vp9_skip_seg6 },\n\t\t{ vp9_quant_seg7, vp9_filt_level_seg7, vp9_refpic_seg7, vp9_skip_seg7 },\n\t};\n\n\tsegment_enabled = !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED);\n\thantro_reg_write(ctx->dev, &vp9_segment_e, segment_enabled);\n\thantro_reg_write(ctx->dev, &vp9_segment_upd_e,\n\t\t\t !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP));\n\thantro_reg_write(ctx->dev, &vp9_segment_temp_upd_e,\n\t\t\t !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE));\n\n\tseg = &dec_params->seg;\n\tabsolute = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE);\n\tupdate_data = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA);\n\n\tfor (segid = 0; segid < 8; ++segid) {\n\t\t/* Quantizer segment feature */\n\t\tfeat_id = V4L2_VP9_SEG_LVL_ALT_Q;\n\t\tfeat_val = dec_params->quant.base_q_idx;\n\t\tif (segment_enabled) {\n\t\t\tif (update_data)\n\t\t\t\tupdate_feat_and_flag(vp9_ctx, seg, feat_id, segid);\n\t\t\tif (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid))\n\t\t\t\tfeat_val = feat_val_clip3(feat_val,\n\t\t\t\t\t\t\t  vp9_ctx->feature_data[segid][feat_id],\n\t\t\t\t\t\t\t  absolute, 255);\n\t\t}\n\t\thantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val);\n\n\t\t/* Loop filter segment feature */\n\t\tfeat_id = V4L2_VP9_SEG_LVL_ALT_L;\n\t\tfeat_val = dec_params->lf.level;\n\t\tif (segment_enabled) {\n\t\t\tif (update_data)\n\t\t\t\tupdate_feat_and_flag(vp9_ctx, seg, feat_id, segid);\n\t\t\tif (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid))\n\t\t\t\tfeat_val = feat_val_clip3(feat_val,\n\t\t\t\t\t\t\t  vp9_ctx->feature_data[segid][feat_id],\n\t\t\t\t\t\t\t  absolute, 63);\n\t\t}\n\t\thantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val);\n\n\t\t/* Reference frame segment feature */\n\t\tfeat_id = V4L2_VP9_SEG_LVL_REF_FRAME;\n\t\tfeat_val = 0;\n\t\tif (segment_enabled) {\n\t\t\tif (update_data)\n\t\t\t\tupdate_feat_and_flag(vp9_ctx, seg, feat_id, segid);\n\t\t\tif (!(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) &&\n\t\t\t    v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid))\n\t\t\t\tfeat_val = vp9_ctx->feature_data[segid][feat_id] + 1;\n\t\t}\n\t\thantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val);\n\n\t\t/* Skip segment feature */\n\t\tfeat_id = V4L2_VP9_SEG_LVL_SKIP;\n\t\tfeat_val = 0;\n\t\tif (segment_enabled) {\n\t\t\tif (update_data)\n\t\t\t\tupdate_feat_and_flag(vp9_ctx, seg, feat_id, segid);\n\t\t\tfeat_val = v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled,\n\t\t\t\t\t\t\t     feat_id, segid) ? 1 : 0;\n\t\t}\n\t\thantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val);\n\t}\n}",
        "static int drxj_open(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxj_data *ext_attr = NULL;\n\tstruct drx_common_attr *common_attr = NULL;": "static int drxj_open(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxj_data *ext_attr = NULL;\n\tstruct drx_common_attr *common_attr = NULL;\n\tu32 driver_version = 0;\n\tstruct drxu_code_info ucode_info;\n\tstruct drx_cfg_mpeg_output cfg_mpeg_output;\n\tint rc;\n\tenum drx_power_mode power_mode = DRX_POWER_UP;\n\n\tif ((demod == NULL) ||\n\t    (demod->my_common_attr == NULL) ||\n\t    (demod->my_ext_attr == NULL) ||\n\t    (demod->my_i2c_dev_addr == NULL) ||\n\t    (demod->my_common_attr->is_opened)) {\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check arguments */\n\tif (demod->my_ext_attr == NULL)\n\t\treturn -EINVAL;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\tcommon_attr = (struct drx_common_attr *) demod->my_common_attr;\n\n\trc = ctrl_power_mode(demod, &power_mode);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (power_mode != DRX_POWER_UP) {\n\t\trc = -EINVAL;\n\t\tpr_err(\"failed to powerup device\\n\");\n\t\tgoto rw_error;\n\t}\n\n\t/* has to be in front of setIqmAf and setOrxNsuAox */\n\trc = get_device_capabilities(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/*\n\t * Soft reset of sys- and osc-clockdomain\n\t *\n\t * HACK: On windows, it writes a 0x07 here, instead of just 0x03.\n\t * As we didn't load the firmware here yet, we should do the same.\n\t * Btw, this is coherent with DRX-K, where we send reset codes\n\t * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.\n\t */\n\trc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tmsleep(1);\n\n\t/* TODO first make sure that everything keeps working before enabling this */\n\t/* PowerDownAnalogBlocks() */\n\trc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = set_iqm_af(demod, false);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = set_orx_nsu_aox(demod, false);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = init_hi(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* disable mpegoutput pins */\n\tmemcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));\n\tcfg_mpeg_output.enable_mpeg_output = false;\n\n\trc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t/* Stop AUD Inform SetAudio it will need to do all setting */\n\trc = power_down_aud(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t/* Stop SCU */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Upload microcode */\n\tif (common_attr->microcode_file != NULL) {\n\t\t/* Dirty trick to use common ucode upload & verify,\n\t\t   pretend device is already open */\n\t\tcommon_attr->is_opened = true;\n\t\tucode_info.mc_file = common_attr->microcode_file;\n\n\t\tif (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {\n\t\t\tpr_err(\"Should powerup before loading the firmware.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\trc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d while uploading the firmware\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tif (common_attr->verify_microcode == true) {\n\t\t\trc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);\n\t\t\tif (rc != 0) {\n\t\t\t\tpr_err(\"error %d while verifying the firmware\\n\",\n\t\t\t\t       rc);\n\t\t\t\tgoto rw_error;\n\t\t\t}\n\t\t}\n\t\tcommon_attr->is_opened = false;\n\t}\n\n\t/* Run SCU for a little while to initialize microcode version numbers */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Initialize scan timeout */\n\tcommon_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;\n\tcommon_attr->scan_desired_lock = DRX_LOCKED;\n\n\tdrxj_reset_mode(ext_attr);\n\text_attr->standard = DRX_STANDARD_UNKNOWN;\n\n\trc = smart_ant_init(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Stamp driver version number in SCU data RAM in BCD code\n\t   Done to enable field application engineers to retrieve drxdriver version\n\t   via I2C from SCU RAM\n\t */\n\tdriver_version = (VERSION_MAJOR / 100) % 10;\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_MAJOR / 10) % 10;\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_MAJOR % 10);\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_MINOR % 10);\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_PATCH / 1000) % 10;\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_PATCH / 100) % 10;\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_PATCH / 10) % 10;\n\tdriver_version <<= 4;\n\tdriver_version += (VERSION_PATCH % 10);\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = ctrl_set_oob(demod, NULL);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* refresh the audio data structure with default */\n\text_attr->aud_data = drxj_default_aud_data_g;\n\n\tdemod->my_common_attr->is_opened = true;\n\tdrxj_set_lna_state(demod, false);\n\treturn 0;\nrw_error:\n\tcommon_attr->is_opened = false;\n\treturn rc;\n}",
        "static void rcu_torture_fwd_prog_cr(struct rcu_fwd *rfp)\n{\n\tunsigned long cver;\n\tunsigned long flags;\n\tunsigned long gps;": "static void rcu_torture_fwd_prog_cr(struct rcu_fwd *rfp)\n{\n\tunsigned long cver;\n\tunsigned long flags;\n\tunsigned long gps;\n\tint i;\n\tlong n_launders;\n\tlong n_launders_cb_snap;\n\tlong n_launders_sa;\n\tlong n_max_cbs;\n\tlong n_max_gps;\n\tstruct rcu_fwd_cb *rfcp;\n\tstruct rcu_fwd_cb *rfcpn;\n\tunsigned long stopat;\n\tunsigned long stoppedat;\n\n\tpr_alert(\"%s: Starting forward-progress test %d\\n\", __func__, rfp->rcu_fwd_id);\n\tif (READ_ONCE(rcu_fwd_emergency_stop))\n\t\treturn; /* Get out of the way quickly, no GP wait! */\n\tif (!cur_ops->call)\n\t\treturn; /* Can't do call_rcu() fwd prog without ->call. */\n\n\t/* Loop continuously posting RCU callbacks. */\n\tatomic_inc(&rcu_fwd_cb_nodelay);\n\tcur_ops->sync(); /* Later readers see above write. */\n\tWRITE_ONCE(rfp->rcu_fwd_startat, jiffies);\n\tstopat = rfp->rcu_fwd_startat + MAX_FWD_CB_JIFFIES;\n\tn_launders = 0;\n\trfp->n_launders_cb = 0; // Hoist initialization for multi-kthread\n\tn_launders_sa = 0;\n\tn_max_cbs = 0;\n\tn_max_gps = 0;\n\tfor (i = 0; i < ARRAY_SIZE(rfp->n_launders_hist); i++)\n\t\trfp->n_launders_hist[i].n_launders = 0;\n\tcver = READ_ONCE(rcu_torture_current_version);\n\tgps = cur_ops->get_gp_seq();\n\trfp->rcu_launder_gp_seq_start = gps;\n\ttick_dep_set_task(current, TICK_DEP_BIT_RCU);\n\twhile (time_before(jiffies, stopat) &&\n\t       !shutdown_time_arrived() &&\n\t       !READ_ONCE(rcu_fwd_emergency_stop) && !torture_must_stop()) {\n\t\trfcp = READ_ONCE(rfp->rcu_fwd_cb_head);\n\t\trfcpn = NULL;\n\t\tif (rfcp)\n\t\t\trfcpn = READ_ONCE(rfcp->rfc_next);\n\t\tif (rfcpn) {\n\t\t\tif (rfcp->rfc_gps >= MIN_FWD_CB_LAUNDERS &&\n\t\t\t    ++n_max_gps >= MIN_FWD_CBS_LAUNDERED)\n\t\t\t\tbreak;\n\t\t\trfp->rcu_fwd_cb_head = rfcpn;\n\t\t\tn_launders++;\n\t\t\tn_launders_sa++;\n\t\t} else if (!cur_ops->cbflood_max || cur_ops->cbflood_max > n_max_cbs) {\n\t\t\trfcp = kmalloc(sizeof(*rfcp), GFP_KERNEL);\n\t\t\tif (WARN_ON_ONCE(!rfcp)) {\n\t\t\t\tschedule_timeout_interruptible(1);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tn_max_cbs++;\n\t\t\tn_launders_sa = 0;\n\t\t\trfcp->rfc_gps = 0;\n\t\t\trfcp->rfc_rfp = rfp;\n\t\t} else {\n\t\t\trfcp = NULL;\n\t\t}\n\t\tif (rfcp)\n\t\t\tcur_ops->call(&rfcp->rh, rcu_torture_fwd_cb_cr);\n\t\trcu_torture_fwd_prog_cond_resched(n_launders + n_max_cbs);\n\t\tif (tick_nohz_full_enabled()) {\n\t\t\tlocal_irq_save(flags);\n\t\t\trcu_momentary_dyntick_idle();\n\t\t\tlocal_irq_restore(flags);\n\t\t}\n\t}\n\tstoppedat = jiffies;\n\tn_launders_cb_snap = READ_ONCE(rfp->n_launders_cb);\n\tcver = READ_ONCE(rcu_torture_current_version) - cver;\n\tgps = rcutorture_seq_diff(cur_ops->get_gp_seq(), gps);\n\tpr_alert(\"%s: Waiting for CBs: %pS() %d\\n\", __func__, cur_ops->cb_barrier, rfp->rcu_fwd_id);\n\tcur_ops->cb_barrier(); /* Wait for callbacks to be invoked. */\n\t(void)rcu_torture_fwd_prog_cbfree(rfp);\n\n\tif (!torture_must_stop() && !READ_ONCE(rcu_fwd_emergency_stop) &&\n\t    !shutdown_time_arrived()) {\n\t\tWARN_ON(n_max_gps < MIN_FWD_CBS_LAUNDERED);\n\t\tpr_alert(\"%s Duration %lu barrier: %lu pending %ld n_launders: %ld n_launders_sa: %ld n_max_gps: %ld n_max_cbs: %ld cver %ld gps %ld\\n\",\n\t\t\t __func__,\n\t\t\t stoppedat - rfp->rcu_fwd_startat, jiffies - stoppedat,\n\t\t\t n_launders + n_max_cbs - n_launders_cb_snap,\n\t\t\t n_launders, n_launders_sa,\n\t\t\t n_max_gps, n_max_cbs, cver, gps);\n\t\tatomic_long_add(n_max_cbs, &rcu_fwd_max_cbs);\n\t\tmutex_lock(&rcu_fwd_mutex); // Serialize histograms.\n\t\trcu_torture_fwd_cb_hist(rfp);\n\t\tmutex_unlock(&rcu_fwd_mutex);\n\t}\n\tschedule_timeout_uninterruptible(HZ); /* Let CBs drain. */\n\ttick_dep_clear_task(current, TICK_DEP_BIT_RCU);\n\tatomic_dec(&rcu_fwd_cb_nodelay);\n}",
        "static int __trace_kprobe_create(int argc, const char *argv[])\n{\n\t/*\n\t * Argument syntax:\n\t *  - Add kprobe:": "static int __trace_kprobe_create(int argc, const char *argv[])\n{\n\t/*\n\t * Argument syntax:\n\t *  - Add kprobe:\n\t *      p[:[GRP/]EVENT] [MOD:]KSYM[+OFFS]|KADDR [FETCHARGS]\n\t *  - Add kretprobe:\n\t *      r[MAXACTIVE][:[GRP/]EVENT] [MOD:]KSYM[+0] [FETCHARGS]\n\t *    Or\n\t *      p:[GRP/]EVENT] [MOD:]KSYM[+0]%return [FETCHARGS]\n\t *\n\t * Fetch args:\n\t *  $retval\t: fetch return value\n\t *  $stack\t: fetch stack address\n\t *  $stackN\t: fetch Nth of stack (N:0-)\n\t *  $comm       : fetch current task comm\n\t *  @ADDR\t: fetch memory at ADDR (ADDR should be in kernel)\n\t *  @SYM[+|-offs] : fetch memory at SYM +|- offs (SYM is a data symbol)\n\t *  %REG\t: fetch register REG\n\t * Dereferencing memory fetch:\n\t *  +|-offs(ARG) : fetch memory at ARG +|- offs address.\n\t * Alias name of args:\n\t *  NAME=FETCHARG : set NAME as alias of FETCHARG.\n\t * Type of args:\n\t *  FETCHARG:TYPE : use TYPE instead of unsigned long.\n\t */\n\tstruct trace_kprobe *tk = NULL;\n\tint i, len, ret = 0;\n\tbool is_return = false;\n\tchar *symbol = NULL, *tmp = NULL;\n\tconst char *event = NULL, *group = KPROBE_EVENT_SYSTEM;\n\tenum probe_print_type ptype;\n\tint maxactive = 0;\n\tlong offset = 0;\n\tvoid *addr = NULL;\n\tchar buf[MAX_EVENT_NAME_LEN];\n\tunsigned int flags = TPARG_FL_KERNEL;\n\n\tswitch (argv[0][0]) {\n\tcase 'r':\n\t\tis_return = true;\n\t\tbreak;\n\tcase 'p':\n\t\tbreak;\n\tdefault:\n\t\treturn -ECANCELED;\n\t}\n\tif (argc < 2)\n\t\treturn -ECANCELED;\n\n\ttrace_probe_log_init(\"trace_kprobe\", argc, argv);\n\n\tevent = strchr(&argv[0][1], ':');\n\tif (event)\n\t\tevent++;\n\n\tif (isdigit(argv[0][1])) {\n\t\tif (!is_return) {\n\t\t\ttrace_probe_log_err(1, MAXACT_NO_KPROBE);\n\t\t\tgoto parse_error;\n\t\t}\n\t\tif (event)\n\t\t\tlen = event - &argv[0][1] - 1;\n\t\telse\n\t\t\tlen = strlen(&argv[0][1]);\n\t\tif (len > MAX_EVENT_NAME_LEN - 1) {\n\t\t\ttrace_probe_log_err(1, BAD_MAXACT);\n\t\t\tgoto parse_error;\n\t\t}\n\t\tmemcpy(buf, &argv[0][1], len);\n\t\tbuf[len] = '\\0';\n\t\tret = kstrtouint(buf, 0, &maxactive);\n\t\tif (ret || !maxactive) {\n\t\t\ttrace_probe_log_err(1, BAD_MAXACT);\n\t\t\tgoto parse_error;\n\t\t}\n\t\t/* kretprobes instances are iterated over via a list. The\n\t\t * maximum should stay reasonable.\n\t\t */\n\t\tif (maxactive > KRETPROBE_MAXACTIVE_MAX) {\n\t\t\ttrace_probe_log_err(1, MAXACT_TOO_BIG);\n\t\t\tgoto parse_error;\n\t\t}\n\t}\n\n\t/* try to parse an address. if that fails, try to read the\n\t * input as a symbol. */\n\tif (kstrtoul(argv[1], 0, (unsigned long *)&addr)) {\n\t\ttrace_probe_log_set_index(1);\n\t\t/* Check whether uprobe event specified */\n\t\tif (strchr(argv[1], '/') && strchr(argv[1], ':')) {\n\t\t\tret = -ECANCELED;\n\t\t\tgoto error;\n\t\t}\n\t\t/* a symbol specified */\n\t\tsymbol = kstrdup(argv[1], GFP_KERNEL);\n\t\tif (!symbol)\n\t\t\treturn -ENOMEM;\n\n\t\ttmp = strchr(symbol, '%');\n\t\tif (tmp) {\n\t\t\tif (!strcmp(tmp, \"%return\")) {\n\t\t\t\t*tmp = '\\0';\n\t\t\t\tis_return = true;\n\t\t\t} else {\n\t\t\t\ttrace_probe_log_err(tmp - symbol, BAD_ADDR_SUFFIX);\n\t\t\t\tgoto parse_error;\n\t\t\t}\n\t\t}\n\n\t\t/* TODO: support .init module functions */\n\t\tret = traceprobe_split_symbol_offset(symbol, &offset);\n\t\tif (ret || offset < 0 || offset > UINT_MAX) {\n\t\t\ttrace_probe_log_err(0, BAD_PROBE_ADDR);\n\t\t\tgoto parse_error;\n\t\t}\n\t\tif (is_return)\n\t\t\tflags |= TPARG_FL_RETURN;\n\t\tret = kprobe_on_func_entry(NULL, symbol, offset);\n\t\tif (ret == 0)\n\t\t\tflags |= TPARG_FL_FENTRY;\n\t\t/* Defer the ENOENT case until register kprobe */\n\t\tif (ret == -EINVAL && is_return) {\n\t\t\ttrace_probe_log_err(0, BAD_RETPROBE);\n\t\t\tgoto parse_error;\n\t\t}\n\t}\n\n\ttrace_probe_log_set_index(0);\n\tif (event) {\n\t\tret = traceprobe_parse_event_name(&event, &group, buf,\n\t\t\t\t\t\t  event - argv[0]);\n\t\tif (ret)\n\t\t\tgoto parse_error;\n\t} else {\n\t\t/* Make a new event name */\n\t\tif (symbol)\n\t\t\tsnprintf(buf, MAX_EVENT_NAME_LEN, \"%c_%s_%ld\",\n\t\t\t\t is_return ? 'r' : 'p', symbol, offset);\n\t\telse\n\t\t\tsnprintf(buf, MAX_EVENT_NAME_LEN, \"%c_0x%p\",\n\t\t\t\t is_return ? 'r' : 'p', addr);\n\t\tsanitize_event_name(buf);\n\t\tevent = buf;\n\t}\n\n\t/* setup a probe */\n\ttk = alloc_trace_kprobe(group, event, addr, symbol, offset, maxactive,\n\t\t\t       argc - 2, is_return);\n\tif (IS_ERR(tk)) {\n\t\tret = PTR_ERR(tk);\n\t\t/* This must return -ENOMEM, else there is a bug */\n\t\tWARN_ON_ONCE(ret != -ENOMEM);\n\t\tgoto out;\t/* We know tk is not allocated */\n\t}\n\targc -= 2; argv += 2;\n\n\t/* parse arguments */\n\tfor (i = 0; i < argc && i < MAX_TRACE_ARGS; i++) {\n\t\ttrace_probe_log_set_index(i + 2);\n\t\tret = traceprobe_parse_probe_arg(&tk->tp, i, argv[i], flags);\n\t\tif (ret)\n\t\t\tgoto error;\t/* This can be -ENOMEM */\n\t}\n\n\tptype = is_return ? PROBE_PRINT_RETURN : PROBE_PRINT_NORMAL;\n\tret = traceprobe_set_print_fmt(&tk->tp, ptype);\n\tif (ret < 0)\n\t\tgoto error;\n\n\tret = register_trace_kprobe(tk);\n\tif (ret) {\n\t\ttrace_probe_log_set_index(1);\n\t\tif (ret == -EILSEQ)\n\t\t\ttrace_probe_log_err(0, BAD_INSN_BNDRY);\n\t\telse if (ret == -ENOENT)\n\t\t\ttrace_probe_log_err(0, BAD_PROBE_ADDR);\n\t\telse if (ret != -ENOMEM && ret != -EEXIST)\n\t\t\ttrace_probe_log_err(0, FAIL_REG_PROBE);\n\t\tgoto error;\n\t}\n\nout:\n\ttrace_probe_log_clear();\n\tkfree(symbol);\n\treturn ret;\n\nparse_error:\n\tret = -EINVAL;\nerror:\n\tfree_trace_kprobe(tk);\n\tgoto out;\n}",
        "static int atmel_pmecc_err_location(struct atmel_pmecc_user *user)\n{\n\tint sector_size = get_sectorsize(user);\n\tint degree = sector_size == 512 ? 13 : 14;\n\tstruct atmel_pmecc *pmecc = user->pmecc;": "static int atmel_pmecc_err_location(struct atmel_pmecc_user *user)\n{\n\tint sector_size = get_sectorsize(user);\n\tint degree = sector_size == 512 ? 13 : 14;\n\tstruct atmel_pmecc *pmecc = user->pmecc;\n\tint strength = get_strength(user);\n\tint ret, roots_nbr, i, err_nbr = 0;\n\tint num = (2 * strength) + 1;\n\ts16 *smu = user->smu;\n\tu32 val;\n\n\twritel(PMERRLOC_DISABLE, pmecc->regs.errloc + ATMEL_PMERRLOC_ELDIS);\n\n\tfor (i = 0; i <= user->lmu[strength + 1] >> 1; i++) {\n\t\twritel_relaxed(smu[(strength + 1) * num + i],\n\t\t\t       pmecc->regs.errloc + ATMEL_PMERRLOC_SIGMA(i));\n\t\terr_nbr++;\n\t}\n\n\tval = (err_nbr - 1) << 16;\n\tif (sector_size == 1024)\n\t\tval |= 1;\n\n\twritel(val, pmecc->regs.errloc + ATMEL_PMERRLOC_ELCFG);\n\twritel((sector_size * 8) + (degree * strength),\n\t       pmecc->regs.errloc + ATMEL_PMERRLOC_ELEN);\n\n\tret = readl_relaxed_poll_timeout(pmecc->regs.errloc +\n\t\t\t\t\t ATMEL_PMERRLOC_ELISR,\n\t\t\t\t\t val, val & PMERRLOC_CALC_DONE, 0,\n\t\t\t\t\t PMECC_MAX_TIMEOUT_MS * 1000);\n\tif (ret) {\n\t\tdev_err(pmecc->dev,\n\t\t\t\"PMECC: Timeout to calculate error location.\\n\");\n\t\treturn ret;\n\t}\n\n\troots_nbr = (val & PMERRLOC_ERR_NUM_MASK) >> 8;\n\t/* Number of roots == degree of smu hence <= cap */\n\tif (roots_nbr == user->lmu[strength + 1] >> 1)\n\t\treturn err_nbr - 1;\n\n\t/*\n\t * Number of roots does not match the degree of smu\n\t * unable to correct error.\n\t */\n\treturn -EBADMSG;\n}",
        "static int ksm_merge_hugepages_time(int mapping, int prot, int timeout, size_t map_size)\n{\n\tvoid *map_ptr, *map_ptr_orig;\n\tstruct timespec start_time, end_time;\n\tunsigned long scan_time_ns;": "static int ksm_merge_hugepages_time(int mapping, int prot, int timeout, size_t map_size)\n{\n\tvoid *map_ptr, *map_ptr_orig;\n\tstruct timespec start_time, end_time;\n\tunsigned long scan_time_ns;\n\tint pagemap_fd, n_normal_pages, n_huge_pages;\n\n\tmap_size *= MB;\n\tsize_t len = map_size;\n\n\tlen -= len % HPAGE_SIZE;\n\tmap_ptr_orig = mmap(NULL, len + HPAGE_SIZE, PROT_READ | PROT_WRITE,\n\t\t\tMAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE, -1, 0);\n\tmap_ptr = map_ptr_orig + HPAGE_SIZE - (uintptr_t)map_ptr_orig % HPAGE_SIZE;\n\n\tif (map_ptr_orig == MAP_FAILED)\n\t\terr(2, \"initial mmap\");\n\n\tif (madvise(map_ptr, len + HPAGE_SIZE, MADV_HUGEPAGE))\n\t\terr(2, \"MADV_HUGEPAGE\");\n\n\tpagemap_fd = open(\"/proc/self/pagemap\", O_RDONLY);\n\tif (pagemap_fd < 0)\n\t\terr(2, \"open pagemap\");\n\n\tn_normal_pages = 0;\n\tn_huge_pages = 0;\n\tfor (void *p = map_ptr; p < map_ptr + len; p += HPAGE_SIZE) {\n\t\tif (allocate_transhuge(p, pagemap_fd) < 0)\n\t\t\tn_normal_pages++;\n\t\telse\n\t\t\tn_huge_pages++;\n\t}\n\tprintf(\"Number of normal pages:    %d\\n\", n_normal_pages);\n\tprintf(\"Number of huge pages:    %d\\n\", n_huge_pages);\n\n\tmemset(map_ptr, '*', len);\n\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &start_time)) {\n\t\tperror(\"clock_gettime\");\n\t\tgoto err_out;\n\t}\n\tif (ksm_merge_pages(map_ptr, map_size, start_time, timeout))\n\t\tgoto err_out;\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &end_time)) {\n\t\tperror(\"clock_gettime\");\n\t\tgoto err_out;\n\t}\n\n\tscan_time_ns = (end_time.tv_sec - start_time.tv_sec) * NSEC_PER_SEC +\n\t\t       (end_time.tv_nsec - start_time.tv_nsec);\n\n\tprintf(\"Total size:    %lu MiB\\n\", map_size / MB);\n\tprintf(\"Total time:    %ld.%09ld s\\n\", scan_time_ns / NSEC_PER_SEC,\n\t       scan_time_ns % NSEC_PER_SEC);\n\tprintf(\"Average speed:  %.3f MiB/s\\n\", (map_size / MB) /\n\t\t\t\t\t       ((double)scan_time_ns / NSEC_PER_SEC));\n\n\tmunmap(map_ptr_orig, len + HPAGE_SIZE);\n\treturn KSFT_PASS;\n\nerr_out:\n\tprintf(\"Not OK\\n\");\n\tmunmap(map_ptr_orig, len + HPAGE_SIZE);\n\treturn KSFT_FAIL;\n}",
        "static int ksm_cow_time(int mapping, int prot, int timeout, size_t page_size)\n{\n\tvoid *map_ptr;\n\tstruct timespec start_time, end_time;\n\tunsigned long cow_time_ns;": "static int ksm_cow_time(int mapping, int prot, int timeout, size_t page_size)\n{\n\tvoid *map_ptr;\n\tstruct timespec start_time, end_time;\n\tunsigned long cow_time_ns;\n\n\t/* page_count must be less than 2*page_size */\n\tsize_t page_count = 4000;\n\n\tmap_ptr = allocate_memory(NULL, prot, mapping, '*', page_size * page_count);\n\tif (!map_ptr)\n\t\treturn KSFT_FAIL;\n\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &start_time)) {\n\t\tperror(\"clock_gettime\");\n\t\treturn KSFT_FAIL;\n\t}\n\tfor (size_t i = 0; i < page_count - 1; i = i + 2)\n\t\tmemset(map_ptr + page_size * i, '-', 1);\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &end_time)) {\n\t\tperror(\"clock_gettime\");\n\t\treturn KSFT_FAIL;\n\t}\n\n\tcow_time_ns = (end_time.tv_sec - start_time.tv_sec) * NSEC_PER_SEC +\n\t\t       (end_time.tv_nsec - start_time.tv_nsec);\n\n\tprintf(\"Total size:    %lu MiB\\n\\n\", (page_size * page_count) / MB);\n\tprintf(\"Not merged pages:\\n\");\n\tprintf(\"Total time:     %ld.%09ld s\\n\", cow_time_ns / NSEC_PER_SEC,\n\t       cow_time_ns % NSEC_PER_SEC);\n\tprintf(\"Average speed:  %.3f MiB/s\\n\\n\", ((page_size * (page_count / 2)) / MB) /\n\t\t\t\t\t       ((double)cow_time_ns / NSEC_PER_SEC));\n\n\t/* Create 2000 pairs of duplicate pages */\n\tfor (size_t i = 0; i < page_count - 1; i = i + 2) {\n\t\tmemset(map_ptr + page_size * i, '+', i / 2 + 1);\n\t\tmemset(map_ptr + page_size * (i + 1), '+', i / 2 + 1);\n\t}\n\tif (ksm_merge_pages(map_ptr, page_size * page_count, start_time, timeout))\n\t\tgoto err_out;\n\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &start_time)) {\n\t\tperror(\"clock_gettime\");\n\t\tgoto err_out;\n\t}\n\tfor (size_t i = 0; i < page_count - 1; i = i + 2)\n\t\tmemset(map_ptr + page_size * i, '-', 1);\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &end_time)) {\n\t\tperror(\"clock_gettime\");\n\t\tgoto err_out;\n\t}\n\n\tcow_time_ns = (end_time.tv_sec - start_time.tv_sec) * NSEC_PER_SEC +\n\t\t       (end_time.tv_nsec - start_time.tv_nsec);\n\n\tprintf(\"Merged pages:\\n\");\n\tprintf(\"Total time:     %ld.%09ld s\\n\", cow_time_ns / NSEC_PER_SEC,\n\t       cow_time_ns % NSEC_PER_SEC);\n\tprintf(\"Average speed:  %.3f MiB/s\\n\", ((page_size * (page_count / 2)) / MB) /\n\t\t\t\t\t       ((double)cow_time_ns / NSEC_PER_SEC));\n\n\tmunmap(map_ptr, page_size * page_count);\n\treturn KSFT_PASS;\n\nerr_out:\n\tprintf(\"Not OK\\n\");\n\tmunmap(map_ptr, page_size * page_count);\n\treturn KSFT_FAIL;\n}",
        "static bool csd_lock_wait_toolong(struct __call_single_data *csd, u64 ts0, u64 *ts1, int *bug_id)\n{\n\tint cpu = -1;\n\tint cpux;\n\tbool firsttime;": "static bool csd_lock_wait_toolong(struct __call_single_data *csd, u64 ts0, u64 *ts1, int *bug_id)\n{\n\tint cpu = -1;\n\tint cpux;\n\tbool firsttime;\n\tu64 ts2, ts_delta;\n\tcall_single_data_t *cpu_cur_csd;\n\tunsigned int flags = READ_ONCE(csd->node.u_flags);\n\tunsigned long long csd_lock_timeout_ns = csd_lock_timeout * NSEC_PER_MSEC;\n\n\tif (!(flags & CSD_FLAG_LOCK)) {\n\t\tif (!unlikely(*bug_id))\n\t\t\treturn true;\n\t\tcpu = csd_lock_wait_getcpu(csd);\n\t\tpr_alert(\"csd: CSD lock (#%d) got unstuck on CPU#%02d, CPU#%02d released the lock.\\n\",\n\t\t\t *bug_id, raw_smp_processor_id(), cpu);\n\t\treturn true;\n\t}\n\n\tts2 = sched_clock();\n\tts_delta = ts2 - *ts1;\n\tif (likely(ts_delta <= csd_lock_timeout_ns || csd_lock_timeout_ns == 0))\n\t\treturn false;\n\n\tfirsttime = !*bug_id;\n\tif (firsttime)\n\t\t*bug_id = atomic_inc_return(&csd_bug_count);\n\tcpu = csd_lock_wait_getcpu(csd);\n\tif (WARN_ONCE(cpu < 0 || cpu >= nr_cpu_ids, \"%s: cpu = %d\\n\", __func__, cpu))\n\t\tcpux = 0;\n\telse\n\t\tcpux = cpu;\n\tcpu_cur_csd = smp_load_acquire(&per_cpu(cur_csd, cpux)); /* Before func and info. */\n\tpr_alert(\"csd: %s non-responsive CSD lock (#%d) on CPU#%d, waiting %llu ns for CPU#%02d %pS(%ps).\\n\",\n\t\t firsttime ? \"Detected\" : \"Continued\", *bug_id, raw_smp_processor_id(), ts2 - ts0,\n\t\t cpu, csd->func, csd->info);\n\tif (cpu_cur_csd && csd != cpu_cur_csd) {\n\t\tpr_alert(\"\\tcsd: CSD lock (#%d) handling prior %pS(%ps) request.\\n\",\n\t\t\t *bug_id, READ_ONCE(per_cpu(cur_csd_func, cpux)),\n\t\t\t READ_ONCE(per_cpu(cur_csd_info, cpux)));\n\t} else {\n\t\tpr_alert(\"\\tcsd: CSD lock (#%d) %s.\\n\",\n\t\t\t *bug_id, !cpu_cur_csd ? \"unresponsive\" : \"handling this request\");\n\t}\n\tif (cpu >= 0) {\n\t\tif (static_branch_unlikely(&csdlock_debug_extended))\n\t\t\tcsd_lock_print_extended(csd, cpu);\n\t\tif (!trigger_single_cpu_backtrace(cpu))\n\t\t\tdump_cpu_task(cpu);\n\t\tif (!cpu_cur_csd) {\n\t\t\tpr_alert(\"csd: Re-sending CSD lock (#%d) IPI from CPU#%02d to CPU#%02d\\n\", *bug_id, raw_smp_processor_id(), cpu);\n\t\t\tarch_send_call_function_single_ipi(cpu);\n\t\t}\n\t}\n\tdump_stack();\n\t*ts1 = ts2;\n\n\treturn false;\n}",
        "static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)\n{\n\tint current_plug_status;\n\tint status_changed = 0;\n\tint reg_cdc_status;": "static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)\n{\n\tint current_plug_status;\n\tint status_changed = 0;\n\tint reg_cdc_status;\n\tint reg_hs_status;\n\tint reg_ts_status;\n\tint type;\n\n\t/* Read jack detect status registers */\n\treg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);\n\treg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);\n\treg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);\n\n\t/* If status values are < 0, read error has occurred. */\n\tif (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)\n\t\treturn -EIO;\n\n\tcurrent_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK))\n\t\t\t\t>> CS42L42_TS_PLUG_SHIFT;\n\n\t/* HSDET_AUTO_DONE */\n\tif (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) {\n\n\t\t/* Disable HSDET_AUTO_DONE */\n\t\tcs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);\n\n\t\ttype = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT;\n\n\t\t/* Configure the HSDET mode. */\n\t\tcs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);\n\n\t\tif (cs42l42->no_type_dect) {\n\t\t\tstatus_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);\n\t\t} else {\n\t\t\tif (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) {\n\t\t\t\tcodec_dbg(cs42l42->codec,\n\t\t\t\t\t  \"Auto detect value not valid (%d), running manual det\\n\",\n\t\t\t\t\t  type);\n\t\t\t\ttype = cs42l42_manual_hs_det(cs42l42);\n\t\t\t}\n\n\t\t\tswitch (type) {\n\t\t\tcase CS42L42_PLUG_CTIA:\n\t\t\tcase CS42L42_PLUG_OMTP:\n\t\t\t\tstatus_changed = 1;\n\t\t\t\tcs42l42->hp_jack_in = 1;\n\t\t\t\tcs42l42->mic_jack_in = 1;\n\t\t\t\tbreak;\n\t\t\tcase CS42L42_PLUG_HEADPHONE:\n\t\t\t\tstatus_changed = 1;\n\t\t\t\tcs42l42->hp_jack_in = 1;\n\t\t\t\tcs42l42->mic_jack_in = 0;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tstatus_changed = 1;\n\t\t\t\tcs42l42->hp_jack_in = 0;\n\t\t\t\tcs42l42->mic_jack_in = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcodec_dbg(cs42l42->codec, \"Detection done (%d)\\n\", type);\n\t\t}\n\n\t\t/* Enable the HPOUT ground clamp and configure the HP pull-down */\n\t\tcs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);\n\t\t/* Re-Enable Tip Sense Interrupt */\n\t\tcs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);\n\t} else {\n\t\tstatus_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);\n\t}\n\n\treturn status_changed;\n}",
        "static void print_drs_error(unsigned int dsr)\n{\n\tint prog_status = (dsr & DSR_RPS) >> 8;\n\n\tif (!(dsr & DSR_AVAILABLE))": "static void print_drs_error(unsigned int dsr)\n{\n\tint prog_status = (dsr & DSR_RPS) >> 8;\n\n\tif (!(dsr & DSR_AVAILABLE))\n\t\tpr_notice(\"DSR.15: (0) Device not Available\\n\");\n\tif ((prog_status & 0x03) == 0x03)\n\t\tpr_notice(\"DSR.9,8: (11) Attempt to program invalid half with 41h command\\n\");\n\telse if (prog_status & 0x02)\n\t\tpr_notice(\"DSR.9,8: (10) Object Mode Program attempt in region with Control Mode data\\n\");\n\telse if (prog_status &  0x01)\n\t\tpr_notice(\"DSR.9,8: (01) Program attempt in region with Object Mode data\\n\");\n\tif (!(dsr & DSR_READY_STATUS))\n\t\tpr_notice(\"DSR.7: (0) Device is Busy\\n\");\n\tif (dsr & DSR_ESS)\n\t\tpr_notice(\"DSR.6: (1) Erase Suspended\\n\");\n\tif (dsr & DSR_ERASE_STATUS)\n\t\tpr_notice(\"DSR.5: (1) Erase/Blank check error\\n\");\n\tif (dsr & DSR_PROGRAM_STATUS)\n\t\tpr_notice(\"DSR.4: (1) Program Error\\n\");\n\tif (dsr & DSR_VPPS)\n\t\tpr_notice(\"DSR.3: (1) Vpp low detect, operation aborted\\n\");\n\tif (dsr & DSR_PSS)\n\t\tpr_notice(\"DSR.2: (1) Program suspended\\n\");\n\tif (dsr & DSR_DPS)\n\t\tpr_notice(\"DSR.1: (1) Aborted Erase/Program attempt on locked block\\n\");\n}",
        "static int perf_sample__fprintf_synth_evt(struct perf_sample *sample, FILE *fp)\n{\n\tstruct perf_synth_intel_evt *data = perf_sample__synth_ptr(sample);\n\tconst char *cfe[32] = {NULL, \"INTR\", \"IRET\", \"SMI\", \"RSM\", \"SIPI\",\n\t\t\t       \"INIT\", \"VMENTRY\", \"VMEXIT\", \"VMEXIT_INTR\",": "static int perf_sample__fprintf_synth_evt(struct perf_sample *sample, FILE *fp)\n{\n\tstruct perf_synth_intel_evt *data = perf_sample__synth_ptr(sample);\n\tconst char *cfe[32] = {NULL, \"INTR\", \"IRET\", \"SMI\", \"RSM\", \"SIPI\",\n\t\t\t       \"INIT\", \"VMENTRY\", \"VMEXIT\", \"VMEXIT_INTR\",\n\t\t\t       \"SHUTDOWN\"};\n\tconst char *evd[64] = {\"PFA\", \"VMXQ\", \"VMXR\"};\n\tconst char *s;\n\tint len, i;\n\n\tif (perf_sample__bad_synth_size(sample, *data))\n\t\treturn 0;\n\n\ts = cfe[data->type];\n\tif (s) {\n\t\tlen = fprintf(fp, \" cfe: %s IP: %d vector: %u\",\n\t\t\t      s, data->ip, data->vector);\n\t} else {\n\t\tlen = fprintf(fp, \" cfe: %u IP: %d vector: %u\",\n\t\t\t      data->type, data->ip, data->vector);\n\t}\n\tfor (i = 0; i < data->evd_cnt; i++) {\n\t\tunsigned int et = data->evd[i].evd_type & 0x3f;\n\n\t\ts = evd[et];\n\t\tif (s) {\n\t\t\tlen += fprintf(fp, \" %s: %#\" PRIx64,\n\t\t\t\t       s, data->evd[i].payload);\n\t\t} else {\n\t\t\tlen += fprintf(fp, \" EVD_%u: %#\" PRIx64,\n\t\t\t\t       et, data->evd[i].payload);\n\t\t}\n\t}\n\treturn len + perf_sample__fprintf_pt_spacing(len, fp);\n}",
        "static void readwriter(struct pl022 *pl022)\n{\n\n\t/*\n\t * The FIFO depth is different between primecell variants.": "static void readwriter(struct pl022 *pl022)\n{\n\n\t/*\n\t * The FIFO depth is different between primecell variants.\n\t * I believe filling in too much in the FIFO might cause\n\t * errons in 8bit wide transfers on ARM variants (just 8 words\n\t * FIFO, means only 8x8 = 64 bits in FIFO) at least.\n\t *\n\t * To prevent this issue, the TX FIFO is only filled to the\n\t * unused RX FIFO fill length, regardless of what the TX\n\t * FIFO status flag indicates.\n\t */\n\tdev_dbg(&pl022->adev->dev,\n\t\t\"%s, rx: %p, rxend: %p, tx: %p, txend: %p\\n\",\n\t\t__func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);\n\n\t/* Read as much as you can */\n\twhile ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)\n\t       && (pl022->rx < pl022->rx_end)) {\n\t\tswitch (pl022->read) {\n\t\tcase READING_NULL:\n\t\t\treadw(SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\tcase READING_U8:\n\t\t\t*(u8 *) (pl022->rx) =\n\t\t\t\treadw(SSP_DR(pl022->virtbase)) & 0xFFU;\n\t\t\tbreak;\n\t\tcase READING_U16:\n\t\t\t*(u16 *) (pl022->rx) =\n\t\t\t\t(u16) readw(SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\tcase READING_U32:\n\t\t\t*(u32 *) (pl022->rx) =\n\t\t\t\treadl(SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\t}\n\t\tpl022->rx += (pl022->cur_chip->n_bytes);\n\t\tpl022->exp_fifo_level--;\n\t}\n\t/*\n\t * Write as much as possible up to the RX FIFO size\n\t */\n\twhile ((pl022->exp_fifo_level < pl022->vendor->fifodepth)\n\t       && (pl022->tx < pl022->tx_end)) {\n\t\tswitch (pl022->write) {\n\t\tcase WRITING_NULL:\n\t\t\twritew(0x0, SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\tcase WRITING_U8:\n\t\t\twritew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\tcase WRITING_U16:\n\t\t\twritew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\tcase WRITING_U32:\n\t\t\twritel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));\n\t\t\tbreak;\n\t\t}\n\t\tpl022->tx += (pl022->cur_chip->n_bytes);\n\t\tpl022->exp_fifo_level++;\n\t\t/*\n\t\t * This inner reader takes care of things appearing in the RX\n\t\t * FIFO as we're transmitting. This will happen a lot since the\n\t\t * clock starts running when you put things into the TX FIFO,\n\t\t * and then things are continuously clocked into the RX FIFO.\n\t\t */\n\t\twhile ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)\n\t\t       && (pl022->rx < pl022->rx_end)) {\n\t\t\tswitch (pl022->read) {\n\t\t\tcase READING_NULL:\n\t\t\t\treadw(SSP_DR(pl022->virtbase));\n\t\t\t\tbreak;\n\t\t\tcase READING_U8:\n\t\t\t\t*(u8 *) (pl022->rx) =\n\t\t\t\t\treadw(SSP_DR(pl022->virtbase)) & 0xFFU;\n\t\t\t\tbreak;\n\t\t\tcase READING_U16:\n\t\t\t\t*(u16 *) (pl022->rx) =\n\t\t\t\t\t(u16) readw(SSP_DR(pl022->virtbase));\n\t\t\t\tbreak;\n\t\t\tcase READING_U32:\n\t\t\t\t*(u32 *) (pl022->rx) =\n\t\t\t\t\treadl(SSP_DR(pl022->virtbase));\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tpl022->rx += (pl022->cur_chip->n_bytes);\n\t\t\tpl022->exp_fifo_level--;\n\t\t}\n\t}\n\t/*\n\t * When we exit here the TX FIFO should be full and the RX FIFO\n\t * should be empty\n\t */\n}",
        "static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)\n{\n\tstruct mxl5005s_state *state = fe->tuner_priv;\n\tunsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];\n\tunsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];": "static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)\n{\n\tstruct mxl5005s_state *state = fe->tuner_priv;\n\tunsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];\n\tunsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];\n\tint TableLen;\n\n\tu32 IfDivval = 0;\n\tunsigned char MasterControlByte;\n\n\tdprintk(1, \"%s() freq=%ld\\n\", __func__, RfFreqHz);\n\n\t/* Set MxL5005S tuner RF frequency according to example code. */\n\n\t/* Tuner RF frequency setting stage 0 */\n\tMXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);\n\tAddrTable[0] = MASTER_CONTROL_ADDR;\n\tByteTable[0] |= state->config->AgcMasterByte;\n\n\tmxl5005s_writeregs(fe, AddrTable, ByteTable, 1);\n\n\t/* Tuner RF frequency setting stage 1 */\n\tMXL_TuneRF(fe, RfFreqHz);\n\n\tMXL_ControlRead(fe, IF_DIVVAL, &IfDivval);\n\n\tMXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);\n\tMXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);\n\tMXL_ControlWrite(fe, IF_DIVVAL, 8);\n\tMXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);\n\n\tMXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);\n\tAddrTable[TableLen] = MASTER_CONTROL_ADDR ;\n\tByteTable[TableLen] = MasterControlByte |\n\t\tstate->config->AgcMasterByte;\n\tTableLen += 1;\n\n\tmxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);\n\n\t/* Wait 30 ms. */\n\tmsleep(150);\n\n\t/* Tuner RF frequency setting stage 2 */\n\tMXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);\n\tMXL_ControlWrite(fe, IF_DIVVAL, IfDivval);\n\tMXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);\n\n\tMXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);\n\tAddrTable[TableLen] = MASTER_CONTROL_ADDR ;\n\tByteTable[TableLen] = MasterControlByte |\n\t\tstate->config->AgcMasterByte ;\n\tTableLen += 1;\n\n\tmxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);\n\n\tmsleep(100);\n\n\treturn 0;\n}",
        "static int ni_repack(struct ntfs_inode *ni)\n{\n\tint err = 0;\n\tstruct ntfs_sb_info *sbi = ni->mi.sbi;\n\tstruct mft_inode *mi, *mi_p = NULL;": "static int ni_repack(struct ntfs_inode *ni)\n{\n\tint err = 0;\n\tstruct ntfs_sb_info *sbi = ni->mi.sbi;\n\tstruct mft_inode *mi, *mi_p = NULL;\n\tstruct ATTRIB *attr = NULL, *attr_p;\n\tstruct ATTR_LIST_ENTRY *le = NULL, *le_p;\n\tCLST alloc = 0;\n\tu8 cluster_bits = sbi->cluster_bits;\n\tCLST svcn, evcn = 0, svcn_p, evcn_p, next_svcn;\n\tu32 roff, rs = sbi->record_size;\n\tstruct runs_tree run;\n\n\trun_init(&run);\n\n\twhile ((attr = ni_enum_attr_ex(ni, attr, &le, &mi))) {\n\t\tif (!attr->non_res)\n\t\t\tcontinue;\n\n\t\tsvcn = le64_to_cpu(attr->nres.svcn);\n\t\tif (svcn != le64_to_cpu(le->vcn)) {\n\t\t\terr = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!svcn) {\n\t\t\talloc = le64_to_cpu(attr->nres.alloc_size) >>\n\t\t\t\tcluster_bits;\n\t\t\tmi_p = NULL;\n\t\t} else if (svcn != evcn + 1) {\n\t\t\terr = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\n\t\tevcn = le64_to_cpu(attr->nres.evcn);\n\n\t\tif (svcn > evcn + 1) {\n\t\t\terr = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!mi_p) {\n\t\t\t/* Do not try if not enogh free space. */\n\t\t\tif (le32_to_cpu(mi->mrec->used) + 8 >= rs)\n\t\t\t\tcontinue;\n\n\t\t\t/* Do not try if last attribute segment. */\n\t\t\tif (evcn + 1 == alloc)\n\t\t\t\tcontinue;\n\t\t\trun_close(&run);\n\t\t}\n\n\t\troff = le16_to_cpu(attr->nres.run_off);\n\t\terr = run_unpack(&run, sbi, ni->mi.rno, svcn, evcn, svcn,\n\t\t\t\t Add2Ptr(attr, roff),\n\t\t\t\t le32_to_cpu(attr->size) - roff);\n\t\tif (err < 0)\n\t\t\tbreak;\n\n\t\tif (!mi_p) {\n\t\t\tmi_p = mi;\n\t\t\tattr_p = attr;\n\t\t\tsvcn_p = svcn;\n\t\t\tevcn_p = evcn;\n\t\t\tle_p = le;\n\t\t\terr = 0;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/*\n\t\t * Run contains data from two records: mi_p and mi\n\t\t * Try to pack in one.\n\t\t */\n\t\terr = mi_pack_runs(mi_p, attr_p, &run, evcn + 1 - svcn_p);\n\t\tif (err)\n\t\t\tbreak;\n\n\t\tnext_svcn = le64_to_cpu(attr_p->nres.evcn) + 1;\n\n\t\tif (next_svcn >= evcn + 1) {\n\t\t\t/* We can remove this attribute segment. */\n\t\t\tal_remove_le(ni, le);\n\t\t\tmi_remove_attr(NULL, mi, attr);\n\t\t\tle = le_p;\n\t\t\tcontinue;\n\t\t}\n\n\t\tattr->nres.svcn = le->vcn = cpu_to_le64(next_svcn);\n\t\tmi->dirty = true;\n\t\tni->attr_list.dirty = true;\n\n\t\tif (evcn + 1 == alloc) {\n\t\t\terr = mi_pack_runs(mi, attr, &run,\n\t\t\t\t\t   evcn + 1 - next_svcn);\n\t\t\tif (err)\n\t\t\t\tbreak;\n\t\t\tmi_p = NULL;\n\t\t} else {\n\t\t\tmi_p = mi;\n\t\t\tattr_p = attr;\n\t\t\tsvcn_p = next_svcn;\n\t\t\tevcn_p = evcn;\n\t\t\tle_p = le;\n\t\t\trun_truncate_head(&run, next_svcn);\n\t\t}\n\t}\n\n\tif (err) {\n\t\tntfs_inode_warn(&ni->vfs_inode, \"repack problem\");\n\t\tntfs_set_state(sbi, NTFS_DIRTY_ERROR);\n\n\t\t/* Pack loaded but not packed runs. */\n\t\tif (mi_p)\n\t\t\tmi_pack_runs(mi_p, attr_p, &run, evcn_p + 1 - svcn_p);\n\t}\n\n\trun_close(&run);\n\treturn err;\n}",
        "static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tstruct npc_key_field *key_fields;\n\t/* Ether type can come from three layers": "static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tstruct npc_key_field *key_fields;\n\t/* Ether type can come from three layers\n\t * (ethernet, single tagged, double tagged)\n\t */\n\tstruct npc_key_field *etype_ether;\n\tstruct npc_key_field *etype_tag1;\n\tstruct npc_key_field *etype_tag2;\n\t/* Outer VLAN TCI can come from two layers\n\t * (single tagged, double tagged)\n\t */\n\tstruct npc_key_field *vlan_tag1;\n\tstruct npc_key_field *vlan_tag2;\n\tu64 *features;\n\tu8 start_lid;\n\tint i;\n\n\tkey_fields = mcam->rx_key_fields;\n\tfeatures = &mcam->rx_features;\n\n\tif (is_npc_intf_tx(intf)) {\n\t\tkey_fields = mcam->tx_key_fields;\n\t\tfeatures = &mcam->tx_features;\n\t}\n\n\t/* Handle header fields which can come from multiple layers like\n\t * etype, outer vlan tci. These fields should have same position in\n\t * the key otherwise to install a mcam rule more than one entry is\n\t * needed which complicates mcam space management.\n\t */\n\tetype_ether = &key_fields[NPC_ETYPE_ETHER];\n\tetype_tag1 = &key_fields[NPC_ETYPE_TAG1];\n\tetype_tag2 = &key_fields[NPC_ETYPE_TAG2];\n\tvlan_tag1 = &key_fields[NPC_VLAN_TAG1];\n\tvlan_tag2 = &key_fields[NPC_VLAN_TAG2];\n\n\t/* if key profile programmed does not extract Ethertype at all */\n\tif (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws)\n\t\tgoto vlan_tci;\n\n\t/* if key profile programmed extracts Ethertype from one layer */\n\tif (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws)\n\t\tkey_fields[NPC_ETYPE] = *etype_ether;\n\tif (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws)\n\t\tkey_fields[NPC_ETYPE] = *etype_tag1;\n\tif (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws)\n\t\tkey_fields[NPC_ETYPE] = *etype_tag2;\n\n\t/* if key profile programmed extracts Ethertype from multiple layers */\n\tif (etype_ether->nr_kws && etype_tag1->nr_kws) {\n\t\tfor (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {\n\t\t\tif (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i])\n\t\t\t\tgoto vlan_tci;\n\t\t}\n\t\tkey_fields[NPC_ETYPE] = *etype_tag1;\n\t}\n\tif (etype_ether->nr_kws && etype_tag2->nr_kws) {\n\t\tfor (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {\n\t\t\tif (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i])\n\t\t\t\tgoto vlan_tci;\n\t\t}\n\t\tkey_fields[NPC_ETYPE] = *etype_tag2;\n\t}\n\tif (etype_tag1->nr_kws && etype_tag2->nr_kws) {\n\t\tfor (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {\n\t\t\tif (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i])\n\t\t\t\tgoto vlan_tci;\n\t\t}\n\t\tkey_fields[NPC_ETYPE] = *etype_tag2;\n\t}\n\n\t/* check none of higher layers overwrite Ethertype */\n\tstart_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1;\n\tif (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf))\n\t\tgoto vlan_tci;\n\t*features |= BIT_ULL(NPC_ETYPE);\nvlan_tci:\n\t/* if key profile does not extract outer vlan tci at all */\n\tif (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws)\n\t\tgoto done;\n\n\t/* if key profile extracts outer vlan tci from one layer */\n\tif (vlan_tag1->nr_kws && !vlan_tag2->nr_kws)\n\t\tkey_fields[NPC_OUTER_VID] = *vlan_tag1;\n\tif (!vlan_tag1->nr_kws && vlan_tag2->nr_kws)\n\t\tkey_fields[NPC_OUTER_VID] = *vlan_tag2;\n\n\t/* if key profile extracts outer vlan tci from multiple layers */\n\tif (vlan_tag1->nr_kws && vlan_tag2->nr_kws) {\n\t\tfor (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {\n\t\t\tif (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i])\n\t\t\t\tgoto done;\n\t\t}\n\t\tkey_fields[NPC_OUTER_VID] = *vlan_tag2;\n\t}\n\t/* check none of higher layers overwrite outer vlan tci */\n\tstart_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1;\n\tif (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf))\n\t\tgoto done;\n\t*features |= BIT_ULL(NPC_OUTER_VID);\ndone:\n\treturn;\n}",
        "static void rtl_hw_start_8125_common(struct rtl8169_private *tp)\n{\n\trtl_pcie_state_l2l3_disable(tp);\n\n\tRTL_W16(tp, 0x382, 0x221b);": "static void rtl_hw_start_8125_common(struct rtl8169_private *tp)\n{\n\trtl_pcie_state_l2l3_disable(tp);\n\n\tRTL_W16(tp, 0x382, 0x221b);\n\tRTL_W8(tp, 0x4500, 0);\n\tRTL_W16(tp, 0x4800, 0);\n\n\t/* disable UPS */\n\tr8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);\n\n\tRTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);\n\n\tr8168_mac_ocp_write(tp, 0xc140, 0xffff);\n\tr8168_mac_ocp_write(tp, 0xc142, 0xffff);\n\n\tr8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);\n\tr8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);\n\tr8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);\n\n\t/* disable new tx descriptor format */\n\tr8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);\n\n\tif (tp->mac_version == RTL_GIGA_MAC_VER_63)\n\t\tr8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);\n\telse\n\t\tr8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);\n\n\tif (tp->mac_version == RTL_GIGA_MAC_VER_63)\n\t\tr8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);\n\telse\n\t\tr8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);\n\n\tr8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);\n\tr8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);\n\tr8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);\n\tr8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);\n\tr8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);\n\tr8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);\n\tr8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);\n\tr8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);\n\tr8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);\n\n\tr8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);\n\tr8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);\n\tudelay(1);\n\tr8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);\n\tRTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);\n\n\tr8168_mac_ocp_write(tp, 0xe098, 0xc302);\n\n\trtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);\n\n\tif (tp->mac_version == RTL_GIGA_MAC_VER_63)\n\t\trtl8125b_config_eee_mac(tp);\n\telse\n\t\trtl8125a_config_eee_mac(tp);\n\n\tRTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);\n\tudelay(10);\n}",
        "static int set_mpeg_start_width(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tstruct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;": "static int set_mpeg_start_width(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tstruct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;\n\tint rc;\n\tu16 fec_oc_comm_mb = 0;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\tcommon_attr = demod->my_common_attr;\n\n\tif ((common_attr->mpeg_cfg.static_clk == true)\n\t    && (common_attr->mpeg_cfg.enable_parallel == false)) {\n\t\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tfec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;\n\t\tif (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)\n\t\t\tfec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;\n\t\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void cobalt_video_input_status_show(struct cobalt_stream *s)\n{\n\tstruct m00389_cvi_regmap __iomem *cvi;\n\tstruct m00233_video_measure_regmap __iomem *vmr;\n\tstruct m00473_freewheel_regmap __iomem *fw;": "static void cobalt_video_input_status_show(struct cobalt_stream *s)\n{\n\tstruct m00389_cvi_regmap __iomem *cvi;\n\tstruct m00233_video_measure_regmap __iomem *vmr;\n\tstruct m00473_freewheel_regmap __iomem *fw;\n\tstruct m00479_clk_loss_detector_regmap __iomem *clkloss;\n\tstruct m00235_fdma_packer_regmap __iomem *packer;\n\tint rx = s->video_channel;\n\tstruct cobalt *cobalt = s->cobalt;\n\tu32 cvi_ctrl, cvi_stat;\n\tu32 vmr_ctrl, vmr_stat;\n\n\tcvi = COBALT_CVI(cobalt, rx);\n\tvmr = COBALT_CVI_VMR(cobalt, rx);\n\tfw = COBALT_CVI_FREEWHEEL(cobalt, rx);\n\tclkloss = COBALT_CVI_CLK_LOSS(cobalt, rx);\n\tpacker = COBALT_CVI_PACKER(cobalt, rx);\n\tcvi_ctrl = ioread32(&cvi->control);\n\tcvi_stat = ioread32(&cvi->status);\n\tvmr_ctrl = ioread32(&vmr->control);\n\tvmr_stat = ioread32(&vmr->status);\n\tcobalt_info(\"rx%d: cvi resolution: %dx%d\\n\", rx,\n\t\t    ioread32(&cvi->frame_width), ioread32(&cvi->frame_height));\n\tcobalt_info(\"rx%d: cvi control: %s%s%s\\n\", rx,\n\t\t(cvi_ctrl & M00389_CONTROL_BITMAP_ENABLE_MSK) ?\n\t\t\t\"enable \" : \"disable \",\n\t\t(cvi_ctrl & M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK) ?\n\t\t\t\"HSync- \" : \"HSync+ \",\n\t\t(cvi_ctrl & M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK) ?\n\t\t\t\"VSync- \" : \"VSync+ \");\n\tcobalt_info(\"rx%d: cvi status: %s%s\\n\", rx,\n\t\t(cvi_stat & M00389_STATUS_BITMAP_LOCK_MSK) ?\n\t\t\t\"lock \" : \"no-lock \",\n\t\t(cvi_stat & M00389_STATUS_BITMAP_ERROR_MSK) ?\n\t\t\t\"error \" : \"no-error \");\n\n\tcobalt_info(\"rx%d: Measurements: %s%s%s%s%s%s%s\\n\", rx,\n\t\t(vmr_ctrl & M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK) ?\n\t\t\t\"HSync- \" : \"HSync+ \",\n\t\t(vmr_ctrl & M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK) ?\n\t\t\t\"VSync- \" : \"VSync+ \",\n\t\t(vmr_ctrl & M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK) ?\n\t\t\t\"enabled \" : \"disabled \",\n\t\t(vmr_ctrl & M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK) ?\n\t\t\t\"irq-enabled \" : \"irq-disabled \",\n\t\t(vmr_ctrl & M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_MSK) ?\n\t\t\t\"update-on-hsync \" : \"\",\n\t\t(vmr_stat & M00233_STATUS_BITMAP_HSYNC_TIMEOUT_MSK) ?\n\t\t\t\"hsync-timeout \" : \"\",\n\t\t(vmr_stat & M00233_STATUS_BITMAP_INIT_DONE_MSK) ?\n\t\t\t\"init-done\" : \"\");\n\tcobalt_info(\"rx%d: irq_status: 0x%02x irq_triggers: 0x%02x\\n\", rx,\n\t\t\tioread32(&vmr->irq_status) & 0xff,\n\t\t\tioread32(&vmr->irq_triggers) & 0xff);\n\tcobalt_info(\"rx%d: vsync: %d\\n\", rx, ioread32(&vmr->vsync_time));\n\tcobalt_info(\"rx%d: vbp: %d\\n\", rx, ioread32(&vmr->vback_porch));\n\tcobalt_info(\"rx%d: vact: %d\\n\", rx, ioread32(&vmr->vactive_area));\n\tcobalt_info(\"rx%d: vfb: %d\\n\", rx, ioread32(&vmr->vfront_porch));\n\tcobalt_info(\"rx%d: hsync: %d\\n\", rx, ioread32(&vmr->hsync_time));\n\tcobalt_info(\"rx%d: hbp: %d\\n\", rx, ioread32(&vmr->hback_porch));\n\tcobalt_info(\"rx%d: hact: %d\\n\", rx, ioread32(&vmr->hactive_area));\n\tcobalt_info(\"rx%d: hfb: %d\\n\", rx, ioread32(&vmr->hfront_porch));\n\tcobalt_info(\"rx%d: Freewheeling: %s%s%s\\n\", rx,\n\t\t(ioread32(&fw->ctrl) & M00473_CTRL_BITMAP_ENABLE_MSK) ?\n\t\t\t\"enabled \" : \"disabled \",\n\t\t(ioread32(&fw->ctrl) & M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_MSK) ?\n\t\t\t\"forced \" : \"\",\n\t\t(ioread32(&fw->status) & M00473_STATUS_BITMAP_FREEWHEEL_MODE_MSK) ?\n\t\t\t\"freewheeling \" : \"video-passthrough \");\n\tiowrite32(0xff, &vmr->irq_status);\n\tcobalt_info(\"rx%d: Clock Loss Detection: %s%s\\n\", rx,\n\t\t(ioread32(&clkloss->ctrl) & M00479_CTRL_BITMAP_ENABLE_MSK) ?\n\t\t\t\"enabled \" : \"disabled \",\n\t\t(ioread32(&clkloss->status) & M00479_STATUS_BITMAP_CLOCK_MISSING_MSK) ?\n\t\t\t\"clock-missing \" : \"found-clock \");\n\tcobalt_info(\"rx%d: Packer: %x\\n\", rx, ioread32(&packer->control));\n}",
        "static int imgu_css_dequeue_data(struct imgu_css *css, int queue, u32 *data)\n{\n\tstatic const unsigned int sp;\n\tvoid __iomem *const base = css->base;\n\tstruct imgu_fw_info *bi = &css->fwp->binary_header[css->fw_sp[sp]];": "static int imgu_css_dequeue_data(struct imgu_css *css, int queue, u32 *data)\n{\n\tstatic const unsigned int sp;\n\tvoid __iomem *const base = css->base;\n\tstruct imgu_fw_info *bi = &css->fwp->binary_header[css->fw_sp[sp]];\n\tstruct imgu_abi_queues __iomem *q = base + IMGU_REG_SP_DMEM_BASE(sp) +\n\t\t\t\t\t\tbi->info.sp.host_sp_queue;\n\tu8 size, start, end, start2;\n\n\tif (queue >= 0) {\n\t\tsize = readb(&q->sp2host_bufq_info[queue].size);\n\t\tstart = readb(&q->sp2host_bufq_info[queue].start);\n\t\tend = readb(&q->sp2host_bufq_info[queue].end);\n\t} else {\n\t\tsize = readb(&q->sp2host_evtq_info.size);\n\t\tstart = readb(&q->sp2host_evtq_info.start);\n\t\tend = readb(&q->sp2host_evtq_info.end);\n\t}\n\n\tif (size == 0)\n\t\treturn -EIO;\n\n\tif (end == start)\n\t\treturn -EBUSY;\t/* Queue empty */\n\n\tstart2 = (start + 1) % size;\n\n\tif (queue >= 0) {\n\t\t*data = readl(&q->sp2host_bufq[queue][start]);\n\t\twriteb(start2, &q->sp2host_bufq_info[queue].start);\n\t} else {\n\t\tint r;\n\n\t\t*data = readl(&q->sp2host_evtq[start]);\n\t\twriteb(start2, &q->sp2host_evtq_info.start);\n\n\t\t/* Acknowledge events dequeued from event queue */\n\t\tr = imgu_css_queue_data(css, queue, 0,\n\t\t\t\t\tIMGU_ABI_EVENT_EVENT_DEQUEUED);\n\t\tif (r < 0)\n\t\t\treturn r;\n\t}\n\n\treturn 0;\n}",
        "static bool rcu_torture_boost_failed(unsigned long gp_state, unsigned long *start)\n{\n\tint cpu;\n\tstatic int dbg_done;\n\tunsigned long end = jiffies;": "static bool rcu_torture_boost_failed(unsigned long gp_state, unsigned long *start)\n{\n\tint cpu;\n\tstatic int dbg_done;\n\tunsigned long end = jiffies;\n\tbool gp_done;\n\tunsigned long j;\n\tstatic unsigned long last_persist;\n\tunsigned long lp;\n\tunsigned long mininterval = test_boost_duration * HZ - HZ / 2;\n\n\tif (end - *start > mininterval) {\n\t\t// Recheck after checking time to avoid false positives.\n\t\tsmp_mb(); // Time check before grace-period check.\n\t\tif (cur_ops->poll_gp_state(gp_state))\n\t\t\treturn false; // passed, though perhaps just barely\n\t\tif (cur_ops->check_boost_failed && !cur_ops->check_boost_failed(gp_state, &cpu)) {\n\t\t\t// At most one persisted message per boost test.\n\t\t\tj = jiffies;\n\t\t\tlp = READ_ONCE(last_persist);\n\t\t\tif (time_after(j, lp + mininterval) && cmpxchg(&last_persist, lp, j) == lp)\n\t\t\t\tpr_info(\"Boost inversion persisted: No QS from CPU %d\\n\", cpu);\n\t\t\treturn false; // passed on a technicality\n\t\t}\n\t\tVERBOSE_TOROUT_STRING(\"rcu_torture_boost boosting failed\");\n\t\tn_rcu_torture_boost_failure++;\n\t\tif (!xchg(&dbg_done, 1) && cur_ops->gp_kthread_dbg) {\n\t\t\tpr_info(\"Boost inversion thread ->rt_priority %u gp_state %lu jiffies %lu\\n\",\n\t\t\t\tcurrent->rt_priority, gp_state, end - *start);\n\t\t\tcur_ops->gp_kthread_dbg();\n\t\t\t// Recheck after print to flag grace period ending during splat.\n\t\t\tgp_done = cur_ops->poll_gp_state(gp_state);\n\t\t\tpr_info(\"Boost inversion: GP %lu %s.\\n\", gp_state,\n\t\t\t\tgp_done ? \"ended already\" : \"still pending\");\n\n\t\t}\n\n\t\treturn true; // failed\n\t} else if (cur_ops->check_boost_failed && !cur_ops->check_boost_failed(gp_state, NULL)) {\n\t\t*start = jiffies;\n\t}\n\n\treturn false; // passed\n}",
        "static int ZSTD_isUpdateAuthorized(ZSTD_cParameter param)\n{\n    switch(param)\n    {\n    case ZSTD_c_compressionLevel:": "static int ZSTD_isUpdateAuthorized(ZSTD_cParameter param)\n{\n    switch(param)\n    {\n    case ZSTD_c_compressionLevel:\n    case ZSTD_c_hashLog:\n    case ZSTD_c_chainLog:\n    case ZSTD_c_searchLog:\n    case ZSTD_c_minMatch:\n    case ZSTD_c_targetLength:\n    case ZSTD_c_strategy:\n        return 1;\n\n    case ZSTD_c_format:\n    case ZSTD_c_windowLog:\n    case ZSTD_c_contentSizeFlag:\n    case ZSTD_c_checksumFlag:\n    case ZSTD_c_dictIDFlag:\n    case ZSTD_c_forceMaxWindow :\n    case ZSTD_c_nbWorkers:\n    case ZSTD_c_jobSize:\n    case ZSTD_c_overlapLog:\n    case ZSTD_c_rsyncable:\n    case ZSTD_c_enableDedicatedDictSearch:\n    case ZSTD_c_enableLongDistanceMatching:\n    case ZSTD_c_ldmHashLog:\n    case ZSTD_c_ldmMinMatch:\n    case ZSTD_c_ldmBucketSizeLog:\n    case ZSTD_c_ldmHashRateLog:\n    case ZSTD_c_forceAttachDict:\n    case ZSTD_c_literalCompressionMode:\n    case ZSTD_c_targetCBlockSize:\n    case ZSTD_c_srcSizeHint:\n    case ZSTD_c_stableInBuffer:\n    case ZSTD_c_stableOutBuffer:\n    case ZSTD_c_blockDelimiters:\n    case ZSTD_c_validateSequences:\n    default:\n        return 0;\n    }\n}",
        "static int ptrace_signal(int signr, kernel_siginfo_t *info, enum pid_type type)\n{\n\t/*\n\t * We do not check sig_kernel_stop(signr) but set this marker\n\t * unconditionally because we do not know whether debugger will": "static int ptrace_signal(int signr, kernel_siginfo_t *info, enum pid_type type)\n{\n\t/*\n\t * We do not check sig_kernel_stop(signr) but set this marker\n\t * unconditionally because we do not know whether debugger will\n\t * change signr. This flag has no meaning unless we are going\n\t * to stop after return from ptrace_stop(). In this case it will\n\t * be checked in do_signal_stop(), we should only stop if it was\n\t * not cleared by SIGCONT while we were sleeping. See also the\n\t * comment in dequeue_signal().\n\t */\n\tcurrent->jobctl |= JOBCTL_STOP_DEQUEUED;\n\tsignr = ptrace_stop(signr, CLD_TRAPPED, 0, info);\n\n\t/* We're back.  Did the debugger cancel the sig?  */\n\tif (signr == 0)\n\t\treturn signr;\n\n\t/*\n\t * Update the siginfo structure if the signal has\n\t * changed.  If the debugger wanted something\n\t * specific in the siginfo structure then it should\n\t * have updated *info via PTRACE_SETSIGINFO.\n\t */\n\tif (signr != info->si_signo) {\n\t\tclear_siginfo(info);\n\t\tinfo->si_signo = signr;\n\t\tinfo->si_errno = 0;\n\t\tinfo->si_code = SI_USER;\n\t\trcu_read_lock();\n\t\tinfo->si_pid = task_pid_vnr(current->parent);\n\t\tinfo->si_uid = from_kuid_munged(current_user_ns(),\n\t\t\t\t\t\ttask_uid(current->parent));\n\t\trcu_read_unlock();\n\t}\n\n\t/* If the (new) signal is now blocked, requeue it.  */\n\tif (sigismember(&current->blocked, signr) ||\n\t    fatal_signal_pending(current)) {\n\t\tsend_signal_locked(signr, info, current, type);\n\t\tsignr = 0;\n\t}\n\n\treturn signr;\n}",
        "static void smc_llc_process_srv_delete_link(struct smc_link_group *lgr)\n{\n\tstruct smc_llc_msg_del_link *del_llc;\n\tstruct smc_link *lnk, *lnk_del;\n\tstruct smc_llc_qentry *qentry;": "static void smc_llc_process_srv_delete_link(struct smc_link_group *lgr)\n{\n\tstruct smc_llc_msg_del_link *del_llc;\n\tstruct smc_link *lnk, *lnk_del;\n\tstruct smc_llc_qentry *qentry;\n\tint active_links;\n\tint i;\n\n\tmutex_lock(&lgr->llc_conf_mutex);\n\tqentry = smc_llc_flow_qentry_clr(&lgr->llc_flow_lcl);\n\tlnk = qentry->link;\n\tdel_llc = &qentry->msg.delete_link;\n\n\tif (qentry->msg.delete_link.hd.flags & SMC_LLC_FLAG_DEL_LINK_ALL) {\n\t\t/* delete entire lgr */\n\t\tsmc_llc_send_link_delete_all(lgr, true, ntohl(\n\t\t\t\t\t      qentry->msg.delete_link.reason));\n\t\tsmc_lgr_terminate_sched(lgr);\n\t\tgoto out;\n\t}\n\t/* delete single link */\n\tlnk_del = NULL;\n\tfor (i = 0; i < SMC_LINKS_PER_LGR_MAX; i++) {\n\t\tif (lgr->lnk[i].link_id == del_llc->link_num) {\n\t\t\tlnk_del = &lgr->lnk[i];\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (!lnk_del)\n\t\tgoto out; /* asymmetric link already deleted */\n\n\tif (smc_link_downing(&lnk_del->state)) {\n\t\tif (smc_switch_conns(lgr, lnk_del, false))\n\t\t\tsmc_wr_tx_wait_no_pending_sends(lnk_del);\n\t}\n\tif (!list_empty(&lgr->list)) {\n\t\t/* qentry is either a request from peer (send it back to\n\t\t * initiate the DELETE_LINK processing), or a locally\n\t\t * enqueued DELETE_LINK request (forward it)\n\t\t */\n\t\tif (!smc_llc_send_message(lnk, &qentry->msg)) {\n\t\t\tstruct smc_llc_qentry *qentry2;\n\n\t\t\tqentry2 = smc_llc_wait(lgr, lnk, SMC_LLC_WAIT_TIME,\n\t\t\t\t\t       SMC_LLC_DELETE_LINK);\n\t\t\tif (qentry2)\n\t\t\t\tsmc_llc_flow_qentry_del(&lgr->llc_flow_lcl);\n\t\t}\n\t}\n\tsmcr_link_clear(lnk_del, true);\n\n\tactive_links = smc_llc_active_link_count(lgr);\n\tif (active_links == 1) {\n\t\tsmcr_lgr_set_type(lgr, SMC_LGR_SINGLE);\n\t} else if (!active_links) {\n\t\tsmcr_lgr_set_type(lgr, SMC_LGR_NONE);\n\t\tsmc_lgr_terminate_sched(lgr);\n\t}\n\n\tif (lgr->type == SMC_LGR_SINGLE && !list_empty(&lgr->list)) {\n\t\t/* trigger setup of asymm alt link */\n\t\tsmc_llc_add_link_local(lnk);\n\t}\nout:\n\tmutex_unlock(&lgr->llc_conf_mutex);\n\tkfree(qentry);\n}",
        "static void sbz_connect_streams(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);": "static void sbz_connect_streams(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tmutex_lock(&spec->chipio_mutex);\n\n\tcodec_dbg(codec, \"Connect Streams entered, mutex locked and loaded.\\n\");\n\n\t/* This value is 0x43 for 96khz, and 0x83 for 192khz. */\n\tchipio_write_no_mutex(codec, 0x18a020, 0x00000043);\n\n\t/* Setup stream 0x14 with it's source and destination points */\n\tchipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);\n\tchipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);\n\tchipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);\n\tchipio_set_stream_channels(codec, 0x14, 2);\n\tchipio_set_stream_control(codec, 0x14, 1);\n\n\tcodec_dbg(codec, \"Connect Streams exited, mutex released.\\n\");\n\n\tmutex_unlock(&spec->chipio_mutex);\n}",
        "static void spell_word(struct vc_data *vc)\n{\n\tstatic char const *delay_str[] = { \"\", \",\", \".\", \". .\", \". . .\" };\n\tu16 *cp = buf;\n\tchar *cp1;": "static void spell_word(struct vc_data *vc)\n{\n\tstatic char const *delay_str[] = { \"\", \",\", \".\", \". .\", \". . .\" };\n\tu16 *cp = buf;\n\tchar *cp1;\n\tchar *str_cap = spk_str_caps_stop;\n\tchar *last_cap = spk_str_caps_stop;\n\tstruct var_t *direct = spk_get_var(DIRECT);\n\tu16 ch;\n\n\tif (!get_word(vc))\n\t\treturn;\n\twhile ((ch = *cp)) {\n\t\tif (cp != buf)\n\t\t\tsynth_printf(\" %s \", delay_str[spk_spell_delay]);\n\t\t/* FIXME: Non-latin1 considered as lower case */\n\t\tif (ch < 0x100 && IS_CHAR(ch, B_CAP)) {\n\t\t\tstr_cap = spk_str_caps_start;\n\t\t\tif (*spk_str_caps_stop)\n\t\t\t\tspk_pitch_shift++;\n\t\t\telse\t/* synth has no pitch */\n\t\t\t\tlast_cap = spk_str_caps_stop;\n\t\t} else {\n\t\t\tstr_cap = spk_str_caps_stop;\n\t\t}\n\t\tif (str_cap != last_cap) {\n\t\t\tsynth_printf(\"%s\", str_cap);\n\t\t\tlast_cap = str_cap;\n\t\t}\n\t\tif (ch >= 0x100 || (direct && direct->u.n.value)) {\n\t\t\tsynth_putwc_s(ch);\n\t\t} else if (this_speakup_key == SPELL_PHONETIC &&\n\t\t    ch <= 0x7f && isalpha(ch)) {\n\t\t\tch &= 0x1f;\n\t\t\tcp1 = phonetic[--ch];\n\t\t\tsynth_printf(\"%s\", cp1);\n\t\t} else {\n\t\t\tcp1 = spk_characters[ch];\n\t\t\tif (*cp1 == '^') {\n\t\t\t\tsynth_printf(\"%s\", spk_msg_get(MSG_CTRL));\n\t\t\t\tcp1++;\n\t\t\t}\n\t\t\tsynth_printf(\"%s\", cp1);\n\t\t}\n\t\tcp++;\n\t}\n\tif (str_cap != spk_str_caps_stop)\n\t\tsynth_printf(\"%s\", spk_str_caps_stop);\n}",
        "static int create_sort_keys(struct hist_trigger_data *hist_data)\n{\n\tstruct trace_array *tr = hist_data->event_file->tr;\n\tchar *fields_str = hist_data->attrs->sort_key_str;\n\tstruct tracing_map_sort_key *sort_key;": "static int create_sort_keys(struct hist_trigger_data *hist_data)\n{\n\tstruct trace_array *tr = hist_data->event_file->tr;\n\tchar *fields_str = hist_data->attrs->sort_key_str;\n\tstruct tracing_map_sort_key *sort_key;\n\tint descending, ret = 0;\n\tunsigned int i, j, k;\n\n\thist_data->n_sort_keys = 1; /* we always have at least one, hitcount */\n\n\tif (!fields_str)\n\t\tgoto out;\n\n\tfor (i = 0; i < TRACING_MAP_SORT_KEYS_MAX; i++) {\n\t\tstruct hist_field *hist_field;\n\t\tchar *field_str, *field_name;\n\t\tconst char *test_name;\n\n\t\tsort_key = &hist_data->sort_keys[i];\n\n\t\tfield_str = strsep(&fields_str, \",\");\n\t\tif (!field_str)\n\t\t\tbreak;\n\n\t\tif (!*field_str) {\n\t\t\tret = -EINVAL;\n\t\t\thist_err(tr, HIST_ERR_EMPTY_SORT_FIELD, errpos(\"sort=\"));\n\t\t\tbreak;\n\t\t}\n\n\t\tif ((i == TRACING_MAP_SORT_KEYS_MAX - 1) && fields_str) {\n\t\t\thist_err(tr, HIST_ERR_TOO_MANY_SORT_FIELDS, errpos(\"sort=\"));\n\t\t\tret = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\n\t\tfield_name = strsep(&field_str, \".\");\n\t\tif (!field_name || !*field_name) {\n\t\t\tret = -EINVAL;\n\t\t\thist_err(tr, HIST_ERR_EMPTY_SORT_FIELD, errpos(\"sort=\"));\n\t\t\tbreak;\n\t\t}\n\n\t\tif (strcmp(field_name, \"hitcount\") == 0) {\n\t\t\tdescending = is_descending(tr, field_str);\n\t\t\tif (descending < 0) {\n\t\t\t\tret = descending;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tsort_key->descending = descending;\n\t\t\tcontinue;\n\t\t}\n\n\t\tfor (j = 1, k = 1; j < hist_data->n_fields; j++) {\n\t\t\tunsigned int idx;\n\n\t\t\thist_field = hist_data->fields[j];\n\t\t\tif (hist_field->flags & HIST_FIELD_FL_VAR)\n\t\t\t\tcontinue;\n\n\t\t\tidx = k++;\n\n\t\t\ttest_name = hist_field_name(hist_field, 0);\n\n\t\t\tif (strcmp(field_name, test_name) == 0) {\n\t\t\t\tsort_key->field_idx = idx;\n\t\t\t\tdescending = is_descending(tr, field_str);\n\t\t\t\tif (descending < 0) {\n\t\t\t\t\tret = descending;\n\t\t\t\t\tgoto out;\n\t\t\t\t}\n\t\t\t\tsort_key->descending = descending;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (j == hist_data->n_fields) {\n\t\t\tret = -EINVAL;\n\t\t\thist_err(tr, HIST_ERR_INVALID_SORT_FIELD, errpos(field_name));\n\t\t\tbreak;\n\t\t}\n\t}\n\n\thist_data->n_sort_keys = i;\n out:\n\treturn ret;\n}",
        "static int t7xx_dpmaif_config_dlq_hw(struct dpmaif_hw_info *hw_info)\n{\n\tstruct dpmaif_dl *dl_que;\n\tint ret;\n": "static int t7xx_dpmaif_config_dlq_hw(struct dpmaif_hw_info *hw_info)\n{\n\tstruct dpmaif_dl *dl_que;\n\tint ret;\n\n\tt7xx_dpmaif_dl_dlq_hpc_hw_init(hw_info);\n\n\tdl_que = &hw_info->dl_que[0]; /* All queues share one BAT/frag BAT table */\n\tif (!dl_que->que_started)\n\t\treturn -EBUSY;\n\n\tt7xx_dpmaif_dl_set_ao_remain_minsz(hw_info);\n\tt7xx_dpmaif_dl_set_ao_bat_bufsz(hw_info);\n\tt7xx_dpmaif_dl_set_ao_frg_bufsz(hw_info);\n\tt7xx_dpmaif_dl_set_ao_bat_rsv_length(hw_info);\n\tt7xx_dpmaif_dl_set_ao_bid_maxcnt(hw_info);\n\tt7xx_dpmaif_dl_set_pkt_alignment(hw_info);\n\tt7xx_dpmaif_dl_set_pit_seqnum(hw_info);\n\tt7xx_dpmaif_dl_set_ao_mtu(hw_info);\n\tt7xx_dpmaif_dl_set_ao_pit_chknum(hw_info);\n\tt7xx_dpmaif_dl_set_ao_bat_check_thres(hw_info);\n\tt7xx_dpmaif_dl_set_ao_frg_check_thres(hw_info);\n\tt7xx_dpmaif_dl_frg_ao_en(hw_info, true);\n\n\tt7xx_dpmaif_dl_set_bat_base_addr(hw_info, dl_que->frg_base);\n\tt7xx_dpmaif_dl_set_bat_size(hw_info, dl_que->frg_size_cnt);\n\tt7xx_dpmaif_dl_bat_en(hw_info, true);\n\n\tret = t7xx_dpmaif_dl_bat_init_done(hw_info, true);\n\tif (ret)\n\t\treturn ret;\n\n\tt7xx_dpmaif_dl_set_bat_base_addr(hw_info, dl_que->bat_base);\n\tt7xx_dpmaif_dl_set_bat_size(hw_info, dl_que->bat_size_cnt);\n\tt7xx_dpmaif_dl_bat_en(hw_info, false);\n\n\tret = t7xx_dpmaif_dl_bat_init_done(hw_info, false);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Init PIT (two PIT table) */\n\tt7xx_dpmaif_config_all_dlq_hw(hw_info);\n\tt7xx_dpmaif_dl_all_q_en(hw_info, true);\n\tt7xx_dpmaif_dl_set_pkt_checksum(hw_info);\n\treturn 0;\n}",
        "static int __hwrm_send(struct bnxt *bp, struct bnxt_hwrm_ctx *ctx)\n{\n\tu32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;\n\tenum bnxt_hwrm_chnl dst = BNXT_HWRM_CHNL_CHIMP;\n\tu32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;": "static int __hwrm_send(struct bnxt *bp, struct bnxt_hwrm_ctx *ctx)\n{\n\tu32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;\n\tenum bnxt_hwrm_chnl dst = BNXT_HWRM_CHNL_CHIMP;\n\tu32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;\n\tstruct bnxt_hwrm_wait_token *token = NULL;\n\tstruct hwrm_short_input short_input = {0};\n\tu16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;\n\tunsigned int i, timeout, tmo_count;\n\tu32 *data = (u32 *)ctx->req;\n\tu32 msg_len = ctx->req_len;\n\tu32 req_type, sts;\n\tint rc = -EBUSY;\n\tu16 len = 0;\n\tu8 *valid;\n\n\tif (ctx->flags & BNXT_HWRM_INTERNAL_RESP_DIRTY)\n\t\tmemset(ctx->resp, 0, PAGE_SIZE);\n\n\treq_type = le16_to_cpu(ctx->req->req_type);\n\tif (BNXT_NO_FW_ACCESS(bp) && req_type != HWRM_FUNC_RESET) {\n\t\tnetdev_dbg(bp->dev, \"hwrm req_type 0x%x skipped, FW channel down\\n\",\n\t\t\t   req_type);\n\t\tgoto exit;\n\t}\n\n\tif (msg_len > BNXT_HWRM_MAX_REQ_LEN &&\n\t    msg_len > bp->hwrm_max_ext_req_len) {\n\t\trc = -E2BIG;\n\t\tgoto exit;\n\t}\n\n\tif (bnxt_kong_hwrm_message(bp, ctx->req)) {\n\t\tdst = BNXT_HWRM_CHNL_KONG;\n\t\tbar_offset = BNXT_GRCPF_REG_KONG_COMM;\n\t\tdoorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;\n\t\tif (le16_to_cpu(ctx->req->cmpl_ring) != INVALID_HW_RING_ID) {\n\t\t\tnetdev_err(bp->dev, \"Ring completions not supported for KONG commands, req_type = %d\\n\",\n\t\t\t\t   req_type);\n\t\t\trc = -EINVAL;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\ttoken = __hwrm_acquire_token(bp, dst);\n\tif (!token) {\n\t\trc = -ENOMEM;\n\t\tgoto exit;\n\t}\n\tctx->req->seq_id = cpu_to_le16(token->seq_id);\n\n\tif ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||\n\t    msg_len > BNXT_HWRM_MAX_REQ_LEN) {\n\t\tshort_input.req_type = ctx->req->req_type;\n\t\tshort_input.signature =\n\t\t\t\tcpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);\n\t\tshort_input.size = cpu_to_le16(msg_len);\n\t\tshort_input.req_addr = cpu_to_le64(ctx->dma_handle);\n\n\t\tdata = (u32 *)&short_input;\n\t\tmsg_len = sizeof(short_input);\n\n\t\tmax_req_len = BNXT_HWRM_SHORT_REQ_LEN;\n\t}\n\n\t/* Ensure any associated DMA buffers are written before doorbell */\n\twmb();\n\n\t/* Write request msg to hwrm channel */\n\t__iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);\n\n\tfor (i = msg_len; i < max_req_len; i += 4)\n\t\twritel(0, bp->bar0 + bar_offset + i);\n\n\t/* Ring channel doorbell */\n\twritel(1, bp->bar0 + doorbell_offset);\n\n\thwrm_req_dbg(bp, ctx->req);\n\n\tif (!pci_is_enabled(bp->pdev)) {\n\t\trc = -ENODEV;\n\t\tgoto exit;\n\t}\n\n\t/* Limit timeout to an upper limit */\n\ttimeout = min(ctx->timeout, bp->hwrm_cmd_max_timeout ?: HWRM_CMD_MAX_TIMEOUT);\n\t/* convert timeout to usec */\n\ttimeout *= 1000;\n\n\ti = 0;\n\t/* Short timeout for the first few iterations:\n\t * number of loops = number of loops for short timeout +\n\t * number of loops for standard timeout.\n\t */\n\ttmo_count = HWRM_SHORT_TIMEOUT_COUNTER;\n\ttimeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;\n\ttmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);\n\n\tif (le16_to_cpu(ctx->req->cmpl_ring) != INVALID_HW_RING_ID) {\n\t\t/* Wait until hwrm response cmpl interrupt is processed */\n\t\twhile (READ_ONCE(token->state) < BNXT_HWRM_COMPLETE &&\n\t\t       i++ < tmo_count) {\n\t\t\t/* Abort the wait for completion if the FW health\n\t\t\t * check has failed.\n\t\t\t */\n\t\t\tif (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))\n\t\t\t\tgoto exit;\n\t\t\t/* on first few passes, just barely sleep */\n\t\t\tif (i < HWRM_SHORT_TIMEOUT_COUNTER) {\n\t\t\t\tusleep_range(HWRM_SHORT_MIN_TIMEOUT,\n\t\t\t\t\t     HWRM_SHORT_MAX_TIMEOUT);\n\t\t\t} else {\n\t\t\t\tif (hwrm_wait_must_abort(bp, req_type, &sts)) {\n\t\t\t\t\thwrm_err(bp, ctx, \"Resp cmpl intr abandoning msg: 0x%x due to firmware status: 0x%x\\n\",\n\t\t\t\t\t\t req_type, sts);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tusleep_range(HWRM_MIN_TIMEOUT,\n\t\t\t\t\t     HWRM_MAX_TIMEOUT);\n\t\t\t}\n\t\t}\n\n\t\tif (READ_ONCE(token->state) != BNXT_HWRM_COMPLETE) {\n\t\t\thwrm_err(bp, ctx, \"Resp cmpl intr err msg: 0x%x\\n\",\n\t\t\t\t req_type);\n\t\t\tgoto exit;\n\t\t}\n\t\tlen = le16_to_cpu(READ_ONCE(ctx->resp->resp_len));\n\t\tvalid = ((u8 *)ctx->resp) + len - 1;\n\t} else {\n\t\t__le16 seen_out_of_seq = ctx->req->seq_id; /* will never see */\n\t\tint j;\n\n\t\t/* Check if response len is updated */\n\t\tfor (i = 0; i < tmo_count; i++) {\n\t\t\t/* Abort the wait for completion if the FW health\n\t\t\t * check has failed.\n\t\t\t */\n\t\t\tif (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))\n\t\t\t\tgoto exit;\n\n\t\t\tif (token &&\n\t\t\t    READ_ONCE(token->state) == BNXT_HWRM_DEFERRED) {\n\t\t\t\t__hwrm_release_token(bp, token);\n\t\t\t\ttoken = NULL;\n\t\t\t}\n\n\t\t\tlen = le16_to_cpu(READ_ONCE(ctx->resp->resp_len));\n\t\t\tif (len) {\n\t\t\t\t__le16 resp_seq = READ_ONCE(ctx->resp->seq_id);\n\n\t\t\t\tif (resp_seq == ctx->req->seq_id)\n\t\t\t\t\tbreak;\n\t\t\t\tif (resp_seq != seen_out_of_seq) {\n\t\t\t\t\tnetdev_warn(bp->dev, \"Discarding out of seq response: 0x%x for msg {0x%x 0x%x}\\n\",\n\t\t\t\t\t\t    le16_to_cpu(resp_seq),\n\t\t\t\t\t\t    req_type,\n\t\t\t\t\t\t    le16_to_cpu(ctx->req->seq_id));\n\t\t\t\t\tseen_out_of_seq = resp_seq;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* on first few passes, just barely sleep */\n\t\t\tif (i < HWRM_SHORT_TIMEOUT_COUNTER) {\n\t\t\t\tusleep_range(HWRM_SHORT_MIN_TIMEOUT,\n\t\t\t\t\t     HWRM_SHORT_MAX_TIMEOUT);\n\t\t\t} else {\n\t\t\t\tif (hwrm_wait_must_abort(bp, req_type, &sts)) {\n\t\t\t\t\thwrm_err(bp, ctx, \"Abandoning msg {0x%x 0x%x} len: %d due to firmware status: 0x%x\\n\",\n\t\t\t\t\t\t req_type,\n\t\t\t\t\t\t le16_to_cpu(ctx->req->seq_id),\n\t\t\t\t\t\t len, sts);\n\t\t\t\t\tgoto exit;\n\t\t\t\t}\n\t\t\t\tusleep_range(HWRM_MIN_TIMEOUT,\n\t\t\t\t\t     HWRM_MAX_TIMEOUT);\n\t\t\t}\n\t\t}\n\n\t\tif (i >= tmo_count) {\n\t\t\thwrm_err(bp, ctx, \"Error (timeout: %u) msg {0x%x 0x%x} len:%d\\n\",\n\t\t\t\t hwrm_total_timeout(i), req_type,\n\t\t\t\t le16_to_cpu(ctx->req->seq_id), len);\n\t\t\tgoto exit;\n\t\t}\n\n\t\t/* Last byte of resp contains valid bit */\n\t\tvalid = ((u8 *)ctx->resp) + len - 1;\n\t\tfor (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; ) {\n\t\t\t/* make sure we read from updated DMA memory */\n\t\t\tdma_rmb();\n\t\t\tif (*valid)\n\t\t\t\tbreak;\n\t\t\tif (j < 10) {\n\t\t\t\tudelay(1);\n\t\t\t\tj++;\n\t\t\t} else {\n\t\t\t\tusleep_range(20, 30);\n\t\t\t\tj += 20;\n\t\t\t}\n\t\t}\n\n\t\tif (j >= HWRM_VALID_BIT_DELAY_USEC) {\n\t\t\thwrm_err(bp, ctx, \"Error (timeout: %u) msg {0x%x 0x%x} len:%d v:%d\\n\",\n\t\t\t\t hwrm_total_timeout(i) + j, req_type,\n\t\t\t\t le16_to_cpu(ctx->req->seq_id), len, *valid);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t/* Zero valid bit for compatibility.  Valid bit in an older spec\n\t * may become a new field in a newer spec.  We must make sure that\n\t * a new field not implemented by old spec will read zero.\n\t */\n\t*valid = 0;\n\trc = le16_to_cpu(ctx->resp->error_code);\n\tif (rc == HWRM_ERR_CODE_BUSY && !(ctx->flags & BNXT_HWRM_CTX_SILENT))\n\t\tnetdev_warn(bp->dev, \"FW returned busy, hwrm req_type 0x%x\\n\",\n\t\t\t    req_type);\n\telse if (rc && rc != HWRM_ERR_CODE_PF_UNAVAILABLE)\n\t\thwrm_err(bp, ctx, \"hwrm req_type 0x%x seq id 0x%x error 0x%x\\n\",\n\t\t\t req_type, token->seq_id, rc);\n\trc = __hwrm_to_stderr(rc);\nexit:\n\tif (token)\n\t\t__hwrm_release_token(bp, token);\n\tif (ctx->flags & BNXT_HWRM_INTERNAL_CTX_OWNED)\n\t\tctx->flags |= BNXT_HWRM_INTERNAL_RESP_DIRTY;\n\telse\n\t\t__hwrm_ctx_drop(bp, ctx);\n\treturn rc;\n}",
        "static inline u16 INFTL_findwriteunit(struct INFTLrecord *inftl, unsigned block)\n{\n\tunsigned int thisVUC = block / (inftl->EraseSize / SECTORSIZE);\n\tunsigned int thisEUN, writeEUN, prev_block, status;\n\tunsigned long blockofs = (block * SECTORSIZE) & (inftl->EraseSize -1);": "static inline u16 INFTL_findwriteunit(struct INFTLrecord *inftl, unsigned block)\n{\n\tunsigned int thisVUC = block / (inftl->EraseSize / SECTORSIZE);\n\tunsigned int thisEUN, writeEUN, prev_block, status;\n\tunsigned long blockofs = (block * SECTORSIZE) & (inftl->EraseSize -1);\n\tstruct mtd_info *mtd = inftl->mbd.mtd;\n\tstruct inftl_oob oob;\n\tstruct inftl_bci bci;\n\tunsigned char anac, nacs, parity;\n\tsize_t retlen;\n\tint silly, silly2 = 3;\n\n\tpr_debug(\"INFTL: INFTL_findwriteunit(inftl=%p,block=%d)\\n\",\n\t\t\tinftl, block);\n\n\tdo {\n\t\t/*\n\t\t * Scan the media to find a unit in the VUC which has\n\t\t * a free space for the block in question.\n\t\t */\n\t\twriteEUN = BLOCK_NIL;\n\t\tthisEUN = inftl->VUtable[thisVUC];\n\t\tsilly = MAX_LOOPS;\n\n\t\twhile (thisEUN <= inftl->lastEUN) {\n\t\t\tinftl_read_oob(mtd, (thisEUN * inftl->EraseSize) +\n\t\t\t\t       blockofs, 8, &retlen, (char *)&bci);\n\n\t\t\tstatus = bci.Status | bci.Status1;\n\t\t\tpr_debug(\"INFTL: status of block %d in EUN %d is %x\\n\",\n\t\t\t\t\tblock , writeEUN, status);\n\n\t\t\tswitch(status) {\n\t\t\tcase SECTOR_FREE:\n\t\t\t\twriteEUN = thisEUN;\n\t\t\t\tbreak;\n\t\t\tcase SECTOR_DELETED:\n\t\t\tcase SECTOR_USED:\n\t\t\t\t/* Can't go any further */\n\t\t\t\tgoto hitused;\n\t\t\tcase SECTOR_IGNORE:\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\t/*\n\t\t\t\t * Invalid block. Don't use it any more.\n\t\t\t\t * Must implement.\n\t\t\t\t */\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (!silly--) {\n\t\t\t\tprintk(KERN_WARNING \"INFTL: infinite loop in \"\n\t\t\t\t\t\"Virtual Unit Chain 0x%x\\n\", thisVUC);\n\t\t\t\treturn BLOCK_NIL;\n\t\t\t}\n\n\t\t\t/* Skip to next block in chain */\n\t\t\tthisEUN = inftl->PUtable[thisEUN];\n\t\t}\n\nhitused:\n\t\tif (writeEUN != BLOCK_NIL)\n\t\t\treturn writeEUN;\n\n\n\t\t/*\n\t\t * OK. We didn't find one in the existing chain, or there\n\t\t * is no existing chain. Allocate a new one.\n\t\t */\n\t\twriteEUN = INFTL_findfreeblock(inftl, 0);\n\n\t\tif (writeEUN == BLOCK_NIL) {\n\t\t\t/*\n\t\t\t * That didn't work - there were no free blocks just\n\t\t\t * waiting to be picked up. We're going to have to fold\n\t\t\t * a chain to make room.\n\t\t\t */\n\t\t\tthisEUN = INFTL_makefreeblock(inftl, block);\n\n\t\t\t/*\n\t\t\t * Hopefully we free something, lets try again.\n\t\t\t * This time we are desperate...\n\t\t\t */\n\t\t\tpr_debug(\"INFTL: using desperate==1 to find free EUN \"\n\t\t\t\t\t\"to accommodate write to VUC %d\\n\",\n\t\t\t\t\tthisVUC);\n\t\t\twriteEUN = INFTL_findfreeblock(inftl, 1);\n\t\t\tif (writeEUN == BLOCK_NIL) {\n\t\t\t\t/*\n\t\t\t\t * Ouch. This should never happen - we should\n\t\t\t\t * always be able to make some room somehow.\n\t\t\t\t * If we get here, we've allocated more storage\n\t\t\t\t * space than actual media, or our makefreeblock\n\t\t\t\t * routine is missing something.\n\t\t\t\t */\n\t\t\t\tprintk(KERN_WARNING \"INFTL: cannot make free \"\n\t\t\t\t\t\"space.\\n\");\n#ifdef DEBUG\n\t\t\t\tINFTL_dumptables(inftl);\n\t\t\t\tINFTL_dumpVUchains(inftl);\n#endif\n\t\t\t\treturn BLOCK_NIL;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * Insert new block into virtual chain. Firstly update the\n\t\t * block headers in flash...\n\t\t */\n\t\tanac = 0;\n\t\tnacs = 0;\n\t\tthisEUN = inftl->VUtable[thisVUC];\n\t\tif (thisEUN != BLOCK_NIL) {\n\t\t\tinftl_read_oob(mtd, thisEUN * inftl->EraseSize\n\t\t\t\t       + 8, 8, &retlen, (char *)&oob.u);\n\t\t\tanac = oob.u.a.ANAC + 1;\n\t\t\tnacs = oob.u.a.NACs + 1;\n\t\t}\n\n\t\tprev_block = inftl->VUtable[thisVUC];\n\t\tif (prev_block < inftl->nb_blocks)\n\t\t\tprev_block -= inftl->firstEUN;\n\n\t\tparity = (nrbits(thisVUC, 16) & 0x1) ? 0x1 : 0;\n\t\tparity |= (nrbits(prev_block, 16) & 0x1) ? 0x2 : 0;\n\t\tparity |= (nrbits(anac, 8) & 0x1) ? 0x4 : 0;\n\t\tparity |= (nrbits(nacs, 8) & 0x1) ? 0x8 : 0;\n\n\t\toob.u.a.virtualUnitNo = cpu_to_le16(thisVUC);\n\t\toob.u.a.prevUnitNo = cpu_to_le16(prev_block);\n\t\toob.u.a.ANAC = anac;\n\t\toob.u.a.NACs = nacs;\n\t\toob.u.a.parityPerField = parity;\n\t\toob.u.a.discarded = 0xaa;\n\n\t\tinftl_write_oob(mtd, writeEUN * inftl->EraseSize + 8, 8,\n\t\t\t\t&retlen, (char *)&oob.u);\n\n\t\t/* Also back up header... */\n\t\toob.u.b.virtualUnitNo = cpu_to_le16(thisVUC);\n\t\toob.u.b.prevUnitNo = cpu_to_le16(prev_block);\n\t\toob.u.b.ANAC = anac;\n\t\toob.u.b.NACs = nacs;\n\t\toob.u.b.parityPerField = parity;\n\t\toob.u.b.discarded = 0xaa;\n\n\t\tinftl_write_oob(mtd, writeEUN * inftl->EraseSize +\n\t\t\t\tSECTORSIZE * 4 + 8, 8, &retlen, (char *)&oob.u);\n\n\t\tinftl->PUtable[writeEUN] = inftl->VUtable[thisVUC];\n\t\tinftl->VUtable[thisVUC] = writeEUN;\n\n\t\tinftl->numfreeEUNs--;\n\t\treturn writeEUN;\n\n\t} while (silly2--);\n\n\tprintk(KERN_WARNING \"INFTL: error folding to make room for Virtual \"\n\t\t\"Unit Chain 0x%x\\n\", thisVUC);\n\treturn BLOCK_NIL;\n}",
        "static void bfq_bfqq_end_wr(struct bfq_queue *bfqq)\n{\n\t/*\n\t * If bfqq has been enjoying interactive weight-raising, then\n\t * reset soft_rt_next_start. We do it for the following": "static void bfq_bfqq_end_wr(struct bfq_queue *bfqq)\n{\n\t/*\n\t * If bfqq has been enjoying interactive weight-raising, then\n\t * reset soft_rt_next_start. We do it for the following\n\t * reason. bfqq may have been conveying the I/O needed to load\n\t * a soft real-time application. Such an application actually\n\t * exhibits a soft real-time I/O pattern after it finishes\n\t * loading, and finally starts doing its job. But, if bfqq has\n\t * been receiving a lot of bandwidth so far (likely to happen\n\t * on a fast device), then soft_rt_next_start now contains a\n\t * high value that. So, without this reset, bfqq would be\n\t * prevented from being possibly considered as soft_rt for a\n\t * very long time.\n\t */\n\n\tif (bfqq->wr_cur_max_time !=\n\t    bfqq->bfqd->bfq_wr_rt_max_time)\n\t\tbfqq->soft_rt_next_start = jiffies;\n\n\tif (bfq_bfqq_busy(bfqq))\n\t\tbfqq->bfqd->wr_busy_queues--;\n\tbfqq->wr_coeff = 1;\n\tbfqq->wr_cur_max_time = 0;\n\tbfqq->last_wr_start_finish = jiffies;\n\t/*\n\t * Trigger a weight change on the next invocation of\n\t * __bfq_entity_update_weight_prio.\n\t */\n\tbfqq->entity.prio_changed = 1;\n}",
        "static void init_adb_hdrs(struct vpe_ctx *ctx)\n{\n\tVPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);\n\tVPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);\n\tVPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);": "static void init_adb_hdrs(struct vpe_ctx *ctx)\n{\n\tVPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);\n\tVPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);\n\tVPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);\n\tVPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);\n\tVPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);\n\tVPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,\n\t\tGET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));\n\tVPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,\n\t\tGET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));\n\tVPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,\n\t\tGET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));\n\tVPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,\n\t\tGET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));\n};\n\n/*\n * Allocate or re-allocate the motion vector DMA buffers\n * There are two buffers, one for input and one for output.\n * However, the roles are reversed after each field is processed.\n * In other words, after each field is processed, the previous\n * output (dst) MV buffer becomes the new input (src) MV buffer.\n */\nstatic int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)\n{\n\tstruct device *dev = ctx->dev->v4l2_dev.dev;\n\n\tif (ctx->mv_buf_size == size)\n\t\treturn 0;\n\n\tif (ctx->mv_buf[0])\n\t\tdma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],\n\t\t\tctx->mv_buf_dma[0]);\n\n\tif (ctx->mv_buf[1])\n\t\tdma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],\n\t\t\tctx->mv_buf_dma[1]);\n\n\tif (size == 0)\n\t\treturn 0;\n\n\tctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],\n\t\t\t\tGFP_KERNEL);\n\tif (!ctx->mv_buf[0]) {\n\t\tvpe_err(ctx->dev, \"failed to allocate motion vector buffer\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],\n\t\t\t\tGFP_KERNEL);\n\tif (!ctx->mv_buf[1]) {\n\t\tvpe_err(ctx->dev, \"failed to allocate motion vector buffer\\n\");\n\t\tdma_free_coherent(dev, size, ctx->mv_buf[0],\n\t\t\tctx->mv_buf_dma[0]);\n\n\t\treturn -ENOMEM;\n\t}\n\n\tctx->mv_buf_size = size;\n\tctx->src_mv_buf_selector = 0;\n\n\treturn 0;\n}",
        "static int dbInitDmapCtl(struct dmapctl * dcp, int level, int i)\n{\t\t\t\t/* start leaf index not covered by range */\n\ts8 *cp;\n\n\tdcp->nleafs = cpu_to_le32(LPERCTL);": "static int dbInitDmapCtl(struct dmapctl * dcp, int level, int i)\n{\t\t\t\t/* start leaf index not covered by range */\n\ts8 *cp;\n\n\tdcp->nleafs = cpu_to_le32(LPERCTL);\n\tdcp->l2nleafs = cpu_to_le32(L2LPERCTL);\n\tdcp->leafidx = cpu_to_le32(CTLLEAFIND);\n\tdcp->height = cpu_to_le32(5);\n\tdcp->budmin = L2BPERDMAP + L2LPERCTL * level;\n\n\t/*\n\t * initialize the leaves of current level that were not covered\n\t * by the specified input block range (i.e. the leaves have no\n\t * low level dmapctl or dmap).\n\t */\n\tcp = &dcp->stree[CTLLEAFIND + i];\n\tfor (; i < LPERCTL; i++)\n\t\t*cp++ = NOFREE;\n\n\t/* build the dmap's binary buddy summary tree */\n\treturn (dbInitTree((struct dmaptree *) dcp));\n}",
        "static inline void __lru_add_drain_all(bool force_all_cpus)\n{\n\t/*\n\t * lru_drain_gen - Global pages generation number\n\t *": "static inline void __lru_add_drain_all(bool force_all_cpus)\n{\n\t/*\n\t * lru_drain_gen - Global pages generation number\n\t *\n\t * (A) Definition: global lru_drain_gen = x implies that all generations\n\t *     0 < n <= x are already *scheduled* for draining.\n\t *\n\t * This is an optimization for the highly-contended use case where a\n\t * user space workload keeps constantly generating a flow of pages for\n\t * each CPU.\n\t */\n\tstatic unsigned int lru_drain_gen;\n\tstatic struct cpumask has_work;\n\tstatic DEFINE_MUTEX(lock);\n\tunsigned cpu, this_gen;\n\n\t/*\n\t * Make sure nobody triggers this path before mm_percpu_wq is fully\n\t * initialized.\n\t */\n\tif (WARN_ON(!mm_percpu_wq))\n\t\treturn;\n\n\t/*\n\t * Guarantee pagevec counter stores visible by this CPU are visible to\n\t * other CPUs before loading the current drain generation.\n\t */\n\tsmp_mb();\n\n\t/*\n\t * (B) Locally cache global LRU draining generation number\n\t *\n\t * The read barrier ensures that the counter is loaded before the mutex\n\t * is taken. It pairs with smp_mb() inside the mutex critical section\n\t * at (D).\n\t */\n\tthis_gen = smp_load_acquire(&lru_drain_gen);\n\n\tmutex_lock(&lock);\n\n\t/*\n\t * (C) Exit the draining operation if a newer generation, from another\n\t * lru_add_drain_all(), was already scheduled for draining. Check (A).\n\t */\n\tif (unlikely(this_gen != lru_drain_gen && !force_all_cpus))\n\t\tgoto done;\n\n\t/*\n\t * (D) Increment global generation number\n\t *\n\t * Pairs with smp_load_acquire() at (B), outside of the critical\n\t * section. Use a full memory barrier to guarantee that the new global\n\t * drain generation number is stored before loading pagevec counters.\n\t *\n\t * This pairing must be done here, before the for_each_online_cpu loop\n\t * below which drains the page vectors.\n\t *\n\t * Let x, y, and z represent some system CPU numbers, where x < y < z.\n\t * Assume CPU #z is in the middle of the for_each_online_cpu loop\n\t * below and has already reached CPU #y's per-cpu data. CPU #x comes\n\t * along, adds some pages to its per-cpu vectors, then calls\n\t * lru_add_drain_all().\n\t *\n\t * If the paired barrier is done at any later step, e.g. after the\n\t * loop, CPU #x will just exit at (C) and miss flushing out all of its\n\t * added pages.\n\t */\n\tWRITE_ONCE(lru_drain_gen, lru_drain_gen + 1);\n\tsmp_mb();\n\n\tcpumask_clear(&has_work);\n\tfor_each_online_cpu(cpu) {\n\t\tstruct work_struct *work = &per_cpu(lru_add_drain_work, cpu);\n\n\t\tif (pagevec_count(&per_cpu(lru_pvecs.lru_add, cpu)) ||\n\t\t    data_race(pagevec_count(&per_cpu(lru_rotate.pvec, cpu))) ||\n\t\t    pagevec_count(&per_cpu(lru_pvecs.lru_deactivate_file, cpu)) ||\n\t\t    pagevec_count(&per_cpu(lru_pvecs.lru_deactivate, cpu)) ||\n\t\t    pagevec_count(&per_cpu(lru_pvecs.lru_lazyfree, cpu)) ||\n\t\t    need_activate_page_drain(cpu) ||\n\t\t    need_mlock_page_drain(cpu) ||\n\t\t    has_bh_in_lru(cpu, NULL)) {\n\t\t\tINIT_WORK(work, lru_add_drain_per_cpu);\n\t\t\tqueue_work_on(cpu, mm_percpu_wq, work);\n\t\t\t__cpumask_set_cpu(cpu, &has_work);\n\t\t}\n\t}\n\n\tfor_each_cpu(cpu, &has_work)\n\t\tflush_work(&per_cpu(lru_add_drain_work, cpu));\n\ndone:\n\tmutex_unlock(&lock);\n}",
        "static void ae5_post_dsp_register_set(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tchipio_8051_write_direct(codec, 0x93, 0x10);": "static void ae5_post_dsp_register_set(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tchipio_8051_write_direct(codec, 0x93, 0x10);\n\tchipio_8051_write_pll_pmu(codec, 0x44, 0xc2);\n\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0x00, spec->mem_base + 0x100);\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0x00, spec->mem_base + 0x100);\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0x00, spec->mem_base + 0x100);\n\twriteb(0xff, spec->mem_base + 0x304);\n\twriteb(0x00, spec->mem_base + 0x100);\n\twriteb(0xff, spec->mem_base + 0x304);\n\n\tca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);\n\tca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);\n\tca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);\n}",
        "static int convert_ctx_accesses(struct bpf_verifier_env *env)\n{\n\tconst struct bpf_verifier_ops *ops = env->ops;\n\tint i, cnt, size, ctx_field_size, delta = 0;\n\tconst int insn_cnt = env->prog->len;": "static int convert_ctx_accesses(struct bpf_verifier_env *env)\n{\n\tconst struct bpf_verifier_ops *ops = env->ops;\n\tint i, cnt, size, ctx_field_size, delta = 0;\n\tconst int insn_cnt = env->prog->len;\n\tstruct bpf_insn insn_buf[16], *insn;\n\tu32 target_size, size_default, off;\n\tstruct bpf_prog *new_prog;\n\tenum bpf_access_type type;\n\tbool is_narrower_load;\n\n\tif (ops->gen_prologue || env->seen_direct_write) {\n\t\tif (!ops->gen_prologue) {\n\t\t\tverbose(env, \"bpf verifier is misconfigured\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tcnt = ops->gen_prologue(insn_buf, env->seen_direct_write,\n\t\t\t\t\tenv->prog);\n\t\tif (cnt >= ARRAY_SIZE(insn_buf)) {\n\t\t\tverbose(env, \"bpf verifier is misconfigured\\n\");\n\t\t\treturn -EINVAL;\n\t\t} else if (cnt) {\n\t\t\tnew_prog = bpf_patch_insn_data(env, 0, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tenv->prog = new_prog;\n\t\t\tdelta += cnt - 1;\n\t\t}\n\t}\n\n\tif (bpf_prog_is_dev_bound(env->prog->aux))\n\t\treturn 0;\n\n\tinsn = env->prog->insnsi + delta;\n\n\tfor (i = 0; i < insn_cnt; i++, insn++) {\n\t\tbpf_convert_ctx_access_t convert_ctx_access;\n\t\tbool ctx_access;\n\n\t\tif (insn->code == (BPF_LDX | BPF_MEM | BPF_B) ||\n\t\t    insn->code == (BPF_LDX | BPF_MEM | BPF_H) ||\n\t\t    insn->code == (BPF_LDX | BPF_MEM | BPF_W) ||\n\t\t    insn->code == (BPF_LDX | BPF_MEM | BPF_DW)) {\n\t\t\ttype = BPF_READ;\n\t\t\tctx_access = true;\n\t\t} else if (insn->code == (BPF_STX | BPF_MEM | BPF_B) ||\n\t\t\t   insn->code == (BPF_STX | BPF_MEM | BPF_H) ||\n\t\t\t   insn->code == (BPF_STX | BPF_MEM | BPF_W) ||\n\t\t\t   insn->code == (BPF_STX | BPF_MEM | BPF_DW) ||\n\t\t\t   insn->code == (BPF_ST | BPF_MEM | BPF_B) ||\n\t\t\t   insn->code == (BPF_ST | BPF_MEM | BPF_H) ||\n\t\t\t   insn->code == (BPF_ST | BPF_MEM | BPF_W) ||\n\t\t\t   insn->code == (BPF_ST | BPF_MEM | BPF_DW)) {\n\t\t\ttype = BPF_WRITE;\n\t\t\tctx_access = BPF_CLASS(insn->code) == BPF_STX;\n\t\t} else {\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (type == BPF_WRITE &&\n\t\t    env->insn_aux_data[i + delta].sanitize_stack_spill) {\n\t\t\tstruct bpf_insn patch[] = {\n\t\t\t\t*insn,\n\t\t\t\tBPF_ST_NOSPEC(),\n\t\t\t};\n\n\t\t\tcnt = ARRAY_SIZE(patch);\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, patch, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (!ctx_access)\n\t\t\tcontinue;\n\n\t\tswitch ((int)env->insn_aux_data[i + delta].ptr_type) {\n\t\tcase PTR_TO_CTX:\n\t\t\tif (!ops->convert_ctx_access)\n\t\t\t\tcontinue;\n\t\t\tconvert_ctx_access = ops->convert_ctx_access;\n\t\t\tbreak;\n\t\tcase PTR_TO_SOCKET:\n\t\tcase PTR_TO_SOCK_COMMON:\n\t\t\tconvert_ctx_access = bpf_sock_convert_ctx_access;\n\t\t\tbreak;\n\t\tcase PTR_TO_TCP_SOCK:\n\t\t\tconvert_ctx_access = bpf_tcp_sock_convert_ctx_access;\n\t\t\tbreak;\n\t\tcase PTR_TO_XDP_SOCK:\n\t\t\tconvert_ctx_access = bpf_xdp_sock_convert_ctx_access;\n\t\t\tbreak;\n\t\tcase PTR_TO_BTF_ID:\n\t\tcase PTR_TO_BTF_ID | PTR_UNTRUSTED:\n\t\t\tif (type == BPF_READ) {\n\t\t\t\tinsn->code = BPF_LDX | BPF_PROBE_MEM |\n\t\t\t\t\tBPF_SIZE((insn)->code);\n\t\t\t\tenv->prog->aux->num_exentries++;\n\t\t\t} else if (resolve_prog_type(env->prog) != BPF_PROG_TYPE_STRUCT_OPS) {\n\t\t\t\tverbose(env, \"Writes through BTF pointers are not allowed\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tcontinue;\n\t\tdefault:\n\t\t\tcontinue;\n\t\t}\n\n\t\tctx_field_size = env->insn_aux_data[i + delta].ctx_field_size;\n\t\tsize = BPF_LDST_BYTES(insn);\n\n\t\t/* If the read access is a narrower load of the field,\n\t\t * convert to a 4/8-byte load, to minimum program type specific\n\t\t * convert_ctx_access changes. If conversion is successful,\n\t\t * we will apply proper mask to the result.\n\t\t */\n\t\tis_narrower_load = size < ctx_field_size;\n\t\tsize_default = bpf_ctx_off_adjust_machine(ctx_field_size);\n\t\toff = insn->off;\n\t\tif (is_narrower_load) {\n\t\t\tu8 size_code;\n\n\t\t\tif (type == BPF_WRITE) {\n\t\t\t\tverbose(env, \"bpf verifier narrow ctx access misconfigured\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tsize_code = BPF_H;\n\t\t\tif (ctx_field_size == 4)\n\t\t\t\tsize_code = BPF_W;\n\t\t\telse if (ctx_field_size == 8)\n\t\t\t\tsize_code = BPF_DW;\n\n\t\t\tinsn->off = off & ~(size_default - 1);\n\t\t\tinsn->code = BPF_LDX | BPF_MEM | size_code;\n\t\t}\n\n\t\ttarget_size = 0;\n\t\tcnt = convert_ctx_access(type, insn, insn_buf, env->prog,\n\t\t\t\t\t &target_size);\n\t\tif (cnt == 0 || cnt >= ARRAY_SIZE(insn_buf) ||\n\t\t    (ctx_field_size && !target_size)) {\n\t\t\tverbose(env, \"bpf verifier is misconfigured\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (is_narrower_load && size < target_size) {\n\t\t\tu8 shift = bpf_ctx_narrow_access_offset(\n\t\t\t\toff, size, size_default) * 8;\n\t\t\tif (shift && cnt + 1 >= ARRAY_SIZE(insn_buf)) {\n\t\t\t\tverbose(env, \"bpf verifier narrow ctx load misconfigured\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tif (ctx_field_size <= 4) {\n\t\t\t\tif (shift)\n\t\t\t\t\tinsn_buf[cnt++] = BPF_ALU32_IMM(BPF_RSH,\n\t\t\t\t\t\t\t\t\tinsn->dst_reg,\n\t\t\t\t\t\t\t\t\tshift);\n\t\t\t\tinsn_buf[cnt++] = BPF_ALU32_IMM(BPF_AND, insn->dst_reg,\n\t\t\t\t\t\t\t\t(1 << size * 8) - 1);\n\t\t\t} else {\n\t\t\t\tif (shift)\n\t\t\t\t\tinsn_buf[cnt++] = BPF_ALU64_IMM(BPF_RSH,\n\t\t\t\t\t\t\t\t\tinsn->dst_reg,\n\t\t\t\t\t\t\t\t\tshift);\n\t\t\t\tinsn_buf[cnt++] = BPF_ALU64_IMM(BPF_AND, insn->dst_reg,\n\t\t\t\t\t\t\t\t(1ULL << size * 8) - 1);\n\t\t\t}\n\t\t}\n\n\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\tif (!new_prog)\n\t\t\treturn -ENOMEM;\n\n\t\tdelta += cnt - 1;\n\n\t\t/* keep walking new program and skip insns we just inserted */\n\t\tenv->prog = new_prog;\n\t\tinsn      = new_prog->insnsi + i + delta;\n\t}\n\n\treturn 0;\n}",
        "static void HUF_buildCTableFromTree(HUF_CElt* CTable, nodeElt const* huffNode, int nonNullRank, U32 maxSymbolValue, U32 maxNbBits)\n{\n    /* fill result into ctable (val, nbBits) */\n    int n;\n    U16 nbPerRank[HUF_TABLELOG_MAX+1] = {0};": "static void HUF_buildCTableFromTree(HUF_CElt* CTable, nodeElt const* huffNode, int nonNullRank, U32 maxSymbolValue, U32 maxNbBits)\n{\n    /* fill result into ctable (val, nbBits) */\n    int n;\n    U16 nbPerRank[HUF_TABLELOG_MAX+1] = {0};\n    U16 valPerRank[HUF_TABLELOG_MAX+1] = {0};\n    int const alphabetSize = (int)(maxSymbolValue + 1);\n    for (n=0; n<=nonNullRank; n++)\n        nbPerRank[huffNode[n].nbBits]++;\n    /* determine starting value per rank */\n    {   U16 min = 0;\n        for (n=(int)maxNbBits; n>0; n--) {\n            valPerRank[n] = min;      /* get starting value within each rank */\n            min += nbPerRank[n];\n            min >>= 1;\n    }   }\n    for (n=0; n<alphabetSize; n++)\n        CTable[huffNode[n].byte].nbBits = huffNode[n].nbBits;   /* push nbBits per symbol, symbol order */\n    for (n=0; n<alphabetSize; n++)\n        CTable[n].val = valPerRank[CTable[n].nbBits]++;   /* assign value within rank, symbol order */\n}",
        "static int get_sample(void)\n{\n\tstruct hwlat_kthread_data *kdata = get_cpu_data();\n\tstruct trace_array *tr = hwlat_trace;\n\tstruct hwlat_sample s;": "static int get_sample(void)\n{\n\tstruct hwlat_kthread_data *kdata = get_cpu_data();\n\tstruct trace_array *tr = hwlat_trace;\n\tstruct hwlat_sample s;\n\ttime_type start, t1, t2, last_t2;\n\ts64 diff, outer_diff, total, last_total = 0;\n\tu64 sample = 0;\n\tu64 thresh = tracing_thresh;\n\tu64 outer_sample = 0;\n\tint ret = -1;\n\tunsigned int count = 0;\n\n\tdo_div(thresh, NSEC_PER_USEC); /* modifies interval value */\n\n\tkdata->nmi_total_ts = 0;\n\tkdata->nmi_count = 0;\n\t/* Make sure NMIs see this first */\n\tbarrier();\n\n\ttrace_hwlat_callback_enabled = true;\n\n\tinit_time(last_t2, 0);\n\tstart = time_get(); /* start timestamp */\n\touter_diff = 0;\n\n\tdo {\n\n\t\tt1 = time_get();\t/* we'll look for a discontinuity */\n\t\tt2 = time_get();\n\n\t\tif (time_u64(last_t2)) {\n\t\t\t/* Check the delta from outer loop (t2 to next t1) */\n\t\t\touter_diff = time_to_us(time_sub(t1, last_t2));\n\t\t\t/* This shouldn't happen */\n\t\t\tif (outer_diff < 0) {\n\t\t\t\thwlat_err(BANNER \"time running backwards\\n\");\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tif (outer_diff > outer_sample)\n\t\t\t\touter_sample = outer_diff;\n\t\t}\n\t\tlast_t2 = t2;\n\n\t\ttotal = time_to_us(time_sub(t2, start)); /* sample width */\n\n\t\t/* Check for possible overflows */\n\t\tif (total < last_total) {\n\t\t\thwlat_err(\"Time total overflowed\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tlast_total = total;\n\n\t\t/* This checks the inner loop (t1 to t2) */\n\t\tdiff = time_to_us(time_sub(t2, t1));     /* current diff */\n\n\t\tif (diff > thresh || outer_diff > thresh) {\n\t\t\tif (!count)\n\t\t\t\tktime_get_real_ts64(&s.timestamp);\n\t\t\tcount++;\n\t\t}\n\n\t\t/* This shouldn't happen */\n\t\tif (diff < 0) {\n\t\t\thwlat_err(BANNER \"time running backwards\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (diff > sample)\n\t\t\tsample = diff; /* only want highest value */\n\n\t} while (total <= hwlat_data.sample_width);\n\n\tbarrier(); /* finish the above in the view for NMIs */\n\ttrace_hwlat_callback_enabled = false;\n\tbarrier(); /* Make sure nmi_total_ts is no longer updated */\n\n\tret = 0;\n\n\t/* If we exceed the threshold value, we have found a hardware latency */\n\tif (sample > thresh || outer_sample > thresh) {\n\t\tu64 latency;\n\n\t\tret = 1;\n\n\t\t/* We read in microseconds */\n\t\tif (kdata->nmi_total_ts)\n\t\t\tdo_div(kdata->nmi_total_ts, NSEC_PER_USEC);\n\n\t\thwlat_data.count++;\n\t\ts.seqnum = hwlat_data.count;\n\t\ts.duration = sample;\n\t\ts.outer_duration = outer_sample;\n\t\ts.nmi_total_ts = kdata->nmi_total_ts;\n\t\ts.nmi_count = kdata->nmi_count;\n\t\ts.count = count;\n\t\ttrace_hwlat_sample(&s);\n\n\t\tlatency = max(sample, outer_sample);\n\n\t\t/* Keep a running maximum ever recorded hardware latency */\n\t\tif (latency > tr->max_latency) {\n\t\t\ttr->max_latency = latency;\n\t\t\tlatency_fsnotify(tr);\n\t\t}\n\t}\n\nout:\n\treturn ret;\n}",
        "static void btf_add_dup_struct_in_cu(struct btf *btf, int start_id)\n{\n#define ID(n) (start_id + n)\n\tbtf__set_pointer_size(btf, 8); /* enforce 64-bit arch */\n": "static void btf_add_dup_struct_in_cu(struct btf *btf, int start_id)\n{\n#define ID(n) (start_id + n)\n\tbtf__set_pointer_size(btf, 8); /* enforce 64-bit arch */\n\n\tbtf__add_int(btf, \"int\", 4, BTF_INT_SIGNED);    /* [1] int */\n\n\tbtf__add_struct(btf, \"s\", 8);                   /* [2] struct s { */\n\tbtf__add_field(btf, \"a\", ID(3), 0, 0);          /*      struct anon a; */\n\tbtf__add_field(btf, \"b\", ID(4), 0, 0);          /*      struct anon b; */\n\t\t\t\t\t\t\t/* } */\n\n\tbtf__add_struct(btf, \"(anon)\", 8);              /* [3] struct anon { */\n\tbtf__add_field(btf, \"f1\", ID(1), 0, 0);         /*      int f1; */\n\tbtf__add_field(btf, \"f2\", ID(1), 32, 0);        /*      int f2; */\n\t\t\t\t\t\t\t/* } */\n\n\tbtf__add_struct(btf, \"(anon)\", 8);              /* [4] struct anon { */\n\tbtf__add_field(btf, \"f1\", ID(1), 0, 0);         /*      int f1; */\n\tbtf__add_field(btf, \"f2\", ID(1), 32, 0);        /*      int f2; */\n\t\t\t\t\t\t\t/* } */\n#undef ID\n}",
        "static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)\n{\n\tint fail = 0;\n\tu64 ret_data, org_4F0, org_7F0;\n\tu8 saved_4F0 = 0, saved_7F0 = 0;": "static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)\n{\n\tint fail = 0;\n\tu64 ret_data, org_4F0, org_7F0;\n\tu8 saved_4F0 = 0, saved_7F0 = 0;\n\tstruct net_device *dev = sp->dev;\n\n\t/* Test Write Error at offset 0 */\n\t/* Note that SPI interface allows write access to all areas\n\t * of EEPROM. Hence doing all negative testing only for Xframe I.\n\t */\n\tif (sp->device_type == XFRAME_I_DEVICE)\n\t\tif (!write_eeprom(sp, 0, 0, 3))\n\t\t\tfail = 1;\n\n\t/* Save current values at offsets 0x4F0 and 0x7F0 */\n\tif (!read_eeprom(sp, 0x4F0, &org_4F0))\n\t\tsaved_4F0 = 1;\n\tif (!read_eeprom(sp, 0x7F0, &org_7F0))\n\t\tsaved_7F0 = 1;\n\n\t/* Test Write at offset 4f0 */\n\tif (write_eeprom(sp, 0x4F0, 0x012345, 3))\n\t\tfail = 1;\n\tif (read_eeprom(sp, 0x4F0, &ret_data))\n\t\tfail = 1;\n\n\tif (ret_data != 0x012345) {\n\t\tDBG_PRINT(ERR_DBG, \"%s: eeprom test error at offset 0x4F0. \"\n\t\t\t  \"Data written %llx Data read %llx\\n\",\n\t\t\t  dev->name, (unsigned long long)0x12345,\n\t\t\t  (unsigned long long)ret_data);\n\t\tfail = 1;\n\t}\n\n\t/* Reset the EEPROM data go FFFF */\n\twrite_eeprom(sp, 0x4F0, 0xFFFFFF, 3);\n\n\t/* Test Write Request Error at offset 0x7c */\n\tif (sp->device_type == XFRAME_I_DEVICE)\n\t\tif (!write_eeprom(sp, 0x07C, 0, 3))\n\t\t\tfail = 1;\n\n\t/* Test Write Request at offset 0x7f0 */\n\tif (write_eeprom(sp, 0x7F0, 0x012345, 3))\n\t\tfail = 1;\n\tif (read_eeprom(sp, 0x7F0, &ret_data))\n\t\tfail = 1;\n\n\tif (ret_data != 0x012345) {\n\t\tDBG_PRINT(ERR_DBG, \"%s: eeprom test error at offset 0x7F0. \"\n\t\t\t  \"Data written %llx Data read %llx\\n\",\n\t\t\t  dev->name, (unsigned long long)0x12345,\n\t\t\t  (unsigned long long)ret_data);\n\t\tfail = 1;\n\t}\n\n\t/* Reset the EEPROM data go FFFF */\n\twrite_eeprom(sp, 0x7F0, 0xFFFFFF, 3);\n\n\tif (sp->device_type == XFRAME_I_DEVICE) {\n\t\t/* Test Write Error at offset 0x80 */\n\t\tif (!write_eeprom(sp, 0x080, 0, 3))\n\t\t\tfail = 1;\n\n\t\t/* Test Write Error at offset 0xfc */\n\t\tif (!write_eeprom(sp, 0x0FC, 0, 3))\n\t\t\tfail = 1;\n\n\t\t/* Test Write Error at offset 0x100 */\n\t\tif (!write_eeprom(sp, 0x100, 0, 3))\n\t\t\tfail = 1;\n\n\t\t/* Test Write Error at offset 4ec */\n\t\tif (!write_eeprom(sp, 0x4EC, 0, 3))\n\t\t\tfail = 1;\n\t}\n\n\t/* Restore values at offsets 0x4F0 and 0x7F0 */\n\tif (saved_4F0)\n\t\twrite_eeprom(sp, 0x4F0, org_4F0, 3);\n\tif (saved_7F0)\n\t\twrite_eeprom(sp, 0x7F0, org_7F0, 3);\n\n\t*data = fail;\n\treturn fail;\n}",
        "static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)\n{\n\tu32  k1 = 0;\n\tu32  k2 = 0;\n\tu8   dbnct = 0;": "static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)\n{\n\tu32  k1 = 0;\n\tu32  k2 = 0;\n\tu8   dbnct = 0;\n\tu32  sclfrq = 0;\n\tu8   hldt = 7;\n\tu8   fast_mode = 0;\n\tu32  src_clk_khz;\n\tu32  bus_freq_khz;\n\n\tsrc_clk_khz = bus->apb_clk / 1000;\n\tbus_freq_khz = bus_freq_hz / 1000;\n\tbus->bus_freq = bus_freq_hz;\n\n\t/* 100KHz and below: */\n\tif (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {\n\t\tsclfrq = src_clk_khz / (bus_freq_khz * 4);\n\n\t\tif (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)\n\t\t\treturn -EDOM;\n\n\t\tif (src_clk_khz >= 40000)\n\t\t\thldt = 17;\n\t\telse if (src_clk_khz >= 12500)\n\t\t\thldt = 15;\n\t\telse\n\t\t\thldt = 7;\n\t}\n\n\t/* 400KHz: */\n\telse if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {\n\t\tsclfrq = 0;\n\t\tfast_mode = I2CCTL3_400K_MODE;\n\n\t\tif (src_clk_khz < 7500)\n\t\t\t/* 400KHZ cannot be supported for core clock < 7.5MHz */\n\t\t\treturn -EDOM;\n\n\t\telse if (src_clk_khz >= 50000) {\n\t\t\tk1 = 80;\n\t\t\tk2 = 48;\n\t\t\thldt = 12;\n\t\t\tdbnct = 7;\n\t\t}\n\n\t\t/* Master or Slave with frequency > 25MHz */\n\t\telse if (src_clk_khz > 25000) {\n\t\t\thldt = clk_coef(src_clk_khz, 300) + 7;\n\t\t\tk1 = clk_coef(src_clk_khz, 1600);\n\t\t\tk2 = clk_coef(src_clk_khz, 900);\n\t\t}\n\t}\n\n\t/* 1MHz: */\n\telse if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {\n\t\tsclfrq = 0;\n\t\tfast_mode = I2CCTL3_400K_MODE;\n\n\t\t/* 1MHZ cannot be supported for core clock < 24 MHz */\n\t\tif (src_clk_khz < 24000)\n\t\t\treturn -EDOM;\n\n\t\tk1 = clk_coef(src_clk_khz, 620);\n\t\tk2 = clk_coef(src_clk_khz, 380);\n\n\t\t/* Core clk > 40 MHz */\n\t\tif (src_clk_khz > 40000) {\n\t\t\t/*\n\t\t\t * Set HLDT:\n\t\t\t * SDA hold time:  (HLDT-7) * T(CLK) >= 120\n\t\t\t * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7\n\t\t\t */\n\t\t\thldt = clk_coef(src_clk_khz, 120) + 7;\n\t\t} else {\n\t\t\thldt = 7;\n\t\t\tdbnct = 2;\n\t\t}\n\t}\n\n\t/* Frequency larger than 1 MHz is not supported */\n\telse\n\t\treturn -EINVAL;\n\n\tif (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {\n\t\tk1 = round_up(k1, 2);\n\t\tk2 = round_up(k2 + 1, 2);\n\t\tif (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||\n\t\t    k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)\n\t\t\treturn -EDOM;\n\t}\n\n\t/* write sclfrq value. bits [6:0] are in I2CCTL2 reg */\n\tiowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),\n\t\t bus->reg + NPCM_I2CCTL2);\n\n\t/* bits [8:7] are in I2CCTL3 reg */\n\tiowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),\n\t\t bus->reg + NPCM_I2CCTL3);\n\n\t/* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */\n\tnpcm_i2c_select_bank(bus, I2C_BANK_0);\n\n\tif (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {\n\t\t/*\n\t\t * Set SCL Low/High Time:\n\t\t * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2\n\t\t * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2\n\t\t */\n\t\tiowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);\n\t\tiowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);\n\n\t\tiowrite8(dbnct, bus->reg + NPCM_I2CCTL5);\n\t}\n\n\tiowrite8(hldt, bus->reg + NPCM_I2CCTL4);\n\n\t/* Return to Bank 1, and stay there by default: */\n\tnpcm_i2c_select_bank(bus, I2C_BANK_1);\n\n\treturn 0;\n}",
        "static int mtk_snand_ecc_init_ctx(struct nand_device *nand)\n{\n\tstruct mtk_snand *snf = nand_to_mtk_snand(nand);\n\tstruct nand_ecc_props *conf = &nand->ecc.ctx.conf;\n\tstruct nand_ecc_props *reqs = &nand->ecc.requirements;": "static int mtk_snand_ecc_init_ctx(struct nand_device *nand)\n{\n\tstruct mtk_snand *snf = nand_to_mtk_snand(nand);\n\tstruct nand_ecc_props *conf = &nand->ecc.ctx.conf;\n\tstruct nand_ecc_props *reqs = &nand->ecc.requirements;\n\tstruct nand_ecc_props *user = &nand->ecc.user_conf;\n\tstruct mtd_info *mtd = nanddev_to_mtd(nand);\n\tint step_size = 0, strength = 0, desired_correction = 0, steps;\n\tbool ecc_user = false;\n\tint ret;\n\tu32 parity_bits, max_ecc_bytes;\n\tstruct mtk_ecc_config *ecc_cfg;\n\n\tret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,\n\t\t\t\t      nand->memorg.oobsize);\n\tif (ret)\n\t\treturn ret;\n\n\tecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);\n\tif (!ecc_cfg)\n\t\treturn -ENOMEM;\n\n\tnand->ecc.ctx.priv = ecc_cfg;\n\n\tif (user->step_size && user->strength) {\n\t\tstep_size = user->step_size;\n\t\tstrength = user->strength;\n\t\tecc_user = true;\n\t} else if (reqs->step_size && reqs->strength) {\n\t\tstep_size = reqs->step_size;\n\t\tstrength = reqs->strength;\n\t}\n\n\tif (step_size && strength) {\n\t\tsteps = mtd->writesize / step_size;\n\t\tdesired_correction = steps * strength;\n\t\tstrength = desired_correction / snf->nfi_cfg.nsectors;\n\t}\n\n\tecc_cfg->mode = ECC_NFI_MODE;\n\tecc_cfg->sectors = snf->nfi_cfg.nsectors;\n\tecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;\n\n\t// calculate the max possible strength under current page format\n\tparity_bits = mtk_ecc_get_parity_bits(snf->ecc);\n\tmax_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;\n\tecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;\n\tmtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);\n\n\t// if there's a user requested strength, find the minimum strength that\n\t// meets the requirement. Otherwise use the maximum strength which is\n\t// expected by BootROM.\n\tif (ecc_user && strength) {\n\t\tu32 s_next = ecc_cfg->strength - 1;\n\n\t\twhile (1) {\n\t\t\tmtk_ecc_adjust_strength(snf->ecc, &s_next);\n\t\t\tif (s_next >= ecc_cfg->strength)\n\t\t\t\tbreak;\n\t\t\tif (s_next < strength)\n\t\t\t\tbreak;\n\t\t\ts_next = ecc_cfg->strength - 1;\n\t\t}\n\t}\n\n\tmtd_set_ooblayout(mtd, &mtk_snand_ooblayout);\n\n\tconf->step_size = snf->caps->sector_size;\n\tconf->strength = ecc_cfg->strength;\n\n\tif (ecc_cfg->strength < strength)\n\t\tdev_warn(snf->dev, \"unable to fulfill ECC of %u bits.\\n\",\n\t\t\t strength);\n\tdev_info(snf->dev, \"ECC strength: %u bits per %u bytes\\n\",\n\t\t ecc_cfg->strength, snf->caps->sector_size);\n\n\treturn 0;\n}",
        "static void alc_headset_mode_ctia(struct hda_codec *codec)\n{\n\tint val;\n\n\tstatic const struct coef_fw coef0255[] = {": "static void alc_headset_mode_ctia(struct hda_codec *codec)\n{\n\tint val;\n\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x45, 0xd489), /* Set to CTIA type */\n\t\tWRITE_COEF(0x1b, 0x0c2b),\n\t\tWRITE_COEFEX(0x57, 0x03, 0x8ea6),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0256[] = {\n\t\tWRITE_COEF(0x45, 0xd489), /* Set to CTIA type */\n\t\tWRITE_COEF(0x1b, 0x0e6b),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0233[] = {\n\t\tWRITE_COEF(0x45, 0xd429),\n\t\tWRITE_COEF(0x1b, 0x0c2b),\n\t\tWRITE_COEF(0x32, 0x4ea3),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0288[] = {\n\t\tUPDATE_COEF(0x50, 0x2000, 0x2000),\n\t\tUPDATE_COEF(0x56, 0x0006, 0x0006),\n\t\tUPDATE_COEF(0x66, 0x0008, 0),\n\t\tUPDATE_COEF(0x67, 0x2000, 0),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0292[] = {\n\t\tWRITE_COEF(0x6b, 0xd429),\n\t\tWRITE_COEF(0x76, 0x0008),\n\t\tWRITE_COEF(0x18, 0x7388),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0293[] = {\n\t\tWRITE_COEF(0x45, 0xd429), /* Set to ctia type */\n\t\tUPDATE_COEF(0x10, 7<<8, 7<<8), /* SET Line1 JD to 1 */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0688[] = {\n\t\tWRITE_COEF(0x11, 0x0001),\n\t\tWRITE_COEF(0x15, 0x0d60),\n\t\tWRITE_COEF(0xc3, 0x0000),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0225_1[] = {\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x35<<10),\n\t\tUPDATE_COEF(0x63, 3<<14, 2<<14),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0225_2[] = {\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x35<<10),\n\t\tUPDATE_COEF(0x63, 3<<14, 1<<14),\n\t\t{}\n\t};\n\n\tswitch (codec->core.vendor_id) {\n\tcase 0x10ec0255:\n\t\talc_process_coef_fw(codec, coef0255);\n\t\tbreak;\n\tcase 0x10ec0230:\n\tcase 0x10ec0236:\n\tcase 0x10ec0256:\n\t\talc_process_coef_fw(codec, coef0256);\n\t\tbreak;\n\tcase 0x10ec0234:\n\tcase 0x10ec0274:\n\tcase 0x10ec0294:\n\t\talc_write_coef_idx(codec, 0x45, 0xd689);\n\t\tbreak;\n\tcase 0x10ec0233:\n\tcase 0x10ec0283:\n\t\talc_process_coef_fw(codec, coef0233);\n\t\tbreak;\n\tcase 0x10ec0298:\n\t\tval = alc_read_coef_idx(codec, 0x50);\n\t\tif (val & (1 << 12)) {\n\t\t\talc_update_coef_idx(codec, 0x8e, 0x0070, 0x0020);\n\t\t\talc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xd400);\n\t\t\tmsleep(300);\n\t\t} else {\n\t\t\talc_update_coef_idx(codec, 0x8e, 0x0070, 0x0010);\n\t\t\talc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xd400);\n\t\t\tmsleep(300);\n\t\t}\n\t\tbreak;\n\tcase 0x10ec0286:\n\tcase 0x10ec0288:\n\t\talc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xd400);\n\t\tmsleep(300);\n\t\talc_process_coef_fw(codec, coef0288);\n\t\tbreak;\n\tcase 0x10ec0292:\n\t\talc_process_coef_fw(codec, coef0292);\n\t\tbreak;\n\tcase 0x10ec0293:\n\t\talc_process_coef_fw(codec, coef0293);\n\t\tbreak;\n\tcase 0x10ec0668:\n\t\talc_process_coef_fw(codec, coef0688);\n\t\tbreak;\n\tcase 0x10ec0215:\n\tcase 0x10ec0225:\n\tcase 0x10ec0285:\n\tcase 0x10ec0295:\n\tcase 0x10ec0289:\n\tcase 0x10ec0299:\n\t\tval = alc_read_coef_idx(codec, 0x45);\n\t\tif (val & (1 << 9))\n\t\t\talc_process_coef_fw(codec, coef0225_2);\n\t\telse\n\t\t\talc_process_coef_fw(codec, coef0225_1);\n\t\tbreak;\n\tcase 0x10ec0867:\n\t\talc_update_coefex_idx(codec, 0x57, 0x5, 1<<14, 0);\n\t\tbreak;\n\t}\n\tcodec_dbg(codec, \"Headset jack set to iPhone-style headset mode.\\n\");\n}",
        "static void print_lock(struct held_lock *hlock)\n{\n\t/*\n\t * We can be called locklessly through debug_show_all_locks() so be\n\t * extra careful, the hlock might have been released and cleared.": "static void print_lock(struct held_lock *hlock)\n{\n\t/*\n\t * We can be called locklessly through debug_show_all_locks() so be\n\t * extra careful, the hlock might have been released and cleared.\n\t *\n\t * If this indeed happens, lets pretend it does not hurt to continue\n\t * to print the lock unless the hlock class_idx does not point to a\n\t * registered class. The rationale here is: since we don't attempt\n\t * to distinguish whether we are in this situation, if it just\n\t * happened we can't count on class_idx to tell either.\n\t */\n\tstruct lock_class *lock = hlock_class(hlock);\n\n\tif (!lock) {\n\t\tprintk(KERN_CONT \"<RELEASED>\\n\");\n\t\treturn;\n\t}\n\n\tprintk(KERN_CONT \"%px\", hlock->instance);\n\tprint_lock_name(lock);\n\tprintk(KERN_CONT \", at: %pS\\n\", (void *)hlock->acquire_ip);\n}",
        "static int init_agc(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drx_common_attr *common_attr = NULL;\n\tstruct drxj_data *ext_attr = NULL;": "static int init_agc(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drx_common_attr *common_attr = NULL;\n\tstruct drxj_data *ext_attr = NULL;\n\tstruct drxj_cfg_agc *p_agc_rf_settings = NULL;\n\tstruct drxj_cfg_agc *p_agc_if_settings = NULL;\n\tint rc;\n\tu16 ingain_tgt_max = 0;\n\tu16 clp_dir_to = 0;\n\tu16 sns_sum_max = 0;\n\tu16 clp_sum_max = 0;\n\tu16 sns_dir_to = 0;\n\tu16 ki_innergain_min = 0;\n\tu16 agc_ki = 0;\n\tu16 ki_max = 0;\n\tu16 if_iaccu_hi_tgt_min = 0;\n\tu16 data = 0;\n\tu16 agc_ki_dgain = 0;\n\tu16 ki_min = 0;\n\tu16 clp_ctrl_mode = 0;\n\tu16 agc_rf = 0;\n\tu16 agc_if = 0;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\tcommon_attr = (struct drx_common_attr *) demod->my_common_attr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\tswitch (ext_attr->standard) {\n\tcase DRX_STANDARD_8VSB:\n\t\tclp_sum_max = 1023;\n\t\tclp_dir_to = (u16) (-9);\n\t\tsns_sum_max = 1023;\n\t\tsns_dir_to = (u16) (-9);\n\t\tki_innergain_min = (u16) (-32768);\n\t\tki_max = 0x032C;\n\t\tagc_ki_dgain = 0xC;\n\t\tif_iaccu_hi_tgt_min = 2047;\n\t\tki_min = 0x0117;\n\t\tingain_tgt_max = 16383;\n\t\tclp_ctrl_mode = 0;\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tp_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);\n\t\tp_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);\n\t\tbreak;\n#ifndef DRXJ_VSB_ONLY\n\tcase DRX_STANDARD_ITU_A:\n\tcase DRX_STANDARD_ITU_C:\n\tcase DRX_STANDARD_ITU_B:\n\t\tingain_tgt_max = 5119;\n\t\tclp_sum_max = 1023;\n\t\tclp_dir_to = (u16) (-5);\n\t\tsns_sum_max = 127;\n\t\tsns_dir_to = (u16) (-3);\n\t\tki_innergain_min = 0;\n\t\tki_max = 0x0657;\n\t\tif_iaccu_hi_tgt_min = 2047;\n\t\tagc_ki_dgain = 0x7;\n\t\tki_min = 0x0117;\n\t\tclp_ctrl_mode = 0;\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tp_agc_if_settings = &(ext_attr->qam_if_agc_cfg);\n\t\tp_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\n\t\trc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tagc_ki &= 0xf000;\n\t\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\tbreak;\n#endif\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\t/* for new AGC interface */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* Gain fed from inner to outer AGC */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\t/* set to p_agc_settings->top before */\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\tagc_rf = 0x800 + p_agc_rf_settings->cut_off_current;\n\tif (common_attr->tuner_rf_agc_pol == true)\n\t\tagc_rf = 0x87ff - agc_rf;\n\n\tagc_if = 0x800;\n\tif (common_attr->tuner_if_agc_pol == true)\n\t\tagc_rf = 0x87ff - agc_rf;\n\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Set/restore Ki DGAIN factor */\n\trc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tdata &= ~SCU_RAM_AGC_KI_DGAIN__M;\n\tdata |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)\n{\n\t/*  Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */\n\t/*  We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */\n\tint ret = _SUCCESS;": "static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)\n{\n\t/*  Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */\n\t/*  We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */\n\tint ret = _SUCCESS;\n\tu32 pageNums, remainSize;\n\tu32 page, offset;\n\tu8 *bufferPtr = buffer;\n\n\tpageNums = size / MAX_DLFW_PAGE_SIZE;\n\tremainSize = size % MAX_DLFW_PAGE_SIZE;\n\n\tfor (page = 0; page < pageNums; page++) {\n\t\toffset = page * MAX_DLFW_PAGE_SIZE;\n\t\tret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE);\n\n\t\tif (ret == _FAIL) {\n\t\t\tprintk(\"====>%s %d\\n\", __func__, __LINE__);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\tif (remainSize) {\n\t\toffset = pageNums * MAX_DLFW_PAGE_SIZE;\n\t\tpage = pageNums;\n\t\tret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);\n\n\t\tif (ret == _FAIL) {\n\t\t\tprintk(\"====>%s %d\\n\", __func__, __LINE__);\n\t\t\tgoto exit;\n\t\t}\n\t}\n\nexit:\n\treturn ret;\n}",
        "static bool gve_rx_ctx_init(struct gve_rx_ctx *ctx, struct gve_rx_ring *rx)\n{\n\tbool qpl_mode = !rx->data.raw_addressing, packet_size_error = false;\n\tbool buffer_error = false, desc_error = false, seqno_error = false;\n\tstruct gve_rx_slot_page_info *page_info;": "static bool gve_rx_ctx_init(struct gve_rx_ctx *ctx, struct gve_rx_ring *rx)\n{\n\tbool qpl_mode = !rx->data.raw_addressing, packet_size_error = false;\n\tbool buffer_error = false, desc_error = false, seqno_error = false;\n\tstruct gve_rx_slot_page_info *page_info;\n\tstruct gve_priv *priv = rx->gve;\n\tu32 idx = rx->cnt & rx->mask;\n\tbool reuse_frags, can_flip;\n\tstruct gve_rx_desc *desc;\n\tu16 packet_size = 0;\n\tu16 n_frags = 0;\n\tint recycle;\n\n\t/** In QPL mode, we only flip buffers when all buffers containing the packet\n\t * can be flipped. RDA can_flip decisions will be made later, per frag.\n\t */\n\tcan_flip = qpl_mode;\n\treuse_frags = can_flip;\n\tdo {\n\t\tu16 frag_size;\n\n\t\tn_frags++;\n\t\tdesc = &rx->desc.desc_ring[idx];\n\t\tdesc_error = unlikely(desc->flags_seq & GVE_RXF_ERR) || desc_error;\n\t\tif (GVE_SEQNO(desc->flags_seq) != rx->desc.seqno) {\n\t\t\tseqno_error = true;\n\t\t\tnetdev_warn(priv->dev,\n\t\t\t\t    \"RX seqno error: want=%d, got=%d, dropping packet and scheduling reset.\",\n\t\t\t\t    rx->desc.seqno, GVE_SEQNO(desc->flags_seq));\n\t\t}\n\t\tfrag_size = be16_to_cpu(desc->len);\n\t\tpacket_size += frag_size;\n\t\tif (frag_size > rx->packet_buffer_size) {\n\t\t\tpacket_size_error = true;\n\t\t\tnetdev_warn(priv->dev,\n\t\t\t\t    \"RX fragment error: packet_buffer_size=%d, frag_size=%d, dropping packet.\",\n\t\t\t\t    rx->packet_buffer_size, be16_to_cpu(desc->len));\n\t\t}\n\t\tpage_info = &rx->data.page_info[idx];\n\t\tif (can_flip) {\n\t\t\trecycle = gve_rx_can_recycle_buffer(page_info);\n\t\t\treuse_frags = reuse_frags && recycle > 0;\n\t\t\tbuffer_error = buffer_error || unlikely(recycle < 0);\n\t\t}\n\t\tidx = (idx + 1) & rx->mask;\n\t\trx->desc.seqno = gve_next_seqno(rx->desc.seqno);\n\t} while (GVE_PKTCONT_BIT_IS_SET(desc->flags_seq));\n\n\tprefetch(rx->desc.desc_ring + idx);\n\n\tctx->curr_frag_cnt = 0;\n\tctx->total_expected_size = packet_size - GVE_RX_PAD;\n\tctx->expected_frag_cnt = n_frags;\n\tctx->skb_head = NULL;\n\tctx->reuse_frags = reuse_frags;\n\n\tif (ctx->expected_frag_cnt > 1) {\n\t\tu64_stats_update_begin(&rx->statss);\n\t\trx->rx_cont_packet_cnt++;\n\t\tu64_stats_update_end(&rx->statss);\n\t}\n\tif (ctx->total_expected_size > priv->rx_copybreak && !ctx->reuse_frags && qpl_mode) {\n\t\tu64_stats_update_begin(&rx->statss);\n\t\trx->rx_copied_pkt++;\n\t\tu64_stats_update_end(&rx->statss);\n\t}\n\n\tif (unlikely(buffer_error || seqno_error || packet_size_error)) {\n\t\tgve_schedule_reset(priv);\n\t\treturn false;\n\t}\n\n\tif (unlikely(desc_error)) {\n\t\tu64_stats_update_begin(&rx->statss);\n\t\trx->rx_desc_err_dropped_pkt++;\n\t\tu64_stats_update_end(&rx->statss);\n\t\treturn false;\n\t}\n\treturn true;\n}",
        "static void lzx_postprocess(u8 *data, u32 size)\n{\n\t/*\n\t * A worthwhile optimization is to push the end-of-buffer check into the\n\t * relatively rare E8 case.  This is possible if we replace the last six": "static void lzx_postprocess(u8 *data, u32 size)\n{\n\t/*\n\t * A worthwhile optimization is to push the end-of-buffer check into the\n\t * relatively rare E8 case.  This is possible if we replace the last six\n\t * bytes of data with E8 bytes; then we are guaranteed to hit an E8 byte\n\t * before reaching end-of-buffer.  In addition, this scheme guarantees\n\t * that no translation can begin following an E8 byte in the last 10\n\t * bytes because a 4-byte offset containing E8 as its high byte is a\n\t * large negative number that is not valid for translation.  That is\n\t * exactly what we need.\n\t */\n\tu8 *tail;\n\tu8 saved_bytes[6];\n\tu8 *p;\n\n\tif (size <= 10)\n\t\treturn;\n\n\ttail = &data[size - 6];\n\tmemcpy(saved_bytes, tail, 6);\n\tmemset(tail, 0xE8, 6);\n\tp = data;\n\tfor (;;) {\n\t\twhile (*p != 0xE8)\n\t\t\tp++;\n\t\tif (p >= tail)\n\t\t\tbreak;\n\t\tundo_e8_translation(p + 1, p - data);\n\t\tp += 5;\n\t}\n\tmemcpy(tail, saved_bytes, 6);\n}",
        "static void dotest(void (*testcase_fn)(void), int expected, int lockclass_mask)\n{\n\tint saved_preempt_count = preempt_count();\n#ifdef CONFIG_PREEMPT_RT\n#ifdef CONFIG_SMP": "static void dotest(void (*testcase_fn)(void), int expected, int lockclass_mask)\n{\n\tint saved_preempt_count = preempt_count();\n#ifdef CONFIG_PREEMPT_RT\n#ifdef CONFIG_SMP\n\tint saved_mgd_count = current->migration_disabled;\n#endif\n\tint saved_rcu_count = current->rcu_read_lock_nesting;\n#endif\n\n\tWARN_ON(irqs_disabled());\n\n\tdebug_locks_silent = !(debug_locks_verbose & lockclass_mask);\n\n\ttestcase_fn();\n\t/*\n\t * Filter out expected failures:\n\t */\n#ifndef CONFIG_PROVE_LOCKING\n\tif (expected == FAILURE && debug_locks) {\n\t\texpected_testcase_failures++;\n\t\tpr_cont(\"failed|\");\n\t}\n\telse\n#endif\n\tif (debug_locks != expected) {\n\t\tunexpected_testcase_failures++;\n\t\tpr_cont(\"FAILED|\");\n\t} else {\n\t\ttestcase_successes++;\n\t\tpr_cont(\"  ok  |\");\n\t}\n\ttestcase_total++;\n\n\tif (debug_locks_verbose & lockclass_mask)\n\t\tpr_cont(\" lockclass mask: %x, debug_locks: %d, expected: %d\\n\",\n\t\t\tlockclass_mask, debug_locks, expected);\n\t/*\n\t * Some tests (e.g. double-unlock) might corrupt the preemption\n\t * count, so restore it:\n\t */\n\tpreempt_count_set(saved_preempt_count);\n\n#ifdef CONFIG_PREEMPT_RT\n#ifdef CONFIG_SMP\n\twhile (current->migration_disabled > saved_mgd_count)\n\t\tmigrate_enable();\n#endif\n\n\twhile (current->rcu_read_lock_nesting > saved_rcu_count)\n\t\trcu_read_unlock();\n\tWARN_ON_ONCE(current->rcu_read_lock_nesting < saved_rcu_count);\n#endif\n\n#ifdef CONFIG_TRACE_IRQFLAGS\n\tif (softirq_count())\n\t\tcurrent->softirqs_enabled = 0;\n\telse\n\t\tcurrent->softirqs_enabled = 1;\n#endif\n\n\treset_locks();\n}",
        "static int dbInitTree(struct dmaptree * dtp)\n{\n\tint l2max, l2free, bsize, nextb, i;\n\tint child, parent, nparent;\n\ts8 *tp, *cp, *cp1;": "static int dbInitTree(struct dmaptree * dtp)\n{\n\tint l2max, l2free, bsize, nextb, i;\n\tint child, parent, nparent;\n\ts8 *tp, *cp, *cp1;\n\n\ttp = dtp->stree;\n\n\t/* Determine the maximum free string possible for the leaves */\n\tl2max = le32_to_cpu(dtp->l2nleafs) + dtp->budmin;\n\n\t/*\n\t * configure the leaf levevl into binary buddy system\n\t *\n\t * Try to combine buddies starting with a buddy size of 1\n\t * (i.e. two leaves). At a buddy size of 1 two buddy leaves\n\t * can be combined if both buddies have a maximum free of l2min;\n\t * the combination will result in the left-most buddy leaf having\n\t * a maximum free of l2min+1.\n\t * After processing all buddies for a given size, process buddies\n\t * at the next higher buddy size (i.e. current size * 2) and\n\t * the next maximum free (current free + 1).\n\t * This continues until the maximum possible buddy combination\n\t * yields maximum free.\n\t */\n\tfor (l2free = dtp->budmin, bsize = 1; l2free < l2max;\n\t     l2free++, bsize = nextb) {\n\t\t/* get next buddy size == current buddy pair size */\n\t\tnextb = bsize << 1;\n\n\t\t/* scan each adjacent buddy pair at current buddy size */\n\t\tfor (i = 0, cp = tp + le32_to_cpu(dtp->leafidx);\n\t\t     i < le32_to_cpu(dtp->nleafs);\n\t\t     i += nextb, cp += nextb) {\n\t\t\t/* coalesce if both adjacent buddies are max free */\n\t\t\tif (*cp == l2free && *(cp + bsize) == l2free) {\n\t\t\t\t*cp = l2free + 1;\t/* left take right */\n\t\t\t\t*(cp + bsize) = -1;\t/* right give left */\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\n\t * bubble summary information of leaves up the tree.\n\t *\n\t * Starting at the leaf node level, the four nodes described by\n\t * the higher level parent node are compared for a maximum free and\n\t * this maximum becomes the value of the parent node.\n\t * when all lower level nodes are processed in this fashion then\n\t * move up to the next level (parent becomes a lower level node) and\n\t * continue the process for that level.\n\t */\n\tfor (child = le32_to_cpu(dtp->leafidx),\n\t     nparent = le32_to_cpu(dtp->nleafs) >> 2;\n\t     nparent > 0; nparent >>= 2, child = parent) {\n\t\t/* get index of 1st node of parent level */\n\t\tparent = (child - 1) >> 2;\n\n\t\t/* set the value of the parent node as the maximum\n\t\t * of the four nodes of the current level.\n\t\t */\n\t\tfor (i = 0, cp = tp + child, cp1 = tp + parent;\n\t\t     i < nparent; i++, cp += 4, cp1++)\n\t\t\t*cp1 = TREEMAX(cp);\n\t}\n\n\treturn (*tp);\n}",
        "static int atomisp_qbuffers_to_css_for_all_pipes(struct atomisp_sub_device *asd)\n{\n\tenum ia_css_buffer_type buf_type;\n\tenum ia_css_pipe_id css_capture_pipe_id = IA_CSS_PIPE_ID_COPY;\n\tenum ia_css_pipe_id css_preview_pipe_id = IA_CSS_PIPE_ID_COPY;": "static int atomisp_qbuffers_to_css_for_all_pipes(struct atomisp_sub_device *asd)\n{\n\tenum ia_css_buffer_type buf_type;\n\tenum ia_css_pipe_id css_capture_pipe_id = IA_CSS_PIPE_ID_COPY;\n\tenum ia_css_pipe_id css_preview_pipe_id = IA_CSS_PIPE_ID_COPY;\n\tenum ia_css_pipe_id css_video_pipe_id = IA_CSS_PIPE_ID_COPY;\n\tenum atomisp_input_stream_id input_stream_id;\n\tstruct atomisp_video_pipe *capture_pipe;\n\tstruct atomisp_video_pipe *preview_pipe;\n\tstruct atomisp_video_pipe *video_pipe;\n\n\tcapture_pipe = &asd->video_out_capture;\n\tpreview_pipe = &asd->video_out_preview;\n\tvideo_pipe = &asd->video_out_video_capture;\n\n\tbuf_type = atomisp_get_css_buf_type(\n\t\t       asd, css_preview_pipe_id,\n\t\t       atomisp_subdev_source_pad(&preview_pipe->vdev));\n\tinput_stream_id = ATOMISP_INPUT_STREAM_PREVIEW;\n\tatomisp_q_video_buffers_to_css(asd, preview_pipe,\n\t\t\t\t       input_stream_id,\n\t\t\t\t       buf_type, css_preview_pipe_id);\n\n\tbuf_type = atomisp_get_css_buf_type(asd, css_capture_pipe_id,\n\t\t\t\t\t    atomisp_subdev_source_pad(&capture_pipe->vdev));\n\tinput_stream_id = ATOMISP_INPUT_STREAM_GENERAL;\n\tatomisp_q_video_buffers_to_css(asd, capture_pipe,\n\t\t\t\t       input_stream_id,\n\t\t\t\t       buf_type, css_capture_pipe_id);\n\n\tbuf_type = atomisp_get_css_buf_type(asd, css_video_pipe_id,\n\t\t\t\t\t    atomisp_subdev_source_pad(&video_pipe->vdev));\n\tinput_stream_id = ATOMISP_INPUT_STREAM_VIDEO;\n\tatomisp_q_video_buffers_to_css(asd, video_pipe,\n\t\t\t\t       input_stream_id,\n\t\t\t\t       buf_type, css_video_pipe_id);\n\treturn 0;\n}",
        "static int spl2sw_mdio_access(struct spl2sw_common *comm, u8 cmd, u8 addr, u8 regnum, u16 wdata)\n{\n\tu32 reg, reg2;\n\tu32 val;\n\tint ret;": "static int spl2sw_mdio_access(struct spl2sw_common *comm, u8 cmd, u8 addr, u8 regnum, u16 wdata)\n{\n\tu32 reg, reg2;\n\tu32 val;\n\tint ret;\n\n\t/* Note that addr (of phy) should match either ext_phy0_addr\n\t * or ext_phy1_addr, or mdio commands won't be sent out.\n\t */\n\treg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);\n\treg &= ~MAC_EXT_PHY0_ADDR;\n\treg |= FIELD_PREP(MAC_EXT_PHY0_ADDR, addr);\n\n\treg2 = FIELD_PREP(MAC_CPU_PHY_WT_DATA, wdata) | FIELD_PREP(MAC_CPU_PHY_CMD, cmd) |\n\t       FIELD_PREP(MAC_CPU_PHY_REG_ADDR, regnum) | FIELD_PREP(MAC_CPU_PHY_ADDR, addr);\n\n\t/* Set ext_phy0_addr and then issue mdio command.\n\t * No interrupt is allowed in between.\n\t */\n\tspin_lock_irq(&comm->mdio_lock);\n\twritel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);\n\twritel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0);\n\tspin_unlock_irq(&comm->mdio_lock);\n\n\tret = read_poll_timeout(readl, val, val & cmd, 1, 1000, true,\n\t\t\t\tcomm->l2sw_reg_base + L2SW_PHY_CNTL_REG1);\n\n\t/* Set ext_phy0_addr back to 31 to prevent\n\t * from sending mdio command to phy by\n\t * hardware auto-mdio function.\n\t */\n\treg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);\n\treg &= ~MAC_EXT_PHY0_ADDR;\n\treg |= FIELD_PREP(MAC_EXT_PHY0_ADDR, 31);\n\twritel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);\n\n\tif (ret == 0)\n\t\treturn val >> 16;\n\telse\n\t\treturn ret;\n}",
        "static int cs_etm__print_cpu_metadata_v1(__u64 *val, int *offset)\n{\n\tint i = *offset, j, total_params = 0;\n\t__u64 magic;\n": "static int cs_etm__print_cpu_metadata_v1(__u64 *val, int *offset)\n{\n\tint i = *offset, j, total_params = 0;\n\t__u64 magic;\n\n\tmagic = val[i + CS_ETM_MAGIC];\n\t/* total params to print is NR_PARAMS + common block size for v1 */\n\ttotal_params = val[i + CS_ETM_NR_TRC_PARAMS] + CS_ETM_COMMON_BLK_MAX_V1;\n\n\tif (magic == __perf_cs_etmv3_magic) {\n\t\tfor (j = 0; j < total_params; j++, i++) {\n\t\t\t/* if newer record - could be excess params */\n\t\t\tif (j >= CS_ETM_PRIV_MAX)\n\t\t\t\tfprintf(stdout, param_unk_fmt, j, val[i]);\n\t\t\telse\n\t\t\t\tfprintf(stdout, cs_etm_priv_fmts[j], val[i]);\n\t\t}\n\t} else if (magic == __perf_cs_etmv4_magic || magic == __perf_cs_ete_magic) {\n\t\t/*\n\t\t * ETE and ETMv4 can be printed in the same block because the number of parameters\n\t\t * is saved and they share the list of parameter names. ETE is also only supported\n\t\t * in V1 files.\n\t\t */\n\t\tfor (j = 0; j < total_params; j++, i++) {\n\t\t\t/* if newer record - could be excess params */\n\t\t\tif (j >= CS_ETE_PRIV_MAX)\n\t\t\t\tfprintf(stdout, param_unk_fmt, j, val[i]);\n\t\t\telse\n\t\t\t\tfprintf(stdout, cs_etmv4_priv_fmts[j], val[i]);\n\t\t}\n\t} else {\n\t\t/* failure - note bad magic value and error out */\n\t\tfprintf(stdout, magic_unk_fmt, magic);\n\t\treturn -EINVAL;\n\t}\n\t*offset = i;\n\treturn 0;\n}",
        "static int decide_core(struct venus_inst *inst)\n{\n\tconst u32 ptype = HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE;\n\tstruct venus_core *core = inst->core;\n\tu32 min_coreid, min_load, cur_inst_load;": "static int decide_core(struct venus_inst *inst)\n{\n\tconst u32 ptype = HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE;\n\tstruct venus_core *core = inst->core;\n\tu32 min_coreid, min_load, cur_inst_load;\n\tu32 min_lp_coreid, min_lp_load, cur_inst_lp_load;\n\tstruct hfi_videocores_usage_type cu;\n\tunsigned long max_freq;\n\tint ret = 0;\n\n\tif (legacy_binding) {\n\t\tif (inst->session_type == VIDC_SESSION_TYPE_DEC)\n\t\t\tcu.video_core_enable_mask = VIDC_CORE_ID_1;\n\t\telse\n\t\t\tcu.video_core_enable_mask = VIDC_CORE_ID_2;\n\n\t\tgoto done;\n\t}\n\n\tif (inst->clk_data.core_id != VIDC_CORE_ID_DEFAULT)\n\t\treturn 0;\n\n\tcur_inst_load = load_per_instance(inst);\n\tcur_inst_load *= inst->clk_data.vpp_freq;\n\t/*TODO : divide this inst->load by work_route */\n\n\tcur_inst_lp_load = load_per_instance(inst);\n\tcur_inst_lp_load *= inst->clk_data.low_power_freq;\n\t/*TODO : divide this inst->load by work_route */\n\n\tmax_freq = core->res->freq_tbl[0].freq;\n\n\tmin_loaded_core(inst, &min_coreid, &min_load, false);\n\tmin_loaded_core(inst, &min_lp_coreid, &min_lp_load, true);\n\n\tif (cur_inst_load + min_load <= max_freq) {\n\t\tinst->clk_data.core_id = min_coreid;\n\t\tcu.video_core_enable_mask = min_coreid;\n\t} else if (cur_inst_lp_load + min_load <= max_freq) {\n\t\t/* Move current instance to LP and return */\n\t\tinst->clk_data.core_id = min_coreid;\n\t\tcu.video_core_enable_mask = min_coreid;\n\t\tpower_save_mode_enable(inst, true);\n\t} else if (cur_inst_lp_load + min_lp_load <= max_freq) {\n\t\t/* Move all instances to LP mode and return */\n\t\tinst->clk_data.core_id = min_lp_coreid;\n\t\tcu.video_core_enable_mask = min_lp_coreid;\n\t\tmove_core_to_power_save_mode(core, min_lp_coreid);\n\t} else {\n\t\tdev_warn(core->dev, \"HW can't support this load\");\n\t\treturn -EINVAL;\n\t}\n\ndone:\n\tret = hfi_session_set_property(inst, ptype, &cu);\n\tif (ret)\n\t\treturn ret;\n\n\treturn ret;\n}",
        "static void meson_gxbb_axg_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)\n{\n\tunsigned long clk_rate = clk_get_rate(i2c->clk);\n\tunsigned int div_h, div_l;\n": "static void meson_gxbb_axg_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)\n{\n\tunsigned long clk_rate = clk_get_rate(i2c->clk);\n\tunsigned int div_h, div_l;\n\n\t/* According to I2C-BUS Spec 2.1, in FAST-MODE, the minimum LOW period is 1.3uS, and\n\t * minimum HIGH is least 0.6us.\n\t * For 400000 freq, the period is 2.5us. To keep within the specs, give 40% of period to\n\t * HIGH and 60% to LOW. This means HIGH at 1.0us and LOW 1.5us.\n\t * The same applies for Fast-mode plus, where LOW is 0.5us and HIGH is 0.26us.\n\t * Duty = H/(H + L) = 2/5\n\t */\n\tif (freq <= I2C_MAX_STANDARD_MODE_FREQ) {\n\t\tdiv_h = DIV_ROUND_UP(clk_rate, freq);\n\t\tdiv_l = DIV_ROUND_UP(div_h, 4);\n\t\tdiv_h = DIV_ROUND_UP(div_h, 2) - FILTER_DELAY;\n\t} else {\n\t\tdiv_h = DIV_ROUND_UP(clk_rate * 2, freq * 5) - FILTER_DELAY;\n\t\tdiv_l = DIV_ROUND_UP(clk_rate * 3, freq * 5 * 2);\n\t}\n\n\t/* clock divider has 12 bits */\n\tif (div_h > GENMASK(11, 0)) {\n\t\tdev_err(i2c->dev, \"requested bus frequency too low\\n\");\n\t\tdiv_h = GENMASK(11, 0);\n\t}\n\tif (div_l > GENMASK(11, 0)) {\n\t\tdev_err(i2c->dev, \"requested bus frequency too low\\n\");\n\t\tdiv_l = GENMASK(11, 0);\n\t}\n\n\tmeson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,\n\t\t\t   FIELD_PREP(REG_CTRL_CLKDIV_MASK, div_h & GENMASK(9, 0)));\n\n\tmeson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,\n\t\t\t   FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div_h >> 10));\n\n\t/* set SCL low delay */\n\tmeson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_MASK,\n\t\t\t   FIELD_PREP(REG_SLV_SCL_LOW_MASK, div_l));\n\n\t/* Enable HIGH/LOW mode */\n\tmeson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, REG_SLV_SCL_LOW_EN);\n\n\tdev_dbg(i2c->dev, \"%s: clk %lu, freq %u, divh %u, divl %u\\n\", __func__,\n\t\tclk_rate, freq, div_h, div_l);\n}",
        "static void cs8409_cs42l42_hw_init(struct hda_codec *codec)\n{\n\tconst struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;\n\tconst struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;\n\tstruct cs8409_spec *spec = codec->spec;": "static void cs8409_cs42l42_hw_init(struct hda_codec *codec)\n{\n\tconst struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;\n\tconst struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;\n\tstruct cs8409_spec *spec = codec->spec;\n\tstruct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];\n\n\tif (spec->gpio_mask) {\n\t\tsnd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,\n\t\t\tspec->gpio_mask);\n\t\tsnd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,\n\t\t\tspec->gpio_dir);\n\t\tsnd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,\n\t\t\tspec->gpio_data);\n\t}\n\n\tfor (; seq->nid; seq++)\n\t\tcs8409_vendor_coef_set(codec, seq->cir, seq->coeff);\n\n\tif (codec->fixup_id == CS8409_BULLSEYE) {\n\t\tfor (; seq_bullseye->nid; seq_bullseye++)\n\t\t\tcs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);\n\t}\n\n\tswitch (codec->fixup_id) {\n\tcase CS8409_CYBORG:\n\tcase CS8409_WARLOCK_MLK_DUAL_MIC:\n\t\t/* DMIC1_MO=00b, DMIC1/2_SR=1 */\n\t\tcs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003);\n\t\tbreak;\n\tcase CS8409_ODIN:\n\t\t/* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */\n\t\tcs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tcs42l42_resume(cs42l42);\n\n\t/* Enable Unsolicited Response */\n\tcs8409_enable_ur(codec, 1);\n}",
        "static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr)\n{\n\tu64 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);\n\tu64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST);\n\tu16 cgx_chans, lbk_chans, sdp_chans, cpt_chans;": "static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr)\n{\n\tu64 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);\n\tu64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST);\n\tu16 cgx_chans, lbk_chans, sdp_chans, cpt_chans;\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tint link, nix_link = 0;\n\tu16 start;\n\tu64 cfg;\n\n\tcgx_chans = nix_const & 0xFFULL;\n\tlbk_chans = (nix_const >> 16) & 0xFFULL;\n\tsdp_chans = nix_const1 & 0xFFFULL;\n\tcpt_chans = (nix_const >> 32) & 0xFFFULL;\n\n\tstart = hw->cgx_chan_base;\n\tfor (link = 0; link < hw->cgx_links; link++, nix_link++) {\n\t\tcfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));\n\t\tcfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cgx_chans));\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);\n\t\trvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);\n\t\tstart += cgx_chans;\n\t}\n\n\tstart = hw->lbk_chan_base;\n\tfor (link = 0; link < hw->lbk_links; link++, nix_link++) {\n\t\tcfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));\n\t\tcfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(lbk_chans));\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);\n\t\trvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);\n\t\tstart += lbk_chans;\n\t}\n\n\tstart = hw->sdp_chan_base;\n\tfor (link = 0; link < hw->sdp_links; link++, nix_link++) {\n\t\tcfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));\n\t\tcfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(sdp_chans));\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);\n\t\trvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);\n\t\tstart += sdp_chans;\n\t}\n\n\tstart = hw->cpt_chan_base;\n\tfor (link = 0; link < hw->cpt_links; link++, nix_link++) {\n\t\tcfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));\n\t\tcfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cpt_chans));\n\t\tcfg |=\tFIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);\n\t\trvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);\n\t\tstart += cpt_chans;\n\t}\n}",
        "static void tls_encrypt_done(struct crypto_async_request *req, int err)\n{\n\tstruct aead_request *aead_req = (struct aead_request *)req;\n\tstruct sock *sk = req->data;\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);": "static void tls_encrypt_done(struct crypto_async_request *req, int err)\n{\n\tstruct aead_request *aead_req = (struct aead_request *)req;\n\tstruct sock *sk = req->data;\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tstruct tls_sw_context_tx *ctx = tls_sw_ctx_tx(tls_ctx);\n\tstruct scatterlist *sge;\n\tstruct sk_msg *msg_en;\n\tstruct tls_rec *rec;\n\tbool ready = false;\n\tint pending;\n\n\trec = container_of(aead_req, struct tls_rec, aead_req);\n\tmsg_en = &rec->msg_encrypted;\n\n\tsge = sk_msg_elem(msg_en, msg_en->sg.curr);\n\tsge->offset -= prot->prepend_size;\n\tsge->length += prot->prepend_size;\n\n\t/* Check if error is previously set on socket */\n\tif (err || sk->sk_err) {\n\t\trec = NULL;\n\n\t\t/* If err is already set on socket, return the same code */\n\t\tif (sk->sk_err) {\n\t\t\tctx->async_wait.err = -sk->sk_err;\n\t\t} else {\n\t\t\tctx->async_wait.err = err;\n\t\t\ttls_err_abort(sk, err);\n\t\t}\n\t}\n\n\tif (rec) {\n\t\tstruct tls_rec *first_rec;\n\n\t\t/* Mark the record as ready for transmission */\n\t\tsmp_store_mb(rec->tx_ready, true);\n\n\t\t/* If received record is at head of tx_list, schedule tx */\n\t\tfirst_rec = list_first_entry(&ctx->tx_list,\n\t\t\t\t\t     struct tls_rec, list);\n\t\tif (rec == first_rec)\n\t\t\tready = true;\n\t}\n\n\tspin_lock_bh(&ctx->encrypt_compl_lock);\n\tpending = atomic_dec_return(&ctx->encrypt_pending);\n\n\tif (!pending && ctx->async_notify)\n\t\tcomplete(&ctx->async_wait.completion);\n\tspin_unlock_bh(&ctx->encrypt_compl_lock);\n\n\tif (!ready)\n\t\treturn;\n\n\t/* Schedule the transmission */\n\tif (!test_and_set_bit(BIT_TX_SCHEDULED, &ctx->tx_bitmask))\n\t\tschedule_delayed_work(&ctx->tx_work.work, 1);\n}",
        "static int mlx90632_calc_object_dsp105(struct mlx90632_data *data, int *val)\n{\n\ts32 ret;\n\ts32 Ea, Eb, Fa, Fb, Ga;\n\tunsigned int read_tmp;": "static int mlx90632_calc_object_dsp105(struct mlx90632_data *data, int *val)\n{\n\ts32 ret;\n\ts32 Ea, Eb, Fa, Fb, Ga;\n\tunsigned int read_tmp;\n\ts16 Ha, Hb, Gb, Ka;\n\ts16 ambient_new_raw, ambient_old_raw, object_new_raw, object_old_raw;\n\ts64 object, ambient;\n\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Ea, &Ea);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Eb, &Eb);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Fa, &Fa);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Fb, &Fb);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Ga, &Ga);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = regmap_read(data->regmap, MLX90632_EE_Ha, &read_tmp);\n\tif (ret < 0)\n\t\treturn ret;\n\tHa = (s16)read_tmp;\n\tret = regmap_read(data->regmap, MLX90632_EE_Hb, &read_tmp);\n\tif (ret < 0)\n\t\treturn ret;\n\tHb = (s16)read_tmp;\n\tret = regmap_read(data->regmap, MLX90632_EE_Gb, &read_tmp);\n\tif (ret < 0)\n\t\treturn ret;\n\tGb = (s16)read_tmp;\n\tret = regmap_read(data->regmap, MLX90632_EE_Ka, &read_tmp);\n\tif (ret < 0)\n\t\treturn ret;\n\tKa = (s16)read_tmp;\n\n\tret = mlx90632_read_all_channel(data,\n\t\t\t\t\t&ambient_new_raw, &ambient_old_raw,\n\t\t\t\t\t&object_new_raw, &object_old_raw);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tif (object_new_raw > MLX90632_EXTENDED_LIMIT &&\n\t    data->mtyp == MLX90632_MTYP_EXTENDED) {\n\t\tret = mlx90632_read_all_channel_extended(data, &object_new_raw,\n\t\t\t\t\t\t\t &ambient_new_raw, &ambient_old_raw);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\t/* Use extended mode calculations */\n\t\tambient = mlx90632_preprocess_temp_amb(ambient_new_raw,\n\t\t\t\t\t\t       ambient_old_raw, Gb);\n\t\tobject = mlx90632_preprocess_temp_obj_extended(object_new_raw,\n\t\t\t\t\t\t\t       ambient_new_raw,\n\t\t\t\t\t\t\t       ambient_old_raw, Ka);\n\t\t*val = mlx90632_calc_temp_object_extended(object, ambient,\n\t\t\t\t\t\t\t  data->object_ambient_temperature,\n\t\t\t\t\t\t\t  Ea, Eb, Fa, Fb, Ga,\n\t\t\t\t\t\t\t  Ha, Hb, data->emissivity);\n\t\treturn 0;\n\t}\n\n\tambient = mlx90632_preprocess_temp_amb(ambient_new_raw,\n\t\t\t\t\t       ambient_old_raw, Gb);\n\tobject = mlx90632_preprocess_temp_obj(object_new_raw,\n\t\t\t\t\t      object_old_raw,\n\t\t\t\t\t      ambient_new_raw,\n\t\t\t\t\t      ambient_old_raw, Ka);\n\n\t*val = mlx90632_calc_temp_object(object, ambient, Ea, Eb, Fa, Fb, Ga,\n\t\t\t\t\t Ha, Hb, data->emissivity);\n\treturn 0;\n}",
        "static const char *btf_show_name(struct btf_show *show)\n{\n\t/* BTF_MAX_ITER array suffixes \"[]\" */\n\tconst char *array_suffixes = \"[][][][][][][][][][]\";\n\tconst char *array_suffix = &array_suffixes[strlen(array_suffixes)];": "static const char *btf_show_name(struct btf_show *show)\n{\n\t/* BTF_MAX_ITER array suffixes \"[]\" */\n\tconst char *array_suffixes = \"[][][][][][][][][][]\";\n\tconst char *array_suffix = &array_suffixes[strlen(array_suffixes)];\n\t/* BTF_MAX_ITER pointer suffixes \"*\" */\n\tconst char *ptr_suffixes = \"**********\";\n\tconst char *ptr_suffix = &ptr_suffixes[strlen(ptr_suffixes)];\n\tconst char *name = NULL, *prefix = \"\", *parens = \"\";\n\tconst struct btf_member *m = show->state.member;\n\tconst struct btf_type *t;\n\tconst struct btf_array *array;\n\tu32 id = show->state.type_id;\n\tconst char *member = NULL;\n\tbool show_member = false;\n\tu64 kinds = 0;\n\tint i;\n\n\tshow->state.name[0] = '\\0';\n\n\t/*\n\t * Don't show type name if we're showing an array member;\n\t * in that case we show the array type so don't need to repeat\n\t * ourselves for each member.\n\t */\n\tif (show->state.array_member)\n\t\treturn \"\";\n\n\t/* Retrieve member name, if any. */\n\tif (m) {\n\t\tmember = btf_name_by_offset(show->btf, m->name_off);\n\t\tshow_member = strlen(member) > 0;\n\t\tid = m->type;\n\t}\n\n\t/*\n\t * Start with type_id, as we have resolved the struct btf_type *\n\t * via btf_modifier_show() past the parent typedef to the child\n\t * struct, int etc it is defined as.  In such cases, the type_id\n\t * still represents the starting type while the struct btf_type *\n\t * in our show->state points at the resolved type of the typedef.\n\t */\n\tt = btf_type_by_id(show->btf, id);\n\tif (!t)\n\t\treturn \"\";\n\n\t/*\n\t * The goal here is to build up the right number of pointer and\n\t * array suffixes while ensuring the type name for a typedef\n\t * is represented.  Along the way we accumulate a list of\n\t * BTF kinds we have encountered, since these will inform later\n\t * display; for example, pointer types will not require an\n\t * opening \"{\" for struct, we will just display the pointer value.\n\t *\n\t * We also want to accumulate the right number of pointer or array\n\t * indices in the format string while iterating until we get to\n\t * the typedef/pointee/array member target type.\n\t *\n\t * We start by pointing at the end of pointer and array suffix\n\t * strings; as we accumulate pointers and arrays we move the pointer\n\t * or array string backwards so it will show the expected number of\n\t * '*' or '[]' for the type.  BTF_SHOW_MAX_ITER of nesting of pointers\n\t * and/or arrays and typedefs are supported as a precaution.\n\t *\n\t * We also want to get typedef name while proceeding to resolve\n\t * type it points to so that we can add parentheses if it is a\n\t * \"typedef struct\" etc.\n\t */\n\tfor (i = 0; i < BTF_SHOW_MAX_ITER; i++) {\n\n\t\tswitch (BTF_INFO_KIND(t->info)) {\n\t\tcase BTF_KIND_TYPEDEF:\n\t\t\tif (!name)\n\t\t\t\tname = btf_name_by_offset(show->btf,\n\t\t\t\t\t\t\t       t->name_off);\n\t\t\tkinds |= BTF_KIND_BIT(BTF_KIND_TYPEDEF);\n\t\t\tid = t->type;\n\t\t\tbreak;\n\t\tcase BTF_KIND_ARRAY:\n\t\t\tkinds |= BTF_KIND_BIT(BTF_KIND_ARRAY);\n\t\t\tparens = \"[\";\n\t\t\tif (!t)\n\t\t\t\treturn \"\";\n\t\t\tarray = btf_type_array(t);\n\t\t\tif (array_suffix > array_suffixes)\n\t\t\t\tarray_suffix -= 2;\n\t\t\tid = array->type;\n\t\t\tbreak;\n\t\tcase BTF_KIND_PTR:\n\t\t\tkinds |= BTF_KIND_BIT(BTF_KIND_PTR);\n\t\t\tif (ptr_suffix > ptr_suffixes)\n\t\t\t\tptr_suffix -= 1;\n\t\t\tid = t->type;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tid = 0;\n\t\t\tbreak;\n\t\t}\n\t\tif (!id)\n\t\t\tbreak;\n\t\tt = btf_type_skip_qualifiers(show->btf, id);\n\t}\n\t/* We may not be able to represent this type; bail to be safe */\n\tif (i == BTF_SHOW_MAX_ITER)\n\t\treturn \"\";\n\n\tif (!name)\n\t\tname = btf_name_by_offset(show->btf, t->name_off);\n\n\tswitch (BTF_INFO_KIND(t->info)) {\n\tcase BTF_KIND_STRUCT:\n\tcase BTF_KIND_UNION:\n\t\tprefix = BTF_INFO_KIND(t->info) == BTF_KIND_STRUCT ?\n\t\t\t \"struct\" : \"union\";\n\t\t/* if it's an array of struct/union, parens is already set */\n\t\tif (!(kinds & (BTF_KIND_BIT(BTF_KIND_ARRAY))))\n\t\t\tparens = \"{\";\n\t\tbreak;\n\tcase BTF_KIND_ENUM:\n\t\tprefix = \"enum\";\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* pointer does not require parens */\n\tif (kinds & BTF_KIND_BIT(BTF_KIND_PTR))\n\t\tparens = \"\";\n\t/* typedef does not require struct/union/enum prefix */\n\tif (kinds & BTF_KIND_BIT(BTF_KIND_TYPEDEF))\n\t\tprefix = \"\";\n\n\tif (!name)\n\t\tname = \"\";\n\n\t/* Even if we don't want type name info, we want parentheses etc */\n\tif (show->flags & BTF_SHOW_NONAME)\n\t\tsnprintf(show->state.name, sizeof(show->state.name), \"%s\",\n\t\t\t parens);\n\telse\n\t\tsnprintf(show->state.name, sizeof(show->state.name),\n\t\t\t \"%s%s%s(%s%s%s%s%s%s)%s\",\n\t\t\t /* first 3 strings comprise \".member = \" */\n\t\t\t show_member ? \".\" : \"\",\n\t\t\t show_member ? member : \"\",\n\t\t\t show_member ? \" = \" : \"\",\n\t\t\t /* ...next is our prefix (struct, enum, etc) */\n\t\t\t prefix,\n\t\t\t strlen(prefix) > 0 && strlen(name) > 0 ? \" \" : \"\",\n\t\t\t /* ...this is the type name itself */\n\t\t\t name,\n\t\t\t /* ...suffixed by the appropriate '*', '[]' suffixes */\n\t\t\t strlen(ptr_suffix) > 0 ? \" \" : \"\", ptr_suffix,\n\t\t\t array_suffix, parens);\n\n\treturn show->state.name;\n}",
        "static int start(struct dvb_frontend *fe, u32 flags, u32 modmask, u32 ts_config)\n{\n\tstruct sx8 *state = fe->demodulator_priv;\n\tstruct mci_base *mci_base = state->mci.base;\n\tstruct sx8_base *sx8_base = (struct sx8_base *)mci_base;": "static int start(struct dvb_frontend *fe, u32 flags, u32 modmask, u32 ts_config)\n{\n\tstruct sx8 *state = fe->demodulator_priv;\n\tstruct mci_base *mci_base = state->mci.base;\n\tstruct sx8_base *sx8_base = (struct sx8_base *)mci_base;\n\tstruct dtv_frontend_properties *p = &fe->dtv_property_cache;\n\tu32 used_ldpc_bitrate = 0, free_ldpc_bitrate;\n\tu32 used_demods = 0;\n\tstruct mci_command cmd;\n\tu32 input = state->mci.tuner;\n\tu32 bits_per_symbol = 0;\n\tint i = -1, stat = 0;\n\n\tif (p->symbol_rate >= (MCLK / 2))\n\t\tflags &= ~1;\n\tif ((flags & 3) == 0)\n\t\treturn -EINVAL;\n\n\tif (flags & 2) {\n\t\tu32 tmp = modmask;\n\n\t\tbits_per_symbol = 1;\n\t\twhile (tmp & 1) {\n\t\t\ttmp >>= 1;\n\t\t\tbits_per_symbol++;\n\t\t}\n\t}\n\n\tmutex_lock(&mci_base->tuner_lock);\n\tif (sx8_base->iq_mode) {\n\t\tstat = -EBUSY;\n\t\tgoto unlock;\n\t}\n\n\tif (sx8_base->direct_mode) {\n\t\tif (p->symbol_rate >= MCLK / 2) {\n\t\t\tif (state->mci.nr < 4)\n\t\t\t\ti = state->mci.nr;\n\t\t} else {\n\t\t\ti = state->mci.nr;\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < SX8_DEMOD_NUM; i++) {\n\t\t\tused_ldpc_bitrate += sx8_base->used_ldpc_bitrate[i];\n\t\t\tif (sx8_base->demod_in_use[i])\n\t\t\t\tused_demods++;\n\t\t}\n\t\tif (used_ldpc_bitrate >= MAX_LDPC_BITRATE ||\n\t\t    ((ts_config & SX8_TSCONFIG_MODE_MASK) >\n\t\t     SX8_TSCONFIG_MODE_NORMAL && used_demods > 0)) {\n\t\t\tstat = -EBUSY;\n\t\t\tgoto unlock;\n\t\t}\n\t\tfree_ldpc_bitrate = MAX_LDPC_BITRATE - used_ldpc_bitrate;\n\t\tif (free_ldpc_bitrate > MAX_DEMOD_LDPC_BITRATE)\n\t\t\tfree_ldpc_bitrate = MAX_DEMOD_LDPC_BITRATE;\n\n\t\twhile (p->symbol_rate * bits_per_symbol > free_ldpc_bitrate)\n\t\t\tbits_per_symbol--;\n\t\tif (bits_per_symbol < 2) {\n\t\t\tstat = -EBUSY;\n\t\t\tgoto unlock;\n\t\t}\n\n\t\tmodmask &= ((1 << (bits_per_symbol - 1)) - 1);\n\t\tif (((flags & 0x02) != 0) && modmask == 0) {\n\t\t\tstat = -EBUSY;\n\t\t\tgoto unlock;\n\t\t}\n\n\t\ti = (p->symbol_rate > (MCLK / 2)) ? 3 : 7;\n\t\twhile (i >= 0 && sx8_base->demod_in_use[i])\n\t\t\ti--;\n\t}\n\n\tif (i < 0) {\n\t\tstat = -EBUSY;\n\t\tgoto unlock;\n\t}\n\tsx8_base->demod_in_use[i] = 1;\n\tsx8_base->used_ldpc_bitrate[state->mci.nr] = p->symbol_rate\n\t\t\t\t\t\t     * bits_per_symbol;\n\tstate->mci.demod = i;\n\n\tif (!sx8_base->tuner_use_count[input])\n\t\tmci_set_tuner(fe, input, 1);\n\tsx8_base->tuner_use_count[input]++;\n\tsx8_base->iq_mode = (ts_config > 1);\nunlock:\n\tmutex_unlock(&mci_base->tuner_lock);\n\tif (stat)\n\t\treturn stat;\n\tmemset(&cmd, 0, sizeof(cmd));\n\n\tif (sx8_base->iq_mode) {\n\t\tcmd.command = SX8_CMD_ENABLE_IQOUTPUT;\n\t\tcmd.demod = state->mci.demod;\n\t\tcmd.output = 0;\n\t\tddb_mci_cmd(&state->mci, &cmd, NULL);\n\t\tddb_mci_config(&state->mci, ts_config);\n\t}\n\tif (p->stream_id != NO_STREAM_ID_FILTER && p->stream_id != 0x80000000)\n\t\tflags |= 0x80;\n\tdev_dbg(mci_base->dev, \"MCI-%d: tuner=%d demod=%d\\n\",\n\t\tstate->mci.nr, state->mci.tuner, state->mci.demod);\n\tcmd.command = MCI_CMD_SEARCH_DVBS;\n\tcmd.dvbs2_search.flags = flags;\n\tcmd.dvbs2_search.s2_modulation_mask = modmask;\n\tcmd.dvbs2_search.retry = 2;\n\tcmd.dvbs2_search.frequency = p->frequency * 1000;\n\tcmd.dvbs2_search.symbol_rate = p->symbol_rate;\n\tcmd.dvbs2_search.scrambling_sequence_index =\n\t\tp->scrambling_sequence_index | 0x80000000;\n\tcmd.dvbs2_search.input_stream_id =\n\t\t(p->stream_id != NO_STREAM_ID_FILTER) ? p->stream_id : 0;\n\tcmd.tuner = state->mci.tuner;\n\tcmd.demod = state->mci.demod;\n\tcmd.output = state->mci.nr;\n\tif (p->stream_id == 0x80000000)\n\t\tcmd.output |= 0x80;\n\tstat = ddb_mci_cmd(&state->mci, &cmd, NULL);\n\tif (stat)\n\t\tstop(fe);\n\treturn stat;\n}",
        "static void test_ip6vxlan_tunnel(void)\n{\n\tstruct test_tunnel_kern *skel = NULL;\n\tstruct nstoken *nstoken;\n\tint local_ip_map_fd = -1;": "static void test_ip6vxlan_tunnel(void)\n{\n\tstruct test_tunnel_kern *skel = NULL;\n\tstruct nstoken *nstoken;\n\tint local_ip_map_fd = -1;\n\tint set_src_prog_fd, get_src_prog_fd;\n\tint set_dst_prog_fd;\n\tint key = 0, ifindex = -1;\n\tuint local_ip;\n\tint err;\n\tDECLARE_LIBBPF_OPTS(bpf_tc_hook, tc_hook,\n\t\t\t    .attach_point = BPF_TC_INGRESS);\n\n\t/* add vxlan tunnel */\n\terr = add_ip6vxlan_tunnel();\n\tif (!ASSERT_OK(err, \"add_ip6vxlan_tunnel\"))\n\t\tgoto done;\n\n\t/* load and attach bpf prog to tunnel dev tc hook point */\n\tskel = test_tunnel_kern__open_and_load();\n\tif (!ASSERT_OK_PTR(skel, \"test_tunnel_kern__open_and_load\"))\n\t\tgoto done;\n\tifindex = if_nametoindex(IP6VXLAN_TUNL_DEV1);\n\tif (!ASSERT_NEQ(ifindex, 0, \"ip6vxlan11 ifindex\"))\n\t\tgoto done;\n\ttc_hook.ifindex = ifindex;\n\tget_src_prog_fd = bpf_program__fd(skel->progs.ip6vxlan_get_tunnel_src);\n\tset_src_prog_fd = bpf_program__fd(skel->progs.ip6vxlan_set_tunnel_src);\n\tif (!ASSERT_GE(set_src_prog_fd, 0, \"bpf_program__fd\"))\n\t\tgoto done;\n\tif (!ASSERT_GE(get_src_prog_fd, 0, \"bpf_program__fd\"))\n\t\tgoto done;\n\tif (attach_tc_prog(&tc_hook, get_src_prog_fd, set_src_prog_fd))\n\t\tgoto done;\n\n\t/* load and attach prog set_md to tunnel dev tc hook point at_ns0 */\n\tnstoken = open_netns(\"at_ns0\");\n\tif (!ASSERT_OK_PTR(nstoken, \"setns src\"))\n\t\tgoto done;\n\tifindex = if_nametoindex(IP6VXLAN_TUNL_DEV0);\n\tif (!ASSERT_NEQ(ifindex, 0, \"ip6vxlan00 ifindex\"))\n\t\tgoto done;\n\ttc_hook.ifindex = ifindex;\n\tset_dst_prog_fd = bpf_program__fd(skel->progs.ip6vxlan_set_tunnel_dst);\n\tif (!ASSERT_GE(set_dst_prog_fd, 0, \"bpf_program__fd\"))\n\t\tgoto done;\n\tif (attach_tc_prog(&tc_hook, -1, set_dst_prog_fd))\n\t\tgoto done;\n\tclose_netns(nstoken);\n\n\t/* use veth1 ip 2 as tunnel source ip */\n\tlocal_ip_map_fd = bpf_map__fd(skel->maps.local_ip_map);\n\tif (!ASSERT_GE(local_ip_map_fd, 0, \"get local_ip_map fd\"))\n\t\tgoto done;\n\tlocal_ip = IP6_ADDR2_HEX_VETH1;\n\terr = bpf_map_update_elem(local_ip_map_fd, &key, &local_ip, BPF_ANY);\n\tif (!ASSERT_OK(err, \"update bpf local_ip_map\"))\n\t\tgoto done;\n\n\t/* ping test */\n\terr = test_ping(AF_INET, IP4_ADDR_TUNL_DEV0);\n\tif (!ASSERT_OK(err, \"test_ping\"))\n\t\tgoto done;\n\ndone:\n\t/* delete ipv6 vxlan tunnel */\n\tdelete_ip6vxlan_tunnel();\n\tif (local_ip_map_fd >= 0)\n\t\tclose(local_ip_map_fd);\n\tif (skel)\n\t\ttest_tunnel_kern__destroy(skel);\n}",
        "static int mtdswap_wlfreq(unsigned int maxdiff)\n{\n\tunsigned int h, x, y, dist, base;\n\n\t/*": "static int mtdswap_wlfreq(unsigned int maxdiff)\n{\n\tunsigned int h, x, y, dist, base;\n\n\t/*\n\t * Calculate linear ramp down from f1 to f2 when maxdiff goes from\n\t * MAX_ERASE_DIFF to MAX_ERASE_DIFF + COLLECT_NONDIRTY_BASE.  Similar\n\t * to triangle with height f1 - f1 and width COLLECT_NONDIRTY_BASE.\n\t */\n\n\tdist = maxdiff - MAX_ERASE_DIFF;\n\tif (dist > COLLECT_NONDIRTY_BASE)\n\t\tdist = COLLECT_NONDIRTY_BASE;\n\n\t/*\n\t * Modelling the slop as right angular triangle with base\n\t * COLLECT_NONDIRTY_BASE and height freq1 - freq2. The ratio y/x is\n\t * equal to the ratio h/base.\n\t */\n\th = COLLECT_NONDIRTY_FREQ1 - COLLECT_NONDIRTY_FREQ2;\n\tbase = COLLECT_NONDIRTY_BASE;\n\n\tx = dist - base;\n\ty = (x * h + base / 2) / base;\n\n\treturn COLLECT_NONDIRTY_FREQ2 + y;\n}",
        "static int __tcf_idr_release(struct tc_action *p, bool bind, bool strict)\n{\n\tint ret = 0;\n\n\t/* Release with strict==1 and bind==0 is only called through act API": "static int __tcf_idr_release(struct tc_action *p, bool bind, bool strict)\n{\n\tint ret = 0;\n\n\t/* Release with strict==1 and bind==0 is only called through act API\n\t * interface (classifiers always bind). Only case when action with\n\t * positive reference count and zero bind count can exist is when it was\n\t * also created with act API (unbinding last classifier will destroy the\n\t * action if it was created by classifier). So only case when bind count\n\t * can be changed after initial check is when unbound action is\n\t * destroyed by act API while classifier binds to action with same id\n\t * concurrently. This result either creation of new action(same behavior\n\t * as before), or reusing existing action if concurrent process\n\t * increments reference count before action is deleted. Both scenarios\n\t * are acceptable.\n\t */\n\tif (p) {\n\t\tif (!bind && strict && atomic_read(&p->tcfa_bindcnt) > 0)\n\t\t\treturn -EPERM;\n\n\t\tif (__tcf_action_put(p, bind))\n\t\t\tret = ACT_P_DELETED;\n\t}\n\n\treturn ret;\n}",
        "static int do_sched_rt_period_timer(struct rt_bandwidth *rt_b, int overrun)\n{\n\tint i, idle = 1, throttled = 0;\n\tconst struct cpumask *span;\n": "static int do_sched_rt_period_timer(struct rt_bandwidth *rt_b, int overrun)\n{\n\tint i, idle = 1, throttled = 0;\n\tconst struct cpumask *span;\n\n\tspan = sched_rt_period_mask();\n#ifdef CONFIG_RT_GROUP_SCHED\n\t/*\n\t * FIXME: isolated CPUs should really leave the root task group,\n\t * whether they are isolcpus or were isolated via cpusets, lest\n\t * the timer run on a CPU which does not service all runqueues,\n\t * potentially leaving other CPUs indefinitely throttled.  If\n\t * isolation is really required, the user will turn the throttle\n\t * off to kill the perturbations it causes anyway.  Meanwhile,\n\t * this maintains functionality for boot and/or troubleshooting.\n\t */\n\tif (rt_b == &root_task_group.rt_bandwidth)\n\t\tspan = cpu_online_mask;\n#endif\n\tfor_each_cpu(i, span) {\n\t\tint enqueue = 0;\n\t\tstruct rt_rq *rt_rq = sched_rt_period_rt_rq(rt_b, i);\n\t\tstruct rq *rq = rq_of_rt_rq(rt_rq);\n\t\tstruct rq_flags rf;\n\t\tint skip;\n\n\t\t/*\n\t\t * When span == cpu_online_mask, taking each rq->lock\n\t\t * can be time-consuming. Try to avoid it when possible.\n\t\t */\n\t\traw_spin_lock(&rt_rq->rt_runtime_lock);\n\t\tif (!sched_feat(RT_RUNTIME_SHARE) && rt_rq->rt_runtime != RUNTIME_INF)\n\t\t\trt_rq->rt_runtime = rt_b->rt_runtime;\n\t\tskip = !rt_rq->rt_time && !rt_rq->rt_nr_running;\n\t\traw_spin_unlock(&rt_rq->rt_runtime_lock);\n\t\tif (skip)\n\t\t\tcontinue;\n\n\t\trq_lock(rq, &rf);\n\t\tupdate_rq_clock(rq);\n\n\t\tif (rt_rq->rt_time) {\n\t\t\tu64 runtime;\n\n\t\t\traw_spin_lock(&rt_rq->rt_runtime_lock);\n\t\t\tif (rt_rq->rt_throttled)\n\t\t\t\tbalance_runtime(rt_rq);\n\t\t\truntime = rt_rq->rt_runtime;\n\t\t\trt_rq->rt_time -= min(rt_rq->rt_time, overrun*runtime);\n\t\t\tif (rt_rq->rt_throttled && rt_rq->rt_time < runtime) {\n\t\t\t\trt_rq->rt_throttled = 0;\n\t\t\t\tenqueue = 1;\n\n\t\t\t\t/*\n\t\t\t\t * When we're idle and a woken (rt) task is\n\t\t\t\t * throttled check_preempt_curr() will set\n\t\t\t\t * skip_update and the time between the wakeup\n\t\t\t\t * and this unthrottle will get accounted as\n\t\t\t\t * 'runtime'.\n\t\t\t\t */\n\t\t\t\tif (rt_rq->rt_nr_running && rq->curr == rq->idle)\n\t\t\t\t\trq_clock_cancel_skipupdate(rq);\n\t\t\t}\n\t\t\tif (rt_rq->rt_time || rt_rq->rt_nr_running)\n\t\t\t\tidle = 0;\n\t\t\traw_spin_unlock(&rt_rq->rt_runtime_lock);\n\t\t} else if (rt_rq->rt_nr_running) {\n\t\t\tidle = 0;\n\t\t\tif (!rt_rq_throttled(rt_rq))\n\t\t\t\tenqueue = 1;\n\t\t}\n\t\tif (rt_rq->rt_throttled)\n\t\t\tthrottled = 1;\n\n\t\tif (enqueue)\n\t\t\tsched_rt_rq_enqueue(rt_rq);\n\t\trq_unlock(rq, &rf);\n\t}\n\n\tif (!throttled && (!rt_bandwidth_enabled() || rt_b->rt_runtime == RUNTIME_INF))\n\t\treturn 1;\n\n\treturn idle;\n}",
        "static int sm_check_block(struct sm_ftl *ftl, int zone, int block)\n{\n\tint boffset;\n\tstruct sm_oob oob;\n\tint lbas[] = { -3, 0, 0, 0 };": "static int sm_check_block(struct sm_ftl *ftl, int zone, int block)\n{\n\tint boffset;\n\tstruct sm_oob oob;\n\tint lbas[] = { -3, 0, 0, 0 };\n\tint i = 0;\n\tint test_lba;\n\n\n\t/* First just check that block doesn't look fishy */\n\t/* Only blocks that are valid or are sliced in two parts, are\n\t * accepted\n\t */\n\tfor (boffset = 0; boffset < ftl->block_size;\n\t\t\t\t\tboffset += SM_SECTOR_SIZE) {\n\n\t\t/* This shouldn't happen anyway */\n\t\tif (sm_read_sector(ftl, zone, block, boffset, NULL, &oob))\n\t\t\treturn -2;\n\n\t\ttest_lba = sm_read_lba(&oob);\n\n\t\tif (lbas[i] != test_lba)\n\t\t\tlbas[++i] = test_lba;\n\n\t\t/* If we found three different LBAs, something is fishy */\n\t\tif (i == 3)\n\t\t\treturn -EIO;\n\t}\n\n\t/* If the block is sliced (partially erased usually) erase it */\n\tif (i == 2) {\n\t\tsm_erase_block(ftl, zone, block, 1);\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}",
        "static int mot_setup(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    unsigned int ioaddr = dev->base_addr;\n    int i, wait, loop;": "static int mot_setup(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    unsigned int ioaddr = dev->base_addr;\n    int i, wait, loop;\n    u8 mac[ETH_ALEN];\n    u_int addr;\n\n    /* Read Ethernet address from Serial EEPROM */\n\n    for (i = 0; i < 3; i++) {\n\tSMC_SELECT_BANK(2);\n\toutw(MOT_EEPROM + i, ioaddr + POINTER);\n\tSMC_SELECT_BANK(1);\n\toutw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL);\n\n\tfor (loop = wait = 0; loop < 200; loop++) {\n\t    udelay(10);\n\t    wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL));\n\t    if (wait == 0) break;\n\t}\n\t\n\tif (wait)\n\t    return -1;\n\t\n\taddr = inw(ioaddr + GENERAL);\n\tmac[2*i]   = addr & 0xff;\n\tmac[2*i+1] = (addr >> 8) & 0xff;\n    }\n    eth_hw_addr_set(dev, mac);\n\n    return 0;\n}",
        "static void smc_llc_process_cli_delete_link(struct smc_link_group *lgr)\n{\n\tstruct smc_link *lnk_del = NULL, *lnk_asym, *lnk;\n\tstruct smc_llc_msg_del_link *del_llc;\n\tstruct smc_llc_qentry *qentry;": "static void smc_llc_process_cli_delete_link(struct smc_link_group *lgr)\n{\n\tstruct smc_link *lnk_del = NULL, *lnk_asym, *lnk;\n\tstruct smc_llc_msg_del_link *del_llc;\n\tstruct smc_llc_qentry *qentry;\n\tint active_links;\n\tint lnk_idx;\n\n\tqentry = smc_llc_flow_qentry_clr(&lgr->llc_flow_lcl);\n\tlnk = qentry->link;\n\tdel_llc = &qentry->msg.delete_link;\n\n\tif (del_llc->hd.flags & SMC_LLC_FLAG_DEL_LINK_ALL) {\n\t\tsmc_lgr_terminate_sched(lgr);\n\t\tgoto out;\n\t}\n\tmutex_lock(&lgr->llc_conf_mutex);\n\t/* delete single link */\n\tfor (lnk_idx = 0; lnk_idx < SMC_LINKS_PER_LGR_MAX; lnk_idx++) {\n\t\tif (lgr->lnk[lnk_idx].link_id != del_llc->link_num)\n\t\t\tcontinue;\n\t\tlnk_del = &lgr->lnk[lnk_idx];\n\t\tbreak;\n\t}\n\tdel_llc->hd.flags |= SMC_LLC_FLAG_RESP;\n\tif (!lnk_del) {\n\t\t/* link was not found */\n\t\tdel_llc->reason = htonl(SMC_LLC_DEL_NOLNK);\n\t\tsmc_llc_send_message(lnk, &qentry->msg);\n\t\tgoto out_unlock;\n\t}\n\tlnk_asym = smc_llc_find_asym_link(lgr);\n\n\tdel_llc->reason = 0;\n\tsmc_llc_send_message(lnk, &qentry->msg); /* response */\n\n\tif (smc_link_downing(&lnk_del->state))\n\t\tsmc_switch_conns(lgr, lnk_del, false);\n\tsmcr_link_clear(lnk_del, true);\n\n\tactive_links = smc_llc_active_link_count(lgr);\n\tif (lnk_del == lnk_asym) {\n\t\t/* expected deletion of asym link, don't change lgr state */\n\t} else if (active_links == 1) {\n\t\tsmcr_lgr_set_type(lgr, SMC_LGR_SINGLE);\n\t} else if (!active_links) {\n\t\tsmcr_lgr_set_type(lgr, SMC_LGR_NONE);\n\t\tsmc_lgr_terminate_sched(lgr);\n\t}\nout_unlock:\n\tmutex_unlock(&lgr->llc_conf_mutex);\nout:\n\tkfree(qentry);\n}",
        "static int ds_set_pullup(struct ds_device *dev, int delay)\n{\n\tint err = 0;\n\tu8 del = 1 + (u8)(delay >> 4);\n\t/* Just storing delay would not get the trunication and roundup. */": "static int ds_set_pullup(struct ds_device *dev, int delay)\n{\n\tint err = 0;\n\tu8 del = 1 + (u8)(delay >> 4);\n\t/* Just storing delay would not get the trunication and roundup. */\n\tint ms = del<<4;\n\n\t/* Enable spu_bit if a delay is set. */\n\tdev->spu_bit = delay ? COMM_SPU : 0;\n\t/* If delay is zero, it has already been disabled, if the time is\n\t * the same as the hardware was last programmed to, there is also\n\t * nothing more to do.  Compare with the recalculated value ms\n\t * rather than del or delay which can have a different value.\n\t */\n\tif (delay == 0 || ms == dev->spu_sleep)\n\t\treturn err;\n\n\terr = ds_send_control(dev, COMM_SET_DURATION | COMM_IM, del);\n\tif (err)\n\t\treturn err;\n\n\tdev->spu_sleep = ms;\n\n\treturn err;\n}",
        "static void test_setsockopt_default_zero_and_set(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_get_retval = NULL, *link_set_eunatch = NULL;\n": "static void test_setsockopt_default_zero_and_set(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_get_retval = NULL, *link_set_eunatch = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that gets the previously set errno, and then\n\t * one that sets the errno to EUNATCH. Assert that the get does not\n\t * see EUNATCH set later, and does not prevent EUNATCH from being set.\n\t */\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\tlink_set_eunatch = bpf_program__attach_cgroup(obj->progs.set_eunatch,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eunatch, \"cg-attach-set_eunatch\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t   &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EUNATCH, \"setsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 2, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, 0, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_get_retval);\n\tbpf_link__destroy(link_set_eunatch);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static void isotp_rcv(struct sk_buff *skb, void *data)\n{\n\tstruct sock *sk = (struct sock *)data;\n\tstruct isotp_sock *so = isotp_sk(sk);\n\tstruct canfd_frame *cf;": "static void isotp_rcv(struct sk_buff *skb, void *data)\n{\n\tstruct sock *sk = (struct sock *)data;\n\tstruct isotp_sock *so = isotp_sk(sk);\n\tstruct canfd_frame *cf;\n\tint ae = (so->opt.flags & CAN_ISOTP_EXTEND_ADDR) ? 1 : 0;\n\tu8 n_pci_type, sf_dl;\n\n\t/* Strictly receive only frames with the configured MTU size\n\t * => clear separation of CAN2.0 / CAN FD transport channels\n\t */\n\tif (skb->len != so->ll.mtu)\n\t\treturn;\n\n\tcf = (struct canfd_frame *)skb->data;\n\n\t/* if enabled: check reception of my configured extended address */\n\tif (ae && cf->data[0] != so->opt.rx_ext_address)\n\t\treturn;\n\n\tn_pci_type = cf->data[ae] & 0xF0;\n\n\t/* Make sure the state changes and data structures stay consistent at\n\t * CAN frame reception time. This locking is not needed in real world\n\t * use cases but the inconsistency can be triggered with syzkaller.\n\t */\n\tspin_lock(&so->rx_lock);\n\n\tif (so->opt.flags & CAN_ISOTP_HALF_DUPLEX) {\n\t\t/* check rx/tx path half duplex expectations */\n\t\tif ((so->tx.state != ISOTP_IDLE && n_pci_type != N_PCI_FC) ||\n\t\t    (so->rx.state != ISOTP_IDLE && n_pci_type == N_PCI_FC))\n\t\t\tgoto out_unlock;\n\t}\n\n\tswitch (n_pci_type) {\n\tcase N_PCI_FC:\n\t\t/* tx path: flow control frame containing the FC parameters */\n\t\tisotp_rcv_fc(so, cf, ae);\n\t\tbreak;\n\n\tcase N_PCI_SF:\n\t\t/* rx path: single frame\n\t\t *\n\t\t * As we do not have a rx.ll_dl configuration, we can only test\n\t\t * if the CAN frames payload length matches the LL_DL == 8\n\t\t * requirements - no matter if it's CAN 2.0 or CAN FD\n\t\t */\n\n\t\t/* get the SF_DL from the N_PCI byte */\n\t\tsf_dl = cf->data[ae] & 0x0F;\n\n\t\tif (cf->len <= CAN_MAX_DLEN) {\n\t\t\tisotp_rcv_sf(sk, cf, SF_PCI_SZ4 + ae, skb, sf_dl);\n\t\t} else {\n\t\t\tif (skb->len == CANFD_MTU) {\n\t\t\t\t/* We have a CAN FD frame and CAN_DL is greater than 8:\n\t\t\t\t * Only frames with the SF_DL == 0 ESC value are valid.\n\t\t\t\t *\n\t\t\t\t * If so take care of the increased SF PCI size\n\t\t\t\t * (SF_PCI_SZ8) to point to the message content behind\n\t\t\t\t * the extended SF PCI info and get the real SF_DL\n\t\t\t\t * length value from the formerly first data byte.\n\t\t\t\t */\n\t\t\t\tif (sf_dl == 0)\n\t\t\t\t\tisotp_rcv_sf(sk, cf, SF_PCI_SZ8 + ae, skb,\n\t\t\t\t\t\t     cf->data[SF_PCI_SZ4 + ae]);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase N_PCI_FF:\n\t\t/* rx path: first frame */\n\t\tisotp_rcv_ff(sk, cf, ae);\n\t\tbreak;\n\n\tcase N_PCI_CF:\n\t\t/* rx path: consecutive frame */\n\t\tisotp_rcv_cf(sk, cf, ae, skb);\n\t\tbreak;\n\t}\n\nout_unlock:\n\tspin_unlock(&so->rx_lock);\n}",
        "static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info)\n{\n\t/* HW can verify IPv4/IPv6 TCP/UDP packets checksum\n\t * csum information provides in psdata[2] word:\n\t * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error": "static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info)\n{\n\t/* HW can verify IPv4/IPv6 TCP/UDP packets checksum\n\t * csum information provides in psdata[2] word:\n\t * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error\n\t * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID\n\t * bits - indicates IPv4/IPv6 packet\n\t * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet\n\t * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets\n\t * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR\n\t */\n\tskb_checksum_none_assert(skb);\n\n\tif (unlikely(!(skb->dev->features & NETIF_F_RXCSUM)))\n\t\treturn;\n\n\tif ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID |\n\t\t\t  AM65_CPSW_RX_PSD_IPV4_VALID)) &&\n\t\t\t  !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) {\n\t\t/* csum for fragmented packets is unsupported */\n\t\tif (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT))\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t}\n}",
        "static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tint rc;": "static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tint rc;\n\tu16 fec_oc_ipr_mode = 0;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\trc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* reset to default (normal bit order) */\n\tfec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);\n\n\tif (ext_attr->bit_reverse_mpeg_outout)\n\t\tfec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;\n\n\trc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void fdc_specify(int fdc, int drive)\n{\n\tunsigned char spec1;\n\tunsigned char spec2;\n\tunsigned long srt;": "static void fdc_specify(int fdc, int drive)\n{\n\tunsigned char spec1;\n\tunsigned char spec2;\n\tunsigned long srt;\n\tunsigned long hlt;\n\tunsigned long hut;\n\tunsigned long dtr = NOMINAL_DTR;\n\tunsigned long scale_dtr = NOMINAL_DTR;\n\tint hlt_max_code = 0x7f;\n\tint hut_max_code = 0xf;\n\n\tif (fdc_state[fdc].need_configure &&\n\t    fdc_state[fdc].version >= FDC_82072A) {\n\t\tfdc_configure(fdc);\n\t\tfdc_state[fdc].need_configure = 0;\n\t}\n\n\tswitch (raw_cmd->rate & 0x03) {\n\tcase 3:\n\t\tdtr = 1000;\n\t\tbreak;\n\tcase 1:\n\t\tdtr = 300;\n\t\tif (fdc_state[fdc].version >= FDC_82078) {\n\t\t\t/* chose the default rate table, not the one\n\t\t\t * where 1 = 2 Mbps */\n\t\t\toutput_byte(fdc, FD_DRIVESPEC);\n\t\t\tif (need_more_output(fdc) == MORE_OUTPUT) {\n\t\t\t\toutput_byte(fdc, UNIT(drive));\n\t\t\t\toutput_byte(fdc, 0xc0);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase 2:\n\t\tdtr = 250;\n\t\tbreak;\n\t}\n\n\tif (fdc_state[fdc].version >= FDC_82072) {\n\t\tscale_dtr = dtr;\n\t\thlt_max_code = 0x00;\t/* 0==256msec*dtr0/dtr (not linear!) */\n\t\thut_max_code = 0x0;\t/* 0==256msec*dtr0/dtr (not linear!) */\n\t}\n\n\t/* Convert step rate from microseconds to milliseconds and 4 bits */\n\tsrt = 16 - DIV_ROUND_UP(drive_params[drive].srt * scale_dtr / 1000,\n\t\t\t\tNOMINAL_DTR);\n\tif (slow_floppy)\n\t\tsrt = srt / 4;\n\n\tSUPBOUND(srt, 0xf);\n\tINFBOUND(srt, 0);\n\n\thlt = DIV_ROUND_UP(drive_params[drive].hlt * scale_dtr / 2,\n\t\t\t   NOMINAL_DTR);\n\tif (hlt < 0x01)\n\t\thlt = 0x01;\n\telse if (hlt > 0x7f)\n\t\thlt = hlt_max_code;\n\n\thut = DIV_ROUND_UP(drive_params[drive].hut * scale_dtr / 16,\n\t\t\t   NOMINAL_DTR);\n\tif (hut < 0x1)\n\t\thut = 0x1;\n\telse if (hut > 0xf)\n\t\thut = hut_max_code;\n\n\tspec1 = (srt << 4) | hut;\n\tspec2 = (hlt << 1) | (use_virtual_dma & 1);\n\n\t/* If these parameters did not change, just return with success */\n\tif (fdc_state[fdc].spec1 != spec1 ||\n\t    fdc_state[fdc].spec2 != spec2) {\n\t\t/* Go ahead and set spec1 and spec2 */\n\t\toutput_byte(fdc, FD_SPECIFY);\n\t\toutput_byte(fdc, fdc_state[fdc].spec1 = spec1);\n\t\toutput_byte(fdc, fdc_state[fdc].spec2 = spec2);\n\t}\n}\t\t\t\t/* fdc_specify */\n\n/* Set the FDC's data transfer rate on behalf of the specified drive.\n * NOTE: with 82072/82077 FDCs, changing the data rate requires a reissue\n * of the specify command (i.e. using the fdc_specify function).\n */\nstatic int fdc_dtr(void)\n{\n\t/* If data rate not already set to desired value, set it. */\n\tif ((raw_cmd->rate & 3) == fdc_state[current_fdc].dtr)\n\t\treturn 0;\n\n\t/* Set dtr */\n\tfdc_outb(raw_cmd->rate & 3, current_fdc, FD_DCR);\n\n\t/* TODO: some FDC/drive combinations (C&T 82C711 with TEAC 1.2MB)\n\t * need a stabilization period of several milliseconds to be\n\t * enforced after data rate changes before R/W operations.\n\t * Pause 5 msec to avoid trouble. (Needs to be 2 jiffies)\n\t */\n\tfdc_state[current_fdc].dtr = raw_cmd->rate & 3;\n\treturn fd_wait_for_completion(jiffies + 2UL * HZ / 100, floppy_ready);\n}\t\t\t\t/* fdc_dtr */\n\nstatic void tell_sector(void)\n{\n\tpr_cont(\": track %d, head %d, sector %d, size %d\",\n\t\treply_buffer[R_TRACK], reply_buffer[R_HEAD],\n\t\treply_buffer[R_SECTOR],\n\t\treply_buffer[R_SIZECODE]);\n}\t\t\t\t/* tell_sector */\n\nstatic void print_errors(void)\n{\n\tDPRINT(\"\");\n\tif (reply_buffer[ST0] & ST0_ECE) {\n\t\tpr_cont(\"Recalibrate failed!\");\n\t} else if (reply_buffer[ST2] & ST2_CRC) {\n\t\tpr_cont(\"data CRC error\");\n\t\ttell_sector();\n\t} else if (reply_buffer[ST1] & ST1_CRC) {\n\t\tpr_cont(\"CRC error\");\n\t\ttell_sector();\n\t} else if ((reply_buffer[ST1] & (ST1_MAM | ST1_ND)) ||\n\t\t   (reply_buffer[ST2] & ST2_MAM)) {\n\t\tif (!probing) {\n\t\t\tpr_cont(\"sector not found\");\n\t\t\ttell_sector();\n\t\t} else\n\t\t\tpr_cont(\"probe failed...\");\n\t} else if (reply_buffer[ST2] & ST2_WC) {\t/* seek error */\n\t\tpr_cont(\"wrong cylinder\");\n\t} else if (reply_buffer[ST2] & ST2_BC) {\t/* cylinder marked as bad */\n\t\tpr_cont(\"bad cylinder\");\n\t} else {\n\t\tpr_cont(\"unknown error. ST[0..2] are: 0x%x 0x%x 0x%x\",\n\t\t\treply_buffer[ST0], reply_buffer[ST1],\n\t\t\treply_buffer[ST2]);\n\t\ttell_sector();\n\t}\n\tpr_cont(\"\\n\");\n}",
        "static void ww_tests(void)\n{\n\tprintk(\"  --------------------------------------------------------------------------\\n\");\n\tprintk(\"  | Wound/wait tests |\\n\");\n\tprintk(\"  ---------------------\\n\");": "static void ww_tests(void)\n{\n\tprintk(\"  --------------------------------------------------------------------------\\n\");\n\tprintk(\"  | Wound/wait tests |\\n\");\n\tprintk(\"  ---------------------\\n\");\n\n\tprint_testname(\"ww api failures\");\n\tdotest(ww_test_fail_acquire, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_normal, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_unneeded_slow, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"ww contexts mixing\");\n\tdotest(ww_test_two_contexts, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_diff_class, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"finishing ww context\");\n\tdotest(ww_test_context_done_twice, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_context_unlock_twice, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_context_fini_early, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_context_lock_after_done, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"locking mismatches\");\n\tdotest(ww_test_object_unlock_twice, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_object_lock_unbalanced, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_object_lock_stale_context, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"EDEADLK handling\");\n\tdotest(ww_test_edeadlk_normal, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_normal_slow, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_no_unlock, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_no_unlock_slow, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_acquire_more, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_acquire_more_slow, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_acquire_more_edeadlk, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_acquire_more_edeadlk_slow, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_acquire_wrong, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_edeadlk_acquire_wrong_slow, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"spinlock nest unlocked\");\n\tdotest(ww_test_spin_nest_unlocked, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"spinlock nest test\");\n\tdotest(ww_test_spin_nest_lock, SUCCESS, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprintk(\"  -----------------------------------------------------\\n\");\n\tprintk(\"                                 |block | try  |context|\\n\");\n\tprintk(\"  -----------------------------------------------------\\n\");\n\n\tprint_testname(\"context\");\n\tdotest(ww_test_context_block, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_context_try, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_context_context, SUCCESS, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"try\");\n\tdotest(ww_test_try_block, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_try_try, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_try_context, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"block\");\n\tdotest(ww_test_block_block, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_block_try, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_block_context, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"spinlock\");\n\tdotest(ww_test_spin_block, FAILURE, LOCKTYPE_WW);\n\tdotest(ww_test_spin_try, SUCCESS, LOCKTYPE_WW);\n\tdotest(ww_test_spin_context, FAILURE, LOCKTYPE_WW);\n\tpr_cont(\"\\n\");\n}",
        "static void io_queue_iowq(struct io_kiocb *req, bool *dont_use)\n{\n\tstruct io_kiocb *link = io_prep_linked_timeout(req);\n\tstruct io_uring_task *tctx = req->task->io_uring;\n": "static void io_queue_iowq(struct io_kiocb *req, bool *dont_use)\n{\n\tstruct io_kiocb *link = io_prep_linked_timeout(req);\n\tstruct io_uring_task *tctx = req->task->io_uring;\n\n\tBUG_ON(!tctx);\n\tBUG_ON(!tctx->io_wq);\n\n\t/* init ->work of the whole link before punting */\n\tio_prep_async_link(req);\n\n\t/*\n\t * Not expected to happen, but if we do have a bug where this _can_\n\t * happen, catch it here and ensure the request is marked as\n\t * canceled. That will make io-wq go through the usual work cancel\n\t * procedure rather than attempt to run this request (or create a new\n\t * worker for it).\n\t */\n\tif (WARN_ON_ONCE(!same_thread_group(req->task, current)))\n\t\treq->work.flags |= IO_WQ_WORK_CANCEL;\n\n\ttrace_io_uring_queue_async_work(req->ctx, req, req->cqe.user_data,\n\t\t\t\t\treq->opcode, req->flags, &req->work,\n\t\t\t\t\tio_wq_is_hashed(&req->work));\n\tio_wq_enqueue(tctx->io_wq, &req->work);\n\tif (link)\n\t\tio_queue_linked_timeout(link);\n}",
        "static void niu_init_rx_xmac(struct niu *np)\n{\n\tstruct niu_parent *parent = np->parent;\n\tstruct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];\n\tint first_rdc_table = tp->first_table_num;": "static void niu_init_rx_xmac(struct niu *np)\n{\n\tstruct niu_parent *parent = np->parent;\n\tstruct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];\n\tint first_rdc_table = tp->first_table_num;\n\tunsigned long i;\n\tu64 val;\n\n\tnw64_mac(XMAC_ADD_FILT0, 0);\n\tnw64_mac(XMAC_ADD_FILT1, 0);\n\tnw64_mac(XMAC_ADD_FILT2, 0);\n\tnw64_mac(XMAC_ADD_FILT12_MASK, 0);\n\tnw64_mac(XMAC_ADD_FILT00_MASK, 0);\n\tfor (i = 0; i < MAC_NUM_HASH; i++)\n\t\tnw64_mac(XMAC_HASH_TBL(i), 0);\n\tnw64_mac(XRXMAC_STAT_MSK, ~(u64)0);\n\tniu_set_primary_mac_rdc_table(np, first_rdc_table, 1);\n\tniu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);\n\n\tval = nr64_mac(XMAC_CONFIG);\n\tval &= ~(XMAC_CONFIG_RX_MAC_ENABLE |\n\t\t XMAC_CONFIG_PROMISCUOUS |\n\t\t XMAC_CONFIG_PROMISC_GROUP |\n\t\t XMAC_CONFIG_ERR_CHK_DIS |\n\t\t XMAC_CONFIG_RX_CRC_CHK_DIS |\n\t\t XMAC_CONFIG_RESERVED_MULTICAST |\n\t\t XMAC_CONFIG_RX_CODEV_CHK_DIS |\n\t\t XMAC_CONFIG_ADDR_FILTER_EN |\n\t\t XMAC_CONFIG_RCV_PAUSE_ENABLE |\n\t\t XMAC_CONFIG_STRIP_CRC |\n\t\t XMAC_CONFIG_PASS_FLOW_CTRL |\n\t\t XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);\n\tval |= (XMAC_CONFIG_HASH_FILTER_EN);\n\tnw64_mac(XMAC_CONFIG, val);\n\n\tnw64_mac(RXMAC_BT_CNT, 0);\n\tnw64_mac(RXMAC_BC_FRM_CNT, 0);\n\tnw64_mac(RXMAC_MC_FRM_CNT, 0);\n\tnw64_mac(RXMAC_FRAG_CNT, 0);\n\tnw64_mac(RXMAC_HIST_CNT1, 0);\n\tnw64_mac(RXMAC_HIST_CNT2, 0);\n\tnw64_mac(RXMAC_HIST_CNT3, 0);\n\tnw64_mac(RXMAC_HIST_CNT4, 0);\n\tnw64_mac(RXMAC_HIST_CNT5, 0);\n\tnw64_mac(RXMAC_HIST_CNT6, 0);\n\tnw64_mac(RXMAC_HIST_CNT7, 0);\n\tnw64_mac(RXMAC_MPSZER_CNT, 0);\n\tnw64_mac(RXMAC_CRC_ER_CNT, 0);\n\tnw64_mac(RXMAC_CD_VIO_CNT, 0);\n\tnw64_mac(LINK_FAULT_CNT, 0);\n}",
        "static void test_setsockopt_legacy_eperm(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_legacy_eperm = NULL, *link_get_retval = NULL;\n": "static void test_setsockopt_legacy_eperm(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_legacy_eperm = NULL, *link_get_retval = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that return a reject without setting errno\n\t * (legacy reject), and one that gets the errno. Assert that for\n\t * backward compatibility the syscall result in EPERM, and this\n\t * is also visible to the helper.\n\t */\n\tlink_legacy_eperm = bpf_program__attach_cgroup(obj->progs.legacy_eperm,\n\t\t\t\t\t\t       cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_legacy_eperm, \"cg-attach-legacy_eperm\"))\n\t\tgoto close_bpf_object;\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t   &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EPERM, \"setsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 2, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, -EPERM, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_legacy_eperm);\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static void init_v4l2_vp9_count_tbl(struct hantro_ctx *ctx)\n{\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tstruct symbol_counts *cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset;\n\tint i, j, k, l, m;": "static void init_v4l2_vp9_count_tbl(struct hantro_ctx *ctx)\n{\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tstruct symbol_counts *cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset;\n\tint i, j, k, l, m;\n\n\tvp9_ctx->cnts.partition = &cnts->partition_counts;\n\tvp9_ctx->cnts.skip = &cnts->mbskip_count;\n\tvp9_ctx->cnts.intra_inter = &cnts->intra_inter_count;\n\tvp9_ctx->cnts.tx32p = &cnts->tx32x32_count;\n\t/*\n\t * g2 hardware uses tx16x16_count[2][3], while the api\n\t * expects tx16p[2][4], so this must be explicitly copied\n\t * into vp9_ctx->cnts.tx16p when passing the data to the\n\t * vp9 library function\n\t */\n\tvp9_ctx->cnts.tx8p = &cnts->tx8x8_count;\n\n\tvp9_ctx->cnts.y_mode = &cnts->sb_ymode_counts;\n\tvp9_ctx->cnts.uv_mode = &cnts->uv_mode_counts;\n\tvp9_ctx->cnts.comp = &cnts->comp_inter_count;\n\tvp9_ctx->cnts.comp_ref = &cnts->comp_ref_count;\n\tvp9_ctx->cnts.single_ref = &cnts->single_ref_count;\n\tvp9_ctx->cnts.filter = &cnts->switchable_interp_counts;\n\tvp9_ctx->cnts.mv_joint = &cnts->mv_counts.joints;\n\tvp9_ctx->cnts.sign = &cnts->mv_counts.sign;\n\tvp9_ctx->cnts.classes = &cnts->mv_counts.classes;\n\tvp9_ctx->cnts.class0 = &cnts->mv_counts.class0;\n\tvp9_ctx->cnts.bits = &cnts->mv_counts.bits;\n\tvp9_ctx->cnts.class0_fp = &cnts->mv_counts.class0_fp;\n\tvp9_ctx->cnts.fp = &cnts->mv_counts.fp;\n\tvp9_ctx->cnts.class0_hp = &cnts->mv_counts.class0_hp;\n\tvp9_ctx->cnts.hp = &cnts->mv_counts.hp;\n\n\tfor (i = 0; i < ARRAY_SIZE(vp9_ctx->cnts.coeff); ++i)\n\t\tfor (j = 0; j < ARRAY_SIZE(vp9_ctx->cnts.coeff[i]); ++j)\n\t\t\tfor (k = 0; k < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0]); ++k)\n\t\t\t\tfor (l = 0; l < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0]); ++l)\n\t\t\t\t\tINNER_LOOP;\n}",
        "static void test_inet_dtime(int family, int type, const char *addr, __u16 port)\n{\n\tint opt = 1, accept_fd = -1, client_fd = -1, listen_fd, err;\n\tchar buf[] = \"testing testing\";\n\tstruct nstoken *nstoken;": "static void test_inet_dtime(int family, int type, const char *addr, __u16 port)\n{\n\tint opt = 1, accept_fd = -1, client_fd = -1, listen_fd, err;\n\tchar buf[] = \"testing testing\";\n\tstruct nstoken *nstoken;\n\n\tnstoken = open_netns(NS_DST);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns dst\"))\n\t\treturn;\n\tlisten_fd = start_server(family, type, addr, port, 0);\n\tclose_netns(nstoken);\n\n\tif (!ASSERT_GE(listen_fd, 0, \"listen\"))\n\t\treturn;\n\n\t/* Ensure the kernel puts the (rcv) timestamp for all skb */\n\terr = setsockopt(listen_fd, SOL_SOCKET, SO_TIMESTAMPNS_NEW,\n\t\t\t &opt, sizeof(opt));\n\tif (!ASSERT_OK(err, \"setsockopt(SO_TIMESTAMPNS_NEW)\"))\n\t\tgoto done;\n\n\tif (type == SOCK_STREAM) {\n\t\t/* Ensure the kernel set EDT when sending out rst/ack\n\t\t * from the kernel's ctl_sk.\n\t\t */\n\t\terr = setsockopt(listen_fd, SOL_TCP, TCP_TX_DELAY, &opt,\n\t\t\t\t sizeof(opt));\n\t\tif (!ASSERT_OK(err, \"setsockopt(TCP_TX_DELAY)\"))\n\t\t\tgoto done;\n\t}\n\n\tnstoken = open_netns(NS_SRC);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns src\"))\n\t\tgoto done;\n\tclient_fd = connect_to_fd(listen_fd, TIMEOUT_MILLIS);\n\tclose_netns(nstoken);\n\n\tif (!ASSERT_GE(client_fd, 0, \"connect_to_fd\"))\n\t\tgoto done;\n\n\tif (type == SOCK_STREAM) {\n\t\tint n;\n\n\t\taccept_fd = accept(listen_fd, NULL, NULL);\n\t\tif (!ASSERT_GE(accept_fd, 0, \"accept\"))\n\t\t\tgoto done;\n\n\t\tn = write(client_fd, buf, sizeof(buf));\n\t\tif (!ASSERT_EQ(n, sizeof(buf), \"send to server\"))\n\t\t\tgoto done;\n\t\trcv_tstamp(accept_fd, buf, sizeof(buf));\n\t} else {\n\t\tsnd_tstamp(client_fd, buf, sizeof(buf));\n\t\trcv_tstamp(listen_fd, buf, sizeof(buf));\n\t}\n\ndone:\n\tclose(listen_fd);\n\tif (accept_fd != -1)\n\t\tclose(accept_fd);\n\tif (client_fd != -1)\n\t\tclose(client_fd);\n}",
        "static int record__aio_pushfn(struct mmap *map, void *to, void *buf, size_t size)\n{\n\tstruct record_aio *aio = to;\n\n\t/*": "static int record__aio_pushfn(struct mmap *map, void *to, void *buf, size_t size)\n{\n\tstruct record_aio *aio = to;\n\n\t/*\n\t * map->core.base data pointed by buf is copied into free map->aio.data[] buffer\n\t * to release space in the kernel buffer as fast as possible, calling\n\t * perf_mmap__consume() from perf_mmap__push() function.\n\t *\n\t * That lets the kernel to proceed with storing more profiling data into\n\t * the kernel buffer earlier than other per-cpu kernel buffers are handled.\n\t *\n\t * Coping can be done in two steps in case the chunk of profiling data\n\t * crosses the upper bound of the kernel buffer. In this case we first move\n\t * part of data from map->start till the upper bound and then the reminder\n\t * from the beginning of the kernel buffer till the end of the data chunk.\n\t */\n\n\tif (record__comp_enabled(aio->rec)) {\n\t\tsize = zstd_compress(aio->rec->session, NULL, aio->data + aio->size,\n\t\t\t\t     mmap__mmap_len(map) - aio->size,\n\t\t\t\t     buf, size);\n\t} else {\n\t\tmemcpy(aio->data + aio->size, buf, size);\n\t}\n\n\tif (!aio->size) {\n\t\t/*\n\t\t * Increment map->refcount to guard map->aio.data[] buffer\n\t\t * from premature deallocation because map object can be\n\t\t * released earlier than aio write request started on\n\t\t * map->aio.data[] buffer is complete.\n\t\t *\n\t\t * perf_mmap__put() is done at record__aio_complete()\n\t\t * after started aio request completion or at record__aio_push()\n\t\t * if the request failed to start.\n\t\t */\n\t\tperf_mmap__get(&map->core);\n\t}\n\n\taio->size += size;\n\n\treturn size;\n}",
        "static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)\n{\n\tstatic const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1;\n\t/* Scale factor is based on the number of bits in fractional portion */\n\tstatic const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);": "static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)\n{\n\tstatic const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1;\n\t/* Scale factor is based on the number of bits in fractional portion */\n\tstatic const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);\n\tstatic const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>\n\t\t\t\t    HW_ATL_TPS_DESC_RATE_Y_SHIFT;\n\tconst u32 link_speed = self->aq_link_status.mbps;\n\tstruct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;\n\tunsigned long num_min_rated_tcs = 0;\n\tu32 tc_weight[AQ_CFG_TCS_MAX];\n\tu32 fixed_max_credit_4b;\n\tu32 fixed_max_credit;\n\tu8 min_rate_msk = 0;\n\tu32 sum_weight = 0;\n\tint tc;\n\n\t/* By default max_credit is based upon MTU (in unit of 64b) */\n\tfixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64;\n\t/* in unit of 4b */\n\tfixed_max_credit_4b = nic_cfg->aq_hw_caps->mtu / 4;\n\n\tif (link_speed) {\n\t\tmin_rate_msk = nic_cfg->tc_min_rate_msk &\n\t\t\t       (BIT(nic_cfg->tcs) - 1);\n\t\tnum_min_rated_tcs = hweight8(min_rate_msk);\n\t}\n\n\t/* First, calculate weights where min_rate is specified */\n\tif (num_min_rated_tcs) {\n\t\tfor (tc = 0; tc != nic_cfg->tcs; tc++) {\n\t\t\tif (!nic_cfg->tc_min_rate[tc]) {\n\t\t\t\ttc_weight[tc] = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\ttc_weight[tc] = (-1L + link_speed +\n\t\t\t\t\t nic_cfg->tc_min_rate[tc] *\n\t\t\t\t\t max_weight) /\n\t\t\t\t\tlink_speed;\n\t\t\ttc_weight[tc] = min(tc_weight[tc], max_weight);\n\t\t\tsum_weight += tc_weight[tc];\n\t\t}\n\t}\n\n\t/* WSP, if min_rate is set for at least one TC.\n\t * RR otherwise.\n\t */\n\thw_atl2_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U);\n\t/* Data TC Arbiter takes precedence over Descriptor TC Arbiter,\n\t * leave Descriptor TC Arbiter as RR.\n\t */\n\thw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);\n\n\thw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);\n\n\tfor (tc = 0; tc != nic_cfg->tcs; tc++) {\n\t\tconst u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;\n\t\tconst u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);\n\t\tu32 weight, max_credit;\n\n\t\thw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc,\n\t\t\t\t\t\t\t      fixed_max_credit);\n\t\thw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E);\n\n\t\tif (num_min_rated_tcs) {\n\t\t\tweight = tc_weight[tc];\n\n\t\t\tif (!weight && sum_weight < max_weight)\n\t\t\t\tweight = (max_weight - sum_weight) /\n\t\t\t\t\t (nic_cfg->tcs - num_min_rated_tcs);\n\t\t\telse if (!weight)\n\t\t\t\tweight = 0x640;\n\n\t\t\tmax_credit = max(2 * weight, fixed_max_credit_4b);\n\t\t} else {\n\t\t\tweight = 0x640;\n\t\t\tmax_credit = 0xFFF0;\n\t\t}\n\n\t\thw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight);\n\t\thw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc,\n\t\t\t\t\t\t\t       max_credit);\n\n\t\thw_atl_tps_tx_desc_rate_en_set(self, desc, en);\n\n\t\tif (en) {\n\t\t\t/* Nominal rate is always 10G */\n\t\t\tconst u32 rate = 10000U * scale /\n\t\t\t\t\t nic_cfg->tc_max_rate[tc];\n\t\t\tconst u32 rate_int = rate >>\n\t\t\t\t\t     HW_ATL_TPS_DESC_RATE_Y_WIDTH;\n\t\t\tconst u32 rate_frac = rate & frac_msk;\n\n\t\t\thw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int);\n\t\t\thw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac);\n\t\t} else {\n\t\t\t/* A value of 1 indicates the queue is not\n\t\t\t * rate controlled.\n\t\t\t */\n\t\t\thw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);\n\t\t\thw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);\n\t\t}\n\t}\n\tfor (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) {\n\t\tconst u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);\n\n\t\thw_atl_tps_tx_desc_rate_en_set(self, desc, 0U);\n\t\thw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);\n\t\thw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);\n\t}\n\n\treturn aq_hw_err_from_flags(self);\n}",
        "static int qcom_osm_l3_probe(struct platform_device *pdev)\n{\n\tu32 info, src, lval, i, prev_freq = 0, freq;\n\tstatic unsigned long hw_rate, xo_rate;\n\tstruct qcom_osm_l3_icc_provider *qp;": "static int qcom_osm_l3_probe(struct platform_device *pdev)\n{\n\tu32 info, src, lval, i, prev_freq = 0, freq;\n\tstatic unsigned long hw_rate, xo_rate;\n\tstruct qcom_osm_l3_icc_provider *qp;\n\tconst struct qcom_osm_l3_desc *desc;\n\tstruct icc_onecell_data *data;\n\tstruct icc_provider *provider;\n\tconst struct qcom_osm_l3_node * const *qnodes;\n\tstruct icc_node *node;\n\tsize_t num_nodes;\n\tstruct clk *clk;\n\tint ret;\n\n\tclk = clk_get(&pdev->dev, \"xo\");\n\tif (IS_ERR(clk))\n\t\treturn PTR_ERR(clk);\n\n\txo_rate = clk_get_rate(clk);\n\tclk_put(clk);\n\n\tclk = clk_get(&pdev->dev, \"alternate\");\n\tif (IS_ERR(clk))\n\t\treturn PTR_ERR(clk);\n\n\thw_rate = clk_get_rate(clk) / CLK_HW_DIV;\n\tclk_put(clk);\n\n\tqp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);\n\tif (!qp)\n\t\treturn -ENOMEM;\n\n\tqp->base = devm_platform_ioremap_resource(pdev, 0);\n\tif (IS_ERR(qp->base))\n\t\treturn PTR_ERR(qp->base);\n\n\t/* HW should be in enabled state to proceed */\n\tif (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {\n\t\tdev_err(&pdev->dev, \"error hardware not enabled\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tdesc = device_get_match_data(&pdev->dev);\n\tif (!desc)\n\t\treturn -EINVAL;\n\n\tqp->reg_perf_state = desc->reg_perf_state;\n\n\tfor (i = 0; i < LUT_MAX_ENTRIES; i++) {\n\t\tinfo = readl_relaxed(qp->base + desc->reg_freq_lut +\n\t\t\t\t     i * desc->lut_row_size);\n\t\tsrc = FIELD_GET(LUT_SRC, info);\n\t\tlval = FIELD_GET(LUT_L_VAL, info);\n\t\tif (src)\n\t\t\tfreq = xo_rate * lval;\n\t\telse\n\t\t\tfreq = hw_rate;\n\n\t\t/* Two of the same frequencies signify end of table */\n\t\tif (i > 0 && prev_freq == freq)\n\t\t\tbreak;\n\n\t\tdev_dbg(&pdev->dev, \"index=%d freq=%d\\n\", i, freq);\n\n\t\tqp->lut_tables[i] = freq;\n\t\tprev_freq = freq;\n\t}\n\tqp->max_state = i;\n\n\tqnodes = desc->nodes;\n\tnum_nodes = desc->num_nodes;\n\n\tdata = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tprovider = &qp->provider;\n\tprovider->dev = &pdev->dev;\n\tprovider->set = qcom_osm_l3_set;\n\tprovider->aggregate = icc_std_aggregate;\n\tprovider->xlate = of_icc_xlate_onecell;\n\tINIT_LIST_HEAD(&provider->nodes);\n\tprovider->data = data;\n\n\tret = icc_provider_add(provider);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"error adding interconnect provider\\n\");\n\t\treturn ret;\n\t}\n\n\tfor (i = 0; i < num_nodes; i++) {\n\t\tsize_t j;\n\n\t\tnode = icc_node_create(qnodes[i]->id);\n\t\tif (IS_ERR(node)) {\n\t\t\tret = PTR_ERR(node);\n\t\t\tgoto err;\n\t\t}\n\n\t\tnode->name = qnodes[i]->name;\n\t\t/* Cast away const and add it back in qcom_osm_l3_set() */\n\t\tnode->data = (void *)qnodes[i];\n\t\ticc_node_add(node, provider);\n\n\t\tfor (j = 0; j < qnodes[i]->num_links; j++)\n\t\t\ticc_link_create(node, qnodes[i]->links[j]);\n\n\t\tdata->nodes[i] = node;\n\t}\n\tdata->num_nodes = num_nodes;\n\n\tplatform_set_drvdata(pdev, qp);\n\n\treturn 0;\nerr:\n\ticc_nodes_remove(provider);\n\ticc_provider_del(provider);\n\n\treturn ret;\n}",
        "static void reset_locks(void)\n{\n\tlocal_irq_disable();\n\tlockdep_free_key_range(&ww_lockdep.acquire_key, 1);\n\tlockdep_free_key_range(&ww_lockdep.mutex_key, 1);": "static void reset_locks(void)\n{\n\tlocal_irq_disable();\n\tlockdep_free_key_range(&ww_lockdep.acquire_key, 1);\n\tlockdep_free_key_range(&ww_lockdep.mutex_key, 1);\n\n\tI1(A); I1(B); I1(C); I1(D);\n\tI1(X1); I1(X2); I1(Y1); I1(Y2); I1(Z1); I1(Z2);\n\tI_WW(t); I_WW(t2); I_WW(o.base); I_WW(o2.base); I_WW(o3.base);\n\tI_RAW_SPINLOCK(A); I_RAW_SPINLOCK(B);\n\tI_LOCAL_LOCK(A);\n\n\tlockdep_reset();\n\n\tI2(A); I2(B); I2(C); I2(D);\n\tinit_shared_classes();\n\traw_spin_lock_init(&raw_lock_A);\n\traw_spin_lock_init(&raw_lock_B);\n\tlocal_lock_init(this_cpu_ptr(&local_A));\n\n\tww_mutex_init(&o, &ww_lockdep); ww_mutex_init(&o2, &ww_lockdep); ww_mutex_init(&o3, &ww_lockdep);\n\tmemset(&t, 0, sizeof(t)); memset(&t2, 0, sizeof(t2));\n\tmemset(&ww_lockdep.acquire_key, 0, sizeof(ww_lockdep.acquire_key));\n\tmemset(&ww_lockdep.mutex_key, 0, sizeof(ww_lockdep.mutex_key));\n\tlocal_irq_enable();\n}",
        "static void freeze_array(struct r1conf *conf, int extra)\n{\n\t/* Stop sync I/O and normal I/O and wait for everything to\n\t * go quiet.\n\t * This is called in two situations:": "static void freeze_array(struct r1conf *conf, int extra)\n{\n\t/* Stop sync I/O and normal I/O and wait for everything to\n\t * go quiet.\n\t * This is called in two situations:\n\t * 1) management command handlers (reshape, remove disk, quiesce).\n\t * 2) one normal I/O request failed.\n\n\t * After array_frozen is set to 1, new sync IO will be blocked at\n\t * raise_barrier(), and new normal I/O will blocked at _wait_barrier()\n\t * or wait_read_barrier(). The flying I/Os will either complete or be\n\t * queued. When everything goes quite, there are only queued I/Os left.\n\n\t * Every flying I/O contributes to a conf->nr_pending[idx], idx is the\n\t * barrier bucket index which this I/O request hits. When all sync and\n\t * normal I/O are queued, sum of all conf->nr_pending[] will match sum\n\t * of all conf->nr_queued[]. But normal I/O failure is an exception,\n\t * in handle_read_error(), we may call freeze_array() before trying to\n\t * fix the read error. In this case, the error read I/O is not queued,\n\t * so get_unqueued_pending() == 1.\n\t *\n\t * Therefore before this function returns, we need to wait until\n\t * get_unqueued_pendings(conf) gets equal to extra. For\n\t * normal I/O context, extra is 1, in rested situations extra is 0.\n\t */\n\tspin_lock_irq(&conf->resync_lock);\n\tconf->array_frozen = 1;\n\traid1_log(conf->mddev, \"wait freeze\");\n\twait_event_lock_irq_cmd(\n\t\tconf->wait_barrier,\n\t\tget_unqueued_pending(conf) == extra,\n\t\tconf->resync_lock,\n\t\tflush_pending_writes(conf));\n\tspin_unlock_irq(&conf->resync_lock);\n}",
        "static void thinkpad_acpi_module_exit(void)\n{\n\tstruct ibm_struct *ibm, *itmp;\n\n\ttpacpi_lifecycle = TPACPI_LIFE_EXITING;": "static void thinkpad_acpi_module_exit(void)\n{\n\tstruct ibm_struct *ibm, *itmp;\n\n\ttpacpi_lifecycle = TPACPI_LIFE_EXITING;\n\n#ifdef CONFIG_SUSPEND\n\tif (tp_features.quirks && tp_features.quirks->s2idle_bug_mmio)\n\t\tacpi_unregister_lps0_dev(&thinkpad_acpi_s2idle_dev_ops);\n#endif\n\tif (tpacpi_hwmon)\n\t\thwmon_device_unregister(tpacpi_hwmon);\n\tif (tp_features.sensors_pdrv_registered)\n\t\tplatform_driver_unregister(&tpacpi_hwmon_pdriver);\n\tif (tp_features.platform_drv_registered)\n\t\tplatform_driver_unregister(&tpacpi_pdriver);\n\n\tlist_for_each_entry_safe_reverse(ibm, itmp,\n\t\t\t\t\t &tpacpi_all_drivers,\n\t\t\t\t\t all_drivers) {\n\t\tibm_exit(ibm);\n\t}\n\n\tdbg_printk(TPACPI_DBG_INIT, \"finished subdriver exit path...\\n\");\n\n\tif (tpacpi_inputdev) {\n\t\tif (tp_features.input_device_registered)\n\t\t\tinput_unregister_device(tpacpi_inputdev);\n\t\telse\n\t\t\tinput_free_device(tpacpi_inputdev);\n\t\tkfree(hotkey_keycode_map);\n\t}\n\n\tif (tpacpi_sensors_pdev)\n\t\tplatform_device_unregister(tpacpi_sensors_pdev);\n\tif (tpacpi_pdev)\n\t\tplatform_device_unregister(tpacpi_pdev);\n\tif (proc_dir)\n\t\tremove_proc_entry(TPACPI_PROC_DIR, acpi_root_dir);\n\tif (tpacpi_wq)\n\t\tdestroy_workqueue(tpacpi_wq);\n\n\tkfree(thinkpad_id.bios_version_str);\n\tkfree(thinkpad_id.ec_version_str);\n\tkfree(thinkpad_id.model_str);\n\tkfree(thinkpad_id.nummodel_str);\n}",
        "static void test_termination(void)\n{\n\tstruct test_default t = test_default_init(guest_error_key);\n\tuint64_t prefix;\n\tuint64_t teid;": "static void test_termination(void)\n{\n\tstruct test_default t = test_default_init(guest_error_key);\n\tuint64_t prefix;\n\tuint64_t teid;\n\tuint64_t teid_mask = BIT(63 - 56) | BIT(63 - 60) | BIT(63 - 61);\n\tuint64_t psw[2];\n\n\tHOST_SYNC(t.vcpu, STAGE_INITED);\n\tHOST_SYNC(t.vcpu, STAGE_SKEYS_SET);\n\n\t/* vcpu, mismatching keys after first page */\n\tERR_PROT_MOP(t.vcpu, LOGICAL, WRITE, mem1, t.size, GADDR_V(mem1), KEY(1), INJECT);\n\t/*\n\t * The memop injected a program exception and the test needs to check the\n\t * Translation-Exception Identification (TEID). It is necessary to run\n\t * the guest in order to be able to read the TEID from guest memory.\n\t * Set the guest program new PSW, so the guest state is not clobbered.\n\t */\n\tprefix = t.run->s.regs.prefix;\n\tpsw[0] = t.run->psw_mask;\n\tpsw[1] = t.run->psw_addr;\n\tMOP(t.vm, ABSOLUTE, WRITE, psw, sizeof(psw), GADDR(prefix + 464));\n\tHOST_SYNC(t.vcpu, STAGE_IDLED);\n\tMOP(t.vm, ABSOLUTE, READ, &teid, sizeof(teid), GADDR(prefix + 168));\n\t/* Bits 56, 60, 61 form a code, 0 being the only one allowing for termination */\n\tASSERT_EQ(teid & teid_mask, 0);\n\n\tkvm_vm_free(t.kvm_vm);\n}",
        "static void ocfs2_xa_block_wipe_namevalue(struct ocfs2_xa_loc *loc)\n{\n\tint i, offset;\n\tint namevalue_offset, first_namevalue_offset, namevalue_size;\n\tstruct ocfs2_xattr_entry *entry = loc->xl_entry;": "static void ocfs2_xa_block_wipe_namevalue(struct ocfs2_xa_loc *loc)\n{\n\tint i, offset;\n\tint namevalue_offset, first_namevalue_offset, namevalue_size;\n\tstruct ocfs2_xattr_entry *entry = loc->xl_entry;\n\tstruct ocfs2_xattr_header *xh = loc->xl_header;\n\tint count = le16_to_cpu(xh->xh_count);\n\n\tnamevalue_offset = le16_to_cpu(entry->xe_name_offset);\n\tnamevalue_size = namevalue_size_xe(entry);\n\tfirst_namevalue_offset = ocfs2_xa_get_free_start(loc);\n\n\t/* Shift the name+value pairs */\n\tmemmove((char *)xh + first_namevalue_offset + namevalue_size,\n\t\t(char *)xh + first_namevalue_offset,\n\t\tnamevalue_offset - first_namevalue_offset);\n\tmemset((char *)xh + first_namevalue_offset, 0, namevalue_size);\n\n\t/* Now tell xh->xh_entries about it */\n\tfor (i = 0; i < count; i++) {\n\t\toffset = le16_to_cpu(xh->xh_entries[i].xe_name_offset);\n\t\tif (offset <= namevalue_offset)\n\t\t\tle16_add_cpu(&xh->xh_entries[i].xe_name_offset,\n\t\t\t\t     namevalue_size);\n\t}\n\n\t/*\n\t * Note that we don't update xh_free_start or xh_name_value_len\n\t * because they're not used in block-stored xattrs.\n\t */\n}",
        "static void set_ssp_complete(struct hci_dev *hdev, void *data, int err)\n{\n\tstruct cmd_lookup match = { NULL, hdev };\n\tstruct mgmt_pending_cmd *cmd = data;\n\tstruct mgmt_mode *cp = cmd->param;": "static void set_ssp_complete(struct hci_dev *hdev, void *data, int err)\n{\n\tstruct cmd_lookup match = { NULL, hdev };\n\tstruct mgmt_pending_cmd *cmd = data;\n\tstruct mgmt_mode *cp = cmd->param;\n\tu8 enable = cp->val;\n\tbool changed;\n\n\t/* Make sure cmd still outstanding. */\n\tif (cmd != pending_find(MGMT_OP_SET_SSP, hdev))\n\t\treturn;\n\n\tif (err) {\n\t\tu8 mgmt_err = mgmt_status(err);\n\n\t\tif (enable && hci_dev_test_and_clear_flag(hdev,\n\t\t\t\t\t\t\t  HCI_SSP_ENABLED)) {\n\t\t\thci_dev_clear_flag(hdev, HCI_HS_ENABLED);\n\t\t\tnew_settings(hdev, NULL);\n\t\t}\n\n\t\tmgmt_pending_foreach(MGMT_OP_SET_SSP, hdev, cmd_status_rsp,\n\t\t\t\t     &mgmt_err);\n\t\treturn;\n\t}\n\n\tif (enable) {\n\t\tchanged = !hci_dev_test_and_set_flag(hdev, HCI_SSP_ENABLED);\n\t} else {\n\t\tchanged = hci_dev_test_and_clear_flag(hdev, HCI_SSP_ENABLED);\n\n\t\tif (!changed)\n\t\t\tchanged = hci_dev_test_and_clear_flag(hdev,\n\t\t\t\t\t\t\t      HCI_HS_ENABLED);\n\t\telse\n\t\t\thci_dev_clear_flag(hdev, HCI_HS_ENABLED);\n\t}\n\n\tmgmt_pending_foreach(MGMT_OP_SET_SSP, hdev, settings_rsp, &match);\n\n\tif (changed)\n\t\tnew_settings(hdev, match.sk);\n\n\tif (match.sk)\n\t\tsock_put(match.sk);\n\n\thci_update_eir_sync(hdev);\n}",
        "static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)\n{\n\tnetdev_info(qdev->ndev, \"enabling Agere specific PHY\\n\");\n\t/* power down device bit 11 = 1 */\n\tql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);": "static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)\n{\n\tnetdev_info(qdev->ndev, \"enabling Agere specific PHY\\n\");\n\t/* power down device bit 11 = 1 */\n\tql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);\n\t/* enable diagnostic mode bit 2 = 1 */\n\tql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);\n\t/* 1000MB amplitude adjust (see Agere errata) */\n\tql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);\n\t/* 1000MB amplitude adjust (see Agere errata) */\n\tql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);\n\t/* 100MB amplitude adjust (see Agere errata) */\n\tql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);\n\t/* 100MB amplitude adjust (see Agere errata) */\n\tql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);\n\t/* 10MB amplitude adjust (see Agere errata) */\n\tql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);\n\t/* 10MB amplitude adjust (see Agere errata) */\n\tql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);\n\t/* point to hidden reg 0x2806 */\n\tql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);\n\t/* Write new PHYAD w/bit 5 set */\n\tql_mii_write_reg_ex(qdev, 0x11,\n\t\t\t    0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);\n\t/*\n\t * Disable diagnostic mode bit 2 = 0\n\t * Power up device bit 11 = 0\n\t * Link up (on) and activity (blink)\n\t */\n\tql_mii_write_reg(qdev, 0x12, 0x840a);\n\tql_mii_write_reg(qdev, 0x00, 0x1140);\n\tql_mii_write_reg(qdev, 0x1c, 0xfaf0);\n}",
        "static void smc_llc_rmt_conf_rkey(struct smc_link_group *lgr)\n{\n\tstruct smc_llc_msg_confirm_rkey *llc;\n\tstruct smc_llc_qentry *qentry;\n\tstruct smc_link *link;": "static void smc_llc_rmt_conf_rkey(struct smc_link_group *lgr)\n{\n\tstruct smc_llc_msg_confirm_rkey *llc;\n\tstruct smc_llc_qentry *qentry;\n\tstruct smc_link *link;\n\tint num_entries;\n\tint rk_idx;\n\tint i;\n\n\tqentry = lgr->llc_flow_rmt.qentry;\n\tllc = &qentry->msg.confirm_rkey;\n\tlink = qentry->link;\n\n\tnum_entries = llc->rtoken[0].num_rkeys;\n\tif (num_entries > SMC_LLC_RKEYS_PER_MSG)\n\t\tgoto out_err;\n\t/* first rkey entry is for receiving link */\n\trk_idx = smc_rtoken_add(link,\n\t\t\t\tllc->rtoken[0].rmb_vaddr,\n\t\t\t\tllc->rtoken[0].rmb_key);\n\tif (rk_idx < 0)\n\t\tgoto out_err;\n\n\tfor (i = 1; i <= min_t(u8, num_entries, SMC_LLC_RKEYS_PER_MSG - 1); i++)\n\t\tsmc_rtoken_set2(lgr, rk_idx, llc->rtoken[i].link_id,\n\t\t\t\tllc->rtoken[i].rmb_vaddr,\n\t\t\t\tllc->rtoken[i].rmb_key);\n\t/* max links is 3 so there is no need to support conf_rkey_cont msgs */\n\tgoto out;\nout_err:\n\tllc->hd.flags |= SMC_LLC_FLAG_RKEY_NEG;\n\tllc->hd.flags |= SMC_LLC_FLAG_RKEY_RETRY;\nout:\n\tllc->hd.flags |= SMC_LLC_FLAG_RESP;\n\tsmc_llc_init_msg_hdr(&llc->hd, link->lgr, sizeof(*llc));\n\tsmc_llc_send_message(link, &qentry->msg);\n\tsmc_llc_flow_qentry_del(&lgr->llc_flow_rmt);\n}",
        "static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts)\n{\n\t/*\n\t * This is a simple algorithm for managing traffic on DMC.\n\t * When there is almost no load the counters overflow every 4s,": "static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts)\n{\n\t/*\n\t * This is a simple algorithm for managing traffic on DMC.\n\t * When there is almost no load the counters overflow every 4s,\n\t * no mater the DMC frequency.\n\t * The high load might be approximated using linear function.\n\t * Knowing that, simple calculation can provide 'busy_time' and\n\t * 'total_time' to the devfreq governor which picks up target\n\t * frequency.\n\t * We want a fast ramp up and slow decay in frequency change function.\n\t */\n\tif (diff_ts < PERF_EVENT_UP_DOWN_THRESHOLD) {\n\t\t/*\n\t\t * Set higher utilization for the simple_ondemand governor.\n\t\t * The governor should increase the frequency of the DMC.\n\t\t */\n\t\tdmc->load = 70;\n\t\tdmc->total = 100;\n\t} else {\n\t\t/*\n\t\t * Set low utilization for the simple_ondemand governor.\n\t\t * The governor should decrease the frequency of the DMC.\n\t\t */\n\t\tdmc->load = 35;\n\t\tdmc->total = 100;\n\t}\n\n\tdev_dbg(dmc->dev, \"diff_ts=%llu\\n\", diff_ts);\n}",
        "static void __init find_zone_movable_pfns_for_nodes(void)\n{\n\tint i, nid;\n\tunsigned long usable_startpfn;\n\tunsigned long kernelcore_node, kernelcore_remaining;": "static void __init find_zone_movable_pfns_for_nodes(void)\n{\n\tint i, nid;\n\tunsigned long usable_startpfn;\n\tunsigned long kernelcore_node, kernelcore_remaining;\n\t/* save the state before borrow the nodemask */\n\tnodemask_t saved_node_state = node_states[N_MEMORY];\n\tunsigned long totalpages = early_calculate_totalpages();\n\tint usable_nodes = nodes_weight(node_states[N_MEMORY]);\n\tstruct memblock_region *r;\n\n\t/* Need to find movable_zone earlier when movable_node is specified. */\n\tfind_usable_zone_for_movable();\n\n\t/*\n\t * If movable_node is specified, ignore kernelcore and movablecore\n\t * options.\n\t */\n\tif (movable_node_is_enabled()) {\n\t\tfor_each_mem_region(r) {\n\t\t\tif (!memblock_is_hotpluggable(r))\n\t\t\t\tcontinue;\n\n\t\t\tnid = memblock_get_region_node(r);\n\n\t\t\tusable_startpfn = PFN_DOWN(r->base);\n\t\t\tzone_movable_pfn[nid] = zone_movable_pfn[nid] ?\n\t\t\t\tmin(usable_startpfn, zone_movable_pfn[nid]) :\n\t\t\t\tusable_startpfn;\n\t\t}\n\n\t\tgoto out2;\n\t}\n\n\t/*\n\t * If kernelcore=mirror is specified, ignore movablecore option\n\t */\n\tif (mirrored_kernelcore) {\n\t\tbool mem_below_4gb_not_mirrored = false;\n\n\t\tfor_each_mem_region(r) {\n\t\t\tif (memblock_is_mirror(r))\n\t\t\t\tcontinue;\n\n\t\t\tnid = memblock_get_region_node(r);\n\n\t\t\tusable_startpfn = memblock_region_memory_base_pfn(r);\n\n\t\t\tif (usable_startpfn < PHYS_PFN(SZ_4G)) {\n\t\t\t\tmem_below_4gb_not_mirrored = true;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tzone_movable_pfn[nid] = zone_movable_pfn[nid] ?\n\t\t\t\tmin(usable_startpfn, zone_movable_pfn[nid]) :\n\t\t\t\tusable_startpfn;\n\t\t}\n\n\t\tif (mem_below_4gb_not_mirrored)\n\t\t\tpr_warn(\"This configuration results in unmirrored kernel memory.\\n\");\n\n\t\tgoto out2;\n\t}\n\n\t/*\n\t * If kernelcore=nn% or movablecore=nn% was specified, calculate the\n\t * amount of necessary memory.\n\t */\n\tif (required_kernelcore_percent)\n\t\trequired_kernelcore = (totalpages * 100 * required_kernelcore_percent) /\n\t\t\t\t       10000UL;\n\tif (required_movablecore_percent)\n\t\trequired_movablecore = (totalpages * 100 * required_movablecore_percent) /\n\t\t\t\t\t10000UL;\n\n\t/*\n\t * If movablecore= was specified, calculate what size of\n\t * kernelcore that corresponds so that memory usable for\n\t * any allocation type is evenly spread. If both kernelcore\n\t * and movablecore are specified, then the value of kernelcore\n\t * will be used for required_kernelcore if it's greater than\n\t * what movablecore would have allowed.\n\t */\n\tif (required_movablecore) {\n\t\tunsigned long corepages;\n\n\t\t/*\n\t\t * Round-up so that ZONE_MOVABLE is at least as large as what\n\t\t * was requested by the user\n\t\t */\n\t\trequired_movablecore =\n\t\t\troundup(required_movablecore, MAX_ORDER_NR_PAGES);\n\t\trequired_movablecore = min(totalpages, required_movablecore);\n\t\tcorepages = totalpages - required_movablecore;\n\n\t\trequired_kernelcore = max(required_kernelcore, corepages);\n\t}\n\n\t/*\n\t * If kernelcore was not specified or kernelcore size is larger\n\t * than totalpages, there is no ZONE_MOVABLE.\n\t */\n\tif (!required_kernelcore || required_kernelcore >= totalpages)\n\t\tgoto out;\n\n\t/* usable_startpfn is the lowest possible pfn ZONE_MOVABLE can be at */\n\tusable_startpfn = arch_zone_lowest_possible_pfn[movable_zone];\n\nrestart:\n\t/* Spread kernelcore memory as evenly as possible throughout nodes */\n\tkernelcore_node = required_kernelcore / usable_nodes;\n\tfor_each_node_state(nid, N_MEMORY) {\n\t\tunsigned long start_pfn, end_pfn;\n\n\t\t/*\n\t\t * Recalculate kernelcore_node if the division per node\n\t\t * now exceeds what is necessary to satisfy the requested\n\t\t * amount of memory for the kernel\n\t\t */\n\t\tif (required_kernelcore < kernelcore_node)\n\t\t\tkernelcore_node = required_kernelcore / usable_nodes;\n\n\t\t/*\n\t\t * As the map is walked, we track how much memory is usable\n\t\t * by the kernel using kernelcore_remaining. When it is\n\t\t * 0, the rest of the node is usable by ZONE_MOVABLE\n\t\t */\n\t\tkernelcore_remaining = kernelcore_node;\n\n\t\t/* Go through each range of PFNs within this node */\n\t\tfor_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {\n\t\t\tunsigned long size_pages;\n\n\t\t\tstart_pfn = max(start_pfn, zone_movable_pfn[nid]);\n\t\t\tif (start_pfn >= end_pfn)\n\t\t\t\tcontinue;\n\n\t\t\t/* Account for what is only usable for kernelcore */\n\t\t\tif (start_pfn < usable_startpfn) {\n\t\t\t\tunsigned long kernel_pages;\n\t\t\t\tkernel_pages = min(end_pfn, usable_startpfn)\n\t\t\t\t\t\t\t\t- start_pfn;\n\n\t\t\t\tkernelcore_remaining -= min(kernel_pages,\n\t\t\t\t\t\t\tkernelcore_remaining);\n\t\t\t\trequired_kernelcore -= min(kernel_pages,\n\t\t\t\t\t\t\trequired_kernelcore);\n\n\t\t\t\t/* Continue if range is now fully accounted */\n\t\t\t\tif (end_pfn <= usable_startpfn) {\n\n\t\t\t\t\t/*\n\t\t\t\t\t * Push zone_movable_pfn to the end so\n\t\t\t\t\t * that if we have to rebalance\n\t\t\t\t\t * kernelcore across nodes, we will\n\t\t\t\t\t * not double account here\n\t\t\t\t\t */\n\t\t\t\t\tzone_movable_pfn[nid] = end_pfn;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tstart_pfn = usable_startpfn;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * The usable PFN range for ZONE_MOVABLE is from\n\t\t\t * start_pfn->end_pfn. Calculate size_pages as the\n\t\t\t * number of pages used as kernelcore\n\t\t\t */\n\t\t\tsize_pages = end_pfn - start_pfn;\n\t\t\tif (size_pages > kernelcore_remaining)\n\t\t\t\tsize_pages = kernelcore_remaining;\n\t\t\tzone_movable_pfn[nid] = start_pfn + size_pages;\n\n\t\t\t/*\n\t\t\t * Some kernelcore has been met, update counts and\n\t\t\t * break if the kernelcore for this node has been\n\t\t\t * satisfied\n\t\t\t */\n\t\t\trequired_kernelcore -= min(required_kernelcore,\n\t\t\t\t\t\t\t\tsize_pages);\n\t\t\tkernelcore_remaining -= size_pages;\n\t\t\tif (!kernelcore_remaining)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*\n\t * If there is still required_kernelcore, we do another pass with one\n\t * less node in the count. This will push zone_movable_pfn[nid] further\n\t * along on the nodes that still have memory until kernelcore is\n\t * satisfied\n\t */\n\tusable_nodes--;\n\tif (usable_nodes && required_kernelcore > usable_nodes)\n\t\tgoto restart;\n\nout2:\n\t/* Align start of ZONE_MOVABLE on all nids to MAX_ORDER_NR_PAGES */\n\tfor (nid = 0; nid < MAX_NUMNODES; nid++) {\n\t\tunsigned long start_pfn, end_pfn;\n\n\t\tzone_movable_pfn[nid] =\n\t\t\troundup(zone_movable_pfn[nid], MAX_ORDER_NR_PAGES);\n\n\t\tget_pfn_range_for_nid(nid, &start_pfn, &end_pfn);\n\t\tif (zone_movable_pfn[nid] >= end_pfn)\n\t\t\tzone_movable_pfn[nid] = 0;\n\t}\n\nout:\n\t/* restore the node_state */\n\tnode_states[N_MEMORY] = saved_node_state;\n}",
        "static void bq_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_frame *xdpf)\n{\n\tstruct list_head *flush_list = this_cpu_ptr(&cpu_map_flush_list);\n\tstruct xdp_bulk_queue *bq = this_cpu_ptr(rcpu->bulkq);\n": "static void bq_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_frame *xdpf)\n{\n\tstruct list_head *flush_list = this_cpu_ptr(&cpu_map_flush_list);\n\tstruct xdp_bulk_queue *bq = this_cpu_ptr(rcpu->bulkq);\n\n\tif (unlikely(bq->count == CPU_MAP_BULK_SIZE))\n\t\tbq_flush_to_queue(bq);\n\n\t/* Notice, xdp_buff/page MUST be queued here, long enough for\n\t * driver to code invoking us to finished, due to driver\n\t * (e.g. ixgbe) recycle tricks based on page-refcnt.\n\t *\n\t * Thus, incoming xdp_frame is always queued here (else we race\n\t * with another CPU on page-refcnt and remaining driver code).\n\t * Queue time is very short, as driver will invoke flush\n\t * operation, when completing napi->poll call.\n\t */\n\tbq->q[bq->count++] = xdpf;\n\n\tif (!bq->flush_node.prev)\n\t\tlist_add(&bq->flush_node, flush_list);\n}",
        "static int gve_tx_add_skb_copy(struct gve_priv *priv, struct gve_tx_ring *tx, struct sk_buff *skb)\n{\n\tint pad_bytes, hlen, hdr_nfrags, payload_nfrags, l4_hdr_offset;\n\tunion gve_tx_desc *pkt_desc, *seg_desc;\n\tstruct gve_tx_buffer_state *info;": "static int gve_tx_add_skb_copy(struct gve_priv *priv, struct gve_tx_ring *tx, struct sk_buff *skb)\n{\n\tint pad_bytes, hlen, hdr_nfrags, payload_nfrags, l4_hdr_offset;\n\tunion gve_tx_desc *pkt_desc, *seg_desc;\n\tstruct gve_tx_buffer_state *info;\n\tint mtd_desc_nr = !!skb->l4_hash;\n\tbool is_gso = skb_is_gso(skb);\n\tu32 idx = tx->req & tx->mask;\n\tint payload_iov = 2;\n\tint copy_offset;\n\tu32 next_idx;\n\tint i;\n\n\tinfo = &tx->info[idx];\n\tpkt_desc = &tx->desc[idx];\n\n\tl4_hdr_offset = skb_checksum_start_offset(skb);\n\t/* If the skb is gso, then we want the tcp header in the first segment\n\t * otherwise we want the linear portion of the skb (which will contain\n\t * the checksum because skb->csum_start and skb->csum_offset are given\n\t * relative to skb->head) in the first segment.\n\t */\n\thlen = is_gso ? l4_hdr_offset + tcp_hdrlen(skb) :\n\t\t\tskb_headlen(skb);\n\n\tinfo->skb =  skb;\n\t/* We don't want to split the header, so if necessary, pad to the end\n\t * of the fifo and then put the header at the beginning of the fifo.\n\t */\n\tpad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, hlen);\n\thdr_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, hlen + pad_bytes,\n\t\t\t\t       &info->iov[0]);\n\tWARN(!hdr_nfrags, \"hdr_nfrags should never be 0!\");\n\tpayload_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, skb->len - hlen,\n\t\t\t\t\t   &info->iov[payload_iov]);\n\n\tgve_tx_fill_pkt_desc(pkt_desc, skb, is_gso, l4_hdr_offset,\n\t\t\t     1 + mtd_desc_nr + payload_nfrags, hlen,\n\t\t\t     info->iov[hdr_nfrags - 1].iov_offset);\n\n\tskb_copy_bits(skb, 0,\n\t\t      tx->tx_fifo.base + info->iov[hdr_nfrags - 1].iov_offset,\n\t\t      hlen);\n\tgve_dma_sync_for_device(&priv->pdev->dev, tx->tx_fifo.qpl->page_buses,\n\t\t\t\tinfo->iov[hdr_nfrags - 1].iov_offset,\n\t\t\t\tinfo->iov[hdr_nfrags - 1].iov_len);\n\tcopy_offset = hlen;\n\n\tif (mtd_desc_nr) {\n\t\tnext_idx = (tx->req + 1) & tx->mask;\n\t\tgve_tx_fill_mtd_desc(&tx->desc[next_idx], skb);\n\t}\n\n\tfor (i = payload_iov; i < payload_nfrags + payload_iov; i++) {\n\t\tnext_idx = (tx->req + 1 + mtd_desc_nr + i - payload_iov) & tx->mask;\n\t\tseg_desc = &tx->desc[next_idx];\n\n\t\tgve_tx_fill_seg_desc(seg_desc, skb, is_gso,\n\t\t\t\t     info->iov[i].iov_len,\n\t\t\t\t     info->iov[i].iov_offset);\n\n\t\tskb_copy_bits(skb, copy_offset,\n\t\t\t      tx->tx_fifo.base + info->iov[i].iov_offset,\n\t\t\t      info->iov[i].iov_len);\n\t\tgve_dma_sync_for_device(&priv->pdev->dev, tx->tx_fifo.qpl->page_buses,\n\t\t\t\t\tinfo->iov[i].iov_offset,\n\t\t\t\t\tinfo->iov[i].iov_len);\n\t\tcopy_offset += info->iov[i].iov_len;\n\t}\n\n\treturn 1 + mtd_desc_nr + payload_nfrags;\n}",
        "static void test_setsockopt_legacy_no_override(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL, *link_legacy_eperm = NULL;\n\tstruct bpf_link *link_get_retval = NULL;": "static void test_setsockopt_legacy_no_override(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL, *link_legacy_eperm = NULL;\n\tstruct bpf_link *link_get_retval = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that sets EUNATCH, then one that return a reject\n\t * without setting errno, and then one that gets the exported errno.\n\t * Assert both the syscall and the helper's errno are unaffected by\n\t * the second prog (i.e. legacy rejects does not override the errno\n\t * to EPERM).\n\t */\n\tlink_set_eunatch = bpf_program__attach_cgroup(obj->progs.set_eunatch,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eunatch, \"cg-attach-set_eunatch\"))\n\t\tgoto close_bpf_object;\n\tlink_legacy_eperm = bpf_program__attach_cgroup(obj->progs.legacy_eperm,\n\t\t\t\t\t\t       cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_legacy_eperm, \"cg-attach-legacy_eperm\"))\n\t\tgoto close_bpf_object;\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t   &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EUNATCH, \"setsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 3, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, -EUNATCH, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_set_eunatch);\n\tbpf_link__destroy(link_legacy_eperm);\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static int check_return_code(struct bpf_verifier_env *env)\n{\n\tstruct tnum enforce_attach_type_range = tnum_unknown;\n\tconst struct bpf_prog *prog = env->prog;\n\tstruct bpf_reg_state *reg;": "static int check_return_code(struct bpf_verifier_env *env)\n{\n\tstruct tnum enforce_attach_type_range = tnum_unknown;\n\tconst struct bpf_prog *prog = env->prog;\n\tstruct bpf_reg_state *reg;\n\tstruct tnum range = tnum_range(0, 1);\n\tenum bpf_prog_type prog_type = resolve_prog_type(env->prog);\n\tint err;\n\tstruct bpf_func_state *frame = env->cur_state->frame[0];\n\tconst bool is_subprog = frame->subprogno;\n\n\t/* LSM and struct_ops func-ptr's return type could be \"void\" */\n\tif (!is_subprog &&\n\t    (prog_type == BPF_PROG_TYPE_STRUCT_OPS ||\n\t     prog_type == BPF_PROG_TYPE_LSM) &&\n\t    !prog->aux->attach_func_proto->type)\n\t\treturn 0;\n\n\t/* eBPF calling convention is such that R0 is used\n\t * to return the value from eBPF program.\n\t * Make sure that it's readable at this time\n\t * of bpf_exit, which means that program wrote\n\t * something into it earlier\n\t */\n\terr = check_reg_arg(env, BPF_REG_0, SRC_OP);\n\tif (err)\n\t\treturn err;\n\n\tif (is_pointer_value(env, BPF_REG_0)) {\n\t\tverbose(env, \"R0 leaks addr as return value\\n\");\n\t\treturn -EACCES;\n\t}\n\n\treg = cur_regs(env) + BPF_REG_0;\n\n\tif (frame->in_async_callback_fn) {\n\t\t/* enforce return zero from async callbacks like timer */\n\t\tif (reg->type != SCALAR_VALUE) {\n\t\t\tverbose(env, \"In async callback the register R0 is not a known value (%s)\\n\",\n\t\t\t\treg_type_str(env, reg->type));\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (!tnum_in(tnum_const(0), reg->var_off)) {\n\t\t\tverbose_invalid_scalar(env, reg, &range, \"async callback\", \"R0\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\treturn 0;\n\t}\n\n\tif (is_subprog) {\n\t\tif (reg->type != SCALAR_VALUE) {\n\t\t\tverbose(env, \"At subprogram exit the register R0 is not a scalar value (%s)\\n\",\n\t\t\t\treg_type_str(env, reg->type));\n\t\t\treturn -EINVAL;\n\t\t}\n\t\treturn 0;\n\t}\n\n\tswitch (prog_type) {\n\tcase BPF_PROG_TYPE_CGROUP_SOCK_ADDR:\n\t\tif (env->prog->expected_attach_type == BPF_CGROUP_UDP4_RECVMSG ||\n\t\t    env->prog->expected_attach_type == BPF_CGROUP_UDP6_RECVMSG ||\n\t\t    env->prog->expected_attach_type == BPF_CGROUP_INET4_GETPEERNAME ||\n\t\t    env->prog->expected_attach_type == BPF_CGROUP_INET6_GETPEERNAME ||\n\t\t    env->prog->expected_attach_type == BPF_CGROUP_INET4_GETSOCKNAME ||\n\t\t    env->prog->expected_attach_type == BPF_CGROUP_INET6_GETSOCKNAME)\n\t\t\trange = tnum_range(1, 1);\n\t\tif (env->prog->expected_attach_type == BPF_CGROUP_INET4_BIND ||\n\t\t    env->prog->expected_attach_type == BPF_CGROUP_INET6_BIND)\n\t\t\trange = tnum_range(0, 3);\n\t\tbreak;\n\tcase BPF_PROG_TYPE_CGROUP_SKB:\n\t\tif (env->prog->expected_attach_type == BPF_CGROUP_INET_EGRESS) {\n\t\t\trange = tnum_range(0, 3);\n\t\t\tenforce_attach_type_range = tnum_range(2, 3);\n\t\t}\n\t\tbreak;\n\tcase BPF_PROG_TYPE_CGROUP_SOCK:\n\tcase BPF_PROG_TYPE_SOCK_OPS:\n\tcase BPF_PROG_TYPE_CGROUP_DEVICE:\n\tcase BPF_PROG_TYPE_CGROUP_SYSCTL:\n\tcase BPF_PROG_TYPE_CGROUP_SOCKOPT:\n\t\tbreak;\n\tcase BPF_PROG_TYPE_RAW_TRACEPOINT:\n\t\tif (!env->prog->aux->attach_btf_id)\n\t\t\treturn 0;\n\t\trange = tnum_const(0);\n\t\tbreak;\n\tcase BPF_PROG_TYPE_TRACING:\n\t\tswitch (env->prog->expected_attach_type) {\n\t\tcase BPF_TRACE_FENTRY:\n\t\tcase BPF_TRACE_FEXIT:\n\t\t\trange = tnum_const(0);\n\t\t\tbreak;\n\t\tcase BPF_TRACE_RAW_TP:\n\t\tcase BPF_MODIFY_RETURN:\n\t\t\treturn 0;\n\t\tcase BPF_TRACE_ITER:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -ENOTSUPP;\n\t\t}\n\t\tbreak;\n\tcase BPF_PROG_TYPE_SK_LOOKUP:\n\t\trange = tnum_range(SK_DROP, SK_PASS);\n\t\tbreak;\n\tcase BPF_PROG_TYPE_EXT:\n\t\t/* freplace program can return anything as its return value\n\t\t * depends on the to-be-replaced kernel func or bpf program.\n\t\t */\n\tdefault:\n\t\treturn 0;\n\t}\n\n\tif (reg->type != SCALAR_VALUE) {\n\t\tverbose(env, \"At program exit the register R0 is not a known value (%s)\\n\",\n\t\t\treg_type_str(env, reg->type));\n\t\treturn -EINVAL;\n\t}\n\n\tif (!tnum_in(range, reg->var_off)) {\n\t\tverbose_invalid_scalar(env, reg, &range, \"program exit\", \"R0\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (!tnum_is_unknown(enforce_attach_type_range) &&\n\t    tnum_in(enforce_attach_type_range, reg->var_off))\n\t\tenv->prog->enforce_expected_attach_type = 1;\n\treturn 0;\n}",
        "static void thread_common_ops(struct test_spec *test, struct ifobject *ifobject)\n{\n\tu64 umem_sz = ifobject->umem->num_frames * ifobject->umem->frame_size;\n\tint mmap_flags = MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE;\n\tint ret, ifindex;": "static void thread_common_ops(struct test_spec *test, struct ifobject *ifobject)\n{\n\tu64 umem_sz = ifobject->umem->num_frames * ifobject->umem->frame_size;\n\tint mmap_flags = MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE;\n\tint ret, ifindex;\n\tvoid *bufs;\n\tu32 i;\n\n\tifobject->ns_fd = switch_namespace(ifobject->nsname);\n\n\tif (ifobject->umem->unaligned_mode)\n\t\tmmap_flags |= MAP_HUGETLB;\n\n\tbufs = mmap(NULL, umem_sz, PROT_READ | PROT_WRITE, mmap_flags, -1, 0);\n\tif (bufs == MAP_FAILED)\n\t\texit_with_error(errno);\n\n\tret = xsk_configure_umem(ifobject->umem, bufs, umem_sz);\n\tif (ret)\n\t\texit_with_error(-ret);\n\n\tfor (i = 0; i < test->nb_sockets; i++) {\n\t\tu32 ctr = 0;\n\n\t\twhile (ctr++ < SOCK_RECONF_CTR) {\n\t\t\tret = xsk_configure_socket(&ifobject->xsk_arr[i], ifobject->umem,\n\t\t\t\t\t\t   ifobject, !!i);\n\t\t\tif (!ret)\n\t\t\t\tbreak;\n\n\t\t\t/* Retry if it fails as xsk_socket__create() is asynchronous */\n\t\t\tif (ctr >= SOCK_RECONF_CTR)\n\t\t\t\texit_with_error(-ret);\n\t\t\tusleep(USLEEP_MAX);\n\t\t}\n\n\t\tif (ifobject->busy_poll)\n\t\t\tenable_busy_poll(&ifobject->xsk_arr[i]);\n\t}\n\n\tifobject->xsk = &ifobject->xsk_arr[0];\n\n\tif (!ifobject->rx_on)\n\t\treturn;\n\n\tifindex = if_nametoindex(ifobject->ifname);\n\tif (!ifindex)\n\t\texit_with_error(errno);\n\n\tret = xsk_setup_xdp_prog(ifindex, &ifobject->xsk_map_fd);\n\tif (ret)\n\t\texit_with_error(-ret);\n\n\tret = xsk_socket__update_xskmap(ifobject->xsk->xsk, ifobject->xsk_map_fd);\n\tif (ret)\n\t\texit_with_error(-ret);\n}",
        "static void test_getsockopt_retval_sync(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_getsockopt *obj;\n\tstruct bpf_link *link_set_eisconn = NULL, *link_clear_retval = NULL;\n\tstruct bpf_link *link_get_retval = NULL;": "static void test_getsockopt_retval_sync(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_getsockopt *obj;\n\tstruct bpf_link *link_set_eisconn = NULL, *link_clear_retval = NULL;\n\tstruct bpf_link *link_get_retval = NULL;\n\tint buf;\n\tsocklen_t optlen = sizeof(buf);\n\n\tobj = cgroup_getset_retval_getsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach getsockopt that sets retval to -EISCONN, and one that clears\n\t * ctx retval. Assert that the clearing ctx retval is synced to helper\n\t * and clears any errors both from kernel and BPF..\n\t */\n\tlink_set_eisconn = bpf_program__attach_cgroup(obj->progs.set_eisconn,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eisconn, \"cg-attach-set_eisconn\"))\n\t\tgoto close_bpf_object;\n\tlink_clear_retval = bpf_program__attach_cgroup(obj->progs.clear_retval,\n\t\t\t\t\t\t       cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_clear_retval, \"cg-attach-clear_retval\"))\n\t\tgoto close_bpf_object;\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_OK(getsockopt(sock_fd, SOL_CUSTOM, 0,\n\t\t\t\t  &buf, &optlen), \"getsockopt\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 3, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, 0, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->ctx_retval_value, 0, \"ctx_retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_set_eisconn);\n\tbpf_link__destroy(link_clear_retval);\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_getsockopt__destroy(obj);\n}",
        "static struct key_vector *resize(struct trie *t, struct key_vector *tn)\n{\n#ifdef CONFIG_IP_FIB_TRIE_STATS\n\tstruct trie_use_stats __percpu *stats = t->stats;\n#endif": "static struct key_vector *resize(struct trie *t, struct key_vector *tn)\n{\n#ifdef CONFIG_IP_FIB_TRIE_STATS\n\tstruct trie_use_stats __percpu *stats = t->stats;\n#endif\n\tstruct key_vector *tp = node_parent(tn);\n\tunsigned long cindex = get_index(tn->key, tp);\n\tint max_work = MAX_WORK;\n\n\tpr_debug(\"In tnode_resize %p inflate_threshold=%d threshold=%d\\n\",\n\t\t tn, inflate_threshold, halve_threshold);\n\n\t/* track the tnode via the pointer from the parent instead of\n\t * doing it ourselves.  This way we can let RCU fully do its\n\t * thing without us interfering\n\t */\n\tBUG_ON(tn != get_child(tp, cindex));\n\n\t/* Double as long as the resulting node has a number of\n\t * nonempty nodes that are above the threshold.\n\t */\n\twhile (should_inflate(tp, tn) && max_work) {\n\t\ttp = inflate(t, tn);\n\t\tif (!tp) {\n#ifdef CONFIG_IP_FIB_TRIE_STATS\n\t\t\tthis_cpu_inc(stats->resize_node_skipped);\n#endif\n\t\t\tbreak;\n\t\t}\n\n\t\tmax_work--;\n\t\ttn = get_child(tp, cindex);\n\t}\n\n\t/* update parent in case inflate failed */\n\ttp = node_parent(tn);\n\n\t/* Return if at least one inflate is run */\n\tif (max_work != MAX_WORK)\n\t\treturn tp;\n\n\t/* Halve as long as the number of empty children in this\n\t * node is above threshold.\n\t */\n\twhile (should_halve(tp, tn) && max_work) {\n\t\ttp = halve(t, tn);\n\t\tif (!tp) {\n#ifdef CONFIG_IP_FIB_TRIE_STATS\n\t\t\tthis_cpu_inc(stats->resize_node_skipped);\n#endif\n\t\t\tbreak;\n\t\t}\n\n\t\tmax_work--;\n\t\ttn = get_child(tp, cindex);\n\t}\n\n\t/* Only one child remains */\n\tif (should_collapse(tn))\n\t\treturn collapse(t, tn);\n\n\t/* update parent in case halve failed */\n\treturn node_parent(tn);\n}",
        "static int yas5xx_get_measure(struct yas5xx *yas5xx, s32 *to, s32 *xo, s32 *yo, s32 *zo)\n{\n\tstruct yas5xx_calibration *c = &yas5xx->calibration;\n\tu16 t, x, y1, y2;\n\t/* These are \"signed x, signed y1 etc */": "static int yas5xx_get_measure(struct yas5xx *yas5xx, s32 *to, s32 *xo, s32 *yo, s32 *zo)\n{\n\tstruct yas5xx_calibration *c = &yas5xx->calibration;\n\tu16 t, x, y1, y2;\n\t/* These are \"signed x, signed y1 etc */\n\ts32 sx, sy1, sy2, sy, sz;\n\tint ret;\n\n\t/* We first get raw data that needs to be translated to [x,y,z] */\n\tret = yas5xx_measure(yas5xx, &t, &x, &y1, &y2);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Do some linearization if available */\n\tsx = yas5xx_linearize(yas5xx, x, 0);\n\tsy1 = yas5xx_linearize(yas5xx, y1, 1);\n\tsy2 = yas5xx_linearize(yas5xx, y2, 2);\n\n\t/*\n\t * Temperature compensation for x, y1, y2 respectively:\n\t *\n\t *          Cx * t\n\t * x' = x - ------\n\t *           100\n\t */\n\tsx = sx - (c->Cx * t) / 100;\n\tsy1 = sy1 - (c->Cy1 * t) / 100;\n\tsy2 = sy2 - (c->Cy2 * t) / 100;\n\n\t/*\n\t * Break y1 and y2 into y and z, y1 and y2 are apparently encoding\n\t * y and z.\n\t */\n\tsy = sy1 - sy2;\n\tsz = -sy1 - sy2;\n\n\t/*\n\t * FIXME: convert to Celsius? Just guessing this is given\n\t * as 1/10:s of degrees so multiply by 100 to get millicentigrades.\n\t */\n\t*to = t * 100;\n\t/*\n\t * Calibrate [x,y,z] with some formulas like this:\n\t *\n\t *            100 * x + a_2 * y + a_3 * z\n\t *  x' = k *  ---------------------------\n\t *                        10\n\t *\n\t *           a_4 * x + a_5 * y + a_6 * z\n\t *  y' = k * ---------------------------\n\t *                        10\n\t *\n\t *           a_7 * x + a_8 * y + a_9 * z\n\t *  z' = k * ---------------------------\n\t *                        10\n\t */\n\t*xo = c->k * ((100 * sx + c->a2 * sy + c->a3 * sz) / 10);\n\t*yo = c->k * ((c->a4 * sx + c->a5 * sy + c->a6 * sz) / 10);\n\t*zo = c->k * ((c->a7 * sx + c->a8 * sy + c->a9 * sz) / 10);\n\n\treturn 0;\n}",
        "static void Usage(void)\n{\n\tprintf(\"This program loads a cgroup skb BPF program to enforce\\n\"\n\t       \"cgroup output (egress) bandwidth limits.\\n\\n\"\n\t       \"USAGE: hbm [-o] [-d]  [-l] [-n <id>] [--no_cn] [-r <rate>]\\n\"": "static void Usage(void)\n{\n\tprintf(\"This program loads a cgroup skb BPF program to enforce\\n\"\n\t       \"cgroup output (egress) bandwidth limits.\\n\\n\"\n\t       \"USAGE: hbm [-o] [-d]  [-l] [-n <id>] [--no_cn] [-r <rate>]\\n\"\n\t       \"           [-s] [-t <secs>] [-w] [-h] [prog]\\n\"\n\t       \"  Where:\\n\"\n\t       \"    -o         indicates egress direction (default)\\n\"\n\t       \"    -d         print BPF trace debug buffer\\n\"\n\t       \"    --edt      use fq's Earliest Departure Time\\n\"\n\t       \"    -l         also limit flows using loopback\\n\"\n\t       \"    -n <#>     to create cgroup \\\"/hbm#\\\" and attach prog\\n\"\n\t       \"               Default is /hbm1\\n\"\n\t       \"    --no_cn    disable CN notifications\\n\"\n\t       \"    -r <rate>  Rate in Mbps\\n\"\n\t       \"    -s         Update HBM stats\\n\"\n\t       \"    -t <time>  Exit after specified seconds (default is 0)\\n\"\n\t       \"    -w\t       Work conserving flag. cgroup can increase\\n\"\n\t       \"               bandwidth beyond the rate limit specified\\n\"\n\t       \"               while there is available bandwidth. Current\\n\"\n\t       \"               implementation assumes there is only eth0\\n\"\n\t       \"               but can be extended to support multiple NICs\\n\"\n\t       \"    -h         print this info\\n\"\n\t       \"    prog       BPF program file name. Name defaults to\\n\"\n\t       \"                 hbm_out_kern.o\\n\");\n}",
        "static int capture_start(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_pipeline *me;\n\tunsigned int thread_id;\n": "static int capture_start(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_pipeline *me;\n\tunsigned int thread_id;\n\n\tint err = 0;\n\tenum sh_css_pipe_config_override copy_ovrd;\n\n\tIA_CSS_ENTER_PRIVATE(\"pipe = %p\", pipe);\n\tif (!pipe) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(-EINVAL);\n\t\treturn -EINVAL;\n\t}\n\n\tme = &pipe->pipeline;\n\n\tif ((pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW   ||\n\t     pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) &&\n\t    (pipe->config.mode != IA_CSS_PIPE_MODE_COPY)) {\n\t\tif (copy_on_sp(pipe)) {\n\t\t\terr = start_copy_on_sp(pipe, &me->out_frame[0]);\n\t\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\t\treturn err;\n\t\t}\n\t}\n\n#if !defined(ISP2401)\n\t/* old isys: need to send_mipi_frames() in all pipe modes */\n\terr = send_mipi_frames(pipe);\n\tif (err) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\treturn err;\n\t}\n#else\n\tif (pipe->config.mode != IA_CSS_PIPE_MODE_COPY) {\n\t\terr = send_mipi_frames(pipe);\n\t\tif (err) {\n\t\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\t\treturn err;\n\t\t}\n\t}\n#endif\n\n\tia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);\n\tcopy_ovrd = 1 << thread_id;\n\n\tstart_pipe(pipe, copy_ovrd, pipe->stream->config.mode);\n\n#if !defined(ISP2401)\n\t/*\n\t * old isys: for IA_CSS_PIPE_MODE_COPY pipe, isys rx has to be configured,\n\t * which is currently done in start_binary(); but COPY pipe contains no binary,\n\t * and does not call start_binary(); so we need to configure the rx here.\n\t */\n\tif (pipe->config.mode == IA_CSS_PIPE_MODE_COPY &&\n\t    pipe->stream->reconfigure_css_rx) {\n\t\tia_css_isys_rx_configure(&pipe->stream->csi_rx_config,\n\t\t\t\t\t pipe->stream->config.mode);\n\t\tpipe->stream->reconfigure_css_rx = false;\n\t}\n#endif\n\n\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\treturn err;\n}",
        "static int add_host_bridge_uport(struct device *match, void *arg)\n{\n\tstruct cxl_port *root_port = arg;\n\tstruct device *host = root_port->dev.parent;\n\tstruct acpi_device *bridge = to_cxl_host_bridge(host, match);": "static int add_host_bridge_uport(struct device *match, void *arg)\n{\n\tstruct cxl_port *root_port = arg;\n\tstruct device *host = root_port->dev.parent;\n\tstruct acpi_device *bridge = to_cxl_host_bridge(host, match);\n\tstruct acpi_pci_root *pci_root;\n\tstruct cxl_dport *dport;\n\tstruct cxl_port *port;\n\tint rc;\n\n\tif (!bridge)\n\t\treturn 0;\n\n\tdport = cxl_find_dport_by_dev(root_port, match);\n\tif (!dport) {\n\t\tdev_dbg(host, \"host bridge expected and not found\\n\");\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Note that this lookup already succeeded in\n\t * to_cxl_host_bridge(), so no need to check for failure here\n\t */\n\tpci_root = acpi_pci_find_root(bridge->handle);\n\trc = devm_cxl_register_pci_bus(host, match, pci_root->bus);\n\tif (rc)\n\t\treturn rc;\n\n\tport = devm_cxl_add_port(host, match, dport->component_reg_phys,\n\t\t\t\t root_port);\n\tif (IS_ERR(port))\n\t\treturn PTR_ERR(port);\n\tdev_dbg(host, \"%s: add: %s\\n\", dev_name(match), dev_name(&port->dev));\n\n\treturn 0;\n}",
        "static int newidle_balance(struct rq *this_rq, struct rq_flags *rf)\n{\n\tunsigned long next_balance = jiffies + HZ;\n\tint this_cpu = this_rq->cpu;\n\tu64 t0, t1, curr_cost = 0;": "static int newidle_balance(struct rq *this_rq, struct rq_flags *rf)\n{\n\tunsigned long next_balance = jiffies + HZ;\n\tint this_cpu = this_rq->cpu;\n\tu64 t0, t1, curr_cost = 0;\n\tstruct sched_domain *sd;\n\tint pulled_task = 0;\n\n\tupdate_misfit_status(NULL, this_rq);\n\n\t/*\n\t * There is a task waiting to run. No need to search for one.\n\t * Return 0; the task will be enqueued when switching to idle.\n\t */\n\tif (this_rq->ttwu_pending)\n\t\treturn 0;\n\n\t/*\n\t * We must set idle_stamp _before_ calling idle_balance(), such that we\n\t * measure the duration of idle_balance() as idle time.\n\t */\n\tthis_rq->idle_stamp = rq_clock(this_rq);\n\n\t/*\n\t * Do not pull tasks towards !active CPUs...\n\t */\n\tif (!cpu_active(this_cpu))\n\t\treturn 0;\n\n\t/*\n\t * This is OK, because current is on_cpu, which avoids it being picked\n\t * for load-balance and preemption/IRQs are still disabled avoiding\n\t * further scheduler activity on it and we're being very careful to\n\t * re-start the picking loop.\n\t */\n\trq_unpin_lock(this_rq, rf);\n\n\trcu_read_lock();\n\tsd = rcu_dereference_check_sched_domain(this_rq->sd);\n\n\tif (!READ_ONCE(this_rq->rd->overload) ||\n\t    (sd && this_rq->avg_idle < sd->max_newidle_lb_cost)) {\n\n\t\tif (sd)\n\t\t\tupdate_next_balance(sd, &next_balance);\n\t\trcu_read_unlock();\n\n\t\tgoto out;\n\t}\n\trcu_read_unlock();\n\n\traw_spin_rq_unlock(this_rq);\n\n\tt0 = sched_clock_cpu(this_cpu);\n\tupdate_blocked_averages(this_cpu);\n\n\trcu_read_lock();\n\tfor_each_domain(this_cpu, sd) {\n\t\tint continue_balancing = 1;\n\t\tu64 domain_cost;\n\n\t\tupdate_next_balance(sd, &next_balance);\n\n\t\tif (this_rq->avg_idle < curr_cost + sd->max_newidle_lb_cost)\n\t\t\tbreak;\n\n\t\tif (sd->flags & SD_BALANCE_NEWIDLE) {\n\n\t\t\tpulled_task = load_balance(this_cpu, this_rq,\n\t\t\t\t\t\t   sd, CPU_NEWLY_IDLE,\n\t\t\t\t\t\t   &continue_balancing);\n\n\t\t\tt1 = sched_clock_cpu(this_cpu);\n\t\t\tdomain_cost = t1 - t0;\n\t\t\tupdate_newidle_cost(sd, domain_cost);\n\n\t\t\tcurr_cost += domain_cost;\n\t\t\tt0 = t1;\n\t\t}\n\n\t\t/*\n\t\t * Stop searching for tasks to pull if there are\n\t\t * now runnable tasks on this rq.\n\t\t */\n\t\tif (pulled_task || this_rq->nr_running > 0 ||\n\t\t    this_rq->ttwu_pending)\n\t\t\tbreak;\n\t}\n\trcu_read_unlock();\n\n\traw_spin_rq_lock(this_rq);\n\n\tif (curr_cost > this_rq->max_idle_balance_cost)\n\t\tthis_rq->max_idle_balance_cost = curr_cost;\n\n\t/*\n\t * While browsing the domains, we released the rq lock, a task could\n\t * have been enqueued in the meantime. Since we're not going idle,\n\t * pretend we pulled a task.\n\t */\n\tif (this_rq->cfs.h_nr_running && !pulled_task)\n\t\tpulled_task = 1;\n\n\t/* Is there a task of a high priority class? */\n\tif (this_rq->nr_running != this_rq->cfs.h_nr_running)\n\t\tpulled_task = -1;\n\nout:\n\t/* Move the next balance forward */\n\tif (time_after(this_rq->next_balance, next_balance))\n\t\tthis_rq->next_balance = next_balance;\n\n\tif (pulled_task)\n\t\tthis_rq->idle_stamp = 0;\n\telse\n\t\tnohz_newidle_balance(this_rq);\n\n\trq_repin_lock(this_rq, rf);\n\n\treturn pulled_task;\n}",
        "static void mana_gd_process_eqe(struct gdma_queue *eq)\n{\n\tu32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE);\n\tstruct gdma_context *gc = eq->gdma_dev->gdma_context;\n\tstruct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr;": "static void mana_gd_process_eqe(struct gdma_queue *eq)\n{\n\tu32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE);\n\tstruct gdma_context *gc = eq->gdma_dev->gdma_context;\n\tstruct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr;\n\tunion gdma_eqe_info eqe_info;\n\tenum gdma_eqe_type type;\n\tstruct gdma_event event;\n\tstruct gdma_queue *cq;\n\tstruct gdma_eqe *eqe;\n\tu32 cq_id;\n\n\teqe = &eq_eqe_ptr[head];\n\teqe_info.as_uint32 = eqe->eqe_info;\n\ttype = eqe_info.type;\n\n\tswitch (type) {\n\tcase GDMA_EQE_COMPLETION:\n\t\tcq_id = eqe->details[0] & 0xFFFFFF;\n\t\tif (WARN_ON_ONCE(cq_id >= gc->max_num_cqs))\n\t\t\tbreak;\n\n\t\tcq = gc->cq_table[cq_id];\n\t\tif (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id))\n\t\t\tbreak;\n\n\t\tif (cq->cq.callback)\n\t\t\tcq->cq.callback(cq->cq.context, cq);\n\n\t\tbreak;\n\n\tcase GDMA_EQE_TEST_EVENT:\n\t\tgc->test_event_eq_id = eq->id;\n\t\tcomplete(&gc->eq_test_event);\n\t\tbreak;\n\n\tcase GDMA_EQE_HWC_INIT_EQ_ID_DB:\n\tcase GDMA_EQE_HWC_INIT_DATA:\n\tcase GDMA_EQE_HWC_INIT_DONE:\n\t\tif (!eq->eq.callback)\n\t\t\tbreak;\n\n\t\tevent.type = type;\n\t\tmemcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE);\n\t\teq->eq.callback(eq->eq.context, eq, &event);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}",
        "static int hotkey_kthread(void *data)\n{\n\tstruct tp_nvram_state s[2] = { 0 };\n\tu32 poll_mask, event_mask;\n\tunsigned int si, so;": "static int hotkey_kthread(void *data)\n{\n\tstruct tp_nvram_state s[2] = { 0 };\n\tu32 poll_mask, event_mask;\n\tunsigned int si, so;\n\tunsigned long t;\n\tunsigned int change_detector;\n\tunsigned int poll_freq;\n\tbool was_frozen;\n\n\tif (tpacpi_lifecycle == TPACPI_LIFE_EXITING)\n\t\tgoto exit;\n\n\tset_freezable();\n\n\tso = 0;\n\tsi = 1;\n\tt = 0;\n\n\t/* Initial state for compares */\n\tmutex_lock(&hotkey_thread_data_mutex);\n\tchange_detector = hotkey_config_change;\n\tpoll_mask = hotkey_source_mask;\n\tevent_mask = hotkey_source_mask &\n\t\t\t(hotkey_driver_mask | hotkey_user_mask);\n\tpoll_freq = hotkey_poll_freq;\n\tmutex_unlock(&hotkey_thread_data_mutex);\n\thotkey_read_nvram(&s[so], poll_mask);\n\n\twhile (!kthread_should_stop()) {\n\t\tif (t == 0) {\n\t\t\tif (likely(poll_freq))\n\t\t\t\tt = 1000/poll_freq;\n\t\t\telse\n\t\t\t\tt = 100;\t/* should never happen... */\n\t\t}\n\t\tt = msleep_interruptible(t);\n\t\tif (unlikely(kthread_freezable_should_stop(&was_frozen)))\n\t\t\tbreak;\n\n\t\tif (t > 0 && !was_frozen)\n\t\t\tcontinue;\n\n\t\tmutex_lock(&hotkey_thread_data_mutex);\n\t\tif (was_frozen || hotkey_config_change != change_detector) {\n\t\t\t/* forget old state on thaw or config change */\n\t\t\tsi = so;\n\t\t\tt = 0;\n\t\t\tchange_detector = hotkey_config_change;\n\t\t}\n\t\tpoll_mask = hotkey_source_mask;\n\t\tevent_mask = hotkey_source_mask &\n\t\t\t\t(hotkey_driver_mask | hotkey_user_mask);\n\t\tpoll_freq = hotkey_poll_freq;\n\t\tmutex_unlock(&hotkey_thread_data_mutex);\n\n\t\tif (likely(poll_mask)) {\n\t\t\thotkey_read_nvram(&s[si], poll_mask);\n\t\t\tif (likely(si != so)) {\n\t\t\t\thotkey_compare_and_issue_event(&s[so], &s[si],\n\t\t\t\t\t\t\t\tevent_mask);\n\t\t\t}\n\t\t}\n\n\t\tso = si;\n\t\tsi ^= 1;\n\t}\n\nexit:\n\treturn 0;\n}",
        "static inline void update_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags)\n{\n\tu64 now = cfs_rq_clock_pelt(cfs_rq);\n\tint decayed;\n": "static inline void update_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags)\n{\n\tu64 now = cfs_rq_clock_pelt(cfs_rq);\n\tint decayed;\n\n\t/*\n\t * Track task load average for carrying it to new CPU after migrated, and\n\t * track group sched_entity load average for task_h_load calc in migration\n\t */\n\tif (se->avg.last_update_time && !(flags & SKIP_AGE_LOAD))\n\t\t__update_load_avg_se(now, cfs_rq, se);\n\n\tdecayed  = update_cfs_rq_load_avg(now, cfs_rq);\n\tdecayed |= propagate_entity_load_avg(se);\n\n\tif (!se->avg.last_update_time && (flags & DO_ATTACH)) {\n\n\t\t/*\n\t\t * DO_ATTACH means we're here from enqueue_entity().\n\t\t * !last_update_time means we've passed through\n\t\t * migrate_task_rq_fair() indicating we migrated.\n\t\t *\n\t\t * IOW we're enqueueing a task on a new CPU.\n\t\t */\n\t\tattach_entity_load_avg(cfs_rq, se);\n\t\tupdate_tg_load_avg(cfs_rq);\n\n\t} else if (decayed) {\n\t\tcfs_rq_util_change(cfs_rq, 0);\n\n\t\tif (flags & UPDATE_TG)\n\t\t\tupdate_tg_load_avg(cfs_rq);\n\t}\n}",
        "static void test_setsockopt_override(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL, *link_set_eisconn = NULL;\n\tstruct bpf_link *link_get_retval = NULL;": "static void test_setsockopt_override(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL, *link_set_eisconn = NULL;\n\tstruct bpf_link *link_get_retval = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that sets EUNATCH, then one that sets EISCONN,\n\t * and then one that gets the exported errno. Assert both the syscall\n\t * and the helper sees the last set errno.\n\t */\n\tlink_set_eunatch = bpf_program__attach_cgroup(obj->progs.set_eunatch,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eunatch, \"cg-attach-set_eunatch\"))\n\t\tgoto close_bpf_object;\n\tlink_set_eisconn = bpf_program__attach_cgroup(obj->progs.set_eisconn,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eisconn, \"cg-attach-set_eisconn\"))\n\t\tgoto close_bpf_object;\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t   &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EISCONN, \"setsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 3, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, -EISCONN, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_set_eunatch);\n\tbpf_link__destroy(link_set_eisconn);\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static bool mlx5e_napi_xsk_post(struct mlx5e_xdpsq *xsksq, struct mlx5e_rq *xskrq)\n{\n\tbool busy_xsk = false, xsk_rx_alloc_err;\n\n\t/* Handle the race between the application querying need_wakeup and the": "static bool mlx5e_napi_xsk_post(struct mlx5e_xdpsq *xsksq, struct mlx5e_rq *xskrq)\n{\n\tbool busy_xsk = false, xsk_rx_alloc_err;\n\n\t/* Handle the race between the application querying need_wakeup and the\n\t * driver setting it:\n\t * 1. Update need_wakeup both before and after the TX. If it goes to\n\t * \"yes\", it can only happen with the first update.\n\t * 2. If the application queried need_wakeup before we set it, the\n\t * packets will be transmitted anyway, even w/o a wakeup.\n\t * 3. Give a chance to clear need_wakeup after new packets were queued\n\t * for TX.\n\t */\n\tmlx5e_xsk_update_tx_wakeup(xsksq);\n\tbusy_xsk |= mlx5e_xsk_tx(xsksq, MLX5E_TX_XSK_POLL_BUDGET);\n\tmlx5e_xsk_update_tx_wakeup(xsksq);\n\n\txsk_rx_alloc_err = INDIRECT_CALL_2(xskrq->post_wqes,\n\t\t\t\t\t   mlx5e_post_rx_mpwqes,\n\t\t\t\t\t   mlx5e_post_rx_wqes,\n\t\t\t\t\t   xskrq);\n\tbusy_xsk |= mlx5e_xsk_update_rx_wakeup(xskrq, xsk_rx_alloc_err);\n\n\treturn busy_xsk;\n}",
        "static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)\n{\n\tu32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;\n\n\tvpu_malone_fill_planes(info);": "static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)\n{\n\tu32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;\n\n\tvpu_malone_fill_planes(info);\n\n\tinfo->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;\n\tinfo->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);\n\n\tinfo->dcp_size = MALONE_DCP_SIZE_MAX;\n\tif (chunks) {\n\t\tu32 mb_num;\n\t\tu32 mb_w;\n\t\tu32 mb_h;\n\n\t\tmb_w = DIV_ROUND_UP(info->decoded_width, 16);\n\t\tmb_h = DIV_ROUND_UP(info->decoded_height, 16);\n\t\tmb_num = mb_w * mb_h;\n\t\tinfo->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;\n\t\tinfo->dcp_size = clamp_t(u32, info->dcp_size,\n\t\t\t\t\t MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);\n\t}\n}",
        "static void addpair(int fp, int un)\n{\n  int i;\n\n  if ( un <= 0xfffe )": "static void addpair(int fp, int un)\n{\n  int i;\n\n  if ( un <= 0xfffe )\n    {\n      /* Check it isn't a duplicate */\n\n      for ( i = 0 ; i < unicount[fp] ; i++ )\n\tif ( unitable[fp][i] == un )\n\t  return;\n\n      /* Add to list */\n\n      if ( unicount[fp] > 254 )\n\t{\n\t  fprintf(stderr, \"ERROR: Only 255 unicodes/glyph permitted!\\n\");\n\t  exit(EX_DATAERR);\n\t}\n\n      unitable[fp][unicount[fp]] = un;\n      unicount[fp]++;\n    }\n\n  /* otherwise: ignore */\n}",
        "static int ca_get_ca_info(struct dst_state *state)\n{\n\tint srcPtr, dstPtr, i, num_ids;\n\tstatic u8 slot_command[8] = {0x07, 0x40, 0x00, 0x00, 0x02, 0x00, 0x00, 0xff};\n\tconst int in_system_id_pos = 8, out_system_id_pos = 4, in_num_ids_pos = 7;": "static int ca_get_ca_info(struct dst_state *state)\n{\n\tint srcPtr, dstPtr, i, num_ids;\n\tstatic u8 slot_command[8] = {0x07, 0x40, 0x00, 0x00, 0x02, 0x00, 0x00, 0xff};\n\tconst int in_system_id_pos = 8, out_system_id_pos = 4, in_num_ids_pos = 7;\n\n\tput_checksum(&slot_command[0], slot_command[0]);\n\tif ((dst_put_ci(state, slot_command, sizeof (slot_command), state->messages, GET_REPLY)) < 0) {\n\t\tdprintk(verbose, DST_CA_ERROR, 1, \" -->dst_put_ci FAILED !\");\n\t\treturn -EIO;\n\t}\n\tdprintk(verbose, DST_CA_INFO, 1, \" -->dst_put_ci SUCCESS !\");\n\n\t// Print raw data\n\tdprintk(verbose, DST_CA_INFO, 0, \" DST data = [\");\n\tfor (i = 0; i < state->messages[0] + 1; i++) {\n\t\tdprintk(verbose, DST_CA_INFO, 0, \" 0x%02x\", state->messages[i]);\n\t}\n\tdprintk(verbose, DST_CA_INFO, 0, \"]\\n\");\n\n\t// Set the command and length of the output\n\tnum_ids = state->messages[in_num_ids_pos];\n\tif (num_ids >= 100) {\n\t\tnum_ids = 100;\n\t\tdprintk(verbose, DST_CA_ERROR, 1, \"Invalid number of ids (>100). Recovering.\");\n\t}\n\tput_command_and_length(&state->messages[0], CA_INFO, num_ids * 2);\n\n\tdprintk(verbose, DST_CA_INFO, 0, \" CA_INFO = [\");\n\tsrcPtr = in_system_id_pos;\n\tdstPtr = out_system_id_pos;\n\tfor(i = 0; i < num_ids; i++) {\n\t\tdprintk(verbose, DST_CA_INFO, 0, \" 0x%02x%02x\", state->messages[srcPtr + 0], state->messages[srcPtr + 1]);\n\t\t// Append to output\n\t\tstate->messages[dstPtr + 0] = state->messages[srcPtr + 0];\n\t\tstate->messages[dstPtr + 1] = state->messages[srcPtr + 1];\n\t\tsrcPtr += 2;\n\t\tdstPtr += 2;\n\t}\n\tdprintk(verbose, DST_CA_INFO, 0, \"]\\n\");\n\n\treturn 0;\n}",
        "static void tick_sched_handle(struct tick_sched *ts, struct pt_regs *regs)\n{\n#ifdef CONFIG_NO_HZ_COMMON\n\t/*\n\t * When we are idle and the tick is stopped, we have to touch": "static void tick_sched_handle(struct tick_sched *ts, struct pt_regs *regs)\n{\n#ifdef CONFIG_NO_HZ_COMMON\n\t/*\n\t * When we are idle and the tick is stopped, we have to touch\n\t * the watchdog as we might not schedule for a really long\n\t * time. This happens on complete idle SMP systems while\n\t * waiting on the login prompt. We also increment the \"start of\n\t * idle\" jiffy stamp so the idle accounting adjustment we do\n\t * when we go busy again does not account too much ticks.\n\t */\n\tif (ts->tick_stopped) {\n\t\ttouch_softlockup_watchdog_sched();\n\t\tif (is_idle_task(current))\n\t\t\tts->idle_jiffies++;\n\t\t/*\n\t\t * In case the current tick fired too early past its expected\n\t\t * expiration, make sure we don't bypass the next clock reprogramming\n\t\t * to the same deadline.\n\t\t */\n\t\tts->next_tick = 0;\n\t}\n#endif\n\tupdate_process_times(user_mode(regs));\n\tprofile_tick(CPU_PROFILING);\n}",
        "static int load_video_binaries(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_frame_info video_in_info, tnr_info,\n\t\t       *video_vf_info, video_bds_out_info, *pipe_out_info, *pipe_vf_out_info;\n\tbool online;": "static int load_video_binaries(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_frame_info video_in_info, tnr_info,\n\t\t       *video_vf_info, video_bds_out_info, *pipe_out_info, *pipe_vf_out_info;\n\tbool online;\n\tint err = 0;\n\tbool continuous = pipe->stream->config.continuous;\n\tunsigned int i;\n\tunsigned int num_output_pins;\n\tstruct ia_css_frame_info video_bin_out_info;\n\tbool need_scaler = false;\n\tbool vf_res_different_than_output = false;\n\tbool need_vf_pp = false;\n\tint vf_ds_log2;\n\tstruct ia_css_video_settings *mycs  = &pipe->pipe_settings.video;\n\n\tIA_CSS_ENTER_PRIVATE(\"\");\n\tassert(pipe);\n\tassert(pipe->mode == IA_CSS_PIPE_ID_VIDEO);\n\t/*\n\t * we only test the video_binary because offline video doesn't need a\n\t * vf_pp binary and online does not (always use) the copy_binary.\n\t * All are always reset at the same time anyway.\n\t */\n\tif (mycs->video_binary.info)\n\t\treturn 0;\n\n\tonline = pipe->stream->config.online;\n\tpipe_out_info = &pipe->output_info[0];\n\tpipe_vf_out_info = &pipe->vf_output_info[0];\n\n\tassert(pipe_out_info);\n\n\t/*\n\t * There is no explicit input format requirement for raw or yuv\n\t * What matters is that there is a binary that supports the stream format.\n\t * This is checked in the binary_find(), so no need to check it here\n\t */\n\terr = ia_css_util_check_input(&pipe->stream->config, false, false);\n\tif (err)\n\t\treturn err;\n\t/* cannot have online video and input_mode memory */\n\tif (online && pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY)\n\t\treturn -EINVAL;\n\tif (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) {\n\t\terr = ia_css_util_check_vf_out_info(pipe_out_info,\n\t\t\t\t\t\t    pipe_vf_out_info);\n\t\tif (err)\n\t\t\treturn err;\n\t} else {\n\t\terr = ia_css_frame_check_info(pipe_out_info);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tif (pipe->out_yuv_ds_input_info.res.width)\n\t\tvideo_bin_out_info = pipe->out_yuv_ds_input_info;\n\telse\n\t\tvideo_bin_out_info = *pipe_out_info;\n\n\t/* Video */\n\tif (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) {\n\t\tvideo_vf_info = pipe_vf_out_info;\n\t\tvf_res_different_than_output = (video_vf_info->res.width !=\n\t\t\t\t\t\tvideo_bin_out_info.res.width) ||\n\t\t\t\t\t       (video_vf_info->res.height != video_bin_out_info.res.height);\n\t} else {\n\t\tvideo_vf_info = NULL;\n\t}\n\n\tneed_scaler = need_downscaling(video_bin_out_info.res, pipe_out_info->res);\n\n\t/* we build up the pipeline starting at the end */\n\t/* YUV post-processing if needed */\n\tif (need_scaler) {\n\t\tstruct ia_css_cas_binary_descr cas_scaler_descr = { };\n\n\t\t/* NV12 is the common format that is supported by both */\n\t\t/* yuv_scaler and the video_xx_isp2_min binaries. */\n\t\tvideo_bin_out_info.format = IA_CSS_FRAME_FORMAT_NV12;\n\n\t\terr = ia_css_pipe_create_cas_scaler_desc_single_output(\n\t\t\t  &video_bin_out_info,\n\t\t\t  pipe_out_info,\n\t\t\t  NULL,\n\t\t\t  &cas_scaler_descr);\n\t\tif (err)\n\t\t\treturn err;\n\t\tmycs->num_yuv_scaler = cas_scaler_descr.num_stage;\n\t\tmycs->yuv_scaler_binary = kcalloc(cas_scaler_descr.num_stage,\n\t\t\t\t\t\t  sizeof(struct ia_css_binary),\n\t\t\t\t\t\t  GFP_KERNEL);\n\t\tif (!mycs->yuv_scaler_binary) {\n\t\t\terr = -ENOMEM;\n\t\t\treturn err;\n\t\t}\n\t\tmycs->is_output_stage = kcalloc(cas_scaler_descr.num_stage,\n\t\t\t\t\t\tsizeof(bool), GFP_KERNEL);\n\t\tif (!mycs->is_output_stage) {\n\t\t\terr = -ENOMEM;\n\t\t\treturn err;\n\t\t}\n\t\tfor (i = 0; i < cas_scaler_descr.num_stage; i++) {\n\t\t\tstruct ia_css_binary_descr yuv_scaler_descr;\n\n\t\t\tmycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i];\n\t\t\tia_css_pipe_get_yuvscaler_binarydesc(pipe,\n\t\t\t\t\t\t\t     &yuv_scaler_descr, &cas_scaler_descr.in_info[i],\n\t\t\t\t\t\t\t     &cas_scaler_descr.out_info[i],\n\t\t\t\t\t\t\t     &cas_scaler_descr.internal_out_info[i],\n\t\t\t\t\t\t\t     &cas_scaler_descr.vf_info[i]);\n\t\t\terr = ia_css_binary_find(&yuv_scaler_descr,\n\t\t\t\t\t\t &mycs->yuv_scaler_binary[i]);\n\t\t\tif (err) {\n\t\t\t\tkfree(mycs->is_output_stage);\n\t\t\t\tmycs->is_output_stage = NULL;\n\t\t\t\treturn err;\n\t\t\t}\n\t\t}\n\t\tia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr);\n\t}\n\n\t{\n\t\tstruct ia_css_binary_descr video_descr;\n\t\tenum ia_css_frame_format vf_info_format;\n\n\t\terr = ia_css_pipe_get_video_binarydesc(pipe,\n\t\t\t\t\t\t       &video_descr, &video_in_info, &video_bds_out_info, &video_bin_out_info,\n\t\t\t\t\t\t       video_vf_info,\n\t\t\t\t\t\t       pipe->stream->config.left_padding);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\t/*\n\t\t * In the case where video_vf_info is not NULL, this allows\n\t\t * us to find a potential video library with desired vf format.\n\t\t * If success, no vf_pp binary is needed.\n\t\t * If failed, we will look up video binary with YUV_LINE vf format\n\t\t */\n\t\terr = ia_css_binary_find(&video_descr,\n\t\t\t\t\t &mycs->video_binary);\n\n\t\tif (err) {\n\t\t\t/* This will do another video binary lookup later for YUV_LINE format*/\n\t\t\tif (video_vf_info)\n\t\t\t\tneed_vf_pp = true;\n\t\t\telse\n\t\t\t\treturn err;\n\t\t} else if (video_vf_info) {\n\t\t\t/*\n\t\t\t * The first video binary lookup is successful, but we\n\t\t\t * may still need vf_pp binary based on additional check\n\t\t\t */\n\t\t\tnum_output_pins = mycs->video_binary.info->num_output_pins;\n\t\t\tvf_ds_log2 = mycs->video_binary.vf_downscale_log2;\n\n\t\t\t/*\n\t\t\t * If the binary has dual output pins, we need vf_pp\n\t\t\t * if the resolution is different.\n\t\t\t */\n\t\t\tneed_vf_pp |= ((num_output_pins == 2) && vf_res_different_than_output);\n\n\t\t\t/*\n\t\t\t * If the binary has single output pin, we need vf_pp\n\t\t\t * if additional scaling is needed for vf\n\t\t\t */\n\t\t\tneed_vf_pp |= ((num_output_pins == 1) &&\n\t\t\t\t       ((video_vf_info->res.width << vf_ds_log2 != pipe_out_info->res.width) ||\n\t\t\t\t\t(video_vf_info->res.height << vf_ds_log2 != pipe_out_info->res.height)));\n\t\t}\n\n\t\tif (need_vf_pp) {\n\t\t\t/* save the current vf_info format for restoration later */\n\t\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,\n\t\t\t\t\t    \"load_video_binaries() need_vf_pp; find video binary with YUV_LINE again\\n\");\n\n\t\t\tvf_info_format = video_vf_info->format;\n\n\t\t\tif (!pipe->config.enable_vfpp_bci)\n\t\t\t\tia_css_frame_info_set_format(video_vf_info,\n\t\t\t\t\t\t\t     IA_CSS_FRAME_FORMAT_YUV_LINE);\n\n\t\t\tia_css_binary_destroy_isp_parameters(&mycs->video_binary);\n\n\t\t\terr = ia_css_binary_find(&video_descr,\n\t\t\t\t\t\t &mycs->video_binary);\n\n\t\t\t/* restore original vf_info format */\n\t\t\tia_css_frame_info_set_format(video_vf_info,\n\t\t\t\t\t\t     vf_info_format);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\t}\n\n\t/*\n\t * If a video binary does not use a ref_frame, we set the frame delay\n\t * to 0. This is the case for the 1-stage low-power video binary.\n\t */\n\tif (!mycs->video_binary.info->sp.enable.ref_frame)\n\t\tpipe->dvs_frame_delay = 0;\n\n\t/*\n\t * The delay latency determines the number of invalid frames after\n\t * a stream is started.\n\t */\n\tpipe->num_invalid_frames = pipe->dvs_frame_delay;\n\tpipe->info.num_invalid_frames = pipe->num_invalid_frames;\n\n\t/*\n\t * Viewfinder frames also decrement num_invalid_frames. If the pipe\n\t * outputs a viewfinder output, then we need double the number of\n\t * invalid frames\n\t */\n\tif (video_vf_info)\n\t\tpipe->num_invalid_frames *= 2;\n\n\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,\n\t\t\t    \"load_video_binaries() num_invalid_frames=%d dvs_frame_delay=%d\\n\",\n\t\t\t    pipe->num_invalid_frames, pipe->dvs_frame_delay);\n\n\t/* pqiao TODO: temp hack for PO, should be removed after offline YUVPP is enabled */\n#if !defined(ISP2401)\n\t/* Copy */\n\tif (!online && !continuous) {\n\t\t/*\n\t\t * TODO: what exactly needs doing, prepend the copy binary to\n\t\t *\t video base this only on !online?\n\t\t */\n\t\terr = load_copy_binary(pipe,\n\t\t\t\t       &mycs->copy_binary,\n\t\t\t\t       &mycs->video_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n#else\n\t(void)continuous;\n#endif\n\n\tif (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0] && need_vf_pp) {\n\t\tstruct ia_css_binary_descr vf_pp_descr;\n\n\t\tif (mycs->video_binary.vf_frame_info.format\n\t\t    == IA_CSS_FRAME_FORMAT_YUV_LINE) {\n\t\t\tia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr,\n\t\t\t\t\t\t\t&mycs->video_binary.vf_frame_info,\n\t\t\t\t\t\t\tpipe_vf_out_info);\n\t\t} else {\n\t\t\t/*\n\t\t\t * output from main binary is not yuv line. currently\n\t\t\t * this is possible only when bci is enabled on vfpp\n\t\t\t * output\n\t\t\t */\n\t\t\tassert(pipe->config.enable_vfpp_bci);\n\t\t\tia_css_pipe_get_yuvscaler_binarydesc(pipe, &vf_pp_descr,\n\t\t\t\t\t\t\t     &mycs->video_binary.vf_frame_info,\n\t\t\t\t\t\t\t     pipe_vf_out_info, NULL, NULL);\n\t\t}\n\n\t\terr = ia_css_binary_find(&vf_pp_descr,\n\t\t\t\t\t &mycs->vf_pp_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\terr = allocate_delay_frames(pipe);\n\n\tif (err)\n\t\treturn err;\n\n\tif (mycs->video_binary.info->sp.enable.block_output) {\n\t\ttnr_info = mycs->video_binary.out_frame_info[0];\n\n\t\t/* Make tnr reference buffers output block height align */\n\t\ttnr_info.res.height = CEIL_MUL(tnr_info.res.height,\n\t\t\t\t\t       mycs->video_binary.info->sp.block.output_block_height);\n\t} else {\n\t\ttnr_info = mycs->video_binary.internal_frame_info;\n\t}\n\ttnr_info.format = IA_CSS_FRAME_FORMAT_YUV_LINE;\n\ttnr_info.raw_bit_depth = SH_CSS_TNR_BIT_DEPTH;\n\n\tfor (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) {\n\t\tif (mycs->tnr_frames[i]) {\n\t\t\tia_css_frame_free(mycs->tnr_frames[i]);\n\t\t\tmycs->tnr_frames[i] = NULL;\n\t\t}\n\t\terr = ia_css_frame_allocate_from_info(\n\t\t\t  &mycs->tnr_frames[i],\n\t\t\t  &tnr_info);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\tIA_CSS_LEAVE_PRIVATE(\"\");\n\treturn 0;\n}",
        "static int smart_ant_init(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = NULL;\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };": "static int smart_ant_init(struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = NULL;\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };\n\tint rc;\n\tu16 data = 0;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\t/*  Write magic word to enable pdr reg write               */\n\trc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\t/* init smart antenna */\n\trc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (ext_attr->smart_ant_inverted) {\n\t\trc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t} else {\n\t\trc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\t/* config SMA_TX pin to smart antenna mode */\n\trc = ctrl_set_uio_cfg(demod, &uio_cfg);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/*  Write magic word to disable pdr reg write               */\n\trc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static bool rcu_accelerate_cbs(struct rcu_node *rnp, struct rcu_data *rdp)\n{\n\tunsigned long gp_seq_req;\n\tbool ret = false;\n": "static bool rcu_accelerate_cbs(struct rcu_node *rnp, struct rcu_data *rdp)\n{\n\tunsigned long gp_seq_req;\n\tbool ret = false;\n\n\trcu_lockdep_assert_cblist_protected(rdp);\n\traw_lockdep_assert_held_rcu_node(rnp);\n\n\t/* If no pending (not yet ready to invoke) callbacks, nothing to do. */\n\tif (!rcu_segcblist_pend_cbs(&rdp->cblist))\n\t\treturn false;\n\n\ttrace_rcu_segcb_stats(&rdp->cblist, TPS(\"SegCbPreAcc\"));\n\n\t/*\n\t * Callbacks are often registered with incomplete grace-period\n\t * information.  Something about the fact that getting exact\n\t * information requires acquiring a global lock...  RCU therefore\n\t * makes a conservative estimate of the grace period number at which\n\t * a given callback will become ready to invoke.\tThe following\n\t * code checks this estimate and improves it when possible, thus\n\t * accelerating callback invocation to an earlier grace-period\n\t * number.\n\t */\n\tgp_seq_req = rcu_seq_snap(&rcu_state.gp_seq);\n\tif (rcu_segcblist_accelerate(&rdp->cblist, gp_seq_req))\n\t\tret = rcu_start_this_gp(rnp, rdp, gp_seq_req);\n\n\t/* Trace depending on how much we were able to accelerate. */\n\tif (rcu_segcblist_restempty(&rdp->cblist, RCU_WAIT_TAIL))\n\t\ttrace_rcu_grace_period(rcu_state.name, gp_seq_req, TPS(\"AccWaitCB\"));\n\telse\n\t\ttrace_rcu_grace_period(rcu_state.name, gp_seq_req, TPS(\"AccReadyCB\"));\n\n\ttrace_rcu_segcb_stats(&rdp->cblist, TPS(\"SegCbPostAcc\"));\n\n\treturn ret;\n}",
        "static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd)\n{\n\t/*\n\t * The ISP2401 new input system CSI2+ receiver has several\n\t * parameters affecting the receiver timings. These depend": "static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd)\n{\n\t/*\n\t * The ISP2401 new input system CSI2+ receiver has several\n\t * parameters affecting the receiver timings. These depend\n\t * on the MIPI bus frequency F in Hz (sensor transmitter rate)\n\t * as follows:\n\t *\tregister value = (A/1e9 + B * UI) / COUNT_ACC\n\t * where\n\t *\tUI = 1 / (2 * F) in seconds\n\t *\tCOUNT_ACC = counter accuracy in seconds\n\t *\tFor ANN and CHV, COUNT_ACC = 0.0625 ns\n\t *\tFor BXT,  COUNT_ACC = 0.125 ns\n\t * A and B are coefficients from the table below,\n\t * depending whether the register minimum or maximum value is\n\t * calculated.\n\t *\t\t\t\t       Minimum     Maximum\n\t * Clock lane\t\t\t       A     B     A     B\n\t * reg_rx_csi_dly_cnt_termen_clane     0     0    38     0\n\t * reg_rx_csi_dly_cnt_settle_clane    95    -8   300   -16\n\t * Data lanes\n\t * reg_rx_csi_dly_cnt_termen_dlane0    0     0    35     4\n\t * reg_rx_csi_dly_cnt_settle_dlane0   85    -2   145    -6\n\t * reg_rx_csi_dly_cnt_termen_dlane1    0     0    35     4\n\t * reg_rx_csi_dly_cnt_settle_dlane1   85    -2   145    -6\n\t * reg_rx_csi_dly_cnt_termen_dlane2    0     0    35     4\n\t * reg_rx_csi_dly_cnt_settle_dlane2   85    -2   145    -6\n\t * reg_rx_csi_dly_cnt_termen_dlane3    0     0    35     4\n\t * reg_rx_csi_dly_cnt_settle_dlane3   85    -2   145    -6\n\t *\n\t * We use the minimum values in the calculations below.\n\t */\n\tstatic const short int coeff_clk_termen[] = { 0, 0 };\n\tstatic const short int coeff_clk_settle[] = { 95, -8 };\n\tstatic const short int coeff_dat_termen[] = { 0, 0 };\n\tstatic const short int coeff_dat_settle[] = { 85, -2 };\n\tstatic const int TERMEN_DEFAULT\t\t  = 0 * 0;\n\tstatic const int SETTLE_DEFAULT\t\t  = 0x480;\n\n\tstatic const hrt_address csi2_port_base[] = {\n\t\t[ATOMISP_CAMERA_PORT_PRIMARY]     = CSI2_PORT_A_BASE,\n\t\t[ATOMISP_CAMERA_PORT_SECONDARY]   = CSI2_PORT_B_BASE,\n\t\t[ATOMISP_CAMERA_PORT_TERTIARY]    = CSI2_PORT_C_BASE,\n\t};\n\t/* Number of lanes on each port, excluding clock lane */\n\tstatic const unsigned char csi2_port_lanes[] = {\n\t\t[ATOMISP_CAMERA_PORT_PRIMARY]     = 4,\n\t\t[ATOMISP_CAMERA_PORT_SECONDARY]   = 2,\n\t\t[ATOMISP_CAMERA_PORT_TERTIARY]    = 2,\n\t};\n\tstatic const hrt_address csi2_lane_base[] = {\n\t\tCSI2_LANE_CL_BASE,\n\t\tCSI2_LANE_D0_BASE,\n\t\tCSI2_LANE_D1_BASE,\n\t\tCSI2_LANE_D2_BASE,\n\t\tCSI2_LANE_D3_BASE,\n\t};\n\n\tint clk_termen;\n\tint clk_settle;\n\tint dat_termen;\n\tint dat_settle;\n\n\tstruct v4l2_control ctrl;\n\tstruct atomisp_device *isp = asd->isp;\n\tstruct camera_mipi_info *mipi_info;\n\tint mipi_freq = 0;\n\tenum atomisp_camera_port port;\n\n\tint n;\n\n\tmipi_info = atomisp_to_sensor_mipi_info(\n\t\t\tisp->inputs[asd->input_curr].camera);\n\tport = mipi_info->port;\n\n\tctrl.id = V4L2_CID_LINK_FREQ;\n\tif (v4l2_g_ctrl\n\t    (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0)\n\t\tmipi_freq = ctrl.value;\n\n\tclk_termen = atomisp_csi2_configure_calc(coeff_clk_termen, mipi_freq,\n\t\t\t\t\t\t TERMEN_DEFAULT);\n\tclk_settle = atomisp_csi2_configure_calc(coeff_clk_settle, mipi_freq,\n\t\t\t\t\t\t SETTLE_DEFAULT);\n\tdat_termen = atomisp_csi2_configure_calc(coeff_dat_termen, mipi_freq,\n\t\t\t\t\t\t TERMEN_DEFAULT);\n\tdat_settle = atomisp_csi2_configure_calc(coeff_dat_settle, mipi_freq,\n\t\t\t\t\t\t SETTLE_DEFAULT);\n\n\tfor (n = 0; n < csi2_port_lanes[port] + 1; n++) {\n\t\thrt_address base = csi2_port_base[port] + csi2_lane_base[n];\n\n\t\tatomisp_css2_hw_store_32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN,\n\t\t\t\t\t n == 0 ? clk_termen : dat_termen);\n\t\tatomisp_css2_hw_store_32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE,\n\t\t\t\t\t n == 0 ? clk_settle : dat_settle);\n\t}\n}",
        "static void alc285_hp_init(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\thda_nid_t hp_pin = alc_get_hp_pin(spec);\n\tint i, val;": "static void alc285_hp_init(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\thda_nid_t hp_pin = alc_get_hp_pin(spec);\n\tint i, val;\n\tint coef38, coef0d, coef36;\n\n\talc_update_coef_idx(codec, 0x4a, 1<<15, 1<<15); /* Reset HP JD */\n\tcoef38 = alc_read_coef_idx(codec, 0x38); /* Amp control */\n\tcoef0d = alc_read_coef_idx(codec, 0x0d); /* Digital Misc control */\n\tcoef36 = alc_read_coef_idx(codec, 0x36); /* Passthrough Control */\n\talc_update_coef_idx(codec, 0x38, 1<<4, 0x0);\n\talc_update_coef_idx(codec, 0x0d, 0x110, 0x0);\n\n\talc_update_coef_idx(codec, 0x67, 0xf000, 0x3000);\n\n\tif (hp_pin)\n\t\tsnd_hda_codec_write(codec, hp_pin, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);\n\n\tmsleep(130);\n\talc_update_coef_idx(codec, 0x36, 1<<14, 1<<14);\n\talc_update_coef_idx(codec, 0x36, 1<<13, 0x0);\n\n\tif (hp_pin)\n\t\tsnd_hda_codec_write(codec, hp_pin, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0);\n\tmsleep(10);\n\talc_write_coef_idx(codec, 0x67, 0x0); /* Set HP depop to manual mode */\n\talc_write_coefex_idx(codec, 0x58, 0x00, 0x7880);\n\talc_write_coefex_idx(codec, 0x58, 0x0f, 0xf049);\n\talc_update_coefex_idx(codec, 0x58, 0x03, 0x00f0, 0x00c0);\n\n\talc_write_coefex_idx(codec, 0x58, 0x00, 0xf888); /* HP depop procedure start */\n\tval = alc_read_coefex_idx(codec, 0x58, 0x00);\n\tfor (i = 0; i < 20 && val & 0x8000; i++) {\n\t\tmsleep(50);\n\t\tval = alc_read_coefex_idx(codec, 0x58, 0x00);\n\t} /* Wait for depop procedure finish  */\n\n\talc_write_coefex_idx(codec, 0x58, 0x00, val); /* write back the result */\n\talc_update_coef_idx(codec, 0x38, 1<<4, coef38);\n\talc_update_coef_idx(codec, 0x0d, 0x110, coef0d);\n\talc_update_coef_idx(codec, 0x36, 3<<13, coef36);\n\n\tmsleep(50);\n\talc_update_coef_idx(codec, 0x4a, 1<<15, 0);\n}",
        "static int kxcjk1013_chip_init(struct kxcjk1013_data *data)\n{\n\tint ret;\n\n#ifdef CONFIG_ACPI": "static int kxcjk1013_chip_init(struct kxcjk1013_data *data)\n{\n\tint ret;\n\n#ifdef CONFIG_ACPI\n\tif (data->acpi_type == ACPI_KIOX010A) {\n\t\t/* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */\n\t\tkiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE);\n\t}\n#endif\n\n\tret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);\n\tif (ret < 0) {\n\t\tdev_err(&data->client->dev, \"Error reading who_am_i\\n\");\n\t\treturn ret;\n\t}\n\n\tdev_dbg(&data->client->dev, \"KXCJK1013 Chip Id %x\\n\", ret);\n\n\tret = kxcjk1013_set_mode(data, STANDBY);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);\n\tif (ret < 0) {\n\t\tdev_err(&data->client->dev, \"Error reading reg_ctrl1\\n\");\n\t\treturn ret;\n\t}\n\n\t/* Set 12 bit mode */\n\tret |= KXCJK1013_REG_CTRL1_BIT_RES;\n\n\tret = i2c_smbus_write_byte_data(data->client, data->regs->ctrl1, ret);\n\tif (ret < 0) {\n\t\tdev_err(&data->client->dev, \"Error reading reg_ctrl\\n\");\n\t\treturn ret;\n\t}\n\n\t/* Setting range to 4G */\n\tret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tret = i2c_smbus_read_byte_data(data->client, data->regs->data_ctrl);\n\tif (ret < 0) {\n\t\tdev_err(&data->client->dev, \"Error reading reg_data_ctrl\\n\");\n\t\treturn ret;\n\t}\n\n\tdata->odr_bits = ret;\n\n\t/* Set up INT polarity */\n\tret = i2c_smbus_read_byte_data(data->client, data->regs->int_ctrl1);\n\tif (ret < 0) {\n\t\tdev_err(&data->client->dev, \"Error reading reg_int_ctrl1\\n\");\n\t\treturn ret;\n\t}\n\n\tif (data->active_high_intr)\n\t\tret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA;\n\telse\n\t\tret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA;\n\n\tret = i2c_smbus_write_byte_data(data->client, data->regs->int_ctrl1, ret);\n\tif (ret < 0) {\n\t\tdev_err(&data->client->dev, \"Error writing reg_int_ctrl1\\n\");\n\t\treturn ret;\n\t}\n\n\t/* On KX023, route all used interrupts to INT1 for now */\n\tif (data->chipset == KX0231025 && data->client->irq > 0) {\n\t\tret = i2c_smbus_write_byte_data(data->client, KX023_REG_INC4,\n\t\t\t\t\t\tKX023_REG_INC4_DRDY1 |\n\t\t\t\t\t\tKX023_REG_INC4_WUFI1);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&data->client->dev, \"Error writing reg_inc4\\n\");\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tret = kxcjk1013_set_mode(data, OPERATION);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tdata->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;\n\n\treturn 0;\n}",
        "static void test_tcp_clear_dtime(struct test_tc_dtime *skel)\n{\n\tint i, t = TCP_IP6_CLEAR_DTIME;\n\t__u32 *dtimes = skel->bss->dtimes[t];\n\t__u32 *errs = skel->bss->errs[t];": "static void test_tcp_clear_dtime(struct test_tc_dtime *skel)\n{\n\tint i, t = TCP_IP6_CLEAR_DTIME;\n\t__u32 *dtimes = skel->bss->dtimes[t];\n\t__u32 *errs = skel->bss->errs[t];\n\n\tskel->bss->test = t;\n\ttest_inet_dtime(AF_INET6, SOCK_STREAM, IP6_DST, 0);\n\n\tASSERT_EQ(dtimes[INGRESS_FWDNS_P100], 0,\n\t\t  dtime_cnt_str(t, INGRESS_FWDNS_P100));\n\tASSERT_EQ(dtimes[INGRESS_FWDNS_P101], 0,\n\t\t  dtime_cnt_str(t, INGRESS_FWDNS_P101));\n\tASSERT_GT(dtimes[EGRESS_FWDNS_P100], 0,\n\t\t  dtime_cnt_str(t, EGRESS_FWDNS_P100));\n\tASSERT_EQ(dtimes[EGRESS_FWDNS_P101], 0,\n\t\t  dtime_cnt_str(t, EGRESS_FWDNS_P101));\n\tASSERT_GT(dtimes[EGRESS_ENDHOST], 0,\n\t\t  dtime_cnt_str(t, EGRESS_ENDHOST));\n\tASSERT_GT(dtimes[INGRESS_ENDHOST], 0,\n\t\t  dtime_cnt_str(t, INGRESS_ENDHOST));\n\n\tfor (i = INGRESS_FWDNS_P100; i < __MAX_CNT; i++)\n\t\tASSERT_EQ(errs[i], 0, dtime_err_str(t, i));\n}",
        "static int check_stripe_cache(struct mddev *mddev)\n{\n\t/* Can only proceed if there are plenty of stripe_heads.\n\t * We need a minimum of one full stripe,, and for sensible progress\n\t * it is best to have about 4 times that.": "static int check_stripe_cache(struct mddev *mddev)\n{\n\t/* Can only proceed if there are plenty of stripe_heads.\n\t * We need a minimum of one full stripe,, and for sensible progress\n\t * it is best to have about 4 times that.\n\t * If we require 4 times, then the default 256 4K stripe_heads will\n\t * allow for chunk sizes up to 256K, which is probably OK.\n\t * If the chunk size is greater, user-space should request more\n\t * stripe_heads first.\n\t */\n\tstruct r5conf *conf = mddev->private;\n\tif (((mddev->chunk_sectors << 9) / RAID5_STRIPE_SIZE(conf)) * 4\n\t    > conf->min_nr_stripes ||\n\t    ((mddev->new_chunk_sectors << 9) / RAID5_STRIPE_SIZE(conf)) * 4\n\t    > conf->min_nr_stripes) {\n\t\tpr_warn(\"md/raid:%s: reshape: not enough stripes.  Needed %lu\\n\",\n\t\t\tmdname(mddev),\n\t\t\t((max(mddev->chunk_sectors, mddev->new_chunk_sectors) << 9)\n\t\t\t / RAID5_STRIPE_SIZE(conf))*4);\n\t\treturn 0;\n\t}\n\treturn 1;\n}",
        "static struct dst_entry *xfrm_dst_check(struct dst_entry *dst, u32 cookie)\n{\n\t/* Code (such as __xfrm4_bundle_create()) sets dst->obsolete\n\t * to DST_OBSOLETE_FORCE_CHK to force all XFRM destinations to\n\t * get validated by dst_ops->check on every use.  We do this": "static struct dst_entry *xfrm_dst_check(struct dst_entry *dst, u32 cookie)\n{\n\t/* Code (such as __xfrm4_bundle_create()) sets dst->obsolete\n\t * to DST_OBSOLETE_FORCE_CHK to force all XFRM destinations to\n\t * get validated by dst_ops->check on every use.  We do this\n\t * because when a normal route referenced by an XFRM dst is\n\t * obsoleted we do not go looking around for all parent\n\t * referencing XFRM dsts so that we can invalidate them.  It\n\t * is just too much work.  Instead we make the checks here on\n\t * every use.  For example:\n\t *\n\t *\tXFRM dst A --> IPv4 dst X\n\t *\n\t * X is the \"xdst->route\" of A (X is also the \"dst->path\" of A\n\t * in this example).  If X is marked obsolete, \"A\" will not\n\t * notice.  That's what we are validating here via the\n\t * stale_bundle() check.\n\t *\n\t * When a dst is removed from the fib tree, DST_OBSOLETE_DEAD will\n\t * be marked on it.\n\t * This will force stale_bundle() to fail on any xdst bundle with\n\t * this dst linked in it.\n\t */\n\tif (dst->obsolete < 0 && !stale_bundle(dst))\n\t\treturn dst;\n\n\treturn NULL;\n}",
        "static void niu_init_rx_bmac(struct niu *np)\n{\n\tstruct niu_parent *parent = np->parent;\n\tstruct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];\n\tint first_rdc_table = tp->first_table_num;": "static void niu_init_rx_bmac(struct niu *np)\n{\n\tstruct niu_parent *parent = np->parent;\n\tstruct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];\n\tint first_rdc_table = tp->first_table_num;\n\tunsigned long i;\n\tu64 val;\n\n\tnw64_mac(BMAC_ADD_FILT0, 0);\n\tnw64_mac(BMAC_ADD_FILT1, 0);\n\tnw64_mac(BMAC_ADD_FILT2, 0);\n\tnw64_mac(BMAC_ADD_FILT12_MASK, 0);\n\tnw64_mac(BMAC_ADD_FILT00_MASK, 0);\n\tfor (i = 0; i < MAC_NUM_HASH; i++)\n\t\tnw64_mac(BMAC_HASH_TBL(i), 0);\n\tniu_set_primary_mac_rdc_table(np, first_rdc_table, 1);\n\tniu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);\n\tnw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);\n\n\tval = nr64_mac(BRXMAC_CONFIG);\n\tval &= ~(BRXMAC_CONFIG_ENABLE |\n\t\t BRXMAC_CONFIG_STRIP_PAD |\n\t\t BRXMAC_CONFIG_STRIP_FCS |\n\t\t BRXMAC_CONFIG_PROMISC |\n\t\t BRXMAC_CONFIG_PROMISC_GRP |\n\t\t BRXMAC_CONFIG_ADDR_FILT_EN |\n\t\t BRXMAC_CONFIG_DISCARD_DIS);\n\tval |= (BRXMAC_CONFIG_HASH_FILT_EN);\n\tnw64_mac(BRXMAC_CONFIG, val);\n\n\tval = nr64_mac(BMAC_ADDR_CMPEN);\n\tval |= BMAC_ADDR_CMPEN_EN0;\n\tnw64_mac(BMAC_ADDR_CMPEN, val);\n}",
        "static int dbBackSplit(dmtree_t * tp, int leafno)\n{\n\tint budsz, bud, w, bsz, size;\n\tint cursz;\n\ts8 *leaf = tp->dmt_stree + le32_to_cpu(tp->dmt_leafidx);": "static int dbBackSplit(dmtree_t * tp, int leafno)\n{\n\tint budsz, bud, w, bsz, size;\n\tint cursz;\n\ts8 *leaf = tp->dmt_stree + le32_to_cpu(tp->dmt_leafidx);\n\n\t/* leaf should be part (not first part) of a binary\n\t * buddy system.\n\t */\n\tassert(leaf[leafno] == NOFREE);\n\n\t/* the back split is accomplished by iteratively finding the leaf\n\t * that starts the buddy system that contains the specified leaf and\n\t * splitting that system in two.  this iteration continues until\n\t * the specified leaf becomes the start of a buddy system.\n\t *\n\t * determine maximum possible l2 size for the specified leaf.\n\t */\n\tsize =\n\t    LITOL2BSZ(leafno, le32_to_cpu(tp->dmt_l2nleafs),\n\t\t      tp->dmt_budmin);\n\n\t/* determine the number of leaves covered by this size.  this\n\t * is the buddy size that we will start with as we search for\n\t * the buddy system that contains the specified leaf.\n\t */\n\tbudsz = BUDSIZE(size, tp->dmt_budmin);\n\n\t/* back split.\n\t */\n\twhile (leaf[leafno] == NOFREE) {\n\t\t/* find the leftmost buddy leaf.\n\t\t */\n\t\tfor (w = leafno, bsz = budsz;; bsz <<= 1,\n\t\t     w = (w < bud) ? w : bud) {\n\t\t\tif (bsz >= le32_to_cpu(tp->dmt_nleafs)) {\n\t\t\t\tjfs_err(\"JFS: block map error in dbBackSplit\");\n\t\t\t\treturn -EIO;\n\t\t\t}\n\n\t\t\t/* determine the buddy.\n\t\t\t */\n\t\t\tbud = w ^ bsz;\n\n\t\t\t/* check if this buddy is the start of the system.\n\t\t\t */\n\t\t\tif (leaf[bud] != NOFREE) {\n\t\t\t\t/* split the leaf at the start of the\n\t\t\t\t * system in two.\n\t\t\t\t */\n\t\t\t\tcursz = leaf[bud] - 1;\n\t\t\t\tdbSplit(tp, bud, cursz, cursz);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (leaf[leafno] != size) {\n\t\tjfs_err(\"JFS: wrong leaf value in dbBackSplit\");\n\t\treturn -EIO;\n\t}\n\treturn 0;\n}",
        "static void zxr_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n\tchipio_set_stream_control(codec, 0x14, 0);": "static void zxr_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n\tchipio_set_stream_control(codec, 0x14, 0);\n\tchipio_set_stream_control(codec, 0x0C, 0);\n\n\tchipio_set_conn_rate(codec, 0x41, SR_192_000);\n\tchipio_set_conn_rate(codec, 0x91, SR_192_000);\n\n\tchipio_write(codec, 0x18a020, 0x00000083);\n\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);\n\tsnd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);\n\n\tca0132_clear_unsolicited(codec);\n\tsbz_set_pin_ctl_default(codec);\n\tsnd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);\n\n\tca0113_mmio_gpio_set(codec, 5, false);\n\tca0113_mmio_gpio_set(codec, 2, false);\n\tca0113_mmio_gpio_set(codec, 3, false);\n\tca0113_mmio_gpio_set(codec, 0, false);\n\tca0113_mmio_gpio_set(codec, 4, true);\n\tca0113_mmio_gpio_set(codec, 0, true);\n\tca0113_mmio_gpio_set(codec, 5, true);\n\tca0113_mmio_gpio_set(codec, 2, false);\n\tca0113_mmio_gpio_set(codec, 3, false);\n}",
        "static void test_v3_last_bit_single_rdist(void)\n{\n\tuint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 };\n\tstruct vm_gic v;\n\tuint64_t addr;": "static void test_v3_last_bit_single_rdist(void)\n{\n\tuint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 };\n\tstruct vm_gic v;\n\tuint64_t addr;\n\tuint32_t val;\n\tint ret;\n\n\tv.vm = vm_create_default_with_vcpus(6, 0, 0, guest_code, vcpuids);\n\n\tv.gic_fd = kvm_create_device(v.vm, KVM_DEV_TYPE_ARM_VGIC_V3, false);\n\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,\n\t\t\t  KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);\n\n\taddr = 0x10000;\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST, &addr, true);\n\n\tret = access_v3_redist_reg(v.gic_fd, 0, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x000, \"read typer of rdist #0\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 3, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x300, \"read typer of rdist #1\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 5, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x500, \"read typer of rdist #2\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 1, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x100, \"read typer of rdist #3\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 2, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x210, \"read typer of rdist #3\");\n\n\tvm_gic_destroy(&v);\n}",
        "static int intel_link_power_up(struct sdw_intel *sdw)\n{\n\tunsigned int link_id = sdw->instance;\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tu32 *shim_mask = sdw->link_res->shim_mask;": "static int intel_link_power_up(struct sdw_intel *sdw)\n{\n\tunsigned int link_id = sdw->instance;\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tu32 *shim_mask = sdw->link_res->shim_mask;\n\tstruct sdw_bus *bus = &sdw->cdns.bus;\n\tstruct sdw_master_prop *prop = &bus->prop;\n\tu32 spa_mask, cpa_mask;\n\tu32 link_control;\n\tint ret = 0;\n\tu32 syncprd;\n\tu32 sync_reg;\n\n\tmutex_lock(sdw->link_res->shim_lock);\n\n\t/*\n\t * The hardware relies on an internal counter, typically 4kHz,\n\t * to generate the SoundWire SSP - which defines a 'safe'\n\t * synchronization point between commands and audio transport\n\t * and allows for multi link synchronization. The SYNCPRD value\n\t * is only dependent on the oscillator clock provided to\n\t * the IP, so adjust based on _DSD properties reported in DSDT\n\t * tables. The values reported are based on either 24MHz\n\t * (CNL/CML) or 38.4 MHz (ICL/TGL+).\n\t */\n\tif (prop->mclk_freq % 6000000)\n\t\tsyncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;\n\telse\n\t\tsyncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;\n\n\tif (!*shim_mask) {\n\t\tdev_dbg(sdw->cdns.dev, \"%s: powering up all links\\n\", __func__);\n\n\t\t/* we first need to program the SyncPRD/CPU registers */\n\t\tdev_dbg(sdw->cdns.dev,\n\t\t\t\"%s: first link up, programming SYNCPRD\\n\", __func__);\n\n\t\t/* set SyncPRD period */\n\t\tsync_reg = intel_readl(shim, SDW_SHIM_SYNC);\n\t\tu32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);\n\n\t\t/* Set SyncCPU bit */\n\t\tsync_reg |= SDW_SHIM_SYNC_SYNCCPU;\n\t\tintel_writel(shim, SDW_SHIM_SYNC, sync_reg);\n\n\t\t/* Link power up sequence */\n\t\tlink_control = intel_readl(shim, SDW_SHIM_LCTL);\n\n\t\t/* only power-up enabled links */\n\t\tspa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);\n\t\tcpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);\n\n\t\tlink_control |=  spa_mask;\n\n\t\tret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);\n\t\tif (ret < 0) {\n\t\t\tdev_err(sdw->cdns.dev, \"Failed to power up link: %d\\n\", ret);\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* SyncCPU will change once link is active */\n\t\tret = intel_wait_bit(shim, SDW_SHIM_SYNC,\n\t\t\t\t     SDW_SHIM_SYNC_SYNCCPU, 0);\n\t\tif (ret < 0) {\n\t\t\tdev_err(sdw->cdns.dev,\n\t\t\t\t\"Failed to set SHIM_SYNC: %d\\n\", ret);\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t*shim_mask |= BIT(link_id);\n\n\tsdw->cdns.link_up = true;\nout:\n\tmutex_unlock(sdw->link_res->shim_lock);\n\n\treturn ret;\n}",
        "static int tcpm_pd_build_request(struct tcpm_port *port, u32 *rdo)\n{\n\tunsigned int mv, ma, mw, flags;\n\tunsigned int max_ma, max_mw;\n\tenum pd_pdo_type type;": "static int tcpm_pd_build_request(struct tcpm_port *port, u32 *rdo)\n{\n\tunsigned int mv, ma, mw, flags;\n\tunsigned int max_ma, max_mw;\n\tenum pd_pdo_type type;\n\tu32 pdo, matching_snk_pdo;\n\tint src_pdo_index = 0;\n\tint snk_pdo_index = 0;\n\tint ret;\n\n\tret = tcpm_pd_select_pdo(port, &snk_pdo_index, &src_pdo_index);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tpdo = port->source_caps[src_pdo_index];\n\tmatching_snk_pdo = port->snk_pdo[snk_pdo_index];\n\ttype = pdo_type(pdo);\n\n\tswitch (type) {\n\tcase PDO_TYPE_FIXED:\n\t\tmv = pdo_fixed_voltage(pdo);\n\t\tbreak;\n\tcase PDO_TYPE_BATT:\n\tcase PDO_TYPE_VAR:\n\t\tmv = pdo_min_voltage(pdo);\n\t\tbreak;\n\tdefault:\n\t\ttcpm_log(port, \"Invalid PDO selected!\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Select maximum available current within the sink pdo's limit */\n\tif (type == PDO_TYPE_BATT) {\n\t\tmw = min_power(pdo, matching_snk_pdo);\n\t\tma = 1000 * mw / mv;\n\t} else {\n\t\tma = min_current(pdo, matching_snk_pdo);\n\t\tmw = ma * mv / 1000;\n\t}\n\n\tflags = RDO_USB_COMM | RDO_NO_SUSPEND;\n\n\t/* Set mismatch bit if offered power is less than operating power */\n\tmax_ma = ma;\n\tmax_mw = mw;\n\tif (mw < port->operating_snk_mw) {\n\t\tflags |= RDO_CAP_MISMATCH;\n\t\tif (type == PDO_TYPE_BATT &&\n\t\t    (pdo_max_power(matching_snk_pdo) > pdo_max_power(pdo)))\n\t\t\tmax_mw = pdo_max_power(matching_snk_pdo);\n\t\telse if (pdo_max_current(matching_snk_pdo) >\n\t\t\t pdo_max_current(pdo))\n\t\t\tmax_ma = pdo_max_current(matching_snk_pdo);\n\t}\n\n\ttcpm_log(port, \"cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d\",\n\t\t port->cc_req, port->cc1, port->cc2, port->vbus_source,\n\t\t port->vconn_role == TYPEC_SOURCE ? \"source\" : \"sink\",\n\t\t port->polarity);\n\n\tif (type == PDO_TYPE_BATT) {\n\t\t*rdo = RDO_BATT(src_pdo_index + 1, mw, max_mw, flags);\n\n\t\ttcpm_log(port, \"Requesting PDO %d: %u mV, %u mW%s\",\n\t\t\t src_pdo_index, mv, mw,\n\t\t\t flags & RDO_CAP_MISMATCH ? \" [mismatch]\" : \"\");\n\t} else {\n\t\t*rdo = RDO_FIXED(src_pdo_index + 1, ma, max_ma, flags);\n\n\t\ttcpm_log(port, \"Requesting PDO %d: %u mV, %u mA%s\",\n\t\t\t src_pdo_index, mv, ma,\n\t\t\t flags & RDO_CAP_MISMATCH ? \" [mismatch]\" : \"\");\n\t}\n\n\tport->req_current_limit = ma;\n\tport->req_supply_voltage = mv;\n\n\treturn 0;\n}",
        "static int ov5640_get_sysclk(struct ov5640_dev *sensor)\n{\n\t /* calculate sysclk */\n\tu32 xvclk = sensor->xclk_freq / 10000;\n\tu32 multiplier, prediv, VCO, sysdiv, pll_rdiv;": "static int ov5640_get_sysclk(struct ov5640_dev *sensor)\n{\n\t /* calculate sysclk */\n\tu32 xvclk = sensor->xclk_freq / 10000;\n\tu32 multiplier, prediv, VCO, sysdiv, pll_rdiv;\n\tu32 sclk_rdiv_map[] = {1, 2, 4, 8};\n\tu32 bit_div2x = 1, sclk_rdiv, sysclk;\n\tu8 temp1, temp2;\n\tint ret;\n\n\tret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL0, &temp1);\n\tif (ret)\n\t\treturn ret;\n\ttemp2 = temp1 & 0x0f;\n\tif (temp2 == 8 || temp2 == 10)\n\t\tbit_div2x = temp2 / 2;\n\n\tret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL1, &temp1);\n\tif (ret)\n\t\treturn ret;\n\tsysdiv = temp1 >> 4;\n\tif (sysdiv == 0)\n\t\tsysdiv = 16;\n\n\tret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL2, &temp1);\n\tif (ret)\n\t\treturn ret;\n\tmultiplier = temp1;\n\n\tret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL3, &temp1);\n\tif (ret)\n\t\treturn ret;\n\tprediv = temp1 & 0x0f;\n\tpll_rdiv = ((temp1 >> 4) & 0x01) + 1;\n\n\tret = ov5640_read_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, &temp1);\n\tif (ret)\n\t\treturn ret;\n\ttemp2 = temp1 & 0x03;\n\tsclk_rdiv = sclk_rdiv_map[temp2];\n\n\tif (!prediv || !sysdiv || !pll_rdiv || !bit_div2x)\n\t\treturn -EINVAL;\n\n\tVCO = xvclk * multiplier / prediv;\n\n\tsysclk = VCO / sysdiv / pll_rdiv * 2 / bit_div2x / sclk_rdiv;\n\n\treturn sysclk;\n}",
        "static inline u32 dw_pcie_enable_ecrc(u32 val)\n{\n\t/*\n\t * DesignWare core version 4.90A has a design issue where the 'TD'\n\t * bit in the Control register-1 of the ATU outbound region acts": "static inline u32 dw_pcie_enable_ecrc(u32 val)\n{\n\t/*\n\t * DesignWare core version 4.90A has a design issue where the 'TD'\n\t * bit in the Control register-1 of the ATU outbound region acts\n\t * like an override for the ECRC setting, i.e., the presence of TLP\n\t * Digest (ECRC) in the outgoing TLPs is solely determined by this\n\t * bit. This is contrary to the PCIe spec which says that the\n\t * enablement of the ECRC is solely determined by the AER\n\t * registers.\n\t *\n\t * Because of this, even when the ECRC is enabled through AER\n\t * registers, the transactions going through ATU won't have TLP\n\t * Digest as there is no way the PCI core AER code could program\n\t * the TD bit which is specific to the DesignWare core.\n\t *\n\t * The best way to handle this scenario is to program the TD bit\n\t * always. It affects only the traffic from root port to downstream\n\t * devices.\n\t *\n\t * At this point,\n\t * When ECRC is enabled in AER registers, everything works normally\n\t * When ECRC is NOT enabled in AER registers, then,\n\t * on Root Port:- TLP Digest (DWord size) gets appended to each packet\n\t *                even through it is not required. Since downstream\n\t *                TLPs are mostly for configuration accesses and BAR\n\t *                accesses, they are not in critical path and won't\n\t *                have much negative effect on the performance.\n\t * on End Point:- TLP Digest is received for some/all the packets coming\n\t *                from the root port. TLP Digest is ignored because,\n\t *                as per the PCIe Spec r5.0 v1.0 section 2.2.3\n\t *                \"TLP Digest Rules\", when an endpoint receives TLP\n\t *                Digest when its ECRC check functionality is disabled\n\t *                in AER registers, received TLP Digest is just ignored.\n\t * Since there is no issue or error reported either side, best way to\n\t * handle the scenario is to program TD bit by default.\n\t */\n\n\treturn val | PCIE_ATU_TD;\n}",
        "static int emc_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct tegra_emc *emc = to_tegra_emc_provider(dst->provider);\n\tunsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);\n\tunsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);": "static int emc_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct tegra_emc *emc = to_tegra_emc_provider(dst->provider);\n\tunsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);\n\tunsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);\n\tunsigned long long rate = max(avg_bw, peak_bw);\n\tunsigned int dram_data_bus_width_bytes;\n\tint err;\n\n\t/*\n\t * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data\n\t * is sampled on both clock edges.  This means that EMC clock rate\n\t * equals to the peak data-rate.\n\t */\n\tdram_data_bus_width_bytes = emc->dram_bus_width / 8;\n\tdo_div(rate, dram_data_bus_width_bytes);\n\trate = min_t(u64, rate, U32_MAX);\n\n\terr = emc_set_min_rate(emc, rate, EMC_RATE_ICC);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}",
        "static void timerlat_hist_usage(char *usage)\n{\n\tint i;\n\n\tchar *msg[] = {": "static void timerlat_hist_usage(char *usage)\n{\n\tint i;\n\n\tchar *msg[] = {\n\t\t\"\",\n\t\t\"  usage: [rtla] timerlat hist [-h] [-q] [-d s] [-D] [-n] [-a us] [-p us] [-i us] [-T us] [-s us] \\\\\",\n\t\t\"         [-t[=file]] [-e sys[:event]] [--filter <filter>] [--trigger <trigger>] [-c cpu-list] \\\\\",\n\t\t\"\t  [-P priority] [-E N] [-b N] [--no-irq] [--no-thread] [--no-header] [--no-summary] \\\\\",\n\t\t\"\t  [--no-index] [--with-zeros] [--dma-latency us]\",\n\t\t\"\",\n\t\t\"\t  -h/--help: print this menu\",\n\t\t\"\t  -a/--auto: set automatic trace mode, stopping the session if argument in us latency is hit\",\n\t\t\"\t  -p/--period us: timerlat period in us\",\n\t\t\"\t  -i/--irq us: stop trace if the irq latency is higher than the argument in us\",\n\t\t\"\t  -T/--thread us: stop trace if the thread latency is higher than the argument in us\",\n\t\t\"\t  -s/--stack us: save the stack trace at the IRQ if a thread latency is higher than the argument in us\",\n\t\t\"\t  -c/--cpus cpus: run the tracer only on the given cpus\",\n\t\t\"\t  -d/--duration time[m|h|d]: duration of the session in seconds\",\n\t\t\"\t  -D/--debug: print debug info\",\n\t\t\"\t  -t/--trace[=file]: save the stopped trace to [file|timerlat_trace.txt]\",\n\t\t\"\t  -e/--event <sys:event>: enable the <sys:event> in the trace instance, multiple -e are allowed\",\n\t\t\"\t     --filter <filter>: enable a trace event filter to the previous -e event\",\n\t\t\"\t     --trigger <trigger>: enable a trace event trigger to the previous -e event\",\n\t\t\"\t  -n/--nano: display data in nanoseconds\",\n\t\t\"\t  -b/--bucket-size N: set the histogram bucket size (default 1)\",\n\t\t\"\t  -E/--entries N: set the number of entries of the histogram (default 256)\",\n\t\t\"\t     --no-irq: ignore IRQ latencies\",\n\t\t\"\t     --no-thread: ignore thread latencies\",\n\t\t\"\t     --no-header: do not print header\",\n\t\t\"\t     --no-summary: do not print summary\",\n\t\t\"\t     --no-index: do not print index\",\n\t\t\"\t     --with-zeros: print zero only entries\",\n\t\t\"\t     --dma-latency us: set /dev/cpu_dma_latency latency <us> to reduce exit from idle latency\",\n\t\t\"\t  -P/--priority o:prio|r:prio|f:prio|d:runtime:period : set scheduling parameters\",\n\t\t\"\t\to:prio - use SCHED_OTHER with prio\",\n\t\t\"\t\tr:prio - use SCHED_RR with prio\",\n\t\t\"\t\tf:prio - use SCHED_FIFO with prio\",\n\t\t\"\t\td:runtime[us|ms|s]:period[us|ms|s] - use SCHED_DEADLINE with runtime and period\",\n\t\t\"\t\t\t\t\t\t       in nanoseconds\",\n\t\tNULL,\n\t};\n\n\tif (usage)\n\t\tfprintf(stderr, \"%s\\n\", usage);\n\n\tfprintf(stderr, \"rtla timerlat hist: a per-cpu histogram of the timer latency (version %s)\\n\",\n\t\t\tVERSION);\n\n\tfor (i = 0; msg[i]; i++)\n\t\tfprintf(stderr, \"%s\\n\", msg[i]);\n\texit(1);\n}",
        "static void overflow_size_helpers_test(struct kunit *test)\n{\n\t/* Make sure struct_size() can be used in a constant expression. */\n\tu8 ce_array[struct_size((struct __test_flex_array *)0, data, 55)];\n\tstruct __test_flex_array *obj;": "static void overflow_size_helpers_test(struct kunit *test)\n{\n\t/* Make sure struct_size() can be used in a constant expression. */\n\tu8 ce_array[struct_size((struct __test_flex_array *)0, data, 55)];\n\tstruct __test_flex_array *obj;\n\tint count = 0;\n\tint var;\n\tvolatile int unconst = 0;\n\n\t/* Verify constant expression against runtime version. */\n\tvar = 55;\n\tOPTIMIZER_HIDE_VAR(var);\n\tKUNIT_EXPECT_EQ(test, sizeof(ce_array), struct_size(obj, data, var));\n\n#define check_one_size_helper(expected, func, args...)\tdo {\t\\\n\tsize_t _r = func(args);\t\t\t\t\t\\\n\tKUNIT_EXPECT_EQ_MSG(test, _r, expected,\t\t\t\\\n\t\t\"expected \" #func \"(\" #args \") to return %zu but got %zu instead\\n\", \\\n\t\t(size_t)(expected), _r);\t\t\t\\\n\tcount++;\t\t\t\t\t\t\\\n} while (0)\n\n\tvar = 4;\n\tcheck_one_size_helper(20,\tsize_mul, var++, 5);\n\tcheck_one_size_helper(20,\tsize_mul, 4, var++);\n\tcheck_one_size_helper(0,\tsize_mul, 0, 3);\n\tcheck_one_size_helper(0,\tsize_mul, 3, 0);\n\tcheck_one_size_helper(6,\tsize_mul, 2, 3);\n\tcheck_one_size_helper(SIZE_MAX,\tsize_mul, SIZE_MAX,  1);\n\tcheck_one_size_helper(SIZE_MAX,\tsize_mul, SIZE_MAX,  3);\n\tcheck_one_size_helper(SIZE_MAX,\tsize_mul, SIZE_MAX, -3);\n\n\tvar = 4;\n\tcheck_one_size_helper(9,\tsize_add, var++, 5);\n\tcheck_one_size_helper(9,\tsize_add, 4, var++);\n\tcheck_one_size_helper(9,\tsize_add, 9, 0);\n\tcheck_one_size_helper(9,\tsize_add, 0, 9);\n\tcheck_one_size_helper(5,\tsize_add, 2, 3);\n\tcheck_one_size_helper(SIZE_MAX, size_add, SIZE_MAX,  1);\n\tcheck_one_size_helper(SIZE_MAX, size_add, SIZE_MAX,  3);\n\tcheck_one_size_helper(SIZE_MAX, size_add, SIZE_MAX, -3);\n\n\tvar = 4;\n\tcheck_one_size_helper(1,\tsize_sub, var--, 3);\n\tcheck_one_size_helper(1,\tsize_sub, 4, var--);\n\tcheck_one_size_helper(1,\tsize_sub, 3, 2);\n\tcheck_one_size_helper(9,\tsize_sub, 9, 0);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, 9, -3);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, 0, 9);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, 2, 3);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, SIZE_MAX,  0);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, SIZE_MAX, 10);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, 0,  SIZE_MAX);\n\tcheck_one_size_helper(SIZE_MAX, size_sub, 14, SIZE_MAX);\n\tcheck_one_size_helper(SIZE_MAX - 2, size_sub, SIZE_MAX - 1,  1);\n\tcheck_one_size_helper(SIZE_MAX - 4, size_sub, SIZE_MAX - 1,  3);\n\tcheck_one_size_helper(1,\t\tsize_sub, SIZE_MAX - 1, -3);\n\n\tvar = 4;\n\tcheck_one_size_helper(4 * sizeof(*obj->data),\n\t\t\t      flex_array_size, obj, data, var++);\n\tcheck_one_size_helper(5 * sizeof(*obj->data),\n\t\t\t      flex_array_size, obj, data, var++);\n\tcheck_one_size_helper(0, flex_array_size, obj, data, 0 + unconst);\n\tcheck_one_size_helper(sizeof(*obj->data),\n\t\t\t      flex_array_size, obj, data, 1 + unconst);\n\tcheck_one_size_helper(7 * sizeof(*obj->data),\n\t\t\t      flex_array_size, obj, data, 7 + unconst);\n\tcheck_one_size_helper(SIZE_MAX,\n\t\t\t      flex_array_size, obj, data, -1 + unconst);\n\tcheck_one_size_helper(SIZE_MAX,\n\t\t\t      flex_array_size, obj, data, SIZE_MAX - 4 + unconst);\n\n\tvar = 4;\n\tcheck_one_size_helper(sizeof(*obj) + (4 * sizeof(*obj->data)),\n\t\t\t      struct_size, obj, data, var++);\n\tcheck_one_size_helper(sizeof(*obj) + (5 * sizeof(*obj->data)),\n\t\t\t      struct_size, obj, data, var++);\n\tcheck_one_size_helper(sizeof(*obj), struct_size, obj, data, 0 + unconst);\n\tcheck_one_size_helper(sizeof(*obj) + sizeof(*obj->data),\n\t\t\t      struct_size, obj, data, 1 + unconst);\n\tcheck_one_size_helper(SIZE_MAX,\n\t\t\t      struct_size, obj, data, -3 + unconst);\n\tcheck_one_size_helper(SIZE_MAX,\n\t\t\t      struct_size, obj, data, SIZE_MAX - 3 + unconst);\n\n\tkunit_info(test, \"%d overflow size helper tests finished\\n\", count);\n#undef check_one_size_helper\n}",
        "static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame **dec_params)\n{\n\tconst struct v4l2_ctrl_vp9_compressed_hdr *prob_updates;\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tstruct v4l2_ctrl *ctrl;": "static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame **dec_params)\n{\n\tconst struct v4l2_ctrl_vp9_compressed_hdr *prob_updates;\n\tstruct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec;\n\tstruct v4l2_ctrl *ctrl;\n\tunsigned int fctx_idx;\n\n\t/* v4l2-specific stuff */\n\thantro_start_prepare_run(ctx);\n\n\tctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_FRAME);\n\tif (WARN_ON(!ctrl))\n\t\treturn -EINVAL;\n\t*dec_params = ctrl->p_cur.p;\n\n\tctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_COMPRESSED_HDR);\n\tif (WARN_ON(!ctrl))\n\t\treturn -EINVAL;\n\tprob_updates = ctrl->p_cur.p;\n\tvp9_ctx->cur.tx_mode = prob_updates->tx_mode;\n\n\t/*\n\t * vp9 stuff\n\t *\n\t * by this point the userspace has done all parts of 6.2 uncompressed_header()\n\t * except this fragment:\n\t * if ( FrameIsIntra || error_resilient_mode ) {\n\t *\tsetup_past_independence ( )\n\t *\tif ( frame_type == KEY_FRAME || error_resilient_mode == 1 ||\n\t *\t     reset_frame_context == 3 ) {\n\t *\t\tfor ( i = 0; i < 4; i ++ ) {\n\t *\t\t\tsave_probs( i )\n\t *\t\t}\n\t *\t} else if ( reset_frame_context == 2 ) {\n\t *\t\tsave_probs( frame_context_idx )\n\t *\t}\n\t *\tframe_context_idx = 0\n\t * }\n\t */\n\tfctx_idx = v4l2_vp9_reset_frame_ctx(*dec_params, vp9_ctx->frame_context);\n\tvp9_ctx->cur.frame_context_idx = fctx_idx;\n\n\t/* 6.1 frame(sz): load_probs() and load_probs2() */\n\tvp9_ctx->probability_tables = vp9_ctx->frame_context[fctx_idx];\n\n\t/*\n\t * The userspace has also performed 6.3 compressed_header(), but handling the\n\t * probs in a special way. All probs which need updating, except MV-related,\n\t * have been read from the bitstream and translated through inv_map_table[],\n\t * but no 6.3.6 inv_recenter_nonneg(v, m) has been performed. The values passed\n\t * by userspace are either translated values (there are no 0 values in\n\t * inv_map_table[]), or zero to indicate no update. All MV-related probs which need\n\t * updating have been read from the bitstream and (mv_prob << 1) | 1 has been\n\t * performed. The values passed by userspace are either new values\n\t * to replace old ones (the above mentioned shift and bitwise or never result in\n\t * a zero) or zero to indicate no update.\n\t * fw_update_probs() performs actual probs updates or leaves probs as-is\n\t * for values for which a zero was passed from userspace.\n\t */\n\tv4l2_vp9_fw_update_probs(&vp9_ctx->probability_tables, prob_updates, *dec_params);\n\n\treturn 0;\n}",
        "static void arc_serial_rx_chars(struct uart_port *port, unsigned int status)\n{\n\tunsigned int ch, flg = 0;\n\n\t/*": "static void arc_serial_rx_chars(struct uart_port *port, unsigned int status)\n{\n\tunsigned int ch, flg = 0;\n\n\t/*\n\t * UART has 4 deep RX-FIFO. Driver's recongnition of this fact\n\t * is very subtle. Here's how ...\n\t * Upon getting a RX-Intr, such that RX-EMPTY=0, meaning data available,\n\t * driver reads the DATA Reg and keeps doing that in a loop, until\n\t * RX-EMPTY=1. Multiple chars being avail, with a single Interrupt,\n\t * before RX-EMPTY=0, implies some sort of buffering going on in the\n\t * controller, which is indeed the Rx-FIFO.\n\t */\n\tdo {\n\t\t/*\n\t\t * This could be an Rx Intr for err (no data),\n\t\t * so check err and clear that Intr first\n\t\t */\n\t\tif (unlikely(status & (RXOERR | RXFERR))) {\n\t\t\tif (status & RXOERR) {\n\t\t\t\tport->icount.overrun++;\n\t\t\t\tflg = TTY_OVERRUN;\n\t\t\t\tUART_CLR_STATUS(port, RXOERR);\n\t\t\t}\n\n\t\t\tif (status & RXFERR) {\n\t\t\t\tport->icount.frame++;\n\t\t\t\tflg = TTY_FRAME;\n\t\t\t\tUART_CLR_STATUS(port, RXFERR);\n\t\t\t}\n\t\t} else\n\t\t\tflg = TTY_NORMAL;\n\n\t\tif (status & RXEMPTY)\n\t\t\tcontinue;\n\n\t\tch = UART_GET_DATA(port);\n\t\tport->icount.rx++;\n\n\t\tif (!(uart_handle_sysrq_char(port, ch)))\n\t\t\tuart_insert_char(port, status, RXOERR, ch, flg);\n\n\t\ttty_flip_buffer_push(&port->state->port);\n\t} while (!((status = UART_GET_STATUS(port)) & RXEMPTY));\n}",
        "static int __init video_init(struct ibm_init_struct *iibm)\n{\n\tint ivga;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing video subdriver\\n\");": "static int __init video_init(struct ibm_init_struct *iibm)\n{\n\tint ivga;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing video subdriver\\n\");\n\n\tTPACPI_ACPIHANDLE_INIT(vid);\n\tif (tpacpi_is_ibm())\n\t\tTPACPI_ACPIHANDLE_INIT(vid2);\n\n\tif (vid2_handle && acpi_evalf(NULL, &ivga, \"\\\\IVGA\", \"d\") && ivga)\n\t\t/* G41, assume IVGA doesn't change */\n\t\tvid_handle = vid2_handle;\n\n\tif (!vid_handle)\n\t\t/* video switching not supported on R30, R31 */\n\t\tvideo_supported = TPACPI_VIDEO_NONE;\n\telse if (tpacpi_is_ibm() &&\n\t\t acpi_evalf(vid_handle, &video_orig_autosw, \"SWIT\", \"qd\"))\n\t\t/* 570 */\n\t\tvideo_supported = TPACPI_VIDEO_570;\n\telse if (tpacpi_is_ibm() &&\n\t\t acpi_evalf(vid_handle, &video_orig_autosw, \"^VADL\", \"qd\"))\n\t\t/* 600e/x, 770e, 770x */\n\t\tvideo_supported = TPACPI_VIDEO_770;\n\telse\n\t\t/* all others */\n\t\tvideo_supported = TPACPI_VIDEO_NEW;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"video is %s, mode %d\\n\",\n\t\tstr_supported(video_supported != TPACPI_VIDEO_NONE),\n\t\tvideo_supported);\n\n\treturn (video_supported != TPACPI_VIDEO_NONE) ? 0 : -ENODEV;\n}",
        "static int test_syswide_multi_same_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));": "static int test_syswide_multi_same_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));\n\tchar *desc = \"Systemwide, Two events, same addr\";\n\tint ret;\n\n\tret = perf_systemwide_event_open(fd1, HW_BREAKPOINT_RW, (__u64)&a, (__u64)sizeof(a));\n\tif (ret) {\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tret = perf_systemwide_event_open(fd2, HW_BREAKPOINT_RW, (__u64)&a, (__u64)sizeof(a));\n\tif (ret) {\n\t\tclose_fds(fd1, nprocs);\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\treset_fds(fd1, nprocs);\n\treset_fds(fd2, nprocs);\n\tenable_fds(fd1, nprocs);\n\tenable_fds(fd2, nprocs);\n\tmulti_dawr_workload();\n\tdisable_fds(fd1, nprocs);\n\tdisable_fds(fd2, nprocs);\n\n\tbreaks1 = read_fds(fd1, nprocs);\n\tbreaks2 = read_fds(fd2, nprocs);\n\n\tclose_fds(fd1, nprocs);\n\tclose_fds(fd2, nprocs);\n\n\tfree(fd1);\n\tfree(fd2);\n\n\tif (breaks1 != 2 || breaks2 != 2) {\n\t\tprintf(\"FAILED: %s: %lld != 2 || %lld != 2\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)\n{\n\tu32 chipver;\n\tint fw, status, j;\n\tstruct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;": "static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)\n{\n\tu32 chipver;\n\tint fw, status, j;\n\tstruct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;\n\n\tstate->base->ts_map = ts_map1_to_1;\n\n\tswitch (state->base->type) {\n\tcase MXL_HYDRA_DEVICE_581:\n\tcase MXL_HYDRA_DEVICE_581S:\n\t\tstate->base->can_clkout = 1;\n\t\tstate->base->demod_num = 8;\n\t\tstate->base->tuner_num = 1;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_581;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_582:\n\t\tstate->base->can_clkout = 1;\n\t\tstate->base->demod_num = 8;\n\t\tstate->base->tuner_num = 3;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_582;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_585:\n\t\tstate->base->can_clkout = 0;\n\t\tstate->base->demod_num = 8;\n\t\tstate->base->tuner_num = 4;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_585;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_544:\n\t\tstate->base->can_clkout = 0;\n\t\tstate->base->demod_num = 4;\n\t\tstate->base->tuner_num = 4;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_544;\n\t\tstate->base->ts_map = ts_map54x;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_541:\n\tcase MXL_HYDRA_DEVICE_541S:\n\t\tstate->base->can_clkout = 0;\n\t\tstate->base->demod_num = 4;\n\t\tstate->base->tuner_num = 1;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_541;\n\t\tstate->base->ts_map = ts_map54x;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_561:\n\tcase MXL_HYDRA_DEVICE_561S:\n\t\tstate->base->can_clkout = 0;\n\t\tstate->base->demod_num = 6;\n\t\tstate->base->tuner_num = 1;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_561;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_568:\n\t\tstate->base->can_clkout = 0;\n\t\tstate->base->demod_num = 8;\n\t\tstate->base->tuner_num = 1;\n\t\tstate->base->chan_bond = 1;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_568;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_542:\n\t\tstate->base->can_clkout = 1;\n\t\tstate->base->demod_num = 4;\n\t\tstate->base->tuner_num = 3;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_542;\n\t\tstate->base->ts_map = ts_map54x;\n\t\tbreak;\n\tcase MXL_HYDRA_DEVICE_TEST:\n\tcase MXL_HYDRA_DEVICE_584:\n\tdefault:\n\t\tstate->base->can_clkout = 0;\n\t\tstate->base->demod_num = 8;\n\t\tstate->base->tuner_num = 4;\n\t\tstate->base->sku_type = MXL_HYDRA_SKU_TYPE_584;\n\t\tbreak;\n\t}\n\n\tstatus = validate_sku(state);\n\tif (status)\n\t\treturn status;\n\n\tupdate_by_mnemonic(state, 0x80030014, 9, 1, 1);\n\tupdate_by_mnemonic(state, 0x8003003C, 12, 1, 1);\n\tstatus = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);\n\tif (status)\n\t\tstate->base->chipversion = 0;\n\telse\n\t\tstate->base->chipversion = (chipver == 2) ? 2 : 1;\n\tdev_info(state->i2cdev, \"Hydra chip version %u\\n\",\n\t\tstate->base->chipversion);\n\n\tcfg_dev_xtal(state, cfg->clk, cfg->cap, 0);\n\n\tfw = firmware_is_alive(state);\n\tif (!fw) {\n\t\tstatus = load_fw(state, cfg);\n\t\tif (status)\n\t\t\treturn status;\n\t}\n\tget_fwinfo(state);\n\n\tconfig_mux(state);\n\tmpeg_interface_cfg.enable = MXL_ENABLE;\n\tmpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;\n\t/*  supports only (0-104&139)MHz */\n\tif (cfg->ts_clk)\n\t\tmpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;\n\telse\n\t\tmpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */\n\tmpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;\n\tmpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;\n\t/* MXL_HYDRA_MPEG_CLK_GAPPED; */\n\tmpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;\n\tmpeg_interface_cfg.mpeg_error_indication =\n\t\tMXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;\n\tmpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;\n\tmpeg_interface_cfg.mpeg_sync_pol  = MXL_HYDRA_MPEG_ACTIVE_HIGH;\n\tmpeg_interface_cfg.mpeg_sync_pulse_width  = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;\n\tmpeg_interface_cfg.mpeg_valid_pol  = MXL_HYDRA_MPEG_ACTIVE_HIGH;\n\n\tfor (j = 0; j < state->base->demod_num; j++) {\n\t\tstatus = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,\n\t\t\t\t   &mpeg_interface_cfg);\n\t\tif (status)\n\t\t\treturn status;\n\t}\n\tset_drive_strength(state, 1);\n\treturn 0;\n}",
        "static void ice_reset_subtask(struct ice_pf *pf)\n{\n\tenum ice_reset_req reset_type = ICE_RESET_INVAL;\n\n\t/* When a CORER/GLOBR/EMPR is about to happen, the hardware triggers an": "static void ice_reset_subtask(struct ice_pf *pf)\n{\n\tenum ice_reset_req reset_type = ICE_RESET_INVAL;\n\n\t/* When a CORER/GLOBR/EMPR is about to happen, the hardware triggers an\n\t * OICR interrupt. The OICR handler (ice_misc_intr) determines what type\n\t * of reset is pending and sets bits in pf->state indicating the reset\n\t * type and ICE_RESET_OICR_RECV. So, if the latter bit is set\n\t * prepare for pending reset if not already (for PF software-initiated\n\t * global resets the software should already be prepared for it as\n\t * indicated by ICE_PREPARED_FOR_RESET; for global resets initiated\n\t * by firmware or software on other PFs, that bit is not set so prepare\n\t * for the reset now), poll for reset done, rebuild and return.\n\t */\n\tif (test_bit(ICE_RESET_OICR_RECV, pf->state)) {\n\t\t/* Perform the largest reset requested */\n\t\tif (test_and_clear_bit(ICE_CORER_RECV, pf->state))\n\t\t\treset_type = ICE_RESET_CORER;\n\t\tif (test_and_clear_bit(ICE_GLOBR_RECV, pf->state))\n\t\t\treset_type = ICE_RESET_GLOBR;\n\t\tif (test_and_clear_bit(ICE_EMPR_RECV, pf->state))\n\t\t\treset_type = ICE_RESET_EMPR;\n\t\t/* return if no valid reset type requested */\n\t\tif (reset_type == ICE_RESET_INVAL)\n\t\t\treturn;\n\t\tice_prepare_for_reset(pf, reset_type);\n\n\t\t/* make sure we are ready to rebuild */\n\t\tif (ice_check_reset(&pf->hw)) {\n\t\t\tset_bit(ICE_RESET_FAILED, pf->state);\n\t\t} else {\n\t\t\t/* done with reset. start rebuild */\n\t\t\tpf->hw.reset_ongoing = false;\n\t\t\tice_rebuild(pf, reset_type);\n\t\t\t/* clear bit to resume normal operations, but\n\t\t\t * ICE_NEEDS_RESTART bit is set in case rebuild failed\n\t\t\t */\n\t\t\tclear_bit(ICE_RESET_OICR_RECV, pf->state);\n\t\t\tclear_bit(ICE_PREPARED_FOR_RESET, pf->state);\n\t\t\tclear_bit(ICE_PFR_REQ, pf->state);\n\t\t\tclear_bit(ICE_CORER_REQ, pf->state);\n\t\t\tclear_bit(ICE_GLOBR_REQ, pf->state);\n\t\t\twake_up(&pf->reset_wait_queue);\n\t\t\tice_reset_all_vfs(pf);\n\t\t}\n\n\t\treturn;\n\t}\n\n\t/* No pending resets to finish processing. Check for new resets */\n\tif (test_bit(ICE_PFR_REQ, pf->state))\n\t\treset_type = ICE_RESET_PFR;\n\tif (test_bit(ICE_CORER_REQ, pf->state))\n\t\treset_type = ICE_RESET_CORER;\n\tif (test_bit(ICE_GLOBR_REQ, pf->state))\n\t\treset_type = ICE_RESET_GLOBR;\n\t/* If no valid reset type requested just return */\n\tif (reset_type == ICE_RESET_INVAL)\n\t\treturn;\n\n\t/* reset if not already down or busy */\n\tif (!test_bit(ICE_DOWN, pf->state) &&\n\t    !test_bit(ICE_CFG_BUSY, pf->state)) {\n\t\tice_do_reset(pf, reset_type);\n\t}\n}",
        "static int test_syswide_multi_diff_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));": "static int test_syswide_multi_diff_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint *fd1 = malloc(nprocs * sizeof(int));\n\tint *fd2 = malloc(nprocs * sizeof(int));\n\tchar *desc = \"Systemwide, Two events, diff addr\";\n\tint ret;\n\n\tret = perf_systemwide_event_open(fd1, HW_BREAKPOINT_RW, (__u64)&a, (__u64)sizeof(a));\n\tif (ret) {\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tret = perf_systemwide_event_open(fd2, HW_BREAKPOINT_RW, (__u64)&b, (__u64)sizeof(b));\n\tif (ret) {\n\t\tclose_fds(fd1, nprocs);\n\t\tperror(\"perf_systemwide_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\treset_fds(fd1, nprocs);\n\treset_fds(fd2, nprocs);\n\tenable_fds(fd1, nprocs);\n\tenable_fds(fd2, nprocs);\n\tmulti_dawr_workload();\n\tdisable_fds(fd1, nprocs);\n\tdisable_fds(fd2, nprocs);\n\n\tbreaks1 = read_fds(fd1, nprocs);\n\tbreaks2 = read_fds(fd2, nprocs);\n\n\tclose_fds(fd1, nprocs);\n\tclose_fds(fd2, nprocs);\n\n\tfree(fd1);\n\tfree(fd2);\n\n\tif (breaks1 != 2 || breaks2 != 2) {\n\t\tprintf(\"FAILED: %s: %lld != 2 || %lld != 2\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static void test_vxlan_tunnel(void)\n{\n\tstruct test_tunnel_kern *skel = NULL;\n\tstruct nstoken *nstoken;\n\tint local_ip_map_fd = -1;": "static void test_vxlan_tunnel(void)\n{\n\tstruct test_tunnel_kern *skel = NULL;\n\tstruct nstoken *nstoken;\n\tint local_ip_map_fd = -1;\n\tint set_src_prog_fd, get_src_prog_fd;\n\tint set_dst_prog_fd;\n\tint key = 0, ifindex = -1;\n\tuint local_ip;\n\tint err;\n\tDECLARE_LIBBPF_OPTS(bpf_tc_hook, tc_hook,\n\t\t\t    .attach_point = BPF_TC_INGRESS);\n\n\t/* add vxlan tunnel */\n\terr = add_vxlan_tunnel();\n\tif (!ASSERT_OK(err, \"add vxlan tunnel\"))\n\t\tgoto done;\n\n\t/* load and attach bpf prog to tunnel dev tc hook point */\n\tskel = test_tunnel_kern__open_and_load();\n\tif (!ASSERT_OK_PTR(skel, \"test_tunnel_kern__open_and_load\"))\n\t\tgoto done;\n\tifindex = if_nametoindex(VXLAN_TUNL_DEV1);\n\tif (!ASSERT_NEQ(ifindex, 0, \"vxlan11 ifindex\"))\n\t\tgoto done;\n\ttc_hook.ifindex = ifindex;\n\tget_src_prog_fd = bpf_program__fd(skel->progs.vxlan_get_tunnel_src);\n\tset_src_prog_fd = bpf_program__fd(skel->progs.vxlan_set_tunnel_src);\n\tif (!ASSERT_GE(get_src_prog_fd, 0, \"bpf_program__fd\"))\n\t\tgoto done;\n\tif (!ASSERT_GE(set_src_prog_fd, 0, \"bpf_program__fd\"))\n\t\tgoto done;\n\tif (attach_tc_prog(&tc_hook, get_src_prog_fd, set_src_prog_fd))\n\t\tgoto done;\n\n\t/* load and attach prog set_md to tunnel dev tc hook point at_ns0 */\n\tnstoken = open_netns(\"at_ns0\");\n\tif (!ASSERT_OK_PTR(nstoken, \"setns src\"))\n\t\tgoto done;\n\tifindex = if_nametoindex(VXLAN_TUNL_DEV0);\n\tif (!ASSERT_NEQ(ifindex, 0, \"vxlan00 ifindex\"))\n\t\tgoto done;\n\ttc_hook.ifindex = ifindex;\n\tset_dst_prog_fd = bpf_program__fd(skel->progs.vxlan_set_tunnel_dst);\n\tif (!ASSERT_GE(set_dst_prog_fd, 0, \"bpf_program__fd\"))\n\t\tgoto done;\n\tif (attach_tc_prog(&tc_hook, -1, set_dst_prog_fd))\n\t\tgoto done;\n\tclose_netns(nstoken);\n\n\t/* use veth1 ip 2 as tunnel source ip */\n\tlocal_ip_map_fd = bpf_map__fd(skel->maps.local_ip_map);\n\tif (!ASSERT_GE(local_ip_map_fd, 0, \"bpf_map__fd\"))\n\t\tgoto done;\n\tlocal_ip = IP4_ADDR2_HEX_VETH1;\n\terr = bpf_map_update_elem(local_ip_map_fd, &key, &local_ip, BPF_ANY);\n\tif (!ASSERT_OK(err, \"update bpf local_ip_map\"))\n\t\tgoto done;\n\n\t/* ping test */\n\terr = test_ping(AF_INET, IP4_ADDR_TUNL_DEV0);\n\tif (!ASSERT_OK(err, \"test_ping\"))\n\t\tgoto done;\n\ndone:\n\t/* delete vxlan tunnel */\n\tdelete_vxlan_tunnel();\n\tif (local_ip_map_fd >= 0)\n\t\tclose(local_ip_map_fd);\n\tif (skel)\n\t\ttest_tunnel_kern__destroy(skel);\n}",
        "static bool __report_matches(const struct expect_report *r)\n{\n\tconst bool is_assert = (r->access[0].type | r->access[1].type) & KCSAN_ACCESS_ASSERT;\n\tbool ret = false;\n\tunsigned long flags;": "static bool __report_matches(const struct expect_report *r)\n{\n\tconst bool is_assert = (r->access[0].type | r->access[1].type) & KCSAN_ACCESS_ASSERT;\n\tbool ret = false;\n\tunsigned long flags;\n\ttypeof(observed.lines) expect;\n\tconst char *end;\n\tchar *cur;\n\tint i;\n\n\t/* Doubled-checked locking. */\n\tif (!report_available())\n\t\treturn false;\n\n\t/* Generate expected report contents. */\n\n\t/* Title */\n\tcur = expect[0];\n\tend = &expect[0][sizeof(expect[0]) - 1];\n\tcur += scnprintf(cur, end - cur, \"BUG: KCSAN: %s in \",\n\t\t\t is_assert ? \"assert: race\" : \"data-race\");\n\tif (r->access[1].fn) {\n\t\tchar tmp[2][64];\n\t\tint cmp;\n\n\t\t/* Expect lexographically sorted function names in title. */\n\t\tscnprintf(tmp[0], sizeof(tmp[0]), \"%pS\", r->access[0].fn);\n\t\tscnprintf(tmp[1], sizeof(tmp[1]), \"%pS\", r->access[1].fn);\n\t\tcmp = strcmp(tmp[0], tmp[1]);\n\t\tcur += scnprintf(cur, end - cur, \"%ps / %ps\",\n\t\t\t\t cmp < 0 ? r->access[0].fn : r->access[1].fn,\n\t\t\t\t cmp < 0 ? r->access[1].fn : r->access[0].fn);\n\t} else {\n\t\tscnprintf(cur, end - cur, \"%pS\", r->access[0].fn);\n\t\t/* The exact offset won't match, remove it. */\n\t\tcur = strchr(expect[0], '+');\n\t\tif (cur)\n\t\t\t*cur = '\\0';\n\t}\n\n\t/* Access 1 */\n\tcur = expect[1];\n\tend = &expect[1][sizeof(expect[1]) - 1];\n\tif (!r->access[1].fn)\n\t\tcur += scnprintf(cur, end - cur, \"race at unknown origin, with \");\n\n\t/* Access 1 & 2 */\n\tfor (i = 0; i < 2; ++i) {\n\t\tconst int ty = r->access[i].type;\n\t\tconst char *const access_type =\n\t\t\t(ty & KCSAN_ACCESS_ASSERT) ?\n\t\t\t\t      ((ty & KCSAN_ACCESS_WRITE) ?\n\t\t\t\t\t       \"assert no accesses\" :\n\t\t\t\t\t       \"assert no writes\") :\n\t\t\t\t      ((ty & KCSAN_ACCESS_WRITE) ?\n\t\t\t\t\t       ((ty & KCSAN_ACCESS_COMPOUND) ?\n\t\t\t\t\t\t\t\"read-write\" :\n\t\t\t\t\t\t\t\"write\") :\n\t\t\t\t\t       \"read\");\n\t\tconst bool is_atomic = (ty & KCSAN_ACCESS_ATOMIC);\n\t\tconst bool is_scoped = (ty & KCSAN_ACCESS_SCOPED);\n\t\tconst char *const access_type_aux =\n\t\t\t\t(is_atomic && is_scoped)\t? \" (marked, reordered)\"\n\t\t\t\t: (is_atomic\t\t\t? \" (marked)\"\n\t\t\t\t   : (is_scoped\t\t\t? \" (reordered)\" : \"\"));\n\n\t\tif (i == 1) {\n\t\t\t/* Access 2 */\n\t\t\tcur = expect[2];\n\t\t\tend = &expect[2][sizeof(expect[2]) - 1];\n\n\t\t\tif (!r->access[1].fn) {\n\t\t\t\t/* Dummy string if no second access is available. */\n\t\t\t\tstrcpy(cur, \"<none>\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tcur += scnprintf(cur, end - cur, \"%s%s to \", access_type,\n\t\t\t\t access_type_aux);\n\n\t\tif (r->access[i].addr) /* Address is optional. */\n\t\t\tcur += scnprintf(cur, end - cur, \"0x%px of %zu bytes\",\n\t\t\t\t\t r->access[i].addr, r->access[i].size);\n\t}\n\n\tspin_lock_irqsave(&observed.lock, flags);\n\tif (!report_available())\n\t\tgoto out; /* A new report is being captured. */\n\n\t/* Finally match expected output to what we actually observed. */\n\tret = strstr(observed.lines[0], expect[0]) &&\n\t      /* Access info may appear in any order. */\n\t      ((strstr(observed.lines[1], expect[1]) &&\n\t\tstrstr(observed.lines[2], expect[2])) ||\n\t       (strstr(observed.lines[1], expect[2]) &&\n\t\tstrstr(observed.lines[2], expect[1])));\nout:\n\tspin_unlock_irqrestore(&observed.lock, flags);\n\treturn ret;\n}",
        "static int mac_onboard_sonic_probe(struct net_device *dev)\n{\n\tstruct sonic_local* lp = netdev_priv(dev);\n\tint sr;\n\tbool commslot = macintosh_config->expansion_type == MAC_EXP_PDS_COMM;": "static int mac_onboard_sonic_probe(struct net_device *dev)\n{\n\tstruct sonic_local* lp = netdev_priv(dev);\n\tint sr;\n\tbool commslot = macintosh_config->expansion_type == MAC_EXP_PDS_COMM;\n\n\t/* Bogus probing, on the models which may or may not have\n\t   Ethernet (BTW, the Ethernet *is* always at the same\n\t   address, and nothing else lives there, at least if Apple's\n\t   documentation is to be believed) */\n\tif (commslot || macintosh_config->ident == MAC_MODEL_C610) {\n\t\tint card_present;\n\n\t\tcard_present = hwreg_present((void*)ONBOARD_SONIC_REGISTERS);\n\t\tif (!card_present) {\n\t\t\tpr_info(\"Onboard/comm-slot SONIC not found\\n\");\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\n\t/* Danger!  My arms are flailing wildly!  You *must* set lp->reg_offset\n\t * and dev->base_addr before using SONIC_READ() or SONIC_WRITE() */\n\tdev->base_addr = ONBOARD_SONIC_REGISTERS;\n\tif (via_alt_mapping)\n\t\tdev->irq = IRQ_AUTO_3;\n\telse\n\t\tdev->irq = IRQ_NUBUS_9;\n\n\t/* The PowerBook's SONIC is 16 bit always. */\n\tif (macintosh_config->ident == MAC_MODEL_PB520) {\n\t\tlp->reg_offset = 0;\n\t\tlp->dma_bitmode = SONIC_BITMODE16;\n\t} else if (commslot) {\n\t\t/* Some of the comm-slot cards are 16 bit.  But some\n\t\t   of them are not.  The 32-bit cards use offset 2 and\n\t\t   have known revisions, we try reading the revision\n\t\t   register at offset 2, if we don't get a known revision\n\t\t   we assume 16 bit at offset 0.  */\n\t\tlp->reg_offset = 2;\n\t\tlp->dma_bitmode = SONIC_BITMODE16;\n\n\t\tsr = SONIC_READ(SONIC_SR);\n\t\tif (sr == 0x0004 || sr == 0x0006 || sr == 0x0100 || sr == 0x0101)\n\t\t\t/* 83932 is 0x0004 or 0x0006, 83934 is 0x0100 or 0x0101 */\n\t\t\tlp->dma_bitmode = SONIC_BITMODE32;\n\t\telse {\n\t\t\tlp->dma_bitmode = SONIC_BITMODE16;\n\t\t\tlp->reg_offset = 0;\n\t\t}\n\t} else {\n\t\t/* All onboard cards are at offset 2 with 32 bit DMA. */\n\t\tlp->reg_offset = 2;\n\t\tlp->dma_bitmode = SONIC_BITMODE32;\n\t}\n\n\tpr_info(\"Onboard/comm-slot SONIC, revision 0x%04x, %d bit DMA, register offset %d\\n\",\n\t\tSONIC_READ(SONIC_SR), lp->dma_bitmode ? 32 : 16,\n\t\tlp->reg_offset);\n\n\t/* This is sometimes useful to find out how MacOS configured the card */\n\tpr_debug(\"%s: DCR=0x%04x, DCR2=0x%04x\\n\", __func__,\n\t\t SONIC_READ(SONIC_DCR) & 0xffff,\n\t\t SONIC_READ(SONIC_DCR2) & 0xffff);\n\n\t/* Software reset, then initialize control registers. */\n\tSONIC_WRITE(SONIC_CMD, SONIC_CR_RST);\n\n\tSONIC_WRITE(SONIC_DCR, SONIC_DCR_EXBUS | SONIC_DCR_BMS |\n\t                       SONIC_DCR_RFT1  | SONIC_DCR_TFT0 |\n\t                       (lp->dma_bitmode ? SONIC_DCR_DW : 0));\n\n\t/* This *must* be written back to in order to restore the\n\t * extended programmable output bits, as it may not have been\n\t * initialised since the hardware reset. */\n\tSONIC_WRITE(SONIC_DCR2, 0);\n\n\t/* Clear *and* disable interrupts to be on the safe side */\n\tSONIC_WRITE(SONIC_IMR, 0);\n\tSONIC_WRITE(SONIC_ISR, 0x7fff);\n\n\t/* Now look for the MAC address. */\n\tmac_onboard_sonic_ethernet_addr(dev);\n\n\tpr_info(\"SONIC ethernet @%08lx, MAC %pM, IRQ %d\\n\",\n\t\tdev->base_addr, dev->dev_addr, dev->irq);\n\n\t/* Shared init code */\n\treturn macsonic_init(dev);\n}",
        "static int io_poll_remove(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_cancel_data cd = { .data = req->poll_update.old_user_data, };\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_kiocb *preq;": "static int io_poll_remove(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_cancel_data cd = { .data = req->poll_update.old_user_data, };\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_kiocb *preq;\n\tint ret2, ret = 0;\n\tbool locked;\n\n\tspin_lock(&ctx->completion_lock);\n\tpreq = io_poll_find(ctx, true, &cd);\n\tif (!preq || !io_poll_disarm(preq)) {\n\t\tspin_unlock(&ctx->completion_lock);\n\t\tret = preq ? -EALREADY : -ENOENT;\n\t\tgoto out;\n\t}\n\tspin_unlock(&ctx->completion_lock);\n\n\tif (req->poll_update.update_events || req->poll_update.update_user_data) {\n\t\t/* only mask one event flags, keep behavior flags */\n\t\tif (req->poll_update.update_events) {\n\t\t\tpreq->poll.events &= ~0xffff;\n\t\t\tpreq->poll.events |= req->poll_update.events & 0xffff;\n\t\t\tpreq->poll.events |= IO_POLL_UNMASK;\n\t\t}\n\t\tif (req->poll_update.update_user_data)\n\t\t\tpreq->cqe.user_data = req->poll_update.new_user_data;\n\n\t\tret2 = io_poll_add(preq, issue_flags);\n\t\t/* successfully updated, don't complete poll request */\n\t\tif (!ret2)\n\t\t\tgoto out;\n\t}\n\n\treq_set_fail(preq);\n\tpreq->cqe.res = -ECANCELED;\n\tlocked = !(issue_flags & IO_URING_F_UNLOCKED);\n\tio_req_task_complete(preq, &locked);\nout:\n\tif (ret < 0)\n\t\treq_set_fail(req);\n\t/* complete update request, we're done with it */\n\t__io_req_complete(req, issue_flags, ret, 0);\n\treturn 0;\n}",
        "static void get_stack_print_output(void *ctx, int cpu, void *data, __u32 size)\n{\n\tbool good_kern_stack = false, good_user_stack = false;\n\tconst char *nonjit_func = \"___bpf_prog_run\";\n\t/* perfbuf-submitted data is 4-byte aligned, but we need 8-byte": "static void get_stack_print_output(void *ctx, int cpu, void *data, __u32 size)\n{\n\tbool good_kern_stack = false, good_user_stack = false;\n\tconst char *nonjit_func = \"___bpf_prog_run\";\n\t/* perfbuf-submitted data is 4-byte aligned, but we need 8-byte\n\t * alignment, so copy data into a local variable, for simplicity\n\t */\n\tstruct get_stack_trace_t e;\n\tint i, num_stack;\n\tstruct ksym *ks;\n\n\tmemset(&e, 0, sizeof(e));\n\tmemcpy(&e, data, size <= sizeof(e) ? size : sizeof(e));\n\n\tif (size < sizeof(struct get_stack_trace_t)) {\n\t\t__u64 *raw_data = data;\n\t\tbool found = false;\n\n\t\tnum_stack = size / sizeof(__u64);\n\t\t/* If jit is enabled, we do not have a good way to\n\t\t * verify the sanity of the kernel stack. So we\n\t\t * just assume it is good if the stack is not empty.\n\t\t * This could be improved in the future.\n\t\t */\n\t\tif (env.jit_enabled) {\n\t\t\tfound = num_stack > 0;\n\t\t} else {\n\t\t\tfor (i = 0; i < num_stack; i++) {\n\t\t\t\tks = ksym_search(raw_data[i]);\n\t\t\t\tif (ks && (strcmp(ks->name, nonjit_func) == 0)) {\n\t\t\t\t\tfound = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (found) {\n\t\t\tgood_kern_stack = true;\n\t\t\tgood_user_stack = true;\n\t\t}\n\t} else {\n\t\tnum_stack = e.kern_stack_size / sizeof(__u64);\n\t\tif (env.jit_enabled) {\n\t\t\tgood_kern_stack = num_stack > 0;\n\t\t} else {\n\t\t\tfor (i = 0; i < num_stack; i++) {\n\t\t\t\tks = ksym_search(e.kern_stack[i]);\n\t\t\t\tif (ks && (strcmp(ks->name, nonjit_func) == 0)) {\n\t\t\t\t\tgood_kern_stack = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (e.user_stack_size > 0 && e.user_stack_buildid_size > 0)\n\t\t\tgood_user_stack = true;\n\t}\n\n\tif (!good_kern_stack)\n\t    CHECK(!good_kern_stack, \"kern_stack\", \"corrupted kernel stack\\n\");\n\tif (!good_user_stack)\n\t    CHECK(!good_user_stack, \"user_stack\", \"corrupted user stack\\n\");\n}",
        "static void test_multi_sethwdebug_range_dawr_overlap(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info1, info2;\n\tunsigned long wp_addr1, wp_addr2;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DAWR Overlap\";": "static void test_multi_sethwdebug_range_dawr_overlap(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info1, info2;\n\tunsigned long wp_addr1, wp_addr2;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DAWR Overlap\";\n\tint len1, len2;\n\tint wh1, wh2;\n\n\twp_addr1 = (unsigned long)&gstruct.a;\n\twp_addr2 = (unsigned long)&gstruct.a;\n\tlen1 = A_LEN;\n\tlen2 = A_LEN;\n\tget_ppc_hw_breakpoint(&info1, PPC_BREAKPOINT_TRIGGER_WRITE, wp_addr1, len1);\n\tget_ppc_hw_breakpoint(&info2, PPC_BREAKPOINT_TRIGGER_READ, wp_addr2, len2);\n\n\t/* PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DAWR Overlap, WO test */\n\twh1 = ptrace_sethwdebug(child_pid, &info1);\n\n\t/* PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DAWR Overlap, RO test */\n\twh2 = ptrace_sethwdebug(child_pid, &info2);\n\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"WO\", wp_addr1, len1);\n\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RO\", wp_addr2, len2);\n\n\tptrace_delhwdebug(child_pid, wh1);\n\tptrace_delhwdebug(child_pid, wh2);\n}",
        "static int __bpf_hash_map_seq_show(struct seq_file *seq, struct htab_elem *elem)\n{\n\tstruct bpf_iter_seq_hash_map_info *info = seq->private;\n\tu32 roundup_key_size, roundup_value_size;\n\tstruct bpf_iter__bpf_map_elem ctx = {};": "static int __bpf_hash_map_seq_show(struct seq_file *seq, struct htab_elem *elem)\n{\n\tstruct bpf_iter_seq_hash_map_info *info = seq->private;\n\tu32 roundup_key_size, roundup_value_size;\n\tstruct bpf_iter__bpf_map_elem ctx = {};\n\tstruct bpf_map *map = info->map;\n\tstruct bpf_iter_meta meta;\n\tint ret = 0, off = 0, cpu;\n\tstruct bpf_prog *prog;\n\tvoid __percpu *pptr;\n\n\tmeta.seq = seq;\n\tprog = bpf_iter_get_info(&meta, elem == NULL);\n\tif (prog) {\n\t\tctx.meta = &meta;\n\t\tctx.map = info->map;\n\t\tif (elem) {\n\t\t\troundup_key_size = round_up(map->key_size, 8);\n\t\t\tctx.key = elem->key;\n\t\t\tif (!info->percpu_value_buf) {\n\t\t\t\tctx.value = elem->key + roundup_key_size;\n\t\t\t} else {\n\t\t\t\troundup_value_size = round_up(map->value_size, 8);\n\t\t\t\tpptr = htab_elem_get_ptr(elem, map->key_size);\n\t\t\t\tfor_each_possible_cpu(cpu) {\n\t\t\t\t\tbpf_long_memcpy(info->percpu_value_buf + off,\n\t\t\t\t\t\t\tper_cpu_ptr(pptr, cpu),\n\t\t\t\t\t\t\troundup_value_size);\n\t\t\t\t\toff += roundup_value_size;\n\t\t\t\t}\n\t\t\t\tctx.value = info->percpu_value_buf;\n\t\t\t}\n\t\t}\n\t\tret = bpf_iter_run_prog(prog, &ctx);\n\t}\n\n\treturn ret;\n}",
        "static int __trace_eprobe_create(int argc, const char *argv[])\n{\n\t/*\n\t * Argument syntax:\n\t *      e[:[GRP/]ENAME] SYSTEM.EVENT [FETCHARGS]": "static int __trace_eprobe_create(int argc, const char *argv[])\n{\n\t/*\n\t * Argument syntax:\n\t *      e[:[GRP/]ENAME] SYSTEM.EVENT [FETCHARGS]\n\t * Fetch args:\n\t *  <name>=$<field>[:TYPE]\n\t */\n\tconst char *event = NULL, *group = EPROBE_EVENT_SYSTEM;\n\tconst char *sys_event = NULL, *sys_name = NULL;\n\tstruct trace_event_call *event_call;\n\tstruct trace_eprobe *ep = NULL;\n\tchar buf1[MAX_EVENT_NAME_LEN];\n\tchar buf2[MAX_EVENT_NAME_LEN];\n\tint ret = 0;\n\tint i;\n\n\tif (argc < 2 || argv[0][0] != 'e')\n\t\treturn -ECANCELED;\n\n\ttrace_probe_log_init(\"event_probe\", argc, argv);\n\n\tevent = strchr(&argv[0][1], ':');\n\tif (event) {\n\t\tevent++;\n\t\tret = traceprobe_parse_event_name(&event, &group, buf1,\n\t\t\t\t\t\t  event - argv[0]);\n\t\tif (ret)\n\t\t\tgoto parse_error;\n\t} else {\n\t\tstrscpy(buf1, argv[1], MAX_EVENT_NAME_LEN);\n\t\tsanitize_event_name(buf1);\n\t\tevent = buf1;\n\t}\n\tif (!is_good_name(event) || !is_good_name(group))\n\t\tgoto parse_error;\n\n\tsys_event = argv[1];\n\tret = traceprobe_parse_event_name(&sys_event, &sys_name, buf2,\n\t\t\t\t\t  sys_event - argv[1]);\n\tif (ret || !sys_name)\n\t\tgoto parse_error;\n\tif (!is_good_name(sys_event) || !is_good_name(sys_name))\n\t\tgoto parse_error;\n\n\tmutex_lock(&event_mutex);\n\tevent_call = find_and_get_event(sys_name, sys_event);\n\tep = alloc_event_probe(group, event, event_call, argc - 2);\n\tmutex_unlock(&event_mutex);\n\n\tif (IS_ERR(ep)) {\n\t\tret = PTR_ERR(ep);\n\t\t/* This must return -ENOMEM or missing event, else there is a bug */\n\t\tWARN_ON_ONCE(ret != -ENOMEM && ret != -ENODEV);\n\t\tep = NULL;\n\t\tgoto error;\n\t}\n\n\targc -= 2; argv += 2;\n\t/* parse arguments */\n\tfor (i = 0; i < argc && i < MAX_TRACE_ARGS; i++) {\n\t\ttrace_probe_log_set_index(i + 2);\n\t\tret = trace_eprobe_tp_update_arg(ep, argv, i);\n\t\tif (ret)\n\t\t\tgoto error;\n\t}\n\tret = traceprobe_set_print_fmt(&ep->tp, PROBE_PRINT_EVENT);\n\tif (ret < 0)\n\t\tgoto error;\n\tinit_trace_eprobe_call(ep);\n\tmutex_lock(&event_mutex);\n\tret = trace_probe_register_event_call(&ep->tp);\n\tif (ret) {\n\t\tif (ret == -EEXIST) {\n\t\t\ttrace_probe_log_set_index(0);\n\t\t\ttrace_probe_log_err(0, EVENT_EXIST);\n\t\t}\n\t\tmutex_unlock(&event_mutex);\n\t\tgoto error;\n\t}\n\tret = dyn_event_add(&ep->devent, &ep->tp.event->call);\n\tmutex_unlock(&event_mutex);\n\treturn ret;\nparse_error:\n\tret = -EINVAL;\nerror:\n\ttrace_event_probe_cleanup(ep);\n\treturn ret;\n}",
        "static void nv_gear_backoff_reseed(struct net_device *dev)\n{\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;\n\tu32 temp, seedset, combinedSeed;": "static void nv_gear_backoff_reseed(struct net_device *dev)\n{\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;\n\tu32 temp, seedset, combinedSeed;\n\tint i;\n\n\t/* Setup seed for free running LFSR */\n\t/* We are going to read the time stamp counter 3 times\n\t   and swizzle bits around to increase randomness */\n\tget_random_bytes(&miniseed1, sizeof(miniseed1));\n\tminiseed1 &= 0x0fff;\n\tif (miniseed1 == 0)\n\t\tminiseed1 = 0xabc;\n\n\tget_random_bytes(&miniseed2, sizeof(miniseed2));\n\tminiseed2 &= 0x0fff;\n\tif (miniseed2 == 0)\n\t\tminiseed2 = 0xabc;\n\tminiseed2_reversed =\n\t\t((miniseed2 & 0xF00) >> 8) |\n\t\t (miniseed2 & 0x0F0) |\n\t\t ((miniseed2 & 0x00F) << 8);\n\n\tget_random_bytes(&miniseed3, sizeof(miniseed3));\n\tminiseed3 &= 0x0fff;\n\tif (miniseed3 == 0)\n\t\tminiseed3 = 0xabc;\n\tminiseed3_reversed =\n\t\t((miniseed3 & 0xF00) >> 8) |\n\t\t (miniseed3 & 0x0F0) |\n\t\t ((miniseed3 & 0x00F) << 8);\n\n\tcombinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |\n\t\t       (miniseed2 ^ miniseed3_reversed);\n\n\t/* Seeds can not be zero */\n\tif ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)\n\t\tcombinedSeed |= 0x08;\n\tif ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)\n\t\tcombinedSeed |= 0x8000;\n\n\t/* No need to disable tx here */\n\ttemp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);\n\ttemp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;\n\ttemp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;\n\twritel(temp, base + NvRegBackOffControl);\n\n\t/* Setup seeds for all gear LFSRs. */\n\tget_random_bytes(&seedset, sizeof(seedset));\n\tseedset = seedset % BACKOFF_SEEDSET_ROWS;\n\tfor (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {\n\t\ttemp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);\n\t\ttemp |= main_seedset[seedset][i-1] & 0x3ff;\n\t\ttemp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);\n\t\twritel(temp, base + NvRegBackOffControl);\n\t}\n}",
        "static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)\n{\n\tstruct stb0899_internal *internal = &state->internal;\n\n\ts32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;": "static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)\n{\n\tstruct stb0899_internal *internal = &state->internal;\n\n\ts32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;\n\ts32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;\n\tu32 csm1, csm2, csm3, csm4;\n\n\tif (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {\n\t\tswitch (modcod) {\n\t\tcase STB0899_QPSK_12:\n\t\t\tgamma_acq\t\t= 25;\n\t\t\tgamma_rho_acq\t\t= 2700;\n\t\t\tgamma_trk\t\t= 12;\n\t\t\tgamma_rho_trk\t\t= 180;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_35:\n\t\t\tgamma_acq\t\t= 38;\n\t\t\tgamma_rho_acq\t\t= 7182;\n\t\t\tgamma_trk\t\t= 14;\n\t\t\tgamma_rho_trk\t\t= 308;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_23:\n\t\t\tgamma_acq\t\t= 42;\n\t\t\tgamma_rho_acq\t\t= 9408;\n\t\t\tgamma_trk\t\t= 17;\n\t\t\tgamma_rho_trk\t\t= 476;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_34:\n\t\t\tgamma_acq\t\t= 53;\n\t\t\tgamma_rho_acq\t\t= 16642;\n\t\t\tgamma_trk\t\t= 19;\n\t\t\tgamma_rho_trk\t\t= 646;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_45:\n\t\t\tgamma_acq\t\t= 53;\n\t\t\tgamma_rho_acq\t\t= 17119;\n\t\t\tgamma_trk\t\t= 22;\n\t\t\tgamma_rho_trk\t\t= 880;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_56:\n\t\t\tgamma_acq\t\t= 55;\n\t\t\tgamma_rho_acq\t\t= 19250;\n\t\t\tgamma_trk\t\t= 23;\n\t\t\tgamma_rho_trk\t\t= 989;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_89:\n\t\t\tgamma_acq\t\t= 60;\n\t\t\tgamma_rho_acq\t\t= 24240;\n\t\t\tgamma_trk\t\t= 24;\n\t\t\tgamma_rho_trk\t\t= 1176;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tcase STB0899_QPSK_910:\n\t\t\tgamma_acq\t\t= 66;\n\t\t\tgamma_rho_acq\t\t= 29634;\n\t\t\tgamma_trk\t\t= 24;\n\t\t\tgamma_rho_trk\t\t= 1176;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tgamma_acq\t\t= 66;\n\t\t\tgamma_rho_acq\t\t= 29634;\n\t\t\tgamma_trk\t\t= 24;\n\t\t\tgamma_rho_trk\t\t= 1176;\n\t\t\tlock_count_thr\t\t= 8;\n\t\t\tbreak;\n\t\t}\n\n\t\tcsm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);\n\t\tSTB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);\n\n\t\tcsm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);\n\t\tcsm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);\n\t\tcsm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);\n\t\tcsm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);\n\n\t\tSTB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);\n\t\tSTB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);\n\t\tSTB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);\n\t\tSTB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);\n\t\tSTB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);\n\t\tSTB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);\n\t\tSTB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);\n\t\tSTB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);\n\t\tSTB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);\n\t\tSTB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);\n\t\tSTB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);\n\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);\n\t}\n}",
        "static void io_wq_submit_work(struct io_wq_work *work)\n{\n\tstruct io_kiocb *req = container_of(work, struct io_kiocb, work);\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\tunsigned int issue_flags = IO_URING_F_UNLOCKED;": "static void io_wq_submit_work(struct io_wq_work *work)\n{\n\tstruct io_kiocb *req = container_of(work, struct io_kiocb, work);\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\tunsigned int issue_flags = IO_URING_F_UNLOCKED;\n\tbool needs_poll = false;\n\tint ret = 0, err = -ECANCELED;\n\n\t/* one will be dropped by ->io_free_work() after returning to io-wq */\n\tif (!(req->flags & REQ_F_REFCOUNT))\n\t\t__io_req_set_refcount(req, 2);\n\telse\n\t\treq_ref_get(req);\n\n\tio_arm_ltimeout(req);\n\n\t/* either cancelled or io-wq is dying, so don't touch tctx->iowq */\n\tif (work->flags & IO_WQ_WORK_CANCEL) {\nfail:\n\t\tio_req_task_queue_fail(req, err);\n\t\treturn;\n\t}\n\tif (!io_assign_file(req, issue_flags)) {\n\t\terr = -EBADF;\n\t\twork->flags |= IO_WQ_WORK_CANCEL;\n\t\tgoto fail;\n\t}\n\n\tif (req->flags & REQ_F_FORCE_ASYNC) {\n\t\tbool opcode_poll = def->pollin || def->pollout;\n\n\t\tif (opcode_poll && file_can_poll(req->file)) {\n\t\t\tneeds_poll = true;\n\t\t\tissue_flags |= IO_URING_F_NONBLOCK;\n\t\t}\n\t}\n\n\tdo {\n\t\tret = io_issue_sqe(req, issue_flags);\n\t\tif (ret != -EAGAIN)\n\t\t\tbreak;\n\t\t/*\n\t\t * We can get EAGAIN for iopolled IO even though we're\n\t\t * forcing a sync submission from here, since we can't\n\t\t * wait for request slots on the block side.\n\t\t */\n\t\tif (!needs_poll) {\n\t\t\tif (!(req->ctx->flags & IORING_SETUP_IOPOLL))\n\t\t\t\tbreak;\n\t\t\tcond_resched();\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (io_arm_poll_handler(req, issue_flags) == IO_APOLL_OK)\n\t\t\treturn;\n\t\t/* aborted or ready, in either case retry blocking */\n\t\tneeds_poll = false;\n\t\tissue_flags &= ~IO_URING_F_NONBLOCK;\n\t} while (1);\n\n\t/* avoid locking problems by failing it from a clean context */\n\tif (ret)\n\t\tio_req_task_queue_fail(req, ret);\n}",
        "static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno)\n{\n\tint rc, leafidx, lev;\n\ts64 b, lblkno;\n\tstruct dmapctl *dcp;": "static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno)\n{\n\tint rc, leafidx, lev;\n\ts64 b, lblkno;\n\tstruct dmapctl *dcp;\n\tint budmin;\n\tstruct metapage *mp;\n\n\t/* starting at the specified dmap control page level and block\n\t * number, search down the dmap control levels for the starting\n\t * block number of a dmap page that contains or starts off\n\t * sufficient free blocks.\n\t */\n\tfor (lev = level, b = *blkno; lev >= 0; lev--) {\n\t\t/* get the buffer of the dmap control page for the block\n\t\t * number and level (i.e. L0, L1, L2).\n\t\t */\n\t\tlblkno = BLKTOCTL(b, bmp->db_l2nbperpage, lev);\n\t\tmp = read_metapage(bmp->db_ipbmap, lblkno, PSIZE, 0);\n\t\tif (mp == NULL)\n\t\t\treturn -EIO;\n\t\tdcp = (struct dmapctl *) mp->data;\n\t\tbudmin = dcp->budmin;\n\n\t\tif (dcp->leafidx != cpu_to_le32(CTLLEAFIND)) {\n\t\t\tjfs_error(bmp->db_ipbmap->i_sb,\n\t\t\t\t  \"Corrupt dmapctl page\\n\");\n\t\t\trelease_metapage(mp);\n\t\t\treturn -EIO;\n\t\t}\n\n\t\t/* search the tree within the dmap control page for\n\t\t * sufficient free space.  if sufficient free space is found,\n\t\t * dbFindLeaf() returns the index of the leaf at which\n\t\t * free space was found.\n\t\t */\n\t\trc = dbFindLeaf((dmtree_t *) dcp, l2nb, &leafidx);\n\n\t\t/* release the buffer.\n\t\t */\n\t\trelease_metapage(mp);\n\n\t\t/* space found ?\n\t\t */\n\t\tif (rc) {\n\t\t\tif (lev != level) {\n\t\t\t\tjfs_error(bmp->db_ipbmap->i_sb,\n\t\t\t\t\t  \"dmap inconsistent\\n\");\n\t\t\t\treturn -EIO;\n\t\t\t}\n\t\t\treturn -ENOSPC;\n\t\t}\n\n\t\t/* adjust the block number to reflect the location within\n\t\t * the dmap control page (i.e. the leaf) at which free\n\t\t * space was found.\n\t\t */\n\t\tb += (((s64) leafidx) << budmin);\n\n\t\t/* we stop the search at this dmap control page level if\n\t\t * the number of blocks required is greater than or equal\n\t\t * to the maximum number of blocks described at the next\n\t\t * (lower) level.\n\t\t */\n\t\tif (l2nb >= budmin)\n\t\t\tbreak;\n\t}\n\n\t*blkno = b;\n\treturn (0);\n}",
        "static int get_strength(struct drxk_state *state, u64 *strength)\n{\n\tint status;\n\tstruct s_cfg_agc   rf_agc, if_agc;\n\tu32          total_gain  = 0;": "static int get_strength(struct drxk_state *state, u64 *strength)\n{\n\tint status;\n\tstruct s_cfg_agc   rf_agc, if_agc;\n\tu32          total_gain  = 0;\n\tu32          atten      = 0;\n\tu32          agc_range   = 0;\n\tu16            scu_lvl  = 0;\n\tu16            scu_coc  = 0;\n\t/* FIXME: those are part of the tuner presets */\n\tu16 tuner_rf_gain         = 50; /* Default value on az6007 driver */\n\tu16 tuner_if_gain         = 40; /* Default value on az6007 driver */\n\n\t*strength = 0;\n\n\tif (is_dvbt(state)) {\n\t\trf_agc = state->m_dvbt_rf_agc_cfg;\n\t\tif_agc = state->m_dvbt_if_agc_cfg;\n\t} else if (is_qam(state)) {\n\t\trf_agc = state->m_qam_rf_agc_cfg;\n\t\tif_agc = state->m_qam_if_agc_cfg;\n\t} else {\n\t\trf_agc = state->m_atv_rf_agc_cfg;\n\t\tif_agc = state->m_atv_if_agc_cfg;\n\t}\n\n\tif (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {\n\t\t/* SCU output_level */\n\t\tstatus = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);\n\t\tif (status < 0)\n\t\t\treturn status;\n\n\t\t/* SCU c.o.c. */\n\t\tstatus = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);\n\t\tif (status < 0)\n\t\t\treturn status;\n\n\t\tif (((u32) scu_lvl + (u32) scu_coc) < 0xffff)\n\t\t\trf_agc.output_level = scu_lvl + scu_coc;\n\t\telse\n\t\t\trf_agc.output_level = 0xffff;\n\n\t\t/* Take RF gain into account */\n\t\ttotal_gain += tuner_rf_gain;\n\n\t\t/* clip output value */\n\t\tif (rf_agc.output_level < rf_agc.min_output_level)\n\t\t\trf_agc.output_level = rf_agc.min_output_level;\n\t\tif (rf_agc.output_level > rf_agc.max_output_level)\n\t\t\trf_agc.output_level = rf_agc.max_output_level;\n\n\t\tagc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);\n\t\tif (agc_range > 0) {\n\t\t\tatten += 100UL *\n\t\t\t\t((u32)(tuner_rf_gain)) *\n\t\t\t\t((u32)(rf_agc.output_level - rf_agc.min_output_level))\n\t\t\t\t/ agc_range;\n\t\t}\n\t}\n\n\tif (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {\n\t\tstatus = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,\n\t\t\t\t&if_agc.output_level);\n\t\tif (status < 0)\n\t\t\treturn status;\n\n\t\tstatus = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,\n\t\t\t\t&if_agc.top);\n\t\tif (status < 0)\n\t\t\treturn status;\n\n\t\t/* Take IF gain into account */\n\t\ttotal_gain += (u32) tuner_if_gain;\n\n\t\t/* clip output value */\n\t\tif (if_agc.output_level < if_agc.min_output_level)\n\t\t\tif_agc.output_level = if_agc.min_output_level;\n\t\tif (if_agc.output_level > if_agc.max_output_level)\n\t\t\tif_agc.output_level = if_agc.max_output_level;\n\n\t\tagc_range  = (u32)(if_agc.max_output_level - if_agc.min_output_level);\n\t\tif (agc_range > 0) {\n\t\t\tatten += 100UL *\n\t\t\t\t((u32)(tuner_if_gain)) *\n\t\t\t\t((u32)(if_agc.output_level - if_agc.min_output_level))\n\t\t\t\t/ agc_range;\n\t\t}\n\t}\n\n\t/*\n\t * Convert to 0..65535 scale.\n\t * If it can't be measured (AGC is disabled), just show 100%.\n\t */\n\tif (total_gain > 0)\n\t\t*strength = (65535UL * atten / total_gain / 100);\n\telse\n\t\t*strength = 65535;\n\n\treturn 0;\n}",
        "static void *raid5_takeover(struct mddev *mddev)\n{\n\t/* raid5 can take over:\n\t *  raid0 - if there is only one strip zone - make it a raid4 layout\n\t *  raid1 - if there are two drives.  We need to know the chunk size": "static void *raid5_takeover(struct mddev *mddev)\n{\n\t/* raid5 can take over:\n\t *  raid0 - if there is only one strip zone - make it a raid4 layout\n\t *  raid1 - if there are two drives.  We need to know the chunk size\n\t *  raid4 - trivial - just use a raid4 layout.\n\t *  raid6 - Providing it is a *_6 layout\n\t */\n\tif (mddev->level == 0)\n\t\treturn raid45_takeover_raid0(mddev, 5);\n\tif (mddev->level == 1)\n\t\treturn raid5_takeover_raid1(mddev);\n\tif (mddev->level == 4) {\n\t\tmddev->new_layout = ALGORITHM_PARITY_N;\n\t\tmddev->new_level = 5;\n\t\treturn setup_conf(mddev);\n\t}\n\tif (mddev->level == 6)\n\t\treturn raid5_takeover_raid6(mddev);\n\n\treturn ERR_PTR(-EINVAL);\n}",
        "static void mptcp_pm_create_subflow_or_signal_addr(struct mptcp_sock *msk)\n{\n\tstruct sock *sk = (struct sock *)msk;\n\tstruct mptcp_pm_addr_entry *local;\n\tunsigned int add_addr_signal_max;": "static void mptcp_pm_create_subflow_or_signal_addr(struct mptcp_sock *msk)\n{\n\tstruct sock *sk = (struct sock *)msk;\n\tstruct mptcp_pm_addr_entry *local;\n\tunsigned int add_addr_signal_max;\n\tunsigned int local_addr_max;\n\tstruct pm_nl_pernet *pernet;\n\tunsigned int subflows_max;\n\n\tpernet = pm_nl_get_pernet(sock_net(sk));\n\n\tadd_addr_signal_max = mptcp_pm_get_add_addr_signal_max(msk);\n\tlocal_addr_max = mptcp_pm_get_local_addr_max(msk);\n\tsubflows_max = mptcp_pm_get_subflows_max(msk);\n\n\t/* do lazy endpoint usage accounting for the MPC subflows */\n\tif (unlikely(!(msk->pm.status & BIT(MPTCP_PM_MPC_ENDPOINT_ACCOUNTED))) && msk->first) {\n\t\tstruct mptcp_addr_info mpc_addr;\n\t\tint mpc_id;\n\n\t\tlocal_address((struct sock_common *)msk->first, &mpc_addr);\n\t\tmpc_id = lookup_id_by_addr(pernet, &mpc_addr);\n\t\tif (mpc_id >= 0)\n\t\t\t__clear_bit(mpc_id, msk->pm.id_avail_bitmap);\n\n\t\tmsk->pm.status |= BIT(MPTCP_PM_MPC_ENDPOINT_ACCOUNTED);\n\t}\n\n\tpr_debug(\"local %d:%d signal %d:%d subflows %d:%d\\n\",\n\t\t msk->pm.local_addr_used, local_addr_max,\n\t\t msk->pm.add_addr_signaled, add_addr_signal_max,\n\t\t msk->pm.subflows, subflows_max);\n\n\t/* check first for announce */\n\tif (msk->pm.add_addr_signaled < add_addr_signal_max) {\n\t\tlocal = select_signal_address(pernet, msk);\n\n\t\t/* due to racing events on both ends we can reach here while\n\t\t * previous add address is still running: if we invoke now\n\t\t * mptcp_pm_announce_addr(), that will fail and the\n\t\t * corresponding id will be marked as used.\n\t\t * Instead let the PM machinery reschedule us when the\n\t\t * current address announce will be completed.\n\t\t */\n\t\tif (msk->pm.addr_signal & BIT(MPTCP_ADD_ADDR_SIGNAL))\n\t\t\treturn;\n\n\t\tif (local) {\n\t\t\tif (mptcp_pm_alloc_anno_list(msk, local)) {\n\t\t\t\t__clear_bit(local->addr.id, msk->pm.id_avail_bitmap);\n\t\t\t\tmsk->pm.add_addr_signaled++;\n\t\t\t\tmptcp_pm_announce_addr(msk, &local->addr, false);\n\t\t\t\tmptcp_pm_nl_addr_send_ack(msk);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* check if should create a new subflow */\n\twhile (msk->pm.local_addr_used < local_addr_max &&\n\t       msk->pm.subflows < subflows_max) {\n\t\tstruct mptcp_addr_info addrs[MPTCP_PM_ADDR_MAX];\n\t\tbool fullmesh;\n\t\tint i, nr;\n\n\t\tlocal = select_local_address(pernet, msk);\n\t\tif (!local)\n\t\t\tbreak;\n\n\t\tfullmesh = !!(local->flags & MPTCP_PM_ADDR_FLAG_FULLMESH);\n\n\t\tmsk->pm.local_addr_used++;\n\t\tnr = fill_remote_addresses_vec(msk, fullmesh, addrs);\n\t\tif (nr)\n\t\t\t__clear_bit(local->addr.id, msk->pm.id_avail_bitmap);\n\t\tspin_unlock_bh(&msk->pm.lock);\n\t\tfor (i = 0; i < nr; i++)\n\t\t\t__mptcp_subflow_connect(sk, &local->addr, &addrs[i]);\n\t\tspin_lock_bh(&msk->pm.lock);\n\t}\n\tmptcp_pm_nl_check_work_pending(msk);\n}",
        "static void cpuset_hotplug_update_tasks(struct cpuset *cs, struct tmpmasks *tmp)\n{\n\tstatic cpumask_t new_cpus;\n\tstatic nodemask_t new_mems;\n\tbool cpus_updated;": "static void cpuset_hotplug_update_tasks(struct cpuset *cs, struct tmpmasks *tmp)\n{\n\tstatic cpumask_t new_cpus;\n\tstatic nodemask_t new_mems;\n\tbool cpus_updated;\n\tbool mems_updated;\n\tstruct cpuset *parent;\nretry:\n\twait_event(cpuset_attach_wq, cs->attach_in_progress == 0);\n\n\tpercpu_down_write(&cpuset_rwsem);\n\n\t/*\n\t * We have raced with task attaching. We wait until attaching\n\t * is finished, so we won't attach a task to an empty cpuset.\n\t */\n\tif (cs->attach_in_progress) {\n\t\tpercpu_up_write(&cpuset_rwsem);\n\t\tgoto retry;\n\t}\n\n\tparent = parent_cs(cs);\n\tcompute_effective_cpumask(&new_cpus, cs, parent);\n\tnodes_and(new_mems, cs->mems_allowed, parent->effective_mems);\n\n\tif (cs->nr_subparts_cpus)\n\t\t/*\n\t\t * Make sure that CPUs allocated to child partitions\n\t\t * do not show up in effective_cpus.\n\t\t */\n\t\tcpumask_andnot(&new_cpus, &new_cpus, cs->subparts_cpus);\n\n\tif (!tmp || !cs->partition_root_state)\n\t\tgoto update_tasks;\n\n\t/*\n\t * In the unlikely event that a partition root has empty\n\t * effective_cpus or its parent becomes erroneous, we have to\n\t * transition it to the erroneous state.\n\t */\n\tif (is_partition_root(cs) && (cpumask_empty(&new_cpus) ||\n\t   (parent->partition_root_state == PRS_ERROR))) {\n\t\tif (cs->nr_subparts_cpus) {\n\t\t\tspin_lock_irq(&callback_lock);\n\t\t\tcs->nr_subparts_cpus = 0;\n\t\t\tcpumask_clear(cs->subparts_cpus);\n\t\t\tspin_unlock_irq(&callback_lock);\n\t\t\tcompute_effective_cpumask(&new_cpus, cs, parent);\n\t\t}\n\n\t\t/*\n\t\t * If the effective_cpus is empty because the child\n\t\t * partitions take away all the CPUs, we can keep\n\t\t * the current partition and let the child partitions\n\t\t * fight for available CPUs.\n\t\t */\n\t\tif ((parent->partition_root_state == PRS_ERROR) ||\n\t\t     cpumask_empty(&new_cpus)) {\n\t\t\tint old_prs;\n\n\t\t\tupdate_parent_subparts_cpumask(cs, partcmd_disable,\n\t\t\t\t\t\t       NULL, tmp);\n\t\t\told_prs = cs->partition_root_state;\n\t\t\tif (old_prs != PRS_ERROR) {\n\t\t\t\tspin_lock_irq(&callback_lock);\n\t\t\t\tcs->partition_root_state = PRS_ERROR;\n\t\t\t\tspin_unlock_irq(&callback_lock);\n\t\t\t\tnotify_partition_change(cs, old_prs, PRS_ERROR);\n\t\t\t}\n\t\t}\n\t\tcpuset_force_rebuild();\n\t}\n\n\t/*\n\t * On the other hand, an erroneous partition root may be transitioned\n\t * back to a regular one or a partition root with no CPU allocated\n\t * from the parent may change to erroneous.\n\t */\n\tif (is_partition_root(parent) &&\n\t   ((cs->partition_root_state == PRS_ERROR) ||\n\t    !cpumask_intersects(&new_cpus, parent->subparts_cpus)) &&\n\t     update_parent_subparts_cpumask(cs, partcmd_update, NULL, tmp))\n\t\tcpuset_force_rebuild();\n\nupdate_tasks:\n\tcpus_updated = !cpumask_equal(&new_cpus, cs->effective_cpus);\n\tmems_updated = !nodes_equal(new_mems, cs->effective_mems);\n\n\tif (mems_updated)\n\t\tcheck_insane_mems_config(&new_mems);\n\n\tif (is_in_v2_mode())\n\t\thotplug_update_tasks(cs, &new_cpus, &new_mems,\n\t\t\t\t     cpus_updated, mems_updated);\n\telse\n\t\thotplug_update_tasks_legacy(cs, &new_cpus, &new_mems,\n\t\t\t\t\t    cpus_updated, mems_updated);\n\n\tpercpu_up_write(&cpuset_rwsem);\n}",
        "static int do_subskeleton(int argc, char **argv)\n{\n\tchar header_guard[MAX_OBJ_NAME_LEN + sizeof(\"__SUBSKEL_H__\")];\n\tsize_t i, len, file_sz, map_cnt = 0, prog_cnt = 0, mmap_sz, var_cnt = 0, var_idx = 0;\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, opts);": "static int do_subskeleton(int argc, char **argv)\n{\n\tchar header_guard[MAX_OBJ_NAME_LEN + sizeof(\"__SUBSKEL_H__\")];\n\tsize_t i, len, file_sz, map_cnt = 0, prog_cnt = 0, mmap_sz, var_cnt = 0, var_idx = 0;\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, opts);\n\tchar obj_name[MAX_OBJ_NAME_LEN] = \"\", *obj_data;\n\tstruct bpf_object *obj = NULL;\n\tconst char *file, *var_name;\n\tchar ident[256];\n\tint fd, err = -1, map_type_id;\n\tconst struct bpf_map *map;\n\tstruct bpf_program *prog;\n\tstruct btf *btf;\n\tconst struct btf_type *map_type, *var_type;\n\tconst struct btf_var_secinfo *var;\n\tstruct stat st;\n\n\tif (!REQ_ARGS(1)) {\n\t\tusage();\n\t\treturn -1;\n\t}\n\tfile = GET_ARG();\n\n\twhile (argc) {\n\t\tif (!REQ_ARGS(2))\n\t\t\treturn -1;\n\n\t\tif (is_prefix(*argv, \"name\")) {\n\t\t\tNEXT_ARG();\n\n\t\t\tif (obj_name[0] != '\\0') {\n\t\t\t\tp_err(\"object name already specified\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tstrncpy(obj_name, *argv, MAX_OBJ_NAME_LEN - 1);\n\t\t\tobj_name[MAX_OBJ_NAME_LEN - 1] = '\\0';\n\t\t} else {\n\t\t\tp_err(\"unknown arg %s\", *argv);\n\t\t\treturn -1;\n\t\t}\n\n\t\tNEXT_ARG();\n\t}\n\n\tif (argc) {\n\t\tp_err(\"extra unknown arguments\");\n\t\treturn -1;\n\t}\n\n\tif (use_loader) {\n\t\tp_err(\"cannot use loader for subskeletons\");\n\t\treturn -1;\n\t}\n\n\tif (stat(file, &st)) {\n\t\tp_err(\"failed to stat() %s: %s\", file, strerror(errno));\n\t\treturn -1;\n\t}\n\tfile_sz = st.st_size;\n\tmmap_sz = roundup(file_sz, sysconf(_SC_PAGE_SIZE));\n\tfd = open(file, O_RDONLY);\n\tif (fd < 0) {\n\t\tp_err(\"failed to open() %s: %s\", file, strerror(errno));\n\t\treturn -1;\n\t}\n\tobj_data = mmap(NULL, mmap_sz, PROT_READ, MAP_PRIVATE, fd, 0);\n\tif (obj_data == MAP_FAILED) {\n\t\tobj_data = NULL;\n\t\tp_err(\"failed to mmap() %s: %s\", file, strerror(errno));\n\t\tgoto out;\n\t}\n\tif (obj_name[0] == '\\0')\n\t\tget_obj_name(obj_name, file);\n\n\t/* The empty object name allows us to use bpf_map__name and produce\n\t * ELF section names out of it. (\".data\" instead of \"obj.data\")\n\t */\n\topts.object_name = \"\";\n\tobj = bpf_object__open_mem(obj_data, file_sz, &opts);\n\tif (!obj) {\n\t\tchar err_buf[256];\n\n\t\tlibbpf_strerror(errno, err_buf, sizeof(err_buf));\n\t\tp_err(\"failed to open BPF object file: %s\", err_buf);\n\t\tobj = NULL;\n\t\tgoto out;\n\t}\n\n\tbtf = bpf_object__btf(obj);\n\tif (!btf) {\n\t\terr = -1;\n\t\tp_err(\"need btf type information for %s\", obj_name);\n\t\tgoto out;\n\t}\n\n\tbpf_object__for_each_program(prog, obj) {\n\t\tprog_cnt++;\n\t}\n\n\t/* First, count how many variables we have to find.\n\t * We need this in advance so the subskel can allocate the right\n\t * amount of storage.\n\t */\n\tbpf_object__for_each_map(map, obj) {\n\t\tif (!get_map_ident(map, ident, sizeof(ident)))\n\t\t\tcontinue;\n\n\t\t/* Also count all maps that have a name */\n\t\tmap_cnt++;\n\n\t\tif (!is_internal_mmapable_map(map, ident, sizeof(ident)))\n\t\t\tcontinue;\n\n\t\tmap_type_id = bpf_map__btf_value_type_id(map);\n\t\tif (map_type_id <= 0) {\n\t\t\terr = map_type_id;\n\t\t\tgoto out;\n\t\t}\n\t\tmap_type = btf__type_by_id(btf, map_type_id);\n\n\t\tvar = btf_var_secinfos(map_type);\n\t\tlen = btf_vlen(map_type);\n\t\tfor (i = 0; i < len; i++, var++) {\n\t\t\tvar_type = btf__type_by_id(btf, var->type);\n\n\t\t\tif (btf_var(var_type)->linkage == BTF_VAR_STATIC)\n\t\t\t\tcontinue;\n\n\t\t\tvar_cnt++;\n\t\t}\n\t}\n\n\tget_header_guard(header_guard, obj_name, \"SUBSKEL_H\");\n\tcodegen(\"\\\n\t\\n\\\n\t/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t/* THIS FILE IS AUTOGENERATED! */\t\t\t\t    \\n\\\n\t#ifndef %2$s\t\t\t\t\t\t\t    \\n\\\n\t#define %2$s\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t#include <errno.h>\t\t\t\t\t\t    \\n\\\n\t#include <stdlib.h>\t\t\t\t\t\t    \\n\\\n\t#include <bpf/libbpf.h>\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\tstruct %1$s {\t\t\t\t\t\t\t    \\n\\\n\t\tstruct bpf_object *obj;\t\t\t\t\t    \\n\\\n\t\tstruct bpf_object_subskeleton *subskel;\t\t\t    \\n\\\n\t\", obj_name, header_guard);\n\n\tif (map_cnt) {\n\t\tprintf(\"\\tstruct {\\n\");\n\t\tbpf_object__for_each_map(map, obj) {\n\t\t\tif (!get_map_ident(map, ident, sizeof(ident)))\n\t\t\t\tcontinue;\n\t\t\tprintf(\"\\t\\tstruct bpf_map *%s;\\n\", ident);\n\t\t}\n\t\tprintf(\"\\t} maps;\\n\");\n\t}\n\n\tif (prog_cnt) {\n\t\tprintf(\"\\tstruct {\\n\");\n\t\tbpf_object__for_each_program(prog, obj) {\n\t\t\tprintf(\"\\t\\tstruct bpf_program *%s;\\n\",\n\t\t\t\tbpf_program__name(prog));\n\t\t}\n\t\tprintf(\"\\t} progs;\\n\");\n\t}\n\n\terr = codegen_subskel_datasecs(obj, obj_name);\n\tif (err)\n\t\tgoto out;\n\n\t/* emit code that will allocate enough storage for all symbols */\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#ifdef __cplusplus\t\t\t\t\t    \\n\\\n\t\t\tstatic inline struct %1$s *open(const struct bpf_object *src);\\n\\\n\t\t\tstatic inline void destroy(struct %1$s *skel);\t    \\n\\\n\t\t#endif /* __cplusplus */\t\t\t\t    \\n\\\n\t\t};\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline void\t\t\t\t\t    \\n\\\n\t\t%1$s__destroy(struct %1$s *skel)\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\tif (!skel)\t\t\t\t\t    \\n\\\n\t\t\t\treturn;\t\t\t\t\t    \\n\\\n\t\t\tif (skel->subskel)\t\t\t\t    \\n\\\n\t\t\t\tbpf_object__destroy_subskeleton(skel->subskel);\\n\\\n\t\t\tfree(skel);\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline struct %1$s *\t\t\t\t    \\n\\\n\t\t%1$s__open(const struct bpf_object *src)\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\tstruct %1$s *obj;\t\t\t\t    \\n\\\n\t\t\tstruct bpf_object_subskeleton *s;\t\t    \\n\\\n\t\t\tint err;\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\tobj = (struct %1$s *)calloc(1, sizeof(*obj));\t    \\n\\\n\t\t\tif (!obj) {\t\t\t\t\t    \\n\\\n\t\t\t\terr = -ENOMEM;\t\t\t\t    \\n\\\n\t\t\t\tgoto err;\t\t\t\t    \\n\\\n\t\t\t}\t\t\t\t\t\t    \\n\\\n\t\t\ts = (struct bpf_object_subskeleton *)calloc(1, sizeof(*s));\\n\\\n\t\t\tif (!s) {\t\t\t\t\t    \\n\\\n\t\t\t\terr = -ENOMEM;\t\t\t\t    \\n\\\n\t\t\t\tgoto err;\t\t\t\t    \\n\\\n\t\t\t}\t\t\t\t\t\t    \\n\\\n\t\t\ts->sz = sizeof(*s);\t\t\t\t    \\n\\\n\t\t\ts->obj = src;\t\t\t\t\t    \\n\\\n\t\t\ts->var_skel_sz = sizeof(*s->vars);\t\t    \\n\\\n\t\t\tobj->subskel = s;\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\t/* vars */\t\t\t\t\t    \\n\\\n\t\t\ts->var_cnt = %2$d;\t\t\t\t    \\n\\\n\t\t\ts->vars = (struct bpf_var_skeleton *)calloc(%2$d, sizeof(*s->vars));\\n\\\n\t\t\tif (!s->vars) {\t\t\t\t\t    \\n\\\n\t\t\t\terr = -ENOMEM;\t\t\t\t    \\n\\\n\t\t\t\tgoto err;\t\t\t\t    \\n\\\n\t\t\t}\t\t\t\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name, var_cnt\n\t);\n\n\t/* walk through each symbol and emit the runtime representation */\n\tbpf_object__for_each_map(map, obj) {\n\t\tif (!is_internal_mmapable_map(map, ident, sizeof(ident)))\n\t\t\tcontinue;\n\n\t\tmap_type_id = bpf_map__btf_value_type_id(map);\n\t\tif (map_type_id <= 0)\n\t\t\t/* skip over internal maps with no type*/\n\t\t\tcontinue;\n\n\t\tmap_type = btf__type_by_id(btf, map_type_id);\n\t\tvar = btf_var_secinfos(map_type);\n\t\tlen = btf_vlen(map_type);\n\t\tfor (i = 0; i < len; i++, var++) {\n\t\t\tvar_type = btf__type_by_id(btf, var->type);\n\t\t\tvar_name = btf__name_by_offset(btf, var_type->name_off);\n\n\t\t\tif (btf_var(var_type)->linkage == BTF_VAR_STATIC)\n\t\t\t\tcontinue;\n\n\t\t\t/* Note that we use the dot prefix in .data as the\n\t\t\t * field access operator i.e. maps%s becomes maps.data\n\t\t\t */\n\t\t\tcodegen(\"\\\n\t\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\t\ts->vars[%3$d].name = \\\"%1$s\\\";\t\t    \\n\\\n\t\t\t\ts->vars[%3$d].map = &obj->maps.%2$s;\t    \\n\\\n\t\t\t\ts->vars[%3$d].addr = (void **) &obj->%2$s.%1$s;\\n\\\n\t\t\t\", var_name, ident, var_idx);\n\n\t\t\tvar_idx++;\n\t\t}\n\t}\n\n\tcodegen_maps_skeleton(obj, map_cnt, false /*mmaped*/);\n\tcodegen_progs_skeleton(obj, prog_cnt, false /*links*/);\n\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\terr = bpf_object__open_subskeleton(s);\t\t    \\n\\\n\t\t\tif (err)\t\t\t\t\t    \\n\\\n\t\t\t\tgoto err;\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\treturn obj;\t\t\t\t\t    \\n\\\n\t\terr:\t\t\t\t\t\t\t    \\n\\\n\t\t\t%1$s__destroy(obj);\t\t\t\t    \\n\\\n\t\t\terrno = -err;\t\t\t\t\t    \\n\\\n\t\t\treturn NULL;\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#ifdef __cplusplus\t\t\t\t\t    \\n\\\n\t\tstruct %1$s *%1$s::open(const struct bpf_object *src) { return %1$s__open(src); }\\n\\\n\t\tvoid %1$s::destroy(struct %1$s *skel) { %1$s__destroy(skel); }\\n\\\n\t\t#endif /* __cplusplus */\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#endif /* %2$s */\t\t\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name, header_guard);\n\terr = 0;\nout:\n\tbpf_object__close(obj);\n\tif (obj_data)\n\t\tmunmap(obj_data, mmap_sz);\n\tclose(fd);\n\treturn err;\n}",
        "static int receive_pkts(struct ifobject *ifobj, struct pollfd *fds)\n{\n\tstruct timeval tv_end, tv_now, tv_timeout = {RECV_TMOUT, 0};\n\tu32 idx_rx = 0, idx_fq = 0, rcvd, i, pkts_sent = 0;\n\tstruct pkt_stream *pkt_stream = ifobj->pkt_stream;": "static int receive_pkts(struct ifobject *ifobj, struct pollfd *fds)\n{\n\tstruct timeval tv_end, tv_now, tv_timeout = {RECV_TMOUT, 0};\n\tu32 idx_rx = 0, idx_fq = 0, rcvd, i, pkts_sent = 0;\n\tstruct pkt_stream *pkt_stream = ifobj->pkt_stream;\n\tstruct xsk_socket_info *xsk = ifobj->xsk;\n\tstruct xsk_umem_info *umem = xsk->umem;\n\tstruct pkt *pkt;\n\tint ret;\n\n\tret = gettimeofday(&tv_now, NULL);\n\tif (ret)\n\t\texit_with_error(errno);\n\ttimeradd(&tv_now, &tv_timeout, &tv_end);\n\n\tpkt = pkt_stream_get_next_rx_pkt(pkt_stream, &pkts_sent);\n\twhile (pkt) {\n\t\tret = gettimeofday(&tv_now, NULL);\n\t\tif (ret)\n\t\t\texit_with_error(errno);\n\t\tif (timercmp(&tv_now, &tv_end, >)) {\n\t\t\tksft_print_msg(\"ERROR: [%s] Receive loop timed out\\n\", __func__);\n\t\t\treturn TEST_FAILURE;\n\t\t}\n\n\t\tkick_rx(xsk);\n\n\t\trcvd = xsk_ring_cons__peek(&xsk->rx, BATCH_SIZE, &idx_rx);\n\t\tif (!rcvd) {\n\t\t\tif (xsk_ring_prod__needs_wakeup(&umem->fq)) {\n\t\t\t\tret = poll(fds, 1, POLL_TMOUT);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\texit_with_error(-ret);\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (ifobj->use_fill_ring) {\n\t\t\tret = xsk_ring_prod__reserve(&umem->fq, rcvd, &idx_fq);\n\t\t\twhile (ret != rcvd) {\n\t\t\t\tif (ret < 0)\n\t\t\t\t\texit_with_error(-ret);\n\t\t\t\tif (xsk_ring_prod__needs_wakeup(&umem->fq)) {\n\t\t\t\t\tret = poll(fds, 1, POLL_TMOUT);\n\t\t\t\t\tif (ret < 0)\n\t\t\t\t\t\texit_with_error(-ret);\n\t\t\t\t}\n\t\t\t\tret = xsk_ring_prod__reserve(&umem->fq, rcvd, &idx_fq);\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < rcvd; i++) {\n\t\t\tconst struct xdp_desc *desc = xsk_ring_cons__rx_desc(&xsk->rx, idx_rx++);\n\t\t\tu64 addr = desc->addr, orig;\n\n\t\t\torig = xsk_umem__extract_addr(addr);\n\t\t\taddr = xsk_umem__add_offset_to_addr(addr);\n\n\t\t\tif (!is_pkt_valid(pkt, umem->buffer, addr, desc->len) ||\n\t\t\t    !is_offset_correct(umem, pkt_stream, addr, pkt->addr))\n\t\t\t\treturn TEST_FAILURE;\n\n\t\t\tif (ifobj->use_fill_ring)\n\t\t\t\t*xsk_ring_prod__fill_addr(&umem->fq, idx_fq++) = orig;\n\t\t\tpkt = pkt_stream_get_next_rx_pkt(pkt_stream, &pkts_sent);\n\t\t}\n\n\t\tif (ifobj->use_fill_ring)\n\t\t\txsk_ring_prod__submit(&umem->fq, rcvd);\n\t\tif (ifobj->release_rx)\n\t\t\txsk_ring_cons__release(&xsk->rx, rcvd);\n\n\t\tpthread_mutex_lock(&pacing_mutex);\n\t\tpkts_in_flight -= pkts_sent;\n\t\tif (pkts_in_flight < umem->num_frames)\n\t\t\tpthread_cond_signal(&pacing_cond);\n\t\tpthread_mutex_unlock(&pacing_mutex);\n\t\tpkts_sent = 0;\n\t}\n\n\treturn TEST_PASS;\n}",
        "static int apply_dir_move(struct send_ctx *sctx, struct pending_dir_move *pm)\n{\n\tstruct fs_path *from_path = NULL;\n\tstruct fs_path *to_path = NULL;\n\tstruct fs_path *name = NULL;": "static int apply_dir_move(struct send_ctx *sctx, struct pending_dir_move *pm)\n{\n\tstruct fs_path *from_path = NULL;\n\tstruct fs_path *to_path = NULL;\n\tstruct fs_path *name = NULL;\n\tu64 orig_progress = sctx->send_progress;\n\tstruct recorded_ref *cur;\n\tu64 parent_ino, parent_gen;\n\tstruct waiting_dir_move *dm = NULL;\n\tu64 rmdir_ino = 0;\n\tu64 rmdir_gen;\n\tu64 ancestor;\n\tbool is_orphan;\n\tint ret;\n\n\tname = fs_path_alloc();\n\tfrom_path = fs_path_alloc();\n\tif (!name || !from_path) {\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tdm = get_waiting_dir_move(sctx, pm->ino);\n\tASSERT(dm);\n\trmdir_ino = dm->rmdir_ino;\n\trmdir_gen = dm->rmdir_gen;\n\tis_orphan = dm->orphanized;\n\tfree_waiting_dir_move(sctx, dm);\n\n\tif (is_orphan) {\n\t\tret = gen_unique_name(sctx, pm->ino,\n\t\t\t\t      pm->gen, from_path);\n\t} else {\n\t\tret = get_first_ref(sctx->parent_root, pm->ino,\n\t\t\t\t    &parent_ino, &parent_gen, name);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tret = get_cur_path(sctx, parent_ino, parent_gen,\n\t\t\t\t   from_path);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tret = fs_path_add_path(from_path, name);\n\t}\n\tif (ret < 0)\n\t\tgoto out;\n\n\tsctx->send_progress = sctx->cur_ino + 1;\n\tret = path_loop(sctx, name, pm->ino, pm->gen, &ancestor);\n\tif (ret < 0)\n\t\tgoto out;\n\tif (ret) {\n\t\tLIST_HEAD(deleted_refs);\n\t\tASSERT(ancestor > BTRFS_FIRST_FREE_OBJECTID);\n\t\tret = add_pending_dir_move(sctx, pm->ino, pm->gen, ancestor,\n\t\t\t\t\t   &pm->update_refs, &deleted_refs,\n\t\t\t\t\t   is_orphan);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (rmdir_ino) {\n\t\t\tdm = get_waiting_dir_move(sctx, pm->ino);\n\t\t\tASSERT(dm);\n\t\t\tdm->rmdir_ino = rmdir_ino;\n\t\t\tdm->rmdir_gen = rmdir_gen;\n\t\t}\n\t\tgoto out;\n\t}\n\tfs_path_reset(name);\n\tto_path = name;\n\tname = NULL;\n\tret = get_cur_path(sctx, pm->ino, pm->gen, to_path);\n\tif (ret < 0)\n\t\tgoto out;\n\n\tret = send_rename(sctx, from_path, to_path);\n\tif (ret < 0)\n\t\tgoto out;\n\n\tif (rmdir_ino) {\n\t\tstruct orphan_dir_info *odi;\n\t\tu64 gen;\n\n\t\todi = get_orphan_dir_info(sctx, rmdir_ino, rmdir_gen);\n\t\tif (!odi) {\n\t\t\t/* already deleted */\n\t\t\tgoto finish;\n\t\t}\n\t\tgen = odi->gen;\n\n\t\tret = can_rmdir(sctx, rmdir_ino, gen, sctx->cur_ino);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (!ret)\n\t\t\tgoto finish;\n\n\t\tname = fs_path_alloc();\n\t\tif (!name) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out;\n\t\t}\n\t\tret = get_cur_path(sctx, rmdir_ino, gen, name);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tret = send_rmdir(sctx, name);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t}\n\nfinish:\n\tret = send_utimes(sctx, pm->ino, pm->gen);\n\tif (ret < 0)\n\t\tgoto out;\n\n\t/*\n\t * After rename/move, need to update the utimes of both new parent(s)\n\t * and old parent(s).\n\t */\n\tlist_for_each_entry(cur, &pm->update_refs, list) {\n\t\t/*\n\t\t * The parent inode might have been deleted in the send snapshot\n\t\t */\n\t\tret = get_inode_info(sctx->send_root, cur->dir, NULL,\n\t\t\t\t     NULL, NULL, NULL, NULL, NULL);\n\t\tif (ret == -ENOENT) {\n\t\t\tret = 0;\n\t\t\tcontinue;\n\t\t}\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\n\t\tret = send_utimes(sctx, cur->dir, cur->dir_gen);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t}\n\nout:\n\tfs_path_free(name);\n\tfs_path_free(from_path);\n\tfs_path_free(to_path);\n\tsctx->send_progress = orig_progress;\n\n\treturn ret;\n}",
        "static struct sctp_ulpevent *sctp_intl_retrieve_first_uo(struct sctp_ulpq *ulpq)\n{\n\tstruct sctp_stream_in *csin, *sin = NULL;\n\tstruct sk_buff *first_frag = NULL;\n\tstruct sk_buff *last_frag = NULL;": "static struct sctp_ulpevent *sctp_intl_retrieve_first_uo(struct sctp_ulpq *ulpq)\n{\n\tstruct sctp_stream_in *csin, *sin = NULL;\n\tstruct sk_buff *first_frag = NULL;\n\tstruct sk_buff *last_frag = NULL;\n\tstruct sctp_ulpevent *retval;\n\tstruct sk_buff *pos;\n\t__u32 next_fsn = 0;\n\t__u16 sid = 0;\n\n\tskb_queue_walk(&ulpq->reasm_uo, pos) {\n\t\tstruct sctp_ulpevent *cevent = sctp_skb2event(pos);\n\n\t\tcsin = sctp_stream_in(&ulpq->asoc->stream, cevent->stream);\n\t\tif (csin->pd_mode_uo)\n\t\t\tcontinue;\n\n\t\tswitch (cevent->msg_flags & SCTP_DATA_FRAG_MASK) {\n\t\tcase SCTP_DATA_FIRST_FRAG:\n\t\t\tif (first_frag)\n\t\t\t\tgoto out;\n\t\t\tfirst_frag = pos;\n\t\t\tlast_frag = pos;\n\t\t\tnext_fsn = 0;\n\t\t\tsin = csin;\n\t\t\tsid = cevent->stream;\n\t\t\tsin->mid_uo = cevent->mid;\n\t\t\tbreak;\n\t\tcase SCTP_DATA_MIDDLE_FRAG:\n\t\t\tif (!first_frag)\n\t\t\t\tbreak;\n\t\t\tif (cevent->stream == sid &&\n\t\t\t    cevent->mid == sin->mid_uo &&\n\t\t\t    cevent->fsn == next_fsn) {\n\t\t\t\tnext_fsn++;\n\t\t\t\tlast_frag = pos;\n\t\t\t} else {\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase SCTP_DATA_LAST_FRAG:\n\t\t\tif (first_frag)\n\t\t\t\tgoto out;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!first_frag)\n\t\treturn NULL;\n\nout:\n\tretval = sctp_make_reassembled_event(ulpq->asoc->base.net,\n\t\t\t\t\t     &ulpq->reasm_uo, first_frag,\n\t\t\t\t\t     last_frag);\n\tif (retval) {\n\t\tsin->fsn_uo = next_fsn;\n\t\tsin->pd_mode_uo = 1;\n\t}\n\n\treturn retval;\n}",
        "static void rcu_torture_mem_dump_obj(void)\n{\n\tstruct rcu_head *rhp;\n\tstruct kmem_cache *kcp;\n\tstatic int z;": "static void rcu_torture_mem_dump_obj(void)\n{\n\tstruct rcu_head *rhp;\n\tstruct kmem_cache *kcp;\n\tstatic int z;\n\n\tkcp = kmem_cache_create(\"rcuscale\", 136, 8, SLAB_STORE_USER, NULL);\n\trhp = kmem_cache_alloc(kcp, GFP_KERNEL);\n\tpr_alert(\"mem_dump_obj() slab test: rcu_torture_stats = %px, &rhp = %px, rhp = %px, &z = %px\\n\", stats_task, &rhp, rhp, &z);\n\tpr_alert(\"mem_dump_obj(ZERO_SIZE_PTR):\");\n\tmem_dump_obj(ZERO_SIZE_PTR);\n\tpr_alert(\"mem_dump_obj(NULL):\");\n\tmem_dump_obj(NULL);\n\tpr_alert(\"mem_dump_obj(%px):\", &rhp);\n\tmem_dump_obj(&rhp);\n\tpr_alert(\"mem_dump_obj(%px):\", rhp);\n\tmem_dump_obj(rhp);\n\tpr_alert(\"mem_dump_obj(%px):\", &rhp->func);\n\tmem_dump_obj(&rhp->func);\n\tpr_alert(\"mem_dump_obj(%px):\", &z);\n\tmem_dump_obj(&z);\n\tkmem_cache_free(kcp, rhp);\n\tkmem_cache_destroy(kcp);\n\trhp = kmalloc(sizeof(*rhp), GFP_KERNEL);\n\tpr_alert(\"mem_dump_obj() kmalloc test: rcu_torture_stats = %px, &rhp = %px, rhp = %px\\n\", stats_task, &rhp, rhp);\n\tpr_alert(\"mem_dump_obj(kmalloc %px):\", rhp);\n\tmem_dump_obj(rhp);\n\tpr_alert(\"mem_dump_obj(kmalloc %px):\", &rhp->func);\n\tmem_dump_obj(&rhp->func);\n\tkfree(rhp);\n\trhp = vmalloc(4096);\n\tpr_alert(\"mem_dump_obj() vmalloc test: rcu_torture_stats = %px, &rhp = %px, rhp = %px\\n\", stats_task, &rhp, rhp);\n\tpr_alert(\"mem_dump_obj(vmalloc %px):\", rhp);\n\tmem_dump_obj(rhp);\n\tpr_alert(\"mem_dump_obj(vmalloc %px):\", &rhp->func);\n\tmem_dump_obj(&rhp->func);\n\tvfree(rhp);\n}",
        "static int mhz_setup(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    size_t len;\n    u8 *buf;": "static int mhz_setup(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    size_t len;\n    u8 *buf;\n    int rc;\n\n    /* Read the station address from the CIS.  It is stored as the last\n       (fourth) string in the Version 1 Version/ID tuple. */\n    if ((link->prod_id[3]) &&\n\t(cvt_ascii_address(dev, link->prod_id[3]) == 0))\n\t    return 0;\n\n    /* Workarounds for broken cards start here. */\n    /* Ugh -- the EM1144 card has two VERS_1 tuples!?! */\n    if (!pcmcia_loop_tuple(link, CISTPL_VERS_1, pcmcia_get_versmac, dev))\n\t    return 0;\n\n    /* Another possibility: for the EM3288, in a special tuple */\n    rc = -1;\n    len = pcmcia_get_tuple(link, 0x81, &buf);\n    if (buf && len >= 13) {\n\t    buf[12] = '\\0';\n\t    if (cvt_ascii_address(dev, buf) == 0)\n\t\t    rc = 0;\n    }\n    kfree(buf);\n\n    return rc;\n};\n\n/*======================================================================\n\n    Configuration stuff for the Motorola Mariner\n\n    mot_config() writes directly to the Mariner configuration\n    registers because the CIS is just bogus.\n\n======================================================================*/\n\nstatic void mot_config(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct smc_private *smc = netdev_priv(dev);\n    unsigned int ioaddr = dev->base_addr;\n    unsigned int iouart = link->resource[1]->start;\n\n    /* Set UART base address and force map with COR bit 1 */\n    writeb(iouart & 0xff,        smc->base + MOT_UART + CISREG_IOBASE_0);\n    writeb((iouart >> 8) & 0xff, smc->base + MOT_UART + CISREG_IOBASE_1);\n    writeb(MOT_NORMAL,           smc->base + MOT_UART + CISREG_COR);\n\n    /* Set SMC base address and force map with COR bit 1 */\n    writeb(ioaddr & 0xff,        smc->base + MOT_LAN + CISREG_IOBASE_0);\n    writeb((ioaddr >> 8) & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_1);\n    writeb(MOT_NORMAL,           smc->base + MOT_LAN + CISREG_COR);\n\n    /* Wait for things to settle down */\n    mdelay(100);\n}",
        "static void freeze_array(struct r10conf *conf, int extra)\n{\n\t/* stop syncio and normal IO and wait for everything to\n\t * go quiet.\n\t * We increment barrier and nr_waiting, and then": "static void freeze_array(struct r10conf *conf, int extra)\n{\n\t/* stop syncio and normal IO and wait for everything to\n\t * go quiet.\n\t * We increment barrier and nr_waiting, and then\n\t * wait until nr_pending match nr_queued+extra\n\t * This is called in the context of one normal IO request\n\t * that has failed. Thus any sync request that might be pending\n\t * will be blocked by nr_pending, and we need to wait for\n\t * pending IO requests to complete or be queued for re-try.\n\t * Thus the number queued (nr_queued) plus this request (extra)\n\t * must match the number of pending IOs (nr_pending) before\n\t * we continue.\n\t */\n\tspin_lock_irq(&conf->resync_lock);\n\tconf->array_freeze_pending++;\n\tconf->barrier++;\n\tconf->nr_waiting++;\n\twait_event_lock_irq_cmd(conf->wait_barrier,\n\t\t\t\tatomic_read(&conf->nr_pending) == conf->nr_queued+extra,\n\t\t\t\tconf->resync_lock,\n\t\t\t\tflush_pending_writes(conf));\n\n\tconf->array_freeze_pending--;\n\tspin_unlock_irq(&conf->resync_lock);\n}",
        "static void send_diff_opt(int fd, struct sockaddr_ll *daddr)\n{\n\tstatic char buf[MAX_HDR_LEN + PAYLOAD_LEN];\n\tstatic char extpkt1[sizeof(buf) + TCPOLEN_TSTAMP_APPA];\n\tstatic char extpkt2[sizeof(buf) + TCPOLEN_MAXSEG];": "static void send_diff_opt(int fd, struct sockaddr_ll *daddr)\n{\n\tstatic char buf[MAX_HDR_LEN + PAYLOAD_LEN];\n\tstatic char extpkt1[sizeof(buf) + TCPOLEN_TSTAMP_APPA];\n\tstatic char extpkt2[sizeof(buf) + TCPOLEN_MAXSEG];\n\tint extpkt1_size = total_hdr_len + PAYLOAD_LEN + TCPOLEN_TSTAMP_APPA;\n\tint extpkt2_size = total_hdr_len + PAYLOAD_LEN + TCPOLEN_MAXSEG;\n\n\tcreate_packet(buf, 0, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt1, buf, 0, 0);\n\twrite_packet(fd, extpkt1, extpkt1_size, daddr);\n\n\tcreate_packet(buf, PAYLOAD_LEN, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt1, buf, 0, 0);\n\twrite_packet(fd, extpkt1, extpkt1_size, daddr);\n\n\tcreate_packet(buf, PAYLOAD_LEN * 2, 0, PAYLOAD_LEN, 0);\n\ttcp_write_options(extpkt2 + MAX_HDR_LEN, TCPOPT_NOP, 0);\n\ttcp_write_options(extpkt2 + MAX_HDR_LEN + 1, TCPOPT_WINDOW, 0);\n\trecompute_packet(extpkt2, buf, TCPOLEN_WINDOW + 1);\n\twrite_packet(fd, extpkt2, extpkt2_size, daddr);\n}",
        "static void atmel_pmecc_get_sigma(struct atmel_pmecc_user *user)\n{\n\ts16 *lmu = user->lmu;\n\ts16 *si = user->si;\n\ts32 *mu = user->mu;": "static void atmel_pmecc_get_sigma(struct atmel_pmecc_user *user)\n{\n\ts16 *lmu = user->lmu;\n\ts16 *si = user->si;\n\ts32 *mu = user->mu;\n\ts32 *dmu = user->dmu;\n\ts32 *delta = user->delta;\n\tint degree = get_sectorsize(user) == 512 ? 13 : 14;\n\tint cw_len = BIT(degree) - 1;\n\tint strength = get_strength(user);\n\tint num = 2 * strength + 1;\n\ts16 *index_of = user->gf_tables->index_of;\n\ts16 *alpha_to = user->gf_tables->alpha_to;\n\tint i, j, k;\n\tu32 dmu_0_count, tmp;\n\ts16 *smu = user->smu;\n\n\t/* index of largest delta */\n\tint ro;\n\tint largest;\n\tint diff;\n\n\tdmu_0_count = 0;\n\n\t/* First Row */\n\n\t/* Mu */\n\tmu[0] = -1;\n\n\tmemset(smu, 0, sizeof(s16) * num);\n\tsmu[0] = 1;\n\n\t/* discrepancy set to 1 */\n\tdmu[0] = 1;\n\t/* polynom order set to 0 */\n\tlmu[0] = 0;\n\tdelta[0] = (mu[0] * 2 - lmu[0]) >> 1;\n\n\t/* Second Row */\n\n\t/* Mu */\n\tmu[1] = 0;\n\t/* Sigma(x) set to 1 */\n\tmemset(&smu[num], 0, sizeof(s16) * num);\n\tsmu[num] = 1;\n\n\t/* discrepancy set to S1 */\n\tdmu[1] = si[1];\n\n\t/* polynom order set to 0 */\n\tlmu[1] = 0;\n\n\tdelta[1] = (mu[1] * 2 - lmu[1]) >> 1;\n\n\t/* Init the Sigma(x) last row */\n\tmemset(&smu[(strength + 1) * num], 0, sizeof(s16) * num);\n\n\tfor (i = 1; i <= strength; i++) {\n\t\tmu[i + 1] = i << 1;\n\t\t/* Begin Computing Sigma (Mu+1) and L(mu) */\n\t\t/* check if discrepancy is set to 0 */\n\t\tif (dmu[i] == 0) {\n\t\t\tdmu_0_count++;\n\n\t\t\ttmp = ((strength - (lmu[i] >> 1) - 1) / 2);\n\t\t\tif ((strength - (lmu[i] >> 1) - 1) & 0x1)\n\t\t\t\ttmp += 2;\n\t\t\telse\n\t\t\t\ttmp += 1;\n\n\t\t\tif (dmu_0_count == tmp) {\n\t\t\t\tfor (j = 0; j <= (lmu[i] >> 1) + 1; j++)\n\t\t\t\t\tsmu[(strength + 1) * num + j] =\n\t\t\t\t\t\t\tsmu[i * num + j];\n\n\t\t\t\tlmu[strength + 1] = lmu[i];\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\t/* copy polynom */\n\t\t\tfor (j = 0; j <= lmu[i] >> 1; j++)\n\t\t\t\tsmu[(i + 1) * num + j] = smu[i * num + j];\n\n\t\t\t/* copy previous polynom order to the next */\n\t\t\tlmu[i + 1] = lmu[i];\n\t\t} else {\n\t\t\tro = 0;\n\t\t\tlargest = -1;\n\t\t\t/* find largest delta with dmu != 0 */\n\t\t\tfor (j = 0; j < i; j++) {\n\t\t\t\tif ((dmu[j]) && (delta[j] > largest)) {\n\t\t\t\t\tlargest = delta[j];\n\t\t\t\t\tro = j;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* compute difference */\n\t\t\tdiff = (mu[i] - mu[ro]);\n\n\t\t\t/* Compute degree of the new smu polynomial */\n\t\t\tif ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))\n\t\t\t\tlmu[i + 1] = lmu[i];\n\t\t\telse\n\t\t\t\tlmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;\n\n\t\t\t/* Init smu[i+1] with 0 */\n\t\t\tfor (k = 0; k < num; k++)\n\t\t\t\tsmu[(i + 1) * num + k] = 0;\n\n\t\t\t/* Compute smu[i+1] */\n\t\t\tfor (k = 0; k <= lmu[ro] >> 1; k++) {\n\t\t\t\ts16 a, b, c;\n\n\t\t\t\tif (!(smu[ro * num + k] && dmu[i]))\n\t\t\t\t\tcontinue;\n\n\t\t\t\ta = index_of[dmu[i]];\n\t\t\t\tb = index_of[dmu[ro]];\n\t\t\t\tc = index_of[smu[ro * num + k]];\n\t\t\t\ttmp = a + (cw_len - b) + c;\n\t\t\t\ta = alpha_to[tmp % cw_len];\n\t\t\t\tsmu[(i + 1) * num + (k + diff)] = a;\n\t\t\t}\n\n\t\t\tfor (k = 0; k <= lmu[i] >> 1; k++)\n\t\t\t\tsmu[(i + 1) * num + k] ^= smu[i * num + k];\n\t\t}\n\n\t\t/* End Computing Sigma (Mu+1) and L(mu) */\n\t\t/* In either case compute delta */\n\t\tdelta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;\n\n\t\t/* Do not compute discrepancy for the last iteration */\n\t\tif (i >= strength)\n\t\t\tcontinue;\n\n\t\tfor (k = 0; k <= (lmu[i + 1] >> 1); k++) {\n\t\t\ttmp = 2 * (i - 1);\n\t\t\tif (k == 0) {\n\t\t\t\tdmu[i + 1] = si[tmp + 3];\n\t\t\t} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {\n\t\t\t\ts16 a, b, c;\n\n\t\t\t\ta = index_of[smu[(i + 1) * num + k]];\n\t\t\t\tb = si[2 * (i - 1) + 3 - k];\n\t\t\t\tc = index_of[b];\n\t\t\t\ttmp = a + c;\n\t\t\t\ttmp %= cw_len;\n\t\t\t\tdmu[i + 1] = alpha_to[tmp] ^ dmu[i + 1];\n\t\t\t}\n\t\t}\n\t}\n}",
        "static void test_xdp_adjust_tail_grow2(void)\n{\n\tconst char *file = \"./test_xdp_adjust_tail_grow.o\";\n\tchar buf[4096]; /* avoid segfault: large buf to hold grow results */\n\tint tailroom = 320; /* SKB_DATA_ALIGN(sizeof(struct skb_shared_info))*/;": "static void test_xdp_adjust_tail_grow2(void)\n{\n\tconst char *file = \"./test_xdp_adjust_tail_grow.o\";\n\tchar buf[4096]; /* avoid segfault: large buf to hold grow results */\n\tint tailroom = 320; /* SKB_DATA_ALIGN(sizeof(struct skb_shared_info))*/;\n\tstruct bpf_object *obj;\n\tint err, cnt, i;\n\tint max_grow, prog_fd;\n\n\tLIBBPF_OPTS(bpf_test_run_opts, tattr,\n\t\t.repeat\t\t= 1,\n\t\t.data_in\t= &buf,\n\t\t.data_out\t= &buf,\n\t\t.data_size_in\t= 0, /* Per test */\n\t\t.data_size_out\t= 0, /* Per test */\n\t);\n\n\terr = bpf_prog_test_load(file, BPF_PROG_TYPE_XDP, &obj, &prog_fd);\n\tif (ASSERT_OK(err, \"test_xdp_adjust_tail_grow\"))\n\t\treturn;\n\n\t/* Test case-64 */\n\tmemset(buf, 1, sizeof(buf));\n\ttattr.data_size_in  =  64; /* Determine test case via pkt size */\n\ttattr.data_size_out = 128; /* Limit copy_size */\n\t/* Kernel side alloc packet memory area that is zero init */\n\terr = bpf_prog_test_run_opts(prog_fd, &tattr);\n\n\tASSERT_EQ(errno, ENOSPC, \"case-64 errno\"); /* Due limit copy_size in bpf_test_finish */\n\tASSERT_EQ(tattr.retval, XDP_TX, \"case-64 retval\");\n\tASSERT_EQ(tattr.data_size_out, 192, \"case-64 data_size_out\"); /* Expected grow size */\n\n\t/* Extra checks for data contents */\n\tASSERT_EQ(buf[0], 1, \"case-64-data buf[0]\"); /*  0-63  memset to 1 */\n\tASSERT_EQ(buf[63], 1, \"case-64-data buf[63]\");\n\tASSERT_EQ(buf[64], 0, \"case-64-data buf[64]\"); /* 64-127 memset to 0 */\n\tASSERT_EQ(buf[127], 0, \"case-64-data buf[127]\");\n\tASSERT_EQ(buf[128], 1, \"case-64-data buf[128]\"); /* 128-191 memset to 1 */\n\tASSERT_EQ(buf[191], 1, \"case-64-data buf[191]\");\n\n\t/* Test case-128 */\n\tmemset(buf, 2, sizeof(buf));\n\ttattr.data_size_in  = 128; /* Determine test case via pkt size */\n\ttattr.data_size_out = sizeof(buf);   /* Copy everything */\n\terr = bpf_prog_test_run_opts(prog_fd, &tattr);\n\n\tmax_grow = 4096 - XDP_PACKET_HEADROOM -\ttailroom; /* 3520 */\n\tASSERT_OK(err, \"case-128\");\n\tASSERT_EQ(tattr.retval, XDP_TX, \"case-128 retval\");\n\tASSERT_EQ(tattr.data_size_out, max_grow, \"case-128 data_size_out\"); /* Expect max grow */\n\n\t/* Extra checks for data content: Count grow size, will contain zeros */\n\tfor (i = 0, cnt = 0; i < sizeof(buf); i++) {\n\t\tif (buf[i] == 0)\n\t\t\tcnt++;\n\t}\n\tASSERT_EQ(cnt, max_grow - tattr.data_size_in, \"case-128-data cnt\"); /* Grow increase */\n\tASSERT_EQ(tattr.data_size_out, max_grow, \"case-128-data data_size_out\"); /* Total grow */\n\n\tbpf_object__close(obj);\n}",
        "static void mana_poll_tx_cq(struct mana_cq *cq)\n{\n\tstruct gdma_comp *completions = cq->gdma_comp_buf;\n\tstruct gdma_posted_wqe_info *wqe_info;\n\tunsigned int pkt_transmitted = 0;": "static void mana_poll_tx_cq(struct mana_cq *cq)\n{\n\tstruct gdma_comp *completions = cq->gdma_comp_buf;\n\tstruct gdma_posted_wqe_info *wqe_info;\n\tunsigned int pkt_transmitted = 0;\n\tunsigned int wqe_unit_cnt = 0;\n\tstruct mana_txq *txq = cq->txq;\n\tstruct mana_port_context *apc;\n\tstruct netdev_queue *net_txq;\n\tstruct gdma_queue *gdma_wq;\n\tunsigned int avail_space;\n\tstruct net_device *ndev;\n\tstruct sk_buff *skb;\n\tbool txq_stopped;\n\tint comp_read;\n\tint i;\n\n\tndev = txq->ndev;\n\tapc = netdev_priv(ndev);\n\n\tcomp_read = mana_gd_poll_cq(cq->gdma_cq, completions,\n\t\t\t\t    CQE_POLLING_BUFFER);\n\n\tif (comp_read < 1)\n\t\treturn;\n\n\tfor (i = 0; i < comp_read; i++) {\n\t\tstruct mana_tx_comp_oob *cqe_oob;\n\n\t\tif (WARN_ON_ONCE(!completions[i].is_sq))\n\t\t\treturn;\n\n\t\tcqe_oob = (struct mana_tx_comp_oob *)completions[i].cqe_data;\n\t\tif (WARN_ON_ONCE(cqe_oob->cqe_hdr.client_type !=\n\t\t\t\t MANA_CQE_COMPLETION))\n\t\t\treturn;\n\n\t\tswitch (cqe_oob->cqe_hdr.cqe_type) {\n\t\tcase CQE_TX_OKAY:\n\t\t\tbreak;\n\n\t\tcase CQE_TX_SA_DROP:\n\t\tcase CQE_TX_MTU_DROP:\n\t\tcase CQE_TX_INVALID_OOB:\n\t\tcase CQE_TX_INVALID_ETH_TYPE:\n\t\tcase CQE_TX_HDR_PROCESSING_ERROR:\n\t\tcase CQE_TX_VF_DISABLED:\n\t\tcase CQE_TX_VPORT_IDX_OUT_OF_RANGE:\n\t\tcase CQE_TX_VPORT_DISABLED:\n\t\tcase CQE_TX_VLAN_TAGGING_VIOLATION:\n\t\t\tWARN_ONCE(1, \"TX: CQE error %d: ignored.\\n\",\n\t\t\t\t  cqe_oob->cqe_hdr.cqe_type);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* If the CQE type is unexpected, log an error, assert,\n\t\t\t * and go through the error path.\n\t\t\t */\n\t\t\tWARN_ONCE(1, \"TX: Unexpected CQE type %d: HW BUG?\\n\",\n\t\t\t\t  cqe_oob->cqe_hdr.cqe_type);\n\t\t\treturn;\n\t\t}\n\n\t\tif (WARN_ON_ONCE(txq->gdma_txq_id != completions[i].wq_num))\n\t\t\treturn;\n\n\t\tskb = skb_dequeue(&txq->pending_skbs);\n\t\tif (WARN_ON_ONCE(!skb))\n\t\t\treturn;\n\n\t\twqe_info = (struct gdma_posted_wqe_info *)skb->cb;\n\t\twqe_unit_cnt += wqe_info->wqe_size_in_bu;\n\n\t\tmana_unmap_skb(skb, apc);\n\n\t\tnapi_consume_skb(skb, cq->budget);\n\n\t\tpkt_transmitted++;\n\t}\n\n\tif (WARN_ON_ONCE(wqe_unit_cnt == 0))\n\t\treturn;\n\n\tmana_move_wq_tail(txq->gdma_sq, wqe_unit_cnt);\n\n\tgdma_wq = txq->gdma_sq;\n\tavail_space = mana_gd_wq_avail_space(gdma_wq);\n\n\t/* Ensure tail updated before checking q stop */\n\tsmp_mb();\n\n\tnet_txq = txq->net_txq;\n\ttxq_stopped = netif_tx_queue_stopped(net_txq);\n\n\t/* Ensure checking txq_stopped before apc->port_is_up. */\n\tsmp_rmb();\n\n\tif (txq_stopped && apc->port_is_up && avail_space >= MAX_TX_WQE_SIZE) {\n\t\tnetif_tx_wake_queue(net_txq);\n\t\tapc->eth_stats.wake_queue++;\n\t}\n\n\tif (atomic_sub_return(pkt_transmitted, &txq->pending_sends) < 0)\n\t\tWARN_ON_ONCE(1);\n\n\tcq->work_done = pkt_transmitted;\n}",
        "static int calc_stack(const char *str, int *parens, int *preds, int *err)\n{\n\tbool is_pred = false;\n\tint nr_preds = 0;\n\tint open = 1; /* Count the expression as \"(E)\" */": "static int calc_stack(const char *str, int *parens, int *preds, int *err)\n{\n\tbool is_pred = false;\n\tint nr_preds = 0;\n\tint open = 1; /* Count the expression as \"(E)\" */\n\tint last_quote = 0;\n\tint max_open = 1;\n\tint quote = 0;\n\tint i;\n\n\t*err = 0;\n\n\tfor (i = 0; str[i]; i++) {\n\t\tif (isspace(str[i]))\n\t\t\tcontinue;\n\t\tif (quote) {\n\t\t\tif (str[i] == quote)\n\t\t\t       quote = 0;\n\t\t\tcontinue;\n\t\t}\n\n\t\tswitch (str[i]) {\n\t\tcase '\\'':\n\t\tcase '\"':\n\t\t\tquote = str[i];\n\t\t\tlast_quote = i;\n\t\t\tbreak;\n\t\tcase '|':\n\t\tcase '&':\n\t\t\tif (str[i+1] != str[i])\n\t\t\t\tbreak;\n\t\t\tis_pred = false;\n\t\t\tcontinue;\n\t\tcase '(':\n\t\t\tis_pred = false;\n\t\t\topen++;\n\t\t\tif (open > max_open)\n\t\t\t\tmax_open = open;\n\t\t\tcontinue;\n\t\tcase ')':\n\t\t\tis_pred = false;\n\t\t\tif (open == 1) {\n\t\t\t\t*err = i;\n\t\t\t\treturn TOO_MANY_CLOSE;\n\t\t\t}\n\t\t\topen--;\n\t\t\tcontinue;\n\t\t}\n\t\tif (!is_pred) {\n\t\t\tnr_preds++;\n\t\t\tis_pred = true;\n\t\t}\n\t}\n\n\tif (quote) {\n\t\t*err = last_quote;\n\t\treturn MISSING_QUOTE;\n\t}\n\n\tif (open != 1) {\n\t\tint level = open;\n\n\t\t/* find the bad open */\n\t\tfor (i--; i; i--) {\n\t\t\tif (quote) {\n\t\t\t\tif (str[i] == quote)\n\t\t\t\t\tquote = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tswitch (str[i]) {\n\t\t\tcase '(':\n\t\t\t\tif (level == open) {\n\t\t\t\t\t*err = i;\n\t\t\t\t\treturn TOO_MANY_OPEN;\n\t\t\t\t}\n\t\t\t\tlevel--;\n\t\t\t\tbreak;\n\t\t\tcase ')':\n\t\t\t\tlevel++;\n\t\t\t\tbreak;\n\t\t\tcase '\\'':\n\t\t\tcase '\"':\n\t\t\t\tquote = str[i];\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* First character is the '(' with missing ')' */\n\t\t*err = 0;\n\t\treturn TOO_MANY_OPEN;\n\t}\n\n\t/* Set the size of the required stacks */\n\t*parens = max_open;\n\t*preds = nr_preds;\n\treturn 0;\n}",
        "static int mlxreg_lc_enable_disable(struct mlxreg_lc *mlxreg_lc, bool action)\n{\n\tu32 regval;\n\tint err;\n": "static int mlxreg_lc_enable_disable(struct mlxreg_lc *mlxreg_lc, bool action)\n{\n\tu32 regval;\n\tint err;\n\n\t/*\n\t * Hardware holds the line card after powering on in the disabled state. Holding line card\n\t * in disabled state protects access to the line components, like FPGA and gearboxes.\n\t * Line card should be enabled in order to get it in operational state. Line card could be\n\t * disabled for moving it to non-operational state. Enabling line card does not affect the\n\t * line card which is already has been enabled. Disabling does not affect the disabled line\n\t * card.\n\t */\n\tmutex_lock(&mlxreg_lc->lock);\n\n\terr = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_ena, &regval);\n\tif (err)\n\t\tgoto regmap_read_fail;\n\n\tif (action)\n\t\tregval |= BIT(mlxreg_lc->data->slot - 1);\n\telse\n\t\tregval &= ~BIT(mlxreg_lc->data->slot - 1);\n\n\terr = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_ena, regval);\n\nregmap_read_fail:\n\tmutex_unlock(&mlxreg_lc->lock);\n\treturn err;\n}",
        "static int receive_sizes(struct drbd_connection *connection, struct packet_info *pi)\n{\n\tstruct drbd_peer_device *peer_device;\n\tstruct drbd_device *device;\n\tstruct p_sizes *p = pi->data;": "static int receive_sizes(struct drbd_connection *connection, struct packet_info *pi)\n{\n\tstruct drbd_peer_device *peer_device;\n\tstruct drbd_device *device;\n\tstruct p_sizes *p = pi->data;\n\tstruct o_qlim *o = (connection->agreed_features & DRBD_FF_WSAME) ? p->qlim : NULL;\n\tenum determine_dev_size dd = DS_UNCHANGED;\n\tsector_t p_size, p_usize, p_csize, my_usize;\n\tsector_t new_size, cur_size;\n\tint ldsc = 0; /* local disk size changed */\n\tenum dds_flags ddsf;\n\n\tpeer_device = conn_peer_device(connection, pi->vnr);\n\tif (!peer_device)\n\t\treturn config_unknown_volume(connection, pi);\n\tdevice = peer_device->device;\n\tcur_size = get_capacity(device->vdisk);\n\n\tp_size = be64_to_cpu(p->d_size);\n\tp_usize = be64_to_cpu(p->u_size);\n\tp_csize = be64_to_cpu(p->c_size);\n\n\t/* just store the peer's disk size for now.\n\t * we still need to figure out whether we accept that. */\n\tdevice->p_size = p_size;\n\n\tif (get_ldev(device)) {\n\t\trcu_read_lock();\n\t\tmy_usize = rcu_dereference(device->ldev->disk_conf)->disk_size;\n\t\trcu_read_unlock();\n\n\t\twarn_if_differ_considerably(device, \"lower level device sizes\",\n\t\t\t   p_size, drbd_get_max_capacity(device->ldev));\n\t\twarn_if_differ_considerably(device, \"user requested size\",\n\t\t\t\t\t    p_usize, my_usize);\n\n\t\t/* if this is the first connect, or an otherwise expected\n\t\t * param exchange, choose the minimum */\n\t\tif (device->state.conn == C_WF_REPORT_PARAMS)\n\t\t\tp_usize = min_not_zero(my_usize, p_usize);\n\n\t\t/* Never shrink a device with usable data during connect,\n\t\t * or \"attach\" on the peer.\n\t\t * But allow online shrinking if we are connected. */\n\t\tnew_size = drbd_new_dev_size(device, device->ldev, p_usize, 0);\n\t\tif (new_size < cur_size &&\n\t\t    device->state.disk >= D_OUTDATED &&\n\t\t    (device->state.conn < C_CONNECTED || device->state.pdsk == D_DISKLESS)) {\n\t\t\tdrbd_err(device, \"The peer's disk size is too small! (%llu < %llu sectors)\\n\",\n\t\t\t\t\t(unsigned long long)new_size, (unsigned long long)cur_size);\n\t\t\tconn_request_state(peer_device->connection, NS(conn, C_DISCONNECTING), CS_HARD);\n\t\t\tput_ldev(device);\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (my_usize != p_usize) {\n\t\t\tstruct disk_conf *old_disk_conf, *new_disk_conf = NULL;\n\n\t\t\tnew_disk_conf = kzalloc(sizeof(struct disk_conf), GFP_KERNEL);\n\t\t\tif (!new_disk_conf) {\n\t\t\t\tput_ldev(device);\n\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\n\t\t\tmutex_lock(&connection->resource->conf_update);\n\t\t\told_disk_conf = device->ldev->disk_conf;\n\t\t\t*new_disk_conf = *old_disk_conf;\n\t\t\tnew_disk_conf->disk_size = p_usize;\n\n\t\t\trcu_assign_pointer(device->ldev->disk_conf, new_disk_conf);\n\t\t\tmutex_unlock(&connection->resource->conf_update);\n\t\t\tkvfree_rcu(old_disk_conf);\n\n\t\t\tdrbd_info(device, \"Peer sets u_size to %lu sectors (old: %lu)\\n\",\n\t\t\t\t (unsigned long)p_usize, (unsigned long)my_usize);\n\t\t}\n\n\t\tput_ldev(device);\n\t}\n\n\tdevice->peer_max_bio_size = be32_to_cpu(p->max_bio_size);\n\t/* Leave drbd_reconsider_queue_parameters() before drbd_determine_dev_size().\n\t   In case we cleared the QUEUE_FLAG_DISCARD from our queue in\n\t   drbd_reconsider_queue_parameters(), we can be sure that after\n\t   drbd_determine_dev_size() no REQ_DISCARDs are in the queue. */\n\n\tddsf = be16_to_cpu(p->dds_flags);\n\tif (get_ldev(device)) {\n\t\tdrbd_reconsider_queue_parameters(device, device->ldev, o);\n\t\tdd = drbd_determine_dev_size(device, ddsf, NULL);\n\t\tput_ldev(device);\n\t\tif (dd == DS_ERROR)\n\t\t\treturn -EIO;\n\t\tdrbd_md_sync(device);\n\t} else {\n\t\t/*\n\t\t * I am diskless, need to accept the peer's *current* size.\n\t\t * I must NOT accept the peers backing disk size,\n\t\t * it may have been larger than mine all along...\n\t\t *\n\t\t * At this point, the peer knows more about my disk, or at\n\t\t * least about what we last agreed upon, than myself.\n\t\t * So if his c_size is less than his d_size, the most likely\n\t\t * reason is that *my* d_size was smaller last time we checked.\n\t\t *\n\t\t * However, if he sends a zero current size,\n\t\t * take his (user-capped or) backing disk size anyways.\n\t\t *\n\t\t * Unless of course he does not have a disk himself.\n\t\t * In which case we ignore this completely.\n\t\t */\n\t\tsector_t new_size = p_csize ?: p_usize ?: p_size;\n\t\tdrbd_reconsider_queue_parameters(device, NULL, o);\n\t\tif (new_size == 0) {\n\t\t\t/* Ignore, peer does not know nothing. */\n\t\t} else if (new_size == cur_size) {\n\t\t\t/* nothing to do */\n\t\t} else if (cur_size != 0 && p_size == 0) {\n\t\t\tdrbd_warn(device, \"Ignored diskless peer device size (peer:%llu != me:%llu sectors)!\\n\",\n\t\t\t\t\t(unsigned long long)new_size, (unsigned long long)cur_size);\n\t\t} else if (new_size < cur_size && device->state.role == R_PRIMARY) {\n\t\t\tdrbd_err(device, \"The peer's device size is too small! (%llu < %llu sectors); demote me first!\\n\",\n\t\t\t\t\t(unsigned long long)new_size, (unsigned long long)cur_size);\n\t\t\tconn_request_state(peer_device->connection, NS(conn, C_DISCONNECTING), CS_HARD);\n\t\t\treturn -EIO;\n\t\t} else {\n\t\t\t/* I believe the peer, if\n\t\t\t *  - I don't have a current size myself\n\t\t\t *  - we agree on the size anyways\n\t\t\t *  - I do have a current size, am Secondary,\n\t\t\t *    and he has the only disk\n\t\t\t *  - I do have a current size, am Primary,\n\t\t\t *    and he has the only disk,\n\t\t\t *    which is larger than my current size\n\t\t\t */\n\t\t\tdrbd_set_my_capacity(device, new_size);\n\t\t}\n\t}\n\n\tif (get_ldev(device)) {\n\t\tif (device->ldev->known_size != drbd_get_capacity(device->ldev->backing_bdev)) {\n\t\t\tdevice->ldev->known_size = drbd_get_capacity(device->ldev->backing_bdev);\n\t\t\tldsc = 1;\n\t\t}\n\n\t\tput_ldev(device);\n\t}\n\n\tif (device->state.conn > C_WF_REPORT_PARAMS) {\n\t\tif (be64_to_cpu(p->c_size) != get_capacity(device->vdisk) ||\n\t\t    ldsc) {\n\t\t\t/* we have different sizes, probably peer\n\t\t\t * needs to know my new size... */\n\t\t\tdrbd_send_sizes(peer_device, 0, ddsf);\n\t\t}\n\t\tif (test_and_clear_bit(RESIZE_PENDING, &device->flags) ||\n\t\t    (dd == DS_GREW && device->state.conn == C_CONNECTED)) {\n\t\t\tif (device->state.pdsk >= D_INCONSISTENT &&\n\t\t\t    device->state.disk >= D_INCONSISTENT) {\n\t\t\t\tif (ddsf & DDSF_NO_RESYNC)\n\t\t\t\t\tdrbd_info(device, \"Resync of new storage suppressed with --assume-clean\\n\");\n\t\t\t\telse\n\t\t\t\t\tresync_after_online_grow(device);\n\t\t\t} else\n\t\t\t\tset_bit(RESYNC_AFTER_NEG, &device->flags);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static int t7xx_dpmaif_tx_drb_buf_init(struct dpmaif_tx_queue *txq)\n{\n\tsize_t brb_skb_size, brb_pd_size;\n\n\tbrb_pd_size = DPMAIF_DRB_LIST_LEN * sizeof(struct dpmaif_drb);": "static int t7xx_dpmaif_tx_drb_buf_init(struct dpmaif_tx_queue *txq)\n{\n\tsize_t brb_skb_size, brb_pd_size;\n\n\tbrb_pd_size = DPMAIF_DRB_LIST_LEN * sizeof(struct dpmaif_drb);\n\tbrb_skb_size = DPMAIF_DRB_LIST_LEN * sizeof(struct dpmaif_drb_skb);\n\n\ttxq->drb_size_cnt = DPMAIF_DRB_LIST_LEN;\n\n\t/* For HW && AP SW */\n\ttxq->drb_base = dma_alloc_coherent(txq->dpmaif_ctrl->dev, brb_pd_size,\n\t\t\t\t\t   &txq->drb_bus_addr, GFP_KERNEL | __GFP_ZERO);\n\tif (!txq->drb_base)\n\t\treturn -ENOMEM;\n\n\t/* For AP SW to record the skb information */\n\ttxq->drb_skb_base = devm_kzalloc(txq->dpmaif_ctrl->dev, brb_skb_size, GFP_KERNEL);\n\tif (!txq->drb_skb_base) {\n\t\tdma_free_coherent(txq->dpmaif_ctrl->dev, brb_pd_size,\n\t\t\t\t  txq->drb_base, txq->drb_bus_addr);\n\t\treturn -ENOMEM;\n\t}\n\n\treturn 0;\n}",
        "static int avs_copier_create(struct avs_dev *adev, struct avs_path_module *mod)\n{\n\tstruct nhlt_acpi_table *nhlt = adev->nhlt;\n\tstruct avs_tplg_module *t = mod->template;\n\tstruct avs_copier_cfg *cfg;": "static int avs_copier_create(struct avs_dev *adev, struct avs_path_module *mod)\n{\n\tstruct nhlt_acpi_table *nhlt = adev->nhlt;\n\tstruct avs_tplg_module *t = mod->template;\n\tstruct avs_copier_cfg *cfg;\n\tstruct nhlt_specific_cfg *ep_blob;\n\tunion avs_connector_node_id node_id = {0};\n\tsize_t cfg_size, data_size = 0;\n\tvoid *data = NULL;\n\tu32 dma_type;\n\tint ret;\n\n\tdma_type = t->cfg_ext->copier.dma_type;\n\tnode_id.dma_type = dma_type;\n\n\tswitch (dma_type) {\n\t\tstruct avs_audio_format *fmt;\n\t\tint direction;\n\n\tcase AVS_DMA_I2S_LINK_OUTPUT:\n\tcase AVS_DMA_I2S_LINK_INPUT:\n\t\tif (avs_dma_type_is_input(dma_type))\n\t\t\tdirection = SNDRV_PCM_STREAM_CAPTURE;\n\t\telse\n\t\t\tdirection = SNDRV_PCM_STREAM_PLAYBACK;\n\n\t\tif (t->cfg_ext->copier.blob_fmt)\n\t\t\tfmt = t->cfg_ext->copier.blob_fmt;\n\t\telse if (direction == SNDRV_PCM_STREAM_CAPTURE)\n\t\t\tfmt = t->in_fmt;\n\t\telse\n\t\t\tfmt = t->cfg_ext->copier.out_fmt;\n\n\t\tep_blob = intel_nhlt_get_endpoint_blob(adev->dev,\n\t\t\tnhlt, t->cfg_ext->copier.vindex.i2s.instance,\n\t\t\tNHLT_LINK_SSP, fmt->valid_bit_depth, fmt->bit_depth,\n\t\t\tfmt->num_channels, fmt->sampling_freq, direction,\n\t\t\tNHLT_DEVICE_I2S);\n\t\tif (!ep_blob) {\n\t\t\tdev_err(adev->dev, \"no I2S ep_blob found\\n\");\n\t\t\treturn -ENOENT;\n\t\t}\n\n\t\tdata = ep_blob->caps;\n\t\tdata_size = ep_blob->size;\n\t\t/* I2S gateway's vindex is statically assigned in topology */\n\t\tnode_id.vindex = t->cfg_ext->copier.vindex.val;\n\n\t\tbreak;\n\n\tcase AVS_DMA_DMIC_LINK_INPUT:\n\t\tdirection = SNDRV_PCM_STREAM_CAPTURE;\n\n\t\tif (t->cfg_ext->copier.blob_fmt)\n\t\t\tfmt = t->cfg_ext->copier.blob_fmt;\n\t\telse\n\t\t\tfmt = t->in_fmt;\n\n\t\tep_blob = intel_nhlt_get_endpoint_blob(adev->dev, nhlt, 0,\n\t\t\t\tNHLT_LINK_DMIC, fmt->valid_bit_depth,\n\t\t\t\tfmt->bit_depth, fmt->num_channels,\n\t\t\t\tfmt->sampling_freq, direction, NHLT_DEVICE_DMIC);\n\t\tif (!ep_blob) {\n\t\t\tdev_err(adev->dev, \"no DMIC ep_blob found\\n\");\n\t\t\treturn -ENOENT;\n\t\t}\n\n\t\tdata = ep_blob->caps;\n\t\tdata_size = ep_blob->size;\n\t\t/* DMIC gateway's vindex is statically assigned in topology */\n\t\tnode_id.vindex = t->cfg_ext->copier.vindex.val;\n\n\t\tbreak;\n\n\tcase AVS_DMA_HDA_HOST_OUTPUT:\n\tcase AVS_DMA_HDA_HOST_INPUT:\n\t\t/* HOST gateway's vindex is dynamically assigned with DMA id */\n\t\tnode_id.vindex = mod->owner->owner->dma_id;\n\t\tbreak;\n\n\tcase AVS_DMA_HDA_LINK_OUTPUT:\n\tcase AVS_DMA_HDA_LINK_INPUT:\n\t\tnode_id.vindex = t->cfg_ext->copier.vindex.val |\n\t\t\t\t mod->owner->owner->dma_id;\n\t\tbreak;\n\n\tcase INVALID_OBJECT_ID:\n\tdefault:\n\t\tnode_id = INVALID_NODE_ID;\n\t\tbreak;\n\t}\n\n\tcfg_size = sizeof(*cfg) + data_size;\n\t/* Every config-BLOB contains gateway attributes. */\n\tif (data_size)\n\t\tcfg_size -= sizeof(cfg->gtw_cfg.config.attrs);\n\n\tcfg = kzalloc(cfg_size, GFP_KERNEL);\n\tif (!cfg)\n\t\treturn -ENOMEM;\n\n\tcfg->base.cpc = t->cfg_base->cpc;\n\tcfg->base.ibs = t->cfg_base->ibs;\n\tcfg->base.obs = t->cfg_base->obs;\n\tcfg->base.is_pages = t->cfg_base->is_pages;\n\tcfg->base.audio_fmt = *t->in_fmt;\n\tcfg->out_fmt = *t->cfg_ext->copier.out_fmt;\n\tcfg->feature_mask = t->cfg_ext->copier.feature_mask;\n\tcfg->gtw_cfg.node_id = node_id;\n\tcfg->gtw_cfg.dma_buffer_size = t->cfg_ext->copier.dma_buffer_size;\n\t/* config_length in DWORDs */\n\tcfg->gtw_cfg.config_length = DIV_ROUND_UP(data_size, 4);\n\tif (data)\n\t\tmemcpy(&cfg->gtw_cfg.config, data, data_size);\n\n\tmod->gtw_attrs = cfg->gtw_cfg.config.attrs;\n\n\tret = avs_dsp_init_module(adev, mod->module_id, mod->owner->instance_id,\n\t\t\t\t  t->core_id, t->domain, cfg, cfg_size,\n\t\t\t\t  &mod->instance_id);\n\tkfree(cfg);\n\treturn ret;\n}",
        "static long get_packet_txtime(struct sk_buff *skb, struct Qdisc *sch)\n{\n\tktime_t transmit_end_time, interval_end, interval_start, tcp_tstamp;\n\tstruct taprio_sched *q = qdisc_priv(sch);\n\tstruct sched_gate_list *sched, *admin;": "static long get_packet_txtime(struct sk_buff *skb, struct Qdisc *sch)\n{\n\tktime_t transmit_end_time, interval_end, interval_start, tcp_tstamp;\n\tstruct taprio_sched *q = qdisc_priv(sch);\n\tstruct sched_gate_list *sched, *admin;\n\tktime_t minimum_time, now, txtime;\n\tint len, packet_transmit_time;\n\tstruct sched_entry *entry;\n\tbool sched_changed;\n\n\tnow = taprio_get_time(q);\n\tminimum_time = ktime_add_ns(now, q->txtime_delay);\n\n\ttcp_tstamp = get_tcp_tstamp(q, skb);\n\tminimum_time = max_t(ktime_t, minimum_time, tcp_tstamp);\n\n\trcu_read_lock();\n\tadmin = rcu_dereference(q->admin_sched);\n\tsched = rcu_dereference(q->oper_sched);\n\tif (admin && ktime_after(minimum_time, admin->base_time))\n\t\tswitch_schedules(q, &admin, &sched);\n\n\t/* Until the schedule starts, all the queues are open */\n\tif (!sched || ktime_before(minimum_time, sched->base_time)) {\n\t\ttxtime = minimum_time;\n\t\tgoto done;\n\t}\n\n\tlen = qdisc_pkt_len(skb);\n\tpacket_transmit_time = length_to_duration(q, len);\n\n\tdo {\n\t\tsched_changed = false;\n\n\t\tentry = find_entry_to_transmit(skb, sch, sched, admin,\n\t\t\t\t\t       minimum_time,\n\t\t\t\t\t       &interval_start, &interval_end,\n\t\t\t\t\t       false);\n\t\tif (!entry) {\n\t\t\ttxtime = 0;\n\t\t\tgoto done;\n\t\t}\n\n\t\ttxtime = entry->next_txtime;\n\t\ttxtime = max_t(ktime_t, txtime, minimum_time);\n\t\ttxtime = max_t(ktime_t, txtime, interval_start);\n\n\t\tif (admin && admin != sched &&\n\t\t    ktime_after(txtime, admin->base_time)) {\n\t\t\tsched = admin;\n\t\t\tsched_changed = true;\n\t\t\tcontinue;\n\t\t}\n\n\t\ttransmit_end_time = ktime_add(txtime, packet_transmit_time);\n\t\tminimum_time = transmit_end_time;\n\n\t\t/* Update the txtime of current entry to the next time it's\n\t\t * interval starts.\n\t\t */\n\t\tif (ktime_after(transmit_end_time, interval_end))\n\t\t\tentry->next_txtime = ktime_add(interval_start, sched->cycle_time);\n\t} while (sched_changed || ktime_after(transmit_end_time, interval_end));\n\n\tentry->next_txtime = transmit_end_time;\n\ndone:\n\trcu_read_unlock();\n\treturn txtime;\n}",
        "static int raid10_start_reshape(struct mddev *mddev)\n{\n\t/* A 'reshape' has been requested. This commits\n\t * the various 'new' fields and sets MD_RECOVER_RESHAPE\n\t * This also checks if there are enough spares and adds them": "static int raid10_start_reshape(struct mddev *mddev)\n{\n\t/* A 'reshape' has been requested. This commits\n\t * the various 'new' fields and sets MD_RECOVER_RESHAPE\n\t * This also checks if there are enough spares and adds them\n\t * to the array.\n\t * We currently require enough spares to make the final\n\t * array non-degraded.  We also require that the difference\n\t * between old and new data_offset - on each device - is\n\t * enough that we never risk over-writing.\n\t */\n\n\tunsigned long before_length, after_length;\n\tsector_t min_offset_diff = 0;\n\tint first = 1;\n\tstruct geom new;\n\tstruct r10conf *conf = mddev->private;\n\tstruct md_rdev *rdev;\n\tint spares = 0;\n\tint ret;\n\n\tif (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery))\n\t\treturn -EBUSY;\n\n\tif (setup_geo(&new, mddev, geo_start) != conf->copies)\n\t\treturn -EINVAL;\n\n\tbefore_length = ((1 << conf->prev.chunk_shift) *\n\t\t\t conf->prev.far_copies);\n\tafter_length = ((1 << conf->geo.chunk_shift) *\n\t\t\tconf->geo.far_copies);\n\n\trdev_for_each(rdev, mddev) {\n\t\tif (!test_bit(In_sync, &rdev->flags)\n\t\t    && !test_bit(Faulty, &rdev->flags))\n\t\t\tspares++;\n\t\tif (rdev->raid_disk >= 0) {\n\t\t\tlong long diff = (rdev->new_data_offset\n\t\t\t\t\t  - rdev->data_offset);\n\t\t\tif (!mddev->reshape_backwards)\n\t\t\t\tdiff = -diff;\n\t\t\tif (diff < 0)\n\t\t\t\tdiff = 0;\n\t\t\tif (first || diff < min_offset_diff)\n\t\t\t\tmin_offset_diff = diff;\n\t\t\tfirst = 0;\n\t\t}\n\t}\n\n\tif (max(before_length, after_length) > min_offset_diff)\n\t\treturn -EINVAL;\n\n\tif (spares < mddev->delta_disks)\n\t\treturn -EINVAL;\n\n\tconf->offset_diff = min_offset_diff;\n\tspin_lock_irq(&conf->device_lock);\n\tif (conf->mirrors_new) {\n\t\tmemcpy(conf->mirrors_new, conf->mirrors,\n\t\t       sizeof(struct raid10_info)*conf->prev.raid_disks);\n\t\tsmp_mb();\n\t\tkfree(conf->mirrors_old);\n\t\tconf->mirrors_old = conf->mirrors;\n\t\tconf->mirrors = conf->mirrors_new;\n\t\tconf->mirrors_new = NULL;\n\t}\n\tsetup_geo(&conf->geo, mddev, geo_start);\n\tsmp_mb();\n\tif (mddev->reshape_backwards) {\n\t\tsector_t size = raid10_size(mddev, 0, 0);\n\t\tif (size < mddev->array_sectors) {\n\t\t\tspin_unlock_irq(&conf->device_lock);\n\t\t\tpr_warn(\"md/raid10:%s: array size must be reduce before number of disks\\n\",\n\t\t\t\tmdname(mddev));\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tmddev->resync_max_sectors = size;\n\t\tconf->reshape_progress = size;\n\t} else\n\t\tconf->reshape_progress = 0;\n\tconf->reshape_safe = conf->reshape_progress;\n\tspin_unlock_irq(&conf->device_lock);\n\n\tif (mddev->delta_disks && mddev->bitmap) {\n\t\tstruct mdp_superblock_1 *sb = NULL;\n\t\tsector_t oldsize, newsize;\n\n\t\toldsize = raid10_size(mddev, 0, 0);\n\t\tnewsize = raid10_size(mddev, 0, conf->geo.raid_disks);\n\n\t\tif (!mddev_is_clustered(mddev)) {\n\t\t\tret = md_bitmap_resize(mddev->bitmap, newsize, 0, 0);\n\t\t\tif (ret)\n\t\t\t\tgoto abort;\n\t\t\telse\n\t\t\t\tgoto out;\n\t\t}\n\n\t\trdev_for_each(rdev, mddev) {\n\t\t\tif (rdev->raid_disk > -1 &&\n\t\t\t    !test_bit(Faulty, &rdev->flags))\n\t\t\t\tsb = page_address(rdev->sb_page);\n\t\t}\n\n\t\t/*\n\t\t * some node is already performing reshape, and no need to\n\t\t * call md_bitmap_resize again since it should be called when\n\t\t * receiving BITMAP_RESIZE msg\n\t\t */\n\t\tif ((sb && (le32_to_cpu(sb->feature_map) &\n\t\t\t    MD_FEATURE_RESHAPE_ACTIVE)) || (oldsize == newsize))\n\t\t\tgoto out;\n\n\t\tret = md_bitmap_resize(mddev->bitmap, newsize, 0, 0);\n\t\tif (ret)\n\t\t\tgoto abort;\n\n\t\tret = md_cluster_ops->resize_bitmaps(mddev, newsize, oldsize);\n\t\tif (ret) {\n\t\t\tmd_bitmap_resize(mddev->bitmap, oldsize, 0, 0);\n\t\t\tgoto abort;\n\t\t}\n\t}\nout:\n\tif (mddev->delta_disks > 0) {\n\t\trdev_for_each(rdev, mddev)\n\t\t\tif (rdev->raid_disk < 0 &&\n\t\t\t    !test_bit(Faulty, &rdev->flags)) {\n\t\t\t\tif (raid10_add_disk(mddev, rdev) == 0) {\n\t\t\t\t\tif (rdev->raid_disk >=\n\t\t\t\t\t    conf->prev.raid_disks)\n\t\t\t\t\t\tset_bit(In_sync, &rdev->flags);\n\t\t\t\t\telse\n\t\t\t\t\t\trdev->recovery_offset = 0;\n\n\t\t\t\t\t/* Failure here is OK */\n\t\t\t\t\tsysfs_link_rdev(mddev, rdev);\n\t\t\t\t}\n\t\t\t} else if (rdev->raid_disk >= conf->prev.raid_disks\n\t\t\t\t   && !test_bit(Faulty, &rdev->flags)) {\n\t\t\t\t/* This is a spare that was manually added */\n\t\t\t\tset_bit(In_sync, &rdev->flags);\n\t\t\t}\n\t}\n\t/* When a reshape changes the number of devices,\n\t * ->degraded is measured against the larger of the\n\t * pre and  post numbers.\n\t */\n\tspin_lock_irq(&conf->device_lock);\n\tmddev->degraded = calc_degraded(conf);\n\tspin_unlock_irq(&conf->device_lock);\n\tmddev->raid_disks = conf->geo.raid_disks;\n\tmddev->reshape_position = conf->reshape_progress;\n\tset_bit(MD_SB_CHANGE_DEVS, &mddev->sb_flags);\n\n\tclear_bit(MD_RECOVERY_SYNC, &mddev->recovery);\n\tclear_bit(MD_RECOVERY_CHECK, &mddev->recovery);\n\tclear_bit(MD_RECOVERY_DONE, &mddev->recovery);\n\tset_bit(MD_RECOVERY_RESHAPE, &mddev->recovery);\n\tset_bit(MD_RECOVERY_RUNNING, &mddev->recovery);\n\n\tmddev->sync_thread = md_register_thread(md_do_sync, mddev,\n\t\t\t\t\t\t\"reshape\");\n\tif (!mddev->sync_thread) {\n\t\tret = -EAGAIN;\n\t\tgoto abort;\n\t}\n\tconf->reshape_checkpoint = jiffies;\n\tmd_wakeup_thread(mddev->sync_thread);\n\tmd_new_event();\n\treturn 0;\n\nabort:\n\tmddev->recovery = 0;\n\tspin_lock_irq(&conf->device_lock);\n\tconf->geo = conf->prev;\n\tmddev->raid_disks = conf->geo.raid_disks;\n\trdev_for_each(rdev, mddev)\n\t\trdev->new_data_offset = rdev->data_offset;\n\tsmp_wmb();\n\tconf->reshape_progress = MaxSector;\n\tconf->reshape_safe = MaxSector;\n\tmddev->reshape_position = MaxSector;\n\tspin_unlock_irq(&conf->device_lock);\n\treturn ret;\n}",
        "static int select_idle_cpu(struct task_struct *p, struct sched_domain *sd, bool has_idle_core, int target)\n{\n\tstruct cpumask *cpus = this_cpu_cpumask_var_ptr(select_idle_mask);\n\tint i, cpu, idle_cpu = -1, nr = INT_MAX;\n\tstruct rq *this_rq = this_rq();": "static int select_idle_cpu(struct task_struct *p, struct sched_domain *sd, bool has_idle_core, int target)\n{\n\tstruct cpumask *cpus = this_cpu_cpumask_var_ptr(select_idle_mask);\n\tint i, cpu, idle_cpu = -1, nr = INT_MAX;\n\tstruct rq *this_rq = this_rq();\n\tint this = smp_processor_id();\n\tstruct sched_domain *this_sd;\n\tu64 time = 0;\n\n\tthis_sd = rcu_dereference(*this_cpu_ptr(&sd_llc));\n\tif (!this_sd)\n\t\treturn -1;\n\n\tcpumask_and(cpus, sched_domain_span(sd), p->cpus_ptr);\n\n\tif (sched_feat(SIS_PROP) && !has_idle_core) {\n\t\tu64 avg_cost, avg_idle, span_avg;\n\t\tunsigned long now = jiffies;\n\n\t\t/*\n\t\t * If we're busy, the assumption that the last idle period\n\t\t * predicts the future is flawed; age away the remaining\n\t\t * predicted idle time.\n\t\t */\n\t\tif (unlikely(this_rq->wake_stamp < now)) {\n\t\t\twhile (this_rq->wake_stamp < now && this_rq->wake_avg_idle) {\n\t\t\t\tthis_rq->wake_stamp++;\n\t\t\t\tthis_rq->wake_avg_idle >>= 1;\n\t\t\t}\n\t\t}\n\n\t\tavg_idle = this_rq->wake_avg_idle;\n\t\tavg_cost = this_sd->avg_scan_cost + 1;\n\n\t\tspan_avg = sd->span_weight * avg_idle;\n\t\tif (span_avg > 4*avg_cost)\n\t\t\tnr = div_u64(span_avg, avg_cost);\n\t\telse\n\t\t\tnr = 4;\n\n\t\ttime = cpu_clock(this);\n\t}\n\n\tfor_each_cpu_wrap(cpu, cpus, target + 1) {\n\t\tif (has_idle_core) {\n\t\t\ti = select_idle_core(p, cpu, cpus, &idle_cpu);\n\t\t\tif ((unsigned int)i < nr_cpumask_bits)\n\t\t\t\treturn i;\n\n\t\t} else {\n\t\t\tif (!--nr)\n\t\t\t\treturn -1;\n\t\t\tidle_cpu = __select_idle_cpu(cpu, p);\n\t\t\tif ((unsigned int)idle_cpu < nr_cpumask_bits)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (has_idle_core)\n\t\tset_idle_cores(target, false);\n\n\tif (sched_feat(SIS_PROP) && !has_idle_core) {\n\t\ttime = cpu_clock(this) - time;\n\n\t\t/*\n\t\t * Account for the scan cost of wakeups against the average\n\t\t * idle time.\n\t\t */\n\t\tthis_rq->wake_avg_idle -= min(this_rq->wake_avg_idle, time);\n\n\t\tupdate_avg(&this_sd->avg_scan_cost, time);\n\t}\n\n\treturn idle_cpu;\n}",
        "static struct sock *mptcp_subflow_get_send(struct mptcp_sock *msk)\n{\n\tstruct subflow_send_info send_info[SSK_MODE_MAX];\n\tstruct mptcp_subflow_context *subflow;\n\tstruct sock *sk = (struct sock *)msk;": "static struct sock *mptcp_subflow_get_send(struct mptcp_sock *msk)\n{\n\tstruct subflow_send_info send_info[SSK_MODE_MAX];\n\tstruct mptcp_subflow_context *subflow;\n\tstruct sock *sk = (struct sock *)msk;\n\tu32 pace, burst, wmem;\n\tint i, nr_active = 0;\n\tstruct sock *ssk;\n\tu64 linger_time;\n\tlong tout = 0;\n\n\tsock_owned_by_me(sk);\n\n\tif (__mptcp_check_fallback(msk)) {\n\t\tif (!msk->first)\n\t\t\treturn NULL;\n\t\treturn sk_stream_memory_free(msk->first) ? msk->first : NULL;\n\t}\n\n\t/* re-use last subflow, if the burst allow that */\n\tif (msk->last_snd && msk->snd_burst > 0 &&\n\t    sk_stream_memory_free(msk->last_snd) &&\n\t    mptcp_subflow_active(mptcp_subflow_ctx(msk->last_snd))) {\n\t\tmptcp_set_timeout(sk);\n\t\treturn msk->last_snd;\n\t}\n\n\t/* pick the subflow with the lower wmem/wspace ratio */\n\tfor (i = 0; i < SSK_MODE_MAX; ++i) {\n\t\tsend_info[i].ssk = NULL;\n\t\tsend_info[i].linger_time = -1;\n\t}\n\n\tmptcp_for_each_subflow(msk, subflow) {\n\t\ttrace_mptcp_subflow_get_send(subflow);\n\t\tssk =  mptcp_subflow_tcp_sock(subflow);\n\t\tif (!mptcp_subflow_active(subflow))\n\t\t\tcontinue;\n\n\t\ttout = max(tout, mptcp_timeout_from_subflow(subflow));\n\t\tnr_active += !subflow->backup;\n\t\tpace = subflow->avg_pacing_rate;\n\t\tif (unlikely(!pace)) {\n\t\t\t/* init pacing rate from socket */\n\t\t\tsubflow->avg_pacing_rate = READ_ONCE(ssk->sk_pacing_rate);\n\t\t\tpace = subflow->avg_pacing_rate;\n\t\t\tif (!pace)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tlinger_time = div_u64((u64)READ_ONCE(ssk->sk_wmem_queued) << 32, pace);\n\t\tif (linger_time < send_info[subflow->backup].linger_time) {\n\t\t\tsend_info[subflow->backup].ssk = ssk;\n\t\t\tsend_info[subflow->backup].linger_time = linger_time;\n\t\t}\n\t}\n\t__mptcp_set_timeout(sk, tout);\n\n\t/* pick the best backup if no other subflow is active */\n\tif (!nr_active)\n\t\tsend_info[SSK_MODE_ACTIVE].ssk = send_info[SSK_MODE_BACKUP].ssk;\n\n\t/* According to the blest algorithm, to avoid HoL blocking for the\n\t * faster flow, we need to:\n\t * - estimate the faster flow linger time\n\t * - use the above to estimate the amount of byte transferred\n\t *   by the faster flow\n\t * - check that the amount of queued data is greter than the above,\n\t *   otherwise do not use the picked, slower, subflow\n\t * We select the subflow with the shorter estimated time to flush\n\t * the queued mem, which basically ensure the above. We just need\n\t * to check that subflow has a non empty cwin.\n\t */\n\tssk = send_info[SSK_MODE_ACTIVE].ssk;\n\tif (!ssk || !sk_stream_memory_free(ssk))\n\t\treturn NULL;\n\n\tburst = min_t(int, MPTCP_SEND_BURST_SIZE, mptcp_wnd_end(msk) - msk->snd_nxt);\n\twmem = READ_ONCE(ssk->sk_wmem_queued);\n\tif (!burst) {\n\t\tmsk->last_snd = NULL;\n\t\treturn ssk;\n\t}\n\n\tsubflow = mptcp_subflow_ctx(ssk);\n\tsubflow->avg_pacing_rate = div_u64((u64)subflow->avg_pacing_rate * wmem +\n\t\t\t\t\t   READ_ONCE(ssk->sk_pacing_rate) * burst,\n\t\t\t\t\t   burst + wmem);\n\tmsk->last_snd = ssk;\n\tmsk->snd_burst = burst;\n\treturn ssk;\n}",
        "static void l2_guest_code(struct svm_test_data *svm)\n{\n\t/* This code raises interrupt INTR_IRQ_NUMBER in the L1's LAPIC,\n\t * and since L1 didn't enable virtual interrupt masking,\n\t * L2 should receive it and not L1.": "static void l2_guest_code(struct svm_test_data *svm)\n{\n\t/* This code raises interrupt INTR_IRQ_NUMBER in the L1's LAPIC,\n\t * and since L1 didn't enable virtual interrupt masking,\n\t * L2 should receive it and not L1.\n\t *\n\t * L2 also has virtual interrupt 'VINTR_IRQ_NUMBER' pending in V_IRQ\n\t * so it should also receive it after the following 'sti'.\n\t */\n\tx2apic_write_reg(APIC_ICR,\n\t\tAPIC_DEST_SELF | APIC_INT_ASSERT | INTR_IRQ_NUMBER);\n\n\t__asm__ __volatile__(\n\t\t\"sti\\n\"\n\t\t\"nop\\n\"\n\t);\n\n\tGUEST_ASSERT(vintr_irq_called);\n\tGUEST_ASSERT(intr_irq_called);\n\n\t__asm__ __volatile__(\n\t\t\"vmcall\\n\"\n\t);\n}",
        "static int run_osnoise(void)\n{\n\tstruct osnoise_variables *osn_var = this_cpu_osn_var();\n\tu64 start, sample, last_sample;\n\tu64 last_int_count, int_count;": "static int run_osnoise(void)\n{\n\tstruct osnoise_variables *osn_var = this_cpu_osn_var();\n\tu64 start, sample, last_sample;\n\tu64 last_int_count, int_count;\n\ts64 noise = 0, max_noise = 0;\n\ts64 total, last_total = 0;\n\tstruct osnoise_sample s;\n\tunsigned int threshold;\n\tu64 runtime, stop_in;\n\tu64 sum_noise = 0;\n\tint hw_count = 0;\n\tint ret = -1;\n\n\t/*\n\t * Considers the current thread as the workload.\n\t */\n\tosn_var->pid = current->pid;\n\n\t/*\n\t * Save the current stats for the diff\n\t */\n\tsave_osn_sample_stats(osn_var, &s);\n\n\t/*\n\t * if threshold is 0, use the default value of 5 us.\n\t */\n\tthreshold = tracing_thresh ? : 5000;\n\n\t/*\n\t * Make sure NMIs see sampling first\n\t */\n\tosn_var->sampling = true;\n\tbarrier();\n\n\t/*\n\t * Transform the *_us config to nanoseconds to avoid the\n\t * division on the main loop.\n\t */\n\truntime = osnoise_data.sample_runtime * NSEC_PER_USEC;\n\tstop_in = osnoise_data.stop_tracing * NSEC_PER_USEC;\n\n\t/*\n\t * Start timestemp\n\t */\n\tstart = time_get();\n\n\t/*\n\t * \"previous\" loop.\n\t */\n\tlast_int_count = set_int_safe_time(osn_var, &last_sample);\n\n\tdo {\n\t\t/*\n\t\t * Get sample!\n\t\t */\n\t\tint_count = set_int_safe_time(osn_var, &sample);\n\n\t\tnoise = time_sub(sample, last_sample);\n\n\t\t/*\n\t\t * This shouldn't happen.\n\t\t */\n\t\tif (noise < 0) {\n\t\t\tosnoise_taint(\"negative noise!\");\n\t\t\tgoto out;\n\t\t}\n\n\t\t/*\n\t\t * Sample runtime.\n\t\t */\n\t\ttotal = time_sub(sample, start);\n\n\t\t/*\n\t\t * Check for possible overflows.\n\t\t */\n\t\tif (total < last_total) {\n\t\t\tosnoise_taint(\"total overflow!\");\n\t\t\tbreak;\n\t\t}\n\n\t\tlast_total = total;\n\n\t\tif (noise >= threshold) {\n\t\t\tint interference = int_count - last_int_count;\n\n\t\t\tif (noise > max_noise)\n\t\t\t\tmax_noise = noise;\n\n\t\t\tif (!interference)\n\t\t\t\thw_count++;\n\n\t\t\tsum_noise += noise;\n\n\t\t\ttrace_sample_threshold(last_sample, noise, interference);\n\n\t\t\tif (osnoise_data.stop_tracing)\n\t\t\t\tif (noise > stop_in)\n\t\t\t\t\tosnoise_stop_tracing();\n\t\t}\n\n\t\t/*\n\t\t * In some cases, notably when running on a nohz_full CPU with\n\t\t * a stopped tick PREEMPT_RCU has no way to account for QSs.\n\t\t * This will eventually cause unwarranted noise as PREEMPT_RCU\n\t\t * will force preemption as the means of ending the current\n\t\t * grace period. We avoid this problem by calling\n\t\t * rcu_momentary_dyntick_idle(), which performs a zero duration\n\t\t * EQS allowing PREEMPT_RCU to end the current grace period.\n\t\t * This call shouldn't be wrapped inside an RCU critical\n\t\t * section.\n\t\t *\n\t\t * Note that in non PREEMPT_RCU kernels QSs are handled through\n\t\t * cond_resched()\n\t\t */\n\t\tif (IS_ENABLED(CONFIG_PREEMPT_RCU)) {\n\t\t\tlocal_irq_disable();\n\t\t\trcu_momentary_dyntick_idle();\n\t\t\tlocal_irq_enable();\n\t\t}\n\n\t\t/*\n\t\t * For the non-preemptive kernel config: let threads runs, if\n\t\t * they so wish.\n\t\t */\n\t\tcond_resched();\n\n\t\tlast_sample = sample;\n\t\tlast_int_count = int_count;\n\n\t} while (total < runtime && !kthread_should_stop());\n\n\t/*\n\t * Finish the above in the view for interrupts.\n\t */\n\tbarrier();\n\n\tosn_var->sampling = false;\n\n\t/*\n\t * Make sure sampling data is no longer updated.\n\t */\n\tbarrier();\n\n\t/*\n\t * Save noise info.\n\t */\n\ts.noise = time_to_us(sum_noise);\n\ts.runtime = time_to_us(total);\n\ts.max_sample = time_to_us(max_noise);\n\ts.hw_count = hw_count;\n\n\t/* Save interference stats info */\n\tdiff_osn_sample_stats(osn_var, &s);\n\n\ttrace_osnoise_sample(&s);\n\n\tnotify_new_max_latency(max_noise);\n\n\tif (osnoise_data.stop_tracing_total)\n\t\tif (s.noise > osnoise_data.stop_tracing_total)\n\t\t\tosnoise_stop_tracing();\n\n\treturn 0;\nout:\n\treturn ret;\n}",
        "static void test_sethwdebug_exact(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info;\n\tunsigned long wp_addr = (unsigned long)&glvar;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG, MODE_EXACT\";": "static void test_sethwdebug_exact(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info;\n\tunsigned long wp_addr = (unsigned long)&glvar;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG, MODE_EXACT\";\n\tint len = 1; /* hardcoded in kernel */\n\tint wh;\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_EXACT, WO test */\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_WRITE, wp_addr, 0);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"WO\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_EXACT, RO test */\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_READ, wp_addr, 0);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RO\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_EXACT, RW test */\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_RW, wp_addr, 0);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RW\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n}",
        "static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)\n{\n\tunsigned int minor_rev;\n\n\t/*": "static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)\n{\n\tunsigned int minor_rev;\n\n\t/*\n\t * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts\n\t * should return 0x31 for sbrn, or that the minor revision\n\t * is a two digit BCD containig minor and sub-minor numbers.\n\t * This was later clarified in xHCI 1.2.\n\t *\n\t * Some USB 3.1 capable hosts therefore have sbrn 0x30, and\n\t * minor revision set to 0x1 instead of 0x10.\n\t */\n\tif (xhci->usb3_rhub.min_rev == 0x1)\n\t\tminor_rev = 1;\n\telse\n\t\tminor_rev = xhci->usb3_rhub.min_rev / 0x10;\n\n\tswitch (minor_rev) {\n\tcase 2:\n\t\thcd->speed = HCD_USB32;\n\t\thcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;\n\t\thcd->self.root_hub->rx_lanes = 2;\n\t\thcd->self.root_hub->tx_lanes = 2;\n\t\thcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;\n\t\tbreak;\n\tcase 1:\n\t\thcd->speed = HCD_USB31;\n\t\thcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;\n\t\thcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;\n\t\tbreak;\n\t}\n\txhci_info(xhci, \"Host supports USB 3.%x %sSuperSpeed\\n\",\n\t\t  minor_rev, minor_rev ? \"Enhanced \" : \"\");\n\n\txhci->usb3_rhub.hcd = hcd;\n}",
        "static int get_vdec_sig_decode_parameters(struct vdec_h264_slice_inst *inst)\n{\n\tconst struct v4l2_ctrl_h264_decode_params *dec_params;\n\tconst struct v4l2_ctrl_h264_sps *sps;\n\tconst struct v4l2_ctrl_h264_pps *pps;": "static int get_vdec_sig_decode_parameters(struct vdec_h264_slice_inst *inst)\n{\n\tconst struct v4l2_ctrl_h264_decode_params *dec_params;\n\tconst struct v4l2_ctrl_h264_sps *sps;\n\tconst struct v4l2_ctrl_h264_pps *pps;\n\tconst struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;\n\tstruct vdec_h264_slice_lat_dec_param *slice_param = &inst->h264_slice_param;\n\tstruct v4l2_h264_reflist_builder reflist_builder;\n\tstruct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN];\n\tstruct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN];\n\tstruct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN];\n\tu8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0;\n\tu8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0;\n\tu8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1;\n\n\tdec_params =\n\t\tmtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);\n\tif (IS_ERR(dec_params))\n\t\treturn PTR_ERR(dec_params);\n\n\tsps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS);\n\tif (IS_ERR(sps))\n\t\treturn PTR_ERR(sps);\n\n\tpps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);\n\tif (IS_ERR(pps))\n\t\treturn PTR_ERR(pps);\n\n\tscaling_matrix =\n\t\tmtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX);\n\tif (IS_ERR(scaling_matrix))\n\t\treturn PTR_ERR(scaling_matrix);\n\n\tmtk_vdec_h264_update_dpb(dec_params, inst->dpb);\n\n\tmtk_vdec_h264_copy_sps_params(&slice_param->sps, sps);\n\tmtk_vdec_h264_copy_pps_params(&slice_param->pps, pps);\n\tmtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix);\n\n\tmtk_vdec_h264_copy_decode_params(&slice_param->decode_params, dec_params, inst->dpb);\n\tmtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params,\n\t\t\t\t    slice_param->h264_dpb_info);\n\n\t/* Build the reference lists */\n\tv4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, inst->dpb);\n\tv4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist);\n\tv4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, v4l2_b1_reflist);\n\n\t/* Adapt the built lists to the firmware's expectations */\n\tmtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid);\n\tmtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid);\n\tmtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid);\n\n\tmemcpy(&inst->vsi_ctx.h264_slice_params, slice_param,\n\t       sizeof(inst->vsi_ctx.h264_slice_params));\n\n\treturn 0;\n}",
        "static void transfer_surpluses(struct list_head *surpluses, struct ioc_now *now)\n{\n\tLIST_HEAD(over_hwa);\n\tLIST_HEAD(inner_walk);\n\tstruct ioc_gq *iocg, *tiocg, *root_iocg;": "static void transfer_surpluses(struct list_head *surpluses, struct ioc_now *now)\n{\n\tLIST_HEAD(over_hwa);\n\tLIST_HEAD(inner_walk);\n\tstruct ioc_gq *iocg, *tiocg, *root_iocg;\n\tu32 after_sum, over_sum, over_target, gamma;\n\n\t/*\n\t * It's pretty unlikely but possible for the total sum of\n\t * hweight_after_donation's to be higher than WEIGHT_ONE, which will\n\t * confuse the following calculations. If such condition is detected,\n\t * scale down everyone over its full share equally to keep the sum below\n\t * WEIGHT_ONE.\n\t */\n\tafter_sum = 0;\n\tover_sum = 0;\n\tlist_for_each_entry(iocg, surpluses, surplus_list) {\n\t\tu32 hwa;\n\n\t\tcurrent_hweight(iocg, &hwa, NULL);\n\t\tafter_sum += iocg->hweight_after_donation;\n\n\t\tif (iocg->hweight_after_donation > hwa) {\n\t\t\tover_sum += iocg->hweight_after_donation;\n\t\t\tlist_add(&iocg->walk_list, &over_hwa);\n\t\t}\n\t}\n\n\tif (after_sum >= WEIGHT_ONE) {\n\t\t/*\n\t\t * The delta should be deducted from the over_sum, calculate\n\t\t * target over_sum value.\n\t\t */\n\t\tu32 over_delta = after_sum - (WEIGHT_ONE - 1);\n\t\tWARN_ON_ONCE(over_sum <= over_delta);\n\t\tover_target = over_sum - over_delta;\n\t} else {\n\t\tover_target = 0;\n\t}\n\n\tlist_for_each_entry_safe(iocg, tiocg, &over_hwa, walk_list) {\n\t\tif (over_target)\n\t\t\tiocg->hweight_after_donation =\n\t\t\t\tdiv_u64((u64)iocg->hweight_after_donation *\n\t\t\t\t\tover_target, over_sum);\n\t\tlist_del_init(&iocg->walk_list);\n\t}\n\n\t/*\n\t * Build pre-order inner node walk list and prepare for donation\n\t * adjustment calculations.\n\t */\n\tlist_for_each_entry(iocg, surpluses, surplus_list) {\n\t\tiocg_build_inner_walk(iocg, &inner_walk);\n\t}\n\n\troot_iocg = list_first_entry(&inner_walk, struct ioc_gq, walk_list);\n\tWARN_ON_ONCE(root_iocg->level > 0);\n\n\tlist_for_each_entry(iocg, &inner_walk, walk_list) {\n\t\tiocg->child_adjusted_sum = 0;\n\t\tiocg->hweight_donating = 0;\n\t\tiocg->hweight_after_donation = 0;\n\t}\n\n\t/*\n\t * Propagate the donating budget (b_t) and after donation budget (b'_t)\n\t * up the hierarchy.\n\t */\n\tlist_for_each_entry(iocg, surpluses, surplus_list) {\n\t\tstruct ioc_gq *parent = iocg->ancestors[iocg->level - 1];\n\n\t\tparent->hweight_donating += iocg->hweight_donating;\n\t\tparent->hweight_after_donation += iocg->hweight_after_donation;\n\t}\n\n\tlist_for_each_entry_reverse(iocg, &inner_walk, walk_list) {\n\t\tif (iocg->level > 0) {\n\t\t\tstruct ioc_gq *parent = iocg->ancestors[iocg->level - 1];\n\n\t\t\tparent->hweight_donating += iocg->hweight_donating;\n\t\t\tparent->hweight_after_donation += iocg->hweight_after_donation;\n\t\t}\n\t}\n\n\t/*\n\t * Calculate inner hwa's (b) and make sure the donation values are\n\t * within the accepted ranges as we're doing low res calculations with\n\t * roundups.\n\t */\n\tlist_for_each_entry(iocg, &inner_walk, walk_list) {\n\t\tif (iocg->level) {\n\t\t\tstruct ioc_gq *parent = iocg->ancestors[iocg->level - 1];\n\n\t\t\tiocg->hweight_active = DIV64_U64_ROUND_UP(\n\t\t\t\t(u64)parent->hweight_active * iocg->active,\n\t\t\t\tparent->child_active_sum);\n\n\t\t}\n\n\t\tiocg->hweight_donating = min(iocg->hweight_donating,\n\t\t\t\t\t     iocg->hweight_active);\n\t\tiocg->hweight_after_donation = min(iocg->hweight_after_donation,\n\t\t\t\t\t\t   iocg->hweight_donating - 1);\n\t\tif (WARN_ON_ONCE(iocg->hweight_active <= 1 ||\n\t\t\t\t iocg->hweight_donating <= 1 ||\n\t\t\t\t iocg->hweight_after_donation == 0)) {\n\t\t\tpr_warn(\"iocg: invalid donation weights in \");\n\t\t\tpr_cont_cgroup_path(iocg_to_blkg(iocg)->blkcg->css.cgroup);\n\t\t\tpr_cont(\": active=%u donating=%u after=%u\\n\",\n\t\t\t\tiocg->hweight_active, iocg->hweight_donating,\n\t\t\t\tiocg->hweight_after_donation);\n\t\t}\n\t}\n\n\t/*\n\t * Calculate the global donation rate (gamma) - the rate to adjust\n\t * non-donating budgets by.\n\t *\n\t * No need to use 64bit multiplication here as the first operand is\n\t * guaranteed to be smaller than WEIGHT_ONE (1<<16).\n\t *\n\t * We know that there are beneficiary nodes and the sum of the donating\n\t * hweights can't be whole; however, due to the round-ups during hweight\n\t * calculations, root_iocg->hweight_donating might still end up equal to\n\t * or greater than whole. Limit the range when calculating the divider.\n\t *\n\t * gamma = (1 - t_r') / (1 - t_r)\n\t */\n\tgamma = DIV_ROUND_UP(\n\t\t(WEIGHT_ONE - root_iocg->hweight_after_donation) * WEIGHT_ONE,\n\t\tWEIGHT_ONE - min_t(u32, root_iocg->hweight_donating, WEIGHT_ONE - 1));\n\n\t/*\n\t * Calculate adjusted hwi, child_adjusted_sum and inuse for the inner\n\t * nodes.\n\t */\n\tlist_for_each_entry(iocg, &inner_walk, walk_list) {\n\t\tstruct ioc_gq *parent;\n\t\tu32 inuse, wpt, wptp;\n\t\tu64 st, sf;\n\n\t\tif (iocg->level == 0) {\n\t\t\t/* adjusted weight sum for 1st level: s' = s * b_pf / b'_pf */\n\t\t\tiocg->child_adjusted_sum = DIV64_U64_ROUND_UP(\n\t\t\t\tiocg->child_active_sum * (WEIGHT_ONE - iocg->hweight_donating),\n\t\t\t\tWEIGHT_ONE - iocg->hweight_after_donation);\n\t\t\tcontinue;\n\t\t}\n\n\t\tparent = iocg->ancestors[iocg->level - 1];\n\n\t\t/* b' = gamma * b_f + b_t' */\n\t\tiocg->hweight_inuse = DIV64_U64_ROUND_UP(\n\t\t\t(u64)gamma * (iocg->hweight_active - iocg->hweight_donating),\n\t\t\tWEIGHT_ONE) + iocg->hweight_after_donation;\n\n\t\t/* w' = s' * b' / b'_p */\n\t\tinuse = DIV64_U64_ROUND_UP(\n\t\t\t(u64)parent->child_adjusted_sum * iocg->hweight_inuse,\n\t\t\tparent->hweight_inuse);\n\n\t\t/* adjusted weight sum for children: s' = s_f + s_t * w'_pt / w_pt */\n\t\tst = DIV64_U64_ROUND_UP(\n\t\t\tiocg->child_active_sum * iocg->hweight_donating,\n\t\t\tiocg->hweight_active);\n\t\tsf = iocg->child_active_sum - st;\n\t\twpt = DIV64_U64_ROUND_UP(\n\t\t\t(u64)iocg->active * iocg->hweight_donating,\n\t\t\tiocg->hweight_active);\n\t\twptp = DIV64_U64_ROUND_UP(\n\t\t\t(u64)inuse * iocg->hweight_after_donation,\n\t\t\tiocg->hweight_inuse);\n\n\t\tiocg->child_adjusted_sum = sf + DIV64_U64_ROUND_UP(st * wptp, wpt);\n\t}\n\n\t/*\n\t * All inner nodes now have ->hweight_inuse and ->child_adjusted_sum and\n\t * we can finally determine leaf adjustments.\n\t */\n\tlist_for_each_entry(iocg, surpluses, surplus_list) {\n\t\tstruct ioc_gq *parent = iocg->ancestors[iocg->level - 1];\n\t\tu32 inuse;\n\n\t\t/*\n\t\t * In-debt iocgs participated in the donation calculation with\n\t\t * the minimum target hweight_inuse. Configuring inuse\n\t\t * accordingly would work fine but debt handling expects\n\t\t * @iocg->inuse stay at the minimum and we don't wanna\n\t\t * interfere.\n\t\t */\n\t\tif (iocg->abs_vdebt) {\n\t\t\tWARN_ON_ONCE(iocg->inuse > 1);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* w' = s' * b' / b'_p, note that b' == b'_t for donating leaves */\n\t\tinuse = DIV64_U64_ROUND_UP(\n\t\t\tparent->child_adjusted_sum * iocg->hweight_after_donation,\n\t\t\tparent->hweight_inuse);\n\n\t\tTRACE_IOCG_PATH(inuse_transfer, iocg, now,\n\t\t\t\tiocg->inuse, inuse,\n\t\t\t\tiocg->hweight_inuse,\n\t\t\t\tiocg->hweight_after_donation);\n\n\t\t__propagate_weights(iocg, iocg->active, inuse, true, now);\n\t}\n\n\t/* walk list should be dissolved after use */\n\tlist_for_each_entry_safe(iocg, tiocg, &inner_walk, walk_list)\n\t\tlist_del_init(&iocg->walk_list);\n}",
        "static int eip197_trc_cache_init(struct safexcel_crypto_priv *priv)\n{\n\tu32 val, dsize, asize;\n\tint cs_rc_max, cs_ht_wc, cs_trc_rec_wc, cs_trc_lg_rec_wc;\n\tint cs_rc_abs_max, cs_ht_sz;": "static int eip197_trc_cache_init(struct safexcel_crypto_priv *priv)\n{\n\tu32 val, dsize, asize;\n\tint cs_rc_max, cs_ht_wc, cs_trc_rec_wc, cs_trc_lg_rec_wc;\n\tint cs_rc_abs_max, cs_ht_sz;\n\tint maxbanks;\n\n\t/* Setup (dummy) virtualization for cache */\n\teip197_trc_cache_setupvirt(priv);\n\n\t/*\n\t * Enable the record cache memory access and\n\t * probe the bank select width\n\t */\n\tval = readl(priv->base + EIP197_CS_RAM_CTRL);\n\tval &= ~EIP197_TRC_ENABLE_MASK;\n\tval |= EIP197_TRC_ENABLE_0 | EIP197_CS_BANKSEL_MASK;\n\twritel(val, priv->base + EIP197_CS_RAM_CTRL);\n\tval = readl(priv->base + EIP197_CS_RAM_CTRL);\n\tmaxbanks = ((val&EIP197_CS_BANKSEL_MASK)>>EIP197_CS_BANKSEL_OFS) + 1;\n\n\t/* Clear all ECC errors */\n\twritel(0, priv->base + EIP197_TRC_ECCCTRL);\n\n\t/*\n\t * Make sure the cache memory is accessible by taking record cache into\n\t * reset. Need data memory access here, not admin access.\n\t */\n\tval = readl(priv->base + EIP197_TRC_PARAMS);\n\tval |= EIP197_TRC_PARAMS_SW_RESET | EIP197_TRC_PARAMS_DATA_ACCESS;\n\twritel(val, priv->base + EIP197_TRC_PARAMS);\n\n\t/* Probed data RAM size in bytes */\n\tdsize = eip197_trc_cache_probe(priv, maxbanks, 0xffffffff, 32);\n\n\t/*\n\t * Now probe the administration RAM size pretty much the same way\n\t * Except that only the lower 30 bits are writable and we don't need\n\t * bank selects\n\t */\n\tval = readl(priv->base + EIP197_TRC_PARAMS);\n\t/* admin access now */\n\tval &= ~(EIP197_TRC_PARAMS_DATA_ACCESS | EIP197_CS_BANKSEL_MASK);\n\twritel(val, priv->base + EIP197_TRC_PARAMS);\n\n\t/* Probed admin RAM size in admin words */\n\tasize = eip197_trc_cache_probe(priv, 0, 0x3fffffff, 16) >> 4;\n\n\t/* Clear any ECC errors detected while probing! */\n\twritel(0, priv->base + EIP197_TRC_ECCCTRL);\n\n\t/* Sanity check probing results */\n\tif (dsize < EIP197_MIN_DSIZE || asize < EIP197_MIN_ASIZE) {\n\t\tdev_err(priv->dev, \"Record cache probing failed (%d,%d).\",\n\t\t\tdsize, asize);\n\t\treturn -ENODEV;\n\t}\n\n\t/*\n\t * Determine optimal configuration from RAM sizes\n\t * Note that we assume that the physical RAM configuration is sane\n\t * Therefore, we don't do any parameter error checking here ...\n\t */\n\n\t/* For now, just use a single record format covering everything */\n\tcs_trc_rec_wc = EIP197_CS_TRC_REC_WC;\n\tcs_trc_lg_rec_wc = EIP197_CS_TRC_REC_WC;\n\n\t/*\n\t * Step #1: How many records will physically fit?\n\t * Hard upper limit is 1023!\n\t */\n\tcs_rc_abs_max = min_t(uint, ((dsize >> 2) / cs_trc_lg_rec_wc), 1023);\n\t/* Step #2: Need at least 2 words in the admin RAM per record */\n\tcs_rc_max = min_t(uint, cs_rc_abs_max, (asize >> 1));\n\t/* Step #3: Determine log2 of hash table size */\n\tcs_ht_sz = __fls(asize - cs_rc_max) - 2;\n\t/* Step #4: determine current size of hash table in dwords */\n\tcs_ht_wc = 16 << cs_ht_sz; /* dwords, not admin words */\n\t/* Step #5: add back excess words and see if we can fit more records */\n\tcs_rc_max = min_t(uint, cs_rc_abs_max, asize - (cs_ht_wc >> 2));\n\n\t/* Clear the cache RAMs */\n\teip197_trc_cache_clear(priv, cs_rc_max, cs_ht_wc);\n\n\t/* Disable the record cache memory access */\n\tval = readl(priv->base + EIP197_CS_RAM_CTRL);\n\tval &= ~EIP197_TRC_ENABLE_MASK;\n\twritel(val, priv->base + EIP197_CS_RAM_CTRL);\n\n\t/* Write head and tail pointers of the record free chain */\n\tval = EIP197_TRC_FREECHAIN_HEAD_PTR(0) |\n\t      EIP197_TRC_FREECHAIN_TAIL_PTR(cs_rc_max - 1);\n\twritel(val, priv->base + EIP197_TRC_FREECHAIN);\n\n\t/* Configure the record cache #1 */\n\tval = EIP197_TRC_PARAMS2_RC_SZ_SMALL(cs_trc_rec_wc) |\n\t      EIP197_TRC_PARAMS2_HTABLE_PTR(cs_rc_max);\n\twritel(val, priv->base + EIP197_TRC_PARAMS2);\n\n\t/* Configure the record cache #2 */\n\tval = EIP197_TRC_PARAMS_RC_SZ_LARGE(cs_trc_lg_rec_wc) |\n\t      EIP197_TRC_PARAMS_BLK_TIMER_SPEED(1) |\n\t      EIP197_TRC_PARAMS_HTABLE_SZ(cs_ht_sz);\n\twritel(val, priv->base + EIP197_TRC_PARAMS);\n\n\tdev_info(priv->dev, \"TRC init: %dd,%da (%dr,%dh)\\n\",\n\t\t dsize, asize, cs_rc_max, cs_ht_wc + cs_ht_wc);\n\treturn 0;\n}",
        "static int active_scan(struct hci_request *req, unsigned long opt)\n{\n\tuint16_t interval = opt;\n\tstruct hci_dev *hdev = req->hdev;\n\tu8 own_addr_type;": "static int active_scan(struct hci_request *req, unsigned long opt)\n{\n\tuint16_t interval = opt;\n\tstruct hci_dev *hdev = req->hdev;\n\tu8 own_addr_type;\n\t/* Accept list is not used for discovery */\n\tu8 filter_policy = 0x00;\n\t/* Default is to enable duplicates filter */\n\tu8 filter_dup = LE_SCAN_FILTER_DUP_ENABLE;\n\t/* Discovery doesn't require controller address resolution */\n\tbool addr_resolv = false;\n\tint err;\n\n\tbt_dev_dbg(hdev, \"\");\n\n\t/* If controller is scanning, it means the background scanning is\n\t * running. Thus, we should temporarily stop it in order to set the\n\t * discovery scanning parameters.\n\t */\n\tif (hci_dev_test_flag(hdev, HCI_LE_SCAN)) {\n\t\thci_req_add_le_scan_disable(req, false);\n\t\tcancel_interleave_scan(hdev);\n\t}\n\n\t/* All active scans will be done with either a resolvable private\n\t * address (when privacy feature has been enabled) or non-resolvable\n\t * private address.\n\t */\n\terr = hci_update_random_address(req, true, scan_use_rpa(hdev),\n\t\t\t\t\t&own_addr_type);\n\tif (err < 0)\n\t\town_addr_type = ADDR_LE_DEV_PUBLIC;\n\n\thci_dev_lock(hdev);\n\tif (hci_is_adv_monitoring(hdev)) {\n\t\t/* Duplicate filter should be disabled when some advertisement\n\t\t * monitor is activated, otherwise AdvMon can only receive one\n\t\t * advertisement for one peer(*) during active scanning, and\n\t\t * might report loss to these peers.\n\t\t *\n\t\t * Note that different controllers have different meanings of\n\t\t * |duplicate|. Some of them consider packets with the same\n\t\t * address as duplicate, and others consider packets with the\n\t\t * same address and the same RSSI as duplicate. Although in the\n\t\t * latter case we don't need to disable duplicate filter, but\n\t\t * it is common to have active scanning for a short period of\n\t\t * time, the power impact should be neglectable.\n\t\t */\n\t\tfilter_dup = LE_SCAN_FILTER_DUP_DISABLE;\n\t}\n\thci_dev_unlock(hdev);\n\n\thci_req_start_scan(req, LE_SCAN_ACTIVE, interval,\n\t\t\t   hdev->le_scan_window_discovery, own_addr_type,\n\t\t\t   filter_policy, filter_dup, addr_resolv);\n\treturn 0;\n}",
        "static void test_multi_sethwdebug_range(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info1, info2;\n\tunsigned long wp_addr1, wp_addr2;\n\tchar *name1 = \"PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DW ALIGNED\";": "static void test_multi_sethwdebug_range(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info1, info2;\n\tunsigned long wp_addr1, wp_addr2;\n\tchar *name1 = \"PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DW ALIGNED\";\n\tchar *name2 = \"PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DW UNALIGNED\";\n\tint len1, len2;\n\tint wh1, wh2;\n\n\twp_addr1 = (unsigned long)&gstruct.a;\n\twp_addr2 = (unsigned long)&gstruct.b;\n\tlen1 = A_LEN;\n\tlen2 = B_LEN;\n\tget_ppc_hw_breakpoint(&info1, PPC_BREAKPOINT_TRIGGER_WRITE, wp_addr1, len1);\n\tget_ppc_hw_breakpoint(&info2, PPC_BREAKPOINT_TRIGGER_READ, wp_addr2, len2);\n\n\t/* PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DW ALIGNED, WO test */\n\twh1 = ptrace_sethwdebug(child_pid, &info1);\n\n\t/* PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DW UNALIGNED, RO test */\n\twh2 = ptrace_sethwdebug(child_pid, &info2);\n\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name1, \"WO\", wp_addr1, len1);\n\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name2, \"RO\", wp_addr2, len2);\n\n\tptrace_delhwdebug(child_pid, wh1);\n\tptrace_delhwdebug(child_pid, wh2);\n}",
        "static void test_barrier_nothreads(struct kunit *test)\n{\n#ifdef CONFIG_KCSAN_WEAK_MEMORY\n\tstruct kcsan_scoped_access *reorder_access = &current->kcsan_ctx.reorder_access;\n#else": "static void test_barrier_nothreads(struct kunit *test)\n{\n#ifdef CONFIG_KCSAN_WEAK_MEMORY\n\tstruct kcsan_scoped_access *reorder_access = &current->kcsan_ctx.reorder_access;\n#else\n\tstruct kcsan_scoped_access *reorder_access = NULL;\n#endif\n\tarch_spinlock_t arch_spinlock = __ARCH_SPIN_LOCK_UNLOCKED;\n\tatomic_t dummy;\n\n\tKCSAN_TEST_REQUIRES(test, reorder_access != NULL);\n\tKCSAN_TEST_REQUIRES(test, IS_ENABLED(CONFIG_SMP));\n\n#define __KCSAN_EXPECT_BARRIER(access_type, barrier, order_before, name)\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\t\t\t\\\n\t\treorder_access->type = (access_type) | KCSAN_ACCESS_SCOPED;\t\t\t\\\n\t\treorder_access->size = sizeof(test_var);\t\t\t\t\t\\\n\t\tbarrier;\t\t\t\t\t\t\t\t\t\\\n\t\tKUNIT_EXPECT_EQ_MSG(test, reorder_access->size,\t\t\t\t\t\\\n\t\t\t\t    order_before ? 0 : sizeof(test_var),\t\t\t\\\n\t\t\t\t    \"improperly instrumented type=(\" #access_type \"): \" name);\t\\\n\t} while (0)\n#define KCSAN_EXPECT_READ_BARRIER(b, o)  __KCSAN_EXPECT_BARRIER(0, b, o, #b)\n#define KCSAN_EXPECT_WRITE_BARRIER(b, o) __KCSAN_EXPECT_BARRIER(KCSAN_ACCESS_WRITE, b, o, #b)\n#define KCSAN_EXPECT_RW_BARRIER(b, o)    __KCSAN_EXPECT_BARRIER(KCSAN_ACCESS_COMPOUND | KCSAN_ACCESS_WRITE, b, o, #b)\n\n\t/*\n\t * Lockdep initialization can strengthen certain locking operations due\n\t * to calling into instrumented files; \"warm up\" our locks.\n\t */\n\tspin_lock(&test_spinlock);\n\tspin_unlock(&test_spinlock);\n\tmutex_lock(&test_mutex);\n\tmutex_unlock(&test_mutex);\n\n\t/* Force creating a valid entry in reorder_access first. */\n\ttest_var = 0;\n\twhile (test_var++ < 1000000 && reorder_access->size != sizeof(test_var))\n\t\t__kcsan_check_read(&test_var, sizeof(test_var));\n\tKUNIT_ASSERT_EQ(test, reorder_access->size, sizeof(test_var));\n\n\tkcsan_nestable_atomic_begin(); /* No watchpoints in called functions. */\n\n\tKCSAN_EXPECT_READ_BARRIER(mb(), true);\n\tKCSAN_EXPECT_READ_BARRIER(wmb(), false);\n\tKCSAN_EXPECT_READ_BARRIER(rmb(), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_mb(), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_wmb(), false);\n\tKCSAN_EXPECT_READ_BARRIER(smp_rmb(), true);\n\tKCSAN_EXPECT_READ_BARRIER(dma_wmb(), false);\n\tKCSAN_EXPECT_READ_BARRIER(dma_rmb(), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_mb__before_atomic(), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_mb__after_atomic(), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_mb__after_spinlock(), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_store_mb(test_var, 0), true);\n\tKCSAN_EXPECT_READ_BARRIER(smp_load_acquire(&test_var), false);\n\tKCSAN_EXPECT_READ_BARRIER(smp_store_release(&test_var, 0), true);\n\tKCSAN_EXPECT_READ_BARRIER(xchg(&test_var, 0), true);\n\tKCSAN_EXPECT_READ_BARRIER(xchg_release(&test_var, 0), true);\n\tKCSAN_EXPECT_READ_BARRIER(xchg_relaxed(&test_var, 0), false);\n\tKCSAN_EXPECT_READ_BARRIER(cmpxchg(&test_var, 0,  0), true);\n\tKCSAN_EXPECT_READ_BARRIER(cmpxchg_release(&test_var, 0,  0), true);\n\tKCSAN_EXPECT_READ_BARRIER(cmpxchg_relaxed(&test_var, 0,  0), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_read(&dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_read_acquire(&dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_set(&dummy, 0), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_set_release(&dummy, 0), true);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_add(1, &dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_add_return(1, &dummy), true);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_add_return_acquire(1, &dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_add_return_release(1, &dummy), true);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_add_return_relaxed(1, &dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_fetch_add(1, &dummy), true);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_fetch_add_acquire(1, &dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_fetch_add_release(1, &dummy), true);\n\tKCSAN_EXPECT_READ_BARRIER(atomic_fetch_add_relaxed(1, &dummy), false);\n\tKCSAN_EXPECT_READ_BARRIER(test_and_set_bit(0, &test_var), true);\n\tKCSAN_EXPECT_READ_BARRIER(test_and_clear_bit(0, &test_var), true);\n\tKCSAN_EXPECT_READ_BARRIER(test_and_change_bit(0, &test_var), true);\n\tKCSAN_EXPECT_READ_BARRIER(clear_bit_unlock(0, &test_var), true);\n\tKCSAN_EXPECT_READ_BARRIER(__clear_bit_unlock(0, &test_var), true);\n\tKCSAN_EXPECT_READ_BARRIER(arch_spin_lock(&arch_spinlock), false);\n\tKCSAN_EXPECT_READ_BARRIER(arch_spin_unlock(&arch_spinlock), true);\n\tKCSAN_EXPECT_READ_BARRIER(spin_lock(&test_spinlock), false);\n\tKCSAN_EXPECT_READ_BARRIER(spin_unlock(&test_spinlock), true);\n\tKCSAN_EXPECT_READ_BARRIER(mutex_lock(&test_mutex), false);\n\tKCSAN_EXPECT_READ_BARRIER(mutex_unlock(&test_mutex), true);\n\n\tKCSAN_EXPECT_WRITE_BARRIER(mb(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(wmb(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(rmb(), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_mb(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_wmb(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_rmb(), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(dma_wmb(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(dma_rmb(), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_mb__before_atomic(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_mb__after_atomic(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_mb__after_spinlock(), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_store_mb(test_var, 0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_load_acquire(&test_var), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(smp_store_release(&test_var, 0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(xchg(&test_var, 0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(xchg_release(&test_var, 0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(xchg_relaxed(&test_var, 0), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(cmpxchg(&test_var, 0,  0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(cmpxchg_release(&test_var, 0,  0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(cmpxchg_relaxed(&test_var, 0,  0), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_read(&dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_read_acquire(&dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_set(&dummy, 0), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_set_release(&dummy, 0), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_add(1, &dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_add_return(1, &dummy), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_add_return_acquire(1, &dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_add_return_release(1, &dummy), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_add_return_relaxed(1, &dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_fetch_add(1, &dummy), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_fetch_add_acquire(1, &dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_fetch_add_release(1, &dummy), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(atomic_fetch_add_relaxed(1, &dummy), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(test_and_set_bit(0, &test_var), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(test_and_clear_bit(0, &test_var), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(test_and_change_bit(0, &test_var), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(clear_bit_unlock(0, &test_var), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(__clear_bit_unlock(0, &test_var), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(arch_spin_lock(&arch_spinlock), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(arch_spin_unlock(&arch_spinlock), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(spin_lock(&test_spinlock), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(spin_unlock(&test_spinlock), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(mutex_lock(&test_mutex), false);\n\tKCSAN_EXPECT_WRITE_BARRIER(mutex_unlock(&test_mutex), true);\n\n\tKCSAN_EXPECT_RW_BARRIER(mb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(wmb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(rmb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_mb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_wmb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_rmb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(dma_wmb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(dma_rmb(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_mb__before_atomic(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_mb__after_atomic(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_mb__after_spinlock(), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_store_mb(test_var, 0), true);\n\tKCSAN_EXPECT_RW_BARRIER(smp_load_acquire(&test_var), false);\n\tKCSAN_EXPECT_RW_BARRIER(smp_store_release(&test_var, 0), true);\n\tKCSAN_EXPECT_RW_BARRIER(xchg(&test_var, 0), true);\n\tKCSAN_EXPECT_RW_BARRIER(xchg_release(&test_var, 0), true);\n\tKCSAN_EXPECT_RW_BARRIER(xchg_relaxed(&test_var, 0), false);\n\tKCSAN_EXPECT_RW_BARRIER(cmpxchg(&test_var, 0,  0), true);\n\tKCSAN_EXPECT_RW_BARRIER(cmpxchg_release(&test_var, 0,  0), true);\n\tKCSAN_EXPECT_RW_BARRIER(cmpxchg_relaxed(&test_var, 0,  0), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_read(&dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_read_acquire(&dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_set(&dummy, 0), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_set_release(&dummy, 0), true);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_add(1, &dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_add_return(1, &dummy), true);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_add_return_acquire(1, &dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_add_return_release(1, &dummy), true);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_add_return_relaxed(1, &dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_fetch_add(1, &dummy), true);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_fetch_add_acquire(1, &dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_fetch_add_release(1, &dummy), true);\n\tKCSAN_EXPECT_RW_BARRIER(atomic_fetch_add_relaxed(1, &dummy), false);\n\tKCSAN_EXPECT_RW_BARRIER(test_and_set_bit(0, &test_var), true);\n\tKCSAN_EXPECT_RW_BARRIER(test_and_clear_bit(0, &test_var), true);\n\tKCSAN_EXPECT_RW_BARRIER(test_and_change_bit(0, &test_var), true);\n\tKCSAN_EXPECT_RW_BARRIER(clear_bit_unlock(0, &test_var), true);\n\tKCSAN_EXPECT_RW_BARRIER(__clear_bit_unlock(0, &test_var), true);\n\tKCSAN_EXPECT_RW_BARRIER(arch_spin_lock(&arch_spinlock), false);\n\tKCSAN_EXPECT_RW_BARRIER(arch_spin_unlock(&arch_spinlock), true);\n\tKCSAN_EXPECT_RW_BARRIER(spin_lock(&test_spinlock), false);\n\tKCSAN_EXPECT_RW_BARRIER(spin_unlock(&test_spinlock), true);\n\tKCSAN_EXPECT_RW_BARRIER(mutex_lock(&test_mutex), false);\n\tKCSAN_EXPECT_RW_BARRIER(mutex_unlock(&test_mutex), true);\n\n#ifdef clear_bit_unlock_is_negative_byte\n\tKCSAN_EXPECT_READ_BARRIER(clear_bit_unlock_is_negative_byte(0, &test_var), true);\n\tKCSAN_EXPECT_WRITE_BARRIER(clear_bit_unlock_is_negative_byte(0, &test_var), true);\n\tKCSAN_EXPECT_RW_BARRIER(clear_bit_unlock_is_negative_byte(0, &test_var), true);\n#endif\n\tkcsan_nestable_atomic_end();\n}",
        "static int cx23885_audio_mux(struct cx23885_dev *dev, unsigned int input)\n{\n\tdprintk(1, \"%s(input=%d)\\n\", __func__, input);\n\n\t/* The baseband video core of the cx23885 has two audio inputs.": "static int cx23885_audio_mux(struct cx23885_dev *dev, unsigned int input)\n{\n\tdprintk(1, \"%s(input=%d)\\n\", __func__, input);\n\n\t/* The baseband video core of the cx23885 has two audio inputs.\n\t * LR1 and LR2. In almost every single case so far only HVR1xxx\n\t * cards we've only ever supported LR1. Time to support LR2,\n\t * which is available via the optional white breakout header on\n\t * the board.\n\t * We'll use a could of existing enums in the card struct to allow\n\t * devs to specify which baseband input they need, or just default\n\t * to what we've always used.\n\t */\n\tif (INPUT(input)->amux == CX25840_AUDIO7)\n\t\tcx23885_flatiron_mux(dev, 1);\n\telse if (INPUT(input)->amux == CX25840_AUDIO6)\n\t\tcx23885_flatiron_mux(dev, 2);\n\telse {\n\t\t/* Not specifically defined, assume the default. */\n\t\tcx23885_flatiron_mux(dev, 1);\n\t}\n\n\treturn 0;\n}",
        "static int coda9_jpeg_gen_dec_huff_tab(struct coda_ctx *ctx, int tab_num)\n{\n\tint ptr_cnt = 0, huff_code = 0, zero_flag = 0, data_flag = 0;\n\tu8 *huff_bits;\n\ts16 *huff_max;": "static int coda9_jpeg_gen_dec_huff_tab(struct coda_ctx *ctx, int tab_num)\n{\n\tint ptr_cnt = 0, huff_code = 0, zero_flag = 0, data_flag = 0;\n\tu8 *huff_bits;\n\ts16 *huff_max;\n\ts16 *huff_min;\n\ts8 *huff_ptr;\n\tint ofs;\n\tint i;\n\n\thuff_bits = coda9_jpeg_get_huff_bits(ctx, tab_num);\n\tif (!huff_bits)\n\t\treturn -EINVAL;\n\n\t/* DC/AC Luma, DC/AC Chroma -> DC Luma/Chroma, AC Luma/Chroma */\n\tofs = ((tab_num & 1) << 1) | ((tab_num >> 1) & 1);\n\tofs *= 16;\n\n\thuff_ptr = ctx->params.jpeg_huff_tab->ptr + ofs;\n\thuff_max = ctx->params.jpeg_huff_tab->max + ofs;\n\thuff_min = ctx->params.jpeg_huff_tab->min + ofs;\n\n\tfor (i = 0; i < 16; i++) {\n\t\tif (huff_bits[i]) {\n\t\t\thuff_ptr[i] = ptr_cnt;\n\t\t\tptr_cnt += huff_bits[i];\n\t\t\thuff_min[i] = huff_code;\n\t\t\thuff_max[i] = huff_code + (huff_bits[i] - 1);\n\t\t\tdata_flag = 1;\n\t\t\tzero_flag = 0;\n\t\t} else {\n\t\t\thuff_ptr[i] = -1;\n\t\t\thuff_min[i] = -1;\n\t\t\thuff_max[i] = -1;\n\t\t\tzero_flag = 1;\n\t\t}\n\n\t\tif (data_flag == 1) {\n\t\t\tif (zero_flag == 1)\n\t\t\t\thuff_code <<= 1;\n\t\t\telse\n\t\t\t\thuff_code = (huff_max[i] + 1) << 1;\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_conn_destroy *req;\n\tunion l5cm_specific_data l5_data;\n\tint ret;": "static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_conn_destroy *req;\n\tunion l5cm_specific_data l5_data;\n\tint ret;\n\tu32 cid, l5_cid;\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_context *ctx;\n\tstruct fcoe_kcqe kcqe;\n\tstruct kcqe *cqes[1];\n\n\treq = (struct fcoe_kwqe_conn_destroy *) kwqe;\n\tcid = req->context_id;\n\tl5_cid = req->conn_id;\n\tif (l5_cid >= dev->max_fcoe_conn)\n\t\treturn -EINVAL;\n\n\tl5_cid += BNX2X_FCOE_L5_CID_BASE;\n\n\tctx = &cp->ctx_tbl[l5_cid];\n\n\tinit_waitqueue_head(&ctx->waitq);\n\tctx->wait_cond = 0;\n\n\tmemset(&kcqe, 0, sizeof(kcqe));\n\tkcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;\n\tmemset(&l5_data, 0, sizeof(l5_data));\n\tret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,\n\t\t\t\t  FCOE_CONNECTION_TYPE, &l5_data);\n\tif (ret == 0) {\n\t\twait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);\n\t\tif (ctx->wait_cond)\n\t\t\tkcqe.completion_status = 0;\n\t}\n\n\tset_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);\n\tqueue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));\n\n\tkcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;\n\tkcqe.fcoe_conn_id = req->conn_id;\n\tkcqe.fcoe_conn_context_id = cid;\n\n\tcqes[0] = (struct kcqe *) &kcqe;\n\tcnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);\n\treturn ret;\n}",
        "static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)\n{\n\tstruct idtcm *idtcm = channel->idtcm;\n\tu16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);\n\tu8 val = 0;": "static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)\n{\n\tstruct idtcm *idtcm = channel->idtcm;\n\tu16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);\n\tu8 val = 0;\n\tint err;\n\n\tval &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);\n\tval |= (ref << WR_REF_INDEX_SHIFT);\n\n\terr = idtcm_write(idtcm, channel->tod_read_secondary,\n\t\t\t  TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));\n\tif (err)\n\t\treturn err;\n\n\tval = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);\n\n\terr = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,\n\t\t\t  &val, sizeof(val));\n\tif (err)\n\t\tdev_err(idtcm->dev, \"%s: err = %d\", __func__, err);\n\n\treturn err;\n}",
        "static void mptcp_sock_destruct(struct sock *sk)\n{\n\t/* if new mptcp socket isn't accepted, it is free'd\n\t * from the tcp listener sockets request queue, linked\n\t * from req->sk.  The tcp socket is released.": "static void mptcp_sock_destruct(struct sock *sk)\n{\n\t/* if new mptcp socket isn't accepted, it is free'd\n\t * from the tcp listener sockets request queue, linked\n\t * from req->sk.  The tcp socket is released.\n\t * This calls the ULP release function which will\n\t * also remove the mptcp socket, via\n\t * sock_put(ctx->conn).\n\t *\n\t * Problem is that the mptcp socket will be in\n\t * ESTABLISHED state and will not have the SOCK_DEAD flag.\n\t * Both result in warnings from inet_sock_destruct.\n\t */\n\tif ((1 << sk->sk_state) & (TCPF_ESTABLISHED | TCPF_CLOSE_WAIT)) {\n\t\tsk->sk_state = TCP_CLOSE;\n\t\tWARN_ON_ONCE(sk->sk_socket);\n\t\tsock_orphan(sk);\n\t}\n\n\tmptcp_destroy_common(mptcp_sk(sk));\n\tinet_sock_destruct(sk);\n}",
        "static void cs42l42_suspend(struct sub_codec *cs42l42)\n{\n\tstruct hda_codec *codec = cs42l42->codec;\n\tstruct cs8409_spec *spec = codec->spec;\n\tint reg_cdc_status = 0;": "static void cs42l42_suspend(struct sub_codec *cs42l42)\n{\n\tstruct hda_codec *codec = cs42l42->codec;\n\tstruct cs8409_spec *spec = codec->spec;\n\tint reg_cdc_status = 0;\n\tconst struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {\n\t\t{ CS42L42_DAC_CTL2, 0x02 },\n\t\t{ CS42L42_HS_CLAMP_DISABLE, 0x00 },\n\t\t{ CS42L42_MIXER_CHA_VOL, 0x3F },\n\t\t{ CS42L42_MIXER_ADC_VOL, 0x3F },\n\t\t{ CS42L42_MIXER_CHB_VOL, 0x3F },\n\t\t{ CS42L42_HP_CTL, 0x0F },\n\t\t{ CS42L42_ASP_RX_DAI0_EN, 0x00 },\n\t\t{ CS42L42_ASP_CLK_CFG, 0x00 },\n\t\t{ CS42L42_PWR_CTL1, 0xFE },\n\t\t{ CS42L42_PWR_CTL2, 0x8C },\n\t\t{ CS42L42_PWR_CTL1, 0xFF },\n\t};\n\n\tcs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));\n\n\tif (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,\n\t\t\t(reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,\n\t\t\ttrue, cs42l42, CS42L42_CODEC_STATUS) < 0)\n\t\tcodec_warn(codec, \"Timeout waiting for PDN_DONE for CS42L42\\n\");\n\n\t/* Power down CS42L42 ASP/EQ/MIX/HP */\n\tcs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);\n\tcs42l42->suspended = 1;\n\tcs42l42->last_page = 0;\n\tcs42l42->hp_jack_in = 0;\n\tcs42l42->mic_jack_in = 0;\n\n\t/* Put CS42L42 into Reset */\n\tspec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);\n\tspec->gpio_data &= ~cs42l42->reset_gpio;\n\tsnd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);\n}",
        "static void cal_ctx_csi2_config(struct cal_ctx *ctx)\n{\n\tu32 val;\n\n\tval = cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx));": "static void cal_ctx_csi2_config(struct cal_ctx *ctx)\n{\n\tu32 val;\n\n\tval = cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx));\n\tcal_set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK);\n\t/*\n\t * DT type: MIPI CSI-2 Specs\n\t *   0x1: All - DT filter is disabled\n\t *  0x24: RGB888 1 pixel  = 3 bytes\n\t *  0x2B: RAW10  4 pixels = 5 bytes\n\t *  0x2A: RAW8   1 pixel  = 1 byte\n\t *  0x1E: YUV422 2 pixels = 4 bytes\n\t */\n\tcal_set_field(&val, ctx->datatype, CAL_CSI2_CTX_DT_MASK);\n\tcal_set_field(&val, ctx->vc, CAL_CSI2_CTX_VC_MASK);\n\tcal_set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK);\n\tcal_set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);\n\tcal_set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,\n\t\t      CAL_CSI2_CTX_PACK_MODE_MASK);\n\tcal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), val);\n\tctx_dbg(3, ctx, \"CAL_CSI2_CTX(%u, %u) = 0x%08x\\n\",\n\t\tctx->phy->instance, ctx->csi2_ctx,\n\t\tcal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx)));\n}",
        "static void unix_peek_fds(struct scm_cookie *scm, struct sk_buff *skb)\n{\n\tscm->fp = scm_fp_dup(UNIXCB(skb).fp);\n\n\t/*": "static void unix_peek_fds(struct scm_cookie *scm, struct sk_buff *skb)\n{\n\tscm->fp = scm_fp_dup(UNIXCB(skb).fp);\n\n\t/*\n\t * Garbage collection of unix sockets starts by selecting a set of\n\t * candidate sockets which have reference only from being in flight\n\t * (total_refs == inflight_refs).  This condition is checked once during\n\t * the candidate collection phase, and candidates are marked as such, so\n\t * that non-candidates can later be ignored.  While inflight_refs is\n\t * protected by unix_gc_lock, total_refs (file count) is not, hence this\n\t * is an instantaneous decision.\n\t *\n\t * Once a candidate, however, the socket must not be reinstalled into a\n\t * file descriptor while the garbage collection is in progress.\n\t *\n\t * If the above conditions are met, then the directed graph of\n\t * candidates (*) does not change while unix_gc_lock is held.\n\t *\n\t * Any operations that changes the file count through file descriptors\n\t * (dup, close, sendmsg) does not change the graph since candidates are\n\t * not installed in fds.\n\t *\n\t * Dequeing a candidate via recvmsg would install it into an fd, but\n\t * that takes unix_gc_lock to decrement the inflight count, so it's\n\t * serialized with garbage collection.\n\t *\n\t * MSG_PEEK is special in that it does not change the inflight count,\n\t * yet does install the socket into an fd.  The following lock/unlock\n\t * pair is to ensure serialization with garbage collection.  It must be\n\t * done between incrementing the file count and installing the file into\n\t * an fd.\n\t *\n\t * If garbage collection starts after the barrier provided by the\n\t * lock/unlock, then it will see the elevated refcount and not mark this\n\t * as a candidate.  If a garbage collection is already in progress\n\t * before the file count was incremented, then the lock/unlock pair will\n\t * ensure that garbage collection is finished before progressing to\n\t * installing the fd.\n\t *\n\t * (*) A -> B where B is on the queue of A or B is on the queue of C\n\t * which is on the queue of listening socket A.\n\t */\n\tspin_lock(&unix_gc_lock);\n\tspin_unlock(&unix_gc_lock);\n}",
        "static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)\n{\n\tstruct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);\n\t// page ops transfer size must be exactly ((sector_size + spare_size) *\n\t// nsectors). Limit the op size if the caller requests more than that.": "static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)\n{\n\tstruct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);\n\t// page ops transfer size must be exactly ((sector_size + spare_size) *\n\t// nsectors). Limit the op size if the caller requests more than that.\n\t// exec_op will read more than needed and discard the leftover if the\n\t// caller requests less data.\n\tif (mtk_snand_is_page_ops(op)) {\n\t\tsize_t l;\n\t\t// skip adjust_op_size for page ops\n\t\tif (ms->autofmt)\n\t\t\treturn 0;\n\t\tl = ms->caps->sector_size + ms->nfi_cfg.spare_size;\n\t\tl *= ms->nfi_cfg.nsectors;\n\t\tif (op->data.nbytes > l)\n\t\t\top->data.nbytes = l;\n\t} else {\n\t\tsize_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;\n\n\t\tif (hl >= SNF_GPRAM_SIZE)\n\t\t\treturn -EOPNOTSUPP;\n\t\tif (op->data.nbytes > SNF_GPRAM_SIZE - hl)\n\t\t\top->data.nbytes = SNF_GPRAM_SIZE - hl;\n\t}\n\treturn 0;\n}",
        "static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)\n{\n\tsize_t size = channel->tre_ring.count * GSI_RING_ELEMENT_SIZE;\n\tu32 channel_id = gsi_channel_id(channel);\n\tunion gsi_channel_scratch scr = { };": "static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)\n{\n\tsize_t size = channel->tre_ring.count * GSI_RING_ELEMENT_SIZE;\n\tu32 channel_id = gsi_channel_id(channel);\n\tunion gsi_channel_scratch scr = { };\n\tstruct gsi_channel_scratch_gpi *gpi;\n\tstruct gsi *gsi = channel->gsi;\n\tu32 wrr_weight = 0;\n\tu32 val;\n\n\t/* Arbitrarily pick TRE 0 as the first channel element to use */\n\tchannel->tre_ring.index = 0;\n\n\t/* We program all channels as GPI type/protocol */\n\tval = chtype_protocol_encoded(gsi->version, GSI_CHANNEL_TYPE_GPI);\n\tif (channel->toward_ipa)\n\t\tval |= CHTYPE_DIR_FMASK;\n\tval |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK);\n\tval |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, ELEMENT_SIZE_FMASK);\n\tiowrite32(val, gsi->virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id));\n\n\tval = r_length_encoded(gsi->version, size);\n\tiowrite32(val, gsi->virt + GSI_CH_C_CNTXT_1_OFFSET(channel_id));\n\n\t/* The context 2 and 3 registers store the low-order and\n\t * high-order 32 bits of the address of the channel ring,\n\t * respectively.\n\t */\n\tval = lower_32_bits(channel->tre_ring.addr);\n\tiowrite32(val, gsi->virt + GSI_CH_C_CNTXT_2_OFFSET(channel_id));\n\tval = upper_32_bits(channel->tre_ring.addr);\n\tiowrite32(val, gsi->virt + GSI_CH_C_CNTXT_3_OFFSET(channel_id));\n\n\t/* Command channel gets low weighted round-robin priority */\n\tif (channel->command)\n\t\twrr_weight = field_max(WRR_WEIGHT_FMASK);\n\tval = u32_encode_bits(wrr_weight, WRR_WEIGHT_FMASK);\n\n\t/* Max prefetch is 1 segment (do not set MAX_PREFETCH_FMASK) */\n\n\t/* No need to use the doorbell engine starting at IPA v4.0 */\n\tif (gsi->version < IPA_VERSION_4_0 && doorbell)\n\t\tval |= USE_DB_ENG_FMASK;\n\n\t/* v4.0 introduces an escape buffer for prefetch.  We use it\n\t * on all but the AP command channel.\n\t */\n\tif (gsi->version >= IPA_VERSION_4_0 && !channel->command) {\n\t\t/* If not otherwise set, prefetch buffers are used */\n\t\tif (gsi->version < IPA_VERSION_4_5)\n\t\t\tval |= USE_ESCAPE_BUF_ONLY_FMASK;\n\t\telse\n\t\t\tval |= u32_encode_bits(GSI_ESCAPE_BUF_ONLY,\n\t\t\t\t\t       PREFETCH_MODE_FMASK);\n\t}\n\t/* All channels set DB_IN_BYTES */\n\tif (gsi->version >= IPA_VERSION_4_9)\n\t\tval |= DB_IN_BYTES;\n\n\tiowrite32(val, gsi->virt + GSI_CH_C_QOS_OFFSET(channel_id));\n\n\t/* Now update the scratch registers for GPI protocol */\n\tgpi = &scr.gpi;\n\tgpi->max_outstanding_tre = gsi_channel_trans_tre_max(gsi, channel_id) *\n\t\t\t\t\tGSI_RING_ELEMENT_SIZE;\n\tgpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE;\n\n\tval = scr.data.word1;\n\tiowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_0_OFFSET(channel_id));\n\n\tval = scr.data.word2;\n\tiowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_1_OFFSET(channel_id));\n\n\tval = scr.data.word3;\n\tiowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_2_OFFSET(channel_id));\n\n\t/* We must preserve the upper 16 bits of the last scratch register.\n\t * The next sequence assumes those bits remain unchanged between the\n\t * read and the write.\n\t */\n\tval = ioread32(gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id));\n\tval = (scr.data.word4 & GENMASK(31, 16)) | (val & GENMASK(15, 0));\n\tiowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id));\n\n\t/* All done! */\n}",
        "static int resize_stripes(struct r5conf *conf, int newsize)\n{\n\t/* Make all the stripes able to hold 'newsize' devices.\n\t * New slots in each stripe get 'page' set to a new page.\n\t *": "static int resize_stripes(struct r5conf *conf, int newsize)\n{\n\t/* Make all the stripes able to hold 'newsize' devices.\n\t * New slots in each stripe get 'page' set to a new page.\n\t *\n\t * This happens in stages:\n\t * 1/ create a new kmem_cache and allocate the required number of\n\t *    stripe_heads.\n\t * 2/ gather all the old stripe_heads and transfer the pages across\n\t *    to the new stripe_heads.  This will have the side effect of\n\t *    freezing the array as once all stripe_heads have been collected,\n\t *    no IO will be possible.  Old stripe heads are freed once their\n\t *    pages have been transferred over, and the old kmem_cache is\n\t *    freed when all stripes are done.\n\t * 3/ reallocate conf->disks to be suitable bigger.  If this fails,\n\t *    we simple return a failure status - no need to clean anything up.\n\t * 4/ allocate new pages for the new slots in the new stripe_heads.\n\t *    If this fails, we don't bother trying the shrink the\n\t *    stripe_heads down again, we just leave them as they are.\n\t *    As each stripe_head is processed the new one is released into\n\t *    active service.\n\t *\n\t * Once step2 is started, we cannot afford to wait for a write,\n\t * so we use GFP_NOIO allocations.\n\t */\n\tstruct stripe_head *osh, *nsh;\n\tLIST_HEAD(newstripes);\n\tstruct disk_info *ndisks;\n\tint err = 0;\n\tstruct kmem_cache *sc;\n\tint i;\n\tint hash, cnt;\n\n\tmd_allow_write(conf->mddev);\n\n\t/* Step 1 */\n\tsc = kmem_cache_create(conf->cache_name[1-conf->active_name],\n\t\t\t       sizeof(struct stripe_head)+(newsize-1)*sizeof(struct r5dev),\n\t\t\t       0, 0, NULL);\n\tif (!sc)\n\t\treturn -ENOMEM;\n\n\t/* Need to ensure auto-resizing doesn't interfere */\n\tmutex_lock(&conf->cache_size_mutex);\n\n\tfor (i = conf->max_nr_stripes; i; i--) {\n\t\tnsh = alloc_stripe(sc, GFP_KERNEL, newsize, conf);\n\t\tif (!nsh)\n\t\t\tbreak;\n\n\t\tlist_add(&nsh->lru, &newstripes);\n\t}\n\tif (i) {\n\t\t/* didn't get enough, give up */\n\t\twhile (!list_empty(&newstripes)) {\n\t\t\tnsh = list_entry(newstripes.next, struct stripe_head, lru);\n\t\t\tlist_del(&nsh->lru);\n\t\t\tfree_stripe(sc, nsh);\n\t\t}\n\t\tkmem_cache_destroy(sc);\n\t\tmutex_unlock(&conf->cache_size_mutex);\n\t\treturn -ENOMEM;\n\t}\n\t/* Step 2 - Must use GFP_NOIO now.\n\t * OK, we have enough stripes, start collecting inactive\n\t * stripes and copying them over\n\t */\n\thash = 0;\n\tcnt = 0;\n\tlist_for_each_entry(nsh, &newstripes, lru) {\n\t\tlock_device_hash_lock(conf, hash);\n\t\twait_event_cmd(conf->wait_for_stripe,\n\t\t\t\t    !list_empty(conf->inactive_list + hash),\n\t\t\t\t    unlock_device_hash_lock(conf, hash),\n\t\t\t\t    lock_device_hash_lock(conf, hash));\n\t\tosh = get_free_stripe(conf, hash);\n\t\tunlock_device_hash_lock(conf, hash);\n\n#if PAGE_SIZE != DEFAULT_STRIPE_SIZE\n\tfor (i = 0; i < osh->nr_pages; i++) {\n\t\tnsh->pages[i] = osh->pages[i];\n\t\tosh->pages[i] = NULL;\n\t}\n#endif\n\t\tfor(i=0; i<conf->pool_size; i++) {\n\t\t\tnsh->dev[i].page = osh->dev[i].page;\n\t\t\tnsh->dev[i].orig_page = osh->dev[i].page;\n\t\t\tnsh->dev[i].offset = osh->dev[i].offset;\n\t\t}\n\t\tnsh->hash_lock_index = hash;\n\t\tfree_stripe(conf->slab_cache, osh);\n\t\tcnt++;\n\t\tif (cnt >= conf->max_nr_stripes / NR_STRIPE_HASH_LOCKS +\n\t\t    !!((conf->max_nr_stripes % NR_STRIPE_HASH_LOCKS) > hash)) {\n\t\t\thash++;\n\t\t\tcnt = 0;\n\t\t}\n\t}\n\tkmem_cache_destroy(conf->slab_cache);\n\n\t/* Step 3.\n\t * At this point, we are holding all the stripes so the array\n\t * is completely stalled, so now is a good time to resize\n\t * conf->disks and the scribble region\n\t */\n\tndisks = kcalloc(newsize, sizeof(struct disk_info), GFP_NOIO);\n\tif (ndisks) {\n\t\tfor (i = 0; i < conf->pool_size; i++)\n\t\t\tndisks[i] = conf->disks[i];\n\n\t\tfor (i = conf->pool_size; i < newsize; i++) {\n\t\t\tndisks[i].extra_page = alloc_page(GFP_NOIO);\n\t\t\tif (!ndisks[i].extra_page)\n\t\t\t\terr = -ENOMEM;\n\t\t}\n\n\t\tif (err) {\n\t\t\tfor (i = conf->pool_size; i < newsize; i++)\n\t\t\t\tif (ndisks[i].extra_page)\n\t\t\t\t\tput_page(ndisks[i].extra_page);\n\t\t\tkfree(ndisks);\n\t\t} else {\n\t\t\tkfree(conf->disks);\n\t\t\tconf->disks = ndisks;\n\t\t}\n\t} else\n\t\terr = -ENOMEM;\n\n\tconf->slab_cache = sc;\n\tconf->active_name = 1-conf->active_name;\n\n\t/* Step 4, return new stripes to service */\n\twhile(!list_empty(&newstripes)) {\n\t\tnsh = list_entry(newstripes.next, struct stripe_head, lru);\n\t\tlist_del_init(&nsh->lru);\n\n#if PAGE_SIZE != DEFAULT_STRIPE_SIZE\n\t\tfor (i = 0; i < nsh->nr_pages; i++) {\n\t\t\tif (nsh->pages[i])\n\t\t\t\tcontinue;\n\t\t\tnsh->pages[i] = alloc_page(GFP_NOIO);\n\t\t\tif (!nsh->pages[i])\n\t\t\t\terr = -ENOMEM;\n\t\t}\n\n\t\tfor (i = conf->raid_disks; i < newsize; i++) {\n\t\t\tif (nsh->dev[i].page)\n\t\t\t\tcontinue;\n\t\t\tnsh->dev[i].page = raid5_get_dev_page(nsh, i);\n\t\t\tnsh->dev[i].orig_page = nsh->dev[i].page;\n\t\t\tnsh->dev[i].offset = raid5_get_page_offset(nsh, i);\n\t\t}\n#else\n\t\tfor (i=conf->raid_disks; i < newsize; i++)\n\t\t\tif (nsh->dev[i].page == NULL) {\n\t\t\t\tstruct page *p = alloc_page(GFP_NOIO);\n\t\t\t\tnsh->dev[i].page = p;\n\t\t\t\tnsh->dev[i].orig_page = p;\n\t\t\t\tnsh->dev[i].offset = 0;\n\t\t\t\tif (!p)\n\t\t\t\t\terr = -ENOMEM;\n\t\t\t}\n#endif\n\t\traid5_release_stripe(nsh);\n\t}\n\t/* critical section pass, GFP_NOIO no longer needed */\n\n\tif (!err)\n\t\tconf->pool_size = newsize;\n\tmutex_unlock(&conf->cache_size_mutex);\n\n\treturn err;\n}",
        "static int dtReadFirst(struct inode *ip, struct btstack * btstack)\n{\n\tint rc = 0;\n\ts64 bn;\n\tint psize = 288;\t/* initial in-line directory */": "static int dtReadFirst(struct inode *ip, struct btstack * btstack)\n{\n\tint rc = 0;\n\ts64 bn;\n\tint psize = 288;\t/* initial in-line directory */\n\tstruct metapage *mp;\n\tdtpage_t *p;\n\ts8 *stbl;\n\tstruct btframe *btsp;\n\tpxd_t *xd;\n\n\tBT_CLR(btstack);\t/* reset stack */\n\n\t/*\n\t *\tdescend leftmost path of the tree\n\t *\n\t * by convention, root bn = 0.\n\t */\n\tfor (bn = 0;;) {\n\t\tDT_GETPAGE(ip, bn, mp, psize, p, rc);\n\t\tif (rc)\n\t\t\treturn rc;\n\n\t\t/*\n\t\t * leftmost leaf page\n\t\t */\n\t\tif (p->header.flag & BT_LEAF) {\n\t\t\t/* return leftmost entry */\n\t\t\tbtsp = btstack->top;\n\t\t\tbtsp->bn = bn;\n\t\t\tbtsp->index = 0;\n\t\t\tbtsp->mp = mp;\n\n\t\t\treturn 0;\n\t\t}\n\n\t\t/*\n\t\t * descend down to leftmost child page\n\t\t */\n\t\tif (BT_STACK_FULL(btstack)) {\n\t\t\tDT_PUTPAGE(mp);\n\t\t\tjfs_error(ip->i_sb, \"btstack overrun\\n\");\n\t\t\tBT_STACK_DUMP(btstack);\n\t\t\treturn -EIO;\n\t\t}\n\t\t/* push (bn, index) of the parent page/entry */\n\t\tBT_PUSH(btstack, bn, 0);\n\n\t\t/* get the leftmost entry */\n\t\tstbl = DT_GETSTBL(p);\n\t\txd = (pxd_t *) & p->slot[stbl[0]];\n\n\t\t/* get the child page block address */\n\t\tbn = addressPXD(xd);\n\t\tpsize = lengthPXD(xd) << JFS_SBI(ip->i_sb)->l2bsize;\n\n\t\t/* unpin the parent page */\n\t\tDT_PUTPAGE(mp);\n\t}\n}",
        "static void __netif_receive_skb_list_core(struct list_head *head, bool pfmemalloc)\n{\n\t/* Fast-path assumptions:\n\t * - There is no RX handler.\n\t * - Only one packet_type matches.": "static void __netif_receive_skb_list_core(struct list_head *head, bool pfmemalloc)\n{\n\t/* Fast-path assumptions:\n\t * - There is no RX handler.\n\t * - Only one packet_type matches.\n\t * If either of these fails, we will end up doing some per-packet\n\t * processing in-line, then handling the 'last ptype' for the whole\n\t * sublist.  This can't cause out-of-order delivery to any single ptype,\n\t * because the 'last ptype' must be constant across the sublist, and all\n\t * other ptypes are handled per-packet.\n\t */\n\t/* Current (common) ptype of sublist */\n\tstruct packet_type *pt_curr = NULL;\n\t/* Current (common) orig_dev of sublist */\n\tstruct net_device *od_curr = NULL;\n\tstruct list_head sublist;\n\tstruct sk_buff *skb, *next;\n\n\tINIT_LIST_HEAD(&sublist);\n\tlist_for_each_entry_safe(skb, next, head, list) {\n\t\tstruct net_device *orig_dev = skb->dev;\n\t\tstruct packet_type *pt_prev = NULL;\n\n\t\tskb_list_del_init(skb);\n\t\t__netif_receive_skb_core(&skb, pfmemalloc, &pt_prev);\n\t\tif (!pt_prev)\n\t\t\tcontinue;\n\t\tif (pt_curr != pt_prev || od_curr != orig_dev) {\n\t\t\t/* dispatch old sublist */\n\t\t\t__netif_receive_skb_list_ptype(&sublist, pt_curr, od_curr);\n\t\t\t/* start new sublist */\n\t\t\tINIT_LIST_HEAD(&sublist);\n\t\t\tpt_curr = pt_prev;\n\t\t\tod_curr = orig_dev;\n\t\t}\n\t\tlist_add_tail(&skb->list, &sublist);\n\t}\n\n\t/* dispatch final sublist */\n\t__netif_receive_skb_list_ptype(&sublist, pt_curr, od_curr);\n}",
        "static int imgu_css_pipeline_init(struct imgu_css *css, unsigned int pipe)\n{\n\tstatic const int BYPC = 2;\t/* Bytes per component */\n\tstatic const struct imgu_abi_buffer_sp buffer_sp_init = {\n\t\t.buf_src = {.queue_id = IMGU_ABI_QUEUE_EVENT_ID},": "static int imgu_css_pipeline_init(struct imgu_css *css, unsigned int pipe)\n{\n\tstatic const int BYPC = 2;\t/* Bytes per component */\n\tstatic const struct imgu_abi_buffer_sp buffer_sp_init = {\n\t\t.buf_src = {.queue_id = IMGU_ABI_QUEUE_EVENT_ID},\n\t\t.buf_type = IMGU_ABI_BUFFER_TYPE_INVALID,\n\t};\n\n\tstruct imgu_abi_isp_iterator_config *cfg_iter;\n\tstruct imgu_abi_isp_ref_config *cfg_ref;\n\tstruct imgu_abi_isp_dvs_config *cfg_dvs;\n\tstruct imgu_abi_isp_tnr3_config *cfg_tnr;\n\tstruct imgu_abi_isp_ref_dmem_state *cfg_ref_state;\n\tstruct imgu_abi_isp_tnr3_dmem_state *cfg_tnr_state;\n\n\tconst int stage = 0;\n\tunsigned int i, j;\n\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tstruct imgu_css_queue *css_queue_in =\n\t\t\t&css_pipe->queue[IPU3_CSS_QUEUE_IN];\n\tstruct imgu_css_queue *css_queue_out =\n\t\t\t&css_pipe->queue[IPU3_CSS_QUEUE_OUT];\n\tstruct imgu_css_queue *css_queue_vf =\n\t\t\t&css_pipe->queue[IPU3_CSS_QUEUE_VF];\n\tconst struct imgu_fw_info *bi =\n\t\t\t&css->fwp->binary_header[css_pipe->bindex];\n\tconst unsigned int stripes = bi->info.isp.sp.iterator.num_stripes;\n\n\tstruct imgu_fw_config_memory_offsets *cofs = (void *)css->fwp +\n\t\tbi->blob.memory_offsets.offsets[IMGU_ABI_PARAM_CLASS_CONFIG];\n\tstruct imgu_fw_state_memory_offsets *sofs = (void *)css->fwp +\n\t\tbi->blob.memory_offsets.offsets[IMGU_ABI_PARAM_CLASS_STATE];\n\n\tstruct imgu_abi_isp_stage *isp_stage;\n\tstruct imgu_abi_sp_stage *sp_stage;\n\tstruct imgu_abi_sp_group *sp_group;\n\tstruct imgu_abi_frames_sp *frames_sp;\n\tstruct imgu_abi_frame_sp *frame_sp;\n\tstruct imgu_abi_frame_sp_info *frame_sp_info;\n\n\tconst unsigned int bds_width_pad =\n\t\t\t\tALIGN(css_pipe->rect[IPU3_CSS_RECT_BDS].width,\n\t\t\t\t      2 * IPU3_UAPI_ISP_VEC_ELEMS);\n\n\tconst enum imgu_abi_memories m0 = IMGU_ABI_MEM_ISP_DMEM0;\n\tenum imgu_abi_param_class cfg = IMGU_ABI_PARAM_CLASS_CONFIG;\n\tvoid *vaddr = css_pipe->binary_params_cs[cfg - 1][m0].vaddr;\n\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);\n\n\tdev_dbg(css->dev, \"%s for pipe %d\", __func__, pipe);\n\n\t/* Configure iterator */\n\n\tcfg_iter = imgu_css_fw_pipeline_params(css, pipe, cfg, m0,\n\t\t\t\t\t       &cofs->dmem.iterator,\n\t\t\t\t\t       sizeof(*cfg_iter), vaddr);\n\tif (!cfg_iter)\n\t\tgoto bad_firmware;\n\n\tframe_sp_info = &cfg_iter->input_info;\n\tframe_sp_info->res.width\t= css_queue_in->fmt.mpix.width;\n\tframe_sp_info->res.height\t= css_queue_in->fmt.mpix.height;\n\tframe_sp_info->padded_width\t= css_queue_in->width_pad;\n\tframe_sp_info->format\t\t= css_queue_in->css_fmt->frame_format;\n\tframe_sp_info->raw_bit_depth\t= css_queue_in->css_fmt->bit_depth;\n\tframe_sp_info->raw_bayer_order\t= css_queue_in->css_fmt->bayer_order;\n\tframe_sp_info->raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\n\tframe_sp_info = &cfg_iter->internal_info;\n\tframe_sp_info->res.width = css_pipe->rect[IPU3_CSS_RECT_BDS].width;\n\tframe_sp_info->res.height = css_pipe->rect[IPU3_CSS_RECT_BDS].height;\n\tframe_sp_info->padded_width\t= bds_width_pad;\n\tframe_sp_info->format\t\t= css_queue_out->css_fmt->frame_format;\n\tframe_sp_info->raw_bit_depth\t= css_queue_out->css_fmt->bit_depth;\n\tframe_sp_info->raw_bayer_order\t= css_queue_out->css_fmt->bayer_order;\n\tframe_sp_info->raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\n\tframe_sp_info = &cfg_iter->output_info;\n\tframe_sp_info->res.width\t= css_queue_out->fmt.mpix.width;\n\tframe_sp_info->res.height\t= css_queue_out->fmt.mpix.height;\n\tframe_sp_info->padded_width\t= css_queue_out->width_pad;\n\tframe_sp_info->format\t\t= css_queue_out->css_fmt->frame_format;\n\tframe_sp_info->raw_bit_depth\t= css_queue_out->css_fmt->bit_depth;\n\tframe_sp_info->raw_bayer_order\t= css_queue_out->css_fmt->bayer_order;\n\tframe_sp_info->raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\n\tframe_sp_info = &cfg_iter->vf_info;\n\tframe_sp_info->res.width\t= css_queue_vf->fmt.mpix.width;\n\tframe_sp_info->res.height\t= css_queue_vf->fmt.mpix.height;\n\tframe_sp_info->padded_width\t= css_queue_vf->width_pad;\n\tframe_sp_info->format\t\t= css_queue_vf->css_fmt->frame_format;\n\tframe_sp_info->raw_bit_depth\t= css_queue_vf->css_fmt->bit_depth;\n\tframe_sp_info->raw_bayer_order\t= css_queue_vf->css_fmt->bayer_order;\n\tframe_sp_info->raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\n\tcfg_iter->dvs_envelope.width =\n\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_ENVELOPE].width;\n\tcfg_iter->dvs_envelope.height =\n\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_ENVELOPE].height;\n\n\t/* Configure reference (delay) frames */\n\n\tcfg_ref = imgu_css_fw_pipeline_params(css, pipe, cfg, m0,\n\t\t\t\t\t      &cofs->dmem.ref,\n\t\t\t\t\t      sizeof(*cfg_ref), vaddr);\n\tif (!cfg_ref)\n\t\tgoto bad_firmware;\n\n\tcfg_ref->port_b.crop = 0;\n\tcfg_ref->port_b.elems = IMGU_ABI_ISP_DDR_WORD_BYTES / BYPC;\n\tcfg_ref->port_b.width =\n\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].width;\n\tcfg_ref->port_b.stride =\n\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].bytesperline;\n\tcfg_ref->width_a_over_b =\n\t\t\t\tIPU3_UAPI_ISP_VEC_ELEMS / cfg_ref->port_b.elems;\n\tcfg_ref->dvs_frame_delay = IPU3_CSS_AUX_FRAMES - 1;\n\tfor (i = 0; i < IPU3_CSS_AUX_FRAMES; i++) {\n\t\tcfg_ref->ref_frame_addr_y[i] =\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].mem[i].daddr;\n\t\tcfg_ref->ref_frame_addr_c[i] =\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].mem[i].daddr +\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].bytesperline *\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_REF].height;\n\t}\n\tfor (; i < IMGU_ABI_FRAMES_REF; i++) {\n\t\tcfg_ref->ref_frame_addr_y[i] = 0;\n\t\tcfg_ref->ref_frame_addr_c[i] = 0;\n\t}\n\n\t/* Configure DVS (digital video stabilization) */\n\n\tcfg_dvs = imgu_css_fw_pipeline_params(css, pipe, cfg, m0,\n\t\t\t\t\t      &cofs->dmem.dvs, sizeof(*cfg_dvs),\n\t\t\t\t\t      vaddr);\n\tif (!cfg_dvs)\n\t\tgoto bad_firmware;\n\n\tcfg_dvs->num_horizontal_blocks =\n\t\t\tALIGN(DIV_ROUND_UP(css_pipe->rect[IPU3_CSS_RECT_GDC].width,\n\t\t\t\t\t   IMGU_DVS_BLOCK_W), 2);\n\tcfg_dvs->num_vertical_blocks =\n\t\t\tDIV_ROUND_UP(css_pipe->rect[IPU3_CSS_RECT_GDC].height,\n\t\t\t\t     IMGU_DVS_BLOCK_H);\n\n\t/* Configure TNR (temporal noise reduction) */\n\n\tif (css_pipe->pipe_id == IPU3_CSS_PIPE_ID_VIDEO) {\n\t\tcfg_tnr = imgu_css_fw_pipeline_params(css, pipe, cfg, m0,\n\t\t\t\t\t\t      &cofs->dmem.tnr3,\n\t\t\t\t\t\t      sizeof(*cfg_tnr),\n\t\t\t\t\t\t      vaddr);\n\t\tif (!cfg_tnr)\n\t\t\tgoto bad_firmware;\n\n\t\tcfg_tnr->port_b.crop = 0;\n\t\tcfg_tnr->port_b.elems = IMGU_ABI_ISP_DDR_WORD_BYTES;\n\t\tcfg_tnr->port_b.width =\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].width;\n\t\tcfg_tnr->port_b.stride =\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].bytesperline;\n\t\tcfg_tnr->width_a_over_b =\n\t\t\tIPU3_UAPI_ISP_VEC_ELEMS / cfg_tnr->port_b.elems;\n\t\tcfg_tnr->frame_height =\n\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR].height;\n\t\tcfg_tnr->delay_frame = IPU3_CSS_AUX_FRAMES - 1;\n\t\tfor (i = 0; i < IPU3_CSS_AUX_FRAMES; i++)\n\t\t\tcfg_tnr->frame_addr[i] =\n\t\t\t\tcss_pipe->aux_frames[IPU3_CSS_AUX_FRAME_TNR]\n\t\t\t\t\t.mem[i].daddr;\n\t\tfor (; i < IMGU_ABI_FRAMES_TNR; i++)\n\t\t\tcfg_tnr->frame_addr[i] = 0;\n\t}\n\n\t/* Configure ref dmem state parameters */\n\n\tcfg = IMGU_ABI_PARAM_CLASS_STATE;\n\tvaddr = css_pipe->binary_params_cs[cfg - 1][m0].vaddr;\n\n\tcfg_ref_state = imgu_css_fw_pipeline_params(css, pipe, cfg, m0,\n\t\t\t\t\t\t    &sofs->dmem.ref,\n\t\t\t\t\t\t    sizeof(*cfg_ref_state),\n\t\t\t\t\t\t    vaddr);\n\tif (!cfg_ref_state)\n\t\tgoto bad_firmware;\n\n\tcfg_ref_state->ref_in_buf_idx = 0;\n\tcfg_ref_state->ref_out_buf_idx = 1;\n\n\t/* Configure tnr dmem state parameters */\n\tif (css_pipe->pipe_id == IPU3_CSS_PIPE_ID_VIDEO) {\n\t\tcfg_tnr_state =\n\t\t\timgu_css_fw_pipeline_params(css, pipe, cfg, m0,\n\t\t\t\t\t\t    &sofs->dmem.tnr3,\n\t\t\t\t\t\t    sizeof(*cfg_tnr_state),\n\t\t\t\t\t\t    vaddr);\n\t\tif (!cfg_tnr_state)\n\t\t\tgoto bad_firmware;\n\n\t\tcfg_tnr_state->in_bufidx = 0;\n\t\tcfg_tnr_state->out_bufidx = 1;\n\t\tcfg_tnr_state->bypass_filter = 0;\n\t\tcfg_tnr_state->total_frame_counter = 0;\n\t\tfor (i = 0; i < IMGU_ABI_BUF_SETS_TNR; i++)\n\t\t\tcfg_tnr_state->buffer_frame_counter[i] = 0;\n\t}\n\n\t/* Configure ISP stage */\n\n\tisp_stage = css_pipe->xmem_isp_stage_ptrs[pipe][stage].vaddr;\n\tmemset(isp_stage, 0, sizeof(*isp_stage));\n\tisp_stage->blob_info = bi->blob;\n\tisp_stage->binary_info = bi->info.isp.sp;\n\tstrscpy(isp_stage->binary_name,\n\t\t(char *)css->fwp + bi->blob.prog_name_offset,\n\t\tsizeof(isp_stage->binary_name));\n\tisp_stage->mem_initializers = bi->info.isp.sp.mem_initializers;\n\tfor (i = IMGU_ABI_PARAM_CLASS_CONFIG; i < IMGU_ABI_PARAM_CLASS_NUM; i++)\n\t\tfor (j = 0; j < IMGU_ABI_NUM_MEMORIES; j++)\n\t\t\tisp_stage->mem_initializers.params[i][j].address =\n\t\t\t\t\tcss_pipe->binary_params_cs[i - 1][j].daddr;\n\n\t/* Configure SP stage */\n\n\tsp_stage = css_pipe->xmem_sp_stage_ptrs[pipe][stage].vaddr;\n\tmemset(sp_stage, 0, sizeof(*sp_stage));\n\n\tframes_sp = &sp_stage->frames;\n\tframes_sp->in.buf_attr = buffer_sp_init;\n\tfor (i = 0; i < IMGU_ABI_BINARY_MAX_OUTPUT_PORTS; i++)\n\t\tframes_sp->out[i].buf_attr = buffer_sp_init;\n\tframes_sp->out_vf.buf_attr = buffer_sp_init;\n\tframes_sp->s3a_buf = buffer_sp_init;\n\tframes_sp->dvs_buf = buffer_sp_init;\n\n\tsp_stage->stage_type = IMGU_ABI_STAGE_TYPE_ISP;\n\tsp_stage->num = stage;\n\tsp_stage->isp_online = 0;\n\tsp_stage->isp_copy_vf = 0;\n\tsp_stage->isp_copy_output = 0;\n\n\tsp_stage->enable.vf_output = css_pipe->vf_output_en;\n\n\tframes_sp->effective_in_res.width =\n\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_EFFECTIVE].width;\n\tframes_sp->effective_in_res.height =\n\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_EFFECTIVE].height;\n\n\tframe_sp = &frames_sp->in;\n\tframe_sp->info.res.width\t= css_queue_in->fmt.mpix.width;\n\tframe_sp->info.res.height\t= css_queue_in->fmt.mpix.height;\n\tframe_sp->info.padded_width\t= css_queue_in->width_pad;\n\tframe_sp->info.format\t\t= css_queue_in->css_fmt->frame_format;\n\tframe_sp->info.raw_bit_depth\t= css_queue_in->css_fmt->bit_depth;\n\tframe_sp->info.raw_bayer_order\t= css_queue_in->css_fmt->bayer_order;\n\tframe_sp->info.raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\tframe_sp->buf_attr.buf_src.queue_id = IMGU_ABI_QUEUE_C_ID;\n\tframe_sp->buf_attr.buf_type\t= IMGU_ABI_BUFFER_TYPE_INPUT_FRAME;\n\n\tframe_sp = &frames_sp->out[0];\n\tframe_sp->info.res.width\t= css_queue_out->fmt.mpix.width;\n\tframe_sp->info.res.height\t= css_queue_out->fmt.mpix.height;\n\tframe_sp->info.padded_width\t= css_queue_out->width_pad;\n\tframe_sp->info.format\t\t= css_queue_out->css_fmt->frame_format;\n\tframe_sp->info.raw_bit_depth\t= css_queue_out->css_fmt->bit_depth;\n\tframe_sp->info.raw_bayer_order\t= css_queue_out->css_fmt->bayer_order;\n\tframe_sp->info.raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\tframe_sp->planes.nv.uv.offset\t= css_queue_out->width_pad *\n\t\t\t\t\t  css_queue_out->fmt.mpix.height;\n\tframe_sp->buf_attr.buf_src.queue_id = IMGU_ABI_QUEUE_D_ID;\n\tframe_sp->buf_attr.buf_type\t= IMGU_ABI_BUFFER_TYPE_OUTPUT_FRAME;\n\n\tframe_sp = &frames_sp->out[1];\n\tframe_sp->buf_attr.buf_src.queue_id = IMGU_ABI_QUEUE_EVENT_ID;\n\n\tframe_sp_info = &frames_sp->internal_frame_info;\n\tframe_sp_info->res.width = css_pipe->rect[IPU3_CSS_RECT_BDS].width;\n\tframe_sp_info->res.height = css_pipe->rect[IPU3_CSS_RECT_BDS].height;\n\tframe_sp_info->padded_width\t= bds_width_pad;\n\tframe_sp_info->format\t\t= css_queue_out->css_fmt->frame_format;\n\tframe_sp_info->raw_bit_depth\t= css_queue_out->css_fmt->bit_depth;\n\tframe_sp_info->raw_bayer_order\t= css_queue_out->css_fmt->bayer_order;\n\tframe_sp_info->raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\n\tframe_sp = &frames_sp->out_vf;\n\tframe_sp->info.res.width\t= css_queue_vf->fmt.mpix.width;\n\tframe_sp->info.res.height\t= css_queue_vf->fmt.mpix.height;\n\tframe_sp->info.padded_width\t= css_queue_vf->width_pad;\n\tframe_sp->info.format\t\t= css_queue_vf->css_fmt->frame_format;\n\tframe_sp->info.raw_bit_depth\t= css_queue_vf->css_fmt->bit_depth;\n\tframe_sp->info.raw_bayer_order\t= css_queue_vf->css_fmt->bayer_order;\n\tframe_sp->info.raw_type\t\t= IMGU_ABI_RAW_TYPE_BAYER;\n\tframe_sp->planes.yuv.u.offset\t= css_queue_vf->width_pad *\n\t\t\t\t\t  css_queue_vf->fmt.mpix.height;\n\tframe_sp->planes.yuv.v.offset\t= css_queue_vf->width_pad *\n\t\t\t\t\t  css_queue_vf->fmt.mpix.height * 5 / 4;\n\tframe_sp->buf_attr.buf_src.queue_id = IMGU_ABI_QUEUE_E_ID;\n\tframe_sp->buf_attr.buf_type\t= IMGU_ABI_BUFFER_TYPE_VF_OUTPUT_FRAME;\n\n\tframes_sp->s3a_buf.buf_src.queue_id = IMGU_ABI_QUEUE_F_ID;\n\tframes_sp->s3a_buf.buf_type\t= IMGU_ABI_BUFFER_TYPE_3A_STATISTICS;\n\n\tframes_sp->dvs_buf.buf_src.queue_id = IMGU_ABI_QUEUE_G_ID;\n\tframes_sp->dvs_buf.buf_type\t= IMGU_ABI_BUFFER_TYPE_DIS_STATISTICS;\n\n\tsp_stage->dvs_envelope.width =\n\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_ENVELOPE].width;\n\tsp_stage->dvs_envelope.height =\n\t\t\t\tcss_pipe->rect[IPU3_CSS_RECT_ENVELOPE].height;\n\n\tsp_stage->isp_pipe_version =\n\t\t\t\tbi->info.isp.sp.pipeline.isp_pipe_version;\n\tsp_stage->isp_deci_log_factor =\n\t\t\tclamp(max(fls(css_pipe->rect[IPU3_CSS_RECT_BDS].width /\n\t\t\t\t      IMGU_MAX_BQ_GRID_WIDTH),\n\t\t\t\t  fls(css_pipe->rect[IPU3_CSS_RECT_BDS].height /\n\t\t\t\t      IMGU_MAX_BQ_GRID_HEIGHT)) - 1, 3, 5);\n\tsp_stage->isp_vf_downscale_bits = 0;\n\tsp_stage->if_config_index = 255;\n\tsp_stage->sp_enable_xnr = 0;\n\tsp_stage->num_stripes = stripes;\n\tsp_stage->enable.s3a = 1;\n\tsp_stage->enable.dvs_stats = 0;\n\n\tsp_stage->xmem_bin_addr = css->binary[css_pipe->bindex].daddr;\n\tsp_stage->xmem_map_addr = css_pipe->sp_ddr_ptrs.daddr;\n\tsp_stage->isp_stage_addr =\n\t\tcss_pipe->xmem_isp_stage_ptrs[pipe][stage].daddr;\n\n\t/* Configure SP group */\n\n\tsp_group = css->xmem_sp_group_ptrs.vaddr;\n\tmemset(&sp_group->pipe[pipe], 0, sizeof(struct imgu_abi_sp_pipeline));\n\n\tsp_group->pipe[pipe].num_stages = 1;\n\tsp_group->pipe[pipe].pipe_id = css_pipe->pipe_id;\n\tsp_group->pipe[pipe].thread_id = pipe;\n\tsp_group->pipe[pipe].pipe_num = pipe;\n\tsp_group->pipe[pipe].num_execs = -1;\n\tsp_group->pipe[pipe].pipe_qos_config = -1;\n\tsp_group->pipe[pipe].required_bds_factor = 0;\n\tsp_group->pipe[pipe].dvs_frame_delay = IPU3_CSS_AUX_FRAMES - 1;\n\tsp_group->pipe[pipe].inout_port_config =\n\t\t\t\t\tIMGU_ABI_PORT_CONFIG_TYPE_INPUT_HOST |\n\t\t\t\t\tIMGU_ABI_PORT_CONFIG_TYPE_OUTPUT_HOST;\n\tsp_group->pipe[pipe].scaler_pp_lut = 0;\n\tsp_group->pipe[pipe].shading.internal_frame_origin_x_bqs_on_sctbl = 0;\n\tsp_group->pipe[pipe].shading.internal_frame_origin_y_bqs_on_sctbl = 0;\n\tsp_group->pipe[pipe].sp_stage_addr[stage] =\n\t\t\tcss_pipe->xmem_sp_stage_ptrs[pipe][stage].daddr;\n\tsp_group->pipe[pipe].pipe_config =\n\t\t\tbi->info.isp.sp.enable.params ? (1 << pipe) : 0;\n\tsp_group->pipe[pipe].pipe_config |= IMGU_ABI_PIPE_CONFIG_ACQUIRE_ISP;\n\n\t/* Initialize parameter pools */\n\n\tif (imgu_css_pool_init(imgu, &css_pipe->pool.parameter_set_info,\n\t\t\t       sizeof(struct imgu_abi_parameter_set_info)) ||\n\t    imgu_css_pool_init(imgu, &css_pipe->pool.acc,\n\t\t\t       sizeof(struct imgu_abi_acc_param)) ||\n\t    imgu_css_pool_init(imgu, &css_pipe->pool.gdc,\n\t\t\t       sizeof(struct imgu_abi_gdc_warp_param) *\n\t\t\t       3 * cfg_dvs->num_horizontal_blocks / 2 *\n\t\t\t       cfg_dvs->num_vertical_blocks) ||\n\t    imgu_css_pool_init(imgu, &css_pipe->pool.obgrid,\n\t\t\t       imgu_css_fw_obgrid_size(\n\t\t\t       &css->fwp->binary_header[css_pipe->bindex])))\n\t\tgoto out_of_memory;\n\n\tfor (i = 0; i < IMGU_ABI_NUM_MEMORIES; i++)\n\t\tif (imgu_css_pool_init(imgu,\n\t\t\t\t       &css_pipe->pool.binary_params_p[i],\n\t\t\t\t       bi->info.isp.sp.mem_initializers.params\n\t\t\t\t       [IMGU_ABI_PARAM_CLASS_PARAM][i].size))\n\t\t\tgoto out_of_memory;\n\n\treturn 0;\n\nbad_firmware:\n\timgu_css_pipeline_cleanup(css, pipe);\n\treturn -EPROTO;\n\nout_of_memory:\n\timgu_css_pipeline_cleanup(css, pipe);\n\treturn -ENOMEM;\n}",
        "static void vidtv_s302m_write_frames(struct vidtv_encoder *e)\n{\n\tstruct vidtv_access_unit *au = e->access_units;\n\tstruct vidtv_s302m_ctx *ctx = e->ctx;\n\tu32 nbytes_per_unit = 0;": "static void vidtv_s302m_write_frames(struct vidtv_encoder *e)\n{\n\tstruct vidtv_access_unit *au = e->access_units;\n\tstruct vidtv_s302m_ctx *ctx = e->ctx;\n\tu32 nbytes_per_unit = 0;\n\tu32 nbytes = 0;\n\tu32 au_sz = 0;\n\tu16 sample;\n\tu32 j;\n\n\twhile (au) {\n\t\tau_sz = au->num_samples *\n\t\t\tsizeof(struct vidtv_s302m_frame_16);\n\n\t\tnbytes_per_unit = vidtv_s302m_write_h(e, au_sz);\n\n\t\tfor (j = 0; j < au->num_samples; ++j) {\n\t\t\tsample = vidtv_s302m_get_sample(e);\n\t\t\tnbytes_per_unit += vidtv_s302m_write_frame(e, sample);\n\n\t\t\tif (e->src_buf)\n\t\t\t\te->src_buf_offset += sizeof(u16);\n\n\t\t\te->sample_count++;\n\t\t}\n\n\t\tau->nbytes = nbytes_per_unit;\n\n\t\tif (au_sz + sizeof(struct vidtv_smpte_s302m_es) != nbytes_per_unit) {\n\t\t\tpr_warn_ratelimited(\"write size was %u, expected %zu\\n\",\n\t\t\t\t\t    nbytes_per_unit,\n\t\t\t\t\t    au_sz + sizeof(struct vidtv_smpte_s302m_es));\n\t\t}\n\n\t\tnbytes += nbytes_per_unit;\n\t\tau->offset = nbytes - nbytes_per_unit;\n\n\t\tnbytes_per_unit = 0;\n\t\tctx->au_count++;\n\n\t\tau = au->next;\n\t}\n}",
        "static int task_fn_mbox_2(struct anybuss_host *cd, struct ab_task *t)\n{\n\tstruct mbox_priv *pd = &t->mbox_pd;\n\tunsigned int ind_ap;\n": "static int task_fn_mbox_2(struct anybuss_host *cd, struct ab_task *t)\n{\n\tstruct mbox_priv *pd = &t->mbox_pd;\n\tunsigned int ind_ap;\n\n\tif (!cd->power_on)\n\t\treturn -EIO;\n\tregmap_read(cd->regmap, REG_IND_AP, &ind_ap);\n\tif (((atomic_read(&cd->ind_ab) ^ ind_ap) & IND_AX_MOUT) == 0) {\n\t\t/* output message not here */\n\t\tif (time_after(jiffies, t->start_jiffies + TIMEOUT))\n\t\t\treturn -ETIMEDOUT;\n\t\treturn -EINPROGRESS;\n\t}\n\t/* grab the returned header and msg */\n\tregmap_bulk_read(cd->regmap, MBOX_OUT_AREA, &pd->hdr,\n\t\t\t sizeof(pd->hdr));\n\tregmap_bulk_read(cd->regmap, MBOX_OUT_AREA + sizeof(pd->hdr),\n\t\t\t pd->msg, pd->msg_in_sz);\n\t/* tell anybus we've consumed the message */\n\tind_ap ^= IND_AX_MOUT;\n\treturn write_ind_ap(cd->regmap, ind_ap);\n}",
        "static int init_bios_attributes(int attr_type, const char *guid)\n{\n\tstruct kobject *attr_name_kobj; //individual attribute names\n\tunion acpi_object *obj = NULL;\n\tunion acpi_object *elements;": "static int init_bios_attributes(int attr_type, const char *guid)\n{\n\tstruct kobject *attr_name_kobj; //individual attribute names\n\tunion acpi_object *obj = NULL;\n\tunion acpi_object *elements;\n\tstruct kset *tmp_set;\n\tint min_elements;\n\n\t/* instance_id needs to be reset for each type GUID\n\t * also, instance IDs are unique within GUID but not across\n\t */\n\tint instance_id = 0;\n\tint retval = 0;\n\n\tretval = alloc_attributes_data(attr_type);\n\tif (retval)\n\t\treturn retval;\n\n\tswitch (attr_type) {\n\tcase ENUM:\tmin_elements = 8;\tbreak;\n\tcase INT:\tmin_elements = 9;\tbreak;\n\tcase STR:\tmin_elements = 8;\tbreak;\n\tcase PO:\tmin_elements = 4;\tbreak;\n\tdefault:\n\t\tpr_err(\"Error: Unknown attr_type: %d\\n\", attr_type);\n\t\treturn -EINVAL;\n\t}\n\n\t/* need to use specific instance_id and guid combination to get right data */\n\tobj = get_wmiobj_pointer(instance_id, guid);\n\tif (!obj)\n\t\treturn -ENODEV;\n\n\tmutex_lock(&wmi_priv.mutex);\n\twhile (obj) {\n\t\tif (obj->type != ACPI_TYPE_PACKAGE) {\n\t\t\tpr_err(\"Error: Expected ACPI-package type, got: %d\\n\", obj->type);\n\t\t\tretval = -EIO;\n\t\t\tgoto err_attr_init;\n\t\t}\n\n\t\tif (obj->package.count < min_elements) {\n\t\t\tpr_err(\"Error: ACPI-package does not have enough elements: %d < %d\\n\",\n\t\t\t       obj->package.count, min_elements);\n\t\t\tgoto nextobj;\n\t\t}\n\n\t\telements = obj->package.elements;\n\n\t\t/* sanity checking */\n\t\tif (elements[ATTR_NAME].type != ACPI_TYPE_STRING) {\n\t\t\tpr_debug(\"incorrect element type\\n\");\n\t\t\tgoto nextobj;\n\t\t}\n\t\tif (strlen(elements[ATTR_NAME].string.pointer) == 0) {\n\t\t\tpr_debug(\"empty attribute found\\n\");\n\t\t\tgoto nextobj;\n\t\t}\n\t\tif (attr_type == PO)\n\t\t\ttmp_set = wmi_priv.authentication_dir_kset;\n\t\telse\n\t\t\ttmp_set = wmi_priv.main_dir_kset;\n\n\t\tif (kset_find_obj(tmp_set, elements[ATTR_NAME].string.pointer)) {\n\t\t\tpr_debug(\"duplicate attribute name found - %s\\n\",\n\t\t\t\telements[ATTR_NAME].string.pointer);\n\t\t\tgoto nextobj;\n\t\t}\n\n\t\t/* build attribute */\n\t\tattr_name_kobj = kzalloc(sizeof(*attr_name_kobj), GFP_KERNEL);\n\t\tif (!attr_name_kobj) {\n\t\t\tretval = -ENOMEM;\n\t\t\tgoto err_attr_init;\n\t\t}\n\n\t\tattr_name_kobj->kset = tmp_set;\n\n\t\tretval = kobject_init_and_add(attr_name_kobj, &attr_name_ktype, NULL, \"%s\",\n\t\t\t\t\t\telements[ATTR_NAME].string.pointer);\n\t\tif (retval) {\n\t\t\tkobject_put(attr_name_kobj);\n\t\t\tgoto err_attr_init;\n\t\t}\n\n\t\t/* enumerate all of this attribute */\n\t\tswitch (attr_type) {\n\t\tcase ENUM:\n\t\t\tretval = populate_enum_data(elements, instance_id, attr_name_kobj,\n\t\t\t\t\tobj->package.count);\n\t\t\tbreak;\n\t\tcase INT:\n\t\t\tretval = populate_int_data(elements, instance_id, attr_name_kobj);\n\t\t\tbreak;\n\t\tcase STR:\n\t\t\tretval = populate_str_data(elements, instance_id, attr_name_kobj);\n\t\t\tbreak;\n\t\tcase PO:\n\t\t\tretval = populate_po_data(elements, instance_id, attr_name_kobj);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tif (retval) {\n\t\t\tpr_debug(\"failed to populate %s\\n\",\n\t\t\t\telements[ATTR_NAME].string.pointer);\n\t\t\tgoto err_attr_init;\n\t\t}\n\nnextobj:\n\t\tkfree(obj);\n\t\tinstance_id++;\n\t\tobj = get_wmiobj_pointer(instance_id, guid);\n\t}\n\n\tmutex_unlock(&wmi_priv.mutex);\n\treturn 0;\n\nerr_attr_init:\n\tmutex_unlock(&wmi_priv.mutex);\n\tkfree(obj);\n\treturn retval;\n}",
        "static int load_bayer_isp_binaries(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_frame_info pre_isp_in_info, *pipe_out_info;\n\tint err = 0;\n\tstruct ia_css_binary_descr pre_de_descr;": "static int load_bayer_isp_binaries(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_frame_info pre_isp_in_info, *pipe_out_info;\n\tint err = 0;\n\tstruct ia_css_binary_descr pre_de_descr;\n\n\tIA_CSS_ENTER_PRIVATE(\"\");\n\tassert(pipe);\n\tassert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE ||\n\t       pipe->mode == IA_CSS_PIPE_ID_COPY);\n\tpipe_out_info = &pipe->output_info[0];\n\n\tif (pipe->pipe_settings.capture.pre_isp_binary.info)\n\t\treturn 0;\n\n\terr = ia_css_frame_check_info(pipe_out_info);\n\tif (err)\n\t\treturn err;\n\n\tia_css_pipe_get_pre_de_binarydesc(pipe, &pre_de_descr,\n\t\t\t\t\t  &pre_isp_in_info,\n\t\t\t\t\t  pipe_out_info);\n\n\terr = ia_css_binary_find(&pre_de_descr,\n\t\t\t\t &pipe->pipe_settings.capture.pre_isp_binary);\n\n\treturn err;\n}",
        "static int bnx2x_process_kill(struct bnx2x *bp, bool global)\n{\n\tint cnt = 1000;\n\tu32 val = 0;\n\tu32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;": "static int bnx2x_process_kill(struct bnx2x *bp, bool global)\n{\n\tint cnt = 1000;\n\tu32 val = 0;\n\tu32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;\n\tu32 tags_63_32 = 0;\n\n\t/* Empty the Tetris buffer, wait for 1s */\n\tdo {\n\t\tsr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);\n\t\tblk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);\n\t\tport_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);\n\t\tport_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);\n\t\tpgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);\n\t\tif (CHIP_IS_E3(bp))\n\t\t\ttags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);\n\n\t\tif ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&\n\t\t    ((port_is_idle_0 & 0x1) == 0x1) &&\n\t\t    ((port_is_idle_1 & 0x1) == 0x1) &&\n\t\t    (pgl_exp_rom2 == 0xffffffff) &&\n\t\t    (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))\n\t\t\tbreak;\n\t\tusleep_range(1000, 2000);\n\t} while (cnt-- > 0);\n\n\tif (cnt <= 0) {\n\t\tBNX2X_ERR(\"Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\\n\");\n\t\tBNX2X_ERR(\"sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\\n\",\n\t\t\t  sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,\n\t\t\t  pgl_exp_rom2);\n\t\treturn -EAGAIN;\n\t}\n\n\tbarrier();\n\n\t/* Close gates #2, #3 and #4 */\n\tbnx2x_set_234_gates(bp, true);\n\n\t/* Poll for IGU VQs for 57712 and newer chips */\n\tif (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))\n\t\treturn -EAGAIN;\n\n\t/* TBD: Indicate that \"process kill\" is in progress to MCP */\n\n\t/* Clear \"unprepared\" bit */\n\tREG_WR(bp, MISC_REG_UNPREPARED, 0);\n\tbarrier();\n\n\t/* Wait for 1ms to empty GLUE and PCI-E core queues,\n\t * PSWHST, GRC and PSWRD Tetris buffer.\n\t */\n\tusleep_range(1000, 2000);\n\n\t/* Prepare to chip reset: */\n\t/* MCP */\n\tif (global)\n\t\tbnx2x_reset_mcp_prep(bp, &val);\n\n\t/* PXP */\n\tbnx2x_pxp_prep(bp);\n\tbarrier();\n\n\t/* reset the chip */\n\tbnx2x_process_kill_chip_reset(bp, global);\n\tbarrier();\n\n\t/* clear errors in PGB */\n\tif (!CHIP_IS_E1x(bp))\n\t\tREG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);\n\n\t/* Recover after reset: */\n\t/* MCP */\n\tif (global && bnx2x_reset_mcp_comp(bp, val))\n\t\treturn -EAGAIN;\n\n\t/* TBD: Add resetting the NO_MCP mode DB here */\n\n\t/* Open the gates #2, #3 and #4 */\n\tbnx2x_set_234_gates(bp, false);\n\n\t/* TBD: IGU/AEU preparation bring back the AEU/IGU to a\n\t * reset state, re-enable attentions. */\n\n\treturn 0;\n}",
        "static int powernv_add_idle_states(void)\n{\n\tint nr_idle_states = 1; /* Snooze */\n\tint dt_idle_states;\n\tu32 has_stop_states = 0;": "static int powernv_add_idle_states(void)\n{\n\tint nr_idle_states = 1; /* Snooze */\n\tint dt_idle_states;\n\tu32 has_stop_states = 0;\n\tint i;\n\tu32 supported_flags = pnv_get_supported_cpuidle_states();\n\n\n\t/* Currently we have snooze statically defined */\n\tif (nr_pnv_idle_states <= 0) {\n\t\tpr_warn(\"cpuidle-powernv : Only Snooze is available\\n\");\n\t\tgoto out;\n\t}\n\n\t/* TODO: Count only states which are eligible for cpuidle */\n\tdt_idle_states = nr_pnv_idle_states;\n\n\t/*\n\t * Since snooze is used as first idle state, max idle states allowed is\n\t * CPUIDLE_STATE_MAX -1\n\t */\n\tif (nr_pnv_idle_states > CPUIDLE_STATE_MAX - 1) {\n\t\tpr_warn(\"cpuidle-powernv: discovered idle states more than allowed\");\n\t\tdt_idle_states = CPUIDLE_STATE_MAX - 1;\n\t}\n\n\t/*\n\t * If the idle states use stop instruction, probe for psscr values\n\t * and psscr mask which are necessary to specify required stop level.\n\t */\n\thas_stop_states = (pnv_idle_states[0].flags &\n\t\t\t   (OPAL_PM_STOP_INST_FAST | OPAL_PM_STOP_INST_DEEP));\n\n\tfor (i = 0; i < dt_idle_states; i++) {\n\t\tunsigned int exit_latency, target_residency;\n\t\tbool stops_timebase = false;\n\t\tstruct pnv_idle_states_t *state = &pnv_idle_states[i];\n\n\t\t/*\n\t\t * Skip the platform idle state whose flag isn't in\n\t\t * the supported_cpuidle_states flag mask.\n\t\t */\n\t\tif ((state->flags & supported_flags) != state->flags)\n\t\t\tcontinue;\n\t\t/*\n\t\t * If an idle state has exit latency beyond\n\t\t * POWERNV_THRESHOLD_LATENCY_NS then don't use it\n\t\t * in cpu-idle.\n\t\t */\n\t\tif (state->latency_ns > POWERNV_THRESHOLD_LATENCY_NS)\n\t\t\tcontinue;\n\t\t/*\n\t\t * Firmware passes residency and latency values in ns.\n\t\t * cpuidle expects it in us.\n\t\t */\n\t\texit_latency = DIV_ROUND_UP(state->latency_ns, 1000);\n\t\ttarget_residency = DIV_ROUND_UP(state->residency_ns, 1000);\n\n\t\tif (has_stop_states && !(state->valid))\n\t\t\t\tcontinue;\n\n\t\tif (state->flags & OPAL_PM_TIMEBASE_STOP)\n\t\t\tstops_timebase = true;\n\n\t\tif (state->flags & OPAL_PM_NAP_ENABLED) {\n\t\t\t/* Add NAP state */\n\t\t\tadd_powernv_state(nr_idle_states, \"Nap\",\n\t\t\t\t\t  CPUIDLE_FLAG_NONE, nap_loop,\n\t\t\t\t\t  target_residency, exit_latency, 0, 0);\n\t\t} else if (has_stop_states && !stops_timebase) {\n\t\t\tadd_powernv_state(nr_idle_states, state->name,\n\t\t\t\t\t  CPUIDLE_FLAG_NONE, stop_loop,\n\t\t\t\t\t  target_residency, exit_latency,\n\t\t\t\t\t  state->psscr_val,\n\t\t\t\t\t  state->psscr_mask);\n\t\t}\n\n\t\t/*\n\t\t * All cpuidle states with CPUIDLE_FLAG_TIMER_STOP set must come\n\t\t * within this config dependency check.\n\t\t */\n#ifdef CONFIG_TICK_ONESHOT\n\t\telse if (state->flags & OPAL_PM_SLEEP_ENABLED ||\n\t\t\t state->flags & OPAL_PM_SLEEP_ENABLED_ER1) {\n\t\t\t/* Add FASTSLEEP state */\n\t\t\tadd_powernv_state(nr_idle_states, \"FastSleep\",\n\t\t\t\t\t  CPUIDLE_FLAG_TIMER_STOP,\n\t\t\t\t\t  fastsleep_loop,\n\t\t\t\t\t  target_residency, exit_latency, 0, 0);\n\t\t} else if (has_stop_states && stops_timebase) {\n\t\t\tadd_powernv_state(nr_idle_states, state->name,\n\t\t\t\t\t  CPUIDLE_FLAG_TIMER_STOP, stop_loop,\n\t\t\t\t\t  target_residency, exit_latency,\n\t\t\t\t\t  state->psscr_val,\n\t\t\t\t\t  state->psscr_mask);\n\t\t}\n#endif\n\t\telse\n\t\t\tcontinue;\n\t\tnr_idle_states++;\n\t}\nout:\n\treturn nr_idle_states;\n}",
        "static void help(char *name)\n{\n\tputs(\"\");\n\tprintf(\"usage: %s [-h] [-i iterations] [-p offset] [-g]\"\n\t       \"[-m mode] [-b vcpu bytes] [-v vcpus] [-o] [-s mem type]\"": "static void help(char *name)\n{\n\tputs(\"\");\n\tprintf(\"usage: %s [-h] [-i iterations] [-p offset] [-g]\"\n\t       \"[-m mode] [-b vcpu bytes] [-v vcpus] [-o] [-s mem type]\"\n\t       \"[-x memslots]\\n\", name);\n\tputs(\"\");\n\tprintf(\" -i: specify iteration counts (default: %\"PRIu64\")\\n\",\n\t       TEST_HOST_LOOP_N);\n\tprintf(\" -g: Do not enable KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2. This\\n\"\n\t       \"     makes KVM_GET_DIRTY_LOG clear the dirty log (i.e.\\n\"\n\t       \"     KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE is not enabled)\\n\"\n\t       \"     and writes will be tracked as soon as dirty logging is\\n\"\n\t       \"     enabled on the memslot (i.e. KVM_DIRTY_LOG_INITIALLY_SET\\n\"\n\t       \"     is not enabled).\\n\");\n\tprintf(\" -p: specify guest physical test memory offset\\n\"\n\t       \"     Warning: a low offset can conflict with the loaded test code.\\n\");\n\tguest_modes_help();\n\tprintf(\" -b: specify the size of the memory region which should be\\n\"\n\t       \"     dirtied by each vCPU. e.g. 10M or 3G.\\n\"\n\t       \"     (default: 1G)\\n\");\n\tprintf(\" -f: specify the fraction of pages which should be written to\\n\"\n\t       \"     as opposed to simply read, in the form\\n\"\n\t       \"     1/<fraction of pages to write>.\\n\"\n\t       \"     (default: 1 i.e. all pages are written to.)\\n\");\n\tprintf(\" -v: specify the number of vCPUs to run.\\n\");\n\tprintf(\" -o: Overlap guest memory accesses instead of partitioning\\n\"\n\t       \"     them into a separate region of memory for each vCPU.\\n\");\n\tbacking_src_help(\"-s\");\n\tprintf(\" -x: Split the memory region into this number of memslots.\\n\"\n\t       \"     (default: 1)\\n\");\n\tputs(\"\");\n\texit(0);\n}",
        "static int lock_torture_writer(void *arg)\n{\n\tstruct lock_stress_stats *lwsp = arg;\n\tint tid = lwsp - cxt.lwsa;\n\tDEFINE_TORTURE_RANDOM(rand);": "static int lock_torture_writer(void *arg)\n{\n\tstruct lock_stress_stats *lwsp = arg;\n\tint tid = lwsp - cxt.lwsa;\n\tDEFINE_TORTURE_RANDOM(rand);\n\n\tVERBOSE_TOROUT_STRING(\"lock_torture_writer task started\");\n\tset_user_nice(current, MAX_NICE);\n\n\tdo {\n\t\tif ((torture_random(&rand) & 0xfffff) == 0)\n\t\t\tschedule_timeout_uninterruptible(1);\n\n\t\tcxt.cur_ops->task_boost(&rand);\n\t\tcxt.cur_ops->writelock(tid);\n\t\tif (WARN_ON_ONCE(lock_is_write_held))\n\t\t\tlwsp->n_lock_fail++;\n\t\tlock_is_write_held = true;\n\t\tif (WARN_ON_ONCE(atomic_read(&lock_is_read_held)))\n\t\t\tlwsp->n_lock_fail++; /* rare, but... */\n\n\t\tlwsp->n_lock_acquired++;\n\t\tcxt.cur_ops->write_delay(&rand);\n\t\tlock_is_write_held = false;\n\t\tWRITE_ONCE(last_lock_release, jiffies);\n\t\tcxt.cur_ops->writeunlock(tid);\n\n\t\tstutter_wait(\"lock_torture_writer\");\n\t} while (!torture_must_stop());\n\n\tcxt.cur_ops->task_boost(NULL); /* reset prio */\n\ttorture_kthread_stopping(\"lock_torture_writer\");\n\treturn 0;\n}",
        "static const struct perf_dlfilter_al *dlfilter__resolve_addr(void *ctx)\n{\n\tstruct dlfilter *d = (struct dlfilter *)ctx;\n\tstruct perf_dlfilter_al *d_addr_al = d->d_addr_al;\n\tstruct addr_location *addr_al = d->addr_al;": "static const struct perf_dlfilter_al *dlfilter__resolve_addr(void *ctx)\n{\n\tstruct dlfilter *d = (struct dlfilter *)ctx;\n\tstruct perf_dlfilter_al *d_addr_al = d->d_addr_al;\n\tstruct addr_location *addr_al = d->addr_al;\n\n\tif (!d->ctx_valid || !d->d_sample->addr_correlates_sym)\n\t\treturn NULL;\n\n\t/* 'size' is also used to indicate already initialized */\n\tif (d_addr_al->size)\n\t\treturn d_addr_al;\n\n\tif (!addr_al->thread) {\n\t\tstruct thread *thread = get_thread(d);\n\n\t\tif (!thread)\n\t\t\treturn NULL;\n\t\tthread__resolve(thread, addr_al, d->sample);\n\t}\n\n\tal_to_d_al(addr_al, d_addr_al);\n\n\td_addr_al->is_kernel_ip = machine__kernel_ip(d->machine, d->sample->addr);\n\n\treturn d_addr_al;\n}",
        "static void gsi_isr_gp_int1(struct gsi *gsi)\n{\n\tu32 result;\n\tu32 val;\n": "static void gsi_isr_gp_int1(struct gsi *gsi)\n{\n\tu32 result;\n\tu32 val;\n\n\t/* This interrupt is used to handle completions of GENERIC GSI\n\t * commands.  We use these to allocate and halt channels on the\n\t * modem's behalf due to a hardware quirk on IPA v4.2.  The modem\n\t * \"owns\" channels even when the AP allocates them, and have no\n\t * way of knowing whether a modem channel's state has been changed.\n\t *\n\t * We also use GENERIC commands to enable/disable channel flow\n\t * control for IPA v4.2+.\n\t *\n\t * It is recommended that we halt the modem channels we allocated\n\t * when shutting down, but it's possible the channel isn't running\n\t * at the time we issue the HALT command.  We'll get an error in\n\t * that case, but it's harmless (the channel is already halted).\n\t * Similarly, we could get an error back when updating flow control\n\t * on a channel because it's not in the proper state.\n\t *\n\t * In either case, we silently ignore a INCORRECT_CHANNEL_STATE\n\t * error if we receive it.\n\t */\n\tval = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET);\n\tresult = u32_get_bits(val, GENERIC_EE_RESULT_FMASK);\n\n\tswitch (result) {\n\tcase GENERIC_EE_SUCCESS:\n\tcase GENERIC_EE_INCORRECT_CHANNEL_STATE:\n\t\tgsi->result = 0;\n\t\tbreak;\n\n\tcase GENERIC_EE_RETRY:\n\t\tgsi->result = -EAGAIN;\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(gsi->dev, \"global INT1 generic result %u\\n\", result);\n\t\tgsi->result = -EIO;\n\t\tbreak;\n\t}\n\n\tcomplete(&gsi->completion);\n}",
        "static int get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst)\n{\n\tconst struct v4l2_ctrl_h264_decode_params *dec_params;\n\tconst struct v4l2_ctrl_h264_sps *sps;\n\tconst struct v4l2_ctrl_h264_pps *pps;": "static int get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst)\n{\n\tconst struct v4l2_ctrl_h264_decode_params *dec_params;\n\tconst struct v4l2_ctrl_h264_sps *sps;\n\tconst struct v4l2_ctrl_h264_pps *pps;\n\tconst struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;\n\tstruct mtk_h264_dec_slice_param *slice_param = &inst->h264_slice_param;\n\tstruct v4l2_h264_reflist_builder reflist_builder;\n\tstruct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN];\n\tstruct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN];\n\tstruct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN];\n\tu8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0;\n\tu8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0;\n\tu8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1;\n\n\tdec_params =\n\t\tmtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);\n\tif (IS_ERR(dec_params))\n\t\treturn PTR_ERR(dec_params);\n\n\tsps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS);\n\tif (IS_ERR(sps))\n\t\treturn PTR_ERR(sps);\n\n\tpps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);\n\tif (IS_ERR(pps))\n\t\treturn PTR_ERR(pps);\n\n\tscaling_matrix =\n\t\tmtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX);\n\tif (IS_ERR(scaling_matrix))\n\t\treturn PTR_ERR(scaling_matrix);\n\n\tmtk_vdec_h264_update_dpb(dec_params, inst->dpb);\n\n\tmtk_vdec_h264_copy_sps_params(&slice_param->sps, sps);\n\tmtk_vdec_h264_copy_pps_params(&slice_param->pps, pps);\n\tmtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix);\n\tmtk_vdec_h264_copy_decode_params(&slice_param->decode_params,\n\t\t\t\t\t dec_params, inst->dpb);\n\tmtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params,\n\t\t\t\t    slice_param->h264_dpb_info);\n\n\t/* Build the reference lists */\n\tv4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps,\n\t\t\t\t       inst->dpb);\n\tv4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist);\n\tv4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist,\n\t\t\t\t    v4l2_b1_reflist);\n\n\t/* Adapt the built lists to the firmware's expectations */\n\tmtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid);\n\tmtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid);\n\tmtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid);\n\n\tmemcpy(&inst->vsi_ctx.h264_slice_params, slice_param,\n\t       sizeof(inst->vsi_ctx.h264_slice_params));\n\n\treturn 0;\n}",
        "static int setup_type_id_case_local(struct core_reloc_test_case *test)\n{\n\tstruct core_reloc_type_id_output *exp = (void *)test->output;\n\tstruct btf *local_btf = btf__parse(test->bpf_obj_file, NULL);\n\tstruct btf *targ_btf = btf__parse(test->btf_src_file, NULL);": "static int setup_type_id_case_local(struct core_reloc_test_case *test)\n{\n\tstruct core_reloc_type_id_output *exp = (void *)test->output;\n\tstruct btf *local_btf = btf__parse(test->bpf_obj_file, NULL);\n\tstruct btf *targ_btf = btf__parse(test->btf_src_file, NULL);\n\tconst struct btf_type *t;\n\tconst char *name;\n\tint i;\n\n\tif (!ASSERT_OK_PTR(local_btf, \"local_btf\") || !ASSERT_OK_PTR(targ_btf, \"targ_btf\")) {\n\t\tbtf__free(local_btf);\n\t\tbtf__free(targ_btf);\n\t\treturn -EINVAL;\n\t}\n\n\texp->local_anon_struct = -1;\n\texp->local_anon_union = -1;\n\texp->local_anon_enum = -1;\n\texp->local_anon_func_proto_ptr = -1;\n\texp->local_anon_void_ptr = -1;\n\texp->local_anon_arr = -1;\n\n\tfor (i = 1; i < btf__type_cnt(local_btf); i++)\n\t{\n\t\tt = btf__type_by_id(local_btf, i);\n\t\t/* we are interested only in anonymous types */\n\t\tif (t->name_off)\n\t\t\tcontinue;\n\n\t\tif (btf_is_struct(t) && btf_vlen(t) &&\n\t\t    (name = btf__name_by_offset(local_btf, btf_members(t)[0].name_off)) &&\n\t\t    strcmp(name, \"marker_field\") == 0) {\n\t\t\texp->local_anon_struct = i;\n\t\t} else if (btf_is_union(t) && btf_vlen(t) &&\n\t\t\t (name = btf__name_by_offset(local_btf, btf_members(t)[0].name_off)) &&\n\t\t\t strcmp(name, \"marker_field\") == 0) {\n\t\t\texp->local_anon_union = i;\n\t\t} else if (btf_is_enum(t) && btf_vlen(t) &&\n\t\t\t (name = btf__name_by_offset(local_btf, btf_enum(t)[0].name_off)) &&\n\t\t\t strcmp(name, \"MARKER_ENUM_VAL\") == 0) {\n\t\t\texp->local_anon_enum = i;\n\t\t} else if (btf_is_ptr(t) && (t = btf__type_by_id(local_btf, t->type))) {\n\t\t\tif (btf_is_func_proto(t) && (t = btf__type_by_id(local_btf, t->type)) &&\n\t\t\t    btf_is_int(t) && (name = btf__name_by_offset(local_btf, t->name_off)) &&\n\t\t\t    strcmp(name, \"_Bool\") == 0) {\n\t\t\t\t/* ptr -> func_proto -> _Bool */\n\t\t\t\texp->local_anon_func_proto_ptr = i;\n\t\t\t} else if (btf_is_void(t)) {\n\t\t\t\t/* ptr -> void */\n\t\t\t\texp->local_anon_void_ptr = i;\n\t\t\t}\n\t\t} else if (btf_is_array(t) && (t = btf__type_by_id(local_btf, btf_array(t)->type)) &&\n\t\t\t   btf_is_int(t) && (name = btf__name_by_offset(local_btf, t->name_off)) &&\n\t\t\t   strcmp(name, \"_Bool\") == 0) {\n\t\t\t/* _Bool[] */\n\t\t\texp->local_anon_arr = i;\n\t\t}\n\t}\n\n\texp->local_struct = find_btf_type(local_btf, \"a_struct\", BTF_KIND_STRUCT);\n\texp->local_union = find_btf_type(local_btf, \"a_union\", BTF_KIND_UNION);\n\texp->local_enum = find_btf_type(local_btf, \"an_enum\", BTF_KIND_ENUM);\n\texp->local_int = find_btf_type(local_btf, \"int\", BTF_KIND_INT);\n\texp->local_struct_typedef = find_btf_type(local_btf, \"named_struct_typedef\", BTF_KIND_TYPEDEF);\n\texp->local_func_proto_typedef = find_btf_type(local_btf, \"func_proto_typedef\", BTF_KIND_TYPEDEF);\n\texp->local_arr_typedef = find_btf_type(local_btf, \"arr_typedef\", BTF_KIND_TYPEDEF);\n\n\tbtf__free(local_btf);\n\tbtf__free(targ_btf);\n\treturn 0;\n}",
        "static int virtio_mem_sbm_sb_states_prepare_next_mb(struct virtio_mem *vm)\n{\n\tconst unsigned long old_nb_mb = vm->sbm.next_mb_id - vm->sbm.first_mb_id;\n\tconst unsigned long old_nb_bits = old_nb_mb * vm->sbm.sbs_per_mb;\n\tconst unsigned long new_nb_bits = (old_nb_mb + 1) * vm->sbm.sbs_per_mb;": "static int virtio_mem_sbm_sb_states_prepare_next_mb(struct virtio_mem *vm)\n{\n\tconst unsigned long old_nb_mb = vm->sbm.next_mb_id - vm->sbm.first_mb_id;\n\tconst unsigned long old_nb_bits = old_nb_mb * vm->sbm.sbs_per_mb;\n\tconst unsigned long new_nb_bits = (old_nb_mb + 1) * vm->sbm.sbs_per_mb;\n\tint old_pages = PFN_UP(BITS_TO_LONGS(old_nb_bits) * sizeof(long));\n\tint new_pages = PFN_UP(BITS_TO_LONGS(new_nb_bits) * sizeof(long));\n\tunsigned long *new_bitmap, *old_bitmap;\n\n\tif (vm->sbm.sb_states && old_pages == new_pages)\n\t\treturn 0;\n\n\tnew_bitmap = vzalloc(new_pages * PAGE_SIZE);\n\tif (!new_bitmap)\n\t\treturn -ENOMEM;\n\n\tmutex_lock(&vm->hotplug_mutex);\n\tif (vm->sbm.sb_states)\n\t\tmemcpy(new_bitmap, vm->sbm.sb_states, old_pages * PAGE_SIZE);\n\n\told_bitmap = vm->sbm.sb_states;\n\tvm->sbm.sb_states = new_bitmap;\n\tmutex_unlock(&vm->hotplug_mutex);\n\n\tvfree(old_bitmap);\n\treturn 0;\n}",
        "static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)\n{\n\tu64 cur_freq, clk_incval, tu_per_sec, uix;\n\tint err;\n": "static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)\n{\n\tu64 cur_freq, clk_incval, tu_per_sec, uix;\n\tint err;\n\n\tcur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));\n\tclk_incval = ice_ptp_read_src_incval(hw);\n\n\t/* Calculate TUs per second divided by 256 */\n\ttu_per_sec = (cur_freq * clk_incval) >> 8;\n\n#define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */\n#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */\n\n\t/* Program the 10Gb/40Gb conversion ratio */\n\tuix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);\n\n\terr = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,\n\t\t\t\t\t uix);\n\tif (err) {\n\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write UIX66_10G_40G, err %d\\n\",\n\t\t\t  err);\n\t\treturn err;\n\t}\n\n\t/* Program the 25Gb/100Gb conversion ratio */\n\tuix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);\n\n\terr = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,\n\t\t\t\t\t uix);\n\tif (err) {\n\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write UIX66_25G_100G, err %d\\n\",\n\t\t\t  err);\n\t\treturn err;\n\t}\n\n\treturn 0;\n}",
        "static void test_v3_last_bit_redist_regions(void)\n{\n\tuint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 };\n\tstruct vm_gic v;\n\tuint64_t addr;": "static void test_v3_last_bit_redist_regions(void)\n{\n\tuint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 };\n\tstruct vm_gic v;\n\tuint64_t addr;\n\tuint32_t val;\n\tint ret;\n\n\tv.vm = vm_create_default_with_vcpus(6, 0, 0, guest_code, vcpuids);\n\n\tv.gic_fd = kvm_create_device(v.vm, KVM_DEV_TYPE_ARM_VGIC_V3, false);\n\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,\n\t\t\t  KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);\n\n\taddr = REDIST_REGION_ATTR_ADDR(2, 0x100000, 0, 0);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, &addr, true);\n\n\taddr = REDIST_REGION_ATTR_ADDR(2, 0x240000, 0, 1);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, &addr, true);\n\n\taddr = REDIST_REGION_ATTR_ADDR(2, 0x200000, 0, 2);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, &addr, true);\n\n\tret = access_v3_redist_reg(v.gic_fd, 0, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x000, \"read typer of rdist #0\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 1, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x100, \"read typer of rdist #1\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 2, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x200, \"read typer of rdist #2\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 3, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x310, \"read typer of rdist #3\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 5, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x500, \"read typer of rdist #5\");\n\n\tret = access_v3_redist_reg(v.gic_fd, 4, GICR_TYPER, &val, false);\n\tTEST_ASSERT(!ret && val == 0x410, \"read typer of rdist #4\");\n\n\tvm_gic_destroy(&v);\n}",
        "static void generate_pkt_descs(struct amdtp_stream *s, const __be32 *ctx_header, unsigned int packets)\n{\n\tstruct pkt_desc *descs = s->pkt_descs;\n\tconst struct seq_desc *seq_descs = s->ctx_data.rx.seq.descs;\n\tconst unsigned int seq_size = s->ctx_data.rx.seq.size;": "static void generate_pkt_descs(struct amdtp_stream *s, const __be32 *ctx_header, unsigned int packets)\n{\n\tstruct pkt_desc *descs = s->pkt_descs;\n\tconst struct seq_desc *seq_descs = s->ctx_data.rx.seq.descs;\n\tconst unsigned int seq_size = s->ctx_data.rx.seq.size;\n\tunsigned int dbc = s->data_block_counter;\n\tunsigned int seq_head = s->ctx_data.rx.seq.head;\n\tbool aware_syt = !(s->flags & CIP_UNAWARE_SYT);\n\tint i;\n\n\tfor (i = 0; i < packets; ++i) {\n\t\tstruct pkt_desc *desc = descs + i;\n\t\tunsigned int index = (s->packet_index + i) % s->queue_size;\n\t\tconst struct seq_desc *seq = seq_descs + seq_head;\n\n\t\tdesc->cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size);\n\n\t\tif (aware_syt && seq->syt_offset != CIP_SYT_NO_INFO)\n\t\t\tdesc->syt = compute_syt(seq->syt_offset, desc->cycle, s->transfer_delay);\n\t\telse\n\t\t\tdesc->syt = CIP_SYT_NO_INFO;\n\n\t\tdesc->data_blocks = seq->data_blocks;\n\n\t\tif (s->flags & CIP_DBC_IS_END_EVENT)\n\t\t\tdbc = (dbc + desc->data_blocks) & 0xff;\n\n\t\tdesc->data_block_counter = dbc;\n\n\t\tif (!(s->flags & CIP_DBC_IS_END_EVENT))\n\t\t\tdbc = (dbc + desc->data_blocks) & 0xff;\n\n\t\tdesc->ctx_payload = s->buffer.packets[index].buffer;\n\n\t\tseq_head = (seq_head + 1) % seq_size;\n\n\t\t++ctx_header;\n\t}\n\n\ts->data_block_counter = dbc;\n\ts->ctx_data.rx.seq.head = seq_head;\n}",
        "static void dm_integrity_map_continue(struct dm_integrity_io *dio, bool from_map)\n{\n\tstruct dm_integrity_c *ic = dio->ic;\n\tstruct bio *bio = dm_bio_from_per_bio_data(dio, sizeof(struct dm_integrity_io));\n\tunsigned journal_section, journal_entry;": "static void dm_integrity_map_continue(struct dm_integrity_io *dio, bool from_map)\n{\n\tstruct dm_integrity_c *ic = dio->ic;\n\tstruct bio *bio = dm_bio_from_per_bio_data(dio, sizeof(struct dm_integrity_io));\n\tunsigned journal_section, journal_entry;\n\tunsigned journal_read_pos;\n\tstruct completion read_comp;\n\tbool discard_retried = false;\n\tbool need_sync_io = ic->internal_hash && dio->op == REQ_OP_READ;\n\tif (unlikely(dio->op == REQ_OP_DISCARD) && ic->mode != 'D')\n\t\tneed_sync_io = true;\n\n\tif (need_sync_io && from_map) {\n\t\tINIT_WORK(&dio->work, integrity_bio_wait);\n\t\tqueue_work(ic->offload_wq, &dio->work);\n\t\treturn;\n\t}\n\nlock_retry:\n\tspin_lock_irq(&ic->endio_wait.lock);\nretry:\n\tif (unlikely(dm_integrity_failed(ic))) {\n\t\tspin_unlock_irq(&ic->endio_wait.lock);\n\t\tdo_endio(ic, bio);\n\t\treturn;\n\t}\n\tdio->range.n_sectors = bio_sectors(bio);\n\tjournal_read_pos = NOT_FOUND;\n\tif (ic->mode == 'J' && likely(dio->op != REQ_OP_DISCARD)) {\n\t\tif (dio->op == REQ_OP_WRITE) {\n\t\t\tunsigned next_entry, i, pos;\n\t\t\tunsigned ws, we, range_sectors;\n\n\t\t\tdio->range.n_sectors = min(dio->range.n_sectors,\n\t\t\t\t\t\t   (sector_t)ic->free_sectors << ic->sb->log2_sectors_per_block);\n\t\t\tif (unlikely(!dio->range.n_sectors)) {\n\t\t\t\tif (from_map)\n\t\t\t\t\tgoto offload_to_thread;\n\t\t\t\tsleep_on_endio_wait(ic);\n\t\t\t\tgoto retry;\n\t\t\t}\n\t\t\trange_sectors = dio->range.n_sectors >> ic->sb->log2_sectors_per_block;\n\t\t\tic->free_sectors -= range_sectors;\n\t\t\tjournal_section = ic->free_section;\n\t\t\tjournal_entry = ic->free_section_entry;\n\n\t\t\tnext_entry = ic->free_section_entry + range_sectors;\n\t\t\tic->free_section_entry = next_entry % ic->journal_section_entries;\n\t\t\tic->free_section += next_entry / ic->journal_section_entries;\n\t\t\tic->n_uncommitted_sections += next_entry / ic->journal_section_entries;\n\t\t\twraparound_section(ic, &ic->free_section);\n\n\t\t\tpos = journal_section * ic->journal_section_entries + journal_entry;\n\t\t\tws = journal_section;\n\t\t\twe = journal_entry;\n\t\t\ti = 0;\n\t\t\tdo {\n\t\t\t\tstruct journal_entry *je;\n\n\t\t\t\tadd_journal_node(ic, &ic->journal_tree[pos], dio->range.logical_sector + i);\n\t\t\t\tpos++;\n\t\t\t\tif (unlikely(pos >= ic->journal_entries))\n\t\t\t\t\tpos = 0;\n\n\t\t\t\tje = access_journal_entry(ic, ws, we);\n\t\t\t\tBUG_ON(!journal_entry_is_unused(je));\n\t\t\t\tjournal_entry_set_inprogress(je);\n\t\t\t\twe++;\n\t\t\t\tif (unlikely(we == ic->journal_section_entries)) {\n\t\t\t\t\twe = 0;\n\t\t\t\t\tws++;\n\t\t\t\t\twraparound_section(ic, &ws);\n\t\t\t\t}\n\t\t\t} while ((i += ic->sectors_per_block) < dio->range.n_sectors);\n\n\t\t\tspin_unlock_irq(&ic->endio_wait.lock);\n\t\t\tgoto journal_read_write;\n\t\t} else {\n\t\t\tsector_t next_sector;\n\t\t\tjournal_read_pos = find_journal_node(ic, dio->range.logical_sector, &next_sector);\n\t\t\tif (likely(journal_read_pos == NOT_FOUND)) {\n\t\t\t\tif (unlikely(dio->range.n_sectors > next_sector - dio->range.logical_sector))\n\t\t\t\t\tdio->range.n_sectors = next_sector - dio->range.logical_sector;\n\t\t\t} else {\n\t\t\t\tunsigned i;\n\t\t\t\tunsigned jp = journal_read_pos + 1;\n\t\t\t\tfor (i = ic->sectors_per_block; i < dio->range.n_sectors; i += ic->sectors_per_block, jp++) {\n\t\t\t\t\tif (!test_journal_node(ic, jp, dio->range.logical_sector + i))\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tdio->range.n_sectors = i;\n\t\t\t}\n\t\t}\n\t}\n\tif (unlikely(!add_new_range(ic, &dio->range, true))) {\n\t\t/*\n\t\t * We must not sleep in the request routine because it could\n\t\t * stall bios on current->bio_list.\n\t\t * So, we offload the bio to a workqueue if we have to sleep.\n\t\t */\n\t\tif (from_map) {\noffload_to_thread:\n\t\t\tspin_unlock_irq(&ic->endio_wait.lock);\n\t\t\tINIT_WORK(&dio->work, integrity_bio_wait);\n\t\t\tqueue_work(ic->wait_wq, &dio->work);\n\t\t\treturn;\n\t\t}\n\t\tif (journal_read_pos != NOT_FOUND)\n\t\t\tdio->range.n_sectors = ic->sectors_per_block;\n\t\twait_and_add_new_range(ic, &dio->range);\n\t\t/*\n\t\t * wait_and_add_new_range drops the spinlock, so the journal\n\t\t * may have been changed arbitrarily. We need to recheck.\n\t\t * To simplify the code, we restrict I/O size to just one block.\n\t\t */\n\t\tif (journal_read_pos != NOT_FOUND) {\n\t\t\tsector_t next_sector;\n\t\t\tunsigned new_pos = find_journal_node(ic, dio->range.logical_sector, &next_sector);\n\t\t\tif (unlikely(new_pos != journal_read_pos)) {\n\t\t\t\tremove_range_unlocked(ic, &dio->range);\n\t\t\t\tgoto retry;\n\t\t\t}\n\t\t}\n\t}\n\tif (ic->mode == 'J' && likely(dio->op == REQ_OP_DISCARD) && !discard_retried) {\n\t\tsector_t next_sector;\n\t\tunsigned new_pos = find_journal_node(ic, dio->range.logical_sector, &next_sector);\n\t\tif (unlikely(new_pos != NOT_FOUND) ||\n\t\t    unlikely(next_sector < dio->range.logical_sector - dio->range.n_sectors)) {\n\t\t\tremove_range_unlocked(ic, &dio->range);\n\t\t\tspin_unlock_irq(&ic->endio_wait.lock);\n\t\t\tqueue_work(ic->commit_wq, &ic->commit_work);\n\t\t\tflush_workqueue(ic->commit_wq);\n\t\t\tqueue_work(ic->writer_wq, &ic->writer_work);\n\t\t\tflush_workqueue(ic->writer_wq);\n\t\t\tdiscard_retried = true;\n\t\t\tgoto lock_retry;\n\t\t}\n\t}\n\tspin_unlock_irq(&ic->endio_wait.lock);\n\n\tif (unlikely(journal_read_pos != NOT_FOUND)) {\n\t\tjournal_section = journal_read_pos / ic->journal_section_entries;\n\t\tjournal_entry = journal_read_pos % ic->journal_section_entries;\n\t\tgoto journal_read_write;\n\t}\n\n\tif (ic->mode == 'B' && (dio->op == REQ_OP_WRITE || unlikely(dio->op == REQ_OP_DISCARD))) {\n\t\tif (!block_bitmap_op(ic, ic->may_write_bitmap, dio->range.logical_sector,\n\t\t\t\t     dio->range.n_sectors, BITMAP_OP_TEST_ALL_SET)) {\n\t\t\tstruct bitmap_block_status *bbs;\n\n\t\t\tbbs = sector_to_bitmap_block(ic, dio->range.logical_sector);\n\t\t\tspin_lock(&bbs->bio_queue_lock);\n\t\t\tbio_list_add(&bbs->bio_queue, bio);\n\t\t\tspin_unlock(&bbs->bio_queue_lock);\n\t\t\tqueue_work(ic->writer_wq, &bbs->work);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tdio->in_flight = (atomic_t)ATOMIC_INIT(2);\n\n\tif (need_sync_io) {\n\t\tinit_completion(&read_comp);\n\t\tdio->completion = &read_comp;\n\t} else\n\t\tdio->completion = NULL;\n\n\tdm_bio_record(&dio->bio_details, bio);\n\tbio_set_dev(bio, ic->dev->bdev);\n\tbio->bi_integrity = NULL;\n\tbio->bi_opf &= ~REQ_INTEGRITY;\n\tbio->bi_end_io = integrity_end_io;\n\tbio->bi_iter.bi_size = dio->range.n_sectors << SECTOR_SHIFT;\n\n\tif (unlikely(dio->op == REQ_OP_DISCARD) && likely(ic->mode != 'D')) {\n\t\tintegrity_metadata(&dio->work);\n\t\tdm_integrity_flush_buffers(ic, false);\n\n\t\tdio->in_flight = (atomic_t)ATOMIC_INIT(1);\n\t\tdio->completion = NULL;\n\n\t\tsubmit_bio_noacct(bio);\n\n\t\treturn;\n\t}\n\n\tsubmit_bio_noacct(bio);\n\n\tif (need_sync_io) {\n\t\twait_for_completion_io(&read_comp);\n\t\tif (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING) &&\n\t\t    dio->range.logical_sector + dio->range.n_sectors > le64_to_cpu(ic->sb->recalc_sector))\n\t\t\tgoto skip_check;\n\t\tif (ic->mode == 'B') {\n\t\t\tif (!block_bitmap_op(ic, ic->recalc_bitmap, dio->range.logical_sector,\n\t\t\t\t\t     dio->range.n_sectors, BITMAP_OP_TEST_ALL_CLEAR))\n\t\t\t\tgoto skip_check;\n\t\t}\n\n\t\tif (likely(!bio->bi_status))\n\t\t\tintegrity_metadata(&dio->work);\n\t\telse\nskip_check:\n\t\t\tdec_in_flight(dio);\n\n\t} else {\n\t\tINIT_WORK(&dio->work, integrity_metadata);\n\t\tqueue_work(ic->metadata_wq, &dio->work);\n\t}\n\n\treturn;\n\njournal_read_write:\n\tif (unlikely(__journal_read_write(dio, bio, journal_section, journal_entry)))\n\t\tgoto lock_retry;\n\n\tdo_endio_flush(ic, dio);\n}",
        "static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)\n{\n\tu8               val;\n\tu8               fif_cts;\n\tbool             done = false;": "static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)\n{\n\tu8               val;\n\tu8               fif_cts;\n\tbool             done = false;\n\tint              status = -ENOTRECOVERABLE;\n\tstruct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);\n\t/* Allow 3 bytes (27 toggles) to be read from the slave: */\n\tint              iter = 27;\n\n\tif ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {\n\t\tdev_dbg(bus->dev, \"bus%d-0x%x recovery skipped, bus not stuck\",\n\t\t\tbus->num, bus->dest_addr);\n\t\tnpcm_i2c_reset(bus);\n\t\treturn 0;\n\t}\n\n\tnpcm_i2c_int_enable(bus, false);\n\tnpcm_i2c_disable(bus);\n\tnpcm_i2c_enable(bus);\n\tiowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);\n\tnpcm_i2c_clear_tx_fifo(bus);\n\tnpcm_i2c_clear_rx_fifo(bus);\n\tiowrite8(0, bus->reg + NPCM_I2CRXF_CTL);\n\tiowrite8(0, bus->reg + NPCM_I2CTXF_CTL);\n\tnpcm_i2c_stall_after_start(bus, false);\n\n\t/* select bank 1 for FIFO regs */\n\tnpcm_i2c_select_bank(bus, I2C_BANK_1);\n\n\t/* clear FIFO and relevant status bits. */\n\tfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);\n\tfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;\n\tfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;\n\tiowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);\n\tnpcm_i2c_set_fifo(bus, -1, 0);\n\n\t/* Repeat the following sequence until SDA is released */\n\tdo {\n\t\t/* Issue a single SCL toggle */\n\t\tiowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);\n\t\tusleep_range(20, 30);\n\t\t/* If SDA line is inactive (high), stop */\n\t\tif (npcm_i2c_get_SDA(_adap)) {\n\t\t\tdone = true;\n\t\t\tstatus = 0;\n\t\t}\n\t} while (!done && iter--);\n\n\t/* If SDA line is released: send start-addr-stop, to re-sync. */\n\tif (npcm_i2c_get_SDA(_adap)) {\n\t\t/* Send an address byte in write direction: */\n\t\tnpcm_i2c_wr_byte(bus, bus->dest_addr);\n\t\tnpcm_i2c_master_start(bus);\n\t\t/* Wait until START condition is sent */\n\t\tstatus = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,\n\t\t\t\t\t    20, 200);\n\t\t/* If START condition was sent */\n\t\tif (npcm_i2c_is_master(bus) > 0) {\n\t\t\tusleep_range(20, 30);\n\t\t\tnpcm_i2c_master_stop(bus);\n\t\t\tusleep_range(200, 500);\n\t\t}\n\t}\n\tnpcm_i2c_reset(bus);\n\tnpcm_i2c_int_enable(bus, true);\n\n\tif ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))\n\t\tstatus = 0;\n\telse\n\t\tstatus = -ENOTRECOVERABLE;\n\tif (status) {\n\t\tif (bus->rec_fail_cnt < ULLONG_MAX)\n\t\t\tbus->rec_fail_cnt++;\n\t} else {\n\t\tif (bus->rec_succ_cnt < ULLONG_MAX)\n\t\t\tbus->rec_succ_cnt++;\n\t}\n\treturn status;\n}",
        "static void test_setsockopt_set(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL;\n": "static void test_setsockopt_set(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that sets EUNATCH, assert that\n\t * we actually get that error when we run setsockopt()\n\t */\n\tlink_set_eunatch = bpf_program__attach_cgroup(obj->progs.set_eunatch,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eunatch, \"cg-attach-set_eunatch\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t   &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EUNATCH, \"setsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 1, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_set_eunatch);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static void qcom_l3_cache__32bit_counter_start(struct perf_event *event)\n{\n\tstruct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);\n\tint idx = event->hw.idx;\n\tu32 evsel = get_event_type(event);": "static void qcom_l3_cache__32bit_counter_start(struct perf_event *event)\n{\n\tstruct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);\n\tint idx = event->hw.idx;\n\tu32 evsel = get_event_type(event);\n\tu32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);\n\n\t/* Set the counter to assert the overflow IRQ on MSB toggling */\n\twritel_relaxed(irqctl | PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);\n\n\t/* Initialize the hardware counter and reset prev_count*/\n\tlocal64_set(&event->hw.prev_count, 0);\n\twritel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));\n\n\t/* Set the event type */\n\twritel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));\n\n\t/* Enable interrupt generation by this counter */\n\twritel_relaxed(PMINTENSET(idx), l3pmu->regs + L3_M_BC_INTENSET);\n\n\t/* Finally, enable the counter */\n\twritel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));\n\twritel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);\n}",
        "static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)\n{\n\tu32 phys_addr_low, phys_addr_hi;\n\tu64 stb_phys_addr;\n\tu32 size = 0;": "static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)\n{\n\tu32 phys_addr_low, phys_addr_hi;\n\tu64 stb_phys_addr;\n\tu32 size = 0;\n\n\t/* Spill to DRAM feature uses separate SMU message port */\n\tdev->msg_port = 1;\n\n\tamd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);\n\tif (size != S2D_TELEMETRY_BYTES_MAX)\n\t\treturn -EIO;\n\n\t/* Get STB DRAM address */\n\tamd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);\n\tamd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);\n\n\tstb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);\n\n\t/* Clear msg_port for other SMU operation */\n\tdev->msg_port = 0;\n\n\tdev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);\n\tif (!dev->stb_virt_addr)\n\t\treturn -ENOMEM;\n\n\treturn 0;\n}",
        "static void rvu_setup_hw_capabilities(struct rvu *rvu)\n{\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\n\thw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;": "static void rvu_setup_hw_capabilities(struct rvu *rvu)\n{\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\n\thw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;\n\thw->cap.nix_fixed_txschq_mapping = false;\n\thw->cap.nix_shaping = true;\n\thw->cap.nix_tx_link_bp = true;\n\thw->cap.nix_rx_multicast = true;\n\thw->cap.nix_shaper_toggle_wait = false;\n\thw->rvu = rvu;\n\n\tif (is_rvu_pre_96xx_C0(rvu)) {\n\t\thw->cap.nix_fixed_txschq_mapping = true;\n\t\thw->cap.nix_txsch_per_cgx_lmac = 4;\n\t\thw->cap.nix_txsch_per_lbk_lmac = 132;\n\t\thw->cap.nix_txsch_per_sdp_lmac = 76;\n\t\thw->cap.nix_shaping = false;\n\t\thw->cap.nix_tx_link_bp = false;\n\t\tif (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))\n\t\t\thw->cap.nix_rx_multicast = false;\n\t}\n\tif (!is_rvu_pre_96xx_C0(rvu))\n\t\thw->cap.nix_shaper_toggle_wait = true;\n\n\tif (!is_rvu_otx2(rvu))\n\t\thw->cap.per_pf_mbox_regs = true;\n}",
        "static int wait_for_valid(struct cxl_dev_state *cxlds)\n{\n\tstruct pci_dev *pdev = to_pci_dev(cxlds->dev);\n\tint d = cxlds->cxl_dvsec, rc;\n\tu32 val;": "static int wait_for_valid(struct cxl_dev_state *cxlds)\n{\n\tstruct pci_dev *pdev = to_pci_dev(cxlds->dev);\n\tint d = cxlds->cxl_dvsec, rc;\n\tu32 val;\n\n\t/*\n\t * Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high\n\t * and Size Low registers are valid. Must be set within 1 second of\n\t * deassertion of reset to CXL device. Likely it is already set by the\n\t * time this runs, but otherwise give a 1.5 second timeout in case of\n\t * clock skew.\n\t */\n\trc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);\n\tif (rc)\n\t\treturn rc;\n\n\tif (val & CXL_DVSEC_MEM_INFO_VALID)\n\t\treturn 0;\n\n\tmsleep(1500);\n\n\trc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);\n\tif (rc)\n\t\treturn rc;\n\n\tif (val & CXL_DVSEC_MEM_INFO_VALID)\n\t\treturn 0;\n\n\treturn -ETIMEDOUT;\n}",
        "static void cas_global_reset(struct cas *cp, int blkflag)\n{\n\tint limit;\n\n\t/* issue a global reset. don't use RSTOUT. */": "static void cas_global_reset(struct cas *cp, int blkflag)\n{\n\tint limit;\n\n\t/* issue a global reset. don't use RSTOUT. */\n\tif (blkflag && !CAS_PHY_MII(cp->phy_type)) {\n\t\t/* For PCS, when the blkflag is set, we should set the\n\t\t * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of\n\t\t * the last autonegotiation from being cleared.  We'll\n\t\t * need some special handling if the chip is set into a\n\t\t * loopback mode.\n\t\t */\n\t\twritel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),\n\t\t       cp->regs + REG_SW_RESET);\n\t} else {\n\t\twritel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);\n\t}\n\n\t/* need to wait at least 3ms before polling register */\n\tmdelay(3);\n\n\tlimit = STOP_TRIES;\n\twhile (limit-- > 0) {\n\t\tu32 val = readl(cp->regs + REG_SW_RESET);\n\t\tif ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)\n\t\t\tgoto done;\n\t\tudelay(10);\n\t}\n\tnetdev_err(cp->dev, \"sw reset failed\\n\");\n\ndone:\n\t/* enable various BIM interrupts */\n\twritel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |\n\t       BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);\n\n\t/* clear out pci error status mask for handled errors.\n\t * we don't deal with DMA counter overflows as they happen\n\t * all the time.\n\t */\n\twritel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |\n\t\t\t       PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |\n\t\t\t       PCI_ERR_BIM_DMA_READ), cp->regs +\n\t       REG_PCI_ERR_STATUS_MASK);\n\n\t/* set up for MII by default to address mac rx reset timeout\n\t * issue\n\t */\n\twritel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);\n}",
        "static int alloc_try_nid_reserved_full_merge_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_reserved_full_merge_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\tstruct region r1, r2;\n\n\tphys_addr_t r3_size = SZ_64;\n\tphys_addr_t total_size;\n\tphys_addr_t max_addr;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2;\n\tr1.size = SMP_CACHE_BYTES;\n\n\tr2.size = SZ_128;\n\tr2.base = r1.base - (r3_size + r2.size);\n\n\ttotal_size = r1.size + r2.size + r3_size;\n\tmin_addr = r2.base + r2.size;\n\tmax_addr = r1.base;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == total_size);\n\tassert(rgn->base == r2.base);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static int bcm3510_tuner_cmd(struct bcm3510_state* st,u8 bc, u16 n, u8 a)\n{\n\tstruct bcm3510_hab_cmd_tune c;\n\tmemset(&c,0,sizeof(struct bcm3510_hab_cmd_tune));\n": "static int bcm3510_tuner_cmd(struct bcm3510_state* st,u8 bc, u16 n, u8 a)\n{\n\tstruct bcm3510_hab_cmd_tune c;\n\tmemset(&c,0,sizeof(struct bcm3510_hab_cmd_tune));\n\n/* I2C Mode disabled,  set 16 control / Data pairs */\n\tc.length = 0x10;\n\tc.clock_width = 0;\n/* CS1, CS0, DATA, CLK bits control the tuner RF_AGC_SEL pin is set to\n * logic high (as Configuration) */\n\tc.misc = 0x10;\n/* Set duration of the initial state of TUNCTL = 3.34 micro Sec */\n\tc.TUNCTL_state = 0x40;\n\n/* PRESCALER DIVIDE RATIO | BC1_2_3_4; (band switch), 1stosc REFERENCE COUNTER REF_S12 and REF_S11 */\n\tc.ctl_dat[0].ctrl.size = BITS_8;\n\tc.ctl_dat[0].data      = 0x80 | bc;\n\n/* Control DATA pin, 1stosc REFERENCE COUNTER REF_S10 to REF_S3 */\n\tc.ctl_dat[1].ctrl.size = BITS_8;\n\tc.ctl_dat[1].data      = 4;\n\n/* set CONTROL BIT 1 to 1, 1stosc REFERENCE COUNTER REF_S2 to REF_S1 */\n\tc.ctl_dat[2].ctrl.size = BITS_3;\n\tc.ctl_dat[2].data      = 0x20;\n\n/* control CS0 pin, pulse byte ? */\n\tc.ctl_dat[3].ctrl.size = BITS_3;\n\tc.ctl_dat[3].ctrl.clk_off = 1;\n\tc.ctl_dat[3].ctrl.cs0  = 1;\n\tc.ctl_dat[3].data      = 0x40;\n\n/* PGM_S18 to PGM_S11 */\n\tc.ctl_dat[4].ctrl.size = BITS_8;\n\tc.ctl_dat[4].data      = n >> 3;\n\n/* PGM_S10 to PGM_S8, SWL_S7 to SWL_S3 */\n\tc.ctl_dat[5].ctrl.size = BITS_8;\n\tc.ctl_dat[5].data      = ((n & 0x7) << 5) | (a >> 2);\n\n/* SWL_S2 and SWL_S1, set CONTROL BIT 2 to 0 */\n\tc.ctl_dat[6].ctrl.size = BITS_3;\n\tc.ctl_dat[6].data      = (a << 6) & 0xdf;\n\n/* control CS0 pin, pulse byte ? */\n\tc.ctl_dat[7].ctrl.size = BITS_3;\n\tc.ctl_dat[7].ctrl.clk_off = 1;\n\tc.ctl_dat[7].ctrl.cs0  = 1;\n\tc.ctl_dat[7].data      = 0x40;\n\n/* PRESCALER DIVIDE RATIO, 2ndosc REFERENCE COUNTER REF_S12 and REF_S11 */\n\tc.ctl_dat[8].ctrl.size = BITS_8;\n\tc.ctl_dat[8].data      = 0x80;\n\n/* 2ndosc REFERENCE COUNTER REF_S10 to REF_S3 */\n\tc.ctl_dat[9].ctrl.size = BITS_8;\n\tc.ctl_dat[9].data      = 0x10;\n\n/* set CONTROL BIT 1 to 1, 2ndosc REFERENCE COUNTER REF_S2 to REF_S1 */\n\tc.ctl_dat[10].ctrl.size = BITS_3;\n\tc.ctl_dat[10].data      = 0x20;\n\n/* pulse byte */\n\tc.ctl_dat[11].ctrl.size = BITS_3;\n\tc.ctl_dat[11].ctrl.clk_off = 1;\n\tc.ctl_dat[11].ctrl.cs1  = 1;\n\tc.ctl_dat[11].data      = 0x40;\n\n/* PGM_S18 to PGM_S11 */\n\tc.ctl_dat[12].ctrl.size = BITS_8;\n\tc.ctl_dat[12].data      = 0x2a;\n\n/* PGM_S10 to PGM_S8 and SWL_S7 to SWL_S3 */\n\tc.ctl_dat[13].ctrl.size = BITS_8;\n\tc.ctl_dat[13].data      = 0x8e;\n\n/* SWL_S2 and SWL_S1 and set CONTROL BIT 2 to 0 */\n\tc.ctl_dat[14].ctrl.size = BITS_3;\n\tc.ctl_dat[14].data      = 0;\n\n/* Pulse Byte */\n\tc.ctl_dat[15].ctrl.size = BITS_3;\n\tc.ctl_dat[15].ctrl.clk_off = 1;\n\tc.ctl_dat[15].ctrl.cs1  = 1;\n\tc.ctl_dat[15].data      = 0x40;\n\n\treturn bcm3510_do_hab_cmd(st,CMD_TUNE, MSGID_TUNE,(u8 *) &c,sizeof(c), NULL, 0);\n}",
        "static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)\n{\n\tstruct pci_dev *pdev = to_pci_dev(isp->dev);\n\tenum ia_css_pipe_id css_pipe_id;\n\tbool stream_restart[MAX_STREAM_NUM] = {0};": "static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)\n{\n\tstruct pci_dev *pdev = to_pci_dev(isp->dev);\n\tenum ia_css_pipe_id css_pipe_id;\n\tbool stream_restart[MAX_STREAM_NUM] = {0};\n\tbool depth_mode = false;\n\tint i, ret, depth_cnt = 0;\n\n\tif (!isp->sw_contex.file_input)\n\t\tatomisp_css_irq_enable(isp,\n\t\t\t\t       IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF, false);\n\n\tBUG_ON(isp->num_of_streams > MAX_STREAM_NUM);\n\n\tfor (i = 0; i < isp->num_of_streams; i++) {\n\t\tstruct atomisp_sub_device *asd = &isp->asd[i];\n\t\tstruct ia_css_pipeline *acc_pipeline;\n\t\tstruct ia_css_pipe *acc_pipe = NULL;\n\n\t\tif (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED &&\n\t\t    !asd->stream_prepared)\n\t\t\tcontinue;\n\n\t\t/*\n\t\t* AtomISP::waitStageUpdate is blocked when WDT happens.\n\t\t* By calling acc_done() for all loaded fw_handles,\n\t\t* HAL will be unblocked.\n\t\t*/\n\t\tacc_pipe = asd->stream_env[i].pipes[IA_CSS_PIPE_ID_ACC];\n\t\tif (acc_pipe) {\n\t\t\tacc_pipeline = ia_css_pipe_get_pipeline(acc_pipe);\n\t\t\tif (acc_pipeline) {\n\t\t\t\tstruct ia_css_pipeline_stage *stage;\n\n\t\t\t\tfor (stage = acc_pipeline->stages; stage;\n\t\t\t\t     stage = stage->next) {\n\t\t\t\t\tconst struct ia_css_fw_info *fw;\n\n\t\t\t\t\tfw = stage->firmware;\n\t\t\t\t\tatomisp_acc_done(asd, fw->handle);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tdepth_cnt++;\n\n\t\tif (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED)\n\t\t\tcancel_work_sync(&asd->delayed_init_work);\n\n\t\tcomplete(&asd->init_done);\n\t\tasd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED;\n\n\t\tstream_restart[asd->index] = true;\n\n\t\tasd->streaming = ATOMISP_DEVICE_STREAMING_STOPPING;\n\n\t\t/* stream off sensor */\n\t\tret = v4l2_subdev_call(\n\t\t\t  isp->inputs[asd->input_curr].\n\t\t\t  camera, video, s_stream, 0);\n\t\tif (ret)\n\t\t\tdev_warn(isp->dev,\n\t\t\t\t \"can't stop streaming on sensor!\\n\");\n\n\t\tatomisp_acc_unload_extensions(asd);\n\n\t\tatomisp_clear_css_buffer_counters(asd);\n\n\t\tcss_pipe_id = atomisp_get_css_pipe_id(asd);\n\t\tatomisp_css_stop(asd, css_pipe_id, true);\n\n\t\tasd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED;\n\n\t\tasd->preview_exp_id = 1;\n\t\tasd->postview_exp_id = 1;\n\t\t/* notify HAL the CSS reset */\n\t\tdev_dbg(isp->dev,\n\t\t\t\"send reset event to %s\\n\", asd->subdev.devnode->name);\n\t\tatomisp_reset_event(asd);\n\t}\n\n\t/* clear irq */\n\tdisable_isp_irq(hrt_isp_css_irq_sp);\n\tclear_isp_irq(hrt_isp_css_irq_sp);\n\n\t/* Set the SRSE to 3 before resetting */\n\tpci_write_config_dword(pdev, PCI_I_CONTROL,\n\t\t\t       isp->saved_regs.i_control | MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);\n\n\t/* reset ISP and restore its state */\n\tisp->isp_timeout = true;\n\tatomisp_reset(isp);\n\tisp->isp_timeout = false;\n\n\tif (!isp_timeout) {\n\t\tfor (i = 0; i < isp->num_of_streams; i++) {\n\t\t\tif (isp->asd[i].depth_mode->val)\n\t\t\t\treturn;\n\t\t}\n\t}\n\n\tfor (i = 0; i < isp->num_of_streams; i++) {\n\t\tstruct atomisp_sub_device *asd = &isp->asd[i];\n\n\t\tif (!stream_restart[i])\n\t\t\tcontinue;\n\n\t\tif (isp->inputs[asd->input_curr].type != FILE_INPUT)\n\t\t\tatomisp_css_input_set_mode(asd,\n\t\t\t\t\t\t   IA_CSS_INPUT_MODE_BUFFERED_SENSOR);\n\n\t\tcss_pipe_id = atomisp_get_css_pipe_id(asd);\n\t\tif (atomisp_css_start(asd, css_pipe_id, true))\n\t\t\tdev_warn(isp->dev,\n\t\t\t\t \"start SP failed, so do not set streaming to be enable!\\n\");\n\t\telse\n\t\t\tasd->streaming = ATOMISP_DEVICE_STREAMING_ENABLED;\n\n\t\tatomisp_csi2_configure(asd);\n\t}\n\n\tif (!isp->sw_contex.file_input) {\n\t\tatomisp_css_irq_enable(isp, IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF,\n\t\t\t\t       atomisp_css_valid_sof(isp));\n\n\t\tif (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_AUTO, true) < 0)\n\t\t\tdev_dbg(isp->dev, \"DFS auto failed while recovering!\\n\");\n\t} else {\n\t\tif (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_MAX, true) < 0)\n\t\t\tdev_dbg(isp->dev, \"DFS max failed while recovering!\\n\");\n\t}\n\n\tfor (i = 0; i < isp->num_of_streams; i++) {\n\t\tstruct atomisp_sub_device *asd;\n\n\t\tasd = &isp->asd[i];\n\n\t\tif (!stream_restart[i])\n\t\t\tcontinue;\n\n\t\tif (asd->continuous_mode->val &&\n\t\t    asd->delayed_init == ATOMISP_DELAYED_INIT_NOT_QUEUED) {\n\t\t\treinit_completion(&asd->init_done);\n\t\t\tasd->delayed_init = ATOMISP_DELAYED_INIT_QUEUED;\n\t\t\tqueue_work(asd->delayed_init_workq,\n\t\t\t\t   &asd->delayed_init_work);\n\t\t}\n\t\t/*\n\t\t * dequeueing buffers is not needed. CSS will recycle\n\t\t * buffers that it has.\n\t\t */\n\t\tatomisp_flush_bufs_and_wakeup(asd);\n\n\t\t/* Requeue unprocessed per-frame parameters. */\n\t\tatomisp_recover_params_queue(&asd->video_out_capture);\n\t\tatomisp_recover_params_queue(&asd->video_out_preview);\n\t\tatomisp_recover_params_queue(&asd->video_out_video_capture);\n\n\t\tif ((asd->depth_mode->val) &&\n\t\t    (depth_cnt == ATOMISP_DEPTH_SENSOR_STREAMON_COUNT)) {\n\t\t\tdepth_mode = true;\n\t\t\tcontinue;\n\t\t}\n\n\t\tret = v4l2_subdev_call(\n\t\t\t  isp->inputs[asd->input_curr].camera, video,\n\t\t\t  s_stream, 1);\n\t\tif (ret)\n\t\t\tdev_warn(isp->dev,\n\t\t\t\t \"can't start streaming on sensor!\\n\");\n\t}\n\n\tif (depth_mode) {\n\t\tif (atomisp_stream_on_master_slave_sensor(isp, true))\n\t\t\tdev_warn(isp->dev,\n\t\t\t\t \"master slave sensor stream on failed!\\n\");\n\t}\n}",
        "static void ca0132_mmio_init_sbz(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp[2], i, count, cur_addr;\n\tconst unsigned int *addr, *data;": "static void ca0132_mmio_init_sbz(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp[2], i, count, cur_addr;\n\tconst unsigned int *addr, *data;\n\n\taddr = ca0113_mmio_init_address_sbz;\n\tfor (i = 0; i < 3; i++)\n\t\twritel(0x00000000, spec->mem_base + addr[i]);\n\n\tcur_addr = i;\n\tswitch (ca0132_quirk(spec)) {\n\tcase QUIRK_ZXR:\n\t\ttmp[0] = 0x00880480;\n\t\ttmp[1] = 0x00000080;\n\t\tbreak;\n\tcase QUIRK_SBZ:\n\t\ttmp[0] = 0x00820680;\n\t\ttmp[1] = 0x00000083;\n\t\tbreak;\n\tcase QUIRK_R3D:\n\t\ttmp[0] = 0x00880680;\n\t\ttmp[1] = 0x00000083;\n\t\tbreak;\n\tdefault:\n\t\ttmp[0] = 0x00000000;\n\t\ttmp[1] = 0x00000000;\n\t\tbreak;\n\t}\n\n\tfor (i = 0; i < 2; i++)\n\t\twritel(tmp[i], spec->mem_base + addr[cur_addr + i]);\n\n\tcur_addr += i;\n\n\tswitch (ca0132_quirk(spec)) {\n\tcase QUIRK_ZXR:\n\t\tcount = ARRAY_SIZE(ca0113_mmio_init_data_zxr);\n\t\tdata = ca0113_mmio_init_data_zxr;\n\t\tbreak;\n\tdefault:\n\t\tcount = ARRAY_SIZE(ca0113_mmio_init_data_sbz);\n\t\tdata = ca0113_mmio_init_data_sbz;\n\t\tbreak;\n\t}\n\n\tfor (i = 0; i < count; i++)\n\t\twritel(data[i], spec->mem_base + addr[cur_addr + i]);\n}",
        "static int rvu_dbg_nix_band_prof_ctx_display(struct seq_file *m, void *unused)\n{\n\tstruct nix_hw *nix_hw = m->private;\n\tstruct nix_cn10k_aq_enq_req aq_req;\n\tstruct nix_cn10k_aq_enq_rsp aq_rsp;": "static int rvu_dbg_nix_band_prof_ctx_display(struct seq_file *m, void *unused)\n{\n\tstruct nix_hw *nix_hw = m->private;\n\tstruct nix_cn10k_aq_enq_req aq_req;\n\tstruct nix_cn10k_aq_enq_rsp aq_rsp;\n\tstruct rvu *rvu = nix_hw->rvu;\n\tstruct nix_ipolicer *ipolicer;\n\tint layer, prof_idx, idx, rc;\n\tu16 pcifunc;\n\tchar *str;\n\n\t/* Ingress policers do not exist on all platforms */\n\tif (!nix_hw->ipolicer)\n\t\treturn 0;\n\n\tfor (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {\n\t\tif (layer == BAND_PROF_INVAL_LAYER)\n\t\t\tcontinue;\n\t\tstr = (layer == BAND_PROF_LEAF_LAYER) ? \"Leaf\" :\n\t\t\t(layer == BAND_PROF_MID_LAYER) ? \"Mid\" : \"Top\";\n\n\t\tseq_printf(m, \"\\n%s bandwidth profiles\\n\", str);\n\t\tseq_puts(m, \"=======================\\n\");\n\n\t\tipolicer = &nix_hw->ipolicer[layer];\n\n\t\tfor (idx = 0; idx < ipolicer->band_prof.max; idx++) {\n\t\t\tif (is_rsrc_free(&ipolicer->band_prof, idx))\n\t\t\t\tcontinue;\n\n\t\t\tprof_idx = (idx & 0x3FFF) | (layer << 14);\n\t\t\trc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp,\n\t\t\t\t\t\t 0x00, NIX_AQ_CTYPE_BANDPROF,\n\t\t\t\t\t\t prof_idx);\n\t\t\tif (rc) {\n\t\t\t\tdev_err(rvu->dev,\n\t\t\t\t\t\"%s: Failed to fetch context of %s profile %d, err %d\\n\",\n\t\t\t\t\t__func__, str, idx, rc);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tseq_printf(m, \"\\n%s bandwidth profile:: %d\\n\", str, idx);\n\t\t\tpcifunc = ipolicer->pfvf_map[idx];\n\t\t\tif (!(pcifunc & RVU_PFVF_FUNC_MASK))\n\t\t\t\tseq_printf(m, \"Allocated to :: PF %d\\n\",\n\t\t\t\t\t   rvu_get_pf(pcifunc));\n\t\t\telse\n\t\t\t\tseq_printf(m, \"Allocated to :: PF %d VF %d\\n\",\n\t\t\t\t\t   rvu_get_pf(pcifunc),\n\t\t\t\t\t   (pcifunc & RVU_PFVF_FUNC_MASK) - 1);\n\t\t\tprint_band_prof_ctx(m, &aq_rsp.prof);\n\t\t}\n\t}\n\treturn 0;\n}",
        "static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)\n{\n\tstruct cqspi_st *cqspi = f_pdata->cqspi;\n\tvoid __iomem *iobase = cqspi->iobase;\n\tconst unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;": "static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)\n{\n\tstruct cqspi_st *cqspi = f_pdata->cqspi;\n\tvoid __iomem *iobase = cqspi->iobase;\n\tconst unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;\n\tunsigned int tshsl, tchsh, tslch, tsd2d;\n\tunsigned int reg;\n\tunsigned int tsclk;\n\n\t/* calculate the number of ref ticks for one sclk tick */\n\ttsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);\n\n\ttshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);\n\t/* this particular value must be at least one sclk */\n\tif (tshsl < tsclk)\n\t\ttshsl = tsclk;\n\n\ttchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);\n\ttslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);\n\ttsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);\n\n\treg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)\n\t       << CQSPI_REG_DELAY_TSHSL_LSB;\n\treg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)\n\t\t<< CQSPI_REG_DELAY_TCHSH_LSB;\n\treg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)\n\t\t<< CQSPI_REG_DELAY_TSLCH_LSB;\n\treg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)\n\t\t<< CQSPI_REG_DELAY_TSD2D_LSB;\n\twritel(reg, iobase + CQSPI_REG_DELAY);\n}",
        "static int lan78xx_set_suspend(struct lan78xx_net *dev, u32 wol)\n{\n\tconst u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };\n\tconst u8 ipv6_multicast[3] = { 0x33, 0x33 };\n\tconst u8 arp_type[2] = { 0x08, 0x06 };": "static int lan78xx_set_suspend(struct lan78xx_net *dev, u32 wol)\n{\n\tconst u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };\n\tconst u8 ipv6_multicast[3] = { 0x33, 0x33 };\n\tconst u8 arp_type[2] = { 0x08, 0x06 };\n\tu32 temp_pmt_ctl;\n\tint mask_index;\n\tu32 temp_wucsr;\n\tu32 buf;\n\tu16 crc;\n\tint ret;\n\n\tret = lan78xx_stop_tx_path(dev);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = lan78xx_stop_rx_path(dev);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tret = lan78xx_write_reg(dev, WUCSR, 0);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = lan78xx_write_reg(dev, WUCSR2, 0);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);\n\tif (ret < 0)\n\t\treturn ret;\n\n\ttemp_wucsr = 0;\n\n\ttemp_pmt_ctl = 0;\n\n\tret = lan78xx_read_reg(dev, PMT_CTL, &temp_pmt_ctl);\n\tif (ret < 0)\n\t\treturn ret;\n\n\ttemp_pmt_ctl &= ~PMT_CTL_RES_CLR_WKP_EN_;\n\ttemp_pmt_ctl |= PMT_CTL_RES_CLR_WKP_STS_;\n\n\tfor (mask_index = 0; mask_index < NUM_OF_WUF_CFG; mask_index++) {\n\t\tret = lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\tmask_index = 0;\n\tif (wol & WAKE_PHY) {\n\t\ttemp_pmt_ctl |= PMT_CTL_PHY_WAKE_EN_;\n\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;\n\t}\n\tif (wol & WAKE_MAGIC) {\n\t\ttemp_wucsr |= WUCSR_MPEN_;\n\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_3_;\n\t}\n\tif (wol & WAKE_BCAST) {\n\t\ttemp_wucsr |= WUCSR_BCST_EN_;\n\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;\n\t}\n\tif (wol & WAKE_MCAST) {\n\t\ttemp_wucsr |= WUCSR_WAKE_EN_;\n\n\t\t/* set WUF_CFG & WUF_MASK for IPv4 Multicast */\n\t\tcrc = lan78xx_wakeframe_crc16(ipv4_multicast, 3);\n\t\tret = lan78xx_write_reg(dev, WUF_CFG(mask_index),\n\t\t\t\t\tWUF_CFGX_EN_ |\n\t\t\t\t\tWUF_CFGX_TYPE_MCAST_ |\n\t\t\t\t\t(0 << WUF_CFGX_OFFSET_SHIFT_) |\n\t\t\t\t\t(crc & WUF_CFGX_CRC16_MASK_));\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tmask_index++;\n\n\t\t/* for IPv6 Multicast */\n\t\tcrc = lan78xx_wakeframe_crc16(ipv6_multicast, 2);\n\t\tret = lan78xx_write_reg(dev, WUF_CFG(mask_index),\n\t\t\t\t\tWUF_CFGX_EN_ |\n\t\t\t\t\tWUF_CFGX_TYPE_MCAST_ |\n\t\t\t\t\t(0 << WUF_CFGX_OFFSET_SHIFT_) |\n\t\t\t\t\t(crc & WUF_CFGX_CRC16_MASK_));\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tmask_index++;\n\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;\n\t}\n\tif (wol & WAKE_UCAST) {\n\t\ttemp_wucsr |= WUCSR_PFDA_EN_;\n\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;\n\t}\n\tif (wol & WAKE_ARP) {\n\t\ttemp_wucsr |= WUCSR_WAKE_EN_;\n\n\t\t/* set WUF_CFG & WUF_MASK\n\t\t * for packettype (offset 12,13) = ARP (0x0806)\n\t\t */\n\t\tcrc = lan78xx_wakeframe_crc16(arp_type, 2);\n\t\tret = lan78xx_write_reg(dev, WUF_CFG(mask_index),\n\t\t\t\t\tWUF_CFGX_EN_ |\n\t\t\t\t\tWUF_CFGX_TYPE_ALL_ |\n\t\t\t\t\t(0 << WUF_CFGX_OFFSET_SHIFT_) |\n\t\t\t\t\t(crc & WUF_CFGX_CRC16_MASK_));\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tmask_index++;\n\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;\n\t}\n\n\tret = lan78xx_write_reg(dev, WUCSR, temp_wucsr);\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/* when multiple WOL bits are set */\n\tif (hweight_long((unsigned long)wol) > 1) {\n\t\ttemp_pmt_ctl |= PMT_CTL_WOL_EN_;\n\t\ttemp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;\n\t\ttemp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;\n\t}\n\tret = lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/* clear WUPS */\n\tret = lan78xx_read_reg(dev, PMT_CTL, &buf);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tbuf |= PMT_CTL_WUPS_MASK_;\n\n\tret = lan78xx_write_reg(dev, PMT_CTL, buf);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tret = lan78xx_start_rx_path(dev);\n\n\treturn ret;\n}",
        "static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr)\n{\n\tspec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr);\n\tspec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr);\n\tspec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr);": "static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr)\n{\n\tspec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr);\n\tspec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr);\n\tspec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr);\n\tspec->source_vhca_port = IFC_GET_CLR(fte_match_set_misc, mask, source_vhca_port, clr);\n\tspec->source_sqn = IFC_GET_CLR(fte_match_set_misc, mask, source_sqn, clr);\n\n\tspec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr);\n\tspec->source_eswitch_owner_vhca_id =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, source_eswitch_owner_vhca_id, clr);\n\n\tspec->outer_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_prio, clr);\n\tspec->outer_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cfi, clr);\n\tspec->outer_second_vid = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_vid, clr);\n\tspec->inner_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, inner_second_prio, clr);\n\tspec->inner_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, inner_second_cfi, clr);\n\tspec->inner_second_vid = IFC_GET_CLR(fte_match_set_misc, mask, inner_second_vid, clr);\n\n\tspec->outer_second_cvlan_tag =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, outer_second_cvlan_tag, clr);\n\tspec->inner_second_cvlan_tag =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, inner_second_cvlan_tag, clr);\n\tspec->outer_second_svlan_tag =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, outer_second_svlan_tag, clr);\n\tspec->inner_second_svlan_tag =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, inner_second_svlan_tag, clr);\n\tspec->gre_protocol = IFC_GET_CLR(fte_match_set_misc, mask, gre_protocol, clr);\n\n\tspec->gre_key_h = IFC_GET_CLR(fte_match_set_misc, mask, gre_key.nvgre.hi, clr);\n\tspec->gre_key_l = IFC_GET_CLR(fte_match_set_misc, mask, gre_key.nvgre.lo, clr);\n\n\tspec->vxlan_vni = IFC_GET_CLR(fte_match_set_misc, mask, vxlan_vni, clr);\n\n\tspec->geneve_vni = IFC_GET_CLR(fte_match_set_misc, mask, geneve_vni, clr);\n\tspec->geneve_tlv_option_0_exist =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, geneve_tlv_option_0_exist, clr);\n\tspec->geneve_oam = IFC_GET_CLR(fte_match_set_misc, mask, geneve_oam, clr);\n\n\tspec->outer_ipv6_flow_label =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, outer_ipv6_flow_label, clr);\n\n\tspec->inner_ipv6_flow_label =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, inner_ipv6_flow_label, clr);\n\n\tspec->geneve_opt_len = IFC_GET_CLR(fte_match_set_misc, mask, geneve_opt_len, clr);\n\tspec->geneve_protocol_type =\n\t\tIFC_GET_CLR(fte_match_set_misc, mask, geneve_protocol_type, clr);\n\n\tspec->bth_dst_qp = IFC_GET_CLR(fte_match_set_misc, mask, bth_dst_qp, clr);\n}",
        "static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)\n{\n\tstruct mcp251xfd_ecc *ecc = &priv->ecc;\n\tstruct net_device_stats *stats = &priv->ndev->stats;\n\tbool handled = false;": "static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)\n{\n\tstruct mcp251xfd_ecc *ecc = &priv->ecc;\n\tstruct net_device_stats *stats = &priv->ndev->stats;\n\tbool handled = false;\n\n\t/* TX MAB underflow\n\t *\n\t * According to MCP2517FD Errata DS80000792B 1. a TX MAB\n\t * underflow is indicated by SERRIF and MODIF.\n\t *\n\t * In addition to the effects mentioned in the Errata, there\n\t * are Bus Errors due to the aborted CAN frame, so a IVMIF\n\t * will be seen as well.\n\t *\n\t * Sometimes there is an ECC error in the TX-RAM, which leads\n\t * to a TX MAB underflow.\n\t *\n\t * However, probably due to a race condition, there is no\n\t * associated MODIF pending.\n\t *\n\t * Further, there are situations, where the SERRIF is caused\n\t * by an ECC error in the TX-RAM, but not even the ECCIF is\n\t * set. This only seems to happen _after_ the first occurrence\n\t * of a ECCIF (which is tracked in ecc->cnt).\n\t *\n\t * Treat all as a known system errors..\n\t */\n\tif ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&\n\t     priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||\n\t    priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||\n\t    ecc->cnt) {\n\t\tconst char *msg;\n\n\t\tif (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||\n\t\t    ecc->cnt)\n\t\t\tmsg = \"TX MAB underflow due to ECC error detected.\";\n\t\telse\n\t\t\tmsg = \"TX MAB underflow detected.\";\n\n\t\tif (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)\n\t\t\tnetdev_dbg(priv->ndev, \"%s\\n\", msg);\n\t\telse\n\t\t\tnetdev_info(priv->ndev, \"%s\\n\", msg);\n\n\t\tstats->tx_aborted_errors++;\n\t\tstats->tx_errors++;\n\t\thandled = true;\n\t}\n\n\t/* RX MAB overflow\n\t *\n\t * According to MCP2517FD Errata DS80000792B 1. a RX MAB\n\t * overflow is indicated by SERRIF.\n\t *\n\t * In addition to the effects mentioned in the Errata, (most\n\t * of the times) a RXOVIF is raised, if the FIFO that is being\n\t * received into has the RXOVIE activated (and we have enabled\n\t * RXOVIE on all FIFOs).\n\t *\n\t * Sometimes there is no RXOVIF just a RXIF is pending.\n\t *\n\t * Treat all as a known system errors..\n\t */\n\tif (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||\n\t    priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {\n\t\tstats->rx_dropped++;\n\t\thandled = true;\n\t}\n\n\tif (!handled)\n\t\tnetdev_err(priv->ndev,\n\t\t\t   \"Unhandled System Error Interrupt (intf=0x%08x)!\\n\",\n\t\t\t   priv->regs_status.intf);\n\n\treturn 0;\n}",
        "static void Et_init2(struct gspca_dev *gspca_dev)\n{\n\t__u8 value;\n\tstatic const __u8 FormLine[] = { 0x84, 0x03, 0x14, 0xf4, 0x01, 0x05 };\n": "static void Et_init2(struct gspca_dev *gspca_dev)\n{\n\t__u8 value;\n\tstatic const __u8 FormLine[] = { 0x84, 0x03, 0x14, 0xf4, 0x01, 0x05 };\n\n\tgspca_dbg(gspca_dev, D_STREAM, \"Open Init2 ET\\n\");\n\treg_w_val(gspca_dev, ET_GPIO_DIR_CTRL, 0x2f);\n\treg_w_val(gspca_dev, ET_GPIO_OUT, 0x10);\n\treg_r(gspca_dev, ET_GPIO_IN, 1);\n\treg_w_val(gspca_dev, ET_ClCK, 0x14); /* 0x14 // 0x16 enabled pattern */\n\treg_w_val(gspca_dev, ET_CTRL, 0x1b);\n\n\t/*  compression et subsampling */\n\tif (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv)\n\t\tvalue = ET_COMP_VAL1;\t/* 320 */\n\telse\n\t\tvalue = ET_COMP_VAL0;\t/* 640 */\n\treg_w_val(gspca_dev, ET_COMP, value);\n\treg_w_val(gspca_dev, ET_MAXQt, 0x1f);\n\treg_w_val(gspca_dev, ET_MINQt, 0x04);\n\t/* undocumented registers */\n\treg_w_val(gspca_dev, ET_REG1d, 0xff);\n\treg_w_val(gspca_dev, ET_REG1e, 0xff);\n\treg_w_val(gspca_dev, ET_REG1f, 0xff);\n\treg_w_val(gspca_dev, ET_REG20, 0x35);\n\treg_w_val(gspca_dev, ET_REG21, 0x01);\n\treg_w_val(gspca_dev, ET_REG22, 0x00);\n\treg_w_val(gspca_dev, ET_REG23, 0xff);\n\treg_w_val(gspca_dev, ET_REG24, 0xff);\n\treg_w_val(gspca_dev, ET_REG25, 0x0f);\n\t/* colors setting */\n\treg_w_val(gspca_dev, 0x30, 0x11);\t\t/* 0x30 */\n\treg_w_val(gspca_dev, 0x31, 0x40);\n\treg_w_val(gspca_dev, 0x32, 0x00);\n\treg_w_val(gspca_dev, ET_O_RED, 0x00);\t\t/* 0x34 */\n\treg_w_val(gspca_dev, ET_O_GREEN1, 0x00);\n\treg_w_val(gspca_dev, ET_O_BLUE, 0x00);\n\treg_w_val(gspca_dev, ET_O_GREEN2, 0x00);\n\t/*************/\n\treg_w_val(gspca_dev, ET_G_RED, 0x80);\t\t/* 0x4d */\n\treg_w_val(gspca_dev, ET_G_GREEN1, 0x80);\n\treg_w_val(gspca_dev, ET_G_BLUE, 0x80);\n\treg_w_val(gspca_dev, ET_G_GREEN2, 0x80);\n\treg_w_val(gspca_dev, ET_G_GR_H, 0x00);\n\treg_w_val(gspca_dev, ET_G_GB_H, 0x00);\t\t/* 0x52 */\n\t/* Window control registers */\n\treg_w_val(gspca_dev, 0x61, 0x80);\t\t/* use cmc_out */\n\treg_w_val(gspca_dev, 0x62, 0x02);\n\treg_w_val(gspca_dev, 0x63, 0x03);\n\treg_w_val(gspca_dev, 0x64, 0x14);\n\treg_w_val(gspca_dev, 0x65, 0x0e);\n\treg_w_val(gspca_dev, 0x66, 0x02);\n\treg_w_val(gspca_dev, 0x67, 0x02);\n\n\t/**************************************/\n\treg_w_val(gspca_dev, ET_SYNCHRO, 0x8f);\t\t/* 0x68 */\n\treg_w_val(gspca_dev, ET_STARTX, 0x69);\t\t/* 0x6a //0x69 */\n\treg_w_val(gspca_dev, ET_STARTY, 0x0d);\t\t/* 0x0d //0x0c */\n\treg_w_val(gspca_dev, ET_WIDTH_LOW, 0x80);\n\treg_w_val(gspca_dev, ET_HEIGTH_LOW, 0xe0);\n\treg_w_val(gspca_dev, ET_W_H_HEIGTH, 0x60);\t/* 6d */\n\treg_w_val(gspca_dev, ET_REG6e, 0x86);\n\treg_w_val(gspca_dev, ET_REG6f, 0x01);\n\treg_w_val(gspca_dev, ET_REG70, 0x26);\n\treg_w_val(gspca_dev, ET_REG71, 0x7a);\n\treg_w_val(gspca_dev, ET_REG72, 0x01);\n\t/* Clock Pattern registers ***************** */\n\treg_w_val(gspca_dev, ET_REG73, 0x00);\n\treg_w_val(gspca_dev, ET_REG74, 0x18);\t\t/* 0x28 */\n\treg_w_val(gspca_dev, ET_REG75, 0x0f);\t\t/* 0x01 */\n\t/**********************************************/\n\treg_w_val(gspca_dev, 0x8a, 0x20);\n\treg_w_val(gspca_dev, 0x8d, 0x0f);\n\treg_w_val(gspca_dev, 0x8e, 0x08);\n\t/**************************************/\n\treg_w_val(gspca_dev, 0x03, 0x08);\n\treg_w_val(gspca_dev, ET_PXL_CLK, 0x03);\n\treg_w_val(gspca_dev, 0x81, 0xff);\n\treg_w_val(gspca_dev, 0x80, 0x00);\n\treg_w_val(gspca_dev, 0x81, 0xff);\n\treg_w_val(gspca_dev, 0x80, 0x20);\n\treg_w_val(gspca_dev, 0x03, 0x01);\n\treg_w_val(gspca_dev, 0x03, 0x00);\n\treg_w_val(gspca_dev, 0x03, 0x08);\n\t/********************************************/\n\n/*\treg_r(gspca_dev, ET_I2C_BASE, 1);\n\t\t\t\t\t always 0x40 as the pas106 ??? */\n\t/* set the sensor */\n\tif (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv)\n\t\tvalue = 0x04;\t\t/* 320 */\n\telse\t\t\t\t/* 640 */\n\t\tvalue = 0x1e;\t/* 0x17\t * setting PixelClock\n\t\t\t\t\t * 0x03 mean 24/(3+1) = 6 Mhz\n\t\t\t\t\t * 0x05 -> 24/(5+1) = 4 Mhz\n\t\t\t\t\t * 0x0b -> 24/(11+1) = 2 Mhz\n\t\t\t\t\t * 0x17 -> 24/(23+1) = 1 Mhz\n\t\t\t\t\t */\n\treg_w_val(gspca_dev, ET_PXL_CLK, value);\n\t/* now set by fifo the FormatLine setting */\n\treg_w(gspca_dev, 0x62, FormLine, 6);\n\n\t/* set exposure times [ 0..0x78] 0->longvalue 0x78->shortvalue */\n\treg_w_val(gspca_dev, 0x81, 0x47);\t/* 0x47; */\n\treg_w_val(gspca_dev, 0x80, 0x40);\t/* 0x40; */\n\t/* Pedro change */\n\t/* Brightness change Brith+ decrease value */\n\t/* Brigth- increase value */\n\t/* original value = 0x70; */\n\treg_w_val(gspca_dev, 0x81, 0x30);\t/* 0x20; - set brightness */\n\treg_w_val(gspca_dev, 0x80, 0x20);\t/* 0x20; */\n}",
        "static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)\n{\n\tstruct bnx2x *bp = params->bp;\n\tconst u8 port = params->port;\n\tconst u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;": "static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)\n{\n\tstruct bnx2x *bp = params->bp;\n\tconst u8 port = params->port;\n\tconst u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;\n\tu8 i = 0;\n\tu32 base_weight = 0;\n\tu8 max_cos = 0;\n\n\t/* Mapping between entry  priority to client number 0 - COS0\n\t * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.\n\t * TODO_ETS - Should be done by reset value or init tool\n\t */\n\tif (port)\n\t\t/*  0x688 (|011|0 10|00 1|000) */\n\t\tREG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);\n\telse\n\t\t/*  (10 1|100 |011|0 10|00 1|000) */\n\t\tREG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);\n\n\t/* TODO_ETS - Should be done by reset value or init tool */\n\tif (port)\n\t\t/* 0x688 (|011|0 10|00 1|000)*/\n\t\tREG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);\n\telse\n\t/* 0x2C688 (10 1|100 |011|0 10|00 1|000) */\n\tREG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);\n\n\tREG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :\n\t\t   PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);\n\n\n\tREG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :\n\t\t   PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);\n\n\tREG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :\n\t\t   PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);\n\t/* In 2 port mode port0 has COS0-5 that can be used for WFQ.\n\t * In 4 port mode port1 has COS0-2 that can be used for WFQ.\n\t */\n\tif (!port) {\n\t\tbase_weight = PBF_REG_COS0_WEIGHT_P0;\n\t\tmax_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;\n\t} else {\n\t\tbase_weight = PBF_REG_COS0_WEIGHT_P1;\n\t\tmax_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;\n\t}\n\n\tfor (i = 0; i < max_cos; i++)\n\t\tREG_WR(bp, base_weight + (0x4 * i), 0);\n\n\tbnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);\n}",
        "static void hd44780_write_gpio4(struct hd44780 *hd, u8 val, unsigned int rs)\n{\n\tDECLARE_BITMAP(values, 6); /* for DATA[4-7], RS, RW */\n\tunsigned int n;\n": "static void hd44780_write_gpio4(struct hd44780 *hd, u8 val, unsigned int rs)\n{\n\tDECLARE_BITMAP(values, 6); /* for DATA[4-7], RS, RW */\n\tunsigned int n;\n\n\t/* High nibble + RS, RW */\n\tvalues[0] = val >> 4;\n\t__assign_bit(4, values, rs);\n\tn = hd->pins[PIN_CTRL_RW] ? 6 : 5;\n\n\t/* Present the data to the port */\n\tgpiod_set_array_value_cansleep(n, &hd->pins[PIN_DATA4], NULL, values);\n\n\thd44780_strobe_gpio(hd);\n\n\t/* Low nibble */\n\tvalues[0] &= ~0x0fUL;\n\tvalues[0] |= val & 0x0f;\n\n\t/* Present the data to the port */\n\tgpiod_set_array_value_cansleep(n, &hd->pins[PIN_DATA4], NULL, values);\n\n\thd44780_strobe_gpio(hd);\n}",
        "static void subflow_finish_connect(struct sock *sk, const struct sk_buff *skb)\n{\n\tstruct mptcp_subflow_context *subflow = mptcp_subflow_ctx(sk);\n\tstruct mptcp_options_received mp_opt;\n\tstruct sock *parent = subflow->conn;": "static void subflow_finish_connect(struct sock *sk, const struct sk_buff *skb)\n{\n\tstruct mptcp_subflow_context *subflow = mptcp_subflow_ctx(sk);\n\tstruct mptcp_options_received mp_opt;\n\tstruct sock *parent = subflow->conn;\n\n\tsubflow->icsk_af_ops->sk_rx_dst_set(sk, skb);\n\n\t/* be sure no special action on any packet other than syn-ack */\n\tif (subflow->conn_finished)\n\t\treturn;\n\n\tmptcp_propagate_sndbuf(parent, sk);\n\tsubflow->rel_write_seq = 1;\n\tsubflow->conn_finished = 1;\n\tsubflow->ssn_offset = TCP_SKB_CB(skb)->seq;\n\tpr_debug(\"subflow=%p synack seq=%x\", subflow, subflow->ssn_offset);\n\n\tmptcp_get_options(skb, &mp_opt);\n\tif (subflow->request_mptcp) {\n\t\tif (!(mp_opt.suboptions & OPTIONS_MPTCP_MPC)) {\n\t\t\tMPTCP_INC_STATS(sock_net(sk),\n\t\t\t\t\tMPTCP_MIB_MPCAPABLEACTIVEFALLBACK);\n\t\t\tmptcp_do_fallback(sk);\n\t\t\tpr_fallback(mptcp_sk(subflow->conn));\n\t\t\tgoto fallback;\n\t\t}\n\n\t\tif (mp_opt.suboptions & OPTION_MPTCP_CSUMREQD)\n\t\t\tWRITE_ONCE(mptcp_sk(parent)->csum_enabled, true);\n\t\tif (mp_opt.deny_join_id0)\n\t\t\tWRITE_ONCE(mptcp_sk(parent)->pm.remote_deny_join_id0, true);\n\t\tsubflow->mp_capable = 1;\n\t\tsubflow->can_ack = 1;\n\t\tsubflow->remote_key = mp_opt.sndr_key;\n\t\tpr_debug(\"subflow=%p, remote_key=%llu\", subflow,\n\t\t\t subflow->remote_key);\n\t\tMPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPCAPABLEACTIVEACK);\n\t\tmptcp_finish_connect(sk);\n\t\tmptcp_set_connected(parent);\n\t} else if (subflow->request_join) {\n\t\tu8 hmac[SHA256_DIGEST_SIZE];\n\n\t\tif (!(mp_opt.suboptions & OPTIONS_MPTCP_MPJ)) {\n\t\t\tsubflow->reset_reason = MPTCP_RST_EMPTCP;\n\t\t\tgoto do_reset;\n\t\t}\n\n\t\tsubflow->backup = mp_opt.backup;\n\t\tsubflow->thmac = mp_opt.thmac;\n\t\tsubflow->remote_nonce = mp_opt.nonce;\n\t\tsubflow->remote_id = mp_opt.join_id;\n\t\tpr_debug(\"subflow=%p, thmac=%llu, remote_nonce=%u backup=%d\",\n\t\t\t subflow, subflow->thmac, subflow->remote_nonce,\n\t\t\t subflow->backup);\n\n\t\tif (!subflow_thmac_valid(subflow)) {\n\t\t\tMPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_JOINACKMAC);\n\t\t\tsubflow->reset_reason = MPTCP_RST_EMPTCP;\n\t\t\tgoto do_reset;\n\t\t}\n\n\t\tif (!mptcp_finish_join(sk))\n\t\t\tgoto do_reset;\n\n\t\tsubflow_generate_hmac(subflow->local_key, subflow->remote_key,\n\t\t\t\t      subflow->local_nonce,\n\t\t\t\t      subflow->remote_nonce,\n\t\t\t\t      hmac);\n\t\tmemcpy(subflow->hmac, hmac, MPTCPOPT_HMAC_LEN);\n\n\t\tsubflow->mp_join = 1;\n\t\tMPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_JOINSYNACKRX);\n\n\t\tif (subflow_use_different_dport(mptcp_sk(parent), sk)) {\n\t\t\tpr_debug(\"synack inet_dport=%d %d\",\n\t\t\t\t ntohs(inet_sk(sk)->inet_dport),\n\t\t\t\t ntohs(inet_sk(parent)->inet_dport));\n\t\t\tMPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_JOINPORTSYNACKRX);\n\t\t}\n\t} else if (mptcp_check_fallback(sk)) {\nfallback:\n\t\tmptcp_rcv_space_init(mptcp_sk(parent), sk);\n\t\tmptcp_set_connected(parent);\n\t}\n\treturn;\n\ndo_reset:\n\tsubflow->reset_transient = 0;\n\tmptcp_subflow_reset(sk);\n}",
        "static int ipv6_create_tempaddr(struct inet6_ifaddr *ifp, bool block)\n{\n\tstruct inet6_dev *idev = ifp->idev;\n\tunsigned long tmp_tstamp, age;\n\tunsigned long regen_advance;": "static int ipv6_create_tempaddr(struct inet6_ifaddr *ifp, bool block)\n{\n\tstruct inet6_dev *idev = ifp->idev;\n\tunsigned long tmp_tstamp, age;\n\tunsigned long regen_advance;\n\tunsigned long now = jiffies;\n\ts32 cnf_temp_preferred_lft;\n\tstruct inet6_ifaddr *ift;\n\tstruct ifa6_config cfg;\n\tlong max_desync_factor;\n\tstruct in6_addr addr;\n\tint ret = 0;\n\n\twrite_lock_bh(&idev->lock);\n\nretry:\n\tin6_dev_hold(idev);\n\tif (idev->cnf.use_tempaddr <= 0) {\n\t\twrite_unlock_bh(&idev->lock);\n\t\tpr_info(\"%s: use_tempaddr is disabled\\n\", __func__);\n\t\tin6_dev_put(idev);\n\t\tret = -1;\n\t\tgoto out;\n\t}\n\tspin_lock_bh(&ifp->lock);\n\tif (ifp->regen_count++ >= idev->cnf.regen_max_retry) {\n\t\tidev->cnf.use_tempaddr = -1;\t/*XXX*/\n\t\tspin_unlock_bh(&ifp->lock);\n\t\twrite_unlock_bh(&idev->lock);\n\t\tpr_warn(\"%s: regeneration time exceeded - disabled temporary address support\\n\",\n\t\t\t__func__);\n\t\tin6_dev_put(idev);\n\t\tret = -1;\n\t\tgoto out;\n\t}\n\tin6_ifa_hold(ifp);\n\tmemcpy(addr.s6_addr, ifp->addr.s6_addr, 8);\n\tipv6_gen_rnd_iid(&addr);\n\n\tage = (now - ifp->tstamp) / HZ;\n\n\tregen_advance = idev->cnf.regen_max_retry *\n\t\t\tidev->cnf.dad_transmits *\n\t\t\tmax(NEIGH_VAR(idev->nd_parms, RETRANS_TIME), HZ/100) / HZ;\n\n\t/* recalculate max_desync_factor each time and update\n\t * idev->desync_factor if it's larger\n\t */\n\tcnf_temp_preferred_lft = READ_ONCE(idev->cnf.temp_prefered_lft);\n\tmax_desync_factor = min_t(__u32,\n\t\t\t\t  idev->cnf.max_desync_factor,\n\t\t\t\t  cnf_temp_preferred_lft - regen_advance);\n\n\tif (unlikely(idev->desync_factor > max_desync_factor)) {\n\t\tif (max_desync_factor > 0) {\n\t\t\tget_random_bytes(&idev->desync_factor,\n\t\t\t\t\t sizeof(idev->desync_factor));\n\t\t\tidev->desync_factor %= max_desync_factor;\n\t\t} else {\n\t\t\tidev->desync_factor = 0;\n\t\t}\n\t}\n\n\tmemset(&cfg, 0, sizeof(cfg));\n\tcfg.valid_lft = min_t(__u32, ifp->valid_lft,\n\t\t\t      idev->cnf.temp_valid_lft + age);\n\tcfg.preferred_lft = cnf_temp_preferred_lft + age - idev->desync_factor;\n\tcfg.preferred_lft = min_t(__u32, ifp->prefered_lft, cfg.preferred_lft);\n\n\tcfg.plen = ifp->prefix_len;\n\ttmp_tstamp = ifp->tstamp;\n\tspin_unlock_bh(&ifp->lock);\n\n\twrite_unlock_bh(&idev->lock);\n\n\t/* A temporary address is created only if this calculated Preferred\n\t * Lifetime is greater than REGEN_ADVANCE time units.  In particular,\n\t * an implementation must not create a temporary address with a zero\n\t * Preferred Lifetime.\n\t * Use age calculation as in addrconf_verify to avoid unnecessary\n\t * temporary addresses being generated.\n\t */\n\tage = (now - tmp_tstamp + ADDRCONF_TIMER_FUZZ_MINUS) / HZ;\n\tif (cfg.preferred_lft <= regen_advance + age) {\n\t\tin6_ifa_put(ifp);\n\t\tin6_dev_put(idev);\n\t\tret = -1;\n\t\tgoto out;\n\t}\n\n\tcfg.ifa_flags = IFA_F_TEMPORARY;\n\t/* set in addrconf_prefix_rcv() */\n\tif (ifp->flags & IFA_F_OPTIMISTIC)\n\t\tcfg.ifa_flags |= IFA_F_OPTIMISTIC;\n\n\tcfg.pfx = &addr;\n\tcfg.scope = ipv6_addr_scope(cfg.pfx);\n\n\tift = ipv6_add_addr(idev, &cfg, block, NULL);\n\tif (IS_ERR(ift)) {\n\t\tin6_ifa_put(ifp);\n\t\tin6_dev_put(idev);\n\t\tpr_info(\"%s: retry temporary address regeneration\\n\", __func__);\n\t\twrite_lock_bh(&idev->lock);\n\t\tgoto retry;\n\t}\n\n\tspin_lock_bh(&ift->lock);\n\tift->ifpub = ifp;\n\tift->cstamp = now;\n\tift->tstamp = tmp_tstamp;\n\tspin_unlock_bh(&ift->lock);\n\n\taddrconf_dad_start(ift);\n\tin6_ifa_put(ift);\n\tin6_dev_put(idev);\nout:\n\treturn ret;\n}",
        "static int set_mclock(struct stv *state, u32 master_clock)\n{\n\tu32 idf = 1;\n\tu32 odf = 4;\n\tu32 quartz = state->base->extclk / 1000000;": "static int set_mclock(struct stv *state, u32 master_clock)\n{\n\tu32 idf = 1;\n\tu32 odf = 4;\n\tu32 quartz = state->base->extclk / 1000000;\n\tu32 fphi = master_clock / 1000000;\n\tu32 ndiv = (fphi * odf * idf) / quartz;\n\tu32 cp = 7;\n\tu32 fvco;\n\n\tif (ndiv >= 7 && ndiv <= 71)\n\t\tcp = 7;\n\telse if (ndiv >=  72 && ndiv <=  79)\n\t\tcp = 8;\n\telse if (ndiv >=  80 && ndiv <=  87)\n\t\tcp = 9;\n\telse if (ndiv >=  88 && ndiv <=  95)\n\t\tcp = 10;\n\telse if (ndiv >=  96 && ndiv <= 103)\n\t\tcp = 11;\n\telse if (ndiv >= 104 && ndiv <= 111)\n\t\tcp = 12;\n\telse if (ndiv >= 112 && ndiv <= 119)\n\t\tcp = 13;\n\telse if (ndiv >= 120 && ndiv <= 127)\n\t\tcp = 14;\n\telse if (ndiv >= 128 && ndiv <= 135)\n\t\tcp = 15;\n\telse if (ndiv >= 136 && ndiv <= 143)\n\t\tcp = 16;\n\telse if (ndiv >= 144 && ndiv <= 151)\n\t\tcp = 17;\n\telse if (ndiv >= 152 && ndiv <= 159)\n\t\tcp = 18;\n\telse if (ndiv >= 160 && ndiv <= 167)\n\t\tcp = 19;\n\telse if (ndiv >= 168 && ndiv <= 175)\n\t\tcp = 20;\n\telse if (ndiv >= 176 && ndiv <= 183)\n\t\tcp = 21;\n\telse if (ndiv >= 184 && ndiv <= 191)\n\t\tcp = 22;\n\telse if (ndiv >= 192 && ndiv <= 199)\n\t\tcp = 23;\n\telse if (ndiv >= 200 && ndiv <= 207)\n\t\tcp = 24;\n\telse if (ndiv >= 208 && ndiv <= 215)\n\t\tcp = 25;\n\telse if (ndiv >= 216 && ndiv <= 223)\n\t\tcp = 26;\n\telse if (ndiv >= 224 && ndiv <= 225)\n\t\tcp = 27;\n\n\twrite_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);\n\twrite_reg(state, RSTV0910_NCOARSE2, odf);\n\twrite_reg(state, RSTV0910_NCOARSE1, ndiv);\n\n\tfvco = (quartz * 2 * ndiv) / idf;\n\tstate->base->mclk = fvco / (2 * odf) * 1000000;\n\n\treturn 0;\n}",
        "static int validate_sku(struct mxl *state)\n{\n\tu32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;\n\tint status;\n\tu32 type = state->base->type;": "static int validate_sku(struct mxl *state)\n{\n\tu32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;\n\tint status;\n\tu32 type = state->base->type;\n\n\tstatus = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);\n\tstatus |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);\n\tstatus |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);\n\tif (status)\n\t\treturn -1;\n\n\tdev_info(state->i2cdev, \"padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\\n\",\n\t\tpad_mux_bond, prcm_chip_id, prcm_so_cid);\n\n\tif (prcm_chip_id != 0x560) {\n\t\tswitch (pad_mux_bond) {\n\t\tcase MXL_HYDRA_SKU_ID_581:\n\t\t\tif (type == MXL_HYDRA_DEVICE_581)\n\t\t\t\treturn 0;\n\t\t\tif (type == MXL_HYDRA_DEVICE_581S) {\n\t\t\t\tstate->base->type = MXL_HYDRA_DEVICE_581;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase MXL_HYDRA_SKU_ID_584:\n\t\t\tif (type == MXL_HYDRA_DEVICE_584)\n\t\t\t\treturn 0;\n\t\t\tbreak;\n\t\tcase MXL_HYDRA_SKU_ID_544:\n\t\t\tif (type == MXL_HYDRA_DEVICE_544)\n\t\t\t\treturn 0;\n\t\t\tif (type == MXL_HYDRA_DEVICE_542)\n\t\t\t\treturn 0;\n\t\t\tbreak;\n\t\tcase MXL_HYDRA_SKU_ID_582:\n\t\t\tif (type == MXL_HYDRA_DEVICE_582)\n\t\t\t\treturn 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t} else {\n\n\t}\n\treturn -1;\n}",
        "static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)\n{\n\t/* ETS disabled configuration*/\n\tstruct bnx2x *bp = params->bp;\n": "static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)\n{\n\t/* ETS disabled configuration*/\n\tstruct bnx2x *bp = params->bp;\n\n\tDP(NETIF_MSG_LINK, \"ETS E2E3 disabled configuration\\n\");\n\n\t/* mapping between entry  priority to client number (0,1,2 -debug and\n\t * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)\n\t * 3bits client num.\n\t *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0\n\t * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000\n\t */\n\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);\n\t/* Bitmap of 5bits length. Each bit specifies whether the entry behaves\n\t * as strict.  Bits 0,1,2 - debug and management entries, 3 -\n\t * COS0 entry, 4 - COS1 entry.\n\t * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT\n\t * bit4   bit3\t  bit2   bit1\t  bit0\n\t * MCP and debug are strict\n\t */\n\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);\n\t/* defines which entries (clients) are subjected to WFQ arbitration */\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);\n\t/* For strict priority entries defines the number of consecutive\n\t * slots for the highest priority.\n\t */\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);\n\t/* mapping between the CREDIT_WEIGHT registers and actual client\n\t * numbers\n\t */\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);\n\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);\n\tREG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);\n\t/* ETS mode disable */\n\tREG_WR(bp, PBF_REG_ETS_ENABLED, 0);\n\t/* If ETS mode is enabled (there is no strict priority) defines a WFQ\n\t * weight for COS0/COS1.\n\t */\n\tREG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);\n\tREG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);\n\t/* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */\n\tREG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);\n\tREG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);\n\t/* Defines the number of consecutive slots for the strict priority */\n\tREG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);\n}",
        "static int alc_auto_parse_customize_define(struct hda_codec *codec)\n{\n\tunsigned int ass, tmp, i;\n\tunsigned nid = 0;\n\tstruct alc_spec *spec = codec->spec;": "static int alc_auto_parse_customize_define(struct hda_codec *codec)\n{\n\tunsigned int ass, tmp, i;\n\tunsigned nid = 0;\n\tstruct alc_spec *spec = codec->spec;\n\n\tspec->cdefine.enable_pcbeep = 1; /* assume always enabled */\n\n\tif (spec->cdefine.fixup) {\n\t\tass = spec->cdefine.sku_cfg;\n\t\tif (ass == ALC_FIXUP_SKU_IGNORE)\n\t\t\treturn -1;\n\t\tgoto do_sku;\n\t}\n\n\tif (!codec->bus->pci)\n\t\treturn -1;\n\tass = codec->core.subsystem_id & 0xffff;\n\tif (ass != codec->bus->pci->subsystem_device && (ass & 1))\n\t\tgoto do_sku;\n\n\tnid = 0x1d;\n\tif (codec->core.vendor_id == 0x10ec0260)\n\t\tnid = 0x17;\n\tass = snd_hda_codec_get_pincfg(codec, nid);\n\n\tif (!(ass & 1)) {\n\t\tcodec_info(codec, \"%s: SKU not ready 0x%08x\\n\",\n\t\t\t   codec->core.chip_name, ass);\n\t\treturn -1;\n\t}\n\n\t/* check sum */\n\ttmp = 0;\n\tfor (i = 1; i < 16; i++) {\n\t\tif ((ass >> i) & 1)\n\t\t\ttmp++;\n\t}\n\tif (((ass >> 16) & 0xf) != tmp)\n\t\treturn -1;\n\n\tspec->cdefine.port_connectivity = ass >> 30;\n\tspec->cdefine.enable_pcbeep = (ass & 0x100000) >> 20;\n\tspec->cdefine.check_sum = (ass >> 16) & 0xf;\n\tspec->cdefine.customization = ass >> 8;\ndo_sku:\n\tspec->cdefine.sku_cfg = ass;\n\tspec->cdefine.external_amp = (ass & 0x38) >> 3;\n\tspec->cdefine.platform_type = (ass & 0x4) >> 2;\n\tspec->cdefine.swap = (ass & 0x2) >> 1;\n\tspec->cdefine.override = ass & 0x1;\n\n\tcodec_dbg(codec, \"SKU: Nid=0x%x sku_cfg=0x%08x\\n\",\n\t\t   nid, spec->cdefine.sku_cfg);\n\tcodec_dbg(codec, \"SKU: port_connectivity=0x%x\\n\",\n\t\t   spec->cdefine.port_connectivity);\n\tcodec_dbg(codec, \"SKU: enable_pcbeep=0x%x\\n\", spec->cdefine.enable_pcbeep);\n\tcodec_dbg(codec, \"SKU: check_sum=0x%08x\\n\", spec->cdefine.check_sum);\n\tcodec_dbg(codec, \"SKU: customization=0x%08x\\n\", spec->cdefine.customization);\n\tcodec_dbg(codec, \"SKU: external_amp=0x%x\\n\", spec->cdefine.external_amp);\n\tcodec_dbg(codec, \"SKU: platform_type=0x%x\\n\", spec->cdefine.platform_type);\n\tcodec_dbg(codec, \"SKU: swap=0x%x\\n\", spec->cdefine.swap);\n\tcodec_dbg(codec, \"SKU: override=0x%x\\n\", spec->cdefine.override);\n\n\treturn 0;\n}",
        "static void test_overflow(bool test_e2big_overflow, bool ret1)\n{\n\t__u32 map_info_len, total_read_len, expected_read_len;\n\tint err, iter_fd, map1_fd, map2_fd, len;\n\tstruct bpf_map_info map_info = {};": "static void test_overflow(bool test_e2big_overflow, bool ret1)\n{\n\t__u32 map_info_len, total_read_len, expected_read_len;\n\tint err, iter_fd, map1_fd, map2_fd, len;\n\tstruct bpf_map_info map_info = {};\n\tstruct bpf_iter_test_kern4 *skel;\n\tstruct bpf_link *link;\n\t__u32 iter_size;\n\tchar *buf;\n\n\tskel = bpf_iter_test_kern4__open();\n\tif (!ASSERT_OK_PTR(skel, \"bpf_iter_test_kern4__open\"))\n\t\treturn;\n\n\t/* create two maps: bpf program will only do bpf_seq_write\n\t * for these two maps. The goal is one map output almost\n\t * fills seq_file buffer and then the other will trigger\n\t * overflow and needs restart.\n\t */\n\tmap1_fd = bpf_map_create(BPF_MAP_TYPE_ARRAY, NULL, 4, 8, 1, NULL);\n\tif (CHECK(map1_fd < 0, \"bpf_map_create\",\n\t\t  \"map_creation failed: %s\\n\", strerror(errno)))\n\t\tgoto out;\n\tmap2_fd = bpf_map_create(BPF_MAP_TYPE_ARRAY, NULL, 4, 8, 1, NULL);\n\tif (CHECK(map2_fd < 0, \"bpf_map_create\",\n\t\t  \"map_creation failed: %s\\n\", strerror(errno)))\n\t\tgoto free_map1;\n\n\t/* bpf_seq_printf kernel buffer is 8 pages, so one map\n\t * bpf_seq_write will mostly fill it, and the other map\n\t * will partially fill and then trigger overflow and need\n\t * bpf_seq_read restart.\n\t */\n\titer_size = sysconf(_SC_PAGE_SIZE) << 3;\n\n\tif (test_e2big_overflow) {\n\t\tskel->rodata->print_len = (iter_size + 8) / 8;\n\t\texpected_read_len = 2 * (iter_size + 8);\n\t} else if (!ret1) {\n\t\tskel->rodata->print_len = (iter_size - 8) / 8;\n\t\texpected_read_len = 2 * (iter_size - 8);\n\t} else {\n\t\tskel->rodata->print_len = 1;\n\t\texpected_read_len = 2 * 8;\n\t}\n\tskel->rodata->ret1 = ret1;\n\n\tif (!ASSERT_OK(bpf_iter_test_kern4__load(skel),\n\t\t  \"bpf_iter_test_kern4__load\"))\n\t\tgoto free_map2;\n\n\t/* setup filtering map_id in bpf program */\n\tmap_info_len = sizeof(map_info);\n\terr = bpf_obj_get_info_by_fd(map1_fd, &map_info, &map_info_len);\n\tif (CHECK(err, \"get_map_info\", \"get map info failed: %s\\n\",\n\t\t  strerror(errno)))\n\t\tgoto free_map2;\n\tskel->bss->map1_id = map_info.id;\n\n\terr = bpf_obj_get_info_by_fd(map2_fd, &map_info, &map_info_len);\n\tif (CHECK(err, \"get_map_info\", \"get map info failed: %s\\n\",\n\t\t  strerror(errno)))\n\t\tgoto free_map2;\n\tskel->bss->map2_id = map_info.id;\n\n\tlink = bpf_program__attach_iter(skel->progs.dump_bpf_map, NULL);\n\tif (!ASSERT_OK_PTR(link, \"attach_iter\"))\n\t\tgoto free_map2;\n\n\titer_fd = bpf_iter_create(bpf_link__fd(link));\n\tif (!ASSERT_GE(iter_fd, 0, \"create_iter\"))\n\t\tgoto free_link;\n\n\tbuf = malloc(expected_read_len);\n\tif (!buf)\n\t\tgoto close_iter;\n\n\t/* do read */\n\ttotal_read_len = 0;\n\tif (test_e2big_overflow) {\n\t\twhile ((len = read(iter_fd, buf, expected_read_len)) > 0)\n\t\t\ttotal_read_len += len;\n\n\t\tCHECK(len != -1 || errno != E2BIG, \"read\",\n\t\t      \"expected ret -1, errno E2BIG, but get ret %d, error %s\\n\",\n\t\t\t  len, strerror(errno));\n\t\tgoto free_buf;\n\t} else if (!ret1) {\n\t\twhile ((len = read(iter_fd, buf, expected_read_len)) > 0)\n\t\t\ttotal_read_len += len;\n\n\t\tif (CHECK(len < 0, \"read\", \"read failed: %s\\n\",\n\t\t\t  strerror(errno)))\n\t\t\tgoto free_buf;\n\t} else {\n\t\tdo {\n\t\t\tlen = read(iter_fd, buf, expected_read_len);\n\t\t\tif (len > 0)\n\t\t\t\ttotal_read_len += len;\n\t\t} while (len > 0 || len == -EAGAIN);\n\n\t\tif (CHECK(len < 0, \"read\", \"read failed: %s\\n\",\n\t\t\t  strerror(errno)))\n\t\t\tgoto free_buf;\n\t}\n\n\tif (!ASSERT_EQ(total_read_len, expected_read_len, \"read\"))\n\t\tgoto free_buf;\n\n\tif (!ASSERT_EQ(skel->bss->map1_accessed, 1, \"map1_accessed\"))\n\t\tgoto free_buf;\n\n\tif (!ASSERT_EQ(skel->bss->map2_accessed, 2, \"map2_accessed\"))\n\t\tgoto free_buf;\n\n\tASSERT_EQ(skel->bss->map2_seqnum1, skel->bss->map2_seqnum2, \"map2_seqnum\");\n\nfree_buf:\n\tfree(buf);\nclose_iter:\n\tclose(iter_fd);\nfree_link:\n\tbpf_link__destroy(link);\nfree_map2:\n\tclose(map2_fd);\nfree_map1:\n\tclose(map1_fd);\nout:\n\tbpf_iter_test_kern4__destroy(skel);\n}",
        "static int quad8_events_configure(struct counter_device *counter)\n{\n\tstruct quad8 *const priv = counter_priv(counter);\n\tunsigned long irq_enabled = 0;\n\tunsigned long irqflags;": "static int quad8_events_configure(struct counter_device *counter)\n{\n\tstruct quad8 *const priv = counter_priv(counter);\n\tunsigned long irq_enabled = 0;\n\tunsigned long irqflags;\n\tstruct counter_event_node *event_node;\n\tunsigned int next_irq_trigger;\n\tunsigned long ior_cfg;\n\tunsigned long base_offset;\n\n\tspin_lock_irqsave(&priv->lock, irqflags);\n\n\tlist_for_each_entry(event_node, &counter->events_list, l) {\n\t\tswitch (event_node->event) {\n\t\tcase COUNTER_EVENT_OVERFLOW:\n\t\t\tnext_irq_trigger = QUAD8_EVENT_CARRY;\n\t\t\tbreak;\n\t\tcase COUNTER_EVENT_THRESHOLD:\n\t\t\tnext_irq_trigger = QUAD8_EVENT_COMPARE;\n\t\t\tbreak;\n\t\tcase COUNTER_EVENT_OVERFLOW_UNDERFLOW:\n\t\t\tnext_irq_trigger = QUAD8_EVENT_CARRY_BORROW;\n\t\t\tbreak;\n\t\tcase COUNTER_EVENT_INDEX:\n\t\t\tnext_irq_trigger = QUAD8_EVENT_INDEX;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* should never reach this path */\n\t\t\tspin_unlock_irqrestore(&priv->lock, irqflags);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\t/* Skip configuration if it is the same as previously set */\n\t\tif (priv->irq_trigger[event_node->channel] == next_irq_trigger)\n\t\t\tcontinue;\n\n\t\t/* Save new IRQ function configuration */\n\t\tpriv->irq_trigger[event_node->channel] = next_irq_trigger;\n\n\t\t/* Load configuration to I/O Control Register */\n\t\tior_cfg = priv->ab_enable[event_node->channel] |\n\t\t\t  priv->preset_enable[event_node->channel] << 1 |\n\t\t\t  priv->irq_trigger[event_node->channel] << 3;\n\t\tbase_offset = priv->base + 2 * event_node->channel + 1;\n\t\toutb(QUAD8_CTR_IOR | ior_cfg, base_offset);\n\n\t\t/* Enable IRQ line */\n\t\tirq_enabled |= BIT(event_node->channel);\n\t}\n\n\toutb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);\n\n\tspin_unlock_irqrestore(&priv->lock, irqflags);\n\n\treturn 0;\n}",
        "static int test_cgcore_lesser_ns_open(const char *root)\n{\n\tstatic char stack[65536];\n\tconst uid_t test_euid = 65534;\t/* usually nobody, any !root is fine */\n\tint ret = KSFT_FAIL;": "static int test_cgcore_lesser_ns_open(const char *root)\n{\n\tstatic char stack[65536];\n\tconst uid_t test_euid = 65534;\t/* usually nobody, any !root is fine */\n\tint ret = KSFT_FAIL;\n\tchar *cg_test_a = NULL, *cg_test_b = NULL;\n\tchar *cg_test_a_procs = NULL, *cg_test_b_procs = NULL;\n\tint cg_test_b_procs_fd = -1;\n\tstruct lesser_ns_open_thread_arg targ = { .fd = -1 };\n\tpid_t pid;\n\tint status;\n\n\tcg_test_a = cg_name(root, \"cg_test_a\");\n\tcg_test_b = cg_name(root, \"cg_test_b\");\n\n\tif (!cg_test_a || !cg_test_b)\n\t\tgoto cleanup;\n\n\tcg_test_a_procs = cg_name(cg_test_a, \"cgroup.procs\");\n\tcg_test_b_procs = cg_name(cg_test_b, \"cgroup.procs\");\n\n\tif (!cg_test_a_procs || !cg_test_b_procs)\n\t\tgoto cleanup;\n\n\tif (cg_create(cg_test_a) || cg_create(cg_test_b))\n\t\tgoto cleanup;\n\n\tif (cg_enter_current(cg_test_b))\n\t\tgoto cleanup;\n\n\tif (chown(cg_test_a_procs, test_euid, -1) ||\n\t    chown(cg_test_b_procs, test_euid, -1))\n\t\tgoto cleanup;\n\n\ttarg.path = cg_test_b_procs;\n\tpid = clone(lesser_ns_open_thread_fn, stack + sizeof(stack),\n\t\t    CLONE_NEWCGROUP | CLONE_FILES | CLONE_VM | SIGCHLD,\n\t\t    &targ);\n\tif (pid < 0)\n\t\tgoto cleanup;\n\n\tif (waitpid(pid, &status, 0) < 0)\n\t\tgoto cleanup;\n\n\tif (!WIFEXITED(status))\n\t\tgoto cleanup;\n\n\tcg_test_b_procs_fd = targ.fd;\n\tif (cg_test_b_procs_fd < 0)\n\t\tgoto cleanup;\n\n\tif (cg_enter_current(cg_test_a))\n\t\tgoto cleanup;\n\n\tif ((status = write(cg_test_b_procs_fd, \"0\", 1)) >= 0 || errno != ENOENT)\n\t\tgoto cleanup;\n\n\tret = KSFT_PASS;\n\ncleanup:\n\tcg_enter_current(root);\n\tif (cg_test_b_procs_fd >= 0)\n\t\tclose(cg_test_b_procs_fd);\n\tif (cg_test_b)\n\t\tcg_destroy(cg_test_b);\n\tif (cg_test_a)\n\t\tcg_destroy(cg_test_a);\n\tfree(cg_test_b_procs);\n\tfree(cg_test_a_procs);\n\tfree(cg_test_b);\n\tfree(cg_test_a);\n\treturn ret;\n}",
        "static int t7xx_cldma_gpd_rx_from_q(struct cldma_queue *queue, int budget, bool *over_budget)\n{\n\tstruct cldma_ctrl *md_ctrl = queue->md_ctrl;\n\tunsigned int hwo_polling_count = 0;\n\tstruct t7xx_cldma_hw *hw_info;": "static int t7xx_cldma_gpd_rx_from_q(struct cldma_queue *queue, int budget, bool *over_budget)\n{\n\tstruct cldma_ctrl *md_ctrl = queue->md_ctrl;\n\tunsigned int hwo_polling_count = 0;\n\tstruct t7xx_cldma_hw *hw_info;\n\tbool rx_not_done = true;\n\tunsigned long flags;\n\tint count = 0;\n\n\thw_info = &md_ctrl->hw_info;\n\n\tdo {\n\t\tstruct cldma_request *req;\n\t\tstruct cldma_gpd *gpd;\n\t\tstruct sk_buff *skb;\n\t\tint ret;\n\n\t\treq = queue->tr_done;\n\t\tif (!req)\n\t\t\treturn -ENODATA;\n\n\t\tgpd = req->gpd;\n\t\tif ((gpd->flags & GPD_FLAGS_HWO) || !req->skb) {\n\t\t\tdma_addr_t gpd_addr;\n\n\t\t\tif (!pci_device_is_present(to_pci_dev(md_ctrl->dev))) {\n\t\t\t\tdev_err(md_ctrl->dev, \"PCIe Link disconnected\\n\");\n\t\t\t\treturn -ENODEV;\n\t\t\t}\n\n\t\t\tgpd_addr = ioread64(hw_info->ap_pdn_base + REG_CLDMA_DL_CURRENT_ADDRL_0 +\n\t\t\t\t\t    queue->index * sizeof(u64));\n\t\t\tif (req->gpd_addr == gpd_addr || hwo_polling_count++ >= 100)\n\t\t\t\treturn 0;\n\n\t\t\tudelay(1);\n\t\t\tcontinue;\n\t\t}\n\n\t\thwo_polling_count = 0;\n\t\tskb = req->skb;\n\n\t\tif (req->mapped_buff) {\n\t\t\tdma_unmap_single(md_ctrl->dev, req->mapped_buff,\n\t\t\t\t\t queue->tr_ring->pkt_size, DMA_FROM_DEVICE);\n\t\t\treq->mapped_buff = 0;\n\t\t}\n\n\t\tskb->len = 0;\n\t\tskb_reset_tail_pointer(skb);\n\t\tskb_put(skb, le16_to_cpu(gpd->data_buff_len));\n\n\t\tret = md_ctrl->recv_skb(queue, skb);\n\t\t/* Break processing, will try again later */\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\treq->skb = NULL;\n\t\tt7xx_cldma_gpd_set_data_ptr(gpd, 0);\n\n\t\tspin_lock_irqsave(&queue->ring_lock, flags);\n\t\tqueue->tr_done = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry);\n\t\tspin_unlock_irqrestore(&queue->ring_lock, flags);\n\t\treq = queue->rx_refill;\n\n\t\tret = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, queue->tr_ring->pkt_size, GFP_KERNEL);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tgpd = req->gpd;\n\t\tt7xx_cldma_gpd_set_data_ptr(gpd, req->mapped_buff);\n\t\tgpd->data_buff_len = 0;\n\t\tgpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO;\n\n\t\tspin_lock_irqsave(&queue->ring_lock, flags);\n\t\tqueue->rx_refill = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry);\n\t\tspin_unlock_irqrestore(&queue->ring_lock, flags);\n\n\t\trx_not_done = ++count < budget || !need_resched();\n\t} while (rx_not_done);\n\n\t*over_budget = true;\n\treturn 0;\n}",
        "static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)\n{\n\tint ret = good_frame;\n\tu32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;\n": "static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)\n{\n\tint ret = good_frame;\n\tu32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;\n\n\t/* bits 5 7 0 | Frame status\n\t * ----------------------------------------------------------\n\t *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)\n\t *      1 0 0 | IPv4/6 No CSUM errorS.\n\t *      1 0 1 | IPv4/6 CSUM PAYLOAD error\n\t *      1 1 0 | IPv4/6 CSUM IP HR error\n\t *      1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS\n\t *      0 0 1 | IPv4/6 unsupported IP PAYLOAD\n\t *      0 1 1 | COE bypassed.. no IPv4/6 frame\n\t *      0 1 0 | Reserved.\n\t */\n\tif (status == 0x0)\n\t\tret = llc_snap;\n\telse if (status == 0x4)\n\t\tret = good_frame;\n\telse if (status == 0x5)\n\t\tret = csum_none;\n\telse if (status == 0x6)\n\t\tret = csum_none;\n\telse if (status == 0x7)\n\t\tret = csum_none;\n\telse if (status == 0x1)\n\t\tret = discard_frame;\n\telse if (status == 0x3)\n\t\tret = discard_frame;\n\treturn ret;\n}",
        "static void test_tailcall_5(void)\n{\n\tint err, map_fd, prog_fd, main_fd, data_fd, i, key[] = { 1111, 1234, 5678 };\n\tstruct bpf_map *prog_array, *data_map;\n\tstruct bpf_program *prog;": "static void test_tailcall_5(void)\n{\n\tint err, map_fd, prog_fd, main_fd, data_fd, i, key[] = { 1111, 1234, 5678 };\n\tstruct bpf_map *prog_array, *data_map;\n\tstruct bpf_program *prog;\n\tstruct bpf_object *obj;\n\tstatic const int zero = 0;\n\tchar buff[128] = {};\n\tchar prog_name[32];\n\tLIBBPF_OPTS(bpf_test_run_opts, topts,\n\t\t.data_in = buff,\n\t\t.data_size_in = sizeof(buff),\n\t\t.repeat = 1,\n\t);\n\n\terr = bpf_prog_test_load(\"tailcall5.o\", BPF_PROG_TYPE_SCHED_CLS, &obj,\n\t\t\t    &prog_fd);\n\tif (CHECK_FAIL(err))\n\t\treturn;\n\n\tprog = bpf_object__find_program_by_name(obj, \"entry\");\n\tif (CHECK_FAIL(!prog))\n\t\tgoto out;\n\n\tmain_fd = bpf_program__fd(prog);\n\tif (CHECK_FAIL(main_fd < 0))\n\t\tgoto out;\n\n\tprog_array = bpf_object__find_map_by_name(obj, \"jmp_table\");\n\tif (CHECK_FAIL(!prog_array))\n\t\tgoto out;\n\n\tmap_fd = bpf_map__fd(prog_array);\n\tif (CHECK_FAIL(map_fd < 0))\n\t\tgoto out;\n\n\tdata_map = bpf_object__find_map_by_name(obj, \"tailcall.bss\");\n\tif (CHECK_FAIL(!data_map || !bpf_map__is_internal(data_map)))\n\t\treturn;\n\n\tdata_fd = bpf_map__fd(data_map);\n\tif (CHECK_FAIL(map_fd < 0))\n\t\treturn;\n\n\tfor (i = 0; i < bpf_map__max_entries(prog_array); i++) {\n\t\tsnprintf(prog_name, sizeof(prog_name), \"classifier_%d\", i);\n\n\t\tprog = bpf_object__find_program_by_name(obj, prog_name);\n\t\tif (CHECK_FAIL(!prog))\n\t\t\tgoto out;\n\n\t\tprog_fd = bpf_program__fd(prog);\n\t\tif (CHECK_FAIL(prog_fd < 0))\n\t\t\tgoto out;\n\n\t\terr = bpf_map_update_elem(map_fd, &i, &prog_fd, BPF_ANY);\n\t\tif (CHECK_FAIL(err))\n\t\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < bpf_map__max_entries(prog_array); i++) {\n\t\terr = bpf_map_update_elem(data_fd, &zero, &key[i], BPF_ANY);\n\t\tif (CHECK_FAIL(err))\n\t\t\tgoto out;\n\n\t\terr = bpf_prog_test_run_opts(main_fd, &topts);\n\t\tASSERT_OK(err, \"tailcall\");\n\t\tASSERT_EQ(topts.retval, i, \"tailcall retval\");\n\t}\n\n\tfor (i = 0; i < bpf_map__max_entries(prog_array); i++) {\n\t\terr = bpf_map_update_elem(data_fd, &zero, &key[i], BPF_ANY);\n\t\tif (CHECK_FAIL(err))\n\t\t\tgoto out;\n\n\t\terr = bpf_map_delete_elem(map_fd, &i);\n\t\tif (CHECK_FAIL(err))\n\t\t\tgoto out;\n\n\t\terr = bpf_prog_test_run_opts(main_fd, &topts);\n\t\tASSERT_OK(err, \"tailcall\");\n\t\tASSERT_EQ(topts.retval, 3, \"tailcall retval\");\n\t}\nout:\n\tbpf_object__close(obj);\n}",
        "static unsigned char update_suffix(struct key_vector *tn)\n{\n\tunsigned char slen = tn->pos;\n\tunsigned long stride, i;\n\tunsigned char slen_max;": "static unsigned char update_suffix(struct key_vector *tn)\n{\n\tunsigned char slen = tn->pos;\n\tunsigned long stride, i;\n\tunsigned char slen_max;\n\n\t/* only vector 0 can have a suffix length greater than or equal to\n\t * tn->pos + tn->bits, the second highest node will have a suffix\n\t * length at most of tn->pos + tn->bits - 1\n\t */\n\tslen_max = min_t(unsigned char, tn->pos + tn->bits - 1, tn->slen);\n\n\t/* search though the list of children looking for nodes that might\n\t * have a suffix greater than the one we currently have.  This is\n\t * why we start with a stride of 2 since a stride of 1 would\n\t * represent the nodes with suffix length equal to tn->pos\n\t */\n\tfor (i = 0, stride = 0x2ul ; i < child_length(tn); i += stride) {\n\t\tstruct key_vector *n = get_child(tn, i);\n\n\t\tif (!n || (n->slen <= slen))\n\t\t\tcontinue;\n\n\t\t/* update stride and slen based on new value */\n\t\tstride <<= (n->slen - slen);\n\t\tslen = n->slen;\n\t\ti &= ~(stride - 1);\n\n\t\t/* stop searching if we have hit the maximum possible value */\n\t\tif (slen >= slen_max)\n\t\t\tbreak;\n\t}\n\n\ttn->slen = slen;\n\n\treturn slen;\n}",
        "static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)\n{\n\tunsigned int delta, tolerance;\n\tint xm, xn, xr;\n": "static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)\n{\n\tunsigned int delta, tolerance;\n\tint xm, xn, xr;\n\n\tfor (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))\n\t\trate <<= 1;\n\t*n = -1;\n\tif (*r > 0xff)\n\t\tgoto out;\n\ttolerance = rate*CM_TOLERANCE_RATE;\n\n\tfor (xn = (1+2); xn < (0x1f+2); xn++) {\n\t\tfor (xm = (1+2); xm < (0xff+2); xm++) {\n\t\t\txr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;\n\n\t\t\tif (xr < rate)\n\t\t\t\tdelta = rate - xr;\n\t\t\telse\n\t\t\t\tdelta = xr - rate;\n\n\t\t\t/*\n\t\t\t * If we found one, remember this,\n\t\t\t * and try to find a closer one\n\t\t\t */\n\t\t\tif (delta < tolerance) {\n\t\t\t\ttolerance = delta;\n\t\t\t\t*m = xm - 2;\n\t\t\t\t*n = xn - 2;\n\t\t\t}\n\t\t}\n\t}\nout:\n\treturn (*n > -1);\n}",
        "static void vm_remove_mappings(struct vm_struct *area, int deallocate_pages)\n{\n\tunsigned long start = ULONG_MAX, end = 0;\n\tunsigned int page_order = vm_area_page_order(area);\n\tint flush_reset = area->flags & VM_FLUSH_RESET_PERMS;": "static void vm_remove_mappings(struct vm_struct *area, int deallocate_pages)\n{\n\tunsigned long start = ULONG_MAX, end = 0;\n\tunsigned int page_order = vm_area_page_order(area);\n\tint flush_reset = area->flags & VM_FLUSH_RESET_PERMS;\n\tint flush_dmap = 0;\n\tint i;\n\n\tremove_vm_area(area->addr);\n\n\t/* If this is not VM_FLUSH_RESET_PERMS memory, no need for the below. */\n\tif (!flush_reset)\n\t\treturn;\n\n\t/*\n\t * If not deallocating pages, just do the flush of the VM area and\n\t * return.\n\t */\n\tif (!deallocate_pages) {\n\t\tvm_unmap_aliases();\n\t\treturn;\n\t}\n\n\t/*\n\t * If execution gets here, flush the vm mapping and reset the direct\n\t * map. Find the start and end range of the direct mappings to make sure\n\t * the vm_unmap_aliases() flush includes the direct map.\n\t */\n\tfor (i = 0; i < area->nr_pages; i += 1U << page_order) {\n\t\tunsigned long addr = (unsigned long)page_address(area->pages[i]);\n\t\tif (addr) {\n\t\t\tunsigned long page_size;\n\n\t\t\tpage_size = PAGE_SIZE << page_order;\n\t\t\tstart = min(addr, start);\n\t\t\tend = max(addr + page_size, end);\n\t\t\tflush_dmap = 1;\n\t\t}\n\t}\n\n\t/*\n\t * Set direct map to something invalid so that it won't be cached if\n\t * there are any accesses after the TLB flush, then flush the TLB and\n\t * reset the direct map permissions to the default.\n\t */\n\tset_area_direct_map(area, set_direct_map_invalid_noflush);\n\t_vm_unmap_aliases(start, end, flush_dmap);\n\tset_area_direct_map(area, set_direct_map_default_noflush);\n}",
        "static void switched_from_dl(struct rq *rq, struct task_struct *p)\n{\n\t/*\n\t * task_non_contending() can start the \"inactive timer\" (if the 0-lag\n\t * time is in the future). If the task switches back to dl before": "static void switched_from_dl(struct rq *rq, struct task_struct *p)\n{\n\t/*\n\t * task_non_contending() can start the \"inactive timer\" (if the 0-lag\n\t * time is in the future). If the task switches back to dl before\n\t * the \"inactive timer\" fires, it can continue to consume its current\n\t * runtime using its current deadline. If it stays outside of\n\t * SCHED_DEADLINE until the 0-lag time passes, inactive_task_timer()\n\t * will reset the task parameters.\n\t */\n\tif (task_on_rq_queued(p) && p->dl.dl_runtime)\n\t\ttask_non_contending(p);\n\n\tif (!task_on_rq_queued(p)) {\n\t\t/*\n\t\t * Inactive timer is armed. However, p is leaving DEADLINE and\n\t\t * might migrate away from this rq while continuing to run on\n\t\t * some other class. We need to remove its contribution from\n\t\t * this rq running_bw now, or sub_rq_bw (below) will complain.\n\t\t */\n\t\tif (p->dl.dl_non_contending)\n\t\t\tsub_running_bw(&p->dl, &rq->dl);\n\t\tsub_rq_bw(&p->dl, &rq->dl);\n\t}\n\n\t/*\n\t * We cannot use inactive_task_timer() to invoke sub_running_bw()\n\t * at the 0-lag time, because the task could have been migrated\n\t * while SCHED_OTHER in the meanwhile.\n\t */\n\tif (p->dl.dl_non_contending)\n\t\tp->dl.dl_non_contending = 0;\n\n\t/*\n\t * Since this might be the only -deadline task on the rq,\n\t * this is the right place to try to pull some other one\n\t * from an overloaded CPU, if any.\n\t */\n\tif (!task_on_rq_queued(p) || rq->dl.dl_nr_running)\n\t\treturn;\n\n\tdeadline_queue_pull_task(rq);\n}",
        "static void bfq_update_depths(struct bfq_data *bfqd, struct sbitmap_queue *bt)\n{\n\tunsigned int depth = 1U << bt->sb.shift;\n\n\tbfqd->full_depth_shift = bt->sb.shift;": "static void bfq_update_depths(struct bfq_data *bfqd, struct sbitmap_queue *bt)\n{\n\tunsigned int depth = 1U << bt->sb.shift;\n\n\tbfqd->full_depth_shift = bt->sb.shift;\n\t/*\n\t * In-word depths if no bfq_queue is being weight-raised:\n\t * leaving 25% of tags only for sync reads.\n\t *\n\t * In next formulas, right-shift the value\n\t * (1U<<bt->sb.shift), instead of computing directly\n\t * (1U<<(bt->sb.shift - something)), to be robust against\n\t * any possible value of bt->sb.shift, without having to\n\t * limit 'something'.\n\t */\n\t/* no more than 50% of tags for async I/O */\n\tbfqd->word_depths[0][0] = max(depth >> 1, 1U);\n\t/*\n\t * no more than 75% of tags for sync writes (25% extra tags\n\t * w.r.t. async I/O, to prevent async I/O from starving sync\n\t * writes)\n\t */\n\tbfqd->word_depths[0][1] = max((depth * 3) >> 2, 1U);\n\n\t/*\n\t * In-word depths in case some bfq_queue is being weight-\n\t * raised: leaving ~63% of tags for sync reads. This is the\n\t * highest percentage for which, in our tests, application\n\t * start-up times didn't suffer from any regression due to tag\n\t * shortage.\n\t */\n\t/* no more than ~18% of tags for async I/O */\n\tbfqd->word_depths[1][0] = max((depth * 3) >> 4, 1U);\n\t/* no more than ~37% of tags for sync writes (~20% extra tags) */\n\tbfqd->word_depths[1][1] = max((depth * 6) >> 4, 1U);\n}",
        "static int super_init_validation(struct raid_set *rs, struct md_rdev *rdev)\n{\n\tint role;\n\tunsigned int d;\n\tstruct mddev *mddev = &rs->md;": "static int super_init_validation(struct raid_set *rs, struct md_rdev *rdev)\n{\n\tint role;\n\tunsigned int d;\n\tstruct mddev *mddev = &rs->md;\n\tuint64_t events_sb;\n\tuint64_t failed_devices[DISKS_ARRAY_ELEMS];\n\tstruct dm_raid_superblock *sb;\n\tuint32_t new_devs = 0, rebuild_and_new = 0, rebuilds = 0;\n\tstruct md_rdev *r;\n\tstruct dm_raid_superblock *sb2;\n\n\tsb = page_address(rdev->sb_page);\n\tevents_sb = le64_to_cpu(sb->events);\n\n\t/*\n\t * Initialise to 1 if this is a new superblock.\n\t */\n\tmddev->events = events_sb ? : 1;\n\n\tmddev->reshape_position = MaxSector;\n\n\tmddev->raid_disks = le32_to_cpu(sb->num_devices);\n\tmddev->level = le32_to_cpu(sb->level);\n\tmddev->layout = le32_to_cpu(sb->layout);\n\tmddev->chunk_sectors = le32_to_cpu(sb->stripe_sectors);\n\n\t/*\n\t * Reshaping is supported, e.g. reshape_position is valid\n\t * in superblock and superblock content is authoritative.\n\t */\n\tif (le32_to_cpu(sb->compat_features) & FEATURE_FLAG_SUPPORTS_V190) {\n\t\t/* Superblock is authoritative wrt given raid set layout! */\n\t\tmddev->new_level = le32_to_cpu(sb->new_level);\n\t\tmddev->new_layout = le32_to_cpu(sb->new_layout);\n\t\tmddev->new_chunk_sectors = le32_to_cpu(sb->new_stripe_sectors);\n\t\tmddev->delta_disks = le32_to_cpu(sb->delta_disks);\n\t\tmddev->array_sectors = le64_to_cpu(sb->array_sectors);\n\n\t\t/* raid was reshaping and got interrupted */\n\t\tif (le32_to_cpu(sb->flags) & SB_FLAG_RESHAPE_ACTIVE) {\n\t\t\tif (test_bit(__CTR_FLAG_DELTA_DISKS, &rs->ctr_flags)) {\n\t\t\t\tDMERR(\"Reshape requested but raid set is still reshaping\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tif (mddev->delta_disks < 0 ||\n\t\t\t    (!mddev->delta_disks && (le32_to_cpu(sb->flags) & SB_FLAG_RESHAPE_BACKWARDS)))\n\t\t\t\tmddev->reshape_backwards = 1;\n\t\t\telse\n\t\t\t\tmddev->reshape_backwards = 0;\n\n\t\t\tmddev->reshape_position = le64_to_cpu(sb->reshape_position);\n\t\t\trs->raid_type = get_raid_type_by_ll(mddev->level, mddev->layout);\n\t\t}\n\n\t} else {\n\t\t/*\n\t\t * No takeover/reshaping, because we don't have the extended v1.9.0 metadata\n\t\t */\n\t\tstruct raid_type *rt_cur = get_raid_type_by_ll(mddev->level, mddev->layout);\n\t\tstruct raid_type *rt_new = get_raid_type_by_ll(mddev->new_level, mddev->new_layout);\n\n\t\tif (rs_takeover_requested(rs)) {\n\t\t\tif (rt_cur && rt_new)\n\t\t\t\tDMERR(\"Takeover raid sets from %s to %s not yet supported by metadata. (raid level change)\",\n\t\t\t\t      rt_cur->name, rt_new->name);\n\t\t\telse\n\t\t\t\tDMERR(\"Takeover raid sets not yet supported by metadata. (raid level change)\");\n\t\t\treturn -EINVAL;\n\t\t} else if (rs_reshape_requested(rs)) {\n\t\t\tDMERR(\"Reshaping raid sets not yet supported by metadata. (raid layout change keeping level)\");\n\t\t\tif (mddev->layout != mddev->new_layout) {\n\t\t\t\tif (rt_cur && rt_new)\n\t\t\t\t\tDMERR(\"\t current layout %s vs new layout %s\",\n\t\t\t\t\t      rt_cur->name, rt_new->name);\n\t\t\t\telse\n\t\t\t\t\tDMERR(\"\t current layout 0x%X vs new layout 0x%X\",\n\t\t\t\t\t      le32_to_cpu(sb->layout), mddev->new_layout);\n\t\t\t}\n\t\t\tif (mddev->chunk_sectors != mddev->new_chunk_sectors)\n\t\t\t\tDMERR(\"\t current stripe sectors %u vs new stripe sectors %u\",\n\t\t\t\t      mddev->chunk_sectors, mddev->new_chunk_sectors);\n\t\t\tif (rs->delta_disks)\n\t\t\t\tDMERR(\"\t current %u disks vs new %u disks\",\n\t\t\t\t      mddev->raid_disks, mddev->raid_disks + rs->delta_disks);\n\t\t\tif (rs_is_raid10(rs)) {\n\t\t\t\tDMERR(\"\t Old layout: %s w/ %u copies\",\n\t\t\t\t      raid10_md_layout_to_format(mddev->layout),\n\t\t\t\t      raid10_md_layout_to_copies(mddev->layout));\n\t\t\t\tDMERR(\"\t New layout: %s w/ %u copies\",\n\t\t\t\t      raid10_md_layout_to_format(mddev->new_layout),\n\t\t\t\t      raid10_md_layout_to_copies(mddev->new_layout));\n\t\t\t}\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tDMINFO(\"Discovered old metadata format; upgrading to extended metadata format\");\n\t}\n\n\tif (!test_bit(__CTR_FLAG_NOSYNC, &rs->ctr_flags))\n\t\tmddev->recovery_cp = le64_to_cpu(sb->array_resync_offset);\n\n\t/*\n\t * During load, we set FirstUse if a new superblock was written.\n\t * There are two reasons we might not have a superblock:\n\t * 1) The raid set is brand new - in which case, all of the\n\t *    devices must have their In_sync bit set.\tAlso,\n\t *    recovery_cp must be 0, unless forced.\n\t * 2) This is a new device being added to an old raid set\n\t *    and the new device needs to be rebuilt - in which\n\t *    case the In_sync bit will /not/ be set and\n\t *    recovery_cp must be MaxSector.\n\t * 3) This is/are a new device(s) being added to an old\n\t *    raid set during takeover to a higher raid level\n\t *    to provide capacity for redundancy or during reshape\n\t *    to add capacity to grow the raid set.\n\t */\n\td = 0;\n\trdev_for_each(r, mddev) {\n\t\tif (test_bit(Journal, &rdev->flags))\n\t\t\tcontinue;\n\n\t\tif (test_bit(FirstUse, &r->flags))\n\t\t\tnew_devs++;\n\n\t\tif (!test_bit(In_sync, &r->flags)) {\n\t\t\tDMINFO(\"Device %d specified for rebuild; clearing superblock\",\n\t\t\t\tr->raid_disk);\n\t\t\trebuilds++;\n\n\t\t\tif (test_bit(FirstUse, &r->flags))\n\t\t\t\trebuild_and_new++;\n\t\t}\n\n\t\td++;\n\t}\n\n\tif (new_devs == rs->raid_disks || !rebuilds) {\n\t\t/* Replace a broken device */\n\t\tif (new_devs == rs->raid_disks) {\n\t\t\tDMINFO(\"Superblocks created for new raid set\");\n\t\t\tset_bit(MD_ARRAY_FIRST_USE, &mddev->flags);\n\t\t} else if (new_devs != rebuilds &&\n\t\t\t   new_devs != rs->delta_disks) {\n\t\t\tDMERR(\"New device injected into existing raid set without \"\n\t\t\t      \"'delta_disks' or 'rebuild' parameter specified\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t} else if (new_devs && new_devs != rebuilds) {\n\t\tDMERR(\"%u 'rebuild' devices cannot be injected into\"\n\t\t      \" a raid set with %u other first-time devices\",\n\t\t      rebuilds, new_devs);\n\t\treturn -EINVAL;\n\t} else if (rebuilds) {\n\t\tif (rebuild_and_new && rebuilds != rebuild_and_new) {\n\t\t\tDMERR(\"new device%s provided without 'rebuild'\",\n\t\t\t      new_devs > 1 ? \"s\" : \"\");\n\t\t\treturn -EINVAL;\n\t\t} else if (!test_bit(__CTR_FLAG_REBUILD, &rs->ctr_flags) && rs_is_recovering(rs)) {\n\t\t\tDMERR(\"'rebuild' specified while raid set is not in-sync (recovery_cp=%llu)\",\n\t\t\t      (unsigned long long) mddev->recovery_cp);\n\t\t\treturn -EINVAL;\n\t\t} else if (rs_is_reshaping(rs)) {\n\t\t\tDMERR(\"'rebuild' specified while raid set is being reshaped (reshape_position=%llu)\",\n\t\t\t      (unsigned long long) mddev->reshape_position);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\t/*\n\t * Now we set the Faulty bit for those devices that are\n\t * recorded in the superblock as failed.\n\t */\n\tsb_retrieve_failed_devices(sb, failed_devices);\n\trdev_for_each(r, mddev) {\n\t\tif (test_bit(Journal, &rdev->flags) ||\n\t\t    !r->sb_page)\n\t\t\tcontinue;\n\t\tsb2 = page_address(r->sb_page);\n\t\tsb2->failed_devices = 0;\n\t\tmemset(sb2->extended_failed_devices, 0, sizeof(sb2->extended_failed_devices));\n\n\t\t/*\n\t\t * Check for any device re-ordering.\n\t\t */\n\t\tif (!test_bit(FirstUse, &r->flags) && (r->raid_disk >= 0)) {\n\t\t\trole = le32_to_cpu(sb2->array_position);\n\t\t\tif (role < 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (role != r->raid_disk) {\n\t\t\t\tif (rs_is_raid10(rs) && __is_raid10_near(mddev->layout)) {\n\t\t\t\t\tif (mddev->raid_disks % __raid10_near_copies(mddev->layout) ||\n\t\t\t\t\t    rs->raid_disks % rs->raid10_copies) {\n\t\t\t\t\t\trs->ti->error =\n\t\t\t\t\t\t\t\"Cannot change raid10 near set to odd # of devices!\";\n\t\t\t\t\t\treturn -EINVAL;\n\t\t\t\t\t}\n\n\t\t\t\t\tsb2->array_position = cpu_to_le32(r->raid_disk);\n\n\t\t\t\t} else if (!(rs_is_raid10(rs) && rt_is_raid0(rs->raid_type)) &&\n\t\t\t\t\t   !(rs_is_raid0(rs) && rt_is_raid10(rs->raid_type)) &&\n\t\t\t\t\t   !rt_is_raid1(rs->raid_type)) {\n\t\t\t\t\trs->ti->error = \"Cannot change device positions in raid set\";\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\n\t\t\t\tDMINFO(\"raid device #%d now at position #%d\", role, r->raid_disk);\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Partial recovery is performed on\n\t\t\t * returning failed devices.\n\t\t\t */\n\t\t\tif (test_bit(role, (void *) failed_devices))\n\t\t\t\tset_bit(Faulty, &r->flags);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static int __jbd2_journal_erase(journal_t *journal, unsigned int flags)\n{\n\tint err = 0;\n\tunsigned long block, log_offset; /* logical */\n\tunsigned long long phys_block, block_start, block_stop; /* physical */": "static int __jbd2_journal_erase(journal_t *journal, unsigned int flags)\n{\n\tint err = 0;\n\tunsigned long block, log_offset; /* logical */\n\tunsigned long long phys_block, block_start, block_stop; /* physical */\n\tloff_t byte_start, byte_stop, byte_count;\n\n\t/* flags must be set to either discard or zeroout */\n\tif ((flags & ~JBD2_JOURNAL_FLUSH_VALID) || !flags ||\n\t\t\t((flags & JBD2_JOURNAL_FLUSH_DISCARD) &&\n\t\t\t(flags & JBD2_JOURNAL_FLUSH_ZEROOUT)))\n\t\treturn -EINVAL;\n\n\tif ((flags & JBD2_JOURNAL_FLUSH_DISCARD) &&\n\t    !bdev_max_discard_sectors(journal->j_dev))\n\t\treturn -EOPNOTSUPP;\n\n\t/*\n\t * lookup block mapping and issue discard/zeroout for each\n\t * contiguous region\n\t */\n\tlog_offset = be32_to_cpu(journal->j_superblock->s_first);\n\tblock_start =  ~0ULL;\n\tfor (block = log_offset; block < journal->j_total_len; block++) {\n\t\terr = jbd2_journal_bmap(journal, block, &phys_block);\n\t\tif (err) {\n\t\t\tpr_err(\"JBD2: bad block at offset %lu\", block);\n\t\t\treturn err;\n\t\t}\n\n\t\tif (block_start == ~0ULL) {\n\t\t\tblock_start = phys_block;\n\t\t\tblock_stop = block_start - 1;\n\t\t}\n\n\t\t/*\n\t\t * last block not contiguous with current block,\n\t\t * process last contiguous region and return to this block on\n\t\t * next loop\n\t\t */\n\t\tif (phys_block != block_stop + 1) {\n\t\t\tblock--;\n\t\t} else {\n\t\t\tblock_stop++;\n\t\t\t/*\n\t\t\t * if this isn't the last block of journal,\n\t\t\t * no need to process now because next block may also\n\t\t\t * be part of this contiguous region\n\t\t\t */\n\t\t\tif (block != journal->j_total_len - 1)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\t/*\n\t\t * end of contiguous region or this is last block of journal,\n\t\t * take care of the region\n\t\t */\n\t\tbyte_start = block_start * journal->j_blocksize;\n\t\tbyte_stop = block_stop * journal->j_blocksize;\n\t\tbyte_count = (block_stop - block_start + 1) *\n\t\t\t\tjournal->j_blocksize;\n\n\t\ttruncate_inode_pages_range(journal->j_dev->bd_inode->i_mapping,\n\t\t\t\tbyte_start, byte_stop);\n\n\t\tif (flags & JBD2_JOURNAL_FLUSH_DISCARD) {\n\t\t\terr = blkdev_issue_discard(journal->j_dev,\n\t\t\t\t\tbyte_start >> SECTOR_SHIFT,\n\t\t\t\t\tbyte_count >> SECTOR_SHIFT,\n\t\t\t\t\tGFP_NOFS);\n\t\t} else if (flags & JBD2_JOURNAL_FLUSH_ZEROOUT) {\n\t\t\terr = blkdev_issue_zeroout(journal->j_dev,\n\t\t\t\t\tbyte_start >> SECTOR_SHIFT,\n\t\t\t\t\tbyte_count >> SECTOR_SHIFT,\n\t\t\t\t\tGFP_NOFS, 0);\n\t\t}\n\n\t\tif (unlikely(err != 0)) {\n\t\t\tpr_err(\"JBD2: (error %d) unable to wipe journal at physical blocks %llu - %llu\",\n\t\t\t\t\terr, block_start, block_stop);\n\t\t\treturn err;\n\t\t}\n\n\t\t/* reset start and stop after processing a region */\n\t\tblock_start = ~0ULL;\n\t}\n\n\treturn blkdev_issue_flush(journal->j_dev);\n}",
        "static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)\n{\n\tstruct cs8409_spec *spec = codec->spec;\n\tstruct sub_codec *cs42l42;\n\tstruct hda_jack_tbl *jk;": "static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)\n{\n\tstruct cs8409_spec *spec = codec->spec;\n\tstruct sub_codec *cs42l42;\n\tstruct hda_jack_tbl *jk;\n\n\tcs42l42 = spec->scodecs[CS8409_CODEC0];\n\tif (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&\n\t    cs42l42_jack_unsol_event(cs42l42)) {\n\t\tjk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);\n\t\tif (jk)\n\t\t\tsnd_hda_jack_unsol_event(codec,\n\t\t\t\t\t\t (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &\n\t\t\t\t\t\t  AC_UNSOL_RES_TAG);\n\n\t\tjk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);\n\t\tif (jk)\n\t\t\tsnd_hda_jack_unsol_event(codec,\n\t\t\t\t\t\t (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &\n\t\t\t\t\t\t  AC_UNSOL_RES_TAG);\n\t}\n\n\tcs42l42 = spec->scodecs[CS8409_CODEC1];\n\tif (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&\n\t    cs42l42_jack_unsol_event(cs42l42)) {\n\t\tjk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);\n\t\tif (jk)\n\t\t\tsnd_hda_jack_unsol_event(codec,\n\t\t\t\t\t\t (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &\n\t\t\t\t\t\t  AC_UNSOL_RES_TAG);\n\t}\n}",
        "static void dev_map_free(struct bpf_map *map)\n{\n\tstruct bpf_dtab *dtab = container_of(map, struct bpf_dtab, map);\n\tint i;\n": "static void dev_map_free(struct bpf_map *map)\n{\n\tstruct bpf_dtab *dtab = container_of(map, struct bpf_dtab, map);\n\tint i;\n\n\t/* At this point bpf_prog->aux->refcnt == 0 and this map->refcnt == 0,\n\t * so the programs (can be more than one that used this map) were\n\t * disconnected from events. The following synchronize_rcu() guarantees\n\t * both rcu read critical sections complete and waits for\n\t * preempt-disable regions (NAPI being the relevant context here) so we\n\t * are certain there will be no further reads against the netdev_map and\n\t * all flush operations are complete. Flush operations can only be done\n\t * from NAPI context for this reason.\n\t */\n\n\tspin_lock(&dev_map_lock);\n\tlist_del_rcu(&dtab->list);\n\tspin_unlock(&dev_map_lock);\n\n\tbpf_clear_redirect_map(map);\n\tsynchronize_rcu();\n\n\t/* Make sure prior __dev_map_entry_free() have completed. */\n\trcu_barrier();\n\n\tif (dtab->map.map_type == BPF_MAP_TYPE_DEVMAP_HASH) {\n\t\tfor (i = 0; i < dtab->n_buckets; i++) {\n\t\t\tstruct bpf_dtab_netdev *dev;\n\t\t\tstruct hlist_head *head;\n\t\t\tstruct hlist_node *next;\n\n\t\t\thead = dev_map_index_hash(dtab, i);\n\n\t\t\thlist_for_each_entry_safe(dev, next, head, index_hlist) {\n\t\t\t\thlist_del_rcu(&dev->index_hlist);\n\t\t\t\tif (dev->xdp_prog)\n\t\t\t\t\tbpf_prog_put(dev->xdp_prog);\n\t\t\t\tdev_put(dev->dev);\n\t\t\t\tkfree(dev);\n\t\t\t}\n\t\t}\n\n\t\tbpf_map_area_free(dtab->dev_index_head);\n\t} else {\n\t\tfor (i = 0; i < dtab->map.max_entries; i++) {\n\t\t\tstruct bpf_dtab_netdev *dev;\n\n\t\t\tdev = rcu_dereference_raw(dtab->netdev_map[i]);\n\t\t\tif (!dev)\n\t\t\t\tcontinue;\n\n\t\t\tif (dev->xdp_prog)\n\t\t\t\tbpf_prog_put(dev->xdp_prog);\n\t\t\tdev_put(dev->dev);\n\t\t\tkfree(dev);\n\t\t}\n\n\t\tbpf_map_area_free(dtab->netdev_map);\n\t}\n\n\tkfree(dtab);\n}",
        "static void test_tcp(int family, const char *addr, __u16 port)\n{\n\tint listen_fd = -1, accept_fd = -1, client_fd = -1;\n\tchar buf[] = \"testing testing\";\n\tint n;": "static void test_tcp(int family, const char *addr, __u16 port)\n{\n\tint listen_fd = -1, accept_fd = -1, client_fd = -1;\n\tchar buf[] = \"testing testing\";\n\tint n;\n\tstruct nstoken *nstoken;\n\n\tnstoken = open_netns(NS_DST);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns dst\"))\n\t\treturn;\n\n\tlisten_fd = start_server(family, SOCK_STREAM, addr, port, 0);\n\tif (!ASSERT_GE(listen_fd, 0, \"listen\"))\n\t\tgoto done;\n\n\tclose_netns(nstoken);\n\tnstoken = open_netns(NS_SRC);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns src\"))\n\t\tgoto done;\n\n\tclient_fd = connect_to_fd(listen_fd, TIMEOUT_MILLIS);\n\tif (!ASSERT_GE(client_fd, 0, \"connect_to_fd\"))\n\t\tgoto done;\n\n\taccept_fd = accept(listen_fd, NULL, NULL);\n\tif (!ASSERT_GE(accept_fd, 0, \"accept\"))\n\t\tgoto done;\n\n\tif (!ASSERT_OK(settimeo(accept_fd, TIMEOUT_MILLIS), \"settimeo\"))\n\t\tgoto done;\n\n\tn = write(client_fd, buf, sizeof(buf));\n\tif (!ASSERT_EQ(n, sizeof(buf), \"send to server\"))\n\t\tgoto done;\n\n\tn = read(accept_fd, buf, sizeof(buf));\n\tASSERT_EQ(n, sizeof(buf), \"recv from server\");\n\ndone:\n\tif (nstoken)\n\t\tclose_netns(nstoken);\n\tif (listen_fd >= 0)\n\t\tclose(listen_fd);\n\tif (accept_fd >= 0)\n\t\tclose(accept_fd);\n\tif (client_fd >= 0)\n\t\tclose(client_fd);\n}",
        "static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)\n{\n\t/*\n\t * It would be really nice if we had a system register that lets us get\n\t * the FIQ source state without having to peek down into sources...": "static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)\n{\n\t/*\n\t * It would be really nice if we had a system register that lets us get\n\t * the FIQ source state without having to peek down into sources...\n\t * but such a register does not seem to exist.\n\t *\n\t * So, we have these potential sources to test for:\n\t *  - Fast IPIs (not yet used)\n\t *  - The 4 timers (CNTP, CNTV for each of HV and guest)\n\t *  - Per-core PMCs (not yet supported)\n\t *  - Per-cluster uncore PMCs (not yet supported)\n\t *\n\t * Since not dealing with any of these results in a FIQ storm,\n\t * we check for everything here, even things we don't support yet.\n\t */\n\n\tif (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING) {\n\t\tif (static_branch_likely(&use_fast_ipi)) {\n\t\t\taic_handle_ipi(regs);\n\t\t} else {\n\t\t\tpr_err_ratelimited(\"Fast IPI fired. Acking.\\n\");\n\t\t\twrite_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1);\n\t\t}\n\t}\n\n\tif (TIMER_FIRING(read_sysreg(cntp_ctl_el0)))\n\t\tgeneric_handle_domain_irq(aic_irqc->hw_domain,\n\t\t\t\t\t  AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS));\n\n\tif (TIMER_FIRING(read_sysreg(cntv_ctl_el0)))\n\t\tgeneric_handle_domain_irq(aic_irqc->hw_domain,\n\t\t\t\t\t  AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT));\n\n\tif (is_kernel_in_hyp_mode()) {\n\t\tuint64_t enabled = read_sysreg_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2);\n\n\t\tif ((enabled & VM_TMR_FIQ_ENABLE_P) &&\n\t\t    TIMER_FIRING(read_sysreg_s(SYS_CNTP_CTL_EL02)))\n\t\t\tgeneric_handle_domain_irq(aic_irqc->hw_domain,\n\t\t\t\t\t\t  AIC_FIQ_HWIRQ(AIC_TMR_EL02_PHYS));\n\n\t\tif ((enabled & VM_TMR_FIQ_ENABLE_V) &&\n\t\t    TIMER_FIRING(read_sysreg_s(SYS_CNTV_CTL_EL02)))\n\t\t\tgeneric_handle_domain_irq(aic_irqc->hw_domain,\n\t\t\t\t\t\t  AIC_FIQ_HWIRQ(AIC_TMR_EL02_VIRT));\n\t}\n\n\tif (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) {\n\t\tint irq;\n\t\tif (cpumask_test_cpu(smp_processor_id(),\n\t\t\t\t     &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff))\n\t\t\tirq = AIC_CPU_PMU_P;\n\t\telse\n\t\t\tirq = AIC_CPU_PMU_E;\n\t\tgeneric_handle_domain_irq(aic_irqc->hw_domain,\n\t\t\t\t\t  AIC_FIQ_HWIRQ(irq));\n\t}\n\n\tif (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ &&\n\t\t\t(read_sysreg_s(SYS_IMP_APL_UPMSR_EL1) & UPMSR_IACT)) {\n\t\t/* Same story with uncore PMCs */\n\t\tpr_err_ratelimited(\"Uncore PMC FIQ fired. Masking.\\n\");\n\t\tsysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE,\n\t\t\t\t   FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF));\n\t}\n}",
        "static int vdec_1_stop(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\tstruct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;\n": "static int vdec_1_stop(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\tstruct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;\n\n\tamvdec_write_dos(core, MPSR, 0);\n\tamvdec_write_dos(core, CPSR, 0);\n\tamvdec_write_dos(core, ASSIST_MBOX1_MASK, 0);\n\n\tamvdec_write_dos(core, DOS_SW_RESET0, BIT(12) | BIT(11));\n\tamvdec_write_dos(core, DOS_SW_RESET0, 0);\n\tamvdec_read_dos(core, DOS_SW_RESET0);\n\n\t/* enable vdec1 isolation */\n\tif (core->platform->revision == VDEC_REVISION_SM1)\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,\n\t\t\t\t   GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);\n\telse\n\t\tregmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0xc0);\n\t/* power off vdec1 memories */\n\tamvdec_write_dos(core, DOS_MEM_PD_VDEC, 0xffffffff);\n\t/* power off vdec1 */\n\tif (core->platform->revision == VDEC_REVISION_SM1)\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,\n\t\t\t\t   GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);\n\telse\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,\n\t\t\t\t   GEN_PWR_VDEC_1, GEN_PWR_VDEC_1);\n\n\tclk_disable_unprepare(core->vdec_1_clk);\n\n\tif (sess->priv)\n\t\tcodec_ops->stop(sess);\n\n\treturn 0;\n}",
        "static int alloc_try_nid_top_down_reserved_with_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;": "static int alloc_try_nid_top_down_reserved_with_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\tstruct region r1, r2;\n\n\tphys_addr_t r3_size = SZ_64;\n\tphys_addr_t gap_size = SMP_CACHE_BYTES;\n\tphys_addr_t total_size;\n\tphys_addr_t max_addr;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2;\n\tr1.size = SMP_CACHE_BYTES;\n\n\tr2.size = SZ_128;\n\tr2.base = r1.base - (r3_size + gap_size + r2.size);\n\n\ttotal_size = r1.size + r2.size + r3_size;\n\tmin_addr = r2.base + r2.size;\n\tmax_addr = r1.base;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn1->size == r1.size + r3_size);\n\tassert(rgn1->base == max_addr - r3_size);\n\n\tassert(rgn2->size == r2.size);\n\tassert(rgn2->base == r2.base);\n\n\tassert(memblock.reserved.cnt == 2);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static int es58x_get_product_info(struct es58x_device *es58x_dev)\n{\n\tstruct usb_device *udev = es58x_dev->udev;\n\tconst int es58x_prod_info_idx = 6;\n\t/* Empirical tests show a prod_info length of maximum 83,": "static int es58x_get_product_info(struct es58x_device *es58x_dev)\n{\n\tstruct usb_device *udev = es58x_dev->udev;\n\tconst int es58x_prod_info_idx = 6;\n\t/* Empirical tests show a prod_info length of maximum 83,\n\t * below should be more than enough.\n\t */\n\tconst size_t prod_info_len = 127;\n\tchar *prod_info;\n\tint ret;\n\n\tprod_info = kmalloc(prod_info_len, GFP_KERNEL);\n\tif (!prod_info)\n\t\treturn -ENOMEM;\n\n\tret = usb_string(udev, es58x_prod_info_idx, prod_info, prod_info_len);\n\tif (ret < 0) {\n\t\tdev_err(es58x_dev->dev,\n\t\t\t\"%s: Could not read the product info: %pe\\n\",\n\t\t\t__func__, ERR_PTR(ret));\n\t\tgoto out_free;\n\t}\n\tif (ret >= prod_info_len - 1) {\n\t\tdev_warn(es58x_dev->dev,\n\t\t\t \"%s: Buffer is too small, result might be truncated\\n\",\n\t\t\t __func__);\n\t}\n\tdev_info(es58x_dev->dev, \"Product info: %s\\n\", prod_info);\n\n out_free:\n\tkfree(prod_info);\n\treturn ret < 0 ? ret : 0;\n}",
        "static int cit_start_model3(struct gspca_dev *gspca_dev)\n{\n\tconst unsigned short compression = 0; /* 0=none, 7=best frame rate */\n\tint i, clock_div = 0;\n": "static int cit_start_model3(struct gspca_dev *gspca_dev)\n{\n\tconst unsigned short compression = 0; /* 0=none, 7=best frame rate */\n\tint i, clock_div = 0;\n\n\t/* HDG not in ibmcam driver, added to see if it helps with\n\t   auto-detecting between model3 and ibm netcamera pro */\n\tcit_read_reg(gspca_dev, 0x128, 1);\n\n\tcit_write_reg(gspca_dev, 0x0000, 0x0100);\n\tcit_read_reg(gspca_dev, 0x0116, 0);\n\tcit_write_reg(gspca_dev, 0x0060, 0x0116);\n\tcit_write_reg(gspca_dev, 0x0002, 0x0112);\n\tcit_write_reg(gspca_dev, 0x0000, 0x0123);\n\tcit_write_reg(gspca_dev, 0x0001, 0x0117);\n\tcit_write_reg(gspca_dev, 0x0040, 0x0108);\n\tcit_write_reg(gspca_dev, 0x0019, 0x012c);\n\tcit_write_reg(gspca_dev, 0x0060, 0x0116);\n\tcit_write_reg(gspca_dev, 0x0002, 0x0115);\n\tcit_write_reg(gspca_dev, 0x0003, 0x0115);\n\tcit_read_reg(gspca_dev, 0x0115, 0);\n\tcit_write_reg(gspca_dev, 0x000b, 0x0115);\n\n\t/* TESTME HDG not in ibmcam driver, added to see if it helps with\n\t   auto-detecting between model3 and ibm netcamera pro */\n\tif (0) {\n\t\tcit_write_reg(gspca_dev, 0x0078, 0x012d);\n\t\tcit_write_reg(gspca_dev, 0x0001, 0x012f);\n\t\tcit_write_reg(gspca_dev, 0xd141, 0x0124);\n\t\tcit_write_reg(gspca_dev, 0x0079, 0x012d);\n\t\tcit_write_reg(gspca_dev, 0x00ff, 0x0130);\n\t\tcit_write_reg(gspca_dev, 0xcd41, 0x0124);\n\t\tcit_write_reg(gspca_dev, 0xfffa, 0x0124);\n\t\tcit_read_reg(gspca_dev, 0x0126, 1);\n\t}\n\n\tcit_model3_Packet1(gspca_dev, 0x000a, 0x0040);\n\tcit_model3_Packet1(gspca_dev, 0x000b, 0x00f6);\n\tcit_model3_Packet1(gspca_dev, 0x000c, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x000d, 0x0020);\n\tcit_model3_Packet1(gspca_dev, 0x000e, 0x0033);\n\tcit_model3_Packet1(gspca_dev, 0x000f, 0x0007);\n\tcit_model3_Packet1(gspca_dev, 0x0010, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0011, 0x0070);\n\tcit_model3_Packet1(gspca_dev, 0x0012, 0x0030);\n\tcit_model3_Packet1(gspca_dev, 0x0013, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0014, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x0015, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x0016, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x0017, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x0018, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x001e, 0x00c3);\n\tcit_model3_Packet1(gspca_dev, 0x0020, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0028, 0x0010);\n\tcit_model3_Packet1(gspca_dev, 0x0029, 0x0054);\n\tcit_model3_Packet1(gspca_dev, 0x002a, 0x0013);\n\tcit_model3_Packet1(gspca_dev, 0x002b, 0x0007);\n\tcit_model3_Packet1(gspca_dev, 0x002d, 0x0028);\n\tcit_model3_Packet1(gspca_dev, 0x002e, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0031, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0032, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0033, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0034, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0035, 0x0038);\n\tcit_model3_Packet1(gspca_dev, 0x003a, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x003c, 0x001e);\n\tcit_model3_Packet1(gspca_dev, 0x003f, 0x000a);\n\tcit_model3_Packet1(gspca_dev, 0x0041, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0046, 0x003f);\n\tcit_model3_Packet1(gspca_dev, 0x0047, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0050, 0x0005);\n\tcit_model3_Packet1(gspca_dev, 0x0052, 0x001a);\n\tcit_model3_Packet1(gspca_dev, 0x0053, 0x0003);\n\tcit_model3_Packet1(gspca_dev, 0x005a, 0x006b);\n\tcit_model3_Packet1(gspca_dev, 0x005d, 0x001e);\n\tcit_model3_Packet1(gspca_dev, 0x005e, 0x0030);\n\tcit_model3_Packet1(gspca_dev, 0x005f, 0x0041);\n\tcit_model3_Packet1(gspca_dev, 0x0064, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x0065, 0x0015);\n\tcit_model3_Packet1(gspca_dev, 0x0068, 0x000f);\n\tcit_model3_Packet1(gspca_dev, 0x0079, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x007a, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x007c, 0x003f);\n\tcit_model3_Packet1(gspca_dev, 0x0082, 0x000f);\n\tcit_model3_Packet1(gspca_dev, 0x0085, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0099, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x009b, 0x0023);\n\tcit_model3_Packet1(gspca_dev, 0x009c, 0x0022);\n\tcit_model3_Packet1(gspca_dev, 0x009d, 0x0096);\n\tcit_model3_Packet1(gspca_dev, 0x009e, 0x0096);\n\tcit_model3_Packet1(gspca_dev, 0x009f, 0x000a);\n\n\tswitch (gspca_dev->pixfmt.width) {\n\tcase 160:\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0101); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x00a0, 0x0103); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x0078, 0x0105); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x010a); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0024, 0x010b); /* Differs everywhere */\n\t\tcit_write_reg(gspca_dev, 0x00a9, 0x0119);\n\t\tcit_write_reg(gspca_dev, 0x0016, 0x011b);\n\t\tcit_write_reg(gspca_dev, 0x0002, 0x011d); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x0003, 0x011e); /* Same on 160x120, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0129); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x00fc, 0x012b); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0018, 0x0102);\n\t\tcit_write_reg(gspca_dev, 0x0004, 0x0104);\n\t\tcit_write_reg(gspca_dev, 0x0004, 0x011a);\n\t\tcit_write_reg(gspca_dev, 0x0028, 0x011c);\n\t\tcit_write_reg(gspca_dev, 0x0022, 0x012a); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0118);\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0132);\n\t\tcit_model3_Packet1(gspca_dev, 0x0021, 0x0001); /* Same */\n\t\tcit_write_reg(gspca_dev, compression, 0x0109);\n\t\tclock_div = 3;\n\t\tbreak;\n\tcase 320:\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0101); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x00a0, 0x0103); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x0078, 0x0105); /* Same on 160x120, 320x240 */\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x010a); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0028, 0x010b); /* Differs everywhere */\n\t\tcit_write_reg(gspca_dev, 0x0002, 0x011d); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x011e);\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0129); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x00fc, 0x012b); /* Same */\n\t\t/* 4 commands from 160x120 skipped */\n\t\tcit_write_reg(gspca_dev, 0x0022, 0x012a); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0021, 0x0001); /* Same */\n\t\tcit_write_reg(gspca_dev, compression, 0x0109);\n\t\tcit_write_reg(gspca_dev, 0x00d9, 0x0119);\n\t\tcit_write_reg(gspca_dev, 0x0006, 0x011b);\n\t\tcit_write_reg(gspca_dev, 0x0021, 0x0102); /* Same on 320x240, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0010, 0x0104);\n\t\tcit_write_reg(gspca_dev, 0x0004, 0x011a);\n\t\tcit_write_reg(gspca_dev, 0x003f, 0x011c);\n\t\tcit_write_reg(gspca_dev, 0x001c, 0x0118);\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0132);\n\t\tclock_div = 5;\n\t\tbreak;\n\tcase 640:\n\t\tcit_write_reg(gspca_dev, 0x00f0, 0x0105);\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x010a); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0038, 0x010b); /* Differs everywhere */\n\t\tcit_write_reg(gspca_dev, 0x00d9, 0x0119); /* Same on 320x240, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0006, 0x011b); /* Same on 320x240, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0004, 0x011d); /* NC */\n\t\tcit_write_reg(gspca_dev, 0x0003, 0x011e); /* Same on 160x120, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0129); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x00fc, 0x012b); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x0021, 0x0102); /* Same on 320x240, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0016, 0x0104); /* NC */\n\t\tcit_write_reg(gspca_dev, 0x0004, 0x011a); /* Same on 320x240, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x003f, 0x011c); /* Same on 320x240, 640x480 */\n\t\tcit_write_reg(gspca_dev, 0x0022, 0x012a); /* Same */\n\t\tcit_write_reg(gspca_dev, 0x001c, 0x0118); /* Same on 320x240, 640x480 */\n\t\tcit_model3_Packet1(gspca_dev, 0x0021, 0x0001); /* Same */\n\t\tcit_write_reg(gspca_dev, compression, 0x0109);\n\t\tcit_write_reg(gspca_dev, 0x0040, 0x0101);\n\t\tcit_write_reg(gspca_dev, 0x0040, 0x0103);\n\t\tcit_write_reg(gspca_dev, 0x0000, 0x0132); /* Same on 320x240, 640x480 */\n\t\tclock_div = 7;\n\t\tbreak;\n\t}\n\n\tcit_model3_Packet1(gspca_dev, 0x007e, 0x000e);\t/* Hue */\n\tcit_model3_Packet1(gspca_dev, 0x0036, 0x0011);\t/* Brightness */\n\tcit_model3_Packet1(gspca_dev, 0x0060, 0x0002);\t/* Sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0061, 0x0004);\t/* Sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0062, 0x0005);\t/* Sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0063, 0x0014);\t/* Sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0096, 0x00a0);\t/* Red sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0097, 0x0096);\t/* Blue sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0067, 0x0001);\t/* Contrast */\n\tcit_model3_Packet1(gspca_dev, 0x005b, 0x000c);\t/* Contrast */\n\tcit_model3_Packet1(gspca_dev, 0x005c, 0x0016);\t/* Contrast */\n\tcit_model3_Packet1(gspca_dev, 0x0098, 0x000b);\n\tcit_model3_Packet1(gspca_dev, 0x002c, 0x0003);\t/* Was 1, broke 640x480 */\n\tcit_model3_Packet1(gspca_dev, 0x002f, 0x002a);\n\tcit_model3_Packet1(gspca_dev, 0x0030, 0x0029);\n\tcit_model3_Packet1(gspca_dev, 0x0037, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0038, 0x0059);\n\tcit_model3_Packet1(gspca_dev, 0x003d, 0x002e);\n\tcit_model3_Packet1(gspca_dev, 0x003e, 0x0028);\n\tcit_model3_Packet1(gspca_dev, 0x0078, 0x0005);\n\tcit_model3_Packet1(gspca_dev, 0x007b, 0x0011);\n\tcit_model3_Packet1(gspca_dev, 0x007d, 0x004b);\n\tcit_model3_Packet1(gspca_dev, 0x007f, 0x0022);\n\tcit_model3_Packet1(gspca_dev, 0x0080, 0x000c);\n\tcit_model3_Packet1(gspca_dev, 0x0081, 0x000b);\n\tcit_model3_Packet1(gspca_dev, 0x0083, 0x00fd);\n\tcit_model3_Packet1(gspca_dev, 0x0086, 0x000b);\n\tcit_model3_Packet1(gspca_dev, 0x0087, 0x000b);\n\tcit_model3_Packet1(gspca_dev, 0x007e, 0x000e);\n\tcit_model3_Packet1(gspca_dev, 0x0096, 0x00a0);\t/* Red sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0097, 0x0096);\t/* Blue sharpness */\n\tcit_model3_Packet1(gspca_dev, 0x0098, 0x000b);\n\n\t/* FIXME we should probably use cit_get_clock_div() here (in\n\t   combination with isoc negotiation using the programmable isoc size)\n\t   like with the IBM netcam pro). */\n\tcit_write_reg(gspca_dev, clock_div, 0x0111); /* Clock Divider */\n\n\tswitch (gspca_dev->pixfmt.width) {\n\tcase 160:\n\t\tcit_model3_Packet1(gspca_dev, 0x001f, 0x0000); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0039, 0x001f); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x003b, 0x003c); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0040, 0x000a);\n\t\tcit_model3_Packet1(gspca_dev, 0x0051, 0x000a);\n\t\tbreak;\n\tcase 320:\n\t\tcit_model3_Packet1(gspca_dev, 0x001f, 0x0000); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0039, 0x001f); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x003b, 0x003c); /* Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0040, 0x0008);\n\t\tcit_model3_Packet1(gspca_dev, 0x0051, 0x000b);\n\t\tbreak;\n\tcase 640:\n\t\tcit_model3_Packet1(gspca_dev, 0x001f, 0x0002);\t/* !Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0039, 0x003e);\t/* !Same */\n\t\tcit_model3_Packet1(gspca_dev, 0x0040, 0x0008);\n\t\tcit_model3_Packet1(gspca_dev, 0x0051, 0x000a);\n\t\tbreak;\n\t}\n\n/*\tif (sd->input_index) { */\n\tif (rca_input) {\n\t\tfor (i = 0; i < ARRAY_SIZE(rca_initdata); i++) {\n\t\t\tif (rca_initdata[i][0])\n\t\t\t\tcit_read_reg(gspca_dev, rca_initdata[i][2], 0);\n\t\t\telse\n\t\t\t\tcit_write_reg(gspca_dev, rca_initdata[i][1],\n\t\t\t\t\t      rca_initdata[i][2]);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static int run_options(struct sockmap_options *options, int cg_fd,  int test)\n{\n\tint i, key, next_key, err, tx_prog_fd = -1, zero = 0;\n\n\t/* If base test skip BPF setup */": "static int run_options(struct sockmap_options *options, int cg_fd,  int test)\n{\n\tint i, key, next_key, err, tx_prog_fd = -1, zero = 0;\n\n\t/* If base test skip BPF setup */\n\tif (test == BASE || test == BASE_SENDPAGE)\n\t\tgoto run;\n\n\t/* Attach programs to sockmap */\n\tif (!txmsg_omit_skb_parser) {\n\t\terr = bpf_prog_attach(prog_fd[0], map_fd[0],\n\t\t\t\t      BPF_SK_SKB_STREAM_PARSER, 0);\n\t\tif (err) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"ERROR: bpf_prog_attach (sockmap %i->%i): %d (%s)\\n\",\n\t\t\t\tprog_fd[0], map_fd[0], err, strerror(errno));\n\t\t\treturn err;\n\t\t}\n\t}\n\n\terr = bpf_prog_attach(prog_fd[1], map_fd[0],\n\t\t\t\tBPF_SK_SKB_STREAM_VERDICT, 0);\n\tif (err) {\n\t\tfprintf(stderr, \"ERROR: bpf_prog_attach (sockmap): %d (%s)\\n\",\n\t\t\terr, strerror(errno));\n\t\treturn err;\n\t}\n\n\t/* Attach programs to TLS sockmap */\n\tif (txmsg_ktls_skb) {\n\t\tif (!txmsg_omit_skb_parser) {\n\t\t\terr = bpf_prog_attach(prog_fd[0], map_fd[8],\n\t\t\t\t\t      BPF_SK_SKB_STREAM_PARSER, 0);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_prog_attach (TLS sockmap %i->%i): %d (%s)\\n\",\n\t\t\t\t\tprog_fd[0], map_fd[8], err, strerror(errno));\n\t\t\t\treturn err;\n\t\t\t}\n\t\t}\n\n\t\terr = bpf_prog_attach(prog_fd[2], map_fd[8],\n\t\t\t\t      BPF_SK_SKB_STREAM_VERDICT, 0);\n\t\tif (err) {\n\t\t\tfprintf(stderr, \"ERROR: bpf_prog_attach (TLS sockmap): %d (%s)\\n\",\n\t\t\t\terr, strerror(errno));\n\t\t\treturn err;\n\t\t}\n\t}\n\n\t/* Attach to cgroups */\n\terr = bpf_prog_attach(prog_fd[3], cg_fd, BPF_CGROUP_SOCK_OPS, 0);\n\tif (err) {\n\t\tfprintf(stderr, \"ERROR: bpf_prog_attach (groups): %d (%s)\\n\",\n\t\t\terr, strerror(errno));\n\t\treturn err;\n\t}\n\nrun:\n\terr = sockmap_init_sockets(options->verbose);\n\tif (err) {\n\t\tfprintf(stderr, \"ERROR: test socket failed: %d\\n\", err);\n\t\tgoto out;\n\t}\n\n\t/* Attach txmsg program to sockmap */\n\tif (txmsg_pass)\n\t\ttx_prog_fd = prog_fd[4];\n\telse if (txmsg_redir)\n\t\ttx_prog_fd = prog_fd[5];\n\telse if (txmsg_apply)\n\t\ttx_prog_fd = prog_fd[6];\n\telse if (txmsg_cork)\n\t\ttx_prog_fd = prog_fd[7];\n\telse if (txmsg_drop)\n\t\ttx_prog_fd = prog_fd[8];\n\telse\n\t\ttx_prog_fd = 0;\n\n\tif (tx_prog_fd) {\n\t\tint redir_fd, i = 0;\n\n\t\terr = bpf_prog_attach(tx_prog_fd,\n\t\t\t\t      map_fd[1], BPF_SK_MSG_VERDICT, 0);\n\t\tif (err) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"ERROR: bpf_prog_attach (txmsg): %d (%s)\\n\",\n\t\t\t\terr, strerror(errno));\n\t\t\tgoto out;\n\t\t}\n\n\t\terr = bpf_map_update_elem(map_fd[1], &i, &c1, BPF_ANY);\n\t\tif (err) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg):  %d (%s\\n\",\n\t\t\t\terr, strerror(errno));\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (txmsg_redir)\n\t\t\tredir_fd = c2;\n\t\telse\n\t\t\tredir_fd = c1;\n\n\t\terr = bpf_map_update_elem(map_fd[2], &i, &redir_fd, BPF_ANY);\n\t\tif (err) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg):  %d (%s\\n\",\n\t\t\t\terr, strerror(errno));\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (txmsg_apply) {\n\t\t\terr = bpf_map_update_elem(map_fd[3],\n\t\t\t\t\t\t  &i, &txmsg_apply, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (apply_bytes):  %d (%s\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_cork) {\n\t\t\terr = bpf_map_update_elem(map_fd[4],\n\t\t\t\t\t\t  &i, &txmsg_cork, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (cork_bytes):  %d (%s\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_start) {\n\t\t\terr = bpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_start, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg_start):  %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_end) {\n\t\t\ti = 1;\n\t\t\terr = bpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_end, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg_end):  %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_start_push) {\n\t\t\ti = 2;\n\t\t\terr = bpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_start_push, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg_start_push):  %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_end_push) {\n\t\t\ti = 3;\n\t\t\terr = bpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_end_push, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem %i@%i (txmsg_end_push):  %d (%s)\\n\",\n\t\t\t\t\ttxmsg_end_push, i, err, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_start_pop) {\n\t\t\ti = 4;\n\t\t\terr = bpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_start_pop, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem %i@%i (txmsg_start_pop):  %d (%s)\\n\",\n\t\t\t\t\ttxmsg_start_pop, i, err, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t} else {\n\t\t\ti = 4;\n\t\t\tbpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_start_pop, BPF_ANY);\n\t\t}\n\n\t\tif (txmsg_pop) {\n\t\t\ti = 5;\n\t\t\terr = bpf_map_update_elem(map_fd[5],\n\t\t\t\t\t\t  &i, &txmsg_pop, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem %i@%i (txmsg_pop):  %d (%s)\\n\",\n\t\t\t\t\ttxmsg_pop, i, err, strerror(errno));\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t} else {\n\t\t\ti = 5;\n\t\t\tbpf_map_update_elem(map_fd[5],\n\t\t\t\t\t    &i, &txmsg_pop, BPF_ANY);\n\n\t\t}\n\n\t\tif (txmsg_ingress) {\n\t\t\tint in = BPF_F_INGRESS;\n\n\t\t\ti = 0;\n\t\t\terr = bpf_map_update_elem(map_fd[6], &i, &in, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg_ingress): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\t\t\ti = 1;\n\t\t\terr = bpf_map_update_elem(map_fd[1], &i, &p1, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (p1 txmsg): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\t\t\terr = bpf_map_update_elem(map_fd[2], &i, &p1, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (p1 redir): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\n\t\t\ti = 2;\n\t\t\terr = bpf_map_update_elem(map_fd[2], &i, &p2, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (p2 txmsg): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_ktls_skb) {\n\t\t\tint ingress = BPF_F_INGRESS;\n\n\t\t\ti = 0;\n\t\t\terr = bpf_map_update_elem(map_fd[8], &i, &p2, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (c1 sockmap): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\n\t\t\tif (txmsg_ktls_skb_redir) {\n\t\t\t\ti = 1;\n\t\t\t\terr = bpf_map_update_elem(map_fd[7],\n\t\t\t\t\t\t\t  &i, &ingress, BPF_ANY);\n\t\t\t\tif (err) {\n\t\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg_ingress): %d (%s)\\n\",\n\t\t\t\t\t\terr, strerror(errno));\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (txmsg_ktls_skb_drop) {\n\t\t\t\ti = 1;\n\t\t\t\terr = bpf_map_update_elem(map_fd[7], &i, &i, BPF_ANY);\n\t\t\t}\n\t\t}\n\n\t\tif (txmsg_redir_skb) {\n\t\t\tint skb_fd = (test == SENDMSG || test == SENDPAGE) ?\n\t\t\t\t\tp2 : p1;\n\t\t\tint ingress = BPF_F_INGRESS;\n\n\t\t\ti = 0;\n\t\t\terr = bpf_map_update_elem(map_fd[7],\n\t\t\t\t\t\t  &i, &ingress, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (txmsg_ingress): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\n\t\t\ti = 3;\n\t\t\terr = bpf_map_update_elem(map_fd[0], &i, &skb_fd, BPF_ANY);\n\t\t\tif (err) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: bpf_map_update_elem (c1 sockmap): %d (%s)\\n\",\n\t\t\t\t\terr, strerror(errno));\n\t\t\t}\n\t\t}\n\t}\n\n\tif (skb_use_parser) {\n\t\ti = 2;\n\t\terr = bpf_map_update_elem(map_fd[7], &i, &skb_use_parser, BPF_ANY);\n\t}\n\n\tif (txmsg_drop)\n\t\toptions->drop_expected = true;\n\n\tif (test == PING_PONG)\n\t\terr = forever_ping_pong(options->rate, options);\n\telse if (test == SENDMSG) {\n\t\toptions->base = false;\n\t\toptions->sendpage = false;\n\t\terr = sendmsg_test(options);\n\t} else if (test == SENDPAGE) {\n\t\toptions->base = false;\n\t\toptions->sendpage = true;\n\t\terr = sendmsg_test(options);\n\t} else if (test == BASE) {\n\t\toptions->base = true;\n\t\toptions->sendpage = false;\n\t\terr = sendmsg_test(options);\n\t} else if (test == BASE_SENDPAGE) {\n\t\toptions->base = true;\n\t\toptions->sendpage = true;\n\t\terr = sendmsg_test(options);\n\t} else\n\t\tfprintf(stderr, \"unknown test\\n\");\nout:\n\t/* Detatch and zero all the maps */\n\tbpf_prog_detach2(prog_fd[3], cg_fd, BPF_CGROUP_SOCK_OPS);\n\tbpf_prog_detach2(prog_fd[0], map_fd[0], BPF_SK_SKB_STREAM_PARSER);\n\tbpf_prog_detach2(prog_fd[1], map_fd[0], BPF_SK_SKB_STREAM_VERDICT);\n\tbpf_prog_detach2(prog_fd[0], map_fd[8], BPF_SK_SKB_STREAM_PARSER);\n\tbpf_prog_detach2(prog_fd[2], map_fd[8], BPF_SK_SKB_STREAM_VERDICT);\n\n\tif (tx_prog_fd >= 0)\n\t\tbpf_prog_detach2(tx_prog_fd, map_fd[1], BPF_SK_MSG_VERDICT);\n\n\tfor (i = 0; i < 8; i++) {\n\t\tkey = next_key = 0;\n\t\tbpf_map_update_elem(map_fd[i], &key, &zero, BPF_ANY);\n\t\twhile (bpf_map_get_next_key(map_fd[i], &key, &next_key) == 0) {\n\t\t\tbpf_map_update_elem(map_fd[i], &key, &zero, BPF_ANY);\n\t\t\tkey = next_key;\n\t\t}\n\t}\n\n\tclose(s1);\n\tclose(s2);\n\tclose(p1);\n\tclose(p2);\n\tclose(c1);\n\tclose(c2);\n\treturn err;\n}",
        "static int dfx_close(struct net_device *dev)\n{\n\tDFX_board_t *bp = netdev_priv(dev);\n\n\tDBG_printk(\"In dfx_close...\\n\");": "static int dfx_close(struct net_device *dev)\n{\n\tDFX_board_t *bp = netdev_priv(dev);\n\n\tDBG_printk(\"In dfx_close...\\n\");\n\n\t/* Disable PDQ interrupts first */\n\n\tdfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);\n\n\t/* Place adapter in DMA_UNAVAILABLE state by resetting adapter */\n\n\t(void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);\n\n\t/*\n\t * Flush any pending transmit buffers\n\t *\n\t * Note: It's important that we flush the transmit buffers\n\t *\t\t BEFORE we clear our copy of the Type 2 register.\n\t *\t\t Otherwise, we'll have no idea how many buffers\n\t *\t\t we need to free.\n\t */\n\n\tdfx_xmt_flush(bp);\n\n\t/*\n\t * Clear Type 1 and Type 2 registers after adapter reset\n\t *\n\t * Note: Even though we're closing the adapter, it's\n\t *       possible that an interrupt will occur after\n\t *\t\t dfx_close is called.  Without some assurance to\n\t *\t\t the contrary we want to make sure that we don't\n\t *\t\t process receive and transmit LLC frames and update\n\t *\t\t the Type 2 register with bad information.\n\t */\n\n\tbp->cmd_req_reg.lword\t= 0;\n\tbp->cmd_rsp_reg.lword\t= 0;\n\tbp->rcv_xmt_reg.lword\t= 0;\n\n\t/* Clear consumer block for the same reason given above */\n\n\tmemset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));\n\n\t/* Release all dynamically allocate skb in the receive ring. */\n\n\tdfx_rcv_flush(bp);\n\n\t/* Clear device structure flags */\n\n\tnetif_stop_queue(dev);\n\n\t/* Deregister (free) IRQ */\n\n\tfree_irq(dev->irq, dev);\n\n\treturn 0;\n}",
        "static void do_sched_cfs_slack_timer(struct cfs_bandwidth *cfs_b)\n{\n\tu64 runtime = 0, slice = sched_cfs_bandwidth_slice();\n\tunsigned long flags;\n": "static void do_sched_cfs_slack_timer(struct cfs_bandwidth *cfs_b)\n{\n\tu64 runtime = 0, slice = sched_cfs_bandwidth_slice();\n\tunsigned long flags;\n\n\t/* confirm we're still not at a refresh boundary */\n\traw_spin_lock_irqsave(&cfs_b->lock, flags);\n\tcfs_b->slack_started = false;\n\n\tif (runtime_refresh_within(cfs_b, min_bandwidth_expiration)) {\n\t\traw_spin_unlock_irqrestore(&cfs_b->lock, flags);\n\t\treturn;\n\t}\n\n\tif (cfs_b->quota != RUNTIME_INF && cfs_b->runtime > slice)\n\t\truntime = cfs_b->runtime;\n\n\traw_spin_unlock_irqrestore(&cfs_b->lock, flags);\n\n\tif (!runtime)\n\t\treturn;\n\n\tdistribute_cfs_runtime(cfs_b);\n}",
        "static void gtp0_build_echo_msg(struct gtp0_header *hdr, __u8 msg_type)\n{\n\tint len_pkt, len_hdr;\n\n\thdr->flags = 0x1e; /* v0, GTP-non-prime. */": "static void gtp0_build_echo_msg(struct gtp0_header *hdr, __u8 msg_type)\n{\n\tint len_pkt, len_hdr;\n\n\thdr->flags = 0x1e; /* v0, GTP-non-prime. */\n\thdr->type = msg_type;\n\t/* GSM TS 09.60. 7.3 In all Path Management Flow Label and TID\n\t * are not used and shall be set to 0.\n\t */\n\thdr->flow = 0;\n\thdr->tid = 0;\n\thdr->number = 0xff;\n\thdr->spare[0] = 0xff;\n\thdr->spare[1] = 0xff;\n\thdr->spare[2] = 0xff;\n\n\tlen_pkt = sizeof(struct gtp0_packet);\n\tlen_hdr = sizeof(struct gtp0_header);\n\n\tif (msg_type == GTP_ECHO_RSP)\n\t\thdr->length = htons(len_pkt - len_hdr);\n\telse\n\t\thdr->length = 0;\n}",
        "static int bperf__read(struct evsel *evsel)\n{\n\tstruct bperf_follower_bpf *skel = evsel->follower_skel;\n\t__u32 num_cpu_bpf = cpu__max_cpu().cpu;\n\tstruct bpf_perf_event_value values[num_cpu_bpf];": "static int bperf__read(struct evsel *evsel)\n{\n\tstruct bperf_follower_bpf *skel = evsel->follower_skel;\n\t__u32 num_cpu_bpf = cpu__max_cpu().cpu;\n\tstruct bpf_perf_event_value values[num_cpu_bpf];\n\tstruct perf_counts_values *counts;\n\tint reading_map_fd, err = 0;\n\t__u32 i;\n\tint j;\n\n\tbperf_sync_counters(evsel);\n\treading_map_fd = bpf_map__fd(skel->maps.accum_readings);\n\n\tfor (i = 0; i < bpf_map__max_entries(skel->maps.accum_readings); i++) {\n\t\tstruct perf_cpu entry;\n\t\t__u32 cpu;\n\n\t\terr = bpf_map_lookup_elem(reading_map_fd, &i, values);\n\t\tif (err)\n\t\t\tgoto out;\n\t\tswitch (evsel->follower_skel->bss->type) {\n\t\tcase BPERF_FILTER_GLOBAL:\n\t\t\tassert(i == 0);\n\n\t\t\tperf_cpu_map__for_each_cpu(entry, j, evsel__cpus(evsel)) {\n\t\t\t\tcounts = perf_counts(evsel->counts, j, 0);\n\t\t\t\tcounts->val = values[entry.cpu].counter;\n\t\t\t\tcounts->ena = values[entry.cpu].enabled;\n\t\t\t\tcounts->run = values[entry.cpu].running;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase BPERF_FILTER_CPU:\n\t\t\tcpu = perf_cpu_map__cpu(evsel__cpus(evsel), i).cpu;\n\t\t\tassert(cpu >= 0);\n\t\t\tcounts = perf_counts(evsel->counts, i, 0);\n\t\t\tcounts->val = values[cpu].counter;\n\t\t\tcounts->ena = values[cpu].enabled;\n\t\t\tcounts->run = values[cpu].running;\n\t\t\tbreak;\n\t\tcase BPERF_FILTER_PID:\n\t\tcase BPERF_FILTER_TGID:\n\t\t\tcounts = perf_counts(evsel->counts, 0, i);\n\t\t\tcounts->val = 0;\n\t\t\tcounts->ena = 0;\n\t\t\tcounts->run = 0;\n\n\t\t\tfor (cpu = 0; cpu < num_cpu_bpf; cpu++) {\n\t\t\t\tcounts->val += values[cpu].counter;\n\t\t\t\tcounts->ena += values[cpu].enabled;\n\t\t\t\tcounts->run += values[cpu].running;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\treturn err;\n}",
        "static void rcu_torture_write_types(void)\n{\n\tbool gp_cond1 = gp_cond, gp_exp1 = gp_exp, gp_normal1 = gp_normal;\n\tbool gp_poll1 = gp_poll, gp_sync1 = gp_sync;\n": "static void rcu_torture_write_types(void)\n{\n\tbool gp_cond1 = gp_cond, gp_exp1 = gp_exp, gp_normal1 = gp_normal;\n\tbool gp_poll1 = gp_poll, gp_sync1 = gp_sync;\n\n\t/* Initialize synctype[] array.  If none set, take default. */\n\tif (!gp_cond1 && !gp_exp1 && !gp_normal1 && !gp_poll1 && !gp_sync1)\n\t\tgp_cond1 = gp_exp1 = gp_normal1 = gp_poll1 = gp_sync1 = true;\n\tif (gp_cond1 && cur_ops->get_gp_state && cur_ops->cond_sync) {\n\t\tsynctype[nsynctypes++] = RTWS_COND_GET;\n\t\tpr_info(\"%s: Testing conditional GPs.\\n\", __func__);\n\t} else if (gp_cond && (!cur_ops->get_gp_state || !cur_ops->cond_sync)) {\n\t\tpr_alert(\"%s: gp_cond without primitives.\\n\", __func__);\n\t}\n\tif (gp_exp1 && cur_ops->exp_sync) {\n\t\tsynctype[nsynctypes++] = RTWS_EXP_SYNC;\n\t\tpr_info(\"%s: Testing expedited GPs.\\n\", __func__);\n\t} else if (gp_exp && !cur_ops->exp_sync) {\n\t\tpr_alert(\"%s: gp_exp without primitives.\\n\", __func__);\n\t}\n\tif (gp_normal1 && cur_ops->deferred_free) {\n\t\tsynctype[nsynctypes++] = RTWS_DEF_FREE;\n\t\tpr_info(\"%s: Testing asynchronous GPs.\\n\", __func__);\n\t} else if (gp_normal && !cur_ops->deferred_free) {\n\t\tpr_alert(\"%s: gp_normal without primitives.\\n\", __func__);\n\t}\n\tif (gp_poll1 && cur_ops->start_gp_poll && cur_ops->poll_gp_state) {\n\t\tsynctype[nsynctypes++] = RTWS_POLL_GET;\n\t\tpr_info(\"%s: Testing polling GPs.\\n\", __func__);\n\t} else if (gp_poll && (!cur_ops->start_gp_poll || !cur_ops->poll_gp_state)) {\n\t\tpr_alert(\"%s: gp_poll without primitives.\\n\", __func__);\n\t}\n\tif (gp_sync1 && cur_ops->sync) {\n\t\tsynctype[nsynctypes++] = RTWS_SYNC;\n\t\tpr_info(\"%s: Testing normal GPs.\\n\", __func__);\n\t} else if (gp_sync && !cur_ops->sync) {\n\t\tpr_alert(\"%s: gp_sync without primitives.\\n\", __func__);\n\t}\n}",
        "static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)\n{\n\tstruct pmc_dev *pmcdev = platform_get_drvdata(pdev);\n\tconst int num_maps = pmcdev->map->lpm_num_maps;\n\tu32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;": "static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)\n{\n\tstruct pmc_dev *pmcdev = platform_get_drvdata(pdev);\n\tconst int num_maps = pmcdev->map->lpm_num_maps;\n\tu32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;\n\tunion acpi_object *out_obj;\n\tstruct acpi_device *adev;\n\tguid_t s0ix_dsm_guid;\n\tu32 *lpm_req_regs, *addr;\n\n\tadev = ACPI_COMPANION(&pdev->dev);\n\tif (!adev)\n\t\treturn;\n\n\tguid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);\n\n\tout_obj = acpi_evaluate_dsm(adev->handle, &s0ix_dsm_guid, 0,\n\t\t\t\t    ACPI_GET_LOW_MODE_REGISTERS, NULL);\n\tif (out_obj && out_obj->type == ACPI_TYPE_BUFFER) {\n\t\tu32 size = out_obj->buffer.length;\n\n\t\tif (size != lpm_size) {\n\t\t\tacpi_handle_debug(adev->handle,\n\t\t\t\t\"_DSM returned unexpected buffer size, have %u, expect %u\\n\",\n\t\t\t\tsize, lpm_size);\n\t\t\tgoto free_acpi_obj;\n\t\t}\n\t} else {\n\t\tacpi_handle_debug(adev->handle,\n\t\t\t\t  \"_DSM function 0 evaluation failed\\n\");\n\t\tgoto free_acpi_obj;\n\t}\n\n\taddr = (u32 *)out_obj->buffer.pointer;\n\n\tlpm_req_regs = devm_kzalloc(&pdev->dev, lpm_size * sizeof(u32),\n\t\t\t\t     GFP_KERNEL);\n\tif (!lpm_req_regs)\n\t\tgoto free_acpi_obj;\n\n\tmemcpy(lpm_req_regs, addr, lpm_size);\n\tpmcdev->lpm_req_regs = lpm_req_regs;\n\nfree_acpi_obj:\n\tACPI_FREE(out_obj);\n}",
        "static int __init test_f4(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 u[32] = {\n\t\t\t0xe6, 0x9d, 0x35, 0x0e, 0x48, 0x01, 0x03, 0xcc,\n\t\t\t0xdb, 0xfd, 0xf4, 0xac, 0x11, 0x91, 0xf4, 0xef,": "static int __init test_f4(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 u[32] = {\n\t\t\t0xe6, 0x9d, 0x35, 0x0e, 0x48, 0x01, 0x03, 0xcc,\n\t\t\t0xdb, 0xfd, 0xf4, 0xac, 0x11, 0x91, 0xf4, 0xef,\n\t\t\t0xb9, 0xa5, 0xf9, 0xe9, 0xa7, 0x83, 0x2c, 0x5e,\n\t\t\t0x2c, 0xbe, 0x97, 0xf2, 0xd2, 0x03, 0xb0, 0x20 };\n\tconst u8 v[32] = {\n\t\t\t0xfd, 0xc5, 0x7f, 0xf4, 0x49, 0xdd, 0x4f, 0x6b,\n\t\t\t0xfb, 0x7c, 0x9d, 0xf1, 0xc2, 0x9a, 0xcb, 0x59,\n\t\t\t0x2a, 0xe7, 0xd4, 0xee, 0xfb, 0xfc, 0x0a, 0x90,\n\t\t\t0x9a, 0xbb, 0xf6, 0x32, 0x3d, 0x8b, 0x18, 0x55 };\n\tconst u8 x[16] = {\n\t\t\t0xab, 0xae, 0x2b, 0x71, 0xec, 0xb2, 0xff, 0xff,\n\t\t\t0x3e, 0x73, 0x77, 0xd1, 0x54, 0x84, 0xcb, 0xd5 };\n\tconst u8 z = 0x00;\n\tconst u8 exp[16] = {\n\t\t\t0x2d, 0x87, 0x74, 0xa9, 0xbe, 0xa1, 0xed, 0xf1,\n\t\t\t0x1c, 0xbd, 0xa9, 0x07, 0xf1, 0x16, 0xc9, 0xf2 };\n\tu8 res[16];\n\tint err;\n\n\terr = smp_f4(tfm_cmac, u, v, x, z, res);\n\tif (err)\n\t\treturn err;\n\n\tif (crypto_memneq(res, exp, 16))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static int pipapo_resize(struct nft_pipapo_field *f, int old_rules, int rules)\n{\n\tlong *new_lt = NULL, *new_p, *old_lt = f->lt, *old_p;\n\tunion nft_pipapo_map_bucket *new_mt, *old_mt = f->mt;\n\tsize_t new_bucket_size, copy;": "static int pipapo_resize(struct nft_pipapo_field *f, int old_rules, int rules)\n{\n\tlong *new_lt = NULL, *new_p, *old_lt = f->lt, *old_p;\n\tunion nft_pipapo_map_bucket *new_mt, *old_mt = f->mt;\n\tsize_t new_bucket_size, copy;\n\tint group, bucket;\n\n\tnew_bucket_size = DIV_ROUND_UP(rules, BITS_PER_LONG);\n#ifdef NFT_PIPAPO_ALIGN\n\tnew_bucket_size = roundup(new_bucket_size,\n\t\t\t\t  NFT_PIPAPO_ALIGN / sizeof(*new_lt));\n#endif\n\n\tif (new_bucket_size == f->bsize)\n\t\tgoto mt;\n\n\tif (new_bucket_size > f->bsize)\n\t\tcopy = f->bsize;\n\telse\n\t\tcopy = new_bucket_size;\n\n\tnew_lt = kvzalloc(f->groups * NFT_PIPAPO_BUCKETS(f->bb) *\n\t\t\t  new_bucket_size * sizeof(*new_lt) +\n\t\t\t  NFT_PIPAPO_ALIGN_HEADROOM,\n\t\t\t  GFP_KERNEL);\n\tif (!new_lt)\n\t\treturn -ENOMEM;\n\n\tnew_p = NFT_PIPAPO_LT_ALIGN(new_lt);\n\told_p = NFT_PIPAPO_LT_ALIGN(old_lt);\n\n\tfor (group = 0; group < f->groups; group++) {\n\t\tfor (bucket = 0; bucket < NFT_PIPAPO_BUCKETS(f->bb); bucket++) {\n\t\t\tmemcpy(new_p, old_p, copy * sizeof(*new_p));\n\t\t\tnew_p += copy;\n\t\t\told_p += copy;\n\n\t\t\tif (new_bucket_size > f->bsize)\n\t\t\t\tnew_p += new_bucket_size - f->bsize;\n\t\t\telse\n\t\t\t\told_p += f->bsize - new_bucket_size;\n\t\t}\n\t}\n\nmt:\n\tnew_mt = kvmalloc(rules * sizeof(*new_mt), GFP_KERNEL);\n\tif (!new_mt) {\n\t\tkvfree(new_lt);\n\t\treturn -ENOMEM;\n\t}\n\n\tmemcpy(new_mt, f->mt, min(old_rules, rules) * sizeof(*new_mt));\n\tif (rules > old_rules) {\n\t\tmemset(new_mt + old_rules, 0,\n\t\t       (rules - old_rules) * sizeof(*new_mt));\n\t}\n\n\tif (new_lt) {\n\t\tf->bsize = new_bucket_size;\n\t\tNFT_PIPAPO_LT_ASSIGN(f, new_lt);\n\t\tkvfree(old_lt);\n\t}\n\n\tf->mt = new_mt;\n\tkvfree(old_mt);\n\n\treturn 0;\n}",
        "static int t7xx_cldma_suspend(struct t7xx_pci_dev *t7xx_dev, void *entity_param)\n{\n\tstruct cldma_ctrl *md_ctrl = entity_param;\n\tstruct t7xx_cldma_hw *hw_info;\n\tunsigned long flags;": "static int t7xx_cldma_suspend(struct t7xx_pci_dev *t7xx_dev, void *entity_param)\n{\n\tstruct cldma_ctrl *md_ctrl = entity_param;\n\tstruct t7xx_cldma_hw *hw_info;\n\tunsigned long flags;\n\n\tif (md_ctrl->hif_id == CLDMA_ID_MD)\n\t\tt7xx_mhccif_mask_set(t7xx_dev, D2H_SW_INT_MASK);\n\n\thw_info = &md_ctrl->hw_info;\n\n\tspin_lock_irqsave(&md_ctrl->cldma_lock, flags);\n\tt7xx_cldma_hw_irq_dis_eq(hw_info, CLDMA_ALL_Q, MTK_TX);\n\tt7xx_cldma_hw_irq_dis_txrx(hw_info, CLDMA_ALL_Q, MTK_TX);\n\tmd_ctrl->txq_active &= ~TXRX_STATUS_BITMASK;\n\tt7xx_cldma_hw_stop_all_qs(hw_info, MTK_TX);\n\tmd_ctrl->txq_started = 0;\n\tspin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);\n\n\treturn 0;\n}",
        "static int demod_attach_stv0910(struct ddb_input *input, int type, int tsfast)\n{\n\tstruct i2c_adapter *i2c = &input->port->i2c->adap;\n\tstruct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];\n\tstruct device *dev = input->port->dev->dev;": "static int demod_attach_stv0910(struct ddb_input *input, int type, int tsfast)\n{\n\tstruct i2c_adapter *i2c = &input->port->i2c->adap;\n\tstruct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];\n\tstruct device *dev = input->port->dev->dev;\n\tstruct stv0910_cfg cfg = stv0910_p;\n\tstruct lnbh25_config lnbcfg = lnbh25_cfg;\n\n\tif (stv0910_single)\n\t\tcfg.single = 1;\n\n\tif (type)\n\t\tcfg.parallel = 2;\n\n\tif (tsfast) {\n\t\tdev_info(dev, \"Enabling stv0910 higher speed TS\\n\");\n\t\tcfg.tsspeed = 0x10;\n\t}\n\n\tdvb->fe = dvb_attach(stv0910_attach, i2c, &cfg, (input->nr & 1));\n\tif (!dvb->fe) {\n\t\tcfg.adr = 0x6c;\n\t\tdvb->fe = dvb_attach(stv0910_attach, i2c,\n\t\t\t\t     &cfg, (input->nr & 1));\n\t}\n\tif (!dvb->fe) {\n\t\tdev_err(dev, \"No STV0910 found!\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\t/* attach lnbh25 - leftshift by one as the lnbh25 driver expects 8bit\n\t * i2c addresses\n\t */\n\tif (has_lnbh25(i2c, 0x0d))\n\t\tlnbcfg.i2c_address = (((input->nr & 1) ? 0x0d : 0x0c) << 1);\n\telse\n\t\tlnbcfg.i2c_address = (((input->nr & 1) ? 0x09 : 0x08) << 1);\n\n\tif (!dvb_attach(lnbh25_attach, dvb->fe, &lnbcfg, i2c)) {\n\t\tdev_err(dev, \"No LNBH25 found!\\n\");\n\t\tdvb_frontend_detach(dvb->fe);\n\t\treturn -ENODEV;\n\t}\n\n\treturn 0;\n}",
        "static struct sctp_ulpevent *sctp_intl_retrieve_first(struct sctp_ulpq *ulpq)\n{\n\tstruct sctp_stream_in *csin, *sin = NULL;\n\tstruct sk_buff *first_frag = NULL;\n\tstruct sk_buff *last_frag = NULL;": "static struct sctp_ulpevent *sctp_intl_retrieve_first(struct sctp_ulpq *ulpq)\n{\n\tstruct sctp_stream_in *csin, *sin = NULL;\n\tstruct sk_buff *first_frag = NULL;\n\tstruct sk_buff *last_frag = NULL;\n\tstruct sctp_ulpevent *retval;\n\tstruct sk_buff *pos;\n\t__u32 next_fsn = 0;\n\t__u16 sid = 0;\n\n\tskb_queue_walk(&ulpq->reasm, pos) {\n\t\tstruct sctp_ulpevent *cevent = sctp_skb2event(pos);\n\n\t\tcsin = sctp_stream_in(&ulpq->asoc->stream, cevent->stream);\n\t\tif (csin->pd_mode)\n\t\t\tcontinue;\n\n\t\tswitch (cevent->msg_flags & SCTP_DATA_FRAG_MASK) {\n\t\tcase SCTP_DATA_FIRST_FRAG:\n\t\t\tif (first_frag)\n\t\t\t\tgoto out;\n\t\t\tif (cevent->mid == csin->mid) {\n\t\t\t\tfirst_frag = pos;\n\t\t\t\tlast_frag = pos;\n\t\t\t\tnext_fsn = 0;\n\t\t\t\tsin = csin;\n\t\t\t\tsid = cevent->stream;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase SCTP_DATA_MIDDLE_FRAG:\n\t\t\tif (!first_frag)\n\t\t\t\tbreak;\n\t\t\tif (cevent->stream == sid &&\n\t\t\t    cevent->mid == sin->mid &&\n\t\t\t    cevent->fsn == next_fsn) {\n\t\t\t\tnext_fsn++;\n\t\t\t\tlast_frag = pos;\n\t\t\t} else {\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase SCTP_DATA_LAST_FRAG:\n\t\t\tif (first_frag)\n\t\t\t\tgoto out;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!first_frag)\n\t\treturn NULL;\n\nout:\n\tretval = sctp_make_reassembled_event(ulpq->asoc->base.net,\n\t\t\t\t\t     &ulpq->reasm, first_frag,\n\t\t\t\t\t     last_frag);\n\tif (retval) {\n\t\tsin->fsn = next_fsn;\n\t\tsin->pd_mode = 1;\n\t}\n\n\treturn retval;\n}",
        "static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)\n{\n\tu32 rx_start_idx, rx_idx, tx_idx, opaque_key;\n\tu32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;\n\tu32 budget;": "static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)\n{\n\tu32 rx_start_idx, rx_idx, tx_idx, opaque_key;\n\tu32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;\n\tu32 budget;\n\tstruct sk_buff *skb;\n\tu8 *tx_data, *rx_data;\n\tdma_addr_t map;\n\tint num_pkts, tx_len, rx_len, i, err;\n\tstruct tg3_rx_buffer_desc *desc;\n\tstruct tg3_napi *tnapi, *rnapi;\n\tstruct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;\n\n\ttnapi = &tp->napi[0];\n\trnapi = &tp->napi[0];\n\tif (tp->irq_cnt > 1) {\n\t\tif (tg3_flag(tp, ENABLE_RSS))\n\t\t\trnapi = &tp->napi[1];\n\t\tif (tg3_flag(tp, ENABLE_TSS))\n\t\t\ttnapi = &tp->napi[1];\n\t}\n\tcoal_now = tnapi->coal_now | rnapi->coal_now;\n\n\terr = -EIO;\n\n\ttx_len = pktsz;\n\tskb = netdev_alloc_skb(tp->dev, tx_len);\n\tif (!skb)\n\t\treturn -ENOMEM;\n\n\ttx_data = skb_put(skb, tx_len);\n\tmemcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);\n\tmemset(tx_data + ETH_ALEN, 0x0, 8);\n\n\ttw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);\n\n\tif (tso_loopback) {\n\t\tstruct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];\n\n\t\tu32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +\n\t\t\t      TG3_TSO_TCP_OPT_LEN;\n\n\t\tmemcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,\n\t\t       sizeof(tg3_tso_header));\n\t\tmss = TG3_TSO_MSS;\n\n\t\tval = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);\n\t\tnum_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);\n\n\t\t/* Set the total length field in the IP header */\n\t\tiph->tot_len = htons((u16)(mss + hdr_len));\n\n\t\tbase_flags = (TXD_FLAG_CPU_PRE_DMA |\n\t\t\t      TXD_FLAG_CPU_POST_DMA);\n\n\t\tif (tg3_flag(tp, HW_TSO_1) ||\n\t\t    tg3_flag(tp, HW_TSO_2) ||\n\t\t    tg3_flag(tp, HW_TSO_3)) {\n\t\t\tstruct tcphdr *th;\n\t\t\tval = ETH_HLEN + TG3_TSO_IP_HDR_LEN;\n\t\t\tth = (struct tcphdr *)&tx_data[val];\n\t\t\tth->check = 0;\n\t\t} else\n\t\t\tbase_flags |= TXD_FLAG_TCPUDP_CSUM;\n\n\t\tif (tg3_flag(tp, HW_TSO_3)) {\n\t\t\tmss |= (hdr_len & 0xc) << 12;\n\t\t\tif (hdr_len & 0x10)\n\t\t\t\tbase_flags |= 0x00000010;\n\t\t\tbase_flags |= (hdr_len & 0x3e0) << 5;\n\t\t} else if (tg3_flag(tp, HW_TSO_2))\n\t\t\tmss |= hdr_len << 9;\n\t\telse if (tg3_flag(tp, HW_TSO_1) ||\n\t\t\t tg3_asic_rev(tp) == ASIC_REV_5705) {\n\t\t\tmss |= (TG3_TSO_TCP_OPT_LEN << 9);\n\t\t} else {\n\t\t\tbase_flags |= (TG3_TSO_TCP_OPT_LEN << 10);\n\t\t}\n\n\t\tdata_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);\n\t} else {\n\t\tnum_pkts = 1;\n\t\tdata_off = ETH_HLEN;\n\n\t\tif (tg3_flag(tp, USE_JUMBO_BDFLAG) &&\n\t\t    tx_len > VLAN_ETH_FRAME_LEN)\n\t\t\tbase_flags |= TXD_FLAG_JMB_PKT;\n\t}\n\n\tfor (i = data_off; i < tx_len; i++)\n\t\ttx_data[i] = (u8) (i & 0xff);\n\n\tmap = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE);\n\tif (dma_mapping_error(&tp->pdev->dev, map)) {\n\t\tdev_kfree_skb(skb);\n\t\treturn -EIO;\n\t}\n\n\tval = tnapi->tx_prod;\n\ttnapi->tx_buffers[val].skb = skb;\n\tdma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);\n\n\ttw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |\n\t       rnapi->coal_now);\n\n\tudelay(10);\n\n\trx_start_idx = rnapi->hw_status->idx[0].rx_producer;\n\n\tbudget = tg3_tx_avail(tnapi);\n\tif (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,\n\t\t\t    base_flags | TXD_FLAG_END, mss, 0)) {\n\t\ttnapi->tx_buffers[val].skb = NULL;\n\t\tdev_kfree_skb(skb);\n\t\treturn -EIO;\n\t}\n\n\ttnapi->tx_prod++;\n\n\t/* Sync BD data before updating mailbox */\n\twmb();\n\n\ttw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);\n\ttr32_mailbox(tnapi->prodmbox);\n\n\tudelay(10);\n\n\t/* 350 usec to allow enough time on some 10/100 Mbps devices.  */\n\tfor (i = 0; i < 35; i++) {\n\t\ttw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |\n\t\t       coal_now);\n\n\t\tudelay(10);\n\n\t\ttx_idx = tnapi->hw_status->idx[0].tx_consumer;\n\t\trx_idx = rnapi->hw_status->idx[0].rx_producer;\n\t\tif ((tx_idx == tnapi->tx_prod) &&\n\t\t    (rx_idx == (rx_start_idx + num_pkts)))\n\t\t\tbreak;\n\t}\n\n\ttg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);\n\tdev_kfree_skb(skb);\n\n\tif (tx_idx != tnapi->tx_prod)\n\t\tgoto out;\n\n\tif (rx_idx != rx_start_idx + num_pkts)\n\t\tgoto out;\n\n\tval = data_off;\n\twhile (rx_idx != rx_start_idx) {\n\t\tdesc = &rnapi->rx_rcb[rx_start_idx++];\n\t\tdesc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;\n\t\topaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;\n\n\t\tif ((desc->err_vlan & RXD_ERR_MASK) != 0 &&\n\t\t    (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))\n\t\t\tgoto out;\n\n\t\trx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)\n\t\t\t - ETH_FCS_LEN;\n\n\t\tif (!tso_loopback) {\n\t\t\tif (rx_len != tx_len)\n\t\t\t\tgoto out;\n\n\t\t\tif (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {\n\t\t\t\tif (opaque_key != RXD_OPAQUE_RING_STD)\n\t\t\t\t\tgoto out;\n\t\t\t} else {\n\t\t\t\tif (opaque_key != RXD_OPAQUE_RING_JUMBO)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\t\t} else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&\n\t\t\t   (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)\n\t\t\t    >> RXD_TCPCSUM_SHIFT != 0xffff) {\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (opaque_key == RXD_OPAQUE_RING_STD) {\n\t\t\trx_data = tpr->rx_std_buffers[desc_idx].data;\n\t\t\tmap = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],\n\t\t\t\t\t     mapping);\n\t\t} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {\n\t\t\trx_data = tpr->rx_jmb_buffers[desc_idx].data;\n\t\t\tmap = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],\n\t\t\t\t\t     mapping);\n\t\t} else\n\t\t\tgoto out;\n\n\t\tdma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len,\n\t\t\t\t\tDMA_FROM_DEVICE);\n\n\t\trx_data += TG3_RX_OFFSET(tp);\n\t\tfor (i = data_off; i < rx_len; i++, val++) {\n\t\t\tif (*(rx_data + i) != (u8) (val & 0xff))\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\terr = 0;\n\n\t/* tg3_free_rings will unmap and free the rx_data */\nout:\n\treturn err;\n}",
        "static void tf103c_dock_report_toprow_kbd_hook(struct tf103c_dock_data *dock)\n{\n\tu8 *esc, *buf = dock->kbd_buf;\n\tint size;\n": "static void tf103c_dock_report_toprow_kbd_hook(struct tf103c_dock_data *dock)\n{\n\tu8 *esc, *buf = dock->kbd_buf;\n\tint size;\n\n\t/*\n\t * Stop AltGr reports from getting reported on the \"Asus TF103C Dock\n\t * Keyboard\" input_dev, since this gets used as \"Fn\" key for the toprow\n\t * keys. Instead we report this on the \"Asus TF103C Dock Top Row Keys\"\n\t * input_dev, when not used to modify the toprow keys.\n\t */\n\tdock->altgr_pressed = buf[TF103C_DOCK_KBD_DATA_MODIFIERS] & 0x40;\n\tbuf[TF103C_DOCK_KBD_DATA_MODIFIERS] &= ~0x40;\n\n\tinput_report_key(dock->input, KEY_RIGHTALT, dock->altgr_pressed);\n\tinput_sync(dock->input);\n\n\t/* Toggle fnlock on AltGr + Esc press */\n\tbuf = buf + TF103C_DOCK_KBD_DATA_KEYS;\n\tsize = TF103C_DOCK_KBD_DATA_MAX_LENGTH - TF103C_DOCK_KBD_DATA_KEYS;\n\tesc = memchr(buf, 0x29, size);\n\tif (!dock->esc_pressed && esc) {\n\t\tif (dock->altgr_pressed) {\n\t\t\tfnlock = !fnlock;\n\t\t\tdock->filter_esc = true;\n\t\t}\n\t}\n\tif (esc && dock->filter_esc)\n\t\t*esc = 0;\n\telse\n\t\tdock->filter_esc = false;\n\n\tdock->esc_pressed = esc != NULL;\n}",
        "static void test_xdp_bonding_with_mode(struct skeletons *skeletons, int mode, int xmit_policy)\n{\n\tint bond1_rx;\n\n\tif (bonding_setup(skeletons, mode, xmit_policy, BOND_BOTH_AND_ATTACH))": "static void test_xdp_bonding_with_mode(struct skeletons *skeletons, int mode, int xmit_policy)\n{\n\tint bond1_rx;\n\n\tif (bonding_setup(skeletons, mode, xmit_policy, BOND_BOTH_AND_ATTACH))\n\t\tgoto out;\n\n\tif (send_udp_packets(xmit_policy != BOND_XMIT_POLICY_LAYER34))\n\t\tgoto out;\n\n\tbond1_rx = get_rx_packets(\"bond1\");\n\tASSERT_EQ(bond1_rx, NPACKETS, \"expected more received packets\");\n\n\tswitch (mode) {\n\tcase BOND_MODE_ROUNDROBIN:\n\tcase BOND_MODE_XOR: {\n\t\tint veth1_rx = get_rx_packets(\"veth1_1\");\n\t\tint veth2_rx = get_rx_packets(\"veth1_2\");\n\t\tint diff = abs(veth1_rx - veth2_rx);\n\n\t\tASSERT_GE(veth1_rx + veth2_rx, NPACKETS, \"expected more packets\");\n\n\t\tswitch (xmit_policy) {\n\t\tcase BOND_XMIT_POLICY_LAYER2:\n\t\t\tASSERT_GE(diff, NPACKETS,\n\t\t\t\t  \"expected packets on only one of the interfaces\");\n\t\t\tbreak;\n\t\tcase BOND_XMIT_POLICY_LAYER23:\n\t\tcase BOND_XMIT_POLICY_LAYER34:\n\t\t\tASSERT_LT(diff, NPACKETS/2,\n\t\t\t\t  \"expected even distribution of packets\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPRINT_FAIL(\"Unimplemented xmit_policy=%d\\n\", xmit_policy);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n\tcase BOND_MODE_ACTIVEBACKUP: {\n\t\tint veth1_rx = get_rx_packets(\"veth1_1\");\n\t\tint veth2_rx = get_rx_packets(\"veth1_2\");\n\t\tint diff = abs(veth1_rx - veth2_rx);\n\n\t\tASSERT_GE(diff, NPACKETS,\n\t\t\t  \"expected packets on only one of the interfaces\");\n\t\tbreak;\n\t}\n\tdefault:\n\t\tPRINT_FAIL(\"Unimplemented xmit_policy=%d\\n\", xmit_policy);\n\t\tbreak;\n\t}\n\nout:\n\tbonding_cleanup(skeletons);\n}",
        "static inline bool service_channel(u8 ch_addr, u8 idx)\n{\n\tu8 const shift = idx * 16;\n\tu32 const adt1 = dim2_read_ctr(ADT + ch_addr, 1);\n\tu32 mask[4] = { 0, 0, 0, 0 };": "static inline bool service_channel(u8 ch_addr, u8 idx)\n{\n\tu8 const shift = idx * 16;\n\tu32 const adt1 = dim2_read_ctr(ADT + ch_addr, 1);\n\tu32 mask[4] = { 0, 0, 0, 0 };\n\tu32 adt_w[4] = { 0, 0, 0, 0 };\n\n\tif (((adt1 >> (ADT1_DNE_BIT + shift)) & 1) == 0)\n\t\treturn false;\n\n\tmask[1] =\n\t\tbit_mask(ADT1_DNE_BIT + shift) |\n\t\tbit_mask(ADT1_ERR_BIT + shift) |\n\t\tbit_mask(ADT1_RDY_BIT + shift);\n\tdim2_write_ctr_mask(ADT + ch_addr, mask, adt_w);\n\n\t/* clear channel status bit */\n\twritel(bit_mask(ch_addr), &g.dim2->ACSR0);\n\n\treturn true;\n}",
        "static void cmpk_handle_interrupt_status(struct net_device *dev, u8 *pmsg)\n{\n\tstruct cmd_pkt_interrupt_status\t rx_intr_status;\t/* */\n\tstruct r8192_priv *priv = ieee80211_priv(dev);\n": "static void cmpk_handle_interrupt_status(struct net_device *dev, u8 *pmsg)\n{\n\tstruct cmd_pkt_interrupt_status\t rx_intr_status;\t/* */\n\tstruct r8192_priv *priv = ieee80211_priv(dev);\n\n\tDMESG(\"---> cmpk_Handle_Interrupt_Status()\\n\");\n\n\t/* 1. Extract TX feedback info from RFD to temp structure buffer. */\n\t/* It seems that FW use big endian(MIPS) and DRV use little endian in\n\t * windows OS. So we have to read the content byte by byte or transfer\n\t * endian type before copy the message copy.\n\t */\n\trx_intr_status.length = pmsg[1];\n\tif (rx_intr_status.length != (sizeof(struct cmd_pkt_interrupt_status) - 2)) {\n\t\tDMESG(\"cmpk_Handle_Interrupt_Status: wrong length!\\n\");\n\t\treturn;\n\t}\n\n\t/* Statistics of beacon for ad-hoc mode. */\n\tif (priv->ieee80211->iw_mode == IW_MODE_ADHOC) {\n\t\t/* 2 maybe need endian transform? */\n\t\trx_intr_status.interrupt_status = *((u32 *)(pmsg + 4));\n\n\t\tDMESG(\"interrupt status = 0x%x\\n\",\n\t\t      rx_intr_status.interrupt_status);\n\n\t\tif (rx_intr_status.interrupt_status & ISR_TX_BCN_OK) {\n\t\t\tpriv->ieee80211->bibsscoordinator = true;\n\t\t\tpriv->stats.txbeaconokint++;\n\t\t} else if (rx_intr_status.interrupt_status & ISR_TX_BCN_ERR) {\n\t\t\tpriv->ieee80211->bibsscoordinator = false;\n\t\t\tpriv->stats.txbeaconerr++;\n\t\t}\n\n\t\tif (rx_intr_status.interrupt_status & ISR_BCN_TIMER_INTR)\n\t\t\tcmdpkt_beacontimerinterrupt_819xusb(dev);\n\t}\n\n\t/* Other information in interrupt status we need? */\n\n\tDMESG(\"<---- cmpk_handle_interrupt_status()\\n\");\n}",
        "static void test_setsockopt_set_and_get(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL, *link_get_retval = NULL;\n": "static void test_setsockopt_set_and_get(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_set_eunatch = NULL, *link_get_retval = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that sets EUNATCH, and one that gets the\n\t * previously set errno. Assert that we get the same errno back.\n\t */\n\tlink_set_eunatch = bpf_program__attach_cgroup(obj->progs.set_eunatch,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eunatch, \"cg-attach-set_eunatch\"))\n\t\tgoto close_bpf_object;\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t   &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EUNATCH, \"setsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 2, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, -EUNATCH, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_set_eunatch);\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static int vga_3wr_probe(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint i;\n\tu16 retword;": "static int vga_3wr_probe(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint i;\n\tu16 retword;\n\n/*fixme: lack of 8b=b3 (11,12)-> 10, 8b=e0 (14,15,16)-> 12 found in gspcav1*/\n\treg_w(gspca_dev, 0x02, 0x0010);\n\treg_r(gspca_dev, 0x0010);\n\treg_w(gspca_dev, 0x01, 0x0000);\n\treg_w(gspca_dev, 0x00, 0x0010);\n\treg_w(gspca_dev, 0x01, 0x0001);\n\treg_w(gspca_dev, 0x91, 0x008b);\n\treg_w(gspca_dev, 0x03, 0x0012);\n\treg_w(gspca_dev, 0x01, 0x0012);\n\treg_w(gspca_dev, 0x05, 0x0012);\n\tretword = i2c_read(gspca_dev, 0x14);\n\tif (retword != 0)\n\t\treturn 0x11;\t\t\t/* HV7131R */\n\tretword = i2c_read(gspca_dev, 0x15);\n\tif (retword != 0)\n\t\treturn 0x11;\t\t\t/* HV7131R */\n\tretword = i2c_read(gspca_dev, 0x16);\n\tif (retword != 0)\n\t\treturn 0x11;\t\t\t/* HV7131R */\n\n\treg_w(gspca_dev, 0x02, 0x0010);\n\tretword = reg_r(gspca_dev, 0x000b) << 8;\n\tretword |= reg_r(gspca_dev, 0x000a);\n\tgspca_dbg(gspca_dev, D_PROBE, \"probe 3wr vga 1 0x%04x\\n\", retword);\n\treg_r(gspca_dev, 0x0010);\n\tif ((retword & 0xff00) == 0x6400)\n\t\treturn 0x02;\t\t/* TAS5130C */\n\tfor (i = 0; i < ARRAY_SIZE(chipset_revision_sensor); i++) {\n\t\tif (chipset_revision_sensor[i].revision == retword) {\n\t\t\tsd->chip_revision = retword;\n\t\t\tsend_unknown(gspca_dev, SENSOR_PB0330);\n\t\t\treturn chipset_revision_sensor[i].internal_sensor_id;\n\t\t}\n\t}\n\n\treg_w(gspca_dev, 0x01, 0x0000);\t/* check PB0330 */\n\treg_w(gspca_dev, 0x01, 0x0001);\n\treg_w(gspca_dev, 0xdd, 0x008b);\n\treg_w(gspca_dev, 0x0a, 0x0010);\n\treg_w(gspca_dev, 0x03, 0x0012);\n\treg_w(gspca_dev, 0x01, 0x0012);\n\tretword = i2c_read(gspca_dev, 0x00);\n\tif (retword != 0) {\n\t\tgspca_dbg(gspca_dev, D_PROBE, \"probe 3wr vga type 0a\\n\");\n\t\treturn 0x0a;\t\t\t/* PB0330 */\n\t}\n\n\t/* probe gc0303 / gc0305 */\n\treg_w(gspca_dev, 0x01, 0x0000);\n\treg_w(gspca_dev, 0x01, 0x0001);\n\treg_w(gspca_dev, 0x98, 0x008b);\n\treg_w(gspca_dev, 0x01, 0x0010);\n\treg_w(gspca_dev, 0x03, 0x0012);\n\tmsleep(2);\n\treg_w(gspca_dev, 0x01, 0x0012);\n\tretword = i2c_read(gspca_dev, 0x00);\n\tif (retword != 0) {\n\t\tgspca_dbg(gspca_dev, D_PROBE, \"probe 3wr vga type %02x\\n\",\n\t\t\t  retword);\n\t\tif (retword == 0x0011)\t\t\t/* gc0303 */\n\t\t\treturn 0x0303;\n\t\tif (retword == 0x0029)\t\t\t/* gc0305 */\n\t\t\tsend_unknown(gspca_dev, SENSOR_GC0305);\n\t\treturn retword;\n\t}\n\n\treg_w(gspca_dev, 0x01, 0x0000);\t/* check OmniVision */\n\treg_w(gspca_dev, 0x01, 0x0001);\n\treg_w(gspca_dev, 0xa1, 0x008b);\n\treg_w(gspca_dev, 0x08, 0x008d);\n\treg_w(gspca_dev, 0x06, 0x0010);\n\treg_w(gspca_dev, 0x01, 0x0012);\n\treg_w(gspca_dev, 0x05, 0x0012);\n\tif (i2c_read(gspca_dev, 0x1c) == 0x007f\t/* OV7610 - manufacturer ID */\n\t    && i2c_read(gspca_dev, 0x1d) == 0x00a2) {\n\t\tsend_unknown(gspca_dev, SENSOR_OV7620);\n\t\treturn 0x06;\t\t/* OmniVision confirm ? */\n\t}\n\n\treg_w(gspca_dev, 0x01, 0x0000);\n\treg_w(gspca_dev, 0x00, 0x0002);\n\treg_w(gspca_dev, 0x01, 0x0010);\n\treg_w(gspca_dev, 0x01, 0x0001);\n\treg_w(gspca_dev, 0xee, 0x008b);\n\treg_w(gspca_dev, 0x03, 0x0012);\n\treg_w(gspca_dev, 0x01, 0x0012);\n\treg_w(gspca_dev, 0x05, 0x0012);\n\tretword = i2c_read(gspca_dev, 0x00) << 8;\t/* ID 0 */\n\tretword |= i2c_read(gspca_dev, 0x01);\t\t/* ID 1 */\n\tgspca_dbg(gspca_dev, D_PROBE, \"probe 3wr vga 2 0x%04x\\n\", retword);\n\tif (retword == 0x2030) {\n\t\tu8 retbyte;\n\n\t\tretbyte = i2c_read(gspca_dev, 0x02);\t/* revision number */\n\t\tgspca_dbg(gspca_dev, D_PROBE, \"sensor PO2030 rev 0x%02x\\n\",\n\t\t\t  retbyte);\n\n\t\tsend_unknown(gspca_dev, SENSOR_PO2030);\n\t\treturn retword;\n\t}\n\n\treg_w(gspca_dev, 0x01, 0x0000);\n\treg_w(gspca_dev, 0x0a, 0x0010);\n\treg_w(gspca_dev, 0xd3, 0x008b);\n\treg_w(gspca_dev, 0x01, 0x0001);\n\treg_w(gspca_dev, 0x03, 0x0012);\n\treg_w(gspca_dev, 0x01, 0x0012);\n\treg_w(gspca_dev, 0x05, 0x0012);\n\treg_w(gspca_dev, 0xd3, 0x008b);\n\tretword = i2c_read(gspca_dev, 0x01);\n\tif (retword != 0) {\n\t\tgspca_dbg(gspca_dev, D_PROBE, \"probe 3wr vga type 0a ? ret: %04x\\n\",\n\t\t\t  retword);\n\t\treturn 0x16;\t\t\t/* adcm2700 (6100/6200) */\n\t}\n\treturn -1;\n}",
        "static void alc_headset_mode_omtp(struct hda_codec *codec)\n{\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */\n\t\tWRITE_COEF(0x1b, 0x0c2b),": "static void alc_headset_mode_omtp(struct hda_codec *codec)\n{\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */\n\t\tWRITE_COEF(0x1b, 0x0c2b),\n\t\tWRITE_COEFEX(0x57, 0x03, 0x8ea6),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0256[] = {\n\t\tWRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */\n\t\tWRITE_COEF(0x1b, 0x0e6b),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0233[] = {\n\t\tWRITE_COEF(0x45, 0xe429),\n\t\tWRITE_COEF(0x1b, 0x0c2b),\n\t\tWRITE_COEF(0x32, 0x4ea3),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0288[] = {\n\t\tUPDATE_COEF(0x50, 0x2000, 0x2000),\n\t\tUPDATE_COEF(0x56, 0x0006, 0x0006),\n\t\tUPDATE_COEF(0x66, 0x0008, 0),\n\t\tUPDATE_COEF(0x67, 0x2000, 0),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0292[] = {\n\t\tWRITE_COEF(0x6b, 0xe429),\n\t\tWRITE_COEF(0x76, 0x0008),\n\t\tWRITE_COEF(0x18, 0x7388),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0293[] = {\n\t\tWRITE_COEF(0x45, 0xe429), /* Set to omtp type */\n\t\tUPDATE_COEF(0x10, 7<<8, 7<<8), /* SET Line1 JD to 1 */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0688[] = {\n\t\tWRITE_COEF(0x11, 0x0001),\n\t\tWRITE_COEF(0x15, 0x0d50),\n\t\tWRITE_COEF(0xc3, 0x0000),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0225[] = {\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x39<<10),\n\t\tUPDATE_COEF(0x63, 3<<14, 2<<14),\n\t\t{}\n\t};\n\n\tswitch (codec->core.vendor_id) {\n\tcase 0x10ec0255:\n\t\talc_process_coef_fw(codec, coef0255);\n\t\tbreak;\n\tcase 0x10ec0230:\n\tcase 0x10ec0236:\n\tcase 0x10ec0256:\n\t\talc_process_coef_fw(codec, coef0256);\n\t\tbreak;\n\tcase 0x10ec0234:\n\tcase 0x10ec0274:\n\tcase 0x10ec0294:\n\t\talc_write_coef_idx(codec, 0x45, 0xe689);\n\t\tbreak;\n\tcase 0x10ec0233:\n\tcase 0x10ec0283:\n\t\talc_process_coef_fw(codec, coef0233);\n\t\tbreak;\n\tcase 0x10ec0298:\n\t\talc_update_coef_idx(codec, 0x8e, 0x0070, 0x0010);/* Headset output enable */\n\t\talc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xe400);\n\t\tmsleep(300);\n\t\tbreak;\n\tcase 0x10ec0286:\n\tcase 0x10ec0288:\n\t\talc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xe400);\n\t\tmsleep(300);\n\t\talc_process_coef_fw(codec, coef0288);\n\t\tbreak;\n\tcase 0x10ec0292:\n\t\talc_process_coef_fw(codec, coef0292);\n\t\tbreak;\n\tcase 0x10ec0293:\n\t\talc_process_coef_fw(codec, coef0293);\n\t\tbreak;\n\tcase 0x10ec0668:\n\t\talc_process_coef_fw(codec, coef0688);\n\t\tbreak;\n\tcase 0x10ec0215:\n\tcase 0x10ec0225:\n\tcase 0x10ec0285:\n\tcase 0x10ec0295:\n\tcase 0x10ec0289:\n\tcase 0x10ec0299:\n\t\talc_process_coef_fw(codec, coef0225);\n\t\tbreak;\n\t}\n\tcodec_dbg(codec, \"Headset jack set to Nokia-style headset mode.\\n\");\n}",
        "static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tint quirk = ca0132_quirk(spec);\n\tunsigned int tmp;": "static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tint quirk = ca0132_quirk(spec);\n\tunsigned int tmp;\n\tint err;\n\n\t/* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */\n\tif (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0\n\t\t\t|| spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)\n\t\treturn 0;\n\n\t/* Set front L/R full range. Zero for full-range, one for redirection. */\n\ttmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;\n\terr = dspio_set_uint_param(codec, 0x96,\n\t\t\tSPEAKER_FULL_RANGE_FRONT_L_R, tmp);\n\tif (err < 0)\n\t\treturn err;\n\n\t/* When setting full-range rear, both rear and center/lfe are set. */\n\ttmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;\n\terr = dspio_set_uint_param(codec, 0x96,\n\t\t\tSPEAKER_FULL_RANGE_CENTER_LFE, tmp);\n\tif (err < 0)\n\t\treturn err;\n\n\terr = dspio_set_uint_param(codec, 0x96,\n\t\t\tSPEAKER_FULL_RANGE_REAR_L_R, tmp);\n\tif (err < 0)\n\t\treturn err;\n\n\t/*\n\t * Only the AE series cards set this value when setting full-range,\n\t * and it's always 1.0f.\n\t */\n\tif (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {\n\t\terr = dspio_set_uint_param(codec, 0x96,\n\t\t\t\tSPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}",
        "static int niu_init_rx_channels(struct niu *np)\n{\n\tunsigned long flags;\n\tu64 seed = jiffies_64;\n\tint err, i;": "static int niu_init_rx_channels(struct niu *np)\n{\n\tunsigned long flags;\n\tu64 seed = jiffies_64;\n\tint err, i;\n\n\tniu_lock_parent(np, flags);\n\tnw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);\n\tnw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));\n\tniu_unlock_parent(np, flags);\n\n\t/* XXX RXDMA 32bit mode? XXX */\n\n\tniu_init_rdc_groups(np);\n\tniu_init_drr_weight(np);\n\n\terr = niu_init_hostinfo(np);\n\tif (err)\n\t\treturn err;\n\n\tfor (i = 0; i < np->num_rx_rings; i++) {\n\t\tstruct rx_ring_info *rp = &np->rx_rings[i];\n\n\t\terr = niu_init_one_rx_channel(np, rp);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}",
        "static int io_provide_buffers(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_provide_buf *p = &req->pbuf;\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_buffer_list *bl;": "static int io_provide_buffers(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_provide_buf *p = &req->pbuf;\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_buffer_list *bl;\n\tint ret = 0;\n\n\tio_ring_submit_lock(ctx, issue_flags);\n\n\tif (unlikely(p->bgid < BGID_ARRAY && !ctx->io_bl)) {\n\t\tret = io_init_bl_list(ctx);\n\t\tif (ret)\n\t\t\tgoto err;\n\t}\n\n\tbl = io_buffer_get_list(ctx, p->bgid);\n\tif (unlikely(!bl)) {\n\t\tbl = kzalloc(sizeof(*bl), GFP_KERNEL);\n\t\tif (!bl) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto err;\n\t\t}\n\t\tINIT_LIST_HEAD(&bl->buf_list);\n\t\tret = io_buffer_add_list(ctx, bl, p->bgid);\n\t\tif (ret) {\n\t\t\tkfree(bl);\n\t\t\tgoto err;\n\t\t}\n\t}\n\t/* can't add buffers via this command for a mapped buffer ring */\n\tif (bl->buf_nr_pages) {\n\t\tret = -EINVAL;\n\t\tgoto err;\n\t}\n\n\tret = io_add_buffers(ctx, p, bl);\nerr:\n\tif (ret < 0)\n\t\treq_set_fail(req);\n\t/* complete before unlock, IOPOLL may need the lock */\n\t__io_req_complete(req, issue_flags, ret, 0);\n\tio_ring_submit_unlock(ctx, issue_flags);\n\treturn 0;\n}",
        "static void AtaPlay(void)\n{\n\t/* ++TeSche: Note that write_sq.active is no longer just a flag but\n\t * holds the number of frames the DMA is currently programmed for\n\t * instead, may be 0, 1 (currently being played) or 2 (pre-programmed).": "static void AtaPlay(void)\n{\n\t/* ++TeSche: Note that write_sq.active is no longer just a flag but\n\t * holds the number of frames the DMA is currently programmed for\n\t * instead, may be 0, 1 (currently being played) or 2 (pre-programmed).\n\t *\n\t * Changes done to write_sq.count and write_sq.active are a bit more\n\t * subtle again so now I must admit I also prefer disabling the irq\n\t * here rather than considering all possible situations. But the point\n\t * is that disabling the irq doesn't have any bad influence on this\n\t * version of the driver as we benefit from having pre-programmed the\n\t * DMA wherever possible: There's no need to reload the DMA at the\n\t * exact time of an interrupt but only at some time while the\n\t * pre-programmed frame is playing!\n\t */\n\tatari_disable_irq(IRQ_MFP_TIMA);\n\n\tif (write_sq.active == 2 ||\t/* DMA is 'full' */\n\t    write_sq.count <= 0) {\t/* nothing to do */\n\t\tatari_enable_irq(IRQ_MFP_TIMA);\n\t\treturn;\n\t}\n\n\tif (write_sq.active == 0) {\n\t\t/* looks like there's nothing 'in' the DMA yet, so try\n\t\t * to put two frames into it (at least one is available).\n\t\t */\n\t\tif (write_sq.count == 1 &&\n\t\t    write_sq.rear_size < write_sq.block_size &&\n\t\t    !write_sq.syncing) {\n\t\t\t/* hmmm, the only existing frame is not\n\t\t\t * yet filled and we're not syncing?\n\t\t\t */\n\t\t\tatari_enable_irq(IRQ_MFP_TIMA);\n\t\t\treturn;\n\t\t}\n\t\tAtaPlayNextFrame(1);\n\t\tif (write_sq.count == 1) {\n\t\t\t/* no more frames */\n\t\t\tatari_enable_irq(IRQ_MFP_TIMA);\n\t\t\treturn;\n\t\t}\n\t\tif (write_sq.count == 2 &&\n\t\t    write_sq.rear_size < write_sq.block_size &&\n\t\t    !write_sq.syncing) {\n\t\t\t/* hmmm, there were two frames, but the second\n\t\t\t * one is not yet filled and we're not syncing?\n\t\t\t */\n\t\t\tatari_enable_irq(IRQ_MFP_TIMA);\n\t\t\treturn;\n\t\t}\n\t\tAtaPlayNextFrame(2);\n\t} else {\n\t\t/* there's already a frame being played so we may only stuff\n\t\t * one new into the DMA, but even if this may be the last\n\t\t * frame existing the previous one is still on write_sq.count.\n\t\t */\n\t\tif (write_sq.count == 2 &&\n\t\t    write_sq.rear_size < write_sq.block_size &&\n\t\t    !write_sq.syncing) {\n\t\t\t/* hmmm, the only existing frame is not\n\t\t\t * yet filled and we're not syncing?\n\t\t\t */\n\t\t\tatari_enable_irq(IRQ_MFP_TIMA);\n\t\t\treturn;\n\t\t}\n\t\tAtaPlayNextFrame(2);\n\t}\n\tatari_enable_irq(IRQ_MFP_TIMA);\n}",
        "static void guest_code_initial(void)\n{\n\t/* set several CRs to \"safe\" value */\n\tunsigned long cr2_59 = 0x10;\t/* enable guarded storage */\n\tunsigned long cr8_63 = 0x1;\t/* monitor mask = 1 */": "static void guest_code_initial(void)\n{\n\t/* set several CRs to \"safe\" value */\n\tunsigned long cr2_59 = 0x10;\t/* enable guarded storage */\n\tunsigned long cr8_63 = 0x1;\t/* monitor mask = 1 */\n\tunsigned long cr10 = 1;\t\t/* PER START */\n\tunsigned long cr11 = -1;\t/* PER END */\n\n\n\t/* Dirty registers */\n\tasm volatile (\n\t\t\"\tlghi\t2,0x11\\n\"\t/* Round toward 0 */\n\t\t\"\tsfpc\t2\\n\"\t\t/* set fpc to !=0 */\n\t\t\"\tlctlg\t2,2,%0\\n\"\n\t\t\"\tlctlg\t8,8,%1\\n\"\n\t\t\"\tlctlg\t10,10,%2\\n\"\n\t\t\"\tlctlg\t11,11,%3\\n\"\n\t\t/* now clobber some general purpose regs */\n\t\t\"\tllihh\t0,0xffff\\n\"\n\t\t\"\tllihl\t1,0x5555\\n\"\n\t\t\"\tllilh\t2,0xaaaa\\n\"\n\t\t\"\tllill\t3,0x0000\\n\"\n\t\t/* now clobber a floating point reg */\n\t\t\"\tlghi\t4,0x1\\n\"\n\t\t\"\tcdgbr\t0,4\\n\"\n\t\t/* now clobber an access reg */\n\t\t\"\tsar\t9,4\\n\"\n\t\t/* We embed diag 501 here to control register content */\n\t\t\"\tdiag 0,0,0x501\\n\"\n\t\t:\n\t\t: \"m\" (cr2_59), \"m\" (cr8_63), \"m\" (cr10), \"m\" (cr11)\n\t\t/* no clobber list as this should not return */\n\t\t);\n}",
        "static bool ssh_rtl_cancel_nonpending(struct ssh_request *r)\n{\n\tstruct ssh_rtl *rtl;\n\tunsigned long flags, fixed;\n\tbool remove;": "static bool ssh_rtl_cancel_nonpending(struct ssh_request *r)\n{\n\tstruct ssh_rtl *rtl;\n\tunsigned long flags, fixed;\n\tbool remove;\n\n\t/*\n\t * Handle unsubmitted request: Try to mark the packet as locked,\n\t * expecting the state to be zero (i.e. unsubmitted). Note that, if\n\t * setting the state worked, we might still be adding the packet to the\n\t * queue in a currently executing submit call. In that case, however,\n\t * ptl reference must have been set previously, as locked is checked\n\t * after setting ptl. Furthermore, when the ptl reference is set, the\n\t * submission process is guaranteed to have entered the critical\n\t * section. Thus only if we successfully locked this request and ptl is\n\t * NULL, we have successfully removed the request, i.e. we are\n\t * guaranteed that, due to the \"locked\" check in ssh_rtl_submit(), the\n\t * packet will never be added. Otherwise, we need to try and grab it\n\t * from the queue, where we are now guaranteed that the packet is or has\n\t * been due to the critical section.\n\t *\n\t * Note that if the cmpxchg() fails, we are guaranteed that ptl has\n\t * been set and is non-NULL, as states can only be nonzero after this\n\t * has been set. Also note that we need to fetch the static (type)\n\t * flags to ensure that they don't cause the cmpxchg() to fail.\n\t */\n\tfixed = READ_ONCE(r->state) & SSH_REQUEST_FLAGS_TY_MASK;\n\tflags = cmpxchg(&r->state, fixed, SSH_REQUEST_SF_LOCKED_BIT);\n\n\t/*\n\t * Force correct ordering with regards to state and ptl reference access\n\t * to safe-guard cancellation to concurrent submission against a\n\t * lost-update problem. First try to exchange state, then also check\n\t * ptl if that worked. This barrier is paired with the\n\t * one in ssh_rtl_submit().\n\t */\n\tsmp_mb__after_atomic();\n\n\tif (flags == fixed && !READ_ONCE(r->packet.ptl)) {\n\t\tif (test_and_set_bit(SSH_REQUEST_SF_COMPLETED_BIT, &r->state))\n\t\t\treturn true;\n\n\t\tssh_rtl_complete_with_status(r, -ECANCELED);\n\t\treturn true;\n\t}\n\n\trtl = ssh_request_rtl(r);\n\tspin_lock(&rtl->queue.lock);\n\n\t/*\n\t * Note: 1) Requests cannot be re-submitted. 2) If a request is\n\t * queued, it cannot be \"transmitting\"/\"pending\" yet. Thus, if we\n\t * successfully remove the request here, we have removed all its\n\t * occurrences in the system.\n\t */\n\n\tremove = test_and_clear_bit(SSH_REQUEST_SF_QUEUED_BIT, &r->state);\n\tif (!remove) {\n\t\tspin_unlock(&rtl->queue.lock);\n\t\treturn false;\n\t}\n\n\tset_bit(SSH_REQUEST_SF_LOCKED_BIT, &r->state);\n\tlist_del(&r->node);\n\n\tspin_unlock(&rtl->queue.lock);\n\n\tssh_request_put(r);\t/* Drop reference obtained from queue. */\n\n\tif (test_and_set_bit(SSH_REQUEST_SF_COMPLETED_BIT, &r->state))\n\t\treturn true;\n\n\tssh_rtl_complete_with_status(r, -ECANCELED);\n\treturn true;\n}",
        "static void cal_camerarx_lane_config(struct cal_camerarx *phy)\n{\n\tu32 val = cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));\n\tu32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;\n\tu32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;": "static void cal_camerarx_lane_config(struct cal_camerarx *phy)\n{\n\tu32 val = cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));\n\tu32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;\n\tu32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;\n\tstruct v4l2_mbus_config_mipi_csi2 *mipi_csi2 =\n\t\t&phy->endpoint.bus.mipi_csi2;\n\tint lane;\n\n\tcal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);\n\tcal_set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);\n\tfor (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {\n\t\t/*\n\t\t * Every lane are one nibble apart starting with the\n\t\t * clock followed by the data lanes so shift masks by 4.\n\t\t */\n\t\tlane_mask <<= 4;\n\t\tpolarity_mask <<= 4;\n\t\tcal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);\n\t\tcal_set_field(&val, mipi_csi2->lane_polarities[lane + 1],\n\t\t\t      polarity_mask);\n\t}\n\n\tcal_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val);\n\tphy_dbg(3, phy, \"CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\\n\",\n\t\tphy->instance, val);\n}",
        "static int runtest_unaligned_512bytes(void)\n{\n\tunsigned long long breaks = 0;\n\tint fd;\n\tchar *desc = \"Process specific, 512 bytes, unaligned\";": "static int runtest_unaligned_512bytes(void)\n{\n\tunsigned long long breaks = 0;\n\tint fd;\n\tchar *desc = \"Process specific, 512 bytes, unaligned\";\n\t__u64 addr = (__u64)&c + 8;\n\tsize_t res;\n\n\tfd = perf_process_event_open(HW_BREAKPOINT_RW, addr, 512);\n\tif (fd < 0) {\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tioctl(fd, PERF_EVENT_IOC_RESET);\n\tioctl(fd, PERF_EVENT_IOC_ENABLE);\n\tmulti_dawr_workload();\n\tioctl(fd, PERF_EVENT_IOC_DISABLE);\n\n\tres = read(fd, &breaks, sizeof(breaks));\n\tassert(res == sizeof(unsigned long long));\n\n\tclose(fd);\n\n\tif (breaks != 2) {\n\t\tprintf(\"FAILED: %s: %lld != 2\\n\", desc, breaks);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static int alloc_try_nid_top_down_reserved_no_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;": "static int alloc_try_nid_top_down_reserved_no_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\tstruct region r1, r2;\n\n\tphys_addr_t r3_size = SZ_256;\n\tphys_addr_t gap_size = SMP_CACHE_BYTES;\n\tphys_addr_t total_size;\n\tphys_addr_t max_addr;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2;\n\tr1.size = SMP_CACHE_BYTES;\n\n\tr2.size = SZ_128;\n\tr2.base = r1.base - (r2.size + gap_size);\n\n\ttotal_size = r1.size + r2.size + r3_size;\n\tmin_addr = r2.base + r2.size;\n\tmax_addr = r1.base;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn1->size == r1.size);\n\tassert(rgn1->base == r1.base);\n\n\tassert(rgn2->size == r2.size + r3_size);\n\tassert(rgn2->base == r2.base - r3_size);\n\n\tassert(memblock.reserved.cnt == 2);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static int cio2_hw_init(struct cio2_device *cio2, struct cio2_queue *q)\n{\n\tstatic const int NUM_VCS = 4;\n\tstatic const int SID;\t/* Stream id */\n\tstatic const int ENTRY;": "static int cio2_hw_init(struct cio2_device *cio2, struct cio2_queue *q)\n{\n\tstatic const int NUM_VCS = 4;\n\tstatic const int SID;\t/* Stream id */\n\tstatic const int ENTRY;\n\tstatic const int FBPT_WIDTH = DIV_ROUND_UP(CIO2_MAX_LOPS,\n\t\t\t\t\tCIO2_FBPT_SUBENTRY_UNIT);\n\tconst u32 num_buffers1 = CIO2_MAX_BUFFERS - 1;\n\tconst struct ipu3_cio2_fmt *fmt;\n\tvoid __iomem *const base = cio2->base;\n\tu8 lanes, csi2bus = q->csi2.port;\n\tu8 sensor_vc = SENSOR_VIR_CH_DFLT;\n\tstruct cio2_csi2_timing timing;\n\tint i, r;\n\n\tfmt = cio2_find_format(NULL, &q->subdev_fmt.code);\n\tif (!fmt)\n\t\treturn -EINVAL;\n\n\tlanes = q->csi2.lanes;\n\n\tr = cio2_csi2_calc_timing(cio2, q, &timing, fmt->bpp, lanes);\n\tif (r)\n\t\treturn r;\n\n\twritel(timing.clk_termen, q->csi_rx_base +\n\t\tCIO2_REG_CSIRX_DLY_CNT_TERMEN(CIO2_CSIRX_DLY_CNT_CLANE_IDX));\n\twritel(timing.clk_settle, q->csi_rx_base +\n\t\tCIO2_REG_CSIRX_DLY_CNT_SETTLE(CIO2_CSIRX_DLY_CNT_CLANE_IDX));\n\n\tfor (i = 0; i < lanes; i++) {\n\t\twritel(timing.dat_termen, q->csi_rx_base +\n\t\t\tCIO2_REG_CSIRX_DLY_CNT_TERMEN(i));\n\t\twritel(timing.dat_settle, q->csi_rx_base +\n\t\t\tCIO2_REG_CSIRX_DLY_CNT_SETTLE(i));\n\t}\n\n\twritel(CIO2_PBM_WMCTRL1_MIN_2CK |\n\t       CIO2_PBM_WMCTRL1_MID1_2CK |\n\t       CIO2_PBM_WMCTRL1_MID2_2CK, base + CIO2_REG_PBM_WMCTRL1);\n\twritel(CIO2_PBM_WMCTRL2_HWM_2CK << CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT |\n\t       CIO2_PBM_WMCTRL2_LWM_2CK << CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT |\n\t       CIO2_PBM_WMCTRL2_OBFFWM_2CK <<\n\t       CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT |\n\t       CIO2_PBM_WMCTRL2_TRANSDYN << CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT |\n\t       CIO2_PBM_WMCTRL2_OBFF_MEM_EN, base + CIO2_REG_PBM_WMCTRL2);\n\twritel(CIO2_PBM_ARB_CTRL_LANES_DIV <<\n\t       CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT |\n\t       CIO2_PBM_ARB_CTRL_LE_EN |\n\t       CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN <<\n\t       CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT |\n\t       CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP <<\n\t       CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT,\n\t       base + CIO2_REG_PBM_ARB_CTRL);\n\twritel(CIO2_CSIRX_STATUS_DLANE_HS_MASK,\n\t       q->csi_rx_base + CIO2_REG_CSIRX_STATUS_DLANE_HS);\n\twritel(CIO2_CSIRX_STATUS_DLANE_LP_MASK,\n\t       q->csi_rx_base + CIO2_REG_CSIRX_STATUS_DLANE_LP);\n\n\twritel(CIO2_FB_HPLL_FREQ, base + CIO2_REG_FB_HPLL_FREQ);\n\twritel(CIO2_ISCLK_RATIO, base + CIO2_REG_ISCLK_RATIO);\n\n\t/* Configure MIPI backend */\n\tfor (i = 0; i < NUM_VCS; i++)\n\t\twritel(1, q->csi_rx_base + CIO2_REG_MIPIBE_SP_LUT_ENTRY(i));\n\n\t/* There are 16 short packet LUT entry */\n\tfor (i = 0; i < 16; i++)\n\t\twritel(CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD,\n\t\t       q->csi_rx_base + CIO2_REG_MIPIBE_LP_LUT_ENTRY(i));\n\twritel(CIO2_MIPIBE_GLOBAL_LUT_DISREGARD,\n\t       q->csi_rx_base + CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD);\n\n\twritel(CIO2_INT_EN_EXT_IE_MASK, base + CIO2_REG_INT_EN_EXT_IE);\n\twritel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_MASK);\n\twritel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_ENABLE);\n\twritel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_EDGE);\n\twritel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE);\n\twritel(CIO2_INT_EN_EXT_OE_MASK, base + CIO2_REG_INT_EN_EXT_OE);\n\n\twritel(CIO2_REG_INT_EN_IRQ | CIO2_INT_IOC(CIO2_DMA_CHAN) |\n\t       CIO2_REG_INT_EN_IOS(CIO2_DMA_CHAN),\n\t       base + CIO2_REG_INT_EN);\n\n\twritel((CIO2_PXM_PXF_FMT_CFG_BPP_10 | CIO2_PXM_PXF_FMT_CFG_PCK_64B)\n\t       << CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT,\n\t       base + CIO2_REG_PXM_PXF_FMT_CFG0(csi2bus));\n\twritel(SID << CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT |\n\t       sensor_vc << CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT |\n\t       fmt->mipicode << CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT,\n\t       q->csi_rx_base + CIO2_REG_MIPIBE_LP_LUT_ENTRY(ENTRY));\n\twritel(0, q->csi_rx_base + CIO2_REG_MIPIBE_COMP_FORMAT(sensor_vc));\n\twritel(0, q->csi_rx_base + CIO2_REG_MIPIBE_FORCE_RAW8);\n\twritel(0, base + CIO2_REG_PXM_SID2BID0(csi2bus));\n\n\twritel(lanes, q->csi_rx_base + CIO2_REG_CSIRX_NOF_ENABLED_LANES);\n\twritel(CIO2_CGC_PRIM_TGE |\n\t       CIO2_CGC_SIDE_TGE |\n\t       CIO2_CGC_XOSC_TGE |\n\t       CIO2_CGC_D3I3_TGE |\n\t       CIO2_CGC_CSI2_INTERFRAME_TGE |\n\t       CIO2_CGC_CSI2_PORT_DCGE |\n\t       CIO2_CGC_SIDE_DCGE |\n\t       CIO2_CGC_PRIM_DCGE |\n\t       CIO2_CGC_ROSC_DCGE |\n\t       CIO2_CGC_XOSC_DCGE |\n\t       CIO2_CGC_CLKGATE_HOLDOFF << CIO2_CGC_CLKGATE_HOLDOFF_SHIFT |\n\t       CIO2_CGC_CSI_CLKGATE_HOLDOFF\n\t       << CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT, base + CIO2_REG_CGC);\n\twritel(CIO2_LTRCTRL_LTRDYNEN, base + CIO2_REG_LTRCTRL);\n\twritel(CIO2_LTRVAL0_VAL << CIO2_LTRVAL02_VAL_SHIFT |\n\t       CIO2_LTRVAL0_SCALE << CIO2_LTRVAL02_SCALE_SHIFT |\n\t       CIO2_LTRVAL1_VAL << CIO2_LTRVAL13_VAL_SHIFT |\n\t       CIO2_LTRVAL1_SCALE << CIO2_LTRVAL13_SCALE_SHIFT,\n\t       base + CIO2_REG_LTRVAL01);\n\twritel(CIO2_LTRVAL2_VAL << CIO2_LTRVAL02_VAL_SHIFT |\n\t       CIO2_LTRVAL2_SCALE << CIO2_LTRVAL02_SCALE_SHIFT |\n\t       CIO2_LTRVAL3_VAL << CIO2_LTRVAL13_VAL_SHIFT |\n\t       CIO2_LTRVAL3_SCALE << CIO2_LTRVAL13_SCALE_SHIFT,\n\t       base + CIO2_REG_LTRVAL23);\n\n\tfor (i = 0; i < CIO2_NUM_DMA_CHAN; i++) {\n\t\twritel(0, base + CIO2_REG_CDMABA(i));\n\t\twritel(0, base + CIO2_REG_CDMAC0(i));\n\t\twritel(0, base + CIO2_REG_CDMAC1(i));\n\t}\n\n\t/* Enable DMA */\n\twritel(PFN_DOWN(q->fbpt_bus_addr), base + CIO2_REG_CDMABA(CIO2_DMA_CHAN));\n\n\twritel(num_buffers1 << CIO2_CDMAC0_FBPT_LEN_SHIFT |\n\t       FBPT_WIDTH << CIO2_CDMAC0_FBPT_WIDTH_SHIFT |\n\t       CIO2_CDMAC0_DMA_INTR_ON_FE |\n\t       CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL |\n\t       CIO2_CDMAC0_DMA_EN |\n\t       CIO2_CDMAC0_DMA_INTR_ON_FS |\n\t       CIO2_CDMAC0_DMA_HALTED, base + CIO2_REG_CDMAC0(CIO2_DMA_CHAN));\n\n\twritel(1 << CIO2_CDMAC1_LINENUMUPDATE_SHIFT,\n\t       base + CIO2_REG_CDMAC1(CIO2_DMA_CHAN));\n\n\twritel(0, base + CIO2_REG_PBM_FOPN_ABORT);\n\n\twritel(CIO2_PXM_FRF_CFG_CRC_TH << CIO2_PXM_FRF_CFG_CRC_TH_SHIFT |\n\t       CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR |\n\t       CIO2_PXM_FRF_CFG_MSK_ECC_RE |\n\t       CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE,\n\t       base + CIO2_REG_PXM_FRF_CFG(q->csi2.port));\n\n\t/* Clear interrupts */\n\twritel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_CLEAR);\n\twritel(~0, base + CIO2_REG_INT_STS_EXT_OE);\n\twritel(~0, base + CIO2_REG_INT_STS_EXT_IE);\n\twritel(~0, base + CIO2_REG_INT_STS);\n\n\t/* Enable devices, starting from the last device in the pipe */\n\twritel(1, q->csi_rx_base + CIO2_REG_MIPIBE_ENABLE);\n\twritel(1, q->csi_rx_base + CIO2_REG_CSIRX_ENABLE);\n\n\treturn 0;\n}",
        "static int __init mem_cgroup_init(void)\n{\n\tint cpu, node;\n\n\t/*": "static int __init mem_cgroup_init(void)\n{\n\tint cpu, node;\n\n\t/*\n\t * Currently s32 type (can refer to struct batched_lruvec_stat) is\n\t * used for per-memcg-per-cpu caching of per-node statistics. In order\n\t * to work fine, we should make sure that the overfill threshold can't\n\t * exceed S32_MAX / PAGE_SIZE.\n\t */\n\tBUILD_BUG_ON(MEMCG_CHARGE_BATCH > S32_MAX / PAGE_SIZE);\n\n\tcpuhp_setup_state_nocalls(CPUHP_MM_MEMCQ_DEAD, \"mm/memctrl:dead\", NULL,\n\t\t\t\t  memcg_hotplug_cpu_dead);\n\n\tfor_each_possible_cpu(cpu)\n\t\tINIT_WORK(&per_cpu_ptr(&memcg_stock, cpu)->work,\n\t\t\t  drain_local_stock);\n\n\tfor_each_node(node) {\n\t\tstruct mem_cgroup_tree_per_node *rtpn;\n\n\t\trtpn = kzalloc_node(sizeof(*rtpn), GFP_KERNEL,\n\t\t\t\t    node_online(node) ? node : NUMA_NO_NODE);\n\n\t\trtpn->rb_root = RB_ROOT;\n\t\trtpn->rb_rightmost = NULL;\n\t\tspin_lock_init(&rtpn->lock);\n\t\tsoft_limit_tree.rb_tree_per_node[node] = rtpn;\n\t}\n\n\treturn 0;\n}",
        "static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)\n{\n\tint num_bytes = num_words * dspi->oper_word_size;\n\tu16 tx_cmd = dspi->tx_cmd;\n": "static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)\n{\n\tint num_bytes = num_words * dspi->oper_word_size;\n\tu16 tx_cmd = dspi->tx_cmd;\n\n\t/*\n\t * If the PCS needs to de-assert (i.e. we're at the end of the buffer\n\t * and cs_change does not want the PCS to stay on), then we need a new\n\t * PUSHR command, since this one (for the body of the buffer)\n\t * necessarily has the CONT bit set.\n\t * So send one word less during this go, to force a split and a command\n\t * with a single word next time, when CONT will be unset.\n\t */\n\tif (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)\n\t\ttx_cmd |= SPI_PUSHR_CMD_EOQ;\n\n\t/* Update CTARE */\n\tregmap_write(dspi->regmap, SPI_CTARE(0),\n\t\t     SPI_FRAME_EBITS(dspi->oper_bits_per_word) |\n\t\t     SPI_CTARE_DTCP(num_words));\n\n\t/*\n\t * Write the CMD FIFO entry first, and then the two\n\t * corresponding TX FIFO entries (or one...).\n\t */\n\tdspi_pushr_cmd_write(dspi, tx_cmd);\n\n\t/* Fill TX FIFO with as many transfers as possible */\n\twhile (num_words--) {\n\t\tu32 data = dspi_pop_tx(dspi);\n\n\t\tdspi_pushr_txdata_write(dspi, data & 0xFFFF);\n\t\tif (dspi->oper_bits_per_word > 16)\n\t\t\tdspi_pushr_txdata_write(dspi, data >> 16);\n\t}\n}",
        "static int timerlat_main(void *data)\n{\n\tstruct osnoise_variables *osn_var = this_cpu_osn_var();\n\tstruct timerlat_variables *tlat = this_cpu_tmr_var();\n\tstruct timerlat_sample s;": "static int timerlat_main(void *data)\n{\n\tstruct osnoise_variables *osn_var = this_cpu_osn_var();\n\tstruct timerlat_variables *tlat = this_cpu_tmr_var();\n\tstruct timerlat_sample s;\n\tstruct sched_param sp;\n\tu64 now, diff;\n\n\t/*\n\t * Make the thread RT, that is how cyclictest is usually used.\n\t */\n\tsp.sched_priority = DEFAULT_TIMERLAT_PRIO;\n\tsched_setscheduler_nocheck(current, SCHED_FIFO, &sp);\n\n\ttlat->count = 0;\n\ttlat->tracing_thread = false;\n\n\thrtimer_init(&tlat->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS_PINNED_HARD);\n\ttlat->timer.function = timerlat_irq;\n\ttlat->kthread = current;\n\tosn_var->pid = current->pid;\n\t/*\n\t * Anotate the arrival time.\n\t */\n\ttlat->abs_period = hrtimer_cb_get_time(&tlat->timer);\n\n\twait_next_period(tlat);\n\n\tosn_var->sampling = 1;\n\n\twhile (!kthread_should_stop()) {\n\t\tnow = ktime_to_ns(hrtimer_cb_get_time(&tlat->timer));\n\t\tdiff = now - tlat->abs_period;\n\n\t\ts.seqnum = tlat->count;\n\t\ts.timer_latency = diff;\n\t\ts.context = THREAD_CONTEXT;\n\n\t\ttrace_timerlat_sample(&s);\n\n\t\ttimerlat_dump_stack(time_to_us(diff));\n\n\t\ttlat->tracing_thread = false;\n\t\tif (osnoise_data.stop_tracing_total)\n\t\t\tif (time_to_us(diff) >= osnoise_data.stop_tracing_total)\n\t\t\t\tosnoise_stop_tracing();\n\n\t\twait_next_period(tlat);\n\t}\n\n\thrtimer_cancel(&tlat->timer);\n\treturn 0;\n}",
        "static int add_host_bridge_dport(struct device *match, void *arg)\n{\n\tacpi_status status;\n\tunsigned long long uid;\n\tstruct cxl_dport *dport;": "static int add_host_bridge_dport(struct device *match, void *arg)\n{\n\tacpi_status status;\n\tunsigned long long uid;\n\tstruct cxl_dport *dport;\n\tstruct cxl_chbs_context ctx;\n\tstruct cxl_port *root_port = arg;\n\tstruct device *host = root_port->dev.parent;\n\tstruct acpi_device *bridge = to_cxl_host_bridge(host, match);\n\n\tif (!bridge)\n\t\treturn 0;\n\n\tstatus = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL,\n\t\t\t\t       &uid);\n\tif (status != AE_OK) {\n\t\tdev_err(host, \"unable to retrieve _UID of %s\\n\",\n\t\t\tdev_name(match));\n\t\treturn -ENODEV;\n\t}\n\n\tctx = (struct cxl_chbs_context) {\n\t\t.dev = host,\n\t\t.uid = uid,\n\t};\n\tacpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);\n\n\tif (ctx.chbcr == 0) {\n\t\tdev_warn(host, \"No CHBS found for Host Bridge: %s\\n\",\n\t\t\t dev_name(match));\n\t\treturn 0;\n\t}\n\n\tdport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);\n\tif (IS_ERR(dport)) {\n\t\tdev_err(host, \"failed to add downstream port: %s\\n\",\n\t\t\tdev_name(match));\n\t\treturn PTR_ERR(dport);\n\t}\n\tdev_dbg(host, \"add dport%llu: %s\\n\", uid, dev_name(match));\n\treturn 0;\n}",
        "static unsigned int tcpm_pd_select_pps_apdo(struct tcpm_port *port)\n{\n\tunsigned int i, j, max_mw = 0, max_mv = 0;\n\tunsigned int min_src_mv, max_src_mv, src_ma, src_mw;\n\tunsigned int min_snk_mv, max_snk_mv;": "static unsigned int tcpm_pd_select_pps_apdo(struct tcpm_port *port)\n{\n\tunsigned int i, j, max_mw = 0, max_mv = 0;\n\tunsigned int min_src_mv, max_src_mv, src_ma, src_mw;\n\tunsigned int min_snk_mv, max_snk_mv;\n\tunsigned int max_op_mv;\n\tu32 pdo, src, snk;\n\tunsigned int src_pdo = 0, snk_pdo = 0;\n\n\t/*\n\t * Select the source PPS APDO providing the most power while staying\n\t * within the board's limits. We skip the first PDO as this is always\n\t * 5V 3A.\n\t */\n\tfor (i = 1; i < port->nr_source_caps; ++i) {\n\t\tpdo = port->source_caps[i];\n\n\t\tswitch (pdo_type(pdo)) {\n\t\tcase PDO_TYPE_APDO:\n\t\t\tif (pdo_apdo_type(pdo) != APDO_TYPE_PPS) {\n\t\t\t\ttcpm_log(port, \"Not PPS APDO (source), ignoring\");\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tmin_src_mv = pdo_pps_apdo_min_voltage(pdo);\n\t\t\tmax_src_mv = pdo_pps_apdo_max_voltage(pdo);\n\t\t\tsrc_ma = pdo_pps_apdo_max_current(pdo);\n\t\t\tsrc_mw = (src_ma * max_src_mv) / 1000;\n\n\t\t\t/*\n\t\t\t * Now search through the sink PDOs to find a matching\n\t\t\t * PPS APDO. Again skip the first sink PDO as this will\n\t\t\t * always be 5V 3A.\n\t\t\t */\n\t\t\tfor (j = 1; j < port->nr_snk_pdo; j++) {\n\t\t\t\tpdo = port->snk_pdo[j];\n\n\t\t\t\tswitch (pdo_type(pdo)) {\n\t\t\t\tcase PDO_TYPE_APDO:\n\t\t\t\t\tif (pdo_apdo_type(pdo) != APDO_TYPE_PPS) {\n\t\t\t\t\t\ttcpm_log(port,\n\t\t\t\t\t\t\t \"Not PPS APDO (sink), ignoring\");\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\tmin_snk_mv =\n\t\t\t\t\t\tpdo_pps_apdo_min_voltage(pdo);\n\t\t\t\t\tmax_snk_mv =\n\t\t\t\t\t\tpdo_pps_apdo_max_voltage(pdo);\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\ttcpm_log(port,\n\t\t\t\t\t\t \"Not APDO type (sink), ignoring\");\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif (min_src_mv <= max_snk_mv &&\n\t\t\t\t    max_src_mv >= min_snk_mv) {\n\t\t\t\t\tmax_op_mv = min(max_src_mv, max_snk_mv);\n\t\t\t\t\tsrc_mw = (max_op_mv * src_ma) / 1000;\n\t\t\t\t\t/* Prefer higher voltages if available */\n\t\t\t\t\tif ((src_mw == max_mw &&\n\t\t\t\t\t     max_op_mv > max_mv) ||\n\t\t\t\t\t    src_mw > max_mw) {\n\t\t\t\t\t\tsrc_pdo = i;\n\t\t\t\t\t\tsnk_pdo = j;\n\t\t\t\t\t\tmax_mw = src_mw;\n\t\t\t\t\t\tmax_mv = max_op_mv;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tbreak;\n\t\tdefault:\n\t\t\ttcpm_log(port, \"Not APDO type (source), ignoring\");\n\t\t\tcontinue;\n\t\t}\n\t}\n\n\tif (src_pdo) {\n\t\tsrc = port->source_caps[src_pdo];\n\t\tsnk = port->snk_pdo[snk_pdo];\n\n\t\tport->pps_data.req_min_volt = max(pdo_pps_apdo_min_voltage(src),\n\t\t\t\t\t\t  pdo_pps_apdo_min_voltage(snk));\n\t\tport->pps_data.req_max_volt = min(pdo_pps_apdo_max_voltage(src),\n\t\t\t\t\t\t  pdo_pps_apdo_max_voltage(snk));\n\t\tport->pps_data.req_max_curr = min_pps_apdo_current(src, snk);\n\t\tport->pps_data.req_out_volt = min(port->pps_data.req_max_volt,\n\t\t\t\t\t\t  max(port->pps_data.req_min_volt,\n\t\t\t\t\t\t      port->pps_data.req_out_volt));\n\t\tport->pps_data.req_op_curr = min(port->pps_data.req_max_curr,\n\t\t\t\t\t\t port->pps_data.req_op_curr);\n\t}\n\n\treturn src_pdo;\n}",
        "static int bpf_program_profiler__read(struct evsel *evsel)\n{\n\t// BPF_MAP_TYPE_PERCPU_ARRAY uses /sys/devices/system/cpu/possible\n\t// Sometimes possible > online, like on a Ryzen 3900X that has 24\n\t// threads but its possible showed 0-31 -acme": "static int bpf_program_profiler__read(struct evsel *evsel)\n{\n\t// BPF_MAP_TYPE_PERCPU_ARRAY uses /sys/devices/system/cpu/possible\n\t// Sometimes possible > online, like on a Ryzen 3900X that has 24\n\t// threads but its possible showed 0-31 -acme\n\tint num_cpu_bpf = libbpf_num_possible_cpus();\n\tstruct bpf_perf_event_value values[num_cpu_bpf];\n\tstruct bpf_counter *counter;\n\tstruct perf_counts_values *counts;\n\tint reading_map_fd;\n\t__u32 key = 0;\n\tint err, idx, bpf_cpu;\n\n\tif (list_empty(&evsel->bpf_counter_list))\n\t\treturn -EAGAIN;\n\n\tperf_cpu_map__for_each_idx(idx, evsel__cpus(evsel)) {\n\t\tcounts = perf_counts(evsel->counts, idx, 0);\n\t\tcounts->val = 0;\n\t\tcounts->ena = 0;\n\t\tcounts->run = 0;\n\t}\n\tlist_for_each_entry(counter, &evsel->bpf_counter_list, list) {\n\t\tstruct bpf_prog_profiler_bpf *skel = counter->skel;\n\n\t\tassert(skel != NULL);\n\t\treading_map_fd = bpf_map__fd(skel->maps.accum_readings);\n\n\t\terr = bpf_map_lookup_elem(reading_map_fd, &key, values);\n\t\tif (err) {\n\t\t\tpr_err(\"failed to read value\\n\");\n\t\t\treturn err;\n\t\t}\n\n\t\tfor (bpf_cpu = 0; bpf_cpu < num_cpu_bpf; bpf_cpu++) {\n\t\t\tidx = perf_cpu_map__idx(evsel__cpus(evsel),\n\t\t\t\t\t\t(struct perf_cpu){.cpu = bpf_cpu});\n\t\t\tif (idx == -1)\n\t\t\t\tcontinue;\n\t\t\tcounts = perf_counts(evsel->counts, idx, 0);\n\t\t\tcounts->val += values[bpf_cpu].counter;\n\t\t\tcounts->ena += values[bpf_cpu].enabled;\n\t\t\tcounts->run += values[bpf_cpu].running;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int set_var(struct fbtft_par *par)\n{\n\t/*\n\t * madctl - memory data access control\n\t *   rgb/bgr:": "static int set_var(struct fbtft_par *par)\n{\n\t/*\n\t * madctl - memory data access control\n\t *   rgb/bgr:\n\t *   1. mode selection pin srgb\n\t *\trgb h/w pin for color filter setting: 0=rgb, 1=bgr\n\t *   2. madctl rgb bit\n\t *\trgb-bgr order color filter panel: 0=rgb, 1=bgr\n\t */\n\tswitch (par->info->var.rotate) {\n\tcase 0:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  mx | my | (par->bgr << 3));\n\t\tbreak;\n\tcase 270:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  my | mv | (par->bgr << 3));\n\t\tbreak;\n\tcase 180:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  par->bgr << 3);\n\t\tbreak;\n\tcase 90:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  mx | mv | (par->bgr << 3));\n\t\tbreak;\n\t}\n\n\treturn 0;\n}",
        "static void atomisp_subdev_init_struct(struct atomisp_sub_device *asd)\n{\n\tv4l2_ctrl_s_ctrl(asd->run_mode, ATOMISP_RUN_MODE_STILL_CAPTURE);\n\tmemset(&asd->params.css_param, 0, sizeof(asd->params.css_param));\n\tasd->params.color_effect = V4L2_COLORFX_NONE;": "static void atomisp_subdev_init_struct(struct atomisp_sub_device *asd)\n{\n\tv4l2_ctrl_s_ctrl(asd->run_mode, ATOMISP_RUN_MODE_STILL_CAPTURE);\n\tmemset(&asd->params.css_param, 0, sizeof(asd->params.css_param));\n\tasd->params.color_effect = V4L2_COLORFX_NONE;\n\tasd->params.bad_pixel_en = true;\n\tasd->params.gdc_cac_en = false;\n\tasd->params.video_dis_en = false;\n\tasd->params.sc_en = false;\n\tasd->params.fpn_en = false;\n\tasd->params.xnr_en = false;\n\tasd->params.false_color = 0;\n\tasd->params.online_process = 1;\n\tasd->params.yuv_ds_en = 0;\n\t/* s3a grid not enabled for any pipe */\n\tasd->params.s3a_enabled_pipe = IA_CSS_PIPE_ID_NUM;\n\n\tasd->params.offline_parm.num_captures = 1;\n\tasd->params.offline_parm.skip_frames = 0;\n\tasd->params.offline_parm.offset = 0;\n\tasd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED;\n\t/* Add for channel */\n\tasd->input_curr = 0;\n\n\tasd->mipi_frame_size = 0;\n\tasd->copy_mode = false;\n\tasd->yuvpp_mode = false;\n\n\tasd->stream_prepared = false;\n\tasd->high_speed_mode = false;\n\tasd->sensor_array_res.height = 0;\n\tasd->sensor_array_res.width = 0;\n\tatomisp_css_init_struct(asd);\n}",
        "static void mlxsw_sp4_bf_key_shift_chunks(u8 chunk_count, char *output)\n{\n\t/* The chunks are suppoosed to be continuous, with no padding.\n\t * Since region ID and eRP ID use 14 bits, and not fully 2 bytes,\n\t * and in Spectrum-4 there is no padding, it is necessary to shift some": "static void mlxsw_sp4_bf_key_shift_chunks(u8 chunk_count, char *output)\n{\n\t/* The chunks are suppoosed to be continuous, with no padding.\n\t * Since region ID and eRP ID use 14 bits, and not fully 2 bytes,\n\t * and in Spectrum-4 there is no padding, it is necessary to shift some\n\t * chunks 2 bits right.\n\t */\n\tswitch (chunk_count) {\n\tcase 2:\n\t\t/* The chunks are copied as follow:\n\t\t * +-------------+-----------------+\n\t\t * | Chunk 0     |   Chunk 1       |\n\t\t * | IDs  | keys |(**) IDs  | keys |\n\t\t * +-------------+-----------------+\n\t\t * In (**), there are two unused bits, therefore, chunk 0 needs\n\t\t * to be shifted two bits right.\n\t\t */\n\t\tright_shift_array(output, MLXSW_SP4_BLOOM_KEY_CHUNK_BYTES, 2);\n\t\tbreak;\n\tcase 3:\n\t\t/* The chunks are copied as follow:\n\t\t * +-------------+-----------------+-----------------+\n\t\t * | Chunk 0     |   Chunk 1       |   Chunk 2       |\n\t\t * | IDs  | keys |(**) IDs  | keys |(**) IDs  | keys |\n\t\t * +-------------+-----------------+-----------------+\n\t\t * In (**), there are two unused bits, therefore, chunk 1 needs\n\t\t * to be shifted two bits right and chunk 0 needs to be shifted\n\t\t * four bits right.\n\t\t */\n\t\tright_shift_array(output + MLXSW_SP4_BLOOM_KEY_CHUNK_BYTES,\n\t\t\t\t  MLXSW_SP4_BLOOM_KEY_CHUNK_BYTES, 2);\n\t\tright_shift_array(output, MLXSW_SP4_BLOOM_KEY_CHUNK_BYTES, 4);\n\t\tbreak;\n\tdefault:\n\t\tWARN_ON(chunk_count > MLXSW_BLOOM_KEY_CHUNKS);\n\t}\n}",
        "static int test_process_multi_diff_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, diff addr, one is RO, other is WO\";": "static int test_process_multi_diff_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, diff addr, one is RO, other is WO\";\n\tsize_t res;\n\n\tfd1 = perf_process_event_open(HW_BREAKPOINT_W, (__u64)&a, (__u64)sizeof(a));\n\tif (fd1 < 0) {\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tfd2 = perf_process_event_open(HW_BREAKPOINT_R, (__u64)&b, (__u64)sizeof(b));\n\tif (fd2 < 0) {\n\t\tclose(fd1);\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tioctl(fd1, PERF_EVENT_IOC_RESET);\n\tioctl(fd2, PERF_EVENT_IOC_RESET);\n\tioctl(fd1, PERF_EVENT_IOC_ENABLE);\n\tioctl(fd2, PERF_EVENT_IOC_ENABLE);\n\tmulti_dawr_workload();\n\tioctl(fd1, PERF_EVENT_IOC_DISABLE);\n\tioctl(fd2, PERF_EVENT_IOC_DISABLE);\n\n\tres = read(fd1, &breaks1, sizeof(breaks1));\n\tassert(res == sizeof(unsigned long long));\n\tres = read(fd2, &breaks2, sizeof(breaks2));\n\tassert(res == sizeof(unsigned long long));\n\n\tclose(fd1);\n\tclose(fd2);\n\n\tif (breaks1 != 1 || breaks2 != 1) {\n\t\tprintf(\"FAILED: %s: %lld != 1 || %lld != 1\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static int dvb_input_attach(struct ddb_input *input)\n{\n\tint ret = 0;\n\tstruct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];\n\tstruct ddb_port *port = input->port;": "static int dvb_input_attach(struct ddb_input *input)\n{\n\tint ret = 0;\n\tstruct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];\n\tstruct ddb_port *port = input->port;\n\tstruct dvb_adapter *adap = dvb->adap;\n\tstruct dvb_demux *dvbdemux = &dvb->demux;\n\tstruct ddb_ids *devids = &input->port->dev->link[input->port->lnr].ids;\n\tint par = 0, osc24 = 0, tsfast = 0;\n\n\t/*\n\t * Determine if bridges with stv0910 demods can run with fast TS and\n\t * thus support high bandwidth transponders.\n\t * STV0910_PR and STV0910_P tuner types covers all relevant bridges,\n\t * namely the CineS2 V7(A) and the Octopus CI S2 Pro/Advanced. All\n\t * DuoFlex S2 V4(A) have type=DDB_TUNER_DVBS_STV0910 without any suffix\n\t * and are limited by the serial link to the bridge, thus won't work\n\t * in fast TS mode.\n\t */\n\tif (port->nr == 0 &&\n\t    (port->type == DDB_TUNER_DVBS_STV0910_PR ||\n\t     port->type == DDB_TUNER_DVBS_STV0910_P)) {\n\t\t/* fast TS on port 0 requires FPGA version >= 1.7 */\n\t\tif ((devids->hwid & 0x00ffffff) >= 0x00010007)\n\t\t\ttsfast = 1;\n\t}\n\n\tdvb->attached = 0x01;\n\n\tdvbdemux->priv = input;\n\tdvbdemux->dmx.capabilities = DMX_TS_FILTERING |\n\t\tDMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING;\n\tdvbdemux->start_feed = start_feed;\n\tdvbdemux->stop_feed = stop_feed;\n\tdvbdemux->filternum = 256;\n\tdvbdemux->feednum = 256;\n\tret = dvb_dmx_init(dvbdemux);\n\tif (ret < 0)\n\t\treturn ret;\n\tdvb->attached = 0x10;\n\n\tdvb->dmxdev.filternum = 256;\n\tdvb->dmxdev.demux = &dvbdemux->dmx;\n\tret = dvb_dmxdev_init(&dvb->dmxdev, adap);\n\tif (ret < 0)\n\t\tgoto err_detach;\n\tdvb->attached = 0x11;\n\n\tdvb->mem_frontend.source = DMX_MEMORY_FE;\n\tdvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->mem_frontend);\n\tdvb->hw_frontend.source = DMX_FRONTEND_0;\n\tdvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->hw_frontend);\n\tret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &dvb->hw_frontend);\n\tif (ret < 0)\n\t\tgoto err_detach;\n\tdvb->attached = 0x12;\n\n\tret = dvb_net_init(adap, &dvb->dvbnet, dvb->dmxdev.demux);\n\tif (ret < 0)\n\t\tgoto err_detach;\n\tdvb->attached = 0x20;\n\n\tdvb->fe = NULL;\n\tdvb->fe2 = NULL;\n\tswitch (port->type) {\n\tcase DDB_TUNER_MXL5XX:\n\t\tif (ddb_fe_attach_mxl5xx(input) < 0)\n\t\t\tgoto err_detach;\n\t\tbreak;\n\tcase DDB_TUNER_DVBS_ST:\n\t\tif (demod_attach_stv0900(input, 0) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_stv6110(input, 0) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBS_ST_AA:\n\t\tif (demod_attach_stv0900(input, 1) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_stv6110(input, 1) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBS_STV0910:\n\t\tif (demod_attach_stv0910(input, 0, tsfast) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_stv6111(input, 0) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBS_STV0910_PR:\n\t\tif (demod_attach_stv0910(input, 1, tsfast) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_stv6111(input, 1) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBS_STV0910_P:\n\t\tif (demod_attach_stv0910(input, 0, tsfast) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_stv6111(input, 1) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBCT_TR:\n\t\tif (demod_attach_drxk(input) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_tda18271(input) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBCT_ST:\n\t\tif (demod_attach_stv0367(input) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_tda18212(input, port->type) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBC2T2I_SONY_P:\n\t\tif (input->port->dev->link[input->port->lnr].info->ts_quirks &\n\t\t    TS_QUIRK_ALT_OSC)\n\t\t\tosc24 = 0;\n\t\telse\n\t\t\tosc24 = 1;\n\t\tfallthrough;\n\tcase DDB_TUNER_DVBCT2_SONY_P:\n\tcase DDB_TUNER_DVBC2T2_SONY_P:\n\tcase DDB_TUNER_ISDBT_SONY_P:\n\t\tif (input->port->dev->link[input->port->lnr].info->ts_quirks\n\t\t\t& TS_QUIRK_SERIAL)\n\t\t\tpar = 0;\n\t\telse\n\t\t\tpar = 1;\n\t\tif (demod_attach_cxd28xx(input, par, osc24) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_tda18212(input, port->type) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DVBC2T2I_SONY:\n\t\tosc24 = 1;\n\t\tfallthrough;\n\tcase DDB_TUNER_DVBCT2_SONY:\n\tcase DDB_TUNER_DVBC2T2_SONY:\n\tcase DDB_TUNER_ISDBT_SONY:\n\t\tif (demod_attach_cxd28xx(input, 0, osc24) < 0)\n\t\t\tgoto err_detach;\n\t\tif (tuner_attach_tda18212(input, port->type) < 0)\n\t\t\tgoto err_tuner;\n\t\tbreak;\n\tcase DDB_TUNER_DUMMY:\n\t\tif (demod_attach_dummy(input) < 0)\n\t\t\tgoto err_detach;\n\t\tbreak;\n\tcase DDB_TUNER_MCI_SX8:\n\t\tif (ddb_fe_attach_mci(input, port->type) < 0)\n\t\t\tgoto err_detach;\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\tdvb->attached = 0x30;\n\n\tif (dvb->fe) {\n\t\tif (dvb_register_frontend(adap, dvb->fe) < 0)\n\t\t\tgoto err_detach;\n\n\t\tif (dvb->fe2) {\n\t\t\tif (dvb_register_frontend(adap, dvb->fe2) < 0) {\n\t\t\t\tdvb_unregister_frontend(dvb->fe);\n\t\t\t\tgoto err_detach;\n\t\t\t}\n\t\t\tdvb->fe2->tuner_priv = dvb->fe->tuner_priv;\n\t\t\tmemcpy(&dvb->fe2->ops.tuner_ops,\n\t\t\t       &dvb->fe->ops.tuner_ops,\n\t\t\t       sizeof(struct dvb_tuner_ops));\n\t\t}\n\t}\n\n\tdvb->attached = 0x31;\n\treturn 0;\n\nerr_tuner:\n\tdev_err(port->dev->dev, \"tuner attach failed!\\n\");\n\n\tif (dvb->fe2)\n\t\tdvb_frontend_detach(dvb->fe2);\n\tif (dvb->fe)\n\t\tdvb_frontend_detach(dvb->fe);\nerr_detach:\n\tdvb_input_detach(input);\n\n\t/* return error from ret if set */\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn -ENODEV;\n}",
        "static int set_var(struct fbtft_par *par)\n{\n\t/* MADCTL - Memory data access control\n\t * RGB/BGR:\n\t * 1. Mode selection pin SRGB": "static int set_var(struct fbtft_par *par)\n{\n\t/* MADCTL - Memory data access control\n\t * RGB/BGR:\n\t * 1. Mode selection pin SRGB\n\t *    RGB H/W pin for color filter setting: 0=RGB, 1=BGR\n\t * 2. MADCTL RGB bit\n\t *    RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR\n\t */\n\tswitch (par->info->var.rotate) {\n\tcase 0:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MX | MY | (par->bgr << 3));\n\t\tbreak;\n\tcase 270:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MY | MV | (par->bgr << 3));\n\t\tbreak;\n\tcase 180:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  par->bgr << 3);\n\t\tbreak;\n\tcase 90:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MX | MV | (par->bgr << 3));\n\t\tbreak;\n\t}\n\n\treturn 0;\n}",
        "static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)\n{\n\tu32 ulRfAgcOutputLevel = 0xffffffff;\n\tu32 ulRfAgcSettleLevel = 528;\t/* Optimum value for MT2060 */\n\tu32 ulRfAgcMinLevel = 0;\t/* Currently unused */": "static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)\n{\n\tu32 ulRfAgcOutputLevel = 0xffffffff;\n\tu32 ulRfAgcSettleLevel = 528;\t/* Optimum value for MT2060 */\n\tu32 ulRfAgcMinLevel = 0;\t/* Currently unused */\n\tu32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX;\t/* Currently unused */\n\tu32 ulRfAgcSpeed = 0;\t/* Currently unused */\n\tu32 ulRfAgcMode = 0;\t/*2;   Off */\n\tu32 ulRfAgcR1 = 820;\n\tu32 ulRfAgcR2 = 2200;\n\tu32 ulRfAgcR3 = 150;\n\tu32 ulIfAgcMode = 0;\t/* Auto */\n\tu32 ulIfAgcOutputLevel = 0xffffffff;\n\tu32 ulIfAgcSettleLevel = 0xffffffff;\n\tu32 ulIfAgcMinLevel = 0xffffffff;\n\tu32 ulIfAgcMaxLevel = 0xffffffff;\n\tu32 ulIfAgcSpeed = 0xffffffff;\n\tu32 ulIfAgcR1 = 820;\n\tu32 ulIfAgcR2 = 2200;\n\tu32 ulIfAgcR3 = 150;\n\tu32 ulClock = state->config.clock;\n\tu32 ulSerialMode = 0;\n\tu32 ulEcOcRegOcModeLop = 4;\t/* Dynamic DTO source */\n\tu32 ulHiI2cDelay = HI_I2C_DELAY;\n\tu32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;\n\tu32 ulHiI2cPatch = 0;\n\tu32 ulEnvironment = APPENV_PORTABLE;\n\tu32 ulEnvironmentDiversity = APPENV_MOBILE;\n\tu32 ulIFFilter = IFFILTER_SAW;\n\n\tstate->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;\n\tstate->if_agc_cfg.outputLevel = 0;\n\tstate->if_agc_cfg.settleLevel = 140;\n\tstate->if_agc_cfg.minOutputLevel = 0;\n\tstate->if_agc_cfg.maxOutputLevel = 1023;\n\tstate->if_agc_cfg.speed = 904;\n\n\tif (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {\n\t\tstate->if_agc_cfg.ctrlMode = AGC_CTRL_USER;\n\t\tstate->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);\n\t}\n\n\tif (ulIfAgcMode == 0 &&\n\t    ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&\n\t    ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&\n\t    ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&\n\t    ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {\n\t\tstate->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;\n\t\tstate->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);\n\t\tstate->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);\n\t\tstate->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);\n\t\tstate->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);\n\t}\n\n\tstate->if_agc_cfg.R1 = (u16) (ulIfAgcR1);\n\tstate->if_agc_cfg.R2 = (u16) (ulIfAgcR2);\n\tstate->if_agc_cfg.R3 = (u16) (ulIfAgcR3);\n\n\tstate->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);\n\tstate->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);\n\tstate->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);\n\n\tstate->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;\n\t/* rest of the RFAgcCfg structure currently unused */\n\tif (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {\n\t\tstate->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;\n\t\tstate->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);\n\t}\n\n\tif (ulRfAgcMode == 0 &&\n\t    ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&\n\t    ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&\n\t    ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&\n\t    ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {\n\t\tstate->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;\n\t\tstate->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);\n\t\tstate->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);\n\t\tstate->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);\n\t\tstate->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);\n\t}\n\n\tif (ulRfAgcMode == 2)\n\t\tstate->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;\n\n\tif (ulEnvironment <= 2)\n\t\tstate->app_env_default = (enum app_env)\n\t\t    (ulEnvironment);\n\tif (ulEnvironmentDiversity <= 2)\n\t\tstate->app_env_diversity = (enum app_env)\n\t\t    (ulEnvironmentDiversity);\n\n\tif (ulIFFilter == IFFILTER_DISCRETE) {\n\t\t/* discrete filter */\n\t\tstate->noise_cal.cpOpt = 0;\n\t\tstate->noise_cal.cpNexpOfs = 40;\n\t\tstate->noise_cal.tdCal2k = -40;\n\t\tstate->noise_cal.tdCal8k = -24;\n\t} else {\n\t\t/* SAW filter */\n\t\tstate->noise_cal.cpOpt = 1;\n\t\tstate->noise_cal.cpNexpOfs = 0;\n\t\tstate->noise_cal.tdCal2k = -21;\n\t\tstate->noise_cal.tdCal8k = -24;\n\t}\n\tstate->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);\n\n\tstate->chip_adr = (state->config.demod_address << 1) | 1;\n\tswitch (ulHiI2cPatch) {\n\tcase 1:\n\t\tstate->m_HiI2cPatch = DRXD_HiI2cPatch_1;\n\t\tbreak;\n\tcase 3:\n\t\tstate->m_HiI2cPatch = DRXD_HiI2cPatch_3;\n\t\tbreak;\n\tdefault:\n\t\tstate->m_HiI2cPatch = NULL;\n\t}\n\n\t/* modify tuner and clock attributes */\n\tstate->intermediate_freq = (u16) (IntermediateFrequency / 1000);\n\t/* expected system clock frequency in kHz */\n\tstate->expected_sys_clock_freq = 48000;\n\t/* real system clock frequency in kHz */\n\tstate->sys_clock_freq = 48000;\n\tstate->osc_clock_freq = (u16) ulClock;\n\tstate->osc_clock_deviation = 0;\n\tstate->cscd_state = CSCD_INIT;\n\tstate->drxd_state = DRXD_UNINITIALIZED;\n\n\tstate->PGA = 0;\n\tstate->type_A = 0;\n\tstate->tuner_mirrors = 0;\n\n\t/* modify MPEG output attributes */\n\tstate->insert_rs_byte = state->config.insert_rs_byte;\n\tstate->enable_parallel = (ulSerialMode != 1);\n\n\t/* Timing div, 250ns/Psys */\n\t/* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */\n\n\tstate->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *\n\t\t\t\t\t  ulHiI2cDelay) / 1000;\n\t/* Bridge delay, uses oscilator clock */\n\t/* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */\n\tstate->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *\n\t\t\t\t\t    ulHiI2cBridgeDelay) / 1000;\n\n\tstate->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;\n\t/* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */\n\tstate->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;\n\treturn 0;\n}",
        "static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)\n{\n\t/*\n\t  Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness\n\t  for cx25840 causes that module to correctly set up its video": "static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)\n{\n\t/*\n\t  Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness\n\t  for cx25840 causes that module to correctly set up its video\n\t  scaling.  This is really a problem in the cx25840 module itself,\n\t  but we work around it here.  The problem has not been seen in\n\t  ivtv because there VBI is supported and set up.  We don't do VBI\n\t  here (at least not yet) and thus we never attempted to even set\n\t  it up.\n\t*/\n\tstruct v4l2_format fmt;\n\tif (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {\n\t\t/* We're not using a cx25840 so don't enable the hack */\n\t\treturn;\n\t}\n\n\tpvr2_trace(PVR2_TRACE_INIT,\n\t\t   \"Module ID %u: Executing cx25840 VBI hack\",\n\t\t   hdw->decoder_client_id);\n\tmemset(&fmt, 0, sizeof(fmt));\n\tfmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;\n\tfmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;\n\tfmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;\n\tv4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,\n\t\t\t     vbi, s_sliced_fmt, &fmt.fmt.sliced);\n}",
        "static int cpu_map_kthread_run(void *data)\n{\n\tstruct bpf_cpu_map_entry *rcpu = data;\n\n\tset_current_state(TASK_INTERRUPTIBLE);": "static int cpu_map_kthread_run(void *data)\n{\n\tstruct bpf_cpu_map_entry *rcpu = data;\n\n\tset_current_state(TASK_INTERRUPTIBLE);\n\n\t/* When kthread gives stop order, then rcpu have been disconnected\n\t * from map, thus no new packets can enter. Remaining in-flight\n\t * per CPU stored packets are flushed to this queue.  Wait honoring\n\t * kthread_stop signal until queue is empty.\n\t */\n\twhile (!kthread_should_stop() || !__ptr_ring_empty(rcpu->queue)) {\n\t\tstruct xdp_cpumap_stats stats = {}; /* zero stats */\n\t\tunsigned int kmem_alloc_drops = 0, sched = 0;\n\t\tgfp_t gfp = __GFP_ZERO | GFP_ATOMIC;\n\t\tint i, n, m, nframes, xdp_n;\n\t\tvoid *frames[CPUMAP_BATCH];\n\t\tvoid *skbs[CPUMAP_BATCH];\n\t\tLIST_HEAD(list);\n\n\t\t/* Release CPU reschedule checks */\n\t\tif (__ptr_ring_empty(rcpu->queue)) {\n\t\t\tset_current_state(TASK_INTERRUPTIBLE);\n\t\t\t/* Recheck to avoid lost wake-up */\n\t\t\tif (__ptr_ring_empty(rcpu->queue)) {\n\t\t\t\tschedule();\n\t\t\t\tsched = 1;\n\t\t\t} else {\n\t\t\t\t__set_current_state(TASK_RUNNING);\n\t\t\t}\n\t\t} else {\n\t\t\tsched = cond_resched();\n\t\t}\n\n\t\t/*\n\t\t * The bpf_cpu_map_entry is single consumer, with this\n\t\t * kthread CPU pinned. Lockless access to ptr_ring\n\t\t * consume side valid as no-resize allowed of queue.\n\t\t */\n\t\tn = __ptr_ring_consume_batched(rcpu->queue, frames,\n\t\t\t\t\t       CPUMAP_BATCH);\n\t\tfor (i = 0, xdp_n = 0; i < n; i++) {\n\t\t\tvoid *f = frames[i];\n\t\t\tstruct page *page;\n\n\t\t\tif (unlikely(__ptr_test_bit(0, &f))) {\n\t\t\t\tstruct sk_buff *skb = f;\n\n\t\t\t\t__ptr_clear_bit(0, &skb);\n\t\t\t\tlist_add_tail(&skb->list, &list);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tframes[xdp_n++] = f;\n\t\t\tpage = virt_to_page(f);\n\n\t\t\t/* Bring struct page memory area to curr CPU. Read by\n\t\t\t * build_skb_around via page_is_pfmemalloc(), and when\n\t\t\t * freed written by page_frag_free call.\n\t\t\t */\n\t\t\tprefetchw(page);\n\t\t}\n\n\t\t/* Support running another XDP prog on this CPU */\n\t\tnframes = cpu_map_bpf_prog_run(rcpu, frames, xdp_n, &stats, &list);\n\t\tif (nframes) {\n\t\t\tm = kmem_cache_alloc_bulk(skbuff_head_cache, gfp, nframes, skbs);\n\t\t\tif (unlikely(m == 0)) {\n\t\t\t\tfor (i = 0; i < nframes; i++)\n\t\t\t\t\tskbs[i] = NULL; /* effect: xdp_return_frame */\n\t\t\t\tkmem_alloc_drops += nframes;\n\t\t\t}\n\t\t}\n\n\t\tlocal_bh_disable();\n\t\tfor (i = 0; i < nframes; i++) {\n\t\t\tstruct xdp_frame *xdpf = frames[i];\n\t\t\tstruct sk_buff *skb = skbs[i];\n\n\t\t\tskb = __xdp_build_skb_from_frame(xdpf, skb,\n\t\t\t\t\t\t\t xdpf->dev_rx);\n\t\t\tif (!skb) {\n\t\t\t\txdp_return_frame(xdpf);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tlist_add_tail(&skb->list, &list);\n\t\t}\n\t\tnetif_receive_skb_list(&list);\n\n\t\t/* Feedback loop via tracepoint */\n\t\ttrace_xdp_cpumap_kthread(rcpu->map_id, n, kmem_alloc_drops,\n\t\t\t\t\t sched, &stats);\n\n\t\tlocal_bh_enable(); /* resched point, may call do_softirq() */\n\t}\n\t__set_current_state(TASK_RUNNING);\n\n\tput_cpu_map_entry(rcpu);\n\treturn 0;\n}",
        "static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)\n{\n\tstruct hantro_dev *vpu = ctx->dev;\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_scaling_matrix *sc = ctrls->scaling;": "static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)\n{\n\tstruct hantro_dev *vpu = ctx->dev;\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_scaling_matrix *sc = ctrls->scaling;\n\tconst struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;\n\tu8 *p = ((u8 *)ctx->hevc_dec.scaling_lists.cpu);\n\tunsigned int scaling_list_enabled;\n\tunsigned int i, j, k;\n\n\tscaling_list_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);\n\thantro_reg_write(vpu, &g2_scaling_list_e, scaling_list_enabled);\n\n\tif (!scaling_list_enabled)\n\t\treturn;\n\n\tfor (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_16x16); i++)\n\t\t*p++ = sc->scaling_list_dc_coef_16x16[i];\n\n\tfor (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_32x32); i++)\n\t\t*p++ = sc->scaling_list_dc_coef_32x32[i];\n\n\t/* 128-bit boundary */\n\tp += 8;\n\n\t/* write scaling lists column by column */\n\n\tfor (i = 0; i < 6; i++)\n\t\tfor (j = 0; j < 4; j++)\n\t\t\tfor (k = 0; k < 4; k++)\n\t\t\t\t*p++ = sc->scaling_list_4x4[i][4 * k + j];\n\n\tfor (i = 0; i < 6; i++)\n\t\tfor (j = 0; j < 8; j++)\n\t\t\tfor (k = 0; k < 8; k++)\n\t\t\t\t*p++ = sc->scaling_list_8x8[i][8 * k + j];\n\n\tfor (i = 0; i < 6; i++)\n\t\tfor (j = 0; j < 8; j++)\n\t\t\tfor (k = 0; k < 8; k++)\n\t\t\t\t*p++ = sc->scaling_list_16x16[i][8 * k + j];\n\n\tfor (i = 0; i < 2; i++)\n\t\tfor (j = 0; j < 8; j++)\n\t\t\tfor (k = 0; k < 8; k++)\n\t\t\t\t*p++ = sc->scaling_list_32x32[i][8 * k + j];\n\n\thantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);\n}",
        "static int alloc_try_nid_bottom_up_reserved_with_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;": "static int alloc_try_nid_bottom_up_reserved_with_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\tstruct region r1, r2;\n\n\tphys_addr_t r3_size = SZ_64;\n\tphys_addr_t gap_size = SMP_CACHE_BYTES;\n\tphys_addr_t total_size;\n\tphys_addr_t max_addr;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2;\n\tr1.size = SMP_CACHE_BYTES;\n\n\tr2.size = SZ_128;\n\tr2.base = r1.base - (r3_size + gap_size + r2.size);\n\n\ttotal_size = r1.size + r2.size + r3_size;\n\tmin_addr = r2.base + r2.size;\n\tmax_addr = r1.base;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr,\n\t\t\t\t\t       NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn1->size == r1.size);\n\tassert(rgn1->base == max_addr);\n\n\tassert(rgn2->size == r2.size + r3_size);\n\tassert(rgn2->base == r2.base);\n\n\tassert(memblock.reserved.cnt == 2);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static int __ebs_rw_bvec(struct ebs_c *ec, int rw, struct bio_vec *bv, struct bvec_iter *iter)\n{\n\tint r = 0;\n\tunsigned char *ba, *pa;\n\tunsigned int cur_len;": "static int __ebs_rw_bvec(struct ebs_c *ec, int rw, struct bio_vec *bv, struct bvec_iter *iter)\n{\n\tint r = 0;\n\tunsigned char *ba, *pa;\n\tunsigned int cur_len;\n\tunsigned int bv_len = bv->bv_len;\n\tunsigned int buf_off = to_bytes(__block_mod(iter->bi_sector, ec->u_bs));\n\tsector_t block = __sector_to_block(ec, iter->bi_sector);\n\tstruct dm_buffer *b;\n\n\tif (unlikely(!bv->bv_page || !bv_len))\n\t\treturn -EIO;\n\n\tpa = bvec_virt(bv);\n\n\t/* Handle overlapping page <-> blocks */\n\twhile (bv_len) {\n\t\tcur_len = min(dm_bufio_get_block_size(ec->bufio) - buf_off, bv_len);\n\n\t\t/* Avoid reading for writes in case bio vector's page overwrites block completely. */\n\t\tif (rw == READ || buf_off || bv_len < dm_bufio_get_block_size(ec->bufio))\n\t\t\tba = dm_bufio_read(ec->bufio, block, &b);\n\t\telse\n\t\t\tba = dm_bufio_new(ec->bufio, block, &b);\n\n\t\tif (IS_ERR(ba)) {\n\t\t\t/*\n\t\t\t * Carry on with next buffer, if any, to issue all possible\n\t\t\t * data but return error.\n\t\t\t */\n\t\t\tr = PTR_ERR(ba);\n\t\t} else {\n\t\t\t/* Copy data to/from bio to buffer if read/new was successful above. */\n\t\t\tba += buf_off;\n\t\t\tif (rw == READ) {\n\t\t\t\tmemcpy(pa, ba, cur_len);\n\t\t\t\tflush_dcache_page(bv->bv_page);\n\t\t\t} else {\n\t\t\t\tflush_dcache_page(bv->bv_page);\n\t\t\t\tmemcpy(ba, pa, cur_len);\n\t\t\t\tdm_bufio_mark_partial_buffer_dirty(b, buf_off, buf_off + cur_len);\n\t\t\t}\n\n\t\t\tdm_bufio_release(b);\n\t\t}\n\n\t\tpa += cur_len;\n\t\tbv_len -= cur_len;\n\t\tbuf_off = 0;\n\t\tblock++;\n\t}\n\n\treturn r;\n}",
        "static int alloc_chain_hlocks(int req)\n{\n\tint bucket, curr, size;\n\n\t/*": "static int alloc_chain_hlocks(int req)\n{\n\tint bucket, curr, size;\n\n\t/*\n\t * We rely on the MSB to act as an escape bit to denote freelist\n\t * pointers. Make sure this bit isn't set in 'normal' class_idx usage.\n\t */\n\tBUILD_BUG_ON((MAX_LOCKDEP_KEYS-1) & CHAIN_BLK_FLAG);\n\n\tinit_data_structures_once();\n\n\tif (nr_free_chain_hlocks < req)\n\t\treturn -1;\n\n\t/*\n\t * We require a minimum of 2 (u16) entries to encode a freelist\n\t * 'pointer'.\n\t */\n\treq = max(req, 2);\n\tbucket = size_to_bucket(req);\n\tcurr = chain_block_buckets[bucket];\n\n\tif (bucket) {\n\t\tif (curr >= 0) {\n\t\t\tdel_chain_block(bucket, req, chain_block_next(curr));\n\t\t\treturn curr;\n\t\t}\n\t\t/* Try bucket 0 */\n\t\tcurr = chain_block_buckets[0];\n\t}\n\n\t/*\n\t * The variable sized freelist is sorted by size; the first entry is\n\t * the largest. Use it if it fits.\n\t */\n\tif (curr >= 0) {\n\t\tsize = chain_block_size(curr);\n\t\tif (likely(size >= req)) {\n\t\t\tdel_chain_block(0, size, chain_block_next(curr));\n\t\t\tadd_chain_block(curr + req, size - req);\n\t\t\treturn curr;\n\t\t}\n\t}\n\n\t/*\n\t * Last resort, split a block in a larger sized bucket.\n\t */\n\tfor (size = MAX_CHAIN_BUCKETS; size > req; size--) {\n\t\tbucket = size_to_bucket(size);\n\t\tcurr = chain_block_buckets[bucket];\n\t\tif (curr < 0)\n\t\t\tcontinue;\n\n\t\tdel_chain_block(bucket, size, chain_block_next(curr));\n\t\tadd_chain_block(curr + req, size - req);\n\t\treturn curr;\n\t}\n\n\treturn -1;\n}",
        "static void yas53x_extract_calibration(u8 *data, struct yas5xx_calibration *c)\n{\n\tu64 val = get_unaligned_be64(data);\n\n\t/*": "static void yas53x_extract_calibration(u8 *data, struct yas5xx_calibration *c)\n{\n\tu64 val = get_unaligned_be64(data);\n\n\t/*\n\t * Bitfield layout for the axis calibration data, for factor\n\t * a2 = 2 etc, k = k, c = clock divider\n\t *\n\t * n   7 6 5 4 3 2 1 0\n\t * 0 [ 2 2 2 2 2 2 3 3 ] bits 63 .. 56\n\t * 1 [ 3 3 4 4 4 4 4 4 ] bits 55 .. 48\n\t * 2 [ 5 5 5 5 5 5 6 6 ] bits 47 .. 40\n\t * 3 [ 6 6 6 6 7 7 7 7 ] bits 39 .. 32\n\t * 4 [ 7 7 7 8 8 8 8 8 ] bits 31 .. 24\n\t * 5 [ 8 9 9 9 9 9 9 9 ] bits 23 .. 16\n\t * 6 [ 9 k k k k k c c ] bits 15 .. 8\n\t * 7 [ c x x x x x x x ] bits  7 .. 0\n\t */\n\tc->a2 = FIELD_GET(GENMASK_ULL(63, 58), val) - 32;\n\tc->a3 = FIELD_GET(GENMASK_ULL(57, 54), val) - 8;\n\tc->a4 = FIELD_GET(GENMASK_ULL(53, 48), val) - 32;\n\tc->a5 = FIELD_GET(GENMASK_ULL(47, 42), val) + 38;\n\tc->a6 = FIELD_GET(GENMASK_ULL(41, 36), val) - 32;\n\tc->a7 = FIELD_GET(GENMASK_ULL(35, 29), val) - 64;\n\tc->a8 = FIELD_GET(GENMASK_ULL(28, 23), val) - 32;\n\tc->a9 = FIELD_GET(GENMASK_ULL(22, 15), val);\n\tc->k = FIELD_GET(GENMASK_ULL(14, 10), val) + 10;\n\tc->dck = FIELD_GET(GENMASK_ULL(9, 7), val);\n}",
        "static int next_cpu(int cpu)\n{\n\t/*\n\t * Advance to the next CPU, skipping those that weren't in the original\n\t * affinity set.  Sadly, there is no CPU_SET_FOR_EACH, and cpu_set_t's": "static int next_cpu(int cpu)\n{\n\t/*\n\t * Advance to the next CPU, skipping those that weren't in the original\n\t * affinity set.  Sadly, there is no CPU_SET_FOR_EACH, and cpu_set_t's\n\t * data storage is considered as opaque.  Note, if this task is pinned\n\t * to a small set of discontigous CPUs, e.g. 2 and 1023, this loop will\n\t * burn a lot cycles and the test will take longer than normal to\n\t * complete.\n\t */\n\tdo {\n\t\tcpu++;\n\t\tif (cpu > max_cpu) {\n\t\t\tcpu = min_cpu;\n\t\t\tTEST_ASSERT(CPU_ISSET(cpu, &possible_mask),\n\t\t\t\t    \"Min CPU = %d must always be usable\", cpu);\n\t\t\tbreak;\n\t\t}\n\t} while (!CPU_ISSET(cpu, &possible_mask));\n\n\treturn cpu;\n}",
        "static void process_rx(struct max_tcpci_chip *chip, u16 status)\n{\n\tstruct pd_message msg;\n\tu8 count, frame_type, rx_buf[TCPC_RECEIVE_BUFFER_LEN];\n\tint ret, payload_index;": "static void process_rx(struct max_tcpci_chip *chip, u16 status)\n{\n\tstruct pd_message msg;\n\tu8 count, frame_type, rx_buf[TCPC_RECEIVE_BUFFER_LEN];\n\tint ret, payload_index;\n\tu8 *rx_buf_ptr;\n\n\t/*\n\t * READABLE_BYTE_COUNT: Indicates the number of bytes in the RX_BUF_BYTE_x registers\n\t * plus one (for the RX_BUF_FRAME_TYPE) Table 4-36.\n\t * Read the count and frame type.\n\t */\n\tret = regmap_raw_read(chip->data.regmap, TCPC_RX_BYTE_CNT, rx_buf, 2);\n\tif (ret < 0) {\n\t\tdev_err(chip->dev, \"TCPC_RX_BYTE_CNT read failed ret:%d\\n\", ret);\n\t\treturn;\n\t}\n\n\tcount = rx_buf[TCPC_RECEIVE_BUFFER_COUNT_OFFSET];\n\tframe_type = rx_buf[TCPC_RECEIVE_BUFFER_FRAME_TYPE_OFFSET];\n\n\tif (count == 0 || frame_type != TCPC_RX_BUF_FRAME_TYPE_SOP) {\n\t\tmax_tcpci_write16(chip, TCPC_ALERT, TCPC_ALERT_RX_STATUS);\n\t\tdev_err(chip->dev, \"%s\\n\", count ==  0 ? \"error: count is 0\" :\n\t\t\t\"error frame_type is not SOP\");\n\t\treturn;\n\t}\n\n\tif (count > sizeof(struct pd_message) || count + 1 > TCPC_RECEIVE_BUFFER_LEN) {\n\t\tdev_err(chip->dev, \"Invalid TCPC_RX_BYTE_CNT %d\\n\", count);\n\t\treturn;\n\t}\n\n\t/*\n\t * Read count + 1 as RX_BUF_BYTE_x is hidden and can only be read through\n\t * TCPC_RX_BYTE_CNT\n\t */\n\tcount += 1;\n\tret = regmap_raw_read(chip->data.regmap, TCPC_RX_BYTE_CNT, rx_buf, count);\n\tif (ret < 0) {\n\t\tdev_err(chip->dev, \"Error: TCPC_RX_BYTE_CNT read failed: %d\\n\", ret);\n\t\treturn;\n\t}\n\n\trx_buf_ptr = rx_buf + TCPC_RECEIVE_BUFFER_RX_BYTE_BUF_OFFSET;\n\tmsg.header = cpu_to_le16(*(u16 *)rx_buf_ptr);\n\trx_buf_ptr = rx_buf_ptr + sizeof(msg.header);\n\tfor (payload_index = 0; payload_index < pd_header_cnt_le(msg.header); payload_index++,\n\t     rx_buf_ptr += sizeof(msg.payload[0]))\n\t\tmsg.payload[payload_index] = cpu_to_le32(*(u32 *)rx_buf_ptr);\n\n\t/*\n\t * Read complete, clear RX status alert bit.\n\t * Clear overflow as well if set.\n\t */\n\tret = max_tcpci_write16(chip, TCPC_ALERT, status & TCPC_ALERT_RX_BUF_OVF ?\n\t\t\t\tTCPC_ALERT_RX_STATUS | TCPC_ALERT_RX_BUF_OVF :\n\t\t\t\tTCPC_ALERT_RX_STATUS);\n\tif (ret < 0)\n\t\treturn;\n\n\ttcpm_pd_receive(chip->port, &msg);\n}",
        "static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)\n{\n\tint ch = mode & CM_OPEN_CH_MASK;\n\n\t/* FIXME: a file should wait until the device becomes free": "static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)\n{\n\tint ch = mode & CM_OPEN_CH_MASK;\n\n\t/* FIXME: a file should wait until the device becomes free\n\t * when it's opened on blocking mode.  however, since the current\n\t * pcm framework doesn't pass file pointer before actually opened,\n\t * we can't know whether blocking mode or not in open callback..\n\t */\n\tmutex_lock(&cm->open_mutex);\n\tif (cm->opened[ch]) {\n\t\tmutex_unlock(&cm->open_mutex);\n\t\treturn -EBUSY;\n\t}\n\tcm->opened[ch] = mode;\n\tcm->channel[ch].substream = subs;\n\tif (! (mode & CM_OPEN_DAC)) {\n\t\t/* disable dual DAC mode */\n\t\tcm->channel[ch].is_dac = 0;\n\t\tspin_lock_irq(&cm->reg_lock);\n\t\tsnd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);\n\t\tspin_unlock_irq(&cm->reg_lock);\n\t}\n\tmutex_unlock(&cm->open_mutex);\n\treturn 0;\n}",
        "static int rcu_implicit_dynticks_qs(struct rcu_data *rdp)\n{\n\tunsigned long jtsq;\n\tstruct rcu_node *rnp = rdp->mynode;\n": "static int rcu_implicit_dynticks_qs(struct rcu_data *rdp)\n{\n\tunsigned long jtsq;\n\tstruct rcu_node *rnp = rdp->mynode;\n\n\t/*\n\t * If the CPU passed through or entered a dynticks idle phase with\n\t * no active irq/NMI handlers, then we can safely pretend that the CPU\n\t * already acknowledged the request to pass through a quiescent\n\t * state.  Either way, that CPU cannot possibly be in an RCU\n\t * read-side critical section that started before the beginning\n\t * of the current RCU grace period.\n\t */\n\tif (rcu_dynticks_in_eqs_since(rdp, rdp->dynticks_snap)) {\n\t\ttrace_rcu_fqs(rcu_state.name, rdp->gp_seq, rdp->cpu, TPS(\"dti\"));\n\t\trcu_gpnum_ovf(rnp, rdp);\n\t\treturn 1;\n\t}\n\n\t/*\n\t * Complain if a CPU that is considered to be offline from RCU's\n\t * perspective has not yet reported a quiescent state.  After all,\n\t * the offline CPU should have reported a quiescent state during\n\t * the CPU-offline process, or, failing that, by rcu_gp_init()\n\t * if it ran concurrently with either the CPU going offline or the\n\t * last task on a leaf rcu_node structure exiting its RCU read-side\n\t * critical section while all CPUs corresponding to that structure\n\t * are offline.  This added warning detects bugs in any of these\n\t * code paths.\n\t *\n\t * The rcu_node structure's ->lock is held here, which excludes\n\t * the relevant portions the CPU-hotplug code, the grace-period\n\t * initialization code, and the rcu_read_unlock() code paths.\n\t *\n\t * For more detail, please refer to the \"Hotplug CPU\" section\n\t * of RCU's Requirements documentation.\n\t */\n\tif (WARN_ON_ONCE(!rcu_rdp_cpu_online(rdp))) {\n\t\tstruct rcu_node *rnp1;\n\n\t\tpr_info(\"%s: grp: %d-%d level: %d ->gp_seq %ld ->completedqs %ld\\n\",\n\t\t\t__func__, rnp->grplo, rnp->grphi, rnp->level,\n\t\t\t(long)rnp->gp_seq, (long)rnp->completedqs);\n\t\tfor (rnp1 = rnp; rnp1; rnp1 = rnp1->parent)\n\t\t\tpr_info(\"%s: %d:%d ->qsmask %#lx ->qsmaskinit %#lx ->qsmaskinitnext %#lx ->rcu_gp_init_mask %#lx\\n\",\n\t\t\t\t__func__, rnp1->grplo, rnp1->grphi, rnp1->qsmask, rnp1->qsmaskinit, rnp1->qsmaskinitnext, rnp1->rcu_gp_init_mask);\n\t\tpr_info(\"%s %d: %c online: %ld(%d) offline: %ld(%d)\\n\",\n\t\t\t__func__, rdp->cpu, \".o\"[rcu_rdp_cpu_online(rdp)],\n\t\t\t(long)rdp->rcu_onl_gp_seq, rdp->rcu_onl_gp_flags,\n\t\t\t(long)rdp->rcu_ofl_gp_seq, rdp->rcu_ofl_gp_flags);\n\t\treturn 1; /* Break things loose after complaining. */\n\t}\n\n\t/*\n\t * A CPU running for an extended time within the kernel can\n\t * delay RCU grace periods: (1) At age jiffies_to_sched_qs,\n\t * set .rcu_urgent_qs, (2) At age 2*jiffies_to_sched_qs, set\n\t * both .rcu_need_heavy_qs and .rcu_urgent_qs.  Note that the\n\t * unsynchronized assignments to the per-CPU rcu_need_heavy_qs\n\t * variable are safe because the assignments are repeated if this\n\t * CPU failed to pass through a quiescent state.  This code\n\t * also checks .jiffies_resched in case jiffies_to_sched_qs\n\t * is set way high.\n\t */\n\tjtsq = READ_ONCE(jiffies_to_sched_qs);\n\tif (!READ_ONCE(rdp->rcu_need_heavy_qs) &&\n\t    (time_after(jiffies, rcu_state.gp_start + jtsq * 2) ||\n\t     time_after(jiffies, rcu_state.jiffies_resched) ||\n\t     rcu_state.cbovld)) {\n\t\tWRITE_ONCE(rdp->rcu_need_heavy_qs, true);\n\t\t/* Store rcu_need_heavy_qs before rcu_urgent_qs. */\n\t\tsmp_store_release(&rdp->rcu_urgent_qs, true);\n\t} else if (time_after(jiffies, rcu_state.gp_start + jtsq)) {\n\t\tWRITE_ONCE(rdp->rcu_urgent_qs, true);\n\t}\n\n\t/*\n\t * NO_HZ_FULL CPUs can run in-kernel without rcu_sched_clock_irq!\n\t * The above code handles this, but only for straight cond_resched().\n\t * And some in-kernel loops check need_resched() before calling\n\t * cond_resched(), which defeats the above code for CPUs that are\n\t * running in-kernel with scheduling-clock interrupts disabled.\n\t * So hit them over the head with the resched_cpu() hammer!\n\t */\n\tif (tick_nohz_full_cpu(rdp->cpu) &&\n\t    (time_after(jiffies, READ_ONCE(rdp->last_fqs_resched) + jtsq * 3) ||\n\t     rcu_state.cbovld)) {\n\t\tWRITE_ONCE(rdp->rcu_urgent_qs, true);\n\t\tresched_cpu(rdp->cpu);\n\t\tWRITE_ONCE(rdp->last_fqs_resched, jiffies);\n\t}\n\n\t/*\n\t * If more than halfway to RCU CPU stall-warning time, invoke\n\t * resched_cpu() more frequently to try to loosen things up a bit.\n\t * Also check to see if the CPU is getting hammered with interrupts,\n\t * but only once per grace period, just to keep the IPIs down to\n\t * a dull roar.\n\t */\n\tif (time_after(jiffies, rcu_state.jiffies_resched)) {\n\t\tif (time_after(jiffies,\n\t\t\t       READ_ONCE(rdp->last_fqs_resched) + jtsq)) {\n\t\t\tresched_cpu(rdp->cpu);\n\t\t\tWRITE_ONCE(rdp->last_fqs_resched, jiffies);\n\t\t}\n\t\tif (IS_ENABLED(CONFIG_IRQ_WORK) &&\n\t\t    !rdp->rcu_iw_pending && rdp->rcu_iw_gp_seq != rnp->gp_seq &&\n\t\t    (rnp->ffmask & rdp->grpmask)) {\n\t\t\trdp->rcu_iw_pending = true;\n\t\t\trdp->rcu_iw_gp_seq = rnp->gp_seq;\n\t\t\tirq_work_queue_on(&rdp->rcu_iw, rdp->cpu);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static void test_pcpu_map_init(void)\n{\n\tpcpu_map_value_t value[nr_cpus];\n\tstruct test_map_init *skel;\n\tint map_fd, err;": "static void test_pcpu_map_init(void)\n{\n\tpcpu_map_value_t value[nr_cpus];\n\tstruct test_map_init *skel;\n\tint map_fd, err;\n\tmap_key_t key;\n\n\t/* max 1 elem in map so insertion is forced to reuse freed entry */\n\tskel = setup(BPF_MAP_TYPE_PERCPU_HASH, 1, &map_fd, 1);\n\tif (!ASSERT_OK_PTR(skel, \"prog_setup\"))\n\t\treturn;\n\n\t/* delete element so the entry can be re-used*/\n\tkey = 1;\n\terr = bpf_map_delete_elem(map_fd, &key);\n\tif (!ASSERT_OK(err, \"bpf_map_delete_elem\"))\n\t\tgoto cleanup;\n\n\t/* run bpf prog that inserts new elem, re-using the slot just freed */\n\terr = prog_run_insert_elem(skel, key, TEST_VALUE);\n\tif (!ASSERT_OK(err, \"prog_run_insert_elem\"))\n\t\tgoto cleanup;\n\n\t/* check that key=1 was re-created by bpf prog */\n\terr = bpf_map_lookup_elem(map_fd, &key, value);\n\tif (!ASSERT_OK(err, \"bpf_map_lookup_elem\"))\n\t\tgoto cleanup;\n\n\t/* and has expected values */\n\tcheck_values_one_cpu(value, TEST_VALUE);\n\ncleanup:\n\ttest_map_init__destroy(skel);\n}",
        "static void ccmp_special_blocks(struct sk_buff *skb, u8 *pn, u8 *b_0, u8 *aad)\n{\n\tstruct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;\n\tu8 qos_tid = ccmp_gcmp_aad(skb, aad);\n": "static void ccmp_special_blocks(struct sk_buff *skb, u8 *pn, u8 *b_0, u8 *aad)\n{\n\tstruct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;\n\tu8 qos_tid = ccmp_gcmp_aad(skb, aad);\n\n\t/* In CCM, the initial vectors (IV) used for CTR mode encryption and CBC\n\t * mode authentication are not allowed to collide, yet both are derived\n\t * from this vector b_0. We only set L := 1 here to indicate that the\n\t * data size can be represented in (L+1) bytes. The CCM layer will take\n\t * care of storing the data length in the top (L+1) bytes and setting\n\t * and clearing the other bits as is required to derive the two IVs.\n\t */\n\tb_0[0] = 0x1;\n\n\t/* Nonce: Nonce Flags | A2 | PN\n\t * Nonce Flags: Priority (b0..b3) | Management (b4) | Reserved (b5..b7)\n\t */\n\tb_0[1] = qos_tid | (ieee80211_is_mgmt(hdr->frame_control) << 4);\n\tmemcpy(&b_0[2], hdr->addr2, ETH_ALEN);\n\tmemcpy(&b_0[8], pn, IEEE80211_CCMP_PN_LEN);\n}",
        "static void send_pulse_homebrew_softcarrier(unsigned int length, ktime_t edge)\n{\n\tktime_t now, target = ktime_add_us(edge, length);\n\t/*\n\t * delta should never exceed 4 seconds and on m68k": "static void send_pulse_homebrew_softcarrier(unsigned int length, ktime_t edge)\n{\n\tktime_t now, target = ktime_add_us(edge, length);\n\t/*\n\t * delta should never exceed 4 seconds and on m68k\n\t * ndelay(s64) does not compile; so use s32 rather than s64.\n\t */\n\ts32 delta;\n\tunsigned int pulse, space;\n\n\t/* Ensure the dividend fits into 32 bit */\n\tpulse = DIV_ROUND_CLOSEST(serial_ir.duty_cycle * (NSEC_PER_SEC / 100),\n\t\t\t\t  serial_ir.carrier);\n\tspace = DIV_ROUND_CLOSEST((100 - serial_ir.duty_cycle) *\n\t\t\t\t  (NSEC_PER_SEC / 100), serial_ir.carrier);\n\n\tfor (;;) {\n\t\tnow = ktime_get();\n\t\tif (ktime_compare(now, target) >= 0)\n\t\t\tbreak;\n\t\ton();\n\t\tedge = ktime_add_ns(edge, pulse);\n\t\tdelta = ktime_to_ns(ktime_sub(edge, now));\n\t\tif (delta > 0)\n\t\t\tndelay(delta);\n\t\tnow = ktime_get();\n\t\toff();\n\t\tif (ktime_compare(now, target) >= 0)\n\t\t\tbreak;\n\t\tedge = ktime_add_ns(edge, space);\n\t\tdelta = ktime_to_ns(ktime_sub(edge, now));\n\t\tif (delta > 0)\n\t\t\tndelay(delta);\n\t}\n}",
        "static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags)\n{\n\tstruct cfs_rq *cfs_rq;\n\tstruct sched_entity *se = &p->se;\n\tint task_sleep = flags & DEQUEUE_SLEEP;": "static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags)\n{\n\tstruct cfs_rq *cfs_rq;\n\tstruct sched_entity *se = &p->se;\n\tint task_sleep = flags & DEQUEUE_SLEEP;\n\tint idle_h_nr_running = task_has_idle_policy(p);\n\tbool was_sched_idle = sched_idle_rq(rq);\n\n\tutil_est_dequeue(&rq->cfs, p);\n\n\tfor_each_sched_entity(se) {\n\t\tcfs_rq = cfs_rq_of(se);\n\t\tdequeue_entity(cfs_rq, se, flags);\n\n\t\tcfs_rq->h_nr_running--;\n\t\tcfs_rq->idle_h_nr_running -= idle_h_nr_running;\n\n\t\tif (cfs_rq_is_idle(cfs_rq))\n\t\t\tidle_h_nr_running = 1;\n\n\t\t/* end evaluation on encountering a throttled cfs_rq */\n\t\tif (cfs_rq_throttled(cfs_rq))\n\t\t\tgoto dequeue_throttle;\n\n\t\t/* Don't dequeue parent if it has other entities besides us */\n\t\tif (cfs_rq->load.weight) {\n\t\t\t/* Avoid re-evaluating load for this entity: */\n\t\t\tse = parent_entity(se);\n\t\t\t/*\n\t\t\t * Bias pick_next to pick a task from this cfs_rq, as\n\t\t\t * p is sleeping when it is within its sched_slice.\n\t\t\t */\n\t\t\tif (task_sleep && se && !throttled_hierarchy(cfs_rq))\n\t\t\t\tset_next_buddy(se);\n\t\t\tbreak;\n\t\t}\n\t\tflags |= DEQUEUE_SLEEP;\n\t}\n\n\tfor_each_sched_entity(se) {\n\t\tcfs_rq = cfs_rq_of(se);\n\n\t\tupdate_load_avg(cfs_rq, se, UPDATE_TG);\n\t\tse_update_runnable(se);\n\t\tupdate_cfs_group(se);\n\n\t\tcfs_rq->h_nr_running--;\n\t\tcfs_rq->idle_h_nr_running -= idle_h_nr_running;\n\n\t\tif (cfs_rq_is_idle(cfs_rq))\n\t\t\tidle_h_nr_running = 1;\n\n\t\t/* end evaluation on encountering a throttled cfs_rq */\n\t\tif (cfs_rq_throttled(cfs_rq))\n\t\t\tgoto dequeue_throttle;\n\n\t}\n\n\t/* At this point se is NULL and we are at root level*/\n\tsub_nr_running(rq, 1);\n\n\t/* balance early to pull high priority tasks */\n\tif (unlikely(!was_sched_idle && sched_idle_rq(rq)))\n\t\trq->next_balance = jiffies;\n\ndequeue_throttle:\n\tutil_est_update(&rq->cfs, p, task_sleep);\n\thrtick_update(rq);\n}",
        "static int rcu_nocb_toggle(void *arg)\n{\n\tint cpu;\n\tint maxcpu = -1;\n\tint oldnice = task_nice(current);": "static int rcu_nocb_toggle(void *arg)\n{\n\tint cpu;\n\tint maxcpu = -1;\n\tint oldnice = task_nice(current);\n\tlong r;\n\tDEFINE_TORTURE_RANDOM(rand);\n\tktime_t toggle_delay;\n\tunsigned long toggle_fuzz;\n\tktime_t toggle_interval = ms_to_ktime(nocbs_toggle);\n\n\tVERBOSE_TOROUT_STRING(\"rcu_nocb_toggle task started\");\n\twhile (!rcu_inkernel_boot_has_ended())\n\t\tschedule_timeout_interruptible(HZ / 10);\n\tfor_each_online_cpu(cpu)\n\t\tmaxcpu = cpu;\n\tWARN_ON(maxcpu < 0);\n\tif (toggle_interval > ULONG_MAX)\n\t\ttoggle_fuzz = ULONG_MAX >> 3;\n\telse\n\t\ttoggle_fuzz = toggle_interval >> 3;\n\tif (toggle_fuzz <= 0)\n\t\ttoggle_fuzz = NSEC_PER_USEC;\n\tdo {\n\t\tr = torture_random(&rand);\n\t\tcpu = (r >> 4) % (maxcpu + 1);\n\t\tif (r & 0x1) {\n\t\t\trcu_nocb_cpu_offload(cpu);\n\t\t\tatomic_long_inc(&n_nocb_offload);\n\t\t} else {\n\t\t\trcu_nocb_cpu_deoffload(cpu);\n\t\t\tatomic_long_inc(&n_nocb_deoffload);\n\t\t}\n\t\ttoggle_delay = torture_random(&rand) % toggle_fuzz + toggle_interval;\n\t\tset_current_state(TASK_INTERRUPTIBLE);\n\t\tschedule_hrtimeout(&toggle_delay, HRTIMER_MODE_REL);\n\t\tif (stutter_wait(\"rcu_nocb_toggle\"))\n\t\t\tsched_set_normal(current, oldnice);\n\t} while (!torture_must_stop());\n\ttorture_kthread_stopping(\"rcu_nocb_toggle\");\n\treturn 0;\n}",
        "static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)\n{\n\tint nixlf_count = rvu_get_nixlf_count(rvu);\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tint rsvd, err;": "static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)\n{\n\tint nixlf_count = rvu_get_nixlf_count(rvu);\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tint rsvd, err;\n\tu16 index;\n\tint cntr;\n\tu64 cfg;\n\n\t/* Actual number of MCAM entries vary by entry size */\n\tcfg = (rvu_read64(rvu, blkaddr,\n\t\t\t  NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;\n\tmcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;\n\tmcam->keysize = cfg;\n\n\t/* Number of banks combined per MCAM entry */\n\tif (cfg == NPC_MCAM_KEY_X4)\n\t\tmcam->banks_per_entry = 4;\n\telse if (cfg == NPC_MCAM_KEY_X2)\n\t\tmcam->banks_per_entry = 2;\n\telse\n\t\tmcam->banks_per_entry = 1;\n\n\t/* Reserve one MCAM entry for each of the NIX LF to\n\t * guarantee space to install default matching DMAC rule.\n\t * Also reserve 2 MCAM entries for each PF for default\n\t * channel based matching or 'bcast & promisc' matching to\n\t * support BCAST and PROMISC modes of operation for PFs.\n\t * PF0 is excluded.\n\t */\n\trsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +\n\t\t((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);\n\tif (mcam->total_entries <= rsvd) {\n\t\tdev_warn(rvu->dev,\n\t\t\t \"Insufficient NPC MCAM size %d for pkt I/O, exiting\\n\",\n\t\t\t mcam->total_entries);\n\t\treturn -ENOMEM;\n\t}\n\n\tmcam->bmap_entries = mcam->total_entries - rsvd;\n\tmcam->nixlf_offset = mcam->bmap_entries;\n\tmcam->pf_offset = mcam->nixlf_offset + nixlf_count;\n\n\t/* Allocate bitmaps for managing MCAM entries */\n\tmcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),\n\t\t\t\t  sizeof(long), GFP_KERNEL);\n\tif (!mcam->bmap)\n\t\treturn -ENOMEM;\n\n\tmcam->bmap_reverse = devm_kcalloc(rvu->dev,\n\t\t\t\t\t  BITS_TO_LONGS(mcam->bmap_entries),\n\t\t\t\t\t  sizeof(long), GFP_KERNEL);\n\tif (!mcam->bmap_reverse)\n\t\treturn -ENOMEM;\n\n\tmcam->bmap_fcnt = mcam->bmap_entries;\n\n\t/* Alloc memory for saving entry to RVU PFFUNC allocation mapping */\n\tmcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,\n\t\t\t\t\t    sizeof(u16), GFP_KERNEL);\n\tif (!mcam->entry2pfvf_map)\n\t\treturn -ENOMEM;\n\n\t/* Reserve 1/8th of MCAM entries at the bottom for low priority\n\t * allocations and another 1/8th at the top for high priority\n\t * allocations.\n\t */\n\tmcam->lprio_count = mcam->bmap_entries / 8;\n\tif (mcam->lprio_count > BITS_PER_LONG)\n\t\tmcam->lprio_count = round_down(mcam->lprio_count,\n\t\t\t\t\t       BITS_PER_LONG);\n\tmcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;\n\tmcam->hprio_count = mcam->lprio_count;\n\tmcam->hprio_end = mcam->hprio_count;\n\n\n\t/* Allocate bitmap for managing MCAM counters and memory\n\t * for saving counter to RVU PFFUNC allocation mapping.\n\t */\n\terr = rvu_alloc_bitmap(&mcam->counters);\n\tif (err)\n\t\treturn err;\n\n\tmcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,\n\t\t\t\t\t   sizeof(u16), GFP_KERNEL);\n\tif (!mcam->cntr2pfvf_map)\n\t\tgoto free_mem;\n\n\t/* Alloc memory for MCAM entry to counter mapping and for tracking\n\t * counter's reference count.\n\t */\n\tmcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,\n\t\t\t\t\t    sizeof(u16), GFP_KERNEL);\n\tif (!mcam->entry2cntr_map)\n\t\tgoto free_mem;\n\n\tmcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,\n\t\t\t\t\t sizeof(u16), GFP_KERNEL);\n\tif (!mcam->cntr_refcnt)\n\t\tgoto free_mem;\n\n\t/* Alloc memory for saving target device of mcam rule */\n\tmcam->entry2target_pffunc = devm_kcalloc(rvu->dev, mcam->total_entries,\n\t\t\t\t\t\t sizeof(u16), GFP_KERNEL);\n\tif (!mcam->entry2target_pffunc)\n\t\tgoto free_mem;\n\n\tfor (index = 0; index < mcam->bmap_entries; index++) {\n\t\tmcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;\n\t\tmcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;\n\t}\n\n\tfor (cntr = 0; cntr < mcam->counters.max; cntr++)\n\t\tmcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;\n\n\tmutex_init(&mcam->lock);\n\n\treturn 0;\n\nfree_mem:\n\tkfree(mcam->counters.bmap);\n\treturn -ENOMEM;\n}",
        "static void smc_llc_rmt_delete_rkey(struct smc_link_group *lgr)\n{\n\tstruct smc_llc_msg_delete_rkey *llc;\n\tstruct smc_llc_qentry *qentry;\n\tstruct smc_link *link;": "static void smc_llc_rmt_delete_rkey(struct smc_link_group *lgr)\n{\n\tstruct smc_llc_msg_delete_rkey *llc;\n\tstruct smc_llc_qentry *qentry;\n\tstruct smc_link *link;\n\tu8 err_mask = 0;\n\tint i, max;\n\n\tqentry = lgr->llc_flow_rmt.qentry;\n\tllc = &qentry->msg.delete_rkey;\n\tlink = qentry->link;\n\n\tif (lgr->smc_version == SMC_V2) {\n\t\tstruct smc_llc_msg_delete_rkey_v2 *llcv2;\n\n\t\tmemcpy(lgr->wr_rx_buf_v2, llc, sizeof(*llc));\n\t\tllcv2 = (struct smc_llc_msg_delete_rkey_v2 *)lgr->wr_rx_buf_v2;\n\t\tllcv2->num_inval_rkeys = 0;\n\n\t\tmax = min_t(u8, llcv2->num_rkeys, SMC_LLC_RKEYS_PER_MSG_V2);\n\t\tfor (i = 0; i < max; i++) {\n\t\t\tif (smc_rtoken_delete(link, llcv2->rkey[i]))\n\t\t\t\tllcv2->num_inval_rkeys++;\n\t\t}\n\t\tmemset(&llc->rkey[0], 0, sizeof(llc->rkey));\n\t\tmemset(&llc->reserved2, 0, sizeof(llc->reserved2));\n\t\tsmc_llc_init_msg_hdr(&llc->hd, link->lgr, sizeof(*llc));\n\t\tif (llcv2->num_inval_rkeys) {\n\t\t\tllc->hd.flags |= SMC_LLC_FLAG_RKEY_NEG;\n\t\t\tllc->err_mask = llcv2->num_inval_rkeys;\n\t\t}\n\t\tgoto finish;\n\t}\n\n\tmax = min_t(u8, llc->num_rkeys, SMC_LLC_DEL_RKEY_MAX);\n\tfor (i = 0; i < max; i++) {\n\t\tif (smc_rtoken_delete(link, llc->rkey[i]))\n\t\t\terr_mask |= 1 << (SMC_LLC_DEL_RKEY_MAX - 1 - i);\n\t}\n\tif (err_mask) {\n\t\tllc->hd.flags |= SMC_LLC_FLAG_RKEY_NEG;\n\t\tllc->err_mask = err_mask;\n\t}\nfinish:\n\tllc->hd.flags |= SMC_LLC_FLAG_RESP;\n\tsmc_llc_send_message(link, &qentry->msg);\n\tsmc_llc_flow_qentry_del(&lgr->llc_flow_rmt);\n}",
        "static int ca0132_set_vipsource(struct hda_codec *codec, int val)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp;\n": "static int ca0132_set_vipsource(struct hda_codec *codec, int val)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp;\n\n\tif (spec->dsp_state != DSP_DOWNLOADED)\n\t\treturn 0;\n\n\t/* if CrystalVoice if off, vipsource should be 0 */\n\tif (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||\n\t    (val == 0)) {\n\t\tchipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);\n\t\tchipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);\n\t\tchipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);\n\t\tif (spec->cur_mic_type == DIGITAL_MIC)\n\t\t\ttmp = FLOAT_TWO;\n\t\telse\n\t\t\ttmp = FLOAT_ONE;\n\t\tdspio_set_uint_param(codec, 0x80, 0x00, tmp);\n\t\ttmp = FLOAT_ZERO;\n\t\tdspio_set_uint_param(codec, 0x80, 0x05, tmp);\n\t} else {\n\t\tchipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);\n\t\tchipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);\n\t\tif (spec->cur_mic_type == DIGITAL_MIC)\n\t\t\ttmp = FLOAT_TWO;\n\t\telse\n\t\t\ttmp = FLOAT_ONE;\n\t\tdspio_set_uint_param(codec, 0x80, 0x00, tmp);\n\t\ttmp = FLOAT_ONE;\n\t\tdspio_set_uint_param(codec, 0x80, 0x05, tmp);\n\t\tmsleep(20);\n\t\tchipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);\n\t}\n\n\treturn 1;\n}",
        "static int ctc2_slope(int y1, int y0, int x1, int x0)\n{\n\tconst int shift_val = 8;\n\tconst int max_slope = (1 << IA_CSS_CTC_COEF_SHIFT) - 1;\n\tint dy = y1 - y0;": "static int ctc2_slope(int y1, int y0, int x1, int x0)\n{\n\tconst int shift_val = 8;\n\tconst int max_slope = (1 << IA_CSS_CTC_COEF_SHIFT) - 1;\n\tint dy = y1 - y0;\n\tint dx = x1 - x0;\n\tint rounding = (dx + 1) >> 1;\n\tint dy_shift = dy << shift_val;\n\tint slope, dydx;\n\n\t/*Protection for parameter values, & avoiding zero divisions*/\n\tassert(y0 >= 0 && y0 <= max_slope);\n\tassert(y1 >= 0 && y1 <= max_slope);\n\tassert(x0 >= 0 && x0 <= max_slope);\n\tassert(x1 > 0 && x1 <= max_slope);\n\tassert(dx > 0);\n\n\tif (dy < 0)\n\t\trounding = -rounding;\n\tslope = (int)(dy_shift + rounding) / dx;\n\n\t/*the slope must lie within the range\n\t  (-max_slope-1) >= (dydx) >= (max_slope)\n\t*/\n\tif (slope <= -max_slope - 1) {\n\t\tdydx = -max_slope - 1;\n\t} else if (slope >= max_slope) {\n\t\tdydx = max_slope;\n\t} else {\n\t\tdydx = slope;\n\t}\n\n\treturn dydx;\n}",
        "static void list_version_get_info(struct target_type *tt, void *param)\n{\n    struct vers_iter *info = param;\n\n    /* Check space - it might have changed since the first iteration */": "static void list_version_get_info(struct target_type *tt, void *param)\n{\n    struct vers_iter *info = param;\n\n    /* Check space - it might have changed since the first iteration */\n    if ((char *)info->vers + sizeof(tt->version) + strlen(tt->name) + 1 >\n\tinfo->end) {\n\n\tinfo->flags = DM_BUFFER_FULL_FLAG;\n\treturn;\n    }\n\n    if (info->old_vers)\n\tinfo->old_vers->next = (uint32_t) ((void *)info->vers -\n\t\t\t\t\t   (void *)info->old_vers);\n    info->vers->version[0] = tt->version[0];\n    info->vers->version[1] = tt->version[1];\n    info->vers->version[2] = tt->version[2];\n    info->vers->next = 0;\n    strcpy(info->vers->name, tt->name);\n\n    info->old_vers = info->vers;\n    info->vers = align_ptr(((void *) ++info->vers) + strlen(tt->name) + 1);\n}",
        "static void cfi_tell_features(struct cfi_pri_intelext *extp)\n{\n        int i;\n        printk(\"  Feature/Command Support: %4.4X\\n\", extp->FeatureSupport);\n\tprintk(\"     - Chip Erase:         %s\\n\", extp->FeatureSupport&1?\"supported\":\"unsupported\");": "static void cfi_tell_features(struct cfi_pri_intelext *extp)\n{\n        int i;\n        printk(\"  Feature/Command Support: %4.4X\\n\", extp->FeatureSupport);\n\tprintk(\"     - Chip Erase:         %s\\n\", extp->FeatureSupport&1?\"supported\":\"unsupported\");\n\tprintk(\"     - Suspend Erase:      %s\\n\", extp->FeatureSupport&2?\"supported\":\"unsupported\");\n\tprintk(\"     - Suspend Program:    %s\\n\", extp->FeatureSupport&4?\"supported\":\"unsupported\");\n\tprintk(\"     - Legacy Lock/Unlock: %s\\n\", extp->FeatureSupport&8?\"supported\":\"unsupported\");\n\tprintk(\"     - Queued Erase:       %s\\n\", extp->FeatureSupport&16?\"supported\":\"unsupported\");\n\tprintk(\"     - Instant block lock: %s\\n\", extp->FeatureSupport&32?\"supported\":\"unsupported\");\n\tprintk(\"     - Protection Bits:    %s\\n\", extp->FeatureSupport&64?\"supported\":\"unsupported\");\n\tprintk(\"     - Page-mode read:     %s\\n\", extp->FeatureSupport&128?\"supported\":\"unsupported\");\n\tprintk(\"     - Synchronous read:   %s\\n\", extp->FeatureSupport&256?\"supported\":\"unsupported\");\n\tfor (i=9; i<32; i++) {\n\t\tif (extp->FeatureSupport & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X:      supported\\n\", i);\n\t}\n\n\tprintk(\"  Supported functions after Suspend: %2.2X\\n\", extp->SuspendCmdSupport);\n\tprintk(\"     - Program after Erase Suspend: %s\\n\", extp->SuspendCmdSupport&1?\"supported\":\"unsupported\");\n\tfor (i=1; i<8; i++) {\n\t\tif (extp->SuspendCmdSupport & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X:               supported\\n\", i);\n\t}\n\n\tprintk(\"  Block Status Register Mask: %4.4X\\n\", extp->BlkStatusRegMask);\n\tprintk(\"     - Lock Bit Active:      %s\\n\", extp->BlkStatusRegMask&1?\"yes\":\"no\");\n\tprintk(\"     - Valid Bit Active:     %s\\n\", extp->BlkStatusRegMask&2?\"yes\":\"no\");\n\tfor (i=2; i<16; i++) {\n\t\tif (extp->BlkStatusRegMask & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X Active: yes\\n\",i);\n\t}\n\n\tprintk(\"  Vcc Logic Supply Optimum Program/Erase Voltage: %d.%d V\\n\",\n\t       extp->VccOptimal >> 8, extp->VccOptimal & 0xf);\n\tif (extp->VppOptimal)\n\t\tprintk(\"  Vpp Programming Supply Optimum Program/Erase Voltage: %d.%d V\\n\",\n\t\t       extp->VppOptimal >> 8, extp->VppOptimal & 0xf);\n}",
        "static void send_changed_ts(int fd, struct sockaddr_ll *daddr)\n{\n\tstatic char buf[MAX_HDR_LEN + PAYLOAD_LEN];\n\tstatic char extpkt[sizeof(buf) + TCPOLEN_TSTAMP_APPA];\n\tint pkt_size = total_hdr_len + PAYLOAD_LEN + TCPOLEN_TSTAMP_APPA;": "static void send_changed_ts(int fd, struct sockaddr_ll *daddr)\n{\n\tstatic char buf[MAX_HDR_LEN + PAYLOAD_LEN];\n\tstatic char extpkt[sizeof(buf) + TCPOLEN_TSTAMP_APPA];\n\tint pkt_size = total_hdr_len + PAYLOAD_LEN + TCPOLEN_TSTAMP_APPA;\n\n\tcreate_packet(buf, 0, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt, buf, 0, 0);\n\twrite_packet(fd, extpkt, pkt_size, daddr);\n\n\tcreate_packet(buf, PAYLOAD_LEN, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt, buf, 0, 0);\n\twrite_packet(fd, extpkt, pkt_size, daddr);\n\n\tcreate_packet(buf, PAYLOAD_LEN * 2, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt, buf, 100, 0);\n\twrite_packet(fd, extpkt, pkt_size, daddr);\n\n\tcreate_packet(buf, PAYLOAD_LEN * 3, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt, buf, 100, 1);\n\twrite_packet(fd, extpkt, pkt_size, daddr);\n\n\tcreate_packet(buf, PAYLOAD_LEN * 4, 0, PAYLOAD_LEN, 0);\n\tadd_standard_tcp_options(extpkt, buf, 100, 2);\n\twrite_packet(fd, extpkt, pkt_size, daddr);\n}",
        "static bool sugov_should_update_freq(struct sugov_policy *sg_policy, u64 time)\n{\n\ts64 delta_ns;\n\n\t/*": "static bool sugov_should_update_freq(struct sugov_policy *sg_policy, u64 time)\n{\n\ts64 delta_ns;\n\n\t/*\n\t * Since cpufreq_update_util() is called with rq->lock held for\n\t * the @target_cpu, our per-CPU data is fully serialized.\n\t *\n\t * However, drivers cannot in general deal with cross-CPU\n\t * requests, so while get_next_freq() will work, our\n\t * sugov_update_commit() call may not for the fast switching platforms.\n\t *\n\t * Hence stop here for remote requests if they aren't supported\n\t * by the hardware, as calculating the frequency is pointless if\n\t * we cannot in fact act on it.\n\t *\n\t * This is needed on the slow switching platforms too to prevent CPUs\n\t * going offline from leaving stale IRQ work items behind.\n\t */\n\tif (!cpufreq_this_cpu_can_update(sg_policy->policy))\n\t\treturn false;\n\n\tif (unlikely(sg_policy->limits_changed)) {\n\t\tsg_policy->limits_changed = false;\n\t\tsg_policy->need_freq_update = true;\n\t\treturn true;\n\t}\n\n\tdelta_ns = time - sg_policy->last_freq_update_time;\n\n\treturn delta_ns >= sg_policy->freq_update_delay_ns;\n}",
        "static int j1939_session_tx_dat(struct j1939_session *session)\n{\n\tstruct j1939_priv *priv = session->priv;\n\tstruct j1939_sk_buff_cb *se_skcb;\n\tint offset, pkt_done, pkt_end;": "static int j1939_session_tx_dat(struct j1939_session *session)\n{\n\tstruct j1939_priv *priv = session->priv;\n\tstruct j1939_sk_buff_cb *se_skcb;\n\tint offset, pkt_done, pkt_end;\n\tunsigned int len, pdelay;\n\tstruct sk_buff *se_skb;\n\tconst u8 *tpdat;\n\tint ret = 0;\n\tu8 dat[8];\n\n\tse_skb = j1939_session_skb_get_by_offset(session, session->pkt.tx * 7);\n\tif (!se_skb)\n\t\treturn -ENOBUFS;\n\n\tse_skcb = j1939_skb_to_cb(se_skb);\n\ttpdat = se_skb->data;\n\tret = 0;\n\tpkt_done = 0;\n\tif (session->skcb.addr.type != J1939_ETP &&\n\t    j1939_cb_is_broadcast(&session->skcb))\n\t\tpkt_end = session->pkt.total;\n\telse\n\t\tpkt_end = session->pkt.last;\n\n\twhile (session->pkt.tx < pkt_end) {\n\t\tdat[0] = session->pkt.tx - session->pkt.dpo + 1;\n\t\toffset = (session->pkt.tx * 7) - se_skcb->offset;\n\t\tlen =  se_skb->len - offset;\n\t\tif (len > 7)\n\t\t\tlen = 7;\n\n\t\tif (offset + len > se_skb->len) {\n\t\t\tnetdev_err_once(priv->ndev,\n\t\t\t\t\t\"%s: 0x%p: requested data outside of queued buffer: offset %i, len %i, pkt.tx: %i\\n\",\n\t\t\t\t\t__func__, session, se_skcb->offset,\n\t\t\t\t\tse_skb->len , session->pkt.tx);\n\t\t\tret = -EOVERFLOW;\n\t\t\tgoto out_free;\n\t\t}\n\n\t\tif (!len) {\n\t\t\tret = -ENOBUFS;\n\t\t\tbreak;\n\t\t}\n\n\t\tmemcpy(&dat[1], &tpdat[offset], len);\n\t\tret = j1939_tp_tx_dat(session, dat, len + 1);\n\t\tif (ret < 0) {\n\t\t\t/* ENOBUFS == CAN interface TX queue is full */\n\t\t\tif (ret != -ENOBUFS)\n\t\t\t\tnetdev_alert(priv->ndev,\n\t\t\t\t\t     \"%s: 0x%p: queue data error: %i\\n\",\n\t\t\t\t\t     __func__, session, ret);\n\t\t\tbreak;\n\t\t}\n\n\t\tsession->last_txcmd = 0xff;\n\t\tpkt_done++;\n\t\tsession->pkt.tx++;\n\t\tpdelay = j1939_cb_is_broadcast(&session->skcb) ? 50 :\n\t\t\tj1939_tp_packet_delay;\n\n\t\tif (session->pkt.tx < session->pkt.total && pdelay) {\n\t\t\tj1939_tp_schedule_txtimer(session, pdelay);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (pkt_done)\n\t\tj1939_tp_set_rxtimeout(session, 250);\n\n out_free:\n\tif (ret)\n\t\tkfree_skb(se_skb);\n\telse\n\t\tconsume_skb(se_skb);\n\n\treturn ret;\n}",
        "static int vphn_unpack_associativity(const long *packed, __be32 *unpacked)\n{\n\t__be64 be_packed[VPHN_REGISTER_COUNT];\n\tint i, nr_assoc_doms = 0;\n\tconst __be16 *field = (const __be16 *) be_packed;": "static int vphn_unpack_associativity(const long *packed, __be32 *unpacked)\n{\n\t__be64 be_packed[VPHN_REGISTER_COUNT];\n\tint i, nr_assoc_doms = 0;\n\tconst __be16 *field = (const __be16 *) be_packed;\n\tu16 last = 0;\n\tbool is_32bit = false;\n\n#define VPHN_FIELD_UNUSED\t(0xffff)\n#define VPHN_FIELD_MSB\t\t(0x8000)\n#define VPHN_FIELD_MASK\t\t(~VPHN_FIELD_MSB)\n\n\t/* Let's fix the values returned by plpar_hcall9() */\n\tfor (i = 0; i < VPHN_REGISTER_COUNT; i++)\n\t\tbe_packed[i] = cpu_to_be64(packed[i]);\n\n\tfor (i = 1; i < VPHN_ASSOC_BUFSIZE; i++) {\n\t\tu16 new = be16_to_cpup(field++);\n\n\t\tif (is_32bit) {\n\t\t\t/*\n\t\t\t * Let's concatenate the 16 bits of this field to the\n\t\t\t * 15 lower bits of the previous field\n\t\t\t */\n\t\t\tunpacked[++nr_assoc_doms] =\n\t\t\t\tcpu_to_be32(last << 16 | new);\n\t\t\tis_32bit = false;\n\t\t} else if (new == VPHN_FIELD_UNUSED)\n\t\t\t/* This is the list terminator */\n\t\t\tbreak;\n\t\telse if (new & VPHN_FIELD_MSB) {\n\t\t\t/* Data is in the lower 15 bits of this field */\n\t\t\tunpacked[++nr_assoc_doms] =\n\t\t\t\tcpu_to_be32(new & VPHN_FIELD_MASK);\n\t\t} else {\n\t\t\t/*\n\t\t\t * Data is in the lower 15 bits of this field\n\t\t\t * concatenated with the next 16 bit field\n\t\t\t */\n\t\t\tlast = new;\n\t\t\tis_32bit = true;\n\t\t}\n\t}\n\n\t/* The first cell contains the length of the property */\n\tunpacked[0] = cpu_to_be32(nr_assoc_doms);\n\n\treturn nr_assoc_doms;\n}",
        "static void __reg_combine_32_into_64(struct bpf_reg_state *reg)\n{\n\t/* special case when 64-bit register has upper 32-bit register\n\t * zeroed. Typically happens after zext or <<32, >>32 sequence\n\t * allowing us to use 32-bit bounds directly,": "static void __reg_combine_32_into_64(struct bpf_reg_state *reg)\n{\n\t/* special case when 64-bit register has upper 32-bit register\n\t * zeroed. Typically happens after zext or <<32, >>32 sequence\n\t * allowing us to use 32-bit bounds directly,\n\t */\n\tif (tnum_equals_const(tnum_clear_subreg(reg->var_off), 0)) {\n\t\t__reg_assign_32_into_64(reg);\n\t} else {\n\t\t/* Otherwise the best we can do is push lower 32bit known and\n\t\t * unknown bits into register (var_off set from jmp logic)\n\t\t * then learn as much as possible from the 64-bit tnum\n\t\t * known and unknown bits. The previous smin/smax bounds are\n\t\t * invalid here because of jmp32 compare so mark them unknown\n\t\t * so they do not impact tnum bounds calculation.\n\t\t */\n\t\t__mark_reg64_unbounded(reg);\n\t\t__update_reg_bounds(reg);\n\t}\n\n\t/* Intersecting with the old var_off might have improved our bounds\n\t * slightly.  e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc),\n\t * then new var_off is (0; 0x7f...fc) which improves our umax.\n\t */\n\t__reg_deduce_bounds(reg);\n\t__reg_bound_offset(reg);\n\t__update_reg_bounds(reg);\n}",
        "static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_conn_enable_disable *req;\n\tstruct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;\n\tunion l5cm_specific_data l5_data;": "static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_conn_enable_disable *req;\n\tstruct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;\n\tunion l5cm_specific_data l5_data;\n\tint ret;\n\tu32 cid, l5_cid;\n\tstruct cnic_local *cp = dev->cnic_priv;\n\n\treq = (struct fcoe_kwqe_conn_enable_disable *) kwqe;\n\tcid = req->context_id;\n\tl5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;\n\n\tif (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {\n\t\tnetdev_err(dev->netdev, \"fcoe_enable size too big\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tfcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);\n\tif (!fcoe_enable)\n\t\treturn -ENOMEM;\n\n\tmemset(fcoe_enable, 0, sizeof(*fcoe_enable));\n\tmemcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));\n\tret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,\n\t\t\t\t  FCOE_CONNECTION_TYPE, &l5_data);\n\treturn ret;\n}",
        "static void drxj_reset_mode(struct drxj_data *ext_attr)\n{\n\t/* Initialize default AFE configuration for QAM */\n\tif (ext_attr->has_lna) {\n\t\t/* IF AGC off, PGA active */": "static void drxj_reset_mode(struct drxj_data *ext_attr)\n{\n\t/* Initialize default AFE configuration for QAM */\n\tif (ext_attr->has_lna) {\n\t\t/* IF AGC off, PGA active */\n#ifndef DRXJ_VSB_ONLY\n\t\text_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;\n\t\text_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;\n\t\text_attr->qam_pga_cfg = 140 + (11 * 13);\n#endif\n\t\text_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;\n\t\text_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;\n\t\text_attr->vsb_pga_cfg = 140 + (11 * 13);\n\t} else {\n\t\t/* IF AGC on, PGA not active */\n#ifndef DRXJ_VSB_ONLY\n\t\text_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;\n\t\text_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;\n\t\text_attr->qam_if_agc_cfg.min_output_level = 0;\n\t\text_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;\n\t\text_attr->qam_if_agc_cfg.speed = 3;\n\t\text_attr->qam_if_agc_cfg.top = 1297;\n\t\text_attr->qam_pga_cfg = 140;\n#endif\n\t\text_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;\n\t\text_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;\n\t\text_attr->vsb_if_agc_cfg.min_output_level = 0;\n\t\text_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;\n\t\text_attr->vsb_if_agc_cfg.speed = 3;\n\t\text_attr->vsb_if_agc_cfg.top = 1024;\n\t\text_attr->vsb_pga_cfg = 140;\n\t}\n\t/* TODO: remove min_output_level and max_output_level for both QAM and VSB after */\n\t/* mc has not used them */\n#ifndef DRXJ_VSB_ONLY\n\text_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;\n\text_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;\n\text_attr->qam_rf_agc_cfg.min_output_level = 0;\n\text_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;\n\text_attr->qam_rf_agc_cfg.speed = 3;\n\text_attr->qam_rf_agc_cfg.top = 9500;\n\text_attr->qam_rf_agc_cfg.cut_off_current = 4000;\n\text_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;\n\text_attr->qam_pre_saw_cfg.reference = 0x07;\n\text_attr->qam_pre_saw_cfg.use_pre_saw = true;\n#endif\n\t/* Initialize default AFE configuration for VSB */\n\text_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;\n\text_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;\n\text_attr->vsb_rf_agc_cfg.min_output_level = 0;\n\text_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;\n\text_attr->vsb_rf_agc_cfg.speed = 3;\n\text_attr->vsb_rf_agc_cfg.top = 9500;\n\text_attr->vsb_rf_agc_cfg.cut_off_current = 4000;\n\text_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;\n\text_attr->vsb_pre_saw_cfg.reference = 0x07;\n\text_attr->vsb_pre_saw_cfg.use_pre_saw = true;\n}",
        "static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)\n{\n\t/*\n\t * On older versions of the flash the xSPI Profile 1.0 table has the\n\t * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.": "static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)\n{\n\t/*\n\t * On older versions of the flash the xSPI Profile 1.0 table has the\n\t * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.\n\t */\n\tif (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)\n\t\tnor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =\n\t\t\tSPINOR_OP_CYPRESS_RD_FAST;\n\n\t/* This flash is also missing the 4-byte Page Program opcode bit. */\n\tspi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],\n\t\t\t\tSPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);\n\t/*\n\t * Since xSPI Page Program opcode is backward compatible with\n\t * Legacy SPI, use Legacy SPI opcode there as well.\n\t */\n\tspi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],\n\t\t\t\tSPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);\n\n\t/*\n\t * The xSPI Profile 1.0 table advertises the number of additional\n\t * address bytes needed for Read Status Register command as 0 but the\n\t * actual value for that is 4.\n\t */\n\tnor->params->rdsr_addr_nbytes = 4;\n}",
        "static int imgu_css_hw_start_sp(struct imgu_css *css, int sp)\n{\n\tvoid __iomem *const base = css->base;\n\tstruct imgu_fw_info *bi = &css->fwp->binary_header[css->fw_sp[sp]];\n\tstruct imgu_abi_sp_init_dmem_cfg dmem_cfg = {": "static int imgu_css_hw_start_sp(struct imgu_css *css, int sp)\n{\n\tvoid __iomem *const base = css->base;\n\tstruct imgu_fw_info *bi = &css->fwp->binary_header[css->fw_sp[sp]];\n\tstruct imgu_abi_sp_init_dmem_cfg dmem_cfg = {\n\t\t.ddr_data_addr = css->binary[css->fw_sp[sp]].daddr\n\t\t\t+ bi->blob.data_source,\n\t\t.dmem_data_addr = bi->blob.data_target,\n\t\t.dmem_bss_addr = bi->blob.bss_target,\n\t\t.data_size = bi->blob.data_size,\n\t\t.bss_size = bi->blob.bss_size,\n\t\t.sp_id = sp,\n\t};\n\n\twrites(&dmem_cfg, sizeof(dmem_cfg), base +\n\t       IMGU_REG_SP_DMEM_BASE(sp) + bi->info.sp.init_dmem_data);\n\n\twritel(bi->info.sp.sp_entry, base + IMGU_REG_SP_START_ADDR(sp));\n\n\twritel(readl(base + IMGU_REG_SP_CTRL(sp))\n\t\t| IMGU_CTRL_START | IMGU_CTRL_RUN, base + IMGU_REG_SP_CTRL(sp));\n\n\tif (imgu_hw_wait(css->base, IMGU_REG_SP_DMEM_BASE(sp)\n\t\t\t + bi->info.sp.sw_state,\n\t\t\t ~0, IMGU_ABI_SP_SWSTATE_INITIALIZED))\n\t\treturn -EIO;\n\n\treturn 0;\n}",
        "static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev)\n{\n\tstruct r8192_priv *priv = rtllib_priv(dev);\n\tu8 i, max_rssi_index = 0, min_rssi_index = 0;\n\tu8 sec_rssi_index = 0, rf_num = 0;": "static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev)\n{\n\tstruct r8192_priv *priv = rtllib_priv(dev);\n\tu8 i, max_rssi_index = 0, min_rssi_index = 0;\n\tu8 sec_rssi_index = 0, rf_num = 0;\n\tu8 tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0;\n\tu8 cck_default_Rx = 0x2;\n\tu8 cck_optional_Rx = 0x3;\n\tlong tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0;\n\tu8 cck_rx_ver2_max_index = 0;\n\tu8 cck_rx_ver2_sec_index = 0;\n\tu8 cur_rf_rssi;\n\tlong cur_cck_pwdb;\n\tstatic u8 disabled_rf_cnt, cck_Rx_Path_initialized;\n\tu8 update_cck_rx_path;\n\n\tif (priv->rf_type != RF_2T4R)\n\t\treturn;\n\n\tif (!cck_Rx_Path_initialized) {\n\t\tDM_RxPathSelTable.cck_Rx_path = (rtl92e_readb(dev, 0xa07)&0xf);\n\t\tcck_Rx_Path_initialized = 1;\n\t}\n\n\tDM_RxPathSelTable.disabledRF = 0xf;\n\tDM_RxPathSelTable.disabledRF &= ~(rtl92e_readb(dev, 0xc04));\n\n\tif (priv->rtllib->mode == WIRELESS_MODE_B)\n\t\tDM_RxPathSelTable.cck_method = CCK_Rx_Version_2;\n\n\tfor (i = 0; i < RF90_PATH_MAX; i++) {\n\t\tDM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];\n\n\t\tif (priv->brfpath_rxenable[i]) {\n\t\t\trf_num++;\n\t\t\tcur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];\n\n\t\t\tif (rf_num == 1) {\n\t\t\t\tmax_rssi_index = min_rssi_index = sec_rssi_index = i;\n\t\t\t\ttmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;\n\t\t\t} else if (rf_num == 2) {\n\t\t\t\tif (cur_rf_rssi >= tmp_max_rssi) {\n\t\t\t\t\ttmp_max_rssi = cur_rf_rssi;\n\t\t\t\t\tmax_rssi_index = i;\n\t\t\t\t} else {\n\t\t\t\t\ttmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;\n\t\t\t\t\tsec_rssi_index = min_rssi_index = i;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (cur_rf_rssi > tmp_max_rssi) {\n\t\t\t\t\ttmp_sec_rssi = tmp_max_rssi;\n\t\t\t\t\tsec_rssi_index = max_rssi_index;\n\t\t\t\t\ttmp_max_rssi = cur_rf_rssi;\n\t\t\t\t\tmax_rssi_index = i;\n\t\t\t\t} else if (cur_rf_rssi == tmp_max_rssi) {\n\t\t\t\t\ttmp_sec_rssi = cur_rf_rssi;\n\t\t\t\t\tsec_rssi_index = i;\n\t\t\t\t} else if ((cur_rf_rssi < tmp_max_rssi) &&\n\t\t\t\t\t   (cur_rf_rssi > tmp_sec_rssi)) {\n\t\t\t\t\ttmp_sec_rssi = cur_rf_rssi;\n\t\t\t\t\tsec_rssi_index = i;\n\t\t\t\t} else if (cur_rf_rssi == tmp_sec_rssi) {\n\t\t\t\t\tif (tmp_sec_rssi == tmp_min_rssi) {\n\t\t\t\t\t\ttmp_sec_rssi = cur_rf_rssi;\n\t\t\t\t\t\tsec_rssi_index = i;\n\t\t\t\t\t}\n\t\t\t\t} else if ((cur_rf_rssi < tmp_sec_rssi) &&\n\t\t\t\t\t   (cur_rf_rssi > tmp_min_rssi)) {\n\t\t\t\t\t;\n\t\t\t\t} else if (cur_rf_rssi == tmp_min_rssi) {\n\t\t\t\t\tif (tmp_sec_rssi == tmp_min_rssi) {\n\t\t\t\t\t\ttmp_min_rssi = cur_rf_rssi;\n\t\t\t\t\t\tmin_rssi_index = i;\n\t\t\t\t\t}\n\t\t\t\t} else if (cur_rf_rssi < tmp_min_rssi) {\n\t\t\t\t\ttmp_min_rssi = cur_rf_rssi;\n\t\t\t\t\tmin_rssi_index = i;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\trf_num = 0;\n\tif (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) {\n\t\tfor (i = 0; i < RF90_PATH_MAX; i++) {\n\t\t\tif (priv->brfpath_rxenable[i]) {\n\t\t\t\trf_num++;\n\t\t\t\tcur_cck_pwdb =\n\t\t\t\t\t DM_RxPathSelTable.cck_pwdb_sta[i];\n\n\t\t\t\tif (rf_num == 1) {\n\t\t\t\t\tcck_rx_ver2_max_index = i;\n\t\t\t\t\tcck_rx_ver2_sec_index = i;\n\t\t\t\t\ttmp_cck_max_pwdb = cur_cck_pwdb;\n\t\t\t\t\ttmp_cck_min_pwdb = cur_cck_pwdb;\n\t\t\t\t\ttmp_cck_sec_pwdb = cur_cck_pwdb;\n\t\t\t\t} else if (rf_num == 2) {\n\t\t\t\t\tif (cur_cck_pwdb >= tmp_cck_max_pwdb) {\n\t\t\t\t\t\ttmp_cck_max_pwdb = cur_cck_pwdb;\n\t\t\t\t\t\tcck_rx_ver2_max_index = i;\n\t\t\t\t\t} else {\n\t\t\t\t\t\ttmp_cck_sec_pwdb = cur_cck_pwdb;\n\t\t\t\t\t\ttmp_cck_min_pwdb = cur_cck_pwdb;\n\t\t\t\t\t\tcck_rx_ver2_sec_index = i;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif (cur_cck_pwdb > tmp_cck_max_pwdb) {\n\t\t\t\t\t\ttmp_cck_sec_pwdb =\n\t\t\t\t\t\t\t tmp_cck_max_pwdb;\n\t\t\t\t\t\tcck_rx_ver2_sec_index =\n\t\t\t\t\t\t\t cck_rx_ver2_max_index;\n\t\t\t\t\t\ttmp_cck_max_pwdb = cur_cck_pwdb;\n\t\t\t\t\t\tcck_rx_ver2_max_index = i;\n\t\t\t\t\t} else if (cur_cck_pwdb ==\n\t\t\t\t\t\t   tmp_cck_max_pwdb) {\n\t\t\t\t\t\ttmp_cck_sec_pwdb = cur_cck_pwdb;\n\t\t\t\t\t\tcck_rx_ver2_sec_index = i;\n\t\t\t\t\t} else if (PWDB_IN_RANGE) {\n\t\t\t\t\t\ttmp_cck_sec_pwdb = cur_cck_pwdb;\n\t\t\t\t\t\tcck_rx_ver2_sec_index = i;\n\t\t\t\t\t} else if (cur_cck_pwdb ==\n\t\t\t\t\t\t   tmp_cck_sec_pwdb) {\n\t\t\t\t\t\tif (tmp_cck_sec_pwdb ==\n\t\t\t\t\t\t    tmp_cck_min_pwdb) {\n\t\t\t\t\t\t\ttmp_cck_sec_pwdb =\n\t\t\t\t\t\t\t\t cur_cck_pwdb;\n\t\t\t\t\t\t\tcck_rx_ver2_sec_index =\n\t\t\t\t\t\t\t\t i;\n\t\t\t\t\t\t}\n\t\t\t\t\t} else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) &&\n\t\t\t\t\t\t   (cur_cck_pwdb > tmp_cck_min_pwdb)) {\n\t\t\t\t\t\t;\n\t\t\t\t\t} else if (cur_cck_pwdb == tmp_cck_min_pwdb) {\n\t\t\t\t\t\tif (tmp_cck_sec_pwdb == tmp_cck_min_pwdb)\n\t\t\t\t\t\t\ttmp_cck_min_pwdb = cur_cck_pwdb;\n\t\t\t\t\t} else if (cur_cck_pwdb < tmp_cck_min_pwdb) {\n\t\t\t\t\t\ttmp_cck_min_pwdb = cur_cck_pwdb;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t}\n\t\t}\n\t}\n\n\tupdate_cck_rx_path = 0;\n\tif (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) {\n\t\tcck_default_Rx = cck_rx_ver2_max_index;\n\t\tcck_optional_Rx = cck_rx_ver2_sec_index;\n\t\tif (tmp_cck_max_pwdb != -64)\n\t\t\tupdate_cck_rx_path = 1;\n\t}\n\n\tif (tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) {\n\t\tif ((tmp_max_rssi - tmp_min_rssi) >=\n\t\t     DM_RxPathSelTable.diff_TH) {\n\t\t\tDM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] =\n\t\t\t\t tmp_max_rssi+5;\n\t\t\trtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,\n\t\t\t\t\t  0x1<<min_rssi_index, 0x0);\n\t\t\trtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,\n\t\t\t\t\t  0x1<<min_rssi_index, 0x0);\n\t\t\tdisabled_rf_cnt++;\n\t\t}\n\t\tif (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) {\n\t\t\tcck_default_Rx = max_rssi_index;\n\t\t\tcck_optional_Rx = sec_rssi_index;\n\t\t\tif (tmp_max_rssi)\n\t\t\t\tupdate_cck_rx_path = 1;\n\t\t}\n\t}\n\n\tif (update_cck_rx_path) {\n\t\tDM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2) |\n\t\t\t\t\t\t(cck_optional_Rx);\n\t\trtl92e_set_bb_reg(dev, rCCK0_AFESetting, 0x0f000000,\n\t\t\t\t  DM_RxPathSelTable.cck_Rx_path);\n\t}\n\n\tif (DM_RxPathSelTable.disabledRF) {\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tif ((DM_RxPathSelTable.disabledRF>>i) & 0x1) {\n\t\t\t\tif (tmp_max_rssi >=\n\t\t\t\t    DM_RxPathSelTable.rf_enable_rssi_th[i]) {\n\t\t\t\t\trtl92e_set_bb_reg(dev,\n\t\t\t\t\t\t\t  rOFDM0_TRxPathEnable,\n\t\t\t\t\t\t\t  0x1 << i, 0x1);\n\t\t\t\t\trtl92e_set_bb_reg(dev,\n\t\t\t\t\t\t\t  rOFDM1_TRxPathEnable,\n\t\t\t\t\t\t\t  0x1 << i, 0x1);\n\t\t\t\t\tDM_RxPathSelTable.rf_enable_rssi_th[i]\n\t\t\t\t\t\t = 100;\n\t\t\t\t\tdisabled_rf_cnt--;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}",
        "static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)\n{\n\tstruct wm_adsp *dsp;\n\tint ret;\n": "static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)\n{\n\tstruct wm_adsp *dsp;\n\tint ret;\n\n\tdsp = &cs35l41->dsp;\n\tdsp->part = \"cs35l41\";\n\tdsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */\n\tdsp->toggle_preload = true;\n\n\tcs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);\n\n\tret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tret = wm_halo_init(dsp);\n\tif (ret) {\n\t\tdev_err(cs35l41->dev, \"wm_halo_init failed: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC,\n\t\t\t   CS35L41_INPUT_SRC_VPMON);\n\tif (ret < 0) {\n\t\tdev_err(cs35l41->dev, \"Write INPUT_SRC_VPMON failed: %d\\n\", ret);\n\t\tgoto err_dsp;\n\t}\n\tret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC,\n\t\t\t   CS35L41_INPUT_SRC_CLASSH);\n\tif (ret < 0) {\n\t\tdev_err(cs35l41->dev, \"Write INPUT_SRC_CLASSH failed: %d\\n\", ret);\n\t\tgoto err_dsp;\n\t}\n\tret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,\n\t\t\t   CS35L41_INPUT_SRC_TEMPMON);\n\tif (ret < 0) {\n\t\tdev_err(cs35l41->dev, \"Write INPUT_SRC_TEMPMON failed: %d\\n\", ret);\n\t\tgoto err_dsp;\n\t}\n\tret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,\n\t\t\t   CS35L41_INPUT_SRC_RSVD);\n\tif (ret < 0) {\n\t\tdev_err(cs35l41->dev, \"Write INPUT_SRC_RSVD failed: %d\\n\", ret);\n\t\tgoto err_dsp;\n\t}\n\n\treturn 0;\n\nerr_dsp:\n\twm_adsp2_remove(dsp);\n\n\treturn ret;\n}",
        "static int nv_tx_done_optimized(struct net_device *dev, int limit)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu32 flags;\n\tint tx_work = 0;": "static int nv_tx_done_optimized(struct net_device *dev, int limit)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu32 flags;\n\tint tx_work = 0;\n\tstruct ring_desc_ex *orig_get_tx = np->get_tx.ex;\n\tunsigned long bytes_cleaned = 0;\n\n\twhile ((np->get_tx.ex != np->put_tx.ex) &&\n\t       !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&\n\t       (tx_work < limit)) {\n\n\t\tnv_unmap_txskb(np, np->get_tx_ctx);\n\n\t\tif (flags & NV_TX2_LASTPACKET) {\n\t\t\tif (unlikely(flags & NV_TX2_ERROR)) {\n\t\t\t\tif ((flags & NV_TX2_RETRYERROR)\n\t\t\t\t    && !(flags & NV_TX2_RETRYCOUNT_MASK)) {\n\t\t\t\t\tif (np->driver_data & DEV_HAS_GEAR_MODE)\n\t\t\t\t\t\tnv_gear_backoff_reseed(dev);\n\t\t\t\t\telse\n\t\t\t\t\t\tnv_legacybackoff_reseed(dev);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tunsigned int len;\n\n\t\t\t\tu64_stats_update_begin(&np->swstats_tx_syncp);\n\t\t\t\tnv_txrx_stats_inc(stat_tx_packets);\n\t\t\t\tlen = np->get_tx_ctx->skb->len;\n\t\t\t\tnv_txrx_stats_add(stat_tx_bytes, len);\n\t\t\t\tu64_stats_update_end(&np->swstats_tx_syncp);\n\t\t\t}\n\n\t\t\tbytes_cleaned += np->get_tx_ctx->skb->len;\n\t\t\tdev_kfree_skb_any(np->get_tx_ctx->skb);\n\t\t\tnp->get_tx_ctx->skb = NULL;\n\t\t\ttx_work++;\n\n\t\t\tif (np->tx_limit)\n\t\t\t\tnv_tx_flip_ownership(dev);\n\t\t}\n\n\t\tif (unlikely(np->get_tx.ex++ == np->last_tx.ex))\n\t\t\tnp->get_tx.ex = np->tx_ring.ex;\n\t\tif (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))\n\t\t\tnp->get_tx_ctx = np->tx_skb;\n\t}\n\n\tnetdev_completed_queue(np->dev, tx_work, bytes_cleaned);\n\n\tif (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {\n\t\tnp->tx_stop = 0;\n\t\tnetif_wake_queue(dev);\n\t}\n\treturn tx_work;\n}",
        "static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tu64 nibble_ena, rx_kex, tx_kex;": "static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tu64 nibble_ena, rx_kex, tx_kex;\n\tu8 intf;\n\n\t/* Reserve last counter for MCAM RX miss action which is set to\n\t * drop packet. This way we will know how many pkts didn't match\n\t * any MCAM entry.\n\t */\n\tmcam->counters.max--;\n\tmcam->rx_miss_act_cntr = mcam->counters.max;\n\n\trx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_RX];\n\ttx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_TX];\n\tnibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);\n\n\tnibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena);\n\tif (nibble_ena) {\n\t\ttx_kex &= ~NPC_PARSE_NIBBLE;\n\t\ttx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);\n\t\tnpc_mkex_default.keyx_cfg[NIX_INTF_TX] = tx_kex;\n\t}\n\n\t/* Configure RX interfaces */\n\tfor (intf = 0; intf < hw->npc_intfs; intf++) {\n\t\tif (is_npc_intf_tx(intf))\n\t\t\tcontinue;\n\n\t\t/* Set RX MCAM search key size. LA..LE (ltype only) + Channel */\n\t\trvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),\n\t\t\t    rx_kex);\n\n\t\t/* If MCAM lookup doesn't result in a match, drop the received\n\t\t * packet. And map this action to a counter to count dropped\n\t\t * packets.\n\t\t */\n\t\trvu_write64(rvu, blkaddr,\n\t\t\t    NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP);\n\n\t\t/* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9]\n\t\t * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0]\n\t\t */\n\t\trvu_write64(rvu, blkaddr,\n\t\t\t    NPC_AF_INTFX_MISS_STAT_ACT(intf),\n\t\t\t    ((mcam->rx_miss_act_cntr >> 9) << 12) |\n\t\t\t    hw->npc_stat_ena | mcam->rx_miss_act_cntr);\n\t}\n\n\t/* Configure TX interfaces */\n\tfor (intf = 0; intf < hw->npc_intfs; intf++) {\n\t\tif (is_npc_intf_rx(intf))\n\t\t\tcontinue;\n\n\t\t/* Extract Ltypes LID_LA to LID_LE */\n\t\trvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),\n\t\t\t    tx_kex);\n\n\t\t/* Set TX miss action to UCAST_DEFAULT i.e\n\t\t * transmit the packet on NIX LF SQ's default channel.\n\t\t */\n\t\trvu_write64(rvu, blkaddr,\n\t\t\t    NPC_AF_INTFX_MISS_ACT(intf),\n\t\t\t    NIX_TX_ACTIONOP_UCAST_DEFAULT);\n\t}\n}",
        "static void or51211_reset(struct dvb_frontend * fe)\n{\n\tstruct dvb_bt8xx_card *bt = fe->dvb->priv;\n\n\t/* RESET DEVICE": "static void or51211_reset(struct dvb_frontend * fe)\n{\n\tstruct dvb_bt8xx_card *bt = fe->dvb->priv;\n\n\t/* RESET DEVICE\n\t * reset is controlled by GPIO-0\n\t * when set to 0 causes reset and when to 1 for normal op\n\t * must remain reset for 128 clock cycles on a 50Mhz clock\n\t * also PRM1 PRM2 & PRM4 are controlled by GPIO-1,GPIO-2 & GPIO-4\n\t * We assume that the reset has be held low long enough or we\n\t * have been reset by a power on.  When the driver is unloaded\n\t * reset set to 0 so if reloaded we have been reset.\n\t */\n\t/* reset & PRM1,2&4 are outputs */\n\tint ret = bttv_gpio_enable(bt->bttv_nr, 0x001F, 0x001F);\n\tif (ret != 0)\n\t\tpr_warn(\"or51211: Init Error - Can't Reset DVR (%i)\\n\", ret);\n\tbttv_write_gpio(bt->bttv_nr, 0x001F, 0x0000);   /* Reset */\n\tmsleep(20);\n\t/* Now set for normal operation */\n\tbttv_write_gpio(bt->bttv_nr, 0x0001F, 0x0001);\n\t/* wait for operation to begin */\n\tmsleep(500);\n}",
        "static void test_v3_redist_ipa_range_check_at_vcpu_run(void)\n{\n\tstruct vm_gic v;\n\tint ret, i;\n\tuint64_t addr;": "static void test_v3_redist_ipa_range_check_at_vcpu_run(void)\n{\n\tstruct vm_gic v;\n\tint ret, i;\n\tuint64_t addr;\n\n\tv = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, 1);\n\n\t/* Set space for 3 redists, we have 1 vcpu, so this succeeds. */\n\taddr = max_phys_size - (3 * 2 * 0x10000);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t\t KVM_VGIC_V3_ADDR_TYPE_REDIST, &addr, true);\n\n\taddr = 0x00000;\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\tKVM_VGIC_V3_ADDR_TYPE_DIST, &addr, true);\n\n\t/* Add the rest of the VCPUs */\n\tfor (i = 1; i < NR_VCPUS; ++i)\n\t\tvm_vcpu_add_default(v.vm, i, guest_code);\n\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,\n\t\t\t  KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);\n\n\t/* Attempt to run a vcpu without enough redist space. */\n\tret = run_vcpu(v.vm, 2);\n\tTEST_ASSERT(ret && errno == EINVAL,\n\t\t\"redist base+size above PA range detected on 1st vcpu run\");\n\n\tvm_gic_destroy(&v);\n}",
        "static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr)\n{\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tu64 hw_const;\n": "static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr)\n{\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tu64 hw_const;\n\n\thw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);\n\n\t/* On OcteonTx2 DWRR quantum is directly configured into each of\n\t * the transmit scheduler queues. And PF/VF drivers were free to\n\t * config any value upto 2^24.\n\t * On CN10K, HW is modified, the quantum configuration at scheduler\n\t * queues is in terms of weight. And SW needs to setup a base DWRR MTU\n\t * at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do\n\t * 'DWRR MTU * weight' to get the quantum.\n\t *\n\t * Check if HW uses a common MTU for all DWRR quantum configs.\n\t * On OcteonTx2 this register field is '0'.\n\t */\n\tif (((hw_const >> 56) & 0x10) == 0x10)\n\t\thw->cap.nix_common_dwrr_mtu = true;\n}",
        "static int connect_dfs_root(struct mount_ctx *mnt_ctx, struct dfs_cache_tgt_list *root_tl)\n{\n\tint rc;\n\tchar *full_path;\n\tstruct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;": "static int connect_dfs_root(struct mount_ctx *mnt_ctx, struct dfs_cache_tgt_list *root_tl)\n{\n\tint rc;\n\tchar *full_path;\n\tstruct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;\n\tstruct smb3_fs_context *ctx = mnt_ctx->fs_ctx;\n\tstruct dfs_cache_tgt_iterator *tit;\n\n\t/* Put initial connections as they might be shared with other mounts.  We need unique dfs\n\t * connections per mount to properly failover, so mount_get_dfs_conns() must be used from\n\t * now on.\n\t */\n\tmount_put_conns(mnt_ctx);\n\tmount_get_dfs_conns(mnt_ctx);\n\tset_root_ses(mnt_ctx);\n\n\tfull_path = build_unc_path_to_root(ctx, cifs_sb, true);\n\tif (IS_ERR(full_path))\n\t\treturn PTR_ERR(full_path);\n\n\tmnt_ctx->origin_fullpath = dfs_cache_canonical_path(ctx->UNC, cifs_sb->local_nls,\n\t\t\t\t\t\t\t    cifs_remap(cifs_sb));\n\tif (IS_ERR(mnt_ctx->origin_fullpath)) {\n\t\trc = PTR_ERR(mnt_ctx->origin_fullpath);\n\t\tmnt_ctx->origin_fullpath = NULL;\n\t\tgoto out;\n\t}\n\n\t/* Try all dfs root targets */\n\tfor (rc = -ENOENT, tit = dfs_cache_get_tgt_iterator(root_tl);\n\t     tit; tit = dfs_cache_get_next_tgt(root_tl, tit)) {\n\t\trc = connect_dfs_target(mnt_ctx, full_path, mnt_ctx->origin_fullpath + 1, tit);\n\t\tif (!rc) {\n\t\t\tmnt_ctx->leaf_fullpath = kstrdup(mnt_ctx->origin_fullpath, GFP_KERNEL);\n\t\t\tif (!mnt_ctx->leaf_fullpath)\n\t\t\t\trc = -ENOMEM;\n\t\t\tbreak;\n\t\t}\n\t}\n\nout:\n\tkfree(full_path);\n\treturn rc;\n}",
        "static int check_anonymous_memory_mapping(int mem_type, int mode, int mapping, int tag_check)\n{\n\tchar *ptr, *map_ptr;\n\tint run, result, map_size;\n\tint item = sizeof(sizes)/sizeof(int);": "static int check_anonymous_memory_mapping(int mem_type, int mode, int mapping, int tag_check)\n{\n\tchar *ptr, *map_ptr;\n\tint run, result, map_size;\n\tint item = sizeof(sizes)/sizeof(int);\n\n\titem = sizeof(sizes)/sizeof(int);\n\tmte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG);\n\tfor (run = 0; run < item; run++) {\n\t\tmap_size = sizes[run] + OVERFLOW + UNDERFLOW;\n\t\tmap_ptr = (char *)mte_allocate_memory(map_size, mem_type, mapping, false);\n\t\tif (check_allocated_memory(map_ptr, map_size, mem_type, false) != KSFT_PASS)\n\t\t\treturn KSFT_FAIL;\n\n\t\tptr = map_ptr + UNDERFLOW;\n\t\tmte_initialize_current_context(mode, (uintptr_t)ptr, sizes[run]);\n\t\t/* Only mte enabled memory will allow tag insertion */\n\t\tptr = mte_insert_tags((void *)ptr, sizes[run]);\n\t\tif (!ptr || cur_mte_cxt.fault_valid == true) {\n\t\t\tksft_print_msg(\"FAIL: Insert tags on anonymous mmap memory\\n\");\n\t\t\tmunmap((void *)map_ptr, map_size);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tresult = check_mte_memory(ptr, sizes[run], mode, tag_check);\n\t\tmte_clear_tags((void *)ptr, sizes[run]);\n\t\tmte_free_memory((void *)map_ptr, map_size, mem_type, false);\n\t\tif (result == KSFT_FAIL)\n\t\t\treturn KSFT_FAIL;\n\t}\n\treturn KSFT_PASS;\n}",
        "static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)\n{\n\tint delay = 1;\n\tu32 id;\n": "static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)\n{\n\tint delay = 1;\n\tu32 id;\n\n\t/*\n\t * After reset, the device should not silently discard config\n\t * requests, but it may still indicate that it needs more time by\n\t * responding to them with CRS completions.  The Root Port will\n\t * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete\n\t * the read (except when CRS SV is enabled and the read was for the\n\t * Vendor ID; in that case it synthesizes 0x0001 data).\n\t *\n\t * Wait for the device to return a non-CRS completion.  Read the\n\t * Command register instead of Vendor ID so we don't have to\n\t * contend with the CRS SV value.\n\t */\n\tpci_read_config_dword(dev, PCI_COMMAND, &id);\n\twhile (PCI_POSSIBLE_ERROR(id)) {\n\t\tif (delay > timeout) {\n\t\t\tpci_warn(dev, \"not ready %dms after %s; giving up\\n\",\n\t\t\t\t delay - 1, reset_type);\n\t\t\treturn -ENOTTY;\n\t\t}\n\n\t\tif (delay > 1000)\n\t\t\tpci_info(dev, \"not ready %dms after %s; waiting\\n\",\n\t\t\t\t delay - 1, reset_type);\n\n\t\tmsleep(delay);\n\t\tdelay *= 2;\n\t\tpci_read_config_dword(dev, PCI_COMMAND, &id);\n\t}\n\n\tif (delay > 1000)\n\t\tpci_info(dev, \"ready %dms after %s\\n\", delay - 1,\n\t\t\t reset_type);\n\n\treturn 0;\n}",
        "static int alloc_top_down_disjoint_check(void)\n{\n\t/* After allocation, this will point to the \"old\" region */\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];": "static int alloc_top_down_disjoint_check(void)\n{\n\t/* After allocation, this will point to the \"old\" region */\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[0];\n\tstruct region r1;\n\tvoid *allocated_ptr = NULL;\n\n\tphys_addr_t r2_size = SZ_16;\n\t/* Use custom alignment */\n\tphys_addr_t alignment = SMP_CACHE_BYTES * 2;\n\tphys_addr_t total_size;\n\tphys_addr_t expected_start;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SZ_2;\n\tr1.size = SZ_2;\n\n\ttotal_size = r1.size + r2_size;\n\texpected_start = memblock_end_of_DRAM() - alignment;\n\n\tmemblock_reserve(r1.base, r1.size);\n\n\tallocated_ptr = memblock_alloc(r2_size, alignment);\n\n\tassert(allocated_ptr);\n\tassert(rgn1->size == r1.size);\n\tassert(rgn1->base == r1.base);\n\n\tassert(rgn2->size == r2_size);\n\tassert(rgn2->base == expected_start);\n\n\tassert(memblock.reserved.cnt == 2);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static int tsi721_doorbell_init(struct tsi721_device *priv)\n{\n\t/* Outbound Doorbells do not require any setup.\n\t * Tsi721 uses dedicated PCI BAR1 to generate doorbells.\n\t * That BAR1 was mapped during the probe routine.": "static int tsi721_doorbell_init(struct tsi721_device *priv)\n{\n\t/* Outbound Doorbells do not require any setup.\n\t * Tsi721 uses dedicated PCI BAR1 to generate doorbells.\n\t * That BAR1 was mapped during the probe routine.\n\t */\n\n\t/* Initialize Inbound Doorbell processing DPC and queue */\n\tpriv->db_discard_count = 0;\n\tINIT_WORK(&priv->idb_work, tsi721_db_dpc);\n\n\t/* Allocate buffer for inbound doorbells queue */\n\tpriv->idb_base = dma_alloc_coherent(&priv->pdev->dev,\n\t\t\t\t\t    IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,\n\t\t\t\t\t    &priv->idb_dma, GFP_KERNEL);\n\tif (!priv->idb_base)\n\t\treturn -ENOMEM;\n\n\ttsi_debug(DBELL, &priv->pdev->dev,\n\t\t  \"Allocated IDB buffer @ %p (phys = %pad)\",\n\t\t  priv->idb_base, &priv->idb_dma);\n\n\tiowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),\n\t\tpriv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));\n\tiowrite32(((u64)priv->idb_dma >> 32),\n\t\tpriv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));\n\tiowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),\n\t\tpriv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));\n\t/* Enable accepting all inbound doorbells */\n\tiowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));\n\n\tiowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));\n\n\tiowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));\n\n\treturn 0;\n}",
        "static bool throttle_cfs_rq(struct cfs_rq *cfs_rq)\n{\n\tstruct rq *rq = rq_of(cfs_rq);\n\tstruct cfs_bandwidth *cfs_b = tg_cfs_bandwidth(cfs_rq->tg);\n\tstruct sched_entity *se;": "static bool throttle_cfs_rq(struct cfs_rq *cfs_rq)\n{\n\tstruct rq *rq = rq_of(cfs_rq);\n\tstruct cfs_bandwidth *cfs_b = tg_cfs_bandwidth(cfs_rq->tg);\n\tstruct sched_entity *se;\n\tlong task_delta, idle_task_delta, dequeue = 1;\n\n\traw_spin_lock(&cfs_b->lock);\n\t/* This will start the period timer if necessary */\n\tif (__assign_cfs_rq_runtime(cfs_b, cfs_rq, 1)) {\n\t\t/*\n\t\t * We have raced with bandwidth becoming available, and if we\n\t\t * actually throttled the timer might not unthrottle us for an\n\t\t * entire period. We additionally needed to make sure that any\n\t\t * subsequent check_cfs_rq_runtime calls agree not to throttle\n\t\t * us, as we may commit to do cfs put_prev+pick_next, so we ask\n\t\t * for 1ns of runtime rather than just check cfs_b.\n\t\t */\n\t\tdequeue = 0;\n\t} else {\n\t\tlist_add_tail_rcu(&cfs_rq->throttled_list,\n\t\t\t\t  &cfs_b->throttled_cfs_rq);\n\t}\n\traw_spin_unlock(&cfs_b->lock);\n\n\tif (!dequeue)\n\t\treturn false;  /* Throttle no longer required. */\n\n\tse = cfs_rq->tg->se[cpu_of(rq_of(cfs_rq))];\n\n\t/* freeze hierarchy runnable averages while throttled */\n\trcu_read_lock();\n\twalk_tg_tree_from(cfs_rq->tg, tg_throttle_down, tg_nop, (void *)rq);\n\trcu_read_unlock();\n\n\ttask_delta = cfs_rq->h_nr_running;\n\tidle_task_delta = cfs_rq->idle_h_nr_running;\n\tfor_each_sched_entity(se) {\n\t\tstruct cfs_rq *qcfs_rq = cfs_rq_of(se);\n\t\t/* throttled entity or throttle-on-deactivate */\n\t\tif (!se->on_rq)\n\t\t\tgoto done;\n\n\t\tdequeue_entity(qcfs_rq, se, DEQUEUE_SLEEP);\n\n\t\tif (cfs_rq_is_idle(group_cfs_rq(se)))\n\t\t\tidle_task_delta = cfs_rq->h_nr_running;\n\n\t\tqcfs_rq->h_nr_running -= task_delta;\n\t\tqcfs_rq->idle_h_nr_running -= idle_task_delta;\n\n\t\tif (qcfs_rq->load.weight) {\n\t\t\t/* Avoid re-evaluating load for this entity: */\n\t\t\tse = parent_entity(se);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfor_each_sched_entity(se) {\n\t\tstruct cfs_rq *qcfs_rq = cfs_rq_of(se);\n\t\t/* throttled entity or throttle-on-deactivate */\n\t\tif (!se->on_rq)\n\t\t\tgoto done;\n\n\t\tupdate_load_avg(qcfs_rq, se, 0);\n\t\tse_update_runnable(se);\n\n\t\tif (cfs_rq_is_idle(group_cfs_rq(se)))\n\t\t\tidle_task_delta = cfs_rq->h_nr_running;\n\n\t\tqcfs_rq->h_nr_running -= task_delta;\n\t\tqcfs_rq->idle_h_nr_running -= idle_task_delta;\n\t}\n\n\t/* At this point se is NULL and we are at root level*/\n\tsub_nr_running(rq, task_delta);\n\ndone:\n\t/*\n\t * Note: distribution will already see us throttled via the\n\t * throttled-list.  rq->lock protects completion.\n\t */\n\tcfs_rq->throttled = 1;\n\tcfs_rq->throttled_clock = rq_clock(rq);\n\treturn true;\n}",
        "static void rcu_barrier_entrain(struct rcu_data *rdp)\n{\n\tunsigned long gseq = READ_ONCE(rcu_state.barrier_sequence);\n\tunsigned long lseq = READ_ONCE(rdp->barrier_seq_snap);\n": "static void rcu_barrier_entrain(struct rcu_data *rdp)\n{\n\tunsigned long gseq = READ_ONCE(rcu_state.barrier_sequence);\n\tunsigned long lseq = READ_ONCE(rdp->barrier_seq_snap);\n\n\tlockdep_assert_held(&rcu_state.barrier_lock);\n\tif (rcu_seq_state(lseq) || !rcu_seq_state(gseq) || rcu_seq_ctr(lseq) != rcu_seq_ctr(gseq))\n\t\treturn;\n\trcu_barrier_trace(TPS(\"IRQ\"), -1, rcu_state.barrier_sequence);\n\trdp->barrier_head.func = rcu_barrier_callback;\n\tdebug_rcu_head_queue(&rdp->barrier_head);\n\trcu_nocb_lock(rdp);\n\tWARN_ON_ONCE(!rcu_nocb_flush_bypass(rdp, NULL, jiffies));\n\tif (rcu_segcblist_entrain(&rdp->cblist, &rdp->barrier_head)) {\n\t\tatomic_inc(&rcu_state.barrier_cpu_count);\n\t} else {\n\t\tdebug_rcu_head_unqueue(&rdp->barrier_head);\n\t\trcu_barrier_trace(TPS(\"IRQNQ\"), -1, rcu_state.barrier_sequence);\n\t}\n\trcu_nocb_unlock(rdp);\n\tsmp_store_release(&rdp->barrier_seq_snap, gseq);\n}",
        "static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_adapter *adapter = hw->back;\n\tstruct pci_dev *pdev = adapter->pdev;\n\tstruct pci_dev *func0_pdev;": "static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_adapter *adapter = hw->back;\n\tstruct pci_dev *pdev = adapter->pdev;\n\tstruct pci_dev *func0_pdev;\n\n\t/* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices\n\t * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0\n\t * It's not valid for function 0 to be disabled and function 1 is up,\n\t * so the lowest numbered ixgbe dev will be device 0 function 0 on one\n\t * of those two root ports\n\t */\n\tfunc0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));\n\tif (func0_pdev) {\n\t\tif (func0_pdev == pdev)\n\t\t\treturn true;\n\t\telse\n\t\t\treturn false;\n\t}\n\tfunc0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));\n\tif (func0_pdev == pdev)\n\t\treturn true;\n\n\treturn false;\n}",
        "static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)\n{\n\ts64 trailing_overhead_ns, one_byte_write_ns, gap_ns;\n\tstruct idt82p33 *idt82p33 = channel->idt82p33;\n\tint err;": "static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)\n{\n\ts64 trailing_overhead_ns, one_byte_write_ns, gap_ns;\n\tstruct idt82p33 *idt82p33 = channel->idt82p33;\n\tint err;\n\n\tidt82p33->tod_write_overhead_ns = 0;\n\n\terr = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);\n\n\tif (err) {\n\t\tdev_err(idt82p33->dev,\n\t\t\t\"Failed in %s with err %d!\\n\", __func__, err);\n\t\treturn err;\n\t}\n\n\terr = idt82p33_measure_one_byte_write_overhead(channel,\n\t\t\t\t\t\t       &one_byte_write_ns);\n\n\tif (err)\n\t\treturn err;\n\n\terr = idt82p33_measure_tod_write_9_byte_overhead(channel);\n\n\tif (err)\n\t\treturn err;\n\n\ttrailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);\n\n\tidt82p33->tod_write_overhead_ns -= trailing_overhead_ns;\n\n\treturn err;\n}",
        "static void wait_context_tests(void)\n{\n\tprintk(\"  --------------------------------------------------------------------------\\n\");\n\tprintk(\"  | wait context tests |\\n\");\n\tprintk(\"  --------------------------------------------------------------------------\\n\");": "static void wait_context_tests(void)\n{\n\tprintk(\"  --------------------------------------------------------------------------\\n\");\n\tprintk(\"  | wait context tests |\\n\");\n\tprintk(\"  --------------------------------------------------------------------------\\n\");\n\tprintk(\"                                 | rcu  | raw  | spin |mutex |\\n\");\n\tprintk(\"  --------------------------------------------------------------------------\\n\");\n\tprint_testname(\"in hardirq context\");\n\tDO_CONTEXT_TESTCASE_OUTER_LIMITED_PREEMPTIBLE(HARDIRQ);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in hardirq context (not threaded)\");\n\tDO_CONTEXT_TESTCASE_OUTER_NOT_PREEMPTIBLE(NOTTHREADED_HARDIRQ);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in softirq context\");\n\tDO_CONTEXT_TESTCASE_OUTER_LIMITED_PREEMPTIBLE(SOFTIRQ);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in RCU context\");\n\tDO_CONTEXT_TESTCASE_OUTER_LIMITED_PREEMPTIBLE(RCU);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in RCU-bh context\");\n\tDO_CONTEXT_TESTCASE_OUTER_LIMITED_PREEMPTIBLE(RCU_BH);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in RCU-sched context\");\n\tDO_CONTEXT_TESTCASE_OUTER_NOT_PREEMPTIBLE(RCU_SCHED);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in RAW_SPINLOCK context\");\n\tDO_CONTEXT_TESTCASE_OUTER_NOT_PREEMPTIBLE(RAW_SPINLOCK);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in SPINLOCK context\");\n\tDO_CONTEXT_TESTCASE_OUTER_LIMITED_PREEMPTIBLE(SPINLOCK);\n\tpr_cont(\"\\n\");\n\n\tprint_testname(\"in MUTEX context\");\n\tDO_CONTEXT_TESTCASE_OUTER_PREEMPTIBLE(MUTEX);\n\tpr_cont(\"\\n\");\n}",
        "static int ah6_input(struct xfrm_state *x, struct sk_buff *skb)\n{\n\t/*\n\t * Before process AH\n\t * [IPv6][Ext1][Ext2][AH][Dest][Payload]": "static int ah6_input(struct xfrm_state *x, struct sk_buff *skb)\n{\n\t/*\n\t * Before process AH\n\t * [IPv6][Ext1][Ext2][AH][Dest][Payload]\n\t * |<-------------->| hdr_len\n\t *\n\t * To erase AH:\n\t * Keeping copy of cleared headers. After AH processing,\n\t * Moving the pointer of skb->network_header by using skb_pull as long\n\t * as AH header length. Then copy back the copy as long as hdr_len\n\t * If destination header following AH exists, copy it into after [Ext2].\n\t *\n\t * |<>|[IPv6][Ext1][Ext2][Dest][Payload]\n\t * There is offset of AH before IPv6 header after the process.\n\t */\n\n\tu8 *auth_data;\n\tu8 *icv;\n\tu8 *work_iph;\n\tstruct sk_buff *trailer;\n\tstruct crypto_ahash *ahash;\n\tstruct ahash_request *req;\n\tstruct scatterlist *sg;\n\tstruct ip_auth_hdr *ah;\n\tstruct ipv6hdr *ip6h;\n\tstruct ah_data *ahp;\n\tu16 hdr_len;\n\tu16 ah_hlen;\n\tint nexthdr;\n\tint nfrags;\n\tint err = -ENOMEM;\n\tint seqhi_len = 0;\n\t__be32 *seqhi;\n\tint sglists = 0;\n\tstruct scatterlist *seqhisg;\n\n\tif (!pskb_may_pull(skb, sizeof(struct ip_auth_hdr)))\n\t\tgoto out;\n\n\t/* We are going to _remove_ AH header to keep sockets happy,\n\t * so... Later this can change. */\n\tif (skb_unclone(skb, GFP_ATOMIC))\n\t\tgoto out;\n\n\tskb->ip_summed = CHECKSUM_NONE;\n\n\thdr_len = skb_network_header_len(skb);\n\tah = (struct ip_auth_hdr *)skb->data;\n\tahp = x->data;\n\tahash = ahp->ahash;\n\n\tnexthdr = ah->nexthdr;\n\tah_hlen = ipv6_authlen(ah);\n\n\tif (ah_hlen != XFRM_ALIGN8(sizeof(*ah) + ahp->icv_full_len) &&\n\t    ah_hlen != XFRM_ALIGN8(sizeof(*ah) + ahp->icv_trunc_len))\n\t\tgoto out;\n\n\tif (!pskb_may_pull(skb, ah_hlen))\n\t\tgoto out;\n\n\terr = skb_cow_data(skb, 0, &trailer);\n\tif (err < 0)\n\t\tgoto out;\n\tnfrags = err;\n\n\tah = (struct ip_auth_hdr *)skb->data;\n\tip6h = ipv6_hdr(skb);\n\n\tskb_push(skb, hdr_len);\n\n\tif (x->props.flags & XFRM_STATE_ESN) {\n\t\tsglists = 1;\n\t\tseqhi_len = sizeof(*seqhi);\n\t}\n\n\twork_iph = ah_alloc_tmp(ahash, nfrags + sglists, hdr_len +\n\t\t\t\tahp->icv_trunc_len + seqhi_len);\n\tif (!work_iph) {\n\t\terr = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tauth_data = ah_tmp_auth((u8 *)work_iph, hdr_len);\n\tseqhi = (__be32 *)(auth_data + ahp->icv_trunc_len);\n\ticv = ah_tmp_icv(ahash, seqhi, seqhi_len);\n\treq = ah_tmp_req(ahash, icv);\n\tsg = ah_req_sg(ahash, req);\n\tseqhisg = sg + nfrags;\n\n\tmemcpy(work_iph, ip6h, hdr_len);\n\tmemcpy(auth_data, ah->auth_data, ahp->icv_trunc_len);\n\tmemset(ah->auth_data, 0, ahp->icv_trunc_len);\n\n\terr = ipv6_clear_mutable_options(ip6h, hdr_len, XFRM_POLICY_IN);\n\tif (err)\n\t\tgoto out_free;\n\n\tip6h->priority    = 0;\n\tip6h->flow_lbl[0] = 0;\n\tip6h->flow_lbl[1] = 0;\n\tip6h->flow_lbl[2] = 0;\n\tip6h->hop_limit   = 0;\n\n\tsg_init_table(sg, nfrags + sglists);\n\terr = skb_to_sgvec_nomark(skb, sg, 0, skb->len);\n\tif (unlikely(err < 0))\n\t\tgoto out_free;\n\n\tif (x->props.flags & XFRM_STATE_ESN) {\n\t\t/* Attach seqhi sg right after packet payload */\n\t\t*seqhi = XFRM_SKB_CB(skb)->seq.input.hi;\n\t\tsg_set_buf(seqhisg, seqhi, seqhi_len);\n\t}\n\n\tahash_request_set_crypt(req, sg, icv, skb->len + seqhi_len);\n\tahash_request_set_callback(req, 0, ah6_input_done, skb);\n\n\tAH_SKB_CB(skb)->tmp = work_iph;\n\n\terr = crypto_ahash_digest(req);\n\tif (err) {\n\t\tif (err == -EINPROGRESS)\n\t\t\tgoto out;\n\n\t\tgoto out_free;\n\t}\n\n\terr = crypto_memneq(icv, auth_data, ahp->icv_trunc_len) ? -EBADMSG : 0;\n\tif (err)\n\t\tgoto out_free;\n\n\tskb->network_header += ah_hlen;\n\tmemcpy(skb_network_header(skb), work_iph, hdr_len);\n\t__skb_pull(skb, ah_hlen + hdr_len);\n\n\tif (x->props.mode == XFRM_MODE_TUNNEL)\n\t\tskb_reset_transport_header(skb);\n\telse\n\t\tskb_set_transport_header(skb, -hdr_len);\n\n\terr = nexthdr;\n\nout_free:\n\tkfree(work_iph);\nout:\n\treturn err;\n}",
        "static int vss_operate(int operation)\n{\n\tchar match[] = \"/dev/\";\n\tFILE *mounts;\n\tstruct mntent *ent;": "static int vss_operate(int operation)\n{\n\tchar match[] = \"/dev/\";\n\tFILE *mounts;\n\tstruct mntent *ent;\n\tstruct stat sb;\n\tchar errdir[1024] = {0};\n\tchar blkdir[23]; /* /sys/dev/block/XXX:XXX */\n\tunsigned int cmd;\n\tint error = 0, root_seen = 0, save_errno = 0;\n\n\tswitch (operation) {\n\tcase VSS_OP_FREEZE:\n\t\tcmd = FIFREEZE;\n\t\tbreak;\n\tcase VSS_OP_THAW:\n\t\tcmd = FITHAW;\n\t\tbreak;\n\tdefault:\n\t\treturn -1;\n\t}\n\n\tmounts = setmntent(\"/proc/mounts\", \"r\");\n\tif (mounts == NULL)\n\t\treturn -1;\n\n\twhile ((ent = getmntent(mounts))) {\n\t\tif (strncmp(ent->mnt_fsname, match, strlen(match)))\n\t\t\tcontinue;\n\t\tif (stat(ent->mnt_fsname, &sb)) {\n\t\t\tsyslog(LOG_ERR, \"Can't stat: %s; error:%d %s!\",\n\t\t\t       ent->mnt_fsname, errno, strerror(errno));\n\t\t} else {\n\t\t\tsprintf(blkdir, \"/sys/dev/block/%d:%d\",\n\t\t\t\tmajor(sb.st_rdev), minor(sb.st_rdev));\n\t\t\tif (is_dev_loop(blkdir))\n\t\t\t\tcontinue;\n\t\t}\n\t\tif (hasmntopt(ent, MNTOPT_RO) != NULL)\n\t\t\tcontinue;\n\t\tif (strcmp(ent->mnt_type, \"vfat\") == 0)\n\t\t\tcontinue;\n\t\tif (strcmp(ent->mnt_dir, \"/\") == 0) {\n\t\t\troot_seen = 1;\n\t\t\tcontinue;\n\t\t}\n\t\terror |= vss_do_freeze(ent->mnt_dir, cmd);\n\t\tif (operation == VSS_OP_FREEZE) {\n\t\t\tif (error)\n\t\t\t\tgoto err;\n\t\t\tfs_frozen = true;\n\t\t}\n\t}\n\n\tendmntent(mounts);\n\n\tif (root_seen) {\n\t\terror |= vss_do_freeze(\"/\", cmd);\n\t\tif (operation == VSS_OP_FREEZE) {\n\t\t\tif (error)\n\t\t\t\tgoto err;\n\t\t\tfs_frozen = true;\n\t\t}\n\t}\n\n\tif (operation == VSS_OP_THAW && !error)\n\t\tfs_frozen = false;\n\n\tgoto out;\nerr:\n\tsave_errno = errno;\n\tif (ent) {\n\t\tstrncpy(errdir, ent->mnt_dir, sizeof(errdir)-1);\n\t\tendmntent(mounts);\n\t}\n\tvss_operate(VSS_OP_THAW);\n\tfs_frozen = false;\n\t/* Call syslog after we thaw all filesystems */\n\tif (ent)\n\t\tsyslog(LOG_ERR, \"FREEZE of %s failed; error:%d %s\",\n\t\t       errdir, save_errno, strerror(save_errno));\n\telse\n\t\tsyslog(LOG_ERR, \"FREEZE of / failed; error:%d %s\", save_errno,\n\t\t       strerror(save_errno));\nout:\n\treturn error;\n}",
        "static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id)\n{\n#if defined(HAS_TRACER_V2)\n\tu32 start_addr;\n\tu32 start_addr_data;": "static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id)\n{\n#if defined(HAS_TRACER_V2)\n\tu32 start_addr;\n\tu32 start_addr_data;\n\tu32 item_size;\n\tu32 tmp;\n\tu8 tid_val;\n\tenum TRACE_DUMP_FORMAT dump_format;\n\n\tint i, j, max_trace_points, point_num, limit = -1;\n\t/* using a static buffer here as the driver has issues allocating memory */\n\tstatic u32 trace_read_buf[TRACE_BUFF_SIZE] = {0};\n\tstatic struct trace_header_t header;\n\tu8 *header_arr;\n\n\t/* read the header and parse it */\n\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"~~~ Tracer \");\n\tswitch (proc_id) {\n\tcase TRACE_SP0_ID:\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"SP0\");\n\t\tstart_addr = TRACE_SP0_ADDR;\n\t\tstart_addr_data = TRACE_SP0_DATA_ADDR;\n\t\titem_size = TRACE_SP0_ITEM_SIZE;\n\t\tmax_trace_points = TRACE_SP0_MAX_POINTS;\n\t\tbreak;\n\tcase TRACE_SP1_ID:\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"SP1\");\n\t\tstart_addr = TRACE_SP1_ADDR;\n\t\tstart_addr_data = TRACE_SP1_DATA_ADDR;\n\t\titem_size = TRACE_SP1_ITEM_SIZE;\n\t\tmax_trace_points = TRACE_SP1_MAX_POINTS;\n\t\tbreak;\n\tcase TRACE_ISP_ID:\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"ISP\");\n\t\tstart_addr = TRACE_ISP_ADDR;\n\t\tstart_addr_data = TRACE_ISP_DATA_ADDR;\n\t\titem_size = TRACE_ISP_ITEM_SIZE;\n\t\tmax_trace_points = TRACE_ISP_MAX_POINTS;\n\t\tbreak;\n\tdefault:\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,\n\t\t\t\t    \"\\t\\ttraces are not supported for this processor ID - exiting\\n\");\n\t\treturn;\n\t}\n\n\tif (!IS_ISP2401) {\n\t\ttmp = ia_css_device_load_uint32(start_addr);\n\t\tpoint_num = (tmp >> 16) & 0xFFFF;\n\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \" ver %d %d points\\n\", tmp & 0xFF,\n\t\t\t\t    point_num);\n\t} else {\n\t\t/* Loading byte-by-byte as using the master routine had issues */\n\t\theader_arr = (uint8_t *)&header;\n\t\tfor (i = 0; i < (int)sizeof(struct trace_header_t); i++)\n\t\t\theader_arr[i] = ia_css_device_load_uint8(start_addr + (i));\n\n\t\tpoint_num = header.max_tracer_points;\n\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \" ver %d %d points\\n\", header.version,\n\t\t\t\t    point_num);\n\n\t\ttmp = header.version;\n\t}\n\tif ((tmp & 0xFF) != TRACER_VER) {\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"\\t\\tUnknown version - exiting\\n\");\n\t\treturn;\n\t}\n\tif (point_num > max_trace_points) {\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"\\t\\tToo many points - exiting\\n\");\n\t\treturn;\n\t}\n\t/* copy the TPs and find the first 0 */\n\tfor (i = 0; i < point_num; i++) {\n\t\ttrace_read_buf[i] = ia_css_device_load_uint32(start_addr_data +\n\t\t\t\t    (i * item_size));\n\t\tif ((limit == (-1)) && (trace_read_buf[i] == 0))\n\t\t\tlimit = i;\n\t}\n\tif (IS_ISP2401) {\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"Status:\\n\");\n\t\tfor (i = 0; i < SH_CSS_MAX_SP_THREADS; i++)\n\t\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,\n\t\t\t\t\t    \"\\tT%d: %3d (%02x)  %6d (%04x)  %10d (%08x)\\n\", i,\n\t\t\t\t\t    header.thr_status_byte[i], header.thr_status_byte[i],\n\t\t\t\t\t    header.thr_status_word[i], header.thr_status_word[i],\n\t\t\t\t\t    header.thr_status_dword[i], header.thr_status_dword[i]);\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"Scratch:\\n\");\n\t\tfor (i = 0; i < MAX_SCRATCH_DATA; i++)\n\t\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"%10d (%08x)  \",\n\t\t\t\t\t    header.scratch_debug[i], header.scratch_debug[i]);\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"\\n\");\n\t}\n\t/* two 0s in the beginning: empty buffer */\n\tif ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) {\n\t\tia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \"\\t\\tEmpty tracer - exiting\\n\");\n\t\treturn;\n\t}\n\t/* no overrun: start from 0 */\n\tif ((limit == point_num - 1) ||\n\t    /* first 0 is at the end - border case */\n\t    (trace_read_buf[limit + 1] ==\n\t     0))   /* did not make a full cycle after the memset */\n\t\tlimit = 0;\n\t/* overrun: limit is the first non-zero after the first zero */\n\telse\n\t\tlimit++;\n\n\t/* print the TPs */\n\tfor (i = 0; i < point_num; i++) {\n\t\tj = (limit + i) % point_num;\n\t\tif (trace_read_buf[j]) {\n\t\t\tif (!IS_ISP2401) {\n\t\t\t\tTRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);\n\t\t\t} else {\n\t\t\t\ttid_val = FIELD_TID_UNPACK(trace_read_buf[j]);\n\t\t\t\tdump_format = TRACE_DUMP_FORMAT_POINT;\n\n\t\t\t\t/*\n\t\t\t\t* When tid value is 111b, the data will be interpreted differently:\n\t\t\t\t* tid val is ignored, major field contains 2 bits (msb) for format type\n\t\t\t\t*/\n\t\t\t\tif (tid_val == FIELD_TID_SEL_FORMAT_PAT) {\n\t\t\t\t\tdump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);\n\t\t\t\t}\n\t\t\t}\n\t\t\tswitch (dump_format) {\n\t\t\tcase TRACE_DUMP_FORMAT_POINT:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d %d:%d value - %d\\n\",\n\t\t\t\t    j, FIELD_MAJOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_MINOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\t/* ISP2400 */\n\t\t\tcase TRACE_DUMP_FORMAT_VALUE24_HEX:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d, %d, 24bit value %x H\\n\",\n\t\t\t\t    j,\n\t\t\t\t    FIELD_MAJOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_24_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\t/* ISP2400 */\n\t\t\tcase TRACE_DUMP_FORMAT_VALUE24_DEC:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d, %d, 24bit value %d D\\n\",\n\t\t\t\t    j,\n\t\t\t\t    FIELD_MAJOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_24_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\t/* ISP2401 */\n\t\t\tcase TRACE_DUMP_FORMAT_POINT_NO_TID:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d %d:%d value - %x (%d)\\n\",\n\t\t\t\t    j,\n\t\t\t\t    FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_MINOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\t/* ISP2401 */\n\t\t\tcase TRACE_DUMP_FORMAT_VALUE24:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d, %d, 24bit value %x (%d)\\n\",\n\t\t\t\t    j,\n\t\t\t\t    FIELD_MAJOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_24_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_24_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\tcase TRACE_DUMP_FORMAT_VALUE24_TIMING:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d, %d, timing %x\\n\",\n\t\t\t\t    j,\n\t\t\t\t    FIELD_MAJOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_24_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\tcase TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\t\"\\t\\t%d, %d, timing delta %x\\n\",\n\t\t\t\t    j,\n\t\t\t\t    FIELD_MAJOR_UNPACK(trace_read_buf[j]),\n\t\t\t\t    FIELD_VALUE_24_UNPACK(trace_read_buf[j]));\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tia_css_debug_dtrace(\n\t\t\t\t    IA_CSS_DEBUG_TRACE,\n\t\t\t\t    \"no such trace dump format %d\",\n\t\t\t\t    dump_format);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n#else\n\t(void)proc_id;\n#endif /* HAS_TRACER_V2 */\n}",
        "static int __init ip_auto_config(void)\n{\n\t__be32 addr;\n#ifdef IPCONFIG_DYNAMIC\n\tint retries = CONF_OPEN_RETRIES;": "static int __init ip_auto_config(void)\n{\n\t__be32 addr;\n#ifdef IPCONFIG_DYNAMIC\n\tint retries = CONF_OPEN_RETRIES;\n#endif\n\tint err;\n\tunsigned int i, count;\n\n\t/* Initialise all name servers and NTP servers to NONE (but only if the\n\t * \"ip=\" or \"nfsaddrs=\" kernel command line parameters weren't decoded,\n\t * otherwise we'll overwrite the IP addresses specified there)\n\t */\n\tif (ic_set_manually == 0) {\n\t\tic_nameservers_predef();\n\t\tic_ntp_servers_predef();\n\t}\n\n#ifdef CONFIG_PROC_FS\n\tproc_create_single(\"pnp\", 0444, init_net.proc_net, pnp_seq_show);\n\n\tif (ipconfig_proc_net_init() == 0)\n\t\tipconfig_proc_net_create(\"ntp_servers\", &ntp_servers_proc_ops);\n#endif /* CONFIG_PROC_FS */\n\n\tif (!ic_enable)\n\t\treturn 0;\n\n\tpr_debug(\"IP-Config: Entered.\\n\");\n#ifdef IPCONFIG_DYNAMIC\n try_try_again:\n#endif\n\t/* Wait for devices to appear */\n\terr = wait_for_devices();\n\tif (err)\n\t\treturn err;\n\n\t/* Setup all network devices */\n\terr = ic_open_devs();\n\tif (err)\n\t\treturn err;\n\n\t/* Give drivers a chance to settle */\n\tmsleep(CONF_POST_OPEN);\n\n\t/*\n\t * If the config information is insufficient (e.g., our IP address or\n\t * IP address of the boot server is missing or we have multiple network\n\t * interfaces and no default was set), use BOOTP or RARP to get the\n\t * missing values.\n\t */\n\tif (ic_myaddr == NONE ||\n#if defined(CONFIG_ROOT_NFS) || defined(CONFIG_CIFS_ROOT)\n\t    (root_server_addr == NONE &&\n\t     ic_servaddr == NONE &&\n\t     (ROOT_DEV == Root_NFS || ROOT_DEV == Root_CIFS)) ||\n#endif\n\t    ic_first_dev->next) {\n#ifdef IPCONFIG_DYNAMIC\n\t\tif (ic_dynamic() < 0) {\n\t\t\tic_close_devs();\n\n\t\t\t/*\n\t\t\t * I don't know why, but sometimes the\n\t\t\t * eepro100 driver (at least) gets upset and\n\t\t\t * doesn't work the first time it's opened.\n\t\t\t * But then if you close it and reopen it, it\n\t\t\t * works just fine.  So we need to try that at\n\t\t\t * least once before giving up.\n\t\t\t *\n\t\t\t * Also, if the root will be NFS-mounted, we\n\t\t\t * have nowhere to go if DHCP fails.  So we\n\t\t\t * just have to keep trying forever.\n\t\t\t *\n\t\t\t * \t\t\t\t-- Chip\n\t\t\t */\n#ifdef CONFIG_ROOT_NFS\n\t\t\tif (ROOT_DEV ==  Root_NFS) {\n\t\t\t\tpr_err(\"IP-Config: Retrying forever (NFS root)...\\n\");\n\t\t\t\tgoto try_try_again;\n\t\t\t}\n#endif\n#ifdef CONFIG_CIFS_ROOT\n\t\t\tif (ROOT_DEV == Root_CIFS) {\n\t\t\t\tpr_err(\"IP-Config: Retrying forever (CIFS root)...\\n\");\n\t\t\t\tgoto try_try_again;\n\t\t\t}\n#endif\n\n\t\t\tif (--retries) {\n\t\t\t\tpr_err(\"IP-Config: Reopening network devices...\\n\");\n\t\t\t\tgoto try_try_again;\n\t\t\t}\n\n\t\t\t/* Oh, well.  At least we tried. */\n\t\t\tpr_err(\"IP-Config: Auto-configuration of network failed\\n\");\n\t\t\treturn -1;\n\t\t}\n#else /* !DYNAMIC */\n\t\tpr_err(\"IP-Config: Incomplete network configuration information\\n\");\n\t\tic_close_devs();\n\t\treturn -1;\n#endif /* IPCONFIG_DYNAMIC */\n\t} else {\n\t\t/* Device selected manually or only one device -> use it */\n\t\tic_dev = ic_first_dev;\n\t}\n\n\taddr = root_nfs_parse_addr(root_server_path);\n\tif (root_server_addr == NONE)\n\t\troot_server_addr = addr;\n\n\t/*\n\t * Use defaults wherever applicable.\n\t */\n\tif (ic_defaults() < 0)\n\t\treturn -1;\n\n\t/*\n\t * Record which protocol was actually used.\n\t */\n#ifdef IPCONFIG_DYNAMIC\n\tic_proto_used = ic_got_reply | (ic_proto_enabled & IC_USE_DHCP);\n#endif\n\n#ifndef IPCONFIG_SILENT\n\t/*\n\t * Clue in the operator.\n\t */\n\tpr_info(\"IP-Config: Complete:\\n\");\n\n\tpr_info(\"     device=%s, hwaddr=%*phC, ipaddr=%pI4, mask=%pI4, gw=%pI4\\n\",\n\t\tic_dev->dev->name, ic_dev->dev->addr_len, ic_dev->dev->dev_addr,\n\t\t&ic_myaddr, &ic_netmask, &ic_gateway);\n\tpr_info(\"     host=%s, domain=%s, nis-domain=%s\\n\",\n\t\tutsname()->nodename, ic_domain, utsname()->domainname);\n\tpr_info(\"     bootserver=%pI4, rootserver=%pI4, rootpath=%s\",\n\t\t&ic_servaddr, &root_server_addr, root_server_path);\n\tif (ic_dev_mtu)\n\t\tpr_cont(\", mtu=%d\", ic_dev_mtu);\n\t/* Name servers (if any): */\n\tfor (i = 0, count = 0; i < CONF_NAMESERVERS_MAX; i++) {\n\t\tif (ic_nameservers[i] != NONE) {\n\t\t\tif (i == 0)\n\t\t\t\tpr_info(\"     nameserver%u=%pI4\",\n\t\t\t\t\ti, &ic_nameservers[i]);\n\t\t\telse\n\t\t\t\tpr_cont(\", nameserver%u=%pI4\",\n\t\t\t\t\ti, &ic_nameservers[i]);\n\n\t\t\tcount++;\n\t\t}\n\t\tif ((i + 1 == CONF_NAMESERVERS_MAX) && count > 0)\n\t\t\tpr_cont(\"\\n\");\n\t}\n\t/* NTP servers (if any): */\n\tfor (i = 0, count = 0; i < CONF_NTP_SERVERS_MAX; i++) {\n\t\tif (ic_ntp_servers[i] != NONE) {\n\t\t\tif (i == 0)\n\t\t\t\tpr_info(\"     ntpserver%u=%pI4\",\n\t\t\t\t\ti, &ic_ntp_servers[i]);\n\t\t\telse\n\t\t\t\tpr_cont(\", ntpserver%u=%pI4\",\n\t\t\t\t\ti, &ic_ntp_servers[i]);\n\n\t\t\tcount++;\n\t\t}\n\t\tif ((i + 1 == CONF_NTP_SERVERS_MAX) && count > 0)\n\t\t\tpr_cont(\"\\n\");\n\t}\n#endif /* !SILENT */\n\n\t/*\n\t * Close all network devices except the device we've\n\t * autoconfigured and set up routes.\n\t */\n\tif (ic_setup_if() < 0 || ic_setup_routes() < 0)\n\t\terr = -1;\n\telse\n\t\terr = 0;\n\n\tic_close_devs();\n\n\treturn err;\n}",
        "static int timer_cb1(void *map, int *key, struct bpf_timer *timer)\n{\n\t/* increment bss variable twice.\n\t * Once via array timer callback and once via lru timer callback\n\t */": "static int timer_cb1(void *map, int *key, struct bpf_timer *timer)\n{\n\t/* increment bss variable twice.\n\t * Once via array timer callback and once via lru timer callback\n\t */\n\tbss_data += 5;\n\n\t/* *key == 0 - the callback was called for array timer.\n\t * *key == 4 - the callback was called from lru timer.\n\t */\n\tif (*key == ARRAY) {\n\t\tstruct bpf_timer *lru_timer;\n\t\tint lru_key = LRU;\n\n\t\t/* rearm array timer to be called again in ~35 seconds */\n\t\tif (bpf_timer_start(timer, 1ull << 35, 0) != 0)\n\t\t\terr |= 1;\n\n\t\tlru_timer = bpf_map_lookup_elem(&lru, &lru_key);\n\t\tif (!lru_timer)\n\t\t\treturn 0;\n\t\tbpf_timer_set_callback(lru_timer, timer_cb1);\n\t\tif (bpf_timer_start(lru_timer, 0, 0) != 0)\n\t\t\terr |= 2;\n\t} else if (*key == LRU) {\n\t\tint lru_key, i;\n\n\t\tfor (i = LRU + 1;\n\t\t     i <= 100  /* for current LRU eviction algorithm this number\n\t\t\t\t* should be larger than ~ lru->max_entries * 2\n\t\t\t\t*/;\n\t\t     i++) {\n\t\t\tstruct elem init = {};\n\n\t\t\t/* lru_key cannot be used as loop induction variable\n\t\t\t * otherwise the loop will be unbounded.\n\t\t\t */\n\t\t\tlru_key = i;\n\n\t\t\t/* add more elements into lru map to push out current\n\t\t\t * element and force deletion of this timer\n\t\t\t */\n\t\t\tbpf_map_update_elem(map, &lru_key, &init, 0);\n\t\t\t/* look it up to bump it into active list */\n\t\t\tbpf_map_lookup_elem(map, &lru_key);\n\n\t\t\t/* keep adding until *key changes underneath,\n\t\t\t * which means that key/timer memory was reused\n\t\t\t */\n\t\t\tif (*key != LRU)\n\t\t\t\tbreak;\n\t\t}\n\n\t\t/* check that the timer was removed */\n\t\tif (bpf_timer_cancel(timer) != -EINVAL)\n\t\t\terr |= 4;\n\t\tok |= 1;\n\t}\n\treturn 0;\n}",
        "static void mark_vcpu_memory_idle(struct kvm_vm *vm, int vcpu_id)\n{\n\tuint64_t base_gva = perf_test_args.vcpu_args[vcpu_id].gva;\n\tuint64_t pages = perf_test_args.vcpu_args[vcpu_id].pages;\n\tuint64_t page;": "static void mark_vcpu_memory_idle(struct kvm_vm *vm, int vcpu_id)\n{\n\tuint64_t base_gva = perf_test_args.vcpu_args[vcpu_id].gva;\n\tuint64_t pages = perf_test_args.vcpu_args[vcpu_id].pages;\n\tuint64_t page;\n\tuint64_t still_idle = 0;\n\tuint64_t no_pfn = 0;\n\tint page_idle_fd;\n\tint pagemap_fd;\n\n\t/* If vCPUs are using an overlapping region, let vCPU 0 mark it idle. */\n\tif (overlap_memory_access && vcpu_id)\n\t\treturn;\n\n\tpage_idle_fd = open(\"/sys/kernel/mm/page_idle/bitmap\", O_RDWR);\n\tTEST_ASSERT(page_idle_fd > 0, \"Failed to open page_idle.\");\n\n\tpagemap_fd = open(\"/proc/self/pagemap\", O_RDONLY);\n\tTEST_ASSERT(pagemap_fd > 0, \"Failed to open pagemap.\");\n\n\tfor (page = 0; page < pages; page++) {\n\t\tuint64_t gva = base_gva + page * perf_test_args.guest_page_size;\n\t\tuint64_t pfn = lookup_pfn(pagemap_fd, vm, gva);\n\n\t\tif (!pfn) {\n\t\t\tno_pfn++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (is_page_idle(page_idle_fd, pfn)) {\n\t\t\tstill_idle++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tmark_page_idle(page_idle_fd, pfn);\n\t}\n\n\t/*\n\t * Assumption: Less than 1% of pages are going to be swapped out from\n\t * under us during this test.\n\t */\n\tTEST_ASSERT(no_pfn < pages / 100,\n\t\t    \"vCPU %d: No PFN for %\" PRIu64 \" out of %\" PRIu64 \" pages.\",\n\t\t    vcpu_id, no_pfn, pages);\n\n\t/*\n\t * Test that at least 90% of memory has been marked idle (the rest might\n\t * not be marked idle because the pages have not yet made it to an LRU\n\t * list or the translations are still cached in the TLB). 90% is\n\t * arbitrary; high enough that we ensure most memory access went through\n\t * access tracking but low enough as to not make the test too brittle\n\t * over time and across architectures.\n\t */\n\tTEST_ASSERT(still_idle < pages / 10,\n\t\t    \"vCPU%d: Too many pages still idle (%\"PRIu64 \" out of %\"\n\t\t    PRIu64 \").\\n\",\n\t\t    vcpu_id, still_idle, pages);\n\n\tclose(page_idle_fd);\n\tclose(pagemap_fd);\n}",
        "static int ov5648_sensor_power(struct ov5648_sensor *sensor, bool on)\n{\n\t/* Keep initialized to zero for disable label. */\n\tint ret = 0;\n": "static int ov5648_sensor_power(struct ov5648_sensor *sensor, bool on)\n{\n\t/* Keep initialized to zero for disable label. */\n\tint ret = 0;\n\n\t/*\n\t * General notes about the power sequence:\n\t * - power-down GPIO must be active (low) during power-on;\n\t * - reset GPIO state does not matter during power-on;\n\t * - XVCLK must be provided 1 ms before register access;\n\t * - 10 ms are needed between power-down deassert and register access.\n\t */\n\n\t/* Note that regulator-and-GPIO-based power is untested. */\n\tif (on) {\n\t\tgpiod_set_value_cansleep(sensor->reset, 1);\n\t\tgpiod_set_value_cansleep(sensor->powerdown, 1);\n\n\t\tret = regulator_enable(sensor->dovdd);\n\t\tif (ret) {\n\t\t\tdev_err(sensor->dev,\n\t\t\t\t\"failed to enable DOVDD regulator\\n\");\n\t\t\tgoto disable;\n\t\t}\n\n\t\tif (sensor->avdd) {\n\t\t\tret = regulator_enable(sensor->avdd);\n\t\t\tif (ret) {\n\t\t\t\tdev_err(sensor->dev,\n\t\t\t\t\t\"failed to enable AVDD regulator\\n\");\n\t\t\t\tgoto disable;\n\t\t\t}\n\t\t}\n\n\t\tret = regulator_enable(sensor->dvdd);\n\t\tif (ret) {\n\t\t\tdev_err(sensor->dev,\n\t\t\t\t\"failed to enable DVDD regulator\\n\");\n\t\t\tgoto disable;\n\t\t}\n\n\t\t/* According to OV5648 power up diagram. */\n\t\tusleep_range(5000, 10000);\n\n\t\tret = clk_prepare_enable(sensor->xvclk);\n\t\tif (ret) {\n\t\t\tdev_err(sensor->dev, \"failed to enable XVCLK clock\\n\");\n\t\t\tgoto disable;\n\t\t}\n\n\t\tgpiod_set_value_cansleep(sensor->reset, 0);\n\t\tgpiod_set_value_cansleep(sensor->powerdown, 0);\n\n\t\tusleep_range(20000, 25000);\n\t} else {\ndisable:\n\t\tgpiod_set_value_cansleep(sensor->powerdown, 1);\n\t\tgpiod_set_value_cansleep(sensor->reset, 1);\n\n\t\tclk_disable_unprepare(sensor->xvclk);\n\n\t\tregulator_disable(sensor->dvdd);\n\n\t\tif (sensor->avdd)\n\t\t\tregulator_disable(sensor->avdd);\n\n\t\tregulator_disable(sensor->dovdd);\n\t}\n\n\treturn ret;\n}",
        "static int test__expr(struct test_suite *t __maybe_unused, int subtest __maybe_unused)\n{\n\tstruct expr_id_data *val_ptr;\n\tconst char *p;\n\tdouble val, num_cpus, num_cores, num_dies, num_packages;": "static int test__expr(struct test_suite *t __maybe_unused, int subtest __maybe_unused)\n{\n\tstruct expr_id_data *val_ptr;\n\tconst char *p;\n\tdouble val, num_cpus, num_cores, num_dies, num_packages;\n\tint ret;\n\tstruct expr_parse_ctx *ctx;\n\n\tTEST_ASSERT_EQUAL(\"ids_union\", test_ids_union(), 0);\n\n\tctx = expr__ctx_new();\n\tTEST_ASSERT_VAL(\"expr__ctx_new\", ctx);\n\texpr__add_id_val(ctx, strdup(\"FOO\"), 1);\n\texpr__add_id_val(ctx, strdup(\"BAR\"), 2);\n\n\tret = test(ctx, \"1+1\", 2);\n\tret |= test(ctx, \"FOO+BAR\", 3);\n\tret |= test(ctx, \"(BAR/2)%2\", 1);\n\tret |= test(ctx, \"1 - -4\",  5);\n\tret |= test(ctx, \"(FOO-1)*2 + (BAR/2)%2 - -4\",  5);\n\tret |= test(ctx, \"1-1 | 1\", 1);\n\tret |= test(ctx, \"1-1 & 1\", 0);\n\tret |= test(ctx, \"min(1,2) + 1\", 2);\n\tret |= test(ctx, \"max(1,2) + 1\", 3);\n\tret |= test(ctx, \"1+1 if 3*4 else 0\", 2);\n\tret |= test(ctx, \"1.1 + 2.1\", 3.2);\n\tret |= test(ctx, \".1 + 2.\", 2.1);\n\tret |= test(ctx, \"d_ratio(1, 2)\", 0.5);\n\tret |= test(ctx, \"d_ratio(2.5, 0)\", 0);\n\tret |= test(ctx, \"1.1 < 2.2\", 1);\n\tret |= test(ctx, \"2.2 > 1.1\", 1);\n\tret |= test(ctx, \"1.1 < 1.1\", 0);\n\tret |= test(ctx, \"2.2 > 2.2\", 0);\n\tret |= test(ctx, \"2.2 < 1.1\", 0);\n\tret |= test(ctx, \"1.1 > 2.2\", 0);\n\n\tif (ret) {\n\t\texpr__ctx_free(ctx);\n\t\treturn ret;\n\t}\n\n\tp = \"FOO/0\";\n\tret = expr__parse(&val, ctx, p);\n\tTEST_ASSERT_VAL(\"division by zero\", ret == -1);\n\n\tp = \"BAR/\";\n\tret = expr__parse(&val, ctx, p);\n\tTEST_ASSERT_VAL(\"missing operand\", ret == -1);\n\n\texpr__ctx_clear(ctx);\n\tTEST_ASSERT_VAL(\"find ids\",\n\t\t\texpr__find_ids(\"FOO + BAR + BAZ + BOZO\", \"FOO\",\n\t\t\t\t\tctx) == 0);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__size(ctx->ids) == 3);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"BAR\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"BAZ\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"BOZO\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\n\texpr__ctx_clear(ctx);\n\tctx->runtime = 3;\n\tTEST_ASSERT_VAL(\"find ids\",\n\t\t\texpr__find_ids(\"EVENT1\\\\,param\\\\=?@ + EVENT2\\\\,param\\\\=?@\",\n\t\t\t\t\tNULL, ctx) == 0);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__size(ctx->ids) == 2);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"EVENT1,param=3@\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"EVENT2,param=3@\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\n\texpr__ctx_clear(ctx);\n\tTEST_ASSERT_VAL(\"find ids\",\n\t\t\texpr__find_ids(\"dash\\\\-event1 - dash\\\\-event2\",\n\t\t\t\t       NULL, ctx) == 0);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__size(ctx->ids) == 2);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"dash-event1\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids, \"dash-event2\",\n\t\t\t\t\t\t    (void **)&val_ptr));\n\n\t/* Only EVENT1 or EVENT2 need be measured depending on the value of smt_on. */\n\texpr__ctx_clear(ctx);\n\tTEST_ASSERT_VAL(\"find ids\",\n\t\t\texpr__find_ids(\"EVENT1 if #smt_on else EVENT2\",\n\t\t\t\tNULL, ctx) == 0);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__size(ctx->ids) == 1);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__find(ctx->ids,\n\t\t\t\t\t\t  smt_on() ? \"EVENT1\" : \"EVENT2\",\n\t\t\t\t\t\t  (void **)&val_ptr));\n\n\t/* The expression is a constant 1.0 without needing to evaluate EVENT1. */\n\texpr__ctx_clear(ctx);\n\tTEST_ASSERT_VAL(\"find ids\",\n\t\t\texpr__find_ids(\"1.0 if EVENT1 > 100.0 else 1.0\",\n\t\t\tNULL, ctx) == 0);\n\tTEST_ASSERT_VAL(\"find ids\", hashmap__size(ctx->ids) == 0);\n\n\t/* Test toplogy constants appear well ordered. */\n\texpr__ctx_clear(ctx);\n\tTEST_ASSERT_VAL(\"#num_cpus\", expr__parse(&num_cpus, ctx, \"#num_cpus\") == 0);\n\tTEST_ASSERT_VAL(\"#num_cores\", expr__parse(&num_cores, ctx, \"#num_cores\") == 0);\n\tTEST_ASSERT_VAL(\"#num_cpus >= #num_cores\", num_cpus >= num_cores);\n\tTEST_ASSERT_VAL(\"#num_dies\", expr__parse(&num_dies, ctx, \"#num_dies\") == 0);\n\tTEST_ASSERT_VAL(\"#num_cores >= #num_dies\", num_cores >= num_dies);\n\tTEST_ASSERT_VAL(\"#num_packages\", expr__parse(&num_packages, ctx, \"#num_packages\") == 0);\n\n\tif (num_dies) // Some platforms do not have CPU die support, for example s390\n\t\tTEST_ASSERT_VAL(\"#num_dies >= #num_packages\", num_dies >= num_packages);\n\n\t/*\n\t * Source count returns the number of events aggregating in a leader\n\t * event including the leader. Check parsing yields an id.\n\t */\n\texpr__ctx_clear(ctx);\n\tTEST_ASSERT_VAL(\"source count\",\n\t\t\texpr__find_ids(\"source_count(EVENT1)\",\n\t\t\tNULL, ctx) == 0);\n\tTEST_ASSERT_VAL(\"source count\", hashmap__size(ctx->ids) == 1);\n\tTEST_ASSERT_VAL(\"source count\", hashmap__find(ctx->ids, \"EVENT1\",\n\t\t\t\t\t\t\t(void **)&val_ptr));\n\n\texpr__ctx_free(ctx);\n\n\treturn 0;\n}",
        "static void codec_vp9_process_lf(struct codec_vp9 *vp9)\n{\n\tunion rpm_param *param = &vp9->rpm_param;\n\tint i;\n": "static void codec_vp9_process_lf(struct codec_vp9 *vp9)\n{\n\tunion rpm_param *param = &vp9->rpm_param;\n\tint i;\n\n\tvp9->lf.mode_ref_delta_enabled = param->p.mode_ref_delta_enabled;\n\tvp9->lf.sharpness_level = param->p.sharpness_level;\n\tvp9->default_filt_lvl = param->p.filter_level;\n\tvp9->seg_4lf.enabled = param->p.seg_enabled;\n\tvp9->seg_4lf.abs_delta = param->p.seg_abs_delta;\n\n\tfor (i = 0; i < 4; i++)\n\t\tvp9->lf.ref_deltas[i] = param->p.ref_deltas[i];\n\n\tfor (i = 0; i < 2; i++)\n\t\tvp9->lf.mode_deltas[i] = param->p.mode_deltas[i];\n\n\tfor (i = 0; i < MAX_SEGMENTS; i++)\n\t\tvp9->seg_4lf.feature_mask[i] =\n\t\t\t(param->p.seg_lf_info[i] & 0x8000) ?\n\t\t\t\t(1 << SEG_LVL_ALT_LF) : 0;\n\n\tfor (i = 0; i < MAX_SEGMENTS; i++)\n\t\tvp9->seg_4lf.feature_data[i][SEG_LVL_ALT_LF] =\n\t\t\t(param->p.seg_lf_info[i] & 0x100) ?\n\t\t\t\t-(param->p.seg_lf_info[i] & 0x3f)\n\t\t\t\t: (param->p.seg_lf_info[i] & 0x3f);\n}",
        "static void sbz_dsp_startup_check(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int dsp_data_check[4];\n\tunsigned int cur_address = 0x390;": "static void sbz_dsp_startup_check(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int dsp_data_check[4];\n\tunsigned int cur_address = 0x390;\n\tunsigned int i;\n\tunsigned int failure = 0;\n\tunsigned int reload = 3;\n\n\tif (spec->startup_check_entered)\n\t\treturn;\n\n\tspec->startup_check_entered = true;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tchipio_read(codec, cur_address, &dsp_data_check[i]);\n\t\tcur_address += 0x4;\n\t}\n\tfor (i = 0; i < 4; i++) {\n\t\tif (dsp_data_check[i] == 0xa1a2a3a4)\n\t\t\tfailure = 1;\n\t}\n\n\tcodec_dbg(codec, \"Startup Check: %d \", failure);\n\tif (failure)\n\t\tcodec_info(codec, \"DSP not initialized properly. Attempting to fix.\");\n\t/*\n\t * While the failure condition is true, and we haven't reached our\n\t * three reload limit, continue trying to reload the driver and\n\t * fix the issue.\n\t */\n\twhile (failure && (reload != 0)) {\n\t\tcodec_info(codec, \"Reloading... Tries left: %d\", reload);\n\t\tsbz_exit_chip(codec);\n\t\tspec->dsp_state = DSP_DOWNLOAD_INIT;\n\t\tcodec->patch_ops.init(codec);\n\t\tfailure = 0;\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tchipio_read(codec, cur_address, &dsp_data_check[i]);\n\t\t\tcur_address += 0x4;\n\t\t}\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tif (dsp_data_check[i] == 0xa1a2a3a4)\n\t\t\t\tfailure = 1;\n\t\t}\n\t\treload--;\n\t}\n\n\tif (!failure && reload < 3)\n\t\tcodec_info(codec, \"DSP fixed.\");\n\n\tif (!failure)\n\t\treturn;\n\n\tcodec_info(codec, \"DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.\");\n}",
        "static void rcu_cpu_kthread(unsigned int cpu)\n{\n\tunsigned int *statusp = this_cpu_ptr(&rcu_data.rcu_cpu_kthread_status);\n\tchar work, *workp = this_cpu_ptr(&rcu_data.rcu_cpu_has_work);\n\tunsigned long *j = this_cpu_ptr(&rcu_data.rcuc_activity);": "static void rcu_cpu_kthread(unsigned int cpu)\n{\n\tunsigned int *statusp = this_cpu_ptr(&rcu_data.rcu_cpu_kthread_status);\n\tchar work, *workp = this_cpu_ptr(&rcu_data.rcu_cpu_has_work);\n\tunsigned long *j = this_cpu_ptr(&rcu_data.rcuc_activity);\n\tint spincnt;\n\n\ttrace_rcu_utilization(TPS(\"Start CPU kthread@rcu_run\"));\n\tfor (spincnt = 0; spincnt < 10; spincnt++) {\n\t\tWRITE_ONCE(*j, jiffies);\n\t\tlocal_bh_disable();\n\t\t*statusp = RCU_KTHREAD_RUNNING;\n\t\tlocal_irq_disable();\n\t\twork = *workp;\n\t\t*workp = 0;\n\t\tlocal_irq_enable();\n\t\tif (work)\n\t\t\trcu_core();\n\t\tlocal_bh_enable();\n\t\tif (*workp == 0) {\n\t\t\ttrace_rcu_utilization(TPS(\"End CPU kthread@rcu_wait\"));\n\t\t\t*statusp = RCU_KTHREAD_WAITING;\n\t\t\treturn;\n\t\t}\n\t}\n\t*statusp = RCU_KTHREAD_YIELDING;\n\ttrace_rcu_utilization(TPS(\"Start CPU kthread@rcu_yield\"));\n\tschedule_timeout_idle(2);\n\ttrace_rcu_utilization(TPS(\"End CPU kthread@rcu_yield\"));\n\t*statusp = RCU_KTHREAD_WAITING;\n\tWRITE_ONCE(*j, jiffies);\n}",
        "static int initialize_dco_operating_mode(struct idtcm_channel *channel)\n{\n\tenum manual_reference ref = MANU_REF_XO_DPLL;\n\tenum pll_mode mode = PLL_MODE_DISABLED;\n\tstruct idtcm *idtcm = channel->idtcm;": "static int initialize_dco_operating_mode(struct idtcm_channel *channel)\n{\n\tenum manual_reference ref = MANU_REF_XO_DPLL;\n\tenum pll_mode mode = PLL_MODE_DISABLED;\n\tstruct idtcm *idtcm = channel->idtcm;\n\tint err;\n\n\tchannel->mode = PTP_PLL_MODE_UNSUPPORTED;\n\n\terr = idtcm_get_pll_mode(channel, &mode);\n\tif (err) {\n\t\tdev_err(idtcm->dev, \"Unable to read pll mode!\");\n\t\treturn err;\n\t}\n\n\tif (mode == PLL_MODE_PLL) {\n\t\terr = idtcm_get_manual_reference(channel, &ref);\n\t\tif (err) {\n\t\t\tdev_err(idtcm->dev, \"Unable to read manual reference!\");\n\t\t\treturn err;\n\t\t}\n\t\terr = initialize_operating_mode_with_manual_reference(channel, ref);\n\t} else {\n\t\terr = initialize_operating_mode_with_pll_mode(channel, mode);\n\t}\n\n\tif (channel->mode == PTP_PLL_MODE_WRITE_PHASE)\n\t\tchannel->configure_write_frequency(channel);\n\n\treturn err;\n}",
        "static int tda1997x_identify_module(struct tda1997x_state *state)\n{\n\tstruct v4l2_subdev *sd = &state->sd;\n\tenum tda1997x_type type;\n\tu8 reg;": "static int tda1997x_identify_module(struct tda1997x_state *state)\n{\n\tstruct v4l2_subdev *sd = &state->sd;\n\tenum tda1997x_type type;\n\tu8 reg;\n\n\t/* Read chip configuration*/\n\treg = io_read(sd, REG_CMTP_REG10);\n\tstate->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */\n\tstate->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */\n\tstate->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */\n\tstate->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */\n\tswitch ((reg >> 4) & 0x03) {\n\tcase 0x00:\n\t\ttype = TDA19971;\n\t\tbreak;\n\tcase 0x02:\n\tcase 0x03:\n\t\ttype = TDA19973;\n\t\tbreak;\n\tdefault:\n\t\tdev_err(&state->client->dev, \"unsupported chip ID\\n\");\n\t\treturn -EIO;\n\t}\n\tif (state->info->type != type) {\n\t\tdev_err(&state->client->dev, \"chip id mismatch\\n\");\n\t\treturn -EIO;\n\t}\n\n\t/* read chip revision */\n\tstate->chip_revision = io_read(sd, REG_CMTP_REG11);\n\n\treturn 0;\n}",
        "static int pfkey_getspi(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tstruct sk_buff *resp_skb;\n\tstruct sadb_x_sa2 *sa2;": "static int pfkey_getspi(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tstruct sk_buff *resp_skb;\n\tstruct sadb_x_sa2 *sa2;\n\tstruct sadb_address *saddr, *daddr;\n\tstruct sadb_msg *out_hdr;\n\tstruct sadb_spirange *range;\n\tstruct xfrm_state *x = NULL;\n\tint mode;\n\tint err;\n\tu32 min_spi, max_spi;\n\tu32 reqid;\n\tu8 proto;\n\tunsigned short family;\n\txfrm_address_t *xsaddr = NULL, *xdaddr = NULL;\n\n\tif (!present_and_same_family(ext_hdrs[SADB_EXT_ADDRESS_SRC-1],\n\t\t\t\t     ext_hdrs[SADB_EXT_ADDRESS_DST-1]))\n\t\treturn -EINVAL;\n\n\tproto = pfkey_satype2proto(hdr->sadb_msg_satype);\n\tif (proto == 0)\n\t\treturn -EINVAL;\n\n\tif ((sa2 = ext_hdrs[SADB_X_EXT_SA2-1]) != NULL) {\n\t\tmode = pfkey_mode_to_xfrm(sa2->sadb_x_sa2_mode);\n\t\tif (mode < 0)\n\t\t\treturn -EINVAL;\n\t\treqid = sa2->sadb_x_sa2_reqid;\n\t} else {\n\t\tmode = 0;\n\t\treqid = 0;\n\t}\n\n\tsaddr = ext_hdrs[SADB_EXT_ADDRESS_SRC-1];\n\tdaddr = ext_hdrs[SADB_EXT_ADDRESS_DST-1];\n\n\tfamily = ((struct sockaddr *)(saddr + 1))->sa_family;\n\tswitch (family) {\n\tcase AF_INET:\n\t\txdaddr = (xfrm_address_t *)&((struct sockaddr_in *)(daddr + 1))->sin_addr.s_addr;\n\t\txsaddr = (xfrm_address_t *)&((struct sockaddr_in *)(saddr + 1))->sin_addr.s_addr;\n\t\tbreak;\n#if IS_ENABLED(CONFIG_IPV6)\n\tcase AF_INET6:\n\t\txdaddr = (xfrm_address_t *)&((struct sockaddr_in6 *)(daddr + 1))->sin6_addr;\n\t\txsaddr = (xfrm_address_t *)&((struct sockaddr_in6 *)(saddr + 1))->sin6_addr;\n\t\tbreak;\n#endif\n\t}\n\n\tif (hdr->sadb_msg_seq) {\n\t\tx = xfrm_find_acq_byseq(net, DUMMY_MARK, hdr->sadb_msg_seq);\n\t\tif (x && !xfrm_addr_equal(&x->id.daddr, xdaddr, family)) {\n\t\t\txfrm_state_put(x);\n\t\t\tx = NULL;\n\t\t}\n\t}\n\n\tif (!x)\n\t\tx = xfrm_find_acq(net, &dummy_mark, mode, reqid, 0, proto, xdaddr, xsaddr, 1, family);\n\n\tif (x == NULL)\n\t\treturn -ENOENT;\n\n\tmin_spi = 0x100;\n\tmax_spi = 0x0fffffff;\n\n\trange = ext_hdrs[SADB_EXT_SPIRANGE-1];\n\tif (range) {\n\t\tmin_spi = range->sadb_spirange_min;\n\t\tmax_spi = range->sadb_spirange_max;\n\t}\n\n\terr = verify_spi_info(x->id.proto, min_spi, max_spi);\n\tif (err) {\n\t\txfrm_state_put(x);\n\t\treturn err;\n\t}\n\n\terr = xfrm_alloc_spi(x, min_spi, max_spi);\n\tresp_skb = err ? ERR_PTR(err) : pfkey_xfrm_state2msg(x);\n\n\tif (IS_ERR(resp_skb)) {\n\t\txfrm_state_put(x);\n\t\treturn  PTR_ERR(resp_skb);\n\t}\n\n\tout_hdr = (struct sadb_msg *) resp_skb->data;\n\tout_hdr->sadb_msg_version = hdr->sadb_msg_version;\n\tout_hdr->sadb_msg_type = SADB_GETSPI;\n\tout_hdr->sadb_msg_satype = pfkey_proto2satype(proto);\n\tout_hdr->sadb_msg_errno = 0;\n\tout_hdr->sadb_msg_reserved = 0;\n\tout_hdr->sadb_msg_seq = hdr->sadb_msg_seq;\n\tout_hdr->sadb_msg_pid = hdr->sadb_msg_pid;\n\n\txfrm_state_put(x);\n\n\tpfkey_broadcast(resp_skb, GFP_KERNEL, BROADCAST_ONE, sk, net);\n\n\treturn 0;\n}",
        "static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)\n{\n\tstruct mtd_info *mtd = &nor->mtd;\n\tu64 min_prot_len;\n\tint ret, status_old, status_new;": "static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)\n{\n\tstruct mtd_info *mtd = &nor->mtd;\n\tu64 min_prot_len;\n\tint ret, status_old, status_new;\n\tu8 mask = spi_nor_get_sr_bp_mask(nor);\n\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n\tu8 pow, val;\n\tloff_t lock_len;\n\tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n\tbool use_top;\n\n\tret = spi_nor_read_sr(nor, nor->bouncebuf);\n\tif (ret)\n\t\treturn ret;\n\n\tstatus_old = nor->bouncebuf[0];\n\n\t/* If nothing in our range is locked, we don't need to do anything */\n\tif (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))\n\t\treturn 0;\n\n\t/* If anything below us is locked, we can't use 'top' protection */\n\tif (!spi_nor_is_unlocked_sr(nor, 0, ofs, status_old))\n\t\tcan_be_top = false;\n\n\t/* If anything above us is locked, we can't use 'bottom' protection */\n\tif (!spi_nor_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),\n\t\t\t\t    status_old))\n\t\tcan_be_bottom = false;\n\n\tif (!can_be_bottom && !can_be_top)\n\t\treturn -EINVAL;\n\n\t/* Prefer top, if both are valid */\n\tuse_top = can_be_top;\n\n\t/* lock_len: length of region that should remain locked */\n\tif (use_top)\n\t\tlock_len = mtd->size - (ofs + len);\n\telse\n\t\tlock_len = ofs;\n\n\tif (lock_len == 0) {\n\t\tval = 0; /* fully unlocked */\n\t} else {\n\t\tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n\t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n\t\tval = pow << SR_BP_SHIFT;\n\n\t\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n\t\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n\n\t\t/* Some power-of-two sizes are not supported */\n\t\tif (val & ~mask)\n\t\t\treturn -EINVAL;\n\t}\n\n\tstatus_new = (status_old & ~mask & ~tb_mask) | val;\n\n\t/* Don't protect status register if we're fully unlocked */\n\tif (lock_len == 0)\n\t\tstatus_new &= ~SR_SRWD;\n\n\tif (!use_top)\n\t\tstatus_new |= tb_mask;\n\n\t/* Don't bother if they're the same */\n\tif (status_new == status_old)\n\t\treturn 0;\n\n\t/* Only modify protection if it will not lock other areas */\n\tif ((status_new & mask) > (status_old & mask))\n\t\treturn -EINVAL;\n\n\treturn spi_nor_write_sr_and_check(nor, status_new);\n}",
        "static int ila_add_mapping(struct net *net, struct ila_xlat_params *xp)\n{\n\tstruct ila_net *ilan = net_generic(net, ila_net_id);\n\tstruct ila_map *ila, *head;\n\tspinlock_t *lock = ila_get_lock(ilan, xp->ip.locator_match);": "static int ila_add_mapping(struct net *net, struct ila_xlat_params *xp)\n{\n\tstruct ila_net *ilan = net_generic(net, ila_net_id);\n\tstruct ila_map *ila, *head;\n\tspinlock_t *lock = ila_get_lock(ilan, xp->ip.locator_match);\n\tint err = 0, order;\n\n\tif (!ilan->xlat.hooks_registered) {\n\t\t/* We defer registering net hooks in the namespace until the\n\t\t * first mapping is added.\n\t\t */\n\t\terr = nf_register_net_hooks(net, ila_nf_hook_ops,\n\t\t\t\t\t    ARRAY_SIZE(ila_nf_hook_ops));\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tilan->xlat.hooks_registered = true;\n\t}\n\n\tila = kzalloc(sizeof(*ila), GFP_KERNEL);\n\tif (!ila)\n\t\treturn -ENOMEM;\n\n\tila_init_saved_csum(&xp->ip);\n\n\tila->xp = *xp;\n\n\torder = ila_order(ila);\n\n\tspin_lock(lock);\n\n\thead = rhashtable_lookup_fast(&ilan->xlat.rhash_table,\n\t\t\t\t      &xp->ip.locator_match,\n\t\t\t\t      rht_params);\n\tif (!head) {\n\t\t/* New entry for the rhash_table */\n\t\terr = rhashtable_lookup_insert_fast(&ilan->xlat.rhash_table,\n\t\t\t\t\t\t    &ila->node, rht_params);\n\t} else {\n\t\tstruct ila_map *tila = head, *prev = NULL;\n\n\t\tdo {\n\t\t\tif (!ila_cmp_params(tila, xp)) {\n\t\t\t\terr = -EEXIST;\n\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\tif (order > ila_order(tila))\n\t\t\t\tbreak;\n\n\t\t\tprev = tila;\n\t\t\ttila = rcu_dereference_protected(tila->next,\n\t\t\t\tlockdep_is_held(lock));\n\t\t} while (tila);\n\n\t\tif (prev) {\n\t\t\t/* Insert in sub list of head */\n\t\t\tRCU_INIT_POINTER(ila->next, tila);\n\t\t\trcu_assign_pointer(prev->next, ila);\n\t\t} else {\n\t\t\t/* Make this ila new head */\n\t\t\tRCU_INIT_POINTER(ila->next, head);\n\t\t\terr = rhashtable_replace_fast(&ilan->xlat.rhash_table,\n\t\t\t\t\t\t      &head->node,\n\t\t\t\t\t\t      &ila->node, rht_params);\n\t\t\tif (err)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\tspin_unlock(lock);\n\n\tif (err)\n\t\tkfree(ila);\n\n\treturn err;\n}",
        "static int hi_cfg_command(const struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct drxj_hi_cmd hi_cmd;\n\tu16 result = 0;": "static int hi_cfg_command(const struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct drxj_hi_cmd hi_cmd;\n\tu16 result = 0;\n\tint rc;\n\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\thi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;\n\thi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;\n\thi_cmd.param2 = ext_attr->hi_cfg_timing_div;\n\thi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;\n\thi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;\n\thi_cmd.param5 = ext_attr->hi_cfg_ctrl;\n\thi_cmd.param6 = ext_attr->hi_cfg_transmit;\n\n\trc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Reset power down flag (set one call only) */\n\text_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));\n\n\treturn 0;\n\nrw_error:\n\treturn rc;\n}",
        "static void increment_tailroom_need_count(struct ieee80211_sub_if_data *sdata)\n{\n\t/*\n\t * When this count is zero, SKB resizing for allocating tailroom\n\t * for IV or MMIC is skipped. But, this check has created two race": "static void increment_tailroom_need_count(struct ieee80211_sub_if_data *sdata)\n{\n\t/*\n\t * When this count is zero, SKB resizing for allocating tailroom\n\t * for IV or MMIC is skipped. But, this check has created two race\n\t * cases in xmit path while transiting from zero count to one:\n\t *\n\t * 1. SKB resize was skipped because no key was added but just before\n\t * the xmit key is added and SW encryption kicks off.\n\t *\n\t * 2. SKB resize was skipped because all the keys were hw planted but\n\t * just before xmit one of the key is deleted and SW encryption kicks\n\t * off.\n\t *\n\t * In both the above case SW encryption will find not enough space for\n\t * tailroom and exits with WARN_ON. (See WARN_ONs at wpa.c)\n\t *\n\t * Solution has been explained at\n\t * http://mid.gmane.org/1308590980.4322.19.camel@jlt3.sipsolutions.net\n\t */\n\n\tassert_key_lock(sdata->local);\n\n\tupdate_vlan_tailroom_need_count(sdata, 1);\n\n\tif (!sdata->crypto_tx_tailroom_needed_cnt++) {\n\t\t/*\n\t\t * Flush all XMIT packets currently using HW encryption or no\n\t\t * encryption at all if the count transition is from 0 -> 1.\n\t\t */\n\t\tsynchronize_net();\n\t}\n}",
        "static int qcom_labibb_check_sc_status(struct labibb_regulator *vreg)\n{\n\tu32 ibb_status, ibb_reg, lab_status, lab_reg;\n\tint ret;\n": "static int qcom_labibb_check_sc_status(struct labibb_regulator *vreg)\n{\n\tu32 ibb_status, ibb_reg, lab_status, lab_reg;\n\tint ret;\n\n\t/* We have to work on both regulators due to PBS... */\n\tlab_reg = ibb_reg = vreg->base + REG_LABIBB_STATUS1;\n\tif (vreg->type == QCOM_LAB_TYPE)\n\t\tibb_reg -= PMI8998_IBB_LAB_REG_OFFSET;\n\telse\n\t\tlab_reg += PMI8998_IBB_LAB_REG_OFFSET;\n\n\tret = regmap_read(vreg->rdev->regmap, lab_reg, &lab_status);\n\tif (ret)\n\t\treturn ret;\n\tret = regmap_read(vreg->rdev->regmap, ibb_reg, &ibb_status);\n\tif (ret)\n\t\treturn ret;\n\n\treturn !!(lab_status & LABIBB_STATUS1_SC_BIT) ||\n\t       !!(ibb_status & LABIBB_STATUS1_SC_BIT);\n}",
        "static int __trace_uprobe_create(int argc, const char **argv)\n{\n\tstruct trace_uprobe *tu;\n\tconst char *event = NULL, *group = UPROBE_EVENT_SYSTEM;\n\tchar *arg, *filename, *rctr, *rctr_end, *tmp;": "static int __trace_uprobe_create(int argc, const char **argv)\n{\n\tstruct trace_uprobe *tu;\n\tconst char *event = NULL, *group = UPROBE_EVENT_SYSTEM;\n\tchar *arg, *filename, *rctr, *rctr_end, *tmp;\n\tchar buf[MAX_EVENT_NAME_LEN];\n\tenum probe_print_type ptype;\n\tstruct path path;\n\tunsigned long offset, ref_ctr_offset;\n\tbool is_return = false;\n\tint i, ret;\n\n\tret = 0;\n\tref_ctr_offset = 0;\n\n\tswitch (argv[0][0]) {\n\tcase 'r':\n\t\tis_return = true;\n\t\tbreak;\n\tcase 'p':\n\t\tbreak;\n\tdefault:\n\t\treturn -ECANCELED;\n\t}\n\n\tif (argc < 2)\n\t\treturn -ECANCELED;\n\n\tif (argv[0][1] == ':')\n\t\tevent = &argv[0][2];\n\n\tif (!strchr(argv[1], '/'))\n\t\treturn -ECANCELED;\n\n\tfilename = kstrdup(argv[1], GFP_KERNEL);\n\tif (!filename)\n\t\treturn -ENOMEM;\n\n\t/* Find the last occurrence, in case the path contains ':' too. */\n\targ = strrchr(filename, ':');\n\tif (!arg || !isdigit(arg[1])) {\n\t\tkfree(filename);\n\t\treturn -ECANCELED;\n\t}\n\n\ttrace_probe_log_init(\"trace_uprobe\", argc, argv);\n\ttrace_probe_log_set_index(1);\t/* filename is the 2nd argument */\n\n\t*arg++ = '\\0';\n\tret = kern_path(filename, LOOKUP_FOLLOW, &path);\n\tif (ret) {\n\t\ttrace_probe_log_err(0, FILE_NOT_FOUND);\n\t\tkfree(filename);\n\t\ttrace_probe_log_clear();\n\t\treturn ret;\n\t}\n\tif (!d_is_reg(path.dentry)) {\n\t\ttrace_probe_log_err(0, NO_REGULAR_FILE);\n\t\tret = -EINVAL;\n\t\tgoto fail_address_parse;\n\t}\n\n\t/* Parse reference counter offset if specified. */\n\trctr = strchr(arg, '(');\n\tif (rctr) {\n\t\trctr_end = strchr(rctr, ')');\n\t\tif (!rctr_end) {\n\t\t\tret = -EINVAL;\n\t\t\trctr_end = rctr + strlen(rctr);\n\t\t\ttrace_probe_log_err(rctr_end - filename,\n\t\t\t\t\t    REFCNT_OPEN_BRACE);\n\t\t\tgoto fail_address_parse;\n\t\t} else if (rctr_end[1] != '\\0') {\n\t\t\tret = -EINVAL;\n\t\t\ttrace_probe_log_err(rctr_end + 1 - filename,\n\t\t\t\t\t    BAD_REFCNT_SUFFIX);\n\t\t\tgoto fail_address_parse;\n\t\t}\n\n\t\t*rctr++ = '\\0';\n\t\t*rctr_end = '\\0';\n\t\tret = kstrtoul(rctr, 0, &ref_ctr_offset);\n\t\tif (ret) {\n\t\t\ttrace_probe_log_err(rctr - filename, BAD_REFCNT);\n\t\t\tgoto fail_address_parse;\n\t\t}\n\t}\n\n\t/* Check if there is %return suffix */\n\ttmp = strchr(arg, '%');\n\tif (tmp) {\n\t\tif (!strcmp(tmp, \"%return\")) {\n\t\t\t*tmp = '\\0';\n\t\t\tis_return = true;\n\t\t} else {\n\t\t\ttrace_probe_log_err(tmp - filename, BAD_ADDR_SUFFIX);\n\t\t\tret = -EINVAL;\n\t\t\tgoto fail_address_parse;\n\t\t}\n\t}\n\n\t/* Parse uprobe offset. */\n\tret = kstrtoul(arg, 0, &offset);\n\tif (ret) {\n\t\ttrace_probe_log_err(arg - filename, BAD_UPROBE_OFFS);\n\t\tgoto fail_address_parse;\n\t}\n\n\t/* setup a probe */\n\ttrace_probe_log_set_index(0);\n\tif (event) {\n\t\tret = traceprobe_parse_event_name(&event, &group, buf,\n\t\t\t\t\t\t  event - argv[0]);\n\t\tif (ret)\n\t\t\tgoto fail_address_parse;\n\t} else {\n\t\tchar *tail;\n\t\tchar *ptr;\n\n\t\ttail = kstrdup(kbasename(filename), GFP_KERNEL);\n\t\tif (!tail) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto fail_address_parse;\n\t\t}\n\n\t\tptr = strpbrk(tail, \".-_\");\n\t\tif (ptr)\n\t\t\t*ptr = '\\0';\n\n\t\tsnprintf(buf, MAX_EVENT_NAME_LEN, \"%c_%s_0x%lx\", 'p', tail, offset);\n\t\tevent = buf;\n\t\tkfree(tail);\n\t}\n\n\targc -= 2;\n\targv += 2;\n\n\ttu = alloc_trace_uprobe(group, event, argc, is_return);\n\tif (IS_ERR(tu)) {\n\t\tret = PTR_ERR(tu);\n\t\t/* This must return -ENOMEM otherwise there is a bug */\n\t\tWARN_ON_ONCE(ret != -ENOMEM);\n\t\tgoto fail_address_parse;\n\t}\n\ttu->offset = offset;\n\ttu->ref_ctr_offset = ref_ctr_offset;\n\ttu->path = path;\n\ttu->filename = filename;\n\n\t/* parse arguments */\n\tfor (i = 0; i < argc && i < MAX_TRACE_ARGS; i++) {\n\t\ttrace_probe_log_set_index(i + 2);\n\t\tret = traceprobe_parse_probe_arg(&tu->tp, i, argv[i],\n\t\t\t\t\tis_return ? TPARG_FL_RETURN : 0);\n\t\tif (ret)\n\t\t\tgoto error;\n\t}\n\n\tptype = is_ret_probe(tu) ? PROBE_PRINT_RETURN : PROBE_PRINT_NORMAL;\n\tret = traceprobe_set_print_fmt(&tu->tp, ptype);\n\tif (ret < 0)\n\t\tgoto error;\n\n\tret = register_trace_uprobe(tu);\n\tif (!ret)\n\t\tgoto out;\n\nerror:\n\tfree_trace_uprobe(tu);\nout:\n\ttrace_probe_log_clear();\n\treturn ret;\n\nfail_address_parse:\n\ttrace_probe_log_clear();\n\tpath_put(&path);\n\tkfree(filename);\n\n\treturn ret;\n}",
        "static void test_tc_redirect_peer_l3(struct netns_setup_result *setup_result)\n{\n\tstruct test_tc_peer *skel = NULL;\n\tstruct nstoken *nstoken = NULL;\n\tint err;": "static void test_tc_redirect_peer_l3(struct netns_setup_result *setup_result)\n{\n\tstruct test_tc_peer *skel = NULL;\n\tstruct nstoken *nstoken = NULL;\n\tint err;\n\tint tunnel_pid = -1;\n\tint src_fd, target_fd = -1;\n\tint ifindex;\n\n\t/* Start a L3 TUN/TAP tunnel between the src and dst namespaces.\n\t * This test is using TUN/TAP instead of e.g. IPIP or GRE tunnel as those\n\t * expose the L2 headers encapsulating the IP packet to BPF and hence\n\t * don't have skb in suitable state for this test. Alternative to TUN/TAP\n\t * would be e.g. Wireguard which would appear as a pure L3 device to BPF,\n\t * but that requires much more complicated setup.\n\t */\n\tnstoken = open_netns(NS_SRC);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns \" NS_SRC))\n\t\treturn;\n\n\tsrc_fd = tun_open(\"tun_src\");\n\tif (!ASSERT_GE(src_fd, 0, \"tun_open tun_src\"))\n\t\tgoto fail;\n\n\tclose_netns(nstoken);\n\n\tnstoken = open_netns(NS_FWD);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns \" NS_FWD))\n\t\tgoto fail;\n\n\ttarget_fd = tun_open(\"tun_fwd\");\n\tif (!ASSERT_GE(target_fd, 0, \"tun_open tun_fwd\"))\n\t\tgoto fail;\n\n\ttunnel_pid = fork();\n\tif (!ASSERT_GE(tunnel_pid, 0, \"fork tun_relay_loop\"))\n\t\tgoto fail;\n\n\tif (tunnel_pid == 0)\n\t\texit(tun_relay_loop(src_fd, target_fd));\n\n\tskel = test_tc_peer__open();\n\tif (!ASSERT_OK_PTR(skel, \"test_tc_peer__open\"))\n\t\tgoto fail;\n\n\tifindex = get_ifindex(\"tun_fwd\");\n\tif (!ASSERT_GE(ifindex, 0, \"get_ifindex tun_fwd\"))\n\t\tgoto fail;\n\n\tskel->rodata->IFINDEX_SRC = ifindex;\n\tskel->rodata->IFINDEX_DST = setup_result->ifindex_veth_dst_fwd;\n\n\terr = test_tc_peer__load(skel);\n\tif (!ASSERT_OK(err, \"test_tc_peer__load\"))\n\t\tgoto fail;\n\n\terr = bpf_program__pin(skel->progs.tc_src_l3, SRC_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" SRC_PROG_PIN_FILE))\n\t\tgoto fail;\n\n\terr = bpf_program__pin(skel->progs.tc_dst_l3, DST_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" DST_PROG_PIN_FILE))\n\t\tgoto fail;\n\n\terr = bpf_program__pin(skel->progs.tc_chk, CHK_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" CHK_PROG_PIN_FILE))\n\t\tgoto fail;\n\n\t/* Load \"tc_src_l3\" to the tun_fwd interface to redirect packets\n\t * towards dst, and \"tc_dst\" to redirect packets\n\t * and \"tc_chk\" on veth_dst_fwd to drop non-redirected packets.\n\t */\n\tSYS(\"tc qdisc add dev tun_fwd clsact\");\n\tSYS(\"tc filter add dev tun_fwd ingress bpf da object-pinned \"\n\t    SRC_PROG_PIN_FILE);\n\n\tSYS(\"tc qdisc add dev veth_dst_fwd clsact\");\n\tSYS(\"tc filter add dev veth_dst_fwd ingress bpf da object-pinned \"\n\t    DST_PROG_PIN_FILE);\n\tSYS(\"tc filter add dev veth_dst_fwd egress bpf da object-pinned \"\n\t    CHK_PROG_PIN_FILE);\n\n\t/* Setup route and neigh tables */\n\tSYS(\"ip -netns \" NS_SRC \" addr add dev tun_src \" IP4_TUN_SRC \"/24\");\n\tSYS(\"ip -netns \" NS_FWD \" addr add dev tun_fwd \" IP4_TUN_FWD \"/24\");\n\n\tSYS(\"ip -netns \" NS_SRC \" addr add dev tun_src \" IP6_TUN_SRC \"/64 nodad\");\n\tSYS(\"ip -netns \" NS_FWD \" addr add dev tun_fwd \" IP6_TUN_FWD \"/64 nodad\");\n\n\tSYS(\"ip -netns \" NS_SRC \" route del \" IP4_DST \"/32 dev veth_src scope global\");\n\tSYS(\"ip -netns \" NS_SRC \" route add \" IP4_DST \"/32 via \" IP4_TUN_FWD\n\t    \" dev tun_src scope global\");\n\tSYS(\"ip -netns \" NS_DST \" route add \" IP4_TUN_SRC \"/32 dev veth_dst scope global\");\n\tSYS(\"ip -netns \" NS_SRC \" route del \" IP6_DST \"/128 dev veth_src scope global\");\n\tSYS(\"ip -netns \" NS_SRC \" route add \" IP6_DST \"/128 via \" IP6_TUN_FWD\n\t    \" dev tun_src scope global\");\n\tSYS(\"ip -netns \" NS_DST \" route add \" IP6_TUN_SRC \"/128 dev veth_dst scope global\");\n\n\tSYS(\"ip -netns \" NS_DST \" neigh add \" IP4_TUN_SRC \" dev veth_dst lladdr \" MAC_DST_FWD);\n\tSYS(\"ip -netns \" NS_DST \" neigh add \" IP6_TUN_SRC \" dev veth_dst lladdr \" MAC_DST_FWD);\n\n\tif (!ASSERT_OK(set_forwarding(false), \"disable forwarding\"))\n\t\tgoto fail;\n\n\ttest_connectivity();\n\nfail:\n\tif (tunnel_pid > 0) {\n\t\tkill(tunnel_pid, SIGTERM);\n\t\twaitpid(tunnel_pid, NULL, 0);\n\t}\n\tif (src_fd >= 0)\n\t\tclose(src_fd);\n\tif (target_fd >= 0)\n\t\tclose(target_fd);\n\tif (skel)\n\t\ttest_tc_peer__destroy(skel);\n\tif (nstoken)\n\t\tclose_netns(nstoken);\n}",
        "static void __bo_take_off_handling(struct hmm_buffer_object *bo)\n{\n\tstruct hmm_bo_device *bdev = bo->bdev;\n\t/* There are 4 situations when we take off a known bo from free rbtree:\n\t * 1. if bo->next && bo->prev == NULL, bo is a rbtree node": "static void __bo_take_off_handling(struct hmm_buffer_object *bo)\n{\n\tstruct hmm_bo_device *bdev = bo->bdev;\n\t/* There are 4 situations when we take off a known bo from free rbtree:\n\t * 1. if bo->next && bo->prev == NULL, bo is a rbtree node\n\t *\tand does not have a linked list after bo, to take off this bo,\n\t *\twe just need erase bo directly and rebalance the free rbtree\n\t */\n\tif (!bo->prev && !bo->next) {\n\t\trb_erase(&bo->node, &bdev->free_rbtree);\n\t\t/* 2. when bo->next != NULL && bo->prev == NULL, bo is a rbtree node,\n\t\t *\tand has a linked list,to take off this bo we need erase bo\n\t\t *\tfirst, then, insert bo->next into free rbtree and rebalance\n\t\t *\tthe free rbtree\n\t\t */\n\t} else if (!bo->prev && bo->next) {\n\t\tbo->next->prev = NULL;\n\t\trb_erase(&bo->node, &bdev->free_rbtree);\n\t\t__bo_insert_to_free_rbtree(&bdev->free_rbtree, bo->next);\n\t\tbo->next = NULL;\n\t\t/* 3. when bo->prev != NULL && bo->next == NULL, bo is not a rbtree\n\t\t *\tnode, bo is the last element of the linked list after rbtree\n\t\t *\tnode, to take off this bo, we just need set the \"prev/next\"\n\t\t *\tpointers to NULL, the free rbtree stays unchaged\n\t\t */\n\t} else if (bo->prev && !bo->next) {\n\t\tbo->prev->next = NULL;\n\t\tbo->prev = NULL;\n\t\t/* 4. when bo->prev != NULL && bo->next != NULL ,bo is not a rbtree\n\t\t *\tnode, bo is in the middle of the linked list after rbtree node,\n\t\t *\tto take off this bo, we just set take the \"prev/next\" pointers\n\t\t *\tto NULL, the free rbtree stays unchaged\n\t\t */\n\t} else if (bo->prev && bo->next) {\n\t\tbo->next->prev = bo->prev;\n\t\tbo->prev->next = bo->next;\n\t\tbo->next = NULL;\n\t\tbo->prev = NULL;\n\t}\n}",
        "static int uaa_to_xfi(struct pci_dev *pci)\n{\n\tunsigned int bar0, bar1, bar2, bar3, bar4, bar5;\n\tunsigned int cmd, irq, cl_size, l_timer, pwr;\n\tunsigned int is_uaa;": "static int uaa_to_xfi(struct pci_dev *pci)\n{\n\tunsigned int bar0, bar1, bar2, bar3, bar4, bar5;\n\tunsigned int cmd, irq, cl_size, l_timer, pwr;\n\tunsigned int is_uaa;\n\tunsigned int data[4] = {0};\n\tunsigned int io_base;\n\tvoid __iomem *mem_base;\n\tint i;\n\tconst u32 CTLX = CTLBITS('C', 'T', 'L', 'X');\n\tconst u32 CTL_ = CTLBITS('C', 'T', 'L', '-');\n\tconst u32 CTLF = CTLBITS('C', 'T', 'L', 'F');\n\tconst u32 CTLi = CTLBITS('C', 'T', 'L', 'i');\n\tconst u32 CTLA = CTLBITS('C', 'T', 'L', 'A');\n\tconst u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');\n\tconst u32 CTLL = CTLBITS('C', 'T', 'L', 'L');\n\n\t/* By default, Hendrix card UAA Bar0 should be using memory... */\n\tio_base = pci_resource_start(pci, 0);\n\tmem_base = ioremap(io_base, pci_resource_len(pci, 0));\n\tif (!mem_base)\n\t\treturn -ENOENT;\n\n\t/* Read current mode from Mode Change Register */\n\tfor (i = 0; i < 4; i++)\n\t\tdata[i] = readl(mem_base + UAA_CORE_CHANGE);\n\n\t/* Determine current mode... */\n\tif (data[0] == CTLA) {\n\t\tis_uaa = ((data[1] == CTLZ && data[2] == CTLL\n\t\t\t  && data[3] == CTLA) || (data[1] == CTLA\n\t\t\t  && data[2] == CTLZ && data[3] == CTLL));\n\t} else if (data[0] == CTLZ) {\n\t\tis_uaa = (data[1] == CTLL\n\t\t\t\t&& data[2] == CTLA && data[3] == CTLA);\n\t} else if (data[0] == CTLL) {\n\t\tis_uaa = (data[1] == CTLA\n\t\t\t\t&& data[2] == CTLA && data[3] == CTLZ);\n\t} else {\n\t\tis_uaa = 0;\n\t}\n\n\tif (!is_uaa) {\n\t\t/* Not in UAA mode currently. Return directly. */\n\t\tiounmap(mem_base);\n\t\treturn 0;\n\t}\n\n\tpci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);\n\tpci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);\n\tpci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);\n\tpci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);\n\tpci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);\n\tpci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);\n\tpci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);\n\tpci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);\n\tpci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);\n\tpci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);\n\tpci_read_config_dword(pci, PCI_COMMAND, &cmd);\n\n\t/* Set up X-Fi core PCI configuration space. */\n\t/* Switch to X-Fi config space with BAR0 exposed. */\n\tpci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);\n\t/* Copy UAA's BAR5 into X-Fi BAR0 */\n\tpci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);\n\t/* Switch to X-Fi config space without BAR0 exposed. */\n\tpci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);\n\tpci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);\n\tpci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);\n\tpci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);\n\tpci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);\n\tpci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);\n\tpci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);\n\tpci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);\n\tpci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);\n\tpci_write_config_dword(pci, PCI_COMMAND, cmd);\n\n\t/* Switch to X-Fi mode */\n\twritel(CTLX, (mem_base + UAA_CORE_CHANGE));\n\twritel(CTL_, (mem_base + UAA_CORE_CHANGE));\n\twritel(CTLF, (mem_base + UAA_CORE_CHANGE));\n\twritel(CTLi, (mem_base + UAA_CORE_CHANGE));\n\n\tiounmap(mem_base);\n\n\treturn 0;\n}",
        "static void guest_code(void)\n{\n\tuint8_t buffer[8192];\n\tint i;\n": "static void guest_code(void)\n{\n\tuint8_t buffer[8192];\n\tint i;\n\n\t/*\n\t * Special case tests.  main() will adjust RCX 2 => 1 and 3 => 8192 to\n\t * test that KVM doesn't explode when userspace modifies the \"count\" on\n\t * a userspace I/O exit.  KVM isn't required to play nice with the I/O\n\t * itself as KVM doesn't support manipulating the count, it just needs\n\t * to not explode or overflow a buffer.\n\t */\n\tguest_ins_port80(buffer, 2);\n\tguest_ins_port80(buffer, 3);\n\n\t/* Verify KVM fills the buffer correctly when not stuffing RCX. */\n\tmemset(buffer, 0, sizeof(buffer));\n\tguest_ins_port80(buffer, 8192);\n\tfor (i = 0; i < 8192; i++)\n\t\tGUEST_ASSERT_2(buffer[i] == 0xaa, i, buffer[i]);\n\n\tGUEST_DONE();\n}",
        "static int __init uwb_init(struct ibm_init_struct *iibm)\n{\n\tint res;\n\tint status = 0;\n": "static int __init uwb_init(struct ibm_init_struct *iibm)\n{\n\tint res;\n\tint status = 0;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\t\"initializing uwb subdriver\\n\");\n\n\tTPACPI_ACPIHANDLE_INIT(hkey);\n\n\ttp_features.uwb = hkey_handle &&\n\t    acpi_evalf(hkey_handle, &status, \"GUWB\", \"qd\");\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\"uwb is %s, status 0x%02x\\n\",\n\t\tstr_supported(tp_features.uwb),\n\t\tstatus);\n\n#ifdef CONFIG_THINKPAD_ACPI_DEBUGFACILITIES\n\tif (dbg_uwbemul) {\n\t\ttp_features.uwb = 1;\n\t\tpr_info(\"uwb switch emulation enabled\\n\");\n\t} else\n#endif\n\tif (tp_features.uwb &&\n\t    !(status & TP_ACPI_UWB_HWPRESENT)) {\n\t\t/* no uwb hardware present in system */\n\t\ttp_features.uwb = 0;\n\t\tdbg_printk(TPACPI_DBG_INIT,\n\t\t\t   \"uwb hardware not installed\\n\");\n\t}\n\n\tif (!tp_features.uwb)\n\t\treturn -ENODEV;\n\n\tres = tpacpi_new_rfkill(TPACPI_RFK_UWB_SW_ID,\n\t\t\t\t&uwb_tprfk_ops,\n\t\t\t\tRFKILL_TYPE_UWB,\n\t\t\t\tTPACPI_RFK_UWB_SW_NAME,\n\t\t\t\tfalse);\n\treturn res;\n}",
        "static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)\n{\n\t/* Sets output mode, MOSI signal, and (optionally) loopback */\n\trspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);\n": "static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)\n{\n\t/* Sets output mode, MOSI signal, and (optionally) loopback */\n\trspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);\n\n\t/* Sets transfer bit rate */\n\trspi_set_rate(rspi);\n\n\t/* Disable dummy transmission, set byte access */\n\trspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);\n\trspi->byte_access = 1;\n\n\t/* Sets RSPCK, SSL, next-access delay value */\n\trspi_write8(rspi, 0x00, RSPI_SPCKD);\n\trspi_write8(rspi, 0x00, RSPI_SSLND);\n\trspi_write8(rspi, 0x00, RSPI_SPND);\n\n\t/* Resets sequencer */\n\trspi_write8(rspi, 0, RSPI_SPSCR);\n\trspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);\n\trspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);\n\n\t/* Sets RSPI mode */\n\trspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);\n\n\treturn 0;\n}",
        "static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)\n{\n\t\n\tu32 idx, valid_slots,tmp,powerdown = 0;\n\tu16 modem_power,pin_config,logic_type;": "static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)\n{\n\t\n\tu32 idx, valid_slots,tmp,powerdown = 0;\n\tu16 modem_power,pin_config,logic_type;\n\n\tdev_dbg(chip->card->dev, \"cs46xx_setup_eapd_slot()+\\n\");\n\n\t/*\n\t *  See if the devices are powered down.  If so, we must power them up first\n\t *  or they will not respond.\n\t */\n\ttmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);\n\n\tif (!(tmp & CLKCR1_SWCE)) {\n\t\tsnd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);\n\t\tpowerdown = 1;\n\t}\n\n\t/*\n\t * Clear PRA.  The Bonzo chip will be used for GPIO not for modem\n\t * stuff.\n\t */\n\tif(chip->nr_ac97_codecs != 2) {\n\t\tdev_err(chip->card->dev,\n\t\t\t\"cs46xx_setup_eapd_slot() - no secondary codec configured\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tmodem_power = snd_cs46xx_codec_read (chip, \n\t\t\t\t\t     AC97_EXTENDED_MSTATUS,\n\t\t\t\t\t     CS46XX_SECONDARY_CODEC_INDEX);\n\tmodem_power &=0xFEFF;\n\n\tsnd_cs46xx_codec_write(chip, \n\t\t\t       AC97_EXTENDED_MSTATUS, modem_power,\n\t\t\t       CS46XX_SECONDARY_CODEC_INDEX);\n\n\t/*\n\t * Set GPIO pin's 7 and 8 so that they are configured for output.\n\t */\n\tpin_config = snd_cs46xx_codec_read (chip, \n\t\t\t\t\t    AC97_GPIO_CFG,\n\t\t\t\t\t    CS46XX_SECONDARY_CODEC_INDEX);\n\tpin_config &=0x27F;\n\n\tsnd_cs46xx_codec_write(chip, \n\t\t\t       AC97_GPIO_CFG, pin_config,\n\t\t\t       CS46XX_SECONDARY_CODEC_INDEX);\n    \n\t/*\n\t * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.\n\t */\n\n\tlogic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,\n\t\t\t\t\t   CS46XX_SECONDARY_CODEC_INDEX);\n\tlogic_type &=0x27F; \n\n\tsnd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,\n\t\t\t\tCS46XX_SECONDARY_CODEC_INDEX);\n\n\tvalid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);\n\tvalid_slots |= 0x200;\n\tsnd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);\n\n\tif ( cs46xx_wait_for_fifo(chip,1) ) {\n\t\tdev_dbg(chip->card->dev, \"FIFO is busy\\n\");\n\t  \n\t  return -EINVAL;\n\t}\n\n\t/*\n\t * Fill slots 12 with the correct value for the GPIO pins. \n\t */\n\tfor(idx = 0x90; idx <= 0x9F; idx++) {\n\t\t/*\n\t\t * Initialize the fifo so that bits 7 and 8 are on.\n\t\t *\n\t\t * Remember that the GPIO pins in bonzo are shifted by 4 bits to\n\t\t * the left.  0x1800 corresponds to bits 7 and 8.\n\t\t */\n\t\tsnd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);\n\n\t\t/*\n\t\t * Wait for command to complete\n\t\t */\n\t\tif ( cs46xx_wait_for_fifo(chip,200) ) {\n\t\t\tdev_dbg(chip->card->dev,\n\t\t\t\t\"failed waiting for FIFO at addr (%02X)\\n\",\n\t\t\t\tidx);\n\n\t\t\treturn -EINVAL;\n\t\t}\n            \n\t\t/*\n\t\t * Write the serial port FIFO index.\n\t\t */\n\t\tsnd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);\n      \n\t\t/*\n\t\t * Tell the serial port to load the new value into the FIFO location.\n\t\t */\n\t\tsnd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);\n\t}\n\n\t/* wait for last command to complete */\n\tcs46xx_wait_for_fifo(chip,200);\n\n\t/*\n\t *  Now, if we powered up the devices, then power them back down again.\n\t *  This is kinda ugly, but should never happen.\n\t */\n\tif (powerdown)\n\t\tsnd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);\n\n\treturn 0;\n}",
        "static void ipv6_gen_rnd_iid(struct in6_addr *addr)\n{\nregen:\n\tget_random_bytes(&addr->s6_addr[8], 8);\n": "static void ipv6_gen_rnd_iid(struct in6_addr *addr)\n{\nregen:\n\tget_random_bytes(&addr->s6_addr[8], 8);\n\n\t/* <draft-ietf-6man-rfc4941bis-08.txt>, Section 3.3.1:\n\t * check if generated address is not inappropriate:\n\t *\n\t * - Reserved IPv6 Interface Identifiers\n\t * - XXX: already assigned to an address on the device\n\t */\n\n\t/* Subnet-router anycast: 0000:0000:0000:0000 */\n\tif (!(addr->s6_addr32[2] | addr->s6_addr32[3]))\n\t\tgoto regen;\n\n\t/* IANA Ethernet block: 0200:5EFF:FE00:0000-0200:5EFF:FE00:5212\n\t * Proxy Mobile IPv6:   0200:5EFF:FE00:5213\n\t * IANA Ethernet block: 0200:5EFF:FE00:5214-0200:5EFF:FEFF:FFFF\n\t */\n\tif (ntohl(addr->s6_addr32[2]) == 0x02005eff &&\n\t    (ntohl(addr->s6_addr32[3]) & 0Xff000000) == 0xfe000000)\n\t\tgoto regen;\n\n\t/* Reserved subnet anycast addresses */\n\tif (ntohl(addr->s6_addr32[2]) == 0xfdffffff &&\n\t    ntohl(addr->s6_addr32[3]) >= 0Xffffff80)\n\t\tgoto regen;\n}",
        "static void replenish_dl_entity(struct sched_dl_entity *dl_se)\n{\n\tstruct dl_rq *dl_rq = dl_rq_of_se(dl_se);\n\tstruct rq *rq = rq_of_dl_rq(dl_rq);\n": "static void replenish_dl_entity(struct sched_dl_entity *dl_se)\n{\n\tstruct dl_rq *dl_rq = dl_rq_of_se(dl_se);\n\tstruct rq *rq = rq_of_dl_rq(dl_rq);\n\n\tBUG_ON(pi_of(dl_se)->dl_runtime <= 0);\n\n\t/*\n\t * This could be the case for a !-dl task that is boosted.\n\t * Just go with full inherited parameters.\n\t */\n\tif (dl_se->dl_deadline == 0) {\n\t\tdl_se->deadline = rq_clock(rq) + pi_of(dl_se)->dl_deadline;\n\t\tdl_se->runtime = pi_of(dl_se)->dl_runtime;\n\t}\n\n\tif (dl_se->dl_yielded && dl_se->runtime > 0)\n\t\tdl_se->runtime = 0;\n\n\t/*\n\t * We keep moving the deadline away until we get some\n\t * available runtime for the entity. This ensures correct\n\t * handling of situations where the runtime overrun is\n\t * arbitrary large.\n\t */\n\twhile (dl_se->runtime <= 0) {\n\t\tdl_se->deadline += pi_of(dl_se)->dl_period;\n\t\tdl_se->runtime += pi_of(dl_se)->dl_runtime;\n\t}\n\n\t/*\n\t * At this point, the deadline really should be \"in\n\t * the future\" with respect to rq->clock. If it's\n\t * not, we are, for some reason, lagging too much!\n\t * Anyway, after having warn userspace abut that,\n\t * we still try to keep the things running by\n\t * resetting the deadline and the budget of the\n\t * entity.\n\t */\n\tif (dl_time_before(dl_se->deadline, rq_clock(rq))) {\n\t\tprintk_deferred_once(\"sched: DL replenish lagged too much\\n\");\n\t\tdl_se->deadline = rq_clock(rq) + pi_of(dl_se)->dl_deadline;\n\t\tdl_se->runtime = pi_of(dl_se)->dl_runtime;\n\t}\n\n\tif (dl_se->dl_yielded)\n\t\tdl_se->dl_yielded = 0;\n\tif (dl_se->dl_throttled)\n\t\tdl_se->dl_throttled = 0;\n}",
        "static void do_optimize_kprobes(void)\n{\n\tlockdep_assert_held(&text_mutex);\n\t/*\n\t * The optimization/unoptimization refers 'online_cpus' via": "static void do_optimize_kprobes(void)\n{\n\tlockdep_assert_held(&text_mutex);\n\t/*\n\t * The optimization/unoptimization refers 'online_cpus' via\n\t * stop_machine() and cpu-hotplug modifies the 'online_cpus'.\n\t * And same time, 'text_mutex' will be held in cpu-hotplug and here.\n\t * This combination can cause a deadlock (cpu-hotplug tries to lock\n\t * 'text_mutex' but stop_machine() can not be done because\n\t * the 'online_cpus' has been changed)\n\t * To avoid this deadlock, caller must have locked cpu-hotplug\n\t * for preventing cpu-hotplug outside of 'text_mutex' locking.\n\t */\n\tlockdep_assert_cpus_held();\n\n\t/* Optimization never be done when disarmed */\n\tif (kprobes_all_disarmed || !kprobes_allow_optimization ||\n\t    list_empty(&optimizing_list))\n\t\treturn;\n\n\tarch_optimize_kprobes(&optimizing_list);\n}",
        "static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)\n{\n\tint err, output;\n\n\t/* Setup supported modes */": "static int tpacpi_dytc_profile_init(struct ibm_init_struct *iibm)\n{\n\tint err, output;\n\n\t/* Setup supported modes */\n\tset_bit(PLATFORM_PROFILE_LOW_POWER, dytc_profile.choices);\n\tset_bit(PLATFORM_PROFILE_BALANCED, dytc_profile.choices);\n\tset_bit(PLATFORM_PROFILE_PERFORMANCE, dytc_profile.choices);\n\n\tdytc_profile_available = DYTC_FUNCMODE_NONE;\n\terr = dytc_command(DYTC_CMD_QUERY, &output);\n\tif (err)\n\t\treturn err;\n\n\tif (output & BIT(DYTC_QUERY_ENABLE_BIT))\n\t\tdytc_version = (output >> DYTC_QUERY_REV_BIT) & 0xF;\n\n\t/* Check DYTC is enabled and supports mode setting */\n\tif (dytc_version < 5)\n\t\treturn -ENODEV;\n\n\t/* Check what capabilities are supported */\n\terr = dytc_command(DYTC_CMD_FUNC_CAP, &output);\n\tif (err)\n\t\treturn err;\n\n\tif (output & BIT(DYTC_FC_MMC)) { /* MMC MODE */\n\t\tdytc_profile_available = DYTC_FUNCMODE_MMC;\n\n\t\t/*\n\t\t * Check if MMC_GET functionality available\n\t\t * Version > 6 and return success from MMC_GET command\n\t\t */\n\t\tdytc_mmc_get_available = false;\n\t\tif (dytc_version >= 6) {\n\t\t\terr = dytc_command(DYTC_CMD_MMC_GET, &output);\n\t\t\tif (!err && ((output & DYTC_ERR_MASK) == DYTC_ERR_SUCCESS))\n\t\t\t\tdytc_mmc_get_available = true;\n\t\t}\n\t} else if (output & BIT(DYTC_FC_PSC)) { /* PSC MODE */\n\t\tdytc_profile_available = DYTC_FUNCMODE_PSC;\n\t} else {\n\t\tdbg_printk(TPACPI_DBG_INIT, \"No DYTC support available\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tdbg_printk(TPACPI_DBG_INIT,\n\t\t\t\"DYTC version %d: thermal mode available\\n\", dytc_version);\n\n\t/* Create platform_profile structure and register */\n\terr = platform_profile_register(&dytc_profile);\n\t/*\n\t * If for some reason platform_profiles aren't enabled\n\t * don't quit terminally.\n\t */\n\tif (err)\n\t\treturn -ENODEV;\n\n\t/* Ensure initial values are correct */\n\tdytc_profile_refresh();\n\n\treturn 0;\n}",
        "static int tegra_emc_devfreq_init(struct tegra_emc *emc)\n{\n\tstruct devfreq *devfreq;\n\n\t/*": "static int tegra_emc_devfreq_init(struct tegra_emc *emc)\n{\n\tstruct devfreq *devfreq;\n\n\t/*\n\t * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold\n\t * should be less than 50.  Secondly, multiple active memory clients\n\t * may cause over 20% of lost clock cycles due to stalls caused by\n\t * competing memory accesses.  This means that threshold should be\n\t * set to a less than 30 in order to have a properly working governor.\n\t */\n\temc->ondemand_data.upthreshold = 20;\n\n\t/*\n\t * Reset statistic gathers state, select global bandwidth for the\n\t * statistics collection mode and set clocks counter saturation\n\t * limit to maximum.\n\t */\n\twritel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);\n\twritel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);\n\twritel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);\n\n\tdevfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,\n\t\t\t\t\t  DEVFREQ_GOV_SIMPLE_ONDEMAND,\n\t\t\t\t\t  &emc->ondemand_data);\n\tif (IS_ERR(devfreq)) {\n\t\tdev_err(emc->dev, \"failed to initialize devfreq: %pe\", devfreq);\n\t\treturn PTR_ERR(devfreq);\n\t}\n\n\treturn 0;\n}",
        "static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)\n{\n\tstruct cx24110_state *state = fe->demodulator_priv;\n\n\tif (len != 3)": "static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)\n{\n\tstruct cx24110_state *state = fe->demodulator_priv;\n\n\tif (len != 3)\n\t\treturn -EINVAL;\n\n/* tuner data is 21 bits long, must be left-aligned in data */\n/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */\n/* FIXME (low): add error handling, avoid infinite loops if HW fails... */\n\n\tcx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */\n\tcx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */\n\n\t/* if the auto tuner writer is still busy, clear it out */\n\twhile (cx24110_readreg(state,0x6d)&0x80)\n\t\tcx24110_writereg(state,0x72,0);\n\n\t/* write the topmost 8 bits */\n\tcx24110_writereg(state,0x72,buf[0]);\n\n\t/* wait for the send to be completed */\n\twhile ((cx24110_readreg(state,0x6d)&0xc0)==0x80)\n\t\t;\n\n\t/* send another 8 bytes */\n\tcx24110_writereg(state,0x72,buf[1]);\n\twhile ((cx24110_readreg(state,0x6d)&0xc0)==0x80)\n\t\t;\n\n\t/* and the topmost 5 bits of this byte */\n\tcx24110_writereg(state,0x72,buf[2]);\n\twhile ((cx24110_readreg(state,0x6d)&0xc0)==0x80)\n\t\t;\n\n\t/* now strobe the enable line once */\n\tcx24110_writereg(state,0x6d,0x32);\n\tcx24110_writereg(state,0x6d,0x30);\n\n\treturn 0;\n}",
        "static int sev_ioctl_do_pdh_export(struct sev_issue_cmd *argp, bool writable)\n{\n\tstruct sev_device *sev = psp_master->sev_data;\n\tstruct sev_user_data_pdh_cert_export input;\n\tvoid *pdh_blob = NULL, *cert_blob = NULL;": "static int sev_ioctl_do_pdh_export(struct sev_issue_cmd *argp, bool writable)\n{\n\tstruct sev_device *sev = psp_master->sev_data;\n\tstruct sev_user_data_pdh_cert_export input;\n\tvoid *pdh_blob = NULL, *cert_blob = NULL;\n\tstruct sev_data_pdh_cert_export data;\n\tvoid __user *input_cert_chain_address;\n\tvoid __user *input_pdh_cert_address;\n\tint ret;\n\n\t/* If platform is not in INIT state then transition it to INIT. */\n\tif (sev->state != SEV_STATE_INIT) {\n\t\tif (!writable)\n\t\t\treturn -EPERM;\n\n\t\tret = __sev_platform_init_locked(&argp->error);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tif (copy_from_user(&input, (void __user *)argp->data, sizeof(input)))\n\t\treturn -EFAULT;\n\n\tmemset(&data, 0, sizeof(data));\n\n\t/* Userspace wants to query the certificate length. */\n\tif (!input.pdh_cert_address ||\n\t    !input.pdh_cert_len ||\n\t    !input.cert_chain_address)\n\t\tgoto cmd;\n\n\tinput_pdh_cert_address = (void __user *)input.pdh_cert_address;\n\tinput_cert_chain_address = (void __user *)input.cert_chain_address;\n\n\t/* Allocate a physically contiguous buffer to store the PDH blob. */\n\tif (input.pdh_cert_len > SEV_FW_BLOB_MAX_SIZE)\n\t\treturn -EFAULT;\n\n\t/* Allocate a physically contiguous buffer to store the cert chain blob. */\n\tif (input.cert_chain_len > SEV_FW_BLOB_MAX_SIZE)\n\t\treturn -EFAULT;\n\n\tpdh_blob = kmalloc(input.pdh_cert_len, GFP_KERNEL);\n\tif (!pdh_blob)\n\t\treturn -ENOMEM;\n\n\tdata.pdh_cert_address = __psp_pa(pdh_blob);\n\tdata.pdh_cert_len = input.pdh_cert_len;\n\n\tcert_blob = kmalloc(input.cert_chain_len, GFP_KERNEL);\n\tif (!cert_blob) {\n\t\tret = -ENOMEM;\n\t\tgoto e_free_pdh;\n\t}\n\n\tdata.cert_chain_address = __psp_pa(cert_blob);\n\tdata.cert_chain_len = input.cert_chain_len;\n\ncmd:\n\tret = __sev_do_cmd_locked(SEV_CMD_PDH_CERT_EXPORT, &data, &argp->error);\n\n\t/* If we query the length, FW responded with expected data. */\n\tinput.cert_chain_len = data.cert_chain_len;\n\tinput.pdh_cert_len = data.pdh_cert_len;\n\n\tif (copy_to_user((void __user *)argp->data, &input, sizeof(input))) {\n\t\tret = -EFAULT;\n\t\tgoto e_free_cert;\n\t}\n\n\tif (pdh_blob) {\n\t\tif (copy_to_user(input_pdh_cert_address,\n\t\t\t\t pdh_blob, input.pdh_cert_len)) {\n\t\t\tret = -EFAULT;\n\t\t\tgoto e_free_cert;\n\t\t}\n\t}\n\n\tif (cert_blob) {\n\t\tif (copy_to_user(input_cert_chain_address,\n\t\t\t\t cert_blob, input.cert_chain_len))\n\t\t\tret = -EFAULT;\n\t}\n\ne_free_cert:\n\tkfree(cert_blob);\ne_free_pdh:\n\tkfree(pdh_blob);\n\treturn ret;\n}",
        "static unsigned long kunit_test_timeout(void)\n{\n\t/*\n\t * TODO(brendanhiggins@google.com): We should probably have some type of\n\t * variable timeout here. The only question is what that timeout value": "static unsigned long kunit_test_timeout(void)\n{\n\t/*\n\t * TODO(brendanhiggins@google.com): We should probably have some type of\n\t * variable timeout here. The only question is what that timeout value\n\t * should be.\n\t *\n\t * The intention has always been, at some point, to be able to label\n\t * tests with some type of size bucket (unit/small, integration/medium,\n\t * large/system/end-to-end, etc), where each size bucket would get a\n\t * default timeout value kind of like what Bazel does:\n\t * https://docs.bazel.build/versions/master/be/common-definitions.html#test.size\n\t * There is still some debate to be had on exactly how we do this. (For\n\t * one, we probably want to have some sort of test runner level\n\t * timeout.)\n\t *\n\t * For more background on this topic, see:\n\t * https://mike-bland.com/2011/11/01/small-medium-large.html\n\t *\n\t * If tests timeout due to exceeding sysctl_hung_task_timeout_secs,\n\t * the task will be killed and an oops generated.\n\t */\n\treturn 300 * msecs_to_jiffies(MSEC_PER_SEC); /* 5 min */\n}",
        "static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)\n{\n\tvoid __iomem *cfg_region;\n\tstruct arm_cmn_node cfg, *dn;\n\tstruct arm_cmn_dtm *dtm;": "static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)\n{\n\tvoid __iomem *cfg_region;\n\tstruct arm_cmn_node cfg, *dn;\n\tstruct arm_cmn_dtm *dtm;\n\tu16 child_count, child_poff;\n\tu32 xp_offset[CMN_MAX_XPS];\n\tu64 reg;\n\tint i, j;\n\tsize_t sz;\n\n\tarm_cmn_init_node_info(cmn, rgn_offset, &cfg);\n\tif (cfg.type != CMN_TYPE_CFG)\n\t\treturn -ENODEV;\n\n\tcfg_region = cmn->base + rgn_offset;\n\treg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2);\n\tcmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);\n\n\treg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);\n\tcmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;\n\tcmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);\n\tcmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);\n\n\treg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);\n\tcmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);\n\tcmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);\n\n\treg = readq_relaxed(cfg_region + CMN_CHILD_INFO);\n\tchild_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);\n\tchild_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);\n\n\tcmn->num_xps = child_count;\n\tcmn->num_dns = cmn->num_xps;\n\n\t/* Pass 1: visit the XPs, enumerate their children */\n\tfor (i = 0; i < cmn->num_xps; i++) {\n\t\treg = readq_relaxed(cfg_region + child_poff + i * 8);\n\t\txp_offset[i] = reg & CMN_CHILD_NODE_ADDR;\n\n\t\treg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);\n\t\tcmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);\n\t}\n\n\t/*\n\t * Some nodes effectively have two separate types, which we'll handle\n\t * by creating one of each internally. For a (very) safe initial upper\n\t * bound, account for double the number of non-XP nodes.\n\t */\n\tdn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,\n\t\t\t  sizeof(*dn), GFP_KERNEL);\n\tif (!dn)\n\t\treturn -ENOMEM;\n\n\t/* Initial safe upper bound on DTMs for any possible mesh layout */\n\ti = cmn->num_xps;\n\tif (cmn->multi_dtm)\n\t\ti += cmn->num_xps + 1;\n\tdtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);\n\tif (!dtm)\n\t\treturn -ENOMEM;\n\n\t/* Pass 2: now we can actually populate the nodes */\n\tcmn->dns = dn;\n\tcmn->dtms = dtm;\n\tfor (i = 0; i < cmn->num_xps; i++) {\n\t\tvoid __iomem *xp_region = cmn->base + xp_offset[i];\n\t\tstruct arm_cmn_node *xp = dn++;\n\t\tunsigned int xp_ports = 0;\n\n\t\tarm_cmn_init_node_info(cmn, xp_offset[i], xp);\n\t\t/*\n\t\t * Thanks to the order in which XP logical IDs seem to be\n\t\t * assigned, we can handily infer the mesh X dimension by\n\t\t * looking out for the XP at (0,1) without needing to know\n\t\t * the exact node ID format, which we can later derive.\n\t\t */\n\t\tif (xp->id == (1 << 3))\n\t\t\tcmn->mesh_x = xp->logid;\n\n\t\tif (cmn->model == CMN600)\n\t\t\txp->dtc = 0xf;\n\t\telse\n\t\t\txp->dtc = 1 << readl_relaxed(xp_region + CMN_DTM_UNIT_INFO);\n\n\t\txp->dtm = dtm - cmn->dtms;\n\t\tarm_cmn_init_dtm(dtm++, xp, 0);\n\t\t/*\n\t\t * Keeping track of connected ports will let us filter out\n\t\t * unnecessary XP events easily. We can also reliably infer the\n\t\t * \"extra device ports\" configuration for the node ID format\n\t\t * from this, since in that case we will see at least one XP\n\t\t * with port 2 connected, for the HN-D.\n\t\t */\n\t\tif (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P0))\n\t\t\txp_ports |= BIT(0);\n\t\tif (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P1))\n\t\t\txp_ports |= BIT(1);\n\t\tif (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P2))\n\t\t\txp_ports |= BIT(2);\n\t\tif (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P3))\n\t\t\txp_ports |= BIT(3);\n\t\tif (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P4))\n\t\t\txp_ports |= BIT(4);\n\t\tif (readq_relaxed(xp_region + CMN_MXP__CONNECT_INFO_P5))\n\t\t\txp_ports |= BIT(5);\n\n\t\tif (cmn->multi_dtm && (xp_ports & 0xc))\n\t\t\tarm_cmn_init_dtm(dtm++, xp, 1);\n\t\tif (cmn->multi_dtm && (xp_ports & 0x30))\n\t\t\tarm_cmn_init_dtm(dtm++, xp, 2);\n\n\t\tcmn->ports_used |= xp_ports;\n\n\t\treg = readq_relaxed(xp_region + CMN_CHILD_INFO);\n\t\tchild_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);\n\t\tchild_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);\n\n\t\tfor (j = 0; j < child_count; j++) {\n\t\t\treg = readq_relaxed(xp_region + child_poff + j * 8);\n\t\t\t/*\n\t\t\t * Don't even try to touch anything external, since in general\n\t\t\t * we haven't a clue how to power up arbitrary CHI requesters.\n\t\t\t * As of CMN-600r1 these could only be RN-SAMs or CXLAs,\n\t\t\t * neither of which have any PMU events anyway.\n\t\t\t * (Actually, CXLAs do seem to have grown some events in r1p2,\n\t\t\t * but they don't go to regular XP DTMs, and they depend on\n\t\t\t * secure configuration which we can't easily deal with)\n\t\t\t */\n\t\t\tif (reg & CMN_CHILD_NODE_EXTERNAL) {\n\t\t\t\tdev_dbg(cmn->dev, \"ignoring external node %llx\\n\", reg);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tarm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);\n\n\t\t\tswitch (dn->type) {\n\t\t\tcase CMN_TYPE_DTC:\n\t\t\t\tcmn->num_dtcs++;\n\t\t\t\tdn++;\n\t\t\t\tbreak;\n\t\t\t/* These guys have PMU events */\n\t\t\tcase CMN_TYPE_DVM:\n\t\t\tcase CMN_TYPE_HNI:\n\t\t\tcase CMN_TYPE_HNF:\n\t\t\tcase CMN_TYPE_SBSX:\n\t\t\tcase CMN_TYPE_RNI:\n\t\t\tcase CMN_TYPE_RND:\n\t\t\tcase CMN_TYPE_MTSX:\n\t\t\tcase CMN_TYPE_CXRA:\n\t\t\tcase CMN_TYPE_CXHA:\n\t\t\tcase CMN_TYPE_CCRA:\n\t\t\tcase CMN_TYPE_CCHA:\n\t\t\tcase CMN_TYPE_CCLA:\n\t\t\t\tdn++;\n\t\t\t\tbreak;\n\t\t\t/* Nothing to see here */\n\t\t\tcase CMN_TYPE_MPAM_S:\n\t\t\tcase CMN_TYPE_MPAM_NS:\n\t\t\tcase CMN_TYPE_RNSAM:\n\t\t\tcase CMN_TYPE_CXLA:\n\t\t\t\tbreak;\n\t\t\t/*\n\t\t\t * Split \"optimised\" combination nodes into separate\n\t\t\t * types for the different event sets. Offsetting the\n\t\t\t * base address lets us handle the second pmu_event_sel\n\t\t\t * register via the normal mechanism later.\n\t\t\t */\n\t\t\tcase CMN_TYPE_HNP:\n\t\t\tcase CMN_TYPE_CCLA_RNI:\n\t\t\t\tdn[1] = dn[0];\n\t\t\t\tdn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL;\n\t\t\t\tdn[1].type = arm_cmn_subtype(dn->type);\n\t\t\t\tdn += 2;\n\t\t\t\tbreak;\n\t\t\t/* Something has gone horribly wrong */\n\t\t\tdefault:\n\t\t\t\tdev_err(cmn->dev, \"invalid device node type: 0x%x\\n\", dn->type);\n\t\t\t\treturn -ENODEV;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Correct for any nodes we added or skipped */\n\tcmn->num_dns = dn - cmn->dns;\n\n\t/* Cheeky +1 to help terminate pointer-based iteration later */\n\tsz = (void *)(dn + 1) - (void *)cmn->dns;\n\tdn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);\n\tif (dn)\n\t\tcmn->dns = dn;\n\n\tsz = (void *)dtm - (void *)cmn->dtms;\n\tdtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);\n\tif (dtm)\n\t\tcmn->dtms = dtm;\n\n\t/*\n\t * If mesh_x wasn't set during discovery then we never saw\n\t * an XP at (0,1), thus we must have an Nx1 configuration.\n\t */\n\tif (!cmn->mesh_x)\n\t\tcmn->mesh_x = cmn->num_xps;\n\tcmn->mesh_y = cmn->num_xps / cmn->mesh_x;\n\n\t/* 1x1 config plays havoc with XP event encodings */\n\tif (cmn->num_xps == 1)\n\t\tdev_warn(cmn->dev, \"1x1 config not fully supported, translate XP events manually\\n\");\n\n\tdev_dbg(cmn->dev, \"model %d, periph_id_2 revision %d\\n\", cmn->model, cmn->rev);\n\treg = cmn->ports_used;\n\tdev_dbg(cmn->dev, \"mesh %dx%d, ID width %d, ports %6pbl%s\\n\",\n\t\tcmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), &reg,\n\t\tcmn->multi_dtm ? \", multi-DTM\" : \"\");\n\n\treturn 0;\n}",
        "static int cake_config_diffserv3(struct Qdisc *sch)\n{\n/*  Simplified Diffserv structure with 3 tins.\n *\t\tLatency Sensitive\t(CS7, CS6, EF, VA, TOS4)\n *\t\tBest Effort": "static int cake_config_diffserv3(struct Qdisc *sch)\n{\n/*  Simplified Diffserv structure with 3 tins.\n *\t\tLatency Sensitive\t(CS7, CS6, EF, VA, TOS4)\n *\t\tBest Effort\n *\t\tLow Priority\t\t(LE, CS1)\n */\n\tstruct cake_sched_data *q = qdisc_priv(sch);\n\tu32 mtu = psched_mtu(qdisc_dev(sch));\n\tu64 rate = q->rate_bps;\n\tu32 quantum = 1024;\n\n\tq->tin_cnt = 3;\n\n\t/* codepoint to class mapping */\n\tq->tin_index = diffserv3;\n\tq->tin_order = bulk_order;\n\n\t/* class characteristics */\n\tcake_set_rate(&q->tins[0], rate, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\tcake_set_rate(&q->tins[1], rate >> 4, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\tcake_set_rate(&q->tins[2], rate >> 2, mtu,\n\t\t      us_to_ns(q->target), us_to_ns(q->interval));\n\n\t/* bandwidth-sharing weights */\n\tq->tins[0].tin_quantum = quantum;\n\tq->tins[1].tin_quantum = quantum >> 4;\n\tq->tins[2].tin_quantum = quantum >> 2;\n\n\treturn 0;\n}",
        "static int lm3532_init_registers(struct lm3532_led *led)\n{\n\tstruct lm3532_data *drvdata = led->priv;\n\tunsigned int runtime_ramp_val;\n\tunsigned int output_cfg_val = 0;": "static int lm3532_init_registers(struct lm3532_led *led)\n{\n\tstruct lm3532_data *drvdata = led->priv;\n\tunsigned int runtime_ramp_val;\n\tunsigned int output_cfg_val = 0;\n\tunsigned int output_cfg_shift = 0;\n\tunsigned int output_cfg_mask = 0;\n\tunsigned int brightness_config_reg;\n\tunsigned int brightness_config_val;\n\tint fs_current_reg;\n\tint fs_current_val;\n\tint ret, i;\n\n\tif (drvdata->enable_gpio)\n\t\tgpiod_direction_output(drvdata->enable_gpio, 1);\n\n\tbrightness_config_reg = LM3532_REG_ZONE_CFG_A + led->control_bank * 2;\n\t/*\n\t * This could be hard coded to the default value but the control\n\t * brightness register may have changed during boot.\n\t */\n\tret = regmap_read(drvdata->regmap, brightness_config_reg,\n\t\t\t  &led->ctrl_brt_pointer);\n\tif (ret)\n\t\treturn ret;\n\n\tled->ctrl_brt_pointer &= LM3532_ZONE_MASK;\n\tbrightness_config_val = led->ctrl_brt_pointer | led->mode;\n\tret = regmap_write(drvdata->regmap, brightness_config_reg,\n\t\t\t   brightness_config_val);\n\tif (ret)\n\t\treturn ret;\n\n\tif (led->full_scale_current) {\n\t\tfs_current_reg = LM3532_REG_CTRL_A_FS_CURR + led->control_bank * 2;\n\t\tfs_current_val = (led->full_scale_current - LM3532_FS_CURR_MIN) /\n\t\t\t\t LM3532_FS_CURR_STEP;\n\n\t\tret = regmap_write(drvdata->regmap, fs_current_reg,\n\t\t\t\t   fs_current_val);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tfor (i = 0; i < led->num_leds; i++) {\n\t\toutput_cfg_shift = led->led_strings[i] * 2;\n\t\toutput_cfg_val |= (led->control_bank << output_cfg_shift);\n\t\toutput_cfg_mask |= LM3532_OUTPUT_CFG_MASK << output_cfg_shift;\n\t}\n\n\tret = regmap_update_bits(drvdata->regmap, LM3532_REG_OUTPUT_CFG,\n\t\t\t\t output_cfg_mask, output_cfg_val);\n\tif (ret)\n\t\treturn ret;\n\n\truntime_ramp_val = drvdata->runtime_ramp_up |\n\t\t\t (drvdata->runtime_ramp_down << LM3532_RAMP_DOWN_SHIFT);\n\n\treturn regmap_write(drvdata->regmap, LM3532_REG_RT_RAMP,\n\t\t\t    runtime_ramp_val);\n}",
        "static void __ksmbd_close_fd(struct ksmbd_file_table *ft, struct ksmbd_file *fp)\n{\n\tstruct file *filp;\n\tstruct ksmbd_lock *smb_lock, *tmp_lock;\n": "static void __ksmbd_close_fd(struct ksmbd_file_table *ft, struct ksmbd_file *fp)\n{\n\tstruct file *filp;\n\tstruct ksmbd_lock *smb_lock, *tmp_lock;\n\n\tfd_limit_close();\n\t__ksmbd_remove_durable_fd(fp);\n\t__ksmbd_remove_fd(ft, fp);\n\n\tclose_id_del_oplock(fp);\n\tfilp = fp->filp;\n\n\t__ksmbd_inode_close(fp);\n\tif (!IS_ERR_OR_NULL(filp))\n\t\tfput(filp);\n\n\t/* because the reference count of fp is 0, it is guaranteed that\n\t * there are not accesses to fp->lock_list.\n\t */\n\tlist_for_each_entry_safe(smb_lock, tmp_lock, &fp->lock_list, flist) {\n\t\tspin_lock(&fp->conn->llist_lock);\n\t\tlist_del(&smb_lock->clist);\n\t\tspin_unlock(&fp->conn->llist_lock);\n\n\t\tlist_del(&smb_lock->flist);\n\t\tlocks_free_lock(smb_lock->fl);\n\t\tkfree(smb_lock);\n\t}\n\n\tif (ksmbd_stream_fd(fp))\n\t\tkfree(fp->stream.name);\n\tkmem_cache_free(filp_cache, fp);\n}",
        "static int kdb_md(int argc, const char **argv)\n{\n\tstatic unsigned long last_addr;\n\tstatic int last_radix, last_bytesperword, last_repeat;\n\tint radix = 16, mdcount = 8, bytesperword = KDB_WORD_SIZE, repeat;": "static int kdb_md(int argc, const char **argv)\n{\n\tstatic unsigned long last_addr;\n\tstatic int last_radix, last_bytesperword, last_repeat;\n\tint radix = 16, mdcount = 8, bytesperword = KDB_WORD_SIZE, repeat;\n\tint nosect = 0;\n\tchar fmtchar, fmtstr[64];\n\tunsigned long addr;\n\tunsigned long word;\n\tlong offset = 0;\n\tint symbolic = 0;\n\tint valid = 0;\n\tint phys = 0;\n\tint raw = 0;\n\n\tkdbgetintenv(\"MDCOUNT\", &mdcount);\n\tkdbgetintenv(\"RADIX\", &radix);\n\tkdbgetintenv(\"BYTESPERWORD\", &bytesperword);\n\n\t/* Assume 'md <addr>' and start with environment values */\n\trepeat = mdcount * 16 / bytesperword;\n\n\tif (strcmp(argv[0], \"mdr\") == 0) {\n\t\tif (argc == 2 || (argc == 0 && last_addr != 0))\n\t\t\tvalid = raw = 1;\n\t\telse\n\t\t\treturn KDB_ARGCOUNT;\n\t} else if (isdigit(argv[0][2])) {\n\t\tbytesperword = (int)(argv[0][2] - '0');\n\t\tif (bytesperword == 0) {\n\t\t\tbytesperword = last_bytesperword;\n\t\t\tif (bytesperword == 0)\n\t\t\t\tbytesperword = 4;\n\t\t}\n\t\tlast_bytesperword = bytesperword;\n\t\trepeat = mdcount * 16 / bytesperword;\n\t\tif (!argv[0][3])\n\t\t\tvalid = 1;\n\t\telse if (argv[0][3] == 'c' && argv[0][4]) {\n\t\t\tchar *p;\n\t\t\trepeat = simple_strtoul(argv[0] + 4, &p, 10);\n\t\t\tmdcount = ((repeat * bytesperword) + 15) / 16;\n\t\t\tvalid = !*p;\n\t\t}\n\t\tlast_repeat = repeat;\n\t} else if (strcmp(argv[0], \"md\") == 0)\n\t\tvalid = 1;\n\telse if (strcmp(argv[0], \"mds\") == 0)\n\t\tvalid = 1;\n\telse if (strcmp(argv[0], \"mdp\") == 0) {\n\t\tphys = valid = 1;\n\t}\n\tif (!valid)\n\t\treturn KDB_NOTFOUND;\n\n\tif (argc == 0) {\n\t\tif (last_addr == 0)\n\t\t\treturn KDB_ARGCOUNT;\n\t\taddr = last_addr;\n\t\tradix = last_radix;\n\t\tbytesperword = last_bytesperword;\n\t\trepeat = last_repeat;\n\t\tif (raw)\n\t\t\tmdcount = repeat;\n\t\telse\n\t\t\tmdcount = ((repeat * bytesperword) + 15) / 16;\n\t}\n\n\tif (argc) {\n\t\tunsigned long val;\n\t\tint diag, nextarg = 1;\n\t\tdiag = kdbgetaddrarg(argc, argv, &nextarg, &addr,\n\t\t\t\t     &offset, NULL);\n\t\tif (diag)\n\t\t\treturn diag;\n\t\tif (argc > nextarg+2)\n\t\t\treturn KDB_ARGCOUNT;\n\n\t\tif (argc >= nextarg) {\n\t\t\tdiag = kdbgetularg(argv[nextarg], &val);\n\t\t\tif (!diag) {\n\t\t\t\tmdcount = (int) val;\n\t\t\t\tif (raw)\n\t\t\t\t\trepeat = mdcount;\n\t\t\t\telse\n\t\t\t\t\trepeat = mdcount * 16 / bytesperword;\n\t\t\t}\n\t\t}\n\t\tif (argc >= nextarg+1) {\n\t\t\tdiag = kdbgetularg(argv[nextarg+1], &val);\n\t\t\tif (!diag)\n\t\t\t\tradix = (int) val;\n\t\t}\n\t}\n\n\tif (strcmp(argv[0], \"mdr\") == 0) {\n\t\tint ret;\n\t\tlast_addr = addr;\n\t\tret = kdb_mdr(addr, mdcount);\n\t\tlast_addr += mdcount;\n\t\tlast_repeat = mdcount;\n\t\tlast_bytesperword = bytesperword; // to make REPEAT happy\n\t\treturn ret;\n\t}\n\n\tswitch (radix) {\n\tcase 10:\n\t\tfmtchar = 'd';\n\t\tbreak;\n\tcase 16:\n\t\tfmtchar = 'x';\n\t\tbreak;\n\tcase 8:\n\t\tfmtchar = 'o';\n\t\tbreak;\n\tdefault:\n\t\treturn KDB_BADRADIX;\n\t}\n\n\tlast_radix = radix;\n\n\tif (bytesperword > KDB_WORD_SIZE)\n\t\treturn KDB_BADWIDTH;\n\n\tswitch (bytesperword) {\n\tcase 8:\n\t\tsprintf(fmtstr, \"%%16.16l%c \", fmtchar);\n\t\tbreak;\n\tcase 4:\n\t\tsprintf(fmtstr, \"%%8.8l%c \", fmtchar);\n\t\tbreak;\n\tcase 2:\n\t\tsprintf(fmtstr, \"%%4.4l%c \", fmtchar);\n\t\tbreak;\n\tcase 1:\n\t\tsprintf(fmtstr, \"%%2.2l%c \", fmtchar);\n\t\tbreak;\n\tdefault:\n\t\treturn KDB_BADWIDTH;\n\t}\n\n\tlast_repeat = repeat;\n\tlast_bytesperword = bytesperword;\n\n\tif (strcmp(argv[0], \"mds\") == 0) {\n\t\tsymbolic = 1;\n\t\t/* Do not save these changes as last_*, they are temporary mds\n\t\t * overrides.\n\t\t */\n\t\tbytesperword = KDB_WORD_SIZE;\n\t\trepeat = mdcount;\n\t\tkdbgetintenv(\"NOSECT\", &nosect);\n\t}\n\n\t/* Round address down modulo BYTESPERWORD */\n\n\taddr &= ~(bytesperword-1);\n\n\twhile (repeat > 0) {\n\t\tunsigned long a;\n\t\tint n, z, num = (symbolic ? 1 : (16 / bytesperword));\n\n\t\tif (KDB_FLAG(CMD_INTERRUPT))\n\t\t\treturn 0;\n\t\tfor (a = addr, z = 0; z < repeat; a += bytesperword, ++z) {\n\t\t\tif (phys) {\n\t\t\t\tif (kdb_getphysword(&word, a, bytesperword)\n\t\t\t\t\t\t|| word)\n\t\t\t\t\tbreak;\n\t\t\t} else if (kdb_getword(&word, a, bytesperword) || word)\n\t\t\t\tbreak;\n\t\t}\n\t\tn = min(num, repeat);\n\t\tkdb_md_line(fmtstr, addr, symbolic, nosect, bytesperword,\n\t\t\t    num, repeat, phys);\n\t\taddr += bytesperword * n;\n\t\trepeat -= n;\n\t\tz = (z + num - 1) / num;\n\t\tif (z > 2) {\n\t\t\tint s = num * (z-2);\n\t\t\tkdb_printf(kdb_machreg_fmt0 \"-\" kdb_machreg_fmt0\n\t\t\t\t   \" zero suppressed\\n\",\n\t\t\t\taddr, addr + bytesperword * s - 1);\n\t\t\taddr += bytesperword * s;\n\t\t\trepeat -= s;\n\t\t}\n\t}\n\tlast_addr = addr;\n\n\treturn 0;\n}",
        "static void set_ref(struct hantro_ctx *ctx)\n{\n\tconst struct v4l2_h264_reference *b0_reflist, *b1_reflist, *p_reflist;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tint reg_num;": "static void set_ref(struct hantro_ctx *ctx)\n{\n\tconst struct v4l2_h264_reference *b0_reflist, *b1_reflist, *p_reflist;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tint reg_num;\n\tu32 reg;\n\tint i;\n\n\tvdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);\n\tvdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);\n\n\t/*\n\t * Set up reference frame picture numbers.\n\t *\n\t * Each G1_REG_REF_PIC(x) register contains numbers of two\n\t * subsequential reference pictures.\n\t */\n\tfor (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) {\n\t\treg = G1_REG_REF_PIC_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, i)) |\n\t\t      G1_REG_REF_PIC_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, i + 1));\n\t\tvdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2));\n\t}\n\n\tb0_reflist = ctx->h264_dec.reflists.b0;\n\tb1_reflist = ctx->h264_dec.reflists.b1;\n\tp_reflist = ctx->h264_dec.reflists.p;\n\n\t/*\n\t * Each G1_REG_BD_REF_PIC(x) register contains three entries\n\t * of each forward and backward picture list.\n\t */\n\treg_num = 0;\n\tfor (i = 0; i < 15; i += 3) {\n\t\treg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i].index) |\n\t\t      G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1].index) |\n\t\t      G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2].index) |\n\t\t      G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i].index) |\n\t\t      G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1].index) |\n\t\t      G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2].index);\n\t\tvdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));\n\t}\n\n\t/*\n\t * G1_REG_BD_P_REF_PIC register contains last entries (index 15)\n\t * of forward and backward reference picture lists and first 4 entries\n\t * of P forward picture list.\n\t */\n\treg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15].index) |\n\t      G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15].index) |\n\t      G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0].index) |\n\t      G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1].index) |\n\t      G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2].index) |\n\t      G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3].index);\n\tvdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC);\n\n\t/*\n\t * Each G1_REG_FWD_PIC(x) register contains six consecutive\n\t * entries of P forward picture list, starting from index 4.\n\t */\n\treg_num = 0;\n\tfor (i = 4; i < HANTRO_H264_DPB_SIZE; i += 6) {\n\t\treg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i].index) |\n\t\t      G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1].index) |\n\t\t      G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2].index) |\n\t\t      G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3].index) |\n\t\t      G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4].index) |\n\t\t      G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5].index);\n\t\tvdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++));\n\t}\n\n\t/* Set up addresses of DPB buffers. */\n\tfor (i = 0; i < HANTRO_H264_DPB_SIZE; i++) {\n\t\tdma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i);\n\n\t\tvdpu_write_relaxed(vpu, dma_addr, G1_REG_ADDR_REF(i));\n\t}\n}",
        "static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)\n{\n\t/*\n\t * The driver currently handles the 8168Bf and the 8168Be identically\n\t * but they can be identified more specifically through the test below": "static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)\n{\n\t/*\n\t * The driver currently handles the 8168Bf and the 8168Be identically\n\t * but they can be identified more specifically through the test below\n\t * if needed:\n\t *\n\t * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be\n\t *\n\t * Same thing for the 8101Eb and the 8101Ec:\n\t *\n\t * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec\n\t */\n\tstatic const struct rtl_mac_info {\n\t\tu16 mask;\n\t\tu16 val;\n\t\tenum mac_version ver;\n\t} mac_info[] = {\n\t\t/* 8125B family. */\n\t\t{ 0x7cf, 0x641,\tRTL_GIGA_MAC_VER_63 },\n\n\t\t/* 8125A family. */\n\t\t{ 0x7cf, 0x609,\tRTL_GIGA_MAC_VER_61 },\n\t\t/* It seems only XID 609 made it to the mass market.\n\t\t * { 0x7cf, 0x608,\tRTL_GIGA_MAC_VER_60 },\n\t\t * { 0x7c8, 0x608,\tRTL_GIGA_MAC_VER_61 },\n\t\t */\n\n\t\t/* RTL8117 */\n\t\t{ 0x7cf, 0x54b,\tRTL_GIGA_MAC_VER_53 },\n\t\t{ 0x7cf, 0x54a,\tRTL_GIGA_MAC_VER_52 },\n\n\t\t/* 8168EP family. */\n\t\t{ 0x7cf, 0x502,\tRTL_GIGA_MAC_VER_51 },\n\t\t/* It seems this chip version never made it to\n\t\t * the wild. Let's disable detection.\n\t\t * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },\n\t\t * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },\n\t\t */\n\n\t\t/* 8168H family. */\n\t\t{ 0x7cf, 0x541,\tRTL_GIGA_MAC_VER_46 },\n\t\t/* It seems this chip version never made it to\n\t\t * the wild. Let's disable detection.\n\t\t * { 0x7cf, 0x540,\tRTL_GIGA_MAC_VER_45 },\n\t\t */\n\n\t\t/* 8168G family. */\n\t\t{ 0x7cf, 0x5c8,\tRTL_GIGA_MAC_VER_44 },\n\t\t{ 0x7cf, 0x509,\tRTL_GIGA_MAC_VER_42 },\n\t\t/* It seems this chip version never made it to\n\t\t * the wild. Let's disable detection.\n\t\t * { 0x7cf, 0x4c1,\tRTL_GIGA_MAC_VER_41 },\n\t\t */\n\t\t{ 0x7cf, 0x4c0,\tRTL_GIGA_MAC_VER_40 },\n\n\t\t/* 8168F family. */\n\t\t{ 0x7c8, 0x488,\tRTL_GIGA_MAC_VER_38 },\n\t\t{ 0x7cf, 0x481,\tRTL_GIGA_MAC_VER_36 },\n\t\t{ 0x7cf, 0x480,\tRTL_GIGA_MAC_VER_35 },\n\n\t\t/* 8168E family. */\n\t\t{ 0x7c8, 0x2c8,\tRTL_GIGA_MAC_VER_34 },\n\t\t{ 0x7cf, 0x2c1,\tRTL_GIGA_MAC_VER_32 },\n\t\t{ 0x7c8, 0x2c0,\tRTL_GIGA_MAC_VER_33 },\n\n\t\t/* 8168D family. */\n\t\t{ 0x7cf, 0x281,\tRTL_GIGA_MAC_VER_25 },\n\t\t{ 0x7c8, 0x280,\tRTL_GIGA_MAC_VER_26 },\n\n\t\t/* 8168DP family. */\n\t\t/* It seems this early RTL8168dp version never made it to\n\t\t * the wild. Support has been removed.\n\t\t * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },\n\t\t */\n\t\t{ 0x7cf, 0x28a,\tRTL_GIGA_MAC_VER_28 },\n\t\t{ 0x7cf, 0x28b,\tRTL_GIGA_MAC_VER_31 },\n\n\t\t/* 8168C family. */\n\t\t{ 0x7cf, 0x3c9,\tRTL_GIGA_MAC_VER_23 },\n\t\t{ 0x7cf, 0x3c8,\tRTL_GIGA_MAC_VER_18 },\n\t\t{ 0x7c8, 0x3c8,\tRTL_GIGA_MAC_VER_24 },\n\t\t{ 0x7cf, 0x3c0,\tRTL_GIGA_MAC_VER_19 },\n\t\t{ 0x7cf, 0x3c2,\tRTL_GIGA_MAC_VER_20 },\n\t\t{ 0x7cf, 0x3c3,\tRTL_GIGA_MAC_VER_21 },\n\t\t{ 0x7c8, 0x3c0,\tRTL_GIGA_MAC_VER_22 },\n\n\t\t/* 8168B family. */\n\t\t{ 0x7cf, 0x380,\tRTL_GIGA_MAC_VER_12 },\n\t\t{ 0x7c8, 0x380,\tRTL_GIGA_MAC_VER_17 },\n\t\t{ 0x7c8, 0x300,\tRTL_GIGA_MAC_VER_11 },\n\n\t\t/* 8101 family. */\n\t\t{ 0x7c8, 0x448,\tRTL_GIGA_MAC_VER_39 },\n\t\t{ 0x7c8, 0x440,\tRTL_GIGA_MAC_VER_37 },\n\t\t{ 0x7cf, 0x409,\tRTL_GIGA_MAC_VER_29 },\n\t\t{ 0x7c8, 0x408,\tRTL_GIGA_MAC_VER_30 },\n\t\t{ 0x7cf, 0x349,\tRTL_GIGA_MAC_VER_08 },\n\t\t{ 0x7cf, 0x249,\tRTL_GIGA_MAC_VER_08 },\n\t\t{ 0x7cf, 0x348,\tRTL_GIGA_MAC_VER_07 },\n\t\t{ 0x7cf, 0x248,\tRTL_GIGA_MAC_VER_07 },\n\t\t{ 0x7cf, 0x340,\tRTL_GIGA_MAC_VER_13 },\n\t\t{ 0x7cf, 0x240,\tRTL_GIGA_MAC_VER_14 },\n\t\t{ 0x7cf, 0x343,\tRTL_GIGA_MAC_VER_10 },\n\t\t{ 0x7cf, 0x342,\tRTL_GIGA_MAC_VER_16 },\n\t\t{ 0x7c8, 0x348,\tRTL_GIGA_MAC_VER_09 },\n\t\t{ 0x7c8, 0x248,\tRTL_GIGA_MAC_VER_09 },\n\t\t{ 0x7c8, 0x340,\tRTL_GIGA_MAC_VER_16 },\n\t\t/* FIXME: where did these entries come from ? -- FR\n\t\t * Not even r8101 vendor driver knows these id's,\n\t\t * so let's disable detection for now. -- HK\n\t\t * { 0xfc8, 0x388,\tRTL_GIGA_MAC_VER_13 },\n\t\t * { 0xfc8, 0x308,\tRTL_GIGA_MAC_VER_13 },\n\t\t */\n\n\t\t/* 8110 family. */\n\t\t{ 0xfc8, 0x980,\tRTL_GIGA_MAC_VER_06 },\n\t\t{ 0xfc8, 0x180,\tRTL_GIGA_MAC_VER_05 },\n\t\t{ 0xfc8, 0x100,\tRTL_GIGA_MAC_VER_04 },\n\t\t{ 0xfc8, 0x040,\tRTL_GIGA_MAC_VER_03 },\n\t\t{ 0xfc8, 0x008,\tRTL_GIGA_MAC_VER_02 },\n\n\t\t/* Catch-all */\n\t\t{ 0x000, 0x000,\tRTL_GIGA_MAC_NONE   }\n\t};\n\tconst struct rtl_mac_info *p = mac_info;\n\tenum mac_version ver;\n\n\twhile ((xid & p->mask) != p->val)\n\t\tp++;\n\tver = p->ver;\n\n\tif (ver != RTL_GIGA_MAC_NONE && !gmii) {\n\t\tif (ver == RTL_GIGA_MAC_VER_42)\n\t\t\tver = RTL_GIGA_MAC_VER_43;\n\t\telse if (ver == RTL_GIGA_MAC_VER_45)\n\t\t\tver = RTL_GIGA_MAC_VER_47;\n\t\telse if (ver == RTL_GIGA_MAC_VER_46)\n\t\t\tver = RTL_GIGA_MAC_VER_48;\n\t}\n\n\treturn ver;\n}",
        "static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_stat *req;\n\tstruct fcoe_stat_ramrod_params *fcoe_stat;\n\tunion l5cm_specific_data l5_data;": "static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_stat *req;\n\tstruct fcoe_stat_ramrod_params *fcoe_stat;\n\tunion l5cm_specific_data l5_data;\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tint ret;\n\tu32 cid;\n\n\treq = (struct fcoe_kwqe_stat *) kwqe;\n\tcid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);\n\n\tfcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);\n\tif (!fcoe_stat)\n\t\treturn -ENOMEM;\n\n\tmemset(fcoe_stat, 0, sizeof(*fcoe_stat));\n\tmemcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));\n\n\tret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,\n\t\t\t\t  FCOE_CONNECTION_TYPE, &l5_data);\n\treturn ret;\n}",
        "static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)\n{\n\tu32 mdlr, iprst1, iprst2, iprst3;\n\tstruct device *dev = &pdev->dev;\n\tstruct regmap *gcr_regmap;": "static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)\n{\n\tu32 mdlr, iprst1, iprst2, iprst3;\n\tstruct device *dev = &pdev->dev;\n\tstruct regmap *gcr_regmap;\n\tu32 ipsrst1_bits = 0;\n\tu32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;\n\tu32 ipsrst3_bits = 0;\n\tconst char *gcr_dt;\n\n\tgcr_dt = (const char *)\n\tof_match_device(dev->driver->of_match_table, dev)->data;\n\n\tgcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);\n\tif (IS_ERR(gcr_regmap)) {\n\t\tdev_err(&pdev->dev, \"Failed to find %s\\n\", gcr_dt);\n\t\treturn PTR_ERR(gcr_regmap);\n\t}\n\n\t/* checking which USB device is enabled */\n\tregmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);\n\tif (!(mdlr & NPCM_MDLR_USBD0))\n\t\tipsrst3_bits |= NPCM_IPSRST3_USBD0;\n\tif (!(mdlr & NPCM_MDLR_USBD1))\n\t\tipsrst1_bits |= NPCM_IPSRST1_USBD1;\n\tif (!(mdlr & NPCM_MDLR_USBD2_4))\n\t\tipsrst1_bits |= (NPCM_IPSRST1_USBD2 |\n\t\t\t\t NPCM_IPSRST1_USBD3 |\n\t\t\t\t NPCM_IPSRST1_USBD4);\n\tif (!(mdlr & NPCM_MDLR_USBD0)) {\n\t\tipsrst1_bits |= (NPCM_IPSRST1_USBD5 |\n\t\t\t\t NPCM_IPSRST1_USBD6);\n\t\tipsrst3_bits |= (NPCM_IPSRST3_USBD7 |\n\t\t\t\t NPCM_IPSRST3_USBD8 |\n\t\t\t\t NPCM_IPSRST3_USBD9);\n\t}\n\n\t/* assert reset USB PHY and USB devices */\n\tiprst1 = readl(rc->base + NPCM_IPSRST1);\n\tiprst2 = readl(rc->base + NPCM_IPSRST2);\n\tiprst3 = readl(rc->base + NPCM_IPSRST3);\n\n\tiprst1 |= ipsrst1_bits;\n\tiprst2 |= ipsrst2_bits;\n\tiprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |\n\t\t   NPCM_IPSRST3_USBPHY2);\n\n\twritel(iprst1, rc->base + NPCM_IPSRST1);\n\twritel(iprst2, rc->base + NPCM_IPSRST2);\n\twritel(iprst3, rc->base + NPCM_IPSRST3);\n\n\t/* clear USB PHY RS bit */\n\tregmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,\n\t\t\t   NPCM_USBXPHYCTL_RS, 0);\n\tregmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,\n\t\t\t   NPCM_USBXPHYCTL_RS, 0);\n\n\t/* deassert reset USB PHY */\n\tiprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);\n\twritel(iprst3, rc->base + NPCM_IPSRST3);\n\n\tudelay(50);\n\n\t/* set USB PHY RS bit */\n\tregmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,\n\t\t\t   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);\n\tregmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,\n\t\t\t   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);\n\n\t/* deassert reset USB devices*/\n\tiprst1 &= ~ipsrst1_bits;\n\tiprst2 &= ~ipsrst2_bits;\n\tiprst3 &= ~ipsrst3_bits;\n\n\twritel(iprst1, rc->base + NPCM_IPSRST1);\n\twritel(iprst2, rc->base + NPCM_IPSRST2);\n\twritel(iprst3, rc->base + NPCM_IPSRST3);\n\n\treturn 0;\n}",
        "static int otx2_set_matchall_egress_rate(struct otx2_nic *nic, u32 burst, u32 maxrate)\n{\n\tstruct otx2_hw *hw = &nic->hw;\n\tstruct nix_txschq_config *req;\n\tu32 burst_exp, burst_mantissa;": "static int otx2_set_matchall_egress_rate(struct otx2_nic *nic, u32 burst, u32 maxrate)\n{\n\tstruct otx2_hw *hw = &nic->hw;\n\tstruct nix_txschq_config *req;\n\tu32 burst_exp, burst_mantissa;\n\tu32 exp, mantissa, div_exp;\n\tint txschq, err;\n\n\t/* All SQs share the same TL4, so pick the first scheduler */\n\ttxschq = hw->txschq_list[NIX_TXSCH_LVL_TL4][0];\n\n\t/* Get exponent and mantissa values from the desired rate */\n\totx2_get_egress_burst_cfg(burst, &burst_exp, &burst_mantissa);\n\totx2_get_egress_rate_cfg(maxrate, &exp, &mantissa, &div_exp);\n\n\tmutex_lock(&nic->mbox.lock);\n\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(&nic->mbox);\n\tif (!req) {\n\t\tmutex_unlock(&nic->mbox.lock);\n\t\treturn -ENOMEM;\n\t}\n\n\treq->lvl = NIX_TXSCH_LVL_TL4;\n\treq->num_regs = 1;\n\treq->reg[0] = NIX_AF_TL4X_PIR(txschq);\n\treq->regval[0] = FIELD_PREP(TLX_BURST_EXPONENT, burst_exp) |\n\t\t\t FIELD_PREP(TLX_BURST_MANTISSA, burst_mantissa) |\n\t\t\t FIELD_PREP(TLX_RATE_DIVIDER_EXPONENT, div_exp) |\n\t\t\t FIELD_PREP(TLX_RATE_EXPONENT, exp) |\n\t\t\t FIELD_PREP(TLX_RATE_MANTISSA, mantissa) | BIT_ULL(0);\n\n\terr = otx2_sync_mbox_msg(&nic->mbox);\n\tmutex_unlock(&nic->mbox.lock);\n\treturn err;\n}",
        "static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx)\n{\n\tstruct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];\n\tstruct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];\n\tstruct device *dev = enet->dev;": "static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx)\n{\n\tstruct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];\n\tstruct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];\n\tstruct device *dev = enet->dev;\n\tu32 tmp;\n\tint err;\n\n\tslot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;\n\n\tslot->skb = netdev_alloc_skb(enet->netdev, slot->len);\n\tif (!slot->skb)\n\t\treturn -ENOMEM;\n\n\tslot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);\n\terr = dma_mapping_error(dev, slot->dma_addr);\n\tif (err) {\n\t\tdev_err(dev, \"Failed to map DMA buffer: %d\\n\", err);\n\t\tkfree_skb(slot->skb);\n\t\tslot->skb = NULL;\n\t\treturn err;\n\t}\n\n\ttmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n\ttmp |= DMA_CTL_STATUS_OWN;\n\tif (idx == enet->rx_ring.length - 1)\n\t\ttmp |= DMA_CTL_STATUS_WRAP;\n\tbuf_desc->ctl = cpu_to_le32(tmp);\n\tbuf_desc->addr = cpu_to_le32(slot->dma_addr);\n\n\treturn 0;\n}",
        "static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)\n{\n\tstruct mtd_info *mtd = &nor->mtd;\n\tu64 min_prot_len;\n\tint ret, status_old, status_new;": "static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)\n{\n\tstruct mtd_info *mtd = &nor->mtd;\n\tu64 min_prot_len;\n\tint ret, status_old, status_new;\n\tu8 mask = spi_nor_get_sr_bp_mask(nor);\n\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n\tu8 pow, val;\n\tloff_t lock_len;\n\tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n\tbool use_top;\n\n\tret = spi_nor_read_sr(nor, nor->bouncebuf);\n\tif (ret)\n\t\treturn ret;\n\n\tstatus_old = nor->bouncebuf[0];\n\n\t/* If nothing in our range is unlocked, we don't need to do anything */\n\tif (spi_nor_is_locked_sr(nor, ofs, len, status_old))\n\t\treturn 0;\n\n\t/* If anything below us is unlocked, we can't use 'bottom' protection */\n\tif (!spi_nor_is_locked_sr(nor, 0, ofs, status_old))\n\t\tcan_be_bottom = false;\n\n\t/* If anything above us is unlocked, we can't use 'top' protection */\n\tif (!spi_nor_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),\n\t\t\t\t  status_old))\n\t\tcan_be_top = false;\n\n\tif (!can_be_bottom && !can_be_top)\n\t\treturn -EINVAL;\n\n\t/* Prefer top, if both are valid */\n\tuse_top = can_be_top;\n\n\t/* lock_len: length of region that should end up locked */\n\tif (use_top)\n\t\tlock_len = mtd->size - ofs;\n\telse\n\t\tlock_len = ofs + len;\n\n\tif (lock_len == mtd->size) {\n\t\tval = mask;\n\t} else {\n\t\tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n\t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n\t\tval = pow << SR_BP_SHIFT;\n\n\t\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n\t\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n\n\t\tif (val & ~mask)\n\t\t\treturn -EINVAL;\n\n\t\t/* Don't \"lock\" with no region! */\n\t\tif (!(val & mask))\n\t\t\treturn -EINVAL;\n\t}\n\n\tstatus_new = (status_old & ~mask & ~tb_mask) | val;\n\n\t/* Disallow further writes if WP pin is asserted */\n\tstatus_new |= SR_SRWD;\n\n\tif (!use_top)\n\t\tstatus_new |= tb_mask;\n\n\t/* Don't bother if they're the same */\n\tif (status_new == status_old)\n\t\treturn 0;\n\n\t/* Only modify protection if it will not unlock other areas */\n\tif ((status_new & mask) < (status_old & mask))\n\t\treturn -EINVAL;\n\n\treturn spi_nor_write_sr_and_check(nor, status_new);\n}",
        "static void ca0132_init_flags(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tif (ca0132_use_alt_functions(spec)) {": "static void ca0132_init_flags(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\n\tif (ca0132_use_alt_functions(spec)) {\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);\n\t\tchipio_set_control_flag(codec,\n\t\t\t\tCONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);\n\t\tchipio_set_control_flag(codec,\n\t\t\t\tCONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);\n\t} else {\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);\n\t\tchipio_set_control_flag(codec,\n\t\t\t\tCONTROL_FLAG_PORT_A_COMMON_MODE, 0);\n\t\tchipio_set_control_flag(codec,\n\t\t\t\tCONTROL_FLAG_PORT_D_COMMON_MODE, 0);\n\t\tchipio_set_control_flag(codec,\n\t\t\t\tCONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);\n\t\tchipio_set_control_flag(codec,\n\t\t\t\tCONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);\n\t\tchipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);\n\t}\n}",
        "static int bperf_cgroup_count(void)\n{\n\tregister __u32 idx = 0;  // to have it in a register to pass BPF verifier\n\tregister int c = 0;\n\tstruct bpf_perf_event_value val, delta, *prev_val, *cgrp_val;": "static int bperf_cgroup_count(void)\n{\n\tregister __u32 idx = 0;  // to have it in a register to pass BPF verifier\n\tregister int c = 0;\n\tstruct bpf_perf_event_value val, delta, *prev_val, *cgrp_val;\n\t__u32 cpu = bpf_get_smp_processor_id();\n\t__u32 cgrp_idx[MAX_LEVELS];\n\tint cgrp_cnt;\n\t__u32 key, cgrp;\n\tlong err;\n\n\tif (use_cgroup_v2)\n\t\tcgrp_cnt = get_cgroup_v2_idx(cgrp_idx, MAX_LEVELS);\n\telse\n\t\tcgrp_cnt = get_cgroup_v1_idx(cgrp_idx, MAX_LEVELS);\n\n\tfor ( ; idx < MAX_EVENTS; idx++) {\n\t\tif (idx == num_events)\n\t\t\tbreak;\n\n\t\t// XXX: do not pass idx directly (for verifier)\n\t\tkey = idx;\n\t\t// this is per-cpu array for diff\n\t\tprev_val = bpf_map_lookup_elem(&prev_readings, &key);\n\t\tif (!prev_val) {\n\t\t\tval.counter = val.enabled = val.running = 0;\n\t\t\tbpf_map_update_elem(&prev_readings, &key, &val, BPF_ANY);\n\n\t\t\tprev_val = bpf_map_lookup_elem(&prev_readings, &key);\n\t\t\tif (!prev_val)\n\t\t\t\tcontinue;\n\t\t}\n\n\t\t// read from global perf_event array\n\t\tkey = idx * num_cpus + cpu;\n\t\terr = bpf_perf_event_read_value(&events, key, &val, sizeof(val));\n\t\tif (err)\n\t\t\tcontinue;\n\n\t\tif (enabled) {\n\t\t\tdelta.counter = val.counter - prev_val->counter;\n\t\t\tdelta.enabled = val.enabled - prev_val->enabled;\n\t\t\tdelta.running = val.running - prev_val->running;\n\n\t\t\tfor (c = 0; c < MAX_LEVELS; c++) {\n\t\t\t\tif (c == cgrp_cnt)\n\t\t\t\t\tbreak;\n\n\t\t\t\tcgrp = cgrp_idx[c];\n\n\t\t\t\t// aggregate the result by cgroup\n\t\t\t\tkey = cgrp * num_events + idx;\n\t\t\t\tcgrp_val = bpf_map_lookup_elem(&cgrp_readings, &key);\n\t\t\t\tif (cgrp_val) {\n\t\t\t\t\tcgrp_val->counter += delta.counter;\n\t\t\t\t\tcgrp_val->enabled += delta.enabled;\n\t\t\t\t\tcgrp_val->running += delta.running;\n\t\t\t\t} else {\n\t\t\t\t\tbpf_map_update_elem(&cgrp_readings, &key,\n\t\t\t\t\t\t\t    &delta, BPF_ANY);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t*prev_val = val;\n\t}\n\treturn 0;\n}",
        "static int init_display(struct fbtft_par *par)\n{\n\tpar->fbtftops.reset(par);\n\n\t/* BTL221722-276L startup sequence, from datasheet */": "static int init_display(struct fbtft_par *par)\n{\n\tpar->fbtftops.reset(par);\n\n\t/* BTL221722-276L startup sequence, from datasheet */\n\n\t/*\n\t * SETEXTCOM: Set extended command set (C1h)\n\t * This command is used to set extended command set access enable.\n\t * Enable: After command (C1h), must write: ffh,83h,40h\n\t */\n\twrite_reg(par, 0xC1, 0xFF, 0x83, 0x40);\n\n\t/*\n\t * Sleep out\n\t * This command turns off sleep mode.\n\t * In this mode the DC/DC converter is enabled, Internal oscillator\n\t * is started, and panel scanning is started.\n\t */\n\twrite_reg(par, 0x11);\n\tmdelay(150);\n\n\t/* Undoc'd register? */\n\twrite_reg(par, 0xCA, 0x70, 0x00, 0xD9);\n\n\t/*\n\t * SETOSC: Set Internal Oscillator (B0h)\n\t * This command is used to set internal oscillator related settings\n\t *\tOSC_EN: Enable internal oscillator\n\t *\tInternal oscillator frequency: 125% x 2.52MHz\n\t */\n\twrite_reg(par, 0xB0, 0x01, 0x11);\n\n\t/* Drive ability setting */\n\twrite_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06);\n\tmdelay(20);\n\n\t/*\n\t * SETPWCTR5: Set Power Control 5(B5h)\n\t * This command is used to set VCOM Low and VCOM High Voltage\n\t * VCOMH 0110101 :  3.925\n\t * VCOML 0100000 : -1.700\n\t * 45h=69  VCOMH: \"VMH\" + 5d   VCOML: \"VMH\" + 5d\n\t */\n\twrite_reg(par, 0xB5, 0x35, 0x20, 0x45);\n\n\t/*\n\t * SETPWCTR4: Set Power Control 4(B4h)\n\t *\tVRH[4:0]:\tSpecify the VREG1 voltage adjusting.\n\t *\t\t\tVREG1 voltage is for gamma voltage setting.\n\t *\tBT[2:0]:\tSwitch the output factor of step-up circuit 2\n\t *\t\t\tfor VGH and VGL voltage generation.\n\t */\n\twrite_reg(par, 0xB4, 0x33, 0x25, 0x4C);\n\tmdelay(10);\n\n\t/*\n\t * Interface Pixel Format (3Ah)\n\t * This command is used to define the format of RGB picture data,\n\t * which is to be transfer via the system and RGB interface.\n\t * RGB interface: 16 Bit/Pixel\n\t */\n\twrite_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);\n\n\t/*\n\t * Display on (29h)\n\t * This command is used to recover from DISPLAY OFF mode.\n\t * Output from the Frame Memory is enabled.\n\t */\n\twrite_reg(par, MIPI_DCS_SET_DISPLAY_ON);\n\tmdelay(10);\n\n\treturn 0;\n}",
        "static int dbAllocAny(struct bmap * bmp, s64 nblocks, int l2nb, s64 * results)\n{\n\tint rc;\n\ts64 blkno = 0;\n": "static int dbAllocAny(struct bmap * bmp, s64 nblocks, int l2nb, s64 * results)\n{\n\tint rc;\n\ts64 blkno = 0;\n\n\t/* starting with the top level dmap control page, search\n\t * down the dmap control levels for sufficient free space.\n\t * if free space is found, dbFindCtl() returns the starting\n\t * block number of the dmap that contains or starts off the\n\t * range of free space.\n\t */\n\tif ((rc = dbFindCtl(bmp, l2nb, bmp->db_maxlevel, &blkno)))\n\t\treturn (rc);\n\n\t/* allocate the blocks.\n\t */\n\trc = dbAllocCtl(bmp, nblocks, l2nb, blkno, results);\n\tif (rc == -ENOSPC) {\n\t\tjfs_error(bmp->db_ipbmap->i_sb, \"unable to allocate blocks\\n\");\n\t\treturn -EIO;\n\t}\n\treturn (rc);\n}",
        "static int __init test_g2(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 u[32] = {\n\t\t\t0xe6, 0x9d, 0x35, 0x0e, 0x48, 0x01, 0x03, 0xcc,\n\t\t\t0xdb, 0xfd, 0xf4, 0xac, 0x11, 0x91, 0xf4, 0xef,": "static int __init test_g2(struct crypto_shash *tfm_cmac)\n{\n\tconst u8 u[32] = {\n\t\t\t0xe6, 0x9d, 0x35, 0x0e, 0x48, 0x01, 0x03, 0xcc,\n\t\t\t0xdb, 0xfd, 0xf4, 0xac, 0x11, 0x91, 0xf4, 0xef,\n\t\t\t0xb9, 0xa5, 0xf9, 0xe9, 0xa7, 0x83, 0x2c, 0x5e,\n\t\t\t0x2c, 0xbe, 0x97, 0xf2, 0xd2, 0x03, 0xb0, 0x20 };\n\tconst u8 v[32] = {\n\t\t\t0xfd, 0xc5, 0x7f, 0xf4, 0x49, 0xdd, 0x4f, 0x6b,\n\t\t\t0xfb, 0x7c, 0x9d, 0xf1, 0xc2, 0x9a, 0xcb, 0x59,\n\t\t\t0x2a, 0xe7, 0xd4, 0xee, 0xfb, 0xfc, 0x0a, 0x90,\n\t\t\t0x9a, 0xbb, 0xf6, 0x32, 0x3d, 0x8b, 0x18, 0x55 };\n\tconst u8 x[16] = {\n\t\t\t0xab, 0xae, 0x2b, 0x71, 0xec, 0xb2, 0xff, 0xff,\n\t\t\t0x3e, 0x73, 0x77, 0xd1, 0x54, 0x84, 0xcb, 0xd5 };\n\tconst u8 y[16] = {\n\t\t\t0xcf, 0xc4, 0x3d, 0xff, 0xf7, 0x83, 0x65, 0x21,\n\t\t\t0x6e, 0x5f, 0xa7, 0x25, 0xcc, 0xe7, 0xe8, 0xa6 };\n\tconst u32 exp_val = 0x2f9ed5ba % 1000000;\n\tu32 val;\n\tint err;\n\n\terr = smp_g2(tfm_cmac, u, v, x, y, &val);\n\tif (err)\n\t\treturn err;\n\n\tif (val != exp_val)\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static void vivid_overlay(struct vivid_dev *dev, struct vivid_buffer *buf)\n{\n\tstruct tpg_data *tpg = &dev->tpg;\n\tunsigned pixsize = tpg_g_twopixelsize(tpg, 0) / 2;\n\tvoid *vbase = dev->fb_vbase_cap;": "static void vivid_overlay(struct vivid_dev *dev, struct vivid_buffer *buf)\n{\n\tstruct tpg_data *tpg = &dev->tpg;\n\tunsigned pixsize = tpg_g_twopixelsize(tpg, 0) / 2;\n\tvoid *vbase = dev->fb_vbase_cap;\n\tvoid *vbuf = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);\n\tunsigned img_width = dev->compose_cap.width;\n\tunsigned img_height = dev->compose_cap.height;\n\tunsigned stride = tpg->bytesperline[0];\n\t/* if quick is true, then valid_pix() doesn't have to be called */\n\tbool quick = dev->bitmap_cap == NULL && dev->clipcount_cap == 0;\n\tint x, y, w, out_x = 0;\n\n\t/*\n\t * Overlay support is only supported for formats that have a twopixelsize\n\t * that's >= 2. Warn and bail out if that's not the case.\n\t */\n\tif (WARN_ON(pixsize == 0))\n\t\treturn;\n\tif ((dev->overlay_cap_field == V4L2_FIELD_TOP ||\n\t     dev->overlay_cap_field == V4L2_FIELD_BOTTOM) &&\n\t    dev->overlay_cap_field != buf->vb.field)\n\t\treturn;\n\n\tvbuf += dev->compose_cap.left * pixsize + dev->compose_cap.top * stride;\n\tx = dev->overlay_cap_left;\n\tw = img_width;\n\tif (x < 0) {\n\t\tout_x = -x;\n\t\tw = w - out_x;\n\t\tx = 0;\n\t} else {\n\t\tw = dev->fb_cap.fmt.width - x;\n\t\tif (w > img_width)\n\t\t\tw = img_width;\n\t}\n\tif (w <= 0)\n\t\treturn;\n\tif (dev->overlay_cap_top >= 0)\n\t\tvbase += dev->overlay_cap_top * dev->fb_cap.fmt.bytesperline;\n\tfor (y = dev->overlay_cap_top;\n\t     y < dev->overlay_cap_top + (int)img_height;\n\t     y++, vbuf += stride) {\n\t\tint px;\n\n\t\tif (y < 0 || y > dev->fb_cap.fmt.height)\n\t\t\tcontinue;\n\t\tif (quick) {\n\t\t\tmemcpy(vbase + x * pixsize,\n\t\t\t       vbuf + out_x * pixsize, w * pixsize);\n\t\t\tvbase += dev->fb_cap.fmt.bytesperline;\n\t\t\tcontinue;\n\t\t}\n\t\tfor (px = 0; px < w; px++) {\n\t\t\tif (!valid_pix(dev, y - dev->overlay_cap_top,\n\t\t\t\t       px + out_x, y, px + x))\n\t\t\t\tcontinue;\n\t\t\tmemcpy(vbase + (px + x) * pixsize,\n\t\t\t       vbuf + (px + out_x) * pixsize,\n\t\t\t       pixsize);\n\t\t}\n\t\tvbase += dev->fb_cap.fmt.bytesperline;\n\t}\n}",
        "static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_conn_enable_disable *req;\n\tstruct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;\n\tunion l5cm_specific_data l5_data;": "static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct fcoe_kwqe_conn_enable_disable *req;\n\tstruct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;\n\tunion l5cm_specific_data l5_data;\n\tint ret;\n\tu32 cid, l5_cid;\n\tstruct cnic_local *cp = dev->cnic_priv;\n\n\treq = (struct fcoe_kwqe_conn_enable_disable *) kwqe;\n\tcid = req->context_id;\n\tl5_cid = req->conn_id;\n\tif (l5_cid >= dev->max_fcoe_conn)\n\t\treturn -EINVAL;\n\n\tl5_cid += BNX2X_FCOE_L5_CID_BASE;\n\n\tif (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {\n\t\tnetdev_err(dev->netdev, \"fcoe_disable size too big\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tfcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);\n\tif (!fcoe_disable)\n\t\treturn -ENOMEM;\n\n\tmemset(fcoe_disable, 0, sizeof(*fcoe_disable));\n\tmemcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));\n\tret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,\n\t\t\t\t  FCOE_CONNECTION_TYPE, &l5_data);\n\treturn ret;\n}",
        "static void fin(void)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n": "static void fin(void)\n{\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n\n\thdr_stg_map_fd = bpf_map__fd(skel->maps.hdr_stg_map);\n\tlport_linum_map_fd = bpf_map__fd(skel->maps.lport_linum_map);\n\n\texp_passive_fin_in.flags = OPTION_F_RAND;\n\texp_passive_fin_in.rand = 0xfa;\n\n\texp_active_fin_in.flags = OPTION_F_RAND;\n\texp_active_fin_in.rand = 0xce;\n\n\tprepare_out();\n\n\tif (write_sysctl(\"/proc/sys/net/ipv4/tcp_syncookies\", \"1\"))\n\t\treturn;\n\n\tlink = bpf_program__attach_cgroup(skel->progs.estab, cg_fd);\n\tif (!ASSERT_OK_PTR(link, \"attach_cgroup(estab)\"))\n\t\treturn;\n\n\tif (sk_fds_connect(&sk_fds, false)) {\n\t\tbpf_link__destroy(link);\n\t\treturn;\n\t}\n\n\tcheck_hdr_and_close_fds(&sk_fds);\n\tbpf_link__destroy(link);\n}",
        "static int unmark_stack_slots_dynptr(struct bpf_verifier_env *env, struct bpf_reg_state *reg)\n{\n\tstruct bpf_func_state *state = func(env, reg);\n\tint spi, i;\n": "static int unmark_stack_slots_dynptr(struct bpf_verifier_env *env, struct bpf_reg_state *reg)\n{\n\tstruct bpf_func_state *state = func(env, reg);\n\tint spi, i;\n\n\tspi = get_spi(reg->off);\n\n\tif (!is_spi_bounds_valid(state, spi, BPF_DYNPTR_NR_SLOTS))\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < BPF_REG_SIZE; i++) {\n\t\tstate->stack[spi].slot_type[i] = STACK_INVALID;\n\t\tstate->stack[spi - 1].slot_type[i] = STACK_INVALID;\n\t}\n\n\t/* Invalidate any slices associated with this dynptr */\n\tif (dynptr_type_refcounted(state->stack[spi].spilled_ptr.dynptr.type)) {\n\t\trelease_reference(env, state->stack[spi].spilled_ptr.id);\n\t\tstate->stack[spi].spilled_ptr.id = 0;\n\t\tstate->stack[spi - 1].spilled_ptr.id = 0;\n\t}\n\n\tstate->stack[spi].spilled_ptr.dynptr.first_slot = false;\n\tstate->stack[spi].spilled_ptr.dynptr.type = 0;\n\tstate->stack[spi - 1].spilled_ptr.dynptr.type = 0;\n\n\treturn 0;\n}",
        "static void dbSplit(dmtree_t * tp, int leafno, int splitsz, int newval)\n{\n\tint budsz;\n\tint cursz;\n\ts8 *leaf = tp->dmt_stree + le32_to_cpu(tp->dmt_leafidx);": "static void dbSplit(dmtree_t * tp, int leafno, int splitsz, int newval)\n{\n\tint budsz;\n\tint cursz;\n\ts8 *leaf = tp->dmt_stree + le32_to_cpu(tp->dmt_leafidx);\n\n\t/* check if the leaf needs to be split.\n\t */\n\tif (leaf[leafno] > tp->dmt_budmin) {\n\t\t/* the split occurs by cutting the buddy system in half\n\t\t * at the specified leaf until we reach the specified\n\t\t * size.  pick up the starting split size (current size\n\t\t * - 1 in l2) and the corresponding buddy size.\n\t\t */\n\t\tcursz = leaf[leafno] - 1;\n\t\tbudsz = BUDSIZE(cursz, tp->dmt_budmin);\n\n\t\t/* split until we reach the specified size.\n\t\t */\n\t\twhile (cursz >= splitsz) {\n\t\t\t/* update the buddy's leaf with its new value.\n\t\t\t */\n\t\t\tdbAdjTree(tp, leafno ^ budsz, cursz);\n\n\t\t\t/* on to the next size and buddy.\n\t\t\t */\n\t\t\tcursz -= 1;\n\t\t\tbudsz >>= 1;\n\t\t}\n\t}\n\n\t/* adjust the dmap tree to reflect the specified leaf's new\n\t * value.\n\t */\n\tdbAdjTree(tp, leafno, newval);\n}",
        "static int hvsi_handshake(struct hvsi_struct *hp)\n{\n\tint ret;\n\n\t/*": "static int hvsi_handshake(struct hvsi_struct *hp)\n{\n\tint ret;\n\n\t/*\n\t * We could have a CLOSE or other data waiting for us before we even try\n\t * to open; try to throw it all away so we don't get confused. (CLOSE\n\t * is the first message sent up the pipe when the FSP comes online. We\n\t * need to distinguish between \"it came up a while ago and we're the first\n\t * user\" and \"it was just reset before it saw our handshake packet\".)\n\t */\n\thvsi_drain_input(hp);\n\n\tset_state(hp, HVSI_WAIT_FOR_VER_RESPONSE);\n\tret = hvsi_query(hp, VSV_SEND_VERSION_NUMBER);\n\tif (ret < 0) {\n\t\tprintk(KERN_ERR \"hvsi%i: couldn't send version query\\n\", hp->index);\n\t\treturn ret;\n\t}\n\n\tret = hvsi_wait(hp, HVSI_OPEN);\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn 0;\n}",
        "static void test_syscalls_common(int msb)\n{\n\tenum ptrace_pass pass = sh->ptrace_pass;\n\n\trun(\"Checking some common syscalls as 64 bit\\n\");": "static void test_syscalls_common(int msb)\n{\n\tenum ptrace_pass pass = sh->ptrace_pass;\n\n\trun(\"Checking some common syscalls as 64 bit\\n\");\n\tcheck_zero(msb, SYS_READ);\n\tcheck_zero(msb, SYS_WRITE);\n\n\trun(\"Checking some 64-bit only syscalls as 64 bit\\n\");\n\tcheck_zero(msb, X64_READV);\n\tcheck_zero(msb, X64_WRITEV);\n\n\trun(\"Checking out of range system calls\\n\");\n\tcheck_for(msb, -64, -2, -ENOSYS);\n\tif (pass >= PTP_FUZZRET)\n\t\tcheck_for(msb, -1, -1, MODIFIED_BY_PTRACE);\n\telse\n\t\tcheck_for(msb, -1, -1, -ENOSYS);\n\tcheck_for(msb, X32_BIT-64, X32_BIT-1, -ENOSYS);\n\tcheck_for(msb, -64-X32_BIT, -1-X32_BIT, -ENOSYS);\n\tcheck_for(msb, INT_MAX-64, INT_MAX-1, -ENOSYS);\n}",
        "static int vt_bind(struct con_driver *con)\n{\n\tconst struct consw *defcsw = NULL, *csw = NULL;\n\tint i, more = 1, first = -1, last = -1, deflt = 0;\n": "static int vt_bind(struct con_driver *con)\n{\n\tconst struct consw *defcsw = NULL, *csw = NULL;\n\tint i, more = 1, first = -1, last = -1, deflt = 0;\n\n \tif (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE))\n\t\tgoto err;\n\n\tcsw = con->con;\n\n\tfor (i = 0; i < MAX_NR_CON_DRIVER; i++) {\n\t\tstruct con_driver *con = &registered_con_driver[i];\n\n\t\tif (con->con && !(con->flag & CON_DRIVER_FLAG_MODULE)) {\n\t\t\tdefcsw = con->con;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!defcsw)\n\t\tgoto err;\n\n\twhile (more) {\n\t\tmore = 0;\n\n\t\tfor (i = con->first; i <= con->last; i++) {\n\t\t\tif (con_driver_map[i] == defcsw) {\n\t\t\t\tif (first == -1)\n\t\t\t\t\tfirst = i;\n\t\t\t\tlast = i;\n\t\t\t\tmore = 1;\n\t\t\t} else if (first != -1)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (first == 0 && last == MAX_NR_CONSOLES -1)\n\t\t\tdeflt = 1;\n\n\t\tif (first != -1)\n\t\t\tdo_bind_con_driver(csw, first, last, deflt);\n\n\t\tfirst = -1;\n\t\tlast = -1;\n\t\tdeflt = 0;\n\t}\n\nerr:\n\treturn 0;\n}",
        "static unsigned int fsm_find(struct ts_config *conf, struct ts_state *state)\n{\n\tstruct ts_fsm *fsm = ts_config_priv(conf);\n\tstruct ts_fsm_token *cur = NULL, *next;\n\tunsigned int match_start, block_idx = 0, tok_idx;": "static unsigned int fsm_find(struct ts_config *conf, struct ts_state *state)\n{\n\tstruct ts_fsm *fsm = ts_config_priv(conf);\n\tstruct ts_fsm_token *cur = NULL, *next;\n\tunsigned int match_start, block_idx = 0, tok_idx;\n\tunsigned block_len = 0, strict, consumed = state->offset;\n\tconst u8 *data;\n\n#define GET_NEXT_BLOCK()\t\t\\\n({\tconsumed += block_idx;\t\t\\\n\tblock_idx = 0;\t\t\t\\\n\tblock_len = conf->get_next_block(consumed, &data, conf, state); })\n\n#define TOKEN_MISMATCH()\t\t\\\n\tdo {\t\t\t\t\\\n\t\tif (strict)\t\t\\\n\t\t\tgoto no_match;\t\\\n\t\tblock_idx++;\t\t\\\n\t\tgoto startover;\t\t\\\n\t} while(0)\n\n#define end_of_data() unlikely(block_idx >= block_len && !GET_NEXT_BLOCK())\n\n\tif (end_of_data())\n\t\tgoto no_match;\n\n\tstrict = fsm->tokens[0].recur != TS_FSM_HEAD_IGNORE;\n\nstartover:\n\tmatch_start = consumed + block_idx;\n\n\tfor (tok_idx = 0; tok_idx < fsm->ntokens; tok_idx++) {\n\t\tcur = &fsm->tokens[tok_idx];\n\n\t\tif (likely(tok_idx < (fsm->ntokens - 1)))\n\t\t\tnext = &fsm->tokens[tok_idx + 1];\n\t\telse\n\t\t\tnext = NULL;\n\n\t\tswitch (cur->recur) {\n\t\tcase TS_FSM_SINGLE:\n\t\t\tif (end_of_data())\n\t\t\t\tgoto no_match;\n\n\t\t\tif (!match_token(cur, data[block_idx]))\n\t\t\t\tTOKEN_MISMATCH();\n\t\t\tbreak;\n\n\t\tcase TS_FSM_PERHAPS:\n\t\t\tif (end_of_data() ||\n\t\t\t    !match_token(cur, data[block_idx]))\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\n\t\tcase TS_FSM_MULTI:\n\t\t\tif (end_of_data())\n\t\t\t\tgoto no_match;\n\n\t\t\tif (!match_token(cur, data[block_idx]))\n\t\t\t\tTOKEN_MISMATCH();\n\n\t\t\tblock_idx++;\n\t\t\tfallthrough;\n\n\t\tcase TS_FSM_ANY:\n\t\t\tif (next == NULL)\n\t\t\t\tgoto found_match;\n\n\t\t\tif (end_of_data())\n\t\t\t\tcontinue;\n\n\t\t\twhile (!match_token(next, data[block_idx])) {\n\t\t\t\tif (!match_token(cur, data[block_idx]))\n\t\t\t\t\tTOKEN_MISMATCH();\n\t\t\t\tblock_idx++;\n\t\t\t\tif (end_of_data())\n\t\t\t\t\tgoto no_match;\n\t\t\t}\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * Optimization: Prefer small local loop over jumping\n\t\t * back and forth until garbage at head is munched.\n\t\t */\n\t\tcase TS_FSM_HEAD_IGNORE:\n\t\t\tif (end_of_data())\n\t\t\t\tcontinue;\n\n\t\t\twhile (!match_token(next, data[block_idx])) {\n\t\t\t\t/*\n\t\t\t\t * Special case, don't start over upon\n\t\t\t\t * a mismatch, give the user the\n\t\t\t\t * chance to specify the type of data\n\t\t\t\t * allowed to be ignored.\n\t\t\t\t */\n\t\t\t\tif (!match_token(cur, data[block_idx]))\n\t\t\t\t\tgoto no_match;\n\n\t\t\t\tblock_idx++;\n\t\t\t\tif (end_of_data())\n\t\t\t\t\tgoto no_match;\n\t\t\t}\n\n\t\t\tmatch_start = consumed + block_idx;\n\t\t\tcontinue;\n\t\t}\n\n\t\tblock_idx++;\n\t}\n\n\tif (end_of_data())\n\t\tgoto found_match;\n\nno_match:\n\treturn UINT_MAX;\n\nfound_match:\n\tstate->offset = consumed + block_idx;\n\treturn match_start;\n}",
        "static int isl7998x_init(struct isl7998x *isl7998x)\n{\n\tconst unsigned int lanes = isl7998x->nr_mipi_lanes;\n\tconst u32 isl7998x_video_in_chan_map[] = { 0x00, 0x11, 0x02, 0x02 };\n\tconst struct reg_sequence isl7998x_init_seq_custom[] = {": "static int isl7998x_init(struct isl7998x *isl7998x)\n{\n\tconst unsigned int lanes = isl7998x->nr_mipi_lanes;\n\tconst u32 isl7998x_video_in_chan_map[] = { 0x00, 0x11, 0x02, 0x02 };\n\tconst struct reg_sequence isl7998x_init_seq_custom[] = {\n\t\t{ ISL7998X_REG_P0_VIDEO_IN_CHAN_CTL,\n\t\t  isl7998x_video_in_chan_map[isl7998x->nr_inputs - 1] },\n\t\t{ ISL7998X_REG_P0_CLK_CTL_4,\n\t\t  (lanes == 1) ? 0x40 : 0x41 },\n\t\t{ ISL7998X_REG_P5_LI_ENGINE_CTL,\n\t\t  (lanes == 1) ? 0x01 : 0x02 },\n\t};\n\tstruct device *dev = isl7998x->subdev.dev;\n\tstruct regmap *regmap = isl7998x->regmap;\n\tint ret;\n\n\tdev_dbg(dev, \"configuring %d lanes for %d inputs (norm %s)\\n\",\n\t\tisl7998x->nr_mipi_lanes, isl7998x->nr_inputs,\n\t\tv4l2_norm_to_name(isl7998x->norm));\n\n\tret = regmap_register_patch(regmap, isl7998x_init_seq_1,\n\t\t\t\t    ARRAY_SIZE(isl7998x_init_seq_1));\n\tif (ret)\n\t\treturn ret;\n\n\tmutex_lock(&isl7998x->lock);\n\tret = isl7998x_set_standard(isl7998x, isl7998x->norm);\n\tmutex_unlock(&isl7998x->lock);\n\tif (ret)\n\t\treturn ret;\n\n\tret = regmap_register_patch(regmap, isl7998x_init_seq_custom,\n\t\t\t\t    ARRAY_SIZE(isl7998x_init_seq_custom));\n\tif (ret)\n\t\treturn ret;\n\n\treturn regmap_register_patch(regmap, isl7998x_init_seq_2,\n\t\t\t\t     ARRAY_SIZE(isl7998x_init_seq_2));\n}",
        "static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se)\n{\n\t/*\n\t * cfs_rq->avg.period_contrib can be used for both cfs_rq and se.\n\t * See ___update_load_avg() for details.": "static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se)\n{\n\t/*\n\t * cfs_rq->avg.period_contrib can be used for both cfs_rq and se.\n\t * See ___update_load_avg() for details.\n\t */\n\tu32 divider = get_pelt_divider(&cfs_rq->avg);\n\n\t/*\n\t * When we attach the @se to the @cfs_rq, we must align the decay\n\t * window because without that, really weird and wonderful things can\n\t * happen.\n\t *\n\t * XXX illustrate\n\t */\n\tse->avg.last_update_time = cfs_rq->avg.last_update_time;\n\tse->avg.period_contrib = cfs_rq->avg.period_contrib;\n\n\t/*\n\t * Hell(o) Nasty stuff.. we need to recompute _sum based on the new\n\t * period_contrib. This isn't strictly correct, but since we're\n\t * entirely outside of the PELT hierarchy, nobody cares if we truncate\n\t * _sum a little.\n\t */\n\tse->avg.util_sum = se->avg.util_avg * divider;\n\n\tse->avg.runnable_sum = se->avg.runnable_avg * divider;\n\n\tse->avg.load_sum = se->avg.load_avg * divider;\n\tif (se_weight(se) < se->avg.load_sum)\n\t\tse->avg.load_sum = div_u64(se->avg.load_sum, se_weight(se));\n\telse\n\t\tse->avg.load_sum = 1;\n\n\tenqueue_load_avg(cfs_rq, se);\n\tcfs_rq->avg.util_avg += se->avg.util_avg;\n\tcfs_rq->avg.util_sum += se->avg.util_sum;\n\tcfs_rq->avg.runnable_avg += se->avg.runnable_avg;\n\tcfs_rq->avg.runnable_sum += se->avg.runnable_sum;\n\n\tadd_tg_cfs_propagate(cfs_rq, se->avg.load_sum);\n\n\tcfs_rq_util_change(cfs_rq, 0);\n\n\ttrace_pelt_cfs_tp(cfs_rq);\n}",
        "static int __init kbdlight_init(struct ibm_init_struct *iibm)\n{\n\tint rc;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing kbdlight subdriver\\n\");": "static int __init kbdlight_init(struct ibm_init_struct *iibm)\n{\n\tint rc;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing kbdlight subdriver\\n\");\n\n\tTPACPI_ACPIHANDLE_INIT(hkey);\n\n\tif (!kbdlight_is_supported()) {\n\t\ttp_features.kbdlight = 0;\n\t\tvdbg_printk(TPACPI_DBG_INIT, \"kbdlight is unsupported\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tkbdlight_brightness = kbdlight_sysfs_get(NULL);\n\ttp_features.kbdlight = 1;\n\n\trc = led_classdev_register(&tpacpi_pdev->dev,\n\t\t\t\t   &tpacpi_led_kbdlight.led_classdev);\n\tif (rc < 0) {\n\t\ttp_features.kbdlight = 0;\n\t\treturn rc;\n\t}\n\n\ttpacpi_hotkey_driver_mask_set(hotkey_driver_mask |\n\t\t\t\t      TP_ACPI_HKEY_KBD_LIGHT_MASK);\n\treturn 0;\n}",
        "static int kdamond_wait_activation(struct damon_ctx *ctx)\n{\n\tstruct damos *s;\n\tunsigned long wait_time;\n\tunsigned long min_wait_time = 0;": "static int kdamond_wait_activation(struct damon_ctx *ctx)\n{\n\tstruct damos *s;\n\tunsigned long wait_time;\n\tunsigned long min_wait_time = 0;\n\tbool init_wait_time = false;\n\n\twhile (!kdamond_need_stop(ctx)) {\n\t\tdamon_for_each_scheme(s, ctx) {\n\t\t\twait_time = damos_wmark_wait_us(s);\n\t\t\tif (!init_wait_time || wait_time < min_wait_time) {\n\t\t\t\tinit_wait_time = true;\n\t\t\t\tmin_wait_time = wait_time;\n\t\t\t}\n\t\t}\n\t\tif (!min_wait_time)\n\t\t\treturn 0;\n\n\t\tkdamond_usleep(min_wait_time);\n\n\t\tif (ctx->callback.after_wmarks_check &&\n\t\t\t\tctx->callback.after_wmarks_check(ctx))\n\t\t\tbreak;\n\t}\n\treturn -EBUSY;\n}",
        "static int aq_set_txsc(struct aq_nic_s *nic, const int txsc_idx)\n{\n\tstruct aq_macsec_txsc *aq_txsc = &nic->macsec_cfg->aq_txsc[txsc_idx];\n\tstruct aq_mss_egress_class_record tx_class_rec = { 0 };\n\tconst struct macsec_secy *secy = aq_txsc->sw_secy;": "static int aq_set_txsc(struct aq_nic_s *nic, const int txsc_idx)\n{\n\tstruct aq_macsec_txsc *aq_txsc = &nic->macsec_cfg->aq_txsc[txsc_idx];\n\tstruct aq_mss_egress_class_record tx_class_rec = { 0 };\n\tconst struct macsec_secy *secy = aq_txsc->sw_secy;\n\tstruct aq_mss_egress_sc_record sc_rec = { 0 };\n\tunsigned int sc_idx = aq_txsc->hw_sc_idx;\n\tstruct aq_hw_s *hw = nic->aq_hw;\n\tint ret = 0;\n\n\taq_ether_addr_to_mac(tx_class_rec.mac_sa, secy->netdev->dev_addr);\n\n\tput_unaligned_be64((__force u64)secy->sci, tx_class_rec.sci);\n\ttx_class_rec.sci_mask = 0;\n\n\ttx_class_rec.sa_mask = 0x3f;\n\n\ttx_class_rec.action = 0; /* forward to SA/SC table */\n\ttx_class_rec.valid = 1;\n\n\ttx_class_rec.sc_idx = sc_idx;\n\n\ttx_class_rec.sc_sa = nic->macsec_cfg->sc_sa;\n\n\tret = aq_mss_set_egress_class_record(hw, &tx_class_rec, txsc_idx);\n\tif (ret)\n\t\treturn ret;\n\n\tsc_rec.protect = secy->protect_frames;\n\tif (secy->tx_sc.encrypt)\n\t\tsc_rec.tci |= BIT(1);\n\tif (secy->tx_sc.scb)\n\t\tsc_rec.tci |= BIT(2);\n\tif (secy->tx_sc.send_sci)\n\t\tsc_rec.tci |= BIT(3);\n\tif (secy->tx_sc.end_station)\n\t\tsc_rec.tci |= BIT(4);\n\t/* The C bit is clear if and only if the Secure Data is\n\t * exactly the same as the User Data and the ICV is 16 octets long.\n\t */\n\tif (!(secy->icv_len == 16 && !secy->tx_sc.encrypt))\n\t\tsc_rec.tci |= BIT(0);\n\n\tsc_rec.an_roll = 0;\n\n\tswitch (secy->key_len) {\n\tcase AQ_MACSEC_KEY_LEN_128_BIT:\n\t\tsc_rec.sak_len = 0;\n\t\tbreak;\n\tcase AQ_MACSEC_KEY_LEN_192_BIT:\n\t\tsc_rec.sak_len = 1;\n\t\tbreak;\n\tcase AQ_MACSEC_KEY_LEN_256_BIT:\n\t\tsc_rec.sak_len = 2;\n\t\tbreak;\n\tdefault:\n\t\tWARN_ONCE(true, \"Invalid sc_sa\");\n\t\treturn -EINVAL;\n\t}\n\n\tsc_rec.curr_an = secy->tx_sc.encoding_sa;\n\tsc_rec.valid = 1;\n\tsc_rec.fresh = 1;\n\n\treturn aq_mss_set_egress_sc_record(hw, &sc_rec, sc_idx);\n}",
        "static int last_log_lsn(struct ntfs_log *log)\n{\n\tint err;\n\tbool usa_error = false;\n\tbool replace_page = false;": "static int last_log_lsn(struct ntfs_log *log)\n{\n\tint err;\n\tbool usa_error = false;\n\tbool replace_page = false;\n\tbool reuse_page = log->l_flags & NTFSLOG_REUSE_TAIL;\n\tbool wrapped_file, wrapped;\n\n\tu32 page_cnt = 1, page_pos = 1;\n\tu32 page_off = 0, page_off1 = 0, saved_off = 0;\n\tu32 final_off, second_off, final_off_prev = 0, second_off_prev = 0;\n\tu32 first_file_off = 0, second_file_off = 0;\n\tu32 part_io_count = 0;\n\tu32 tails = 0;\n\tu32 this_off, curpage_off, nextpage_off, remain_pages;\n\n\tu64 expected_seq, seq_base = 0, lsn_base = 0;\n\tu64 best_lsn, best_lsn1, best_lsn2;\n\tu64 lsn_cur, lsn1, lsn2;\n\tu64 last_ok_lsn = reuse_page ? log->last_lsn : 0;\n\n\tu16 cur_pos, best_page_pos;\n\n\tstruct RECORD_PAGE_HDR *page = NULL;\n\tstruct RECORD_PAGE_HDR *tst_page = NULL;\n\tstruct RECORD_PAGE_HDR *first_tail = NULL;\n\tstruct RECORD_PAGE_HDR *second_tail = NULL;\n\tstruct RECORD_PAGE_HDR *tail_page = NULL;\n\tstruct RECORD_PAGE_HDR *second_tail_prev = NULL;\n\tstruct RECORD_PAGE_HDR *first_tail_prev = NULL;\n\tstruct RECORD_PAGE_HDR *page_bufs = NULL;\n\tstruct RECORD_PAGE_HDR *best_page;\n\n\tif (log->major_ver >= 2) {\n\t\tfinal_off = 0x02 * log->page_size;\n\t\tsecond_off = 0x12 * log->page_size;\n\n\t\t// 0x10 == 0x12 - 0x2\n\t\tpage_bufs = kmalloc(log->page_size * 0x10, GFP_NOFS);\n\t\tif (!page_bufs)\n\t\t\treturn -ENOMEM;\n\t} else {\n\t\tsecond_off = log->first_page - log->page_size;\n\t\tfinal_off = second_off - log->page_size;\n\t}\n\nnext_tail:\n\t/* Read second tail page (at pos 3/0x12000). */\n\tif (read_log_page(log, second_off, &second_tail, &usa_error) ||\n\t    usa_error || second_tail->rhdr.sign != NTFS_RCRD_SIGNATURE) {\n\t\tkfree(second_tail);\n\t\tsecond_tail = NULL;\n\t\tsecond_file_off = 0;\n\t\tlsn2 = 0;\n\t} else {\n\t\tsecond_file_off = hdr_file_off(log, second_tail);\n\t\tlsn2 = le64_to_cpu(second_tail->record_hdr.last_end_lsn);\n\t}\n\n\t/* Read first tail page (at pos 2/0x2000). */\n\tif (read_log_page(log, final_off, &first_tail, &usa_error) ||\n\t    usa_error || first_tail->rhdr.sign != NTFS_RCRD_SIGNATURE) {\n\t\tkfree(first_tail);\n\t\tfirst_tail = NULL;\n\t\tfirst_file_off = 0;\n\t\tlsn1 = 0;\n\t} else {\n\t\tfirst_file_off = hdr_file_off(log, first_tail);\n\t\tlsn1 = le64_to_cpu(first_tail->record_hdr.last_end_lsn);\n\t}\n\n\tif (log->major_ver < 2) {\n\t\tint best_page;\n\n\t\tfirst_tail_prev = first_tail;\n\t\tfinal_off_prev = first_file_off;\n\t\tsecond_tail_prev = second_tail;\n\t\tsecond_off_prev = second_file_off;\n\t\ttails = 1;\n\n\t\tif (!first_tail && !second_tail)\n\t\t\tgoto tail_read;\n\n\t\tif (first_tail && second_tail)\n\t\t\tbest_page = lsn1 < lsn2 ? 1 : 0;\n\t\telse if (first_tail)\n\t\t\tbest_page = 0;\n\t\telse\n\t\t\tbest_page = 1;\n\n\t\tpage_off = best_page ? second_file_off : first_file_off;\n\t\tseq_base = (best_page ? lsn2 : lsn1) >> log->file_data_bits;\n\t\tgoto tail_read;\n\t}\n\n\tbest_lsn1 = first_tail ? base_lsn(log, first_tail, first_file_off) : 0;\n\tbest_lsn2 =\n\t\tsecond_tail ? base_lsn(log, second_tail, second_file_off) : 0;\n\n\tif (first_tail && second_tail) {\n\t\tif (best_lsn1 > best_lsn2) {\n\t\t\tbest_lsn = best_lsn1;\n\t\t\tbest_page = first_tail;\n\t\t\tthis_off = first_file_off;\n\t\t} else {\n\t\t\tbest_lsn = best_lsn2;\n\t\t\tbest_page = second_tail;\n\t\t\tthis_off = second_file_off;\n\t\t}\n\t} else if (first_tail) {\n\t\tbest_lsn = best_lsn1;\n\t\tbest_page = first_tail;\n\t\tthis_off = first_file_off;\n\t} else if (second_tail) {\n\t\tbest_lsn = best_lsn2;\n\t\tbest_page = second_tail;\n\t\tthis_off = second_file_off;\n\t} else {\n\t\tgoto tail_read;\n\t}\n\n\tbest_page_pos = le16_to_cpu(best_page->page_pos);\n\n\tif (!tails) {\n\t\tif (best_page_pos == page_pos) {\n\t\t\tseq_base = best_lsn >> log->file_data_bits;\n\t\t\tsaved_off = page_off = le32_to_cpu(best_page->file_off);\n\t\t\tlsn_base = best_lsn;\n\n\t\t\tmemmove(page_bufs, best_page, log->page_size);\n\n\t\t\tpage_cnt = le16_to_cpu(best_page->page_count);\n\t\t\tif (page_cnt > 1)\n\t\t\t\tpage_pos += 1;\n\n\t\t\ttails = 1;\n\t\t}\n\t} else if (seq_base == (best_lsn >> log->file_data_bits) &&\n\t\t   saved_off + log->page_size == this_off &&\n\t\t   lsn_base < best_lsn &&\n\t\t   (page_pos != page_cnt || best_page_pos == page_pos ||\n\t\t    best_page_pos == 1) &&\n\t\t   (page_pos >= page_cnt || best_page_pos == page_pos)) {\n\t\tu16 bppc = le16_to_cpu(best_page->page_count);\n\n\t\tsaved_off += log->page_size;\n\t\tlsn_base = best_lsn;\n\n\t\tmemmove(Add2Ptr(page_bufs, tails * log->page_size), best_page,\n\t\t\tlog->page_size);\n\n\t\ttails += 1;\n\n\t\tif (best_page_pos != bppc) {\n\t\t\tpage_cnt = bppc;\n\t\t\tpage_pos = best_page_pos;\n\n\t\t\tif (page_cnt > 1)\n\t\t\t\tpage_pos += 1;\n\t\t} else {\n\t\t\tpage_pos = page_cnt = 1;\n\t\t}\n\t} else {\n\t\tkfree(first_tail);\n\t\tkfree(second_tail);\n\t\tgoto tail_read;\n\t}\n\n\tkfree(first_tail_prev);\n\tfirst_tail_prev = first_tail;\n\tfinal_off_prev = first_file_off;\n\tfirst_tail = NULL;\n\n\tkfree(second_tail_prev);\n\tsecond_tail_prev = second_tail;\n\tsecond_off_prev = second_file_off;\n\tsecond_tail = NULL;\n\n\tfinal_off += log->page_size;\n\tsecond_off += log->page_size;\n\n\tif (tails < 0x10)\n\t\tgoto next_tail;\ntail_read:\n\tfirst_tail = first_tail_prev;\n\tfinal_off = final_off_prev;\n\n\tsecond_tail = second_tail_prev;\n\tsecond_off = second_off_prev;\n\n\tpage_cnt = page_pos = 1;\n\n\tcurpage_off = seq_base == log->seq_num ? min(log->next_page, page_off)\n\t\t\t\t\t       : log->next_page;\n\n\twrapped_file =\n\t\tcurpage_off == log->first_page &&\n\t\t!(log->l_flags & (NTFSLOG_NO_LAST_LSN | NTFSLOG_REUSE_TAIL));\n\n\texpected_seq = wrapped_file ? (log->seq_num + 1) : log->seq_num;\n\n\tnextpage_off = curpage_off;\n\nnext_page:\n\ttail_page = NULL;\n\t/* Read the next log page. */\n\terr = read_log_page(log, curpage_off, &page, &usa_error);\n\n\t/* Compute the next log page offset the file. */\n\tnextpage_off = next_page_off(log, curpage_off);\n\twrapped = nextpage_off == log->first_page;\n\n\tif (tails > 1) {\n\t\tstruct RECORD_PAGE_HDR *cur_page =\n\t\t\tAdd2Ptr(page_bufs, curpage_off - page_off);\n\n\t\tif (curpage_off == saved_off) {\n\t\t\ttail_page = cur_page;\n\t\t\tgoto use_tail_page;\n\t\t}\n\n\t\tif (page_off > curpage_off || curpage_off >= saved_off)\n\t\t\tgoto use_tail_page;\n\n\t\tif (page_off1)\n\t\t\tgoto use_cur_page;\n\n\t\tif (!err && !usa_error &&\n\t\t    page->rhdr.sign == NTFS_RCRD_SIGNATURE &&\n\t\t    cur_page->rhdr.lsn == page->rhdr.lsn &&\n\t\t    cur_page->record_hdr.next_record_off ==\n\t\t\t    page->record_hdr.next_record_off &&\n\t\t    ((page_pos == page_cnt &&\n\t\t      le16_to_cpu(page->page_pos) == 1) ||\n\t\t     (page_pos != page_cnt &&\n\t\t      le16_to_cpu(page->page_pos) == page_pos + 1 &&\n\t\t      le16_to_cpu(page->page_count) == page_cnt))) {\n\t\t\tcur_page = NULL;\n\t\t\tgoto use_tail_page;\n\t\t}\n\n\t\tpage_off1 = page_off;\n\nuse_cur_page:\n\n\t\tlsn_cur = le64_to_cpu(cur_page->rhdr.lsn);\n\n\t\tif (last_ok_lsn !=\n\t\t\t    le64_to_cpu(cur_page->record_hdr.last_end_lsn) &&\n\t\t    ((lsn_cur >> log->file_data_bits) +\n\t\t     ((curpage_off <\n\t\t       (lsn_to_vbo(log, lsn_cur) & ~log->page_mask))\n\t\t\t      ? 1\n\t\t\t      : 0)) != expected_seq) {\n\t\t\tgoto check_tail;\n\t\t}\n\n\t\tif (!is_log_record_end(cur_page)) {\n\t\t\ttail_page = NULL;\n\t\t\tlast_ok_lsn = lsn_cur;\n\t\t\tgoto next_page_1;\n\t\t}\n\n\t\tlog->seq_num = expected_seq;\n\t\tlog->l_flags &= ~NTFSLOG_NO_LAST_LSN;\n\t\tlog->last_lsn = le64_to_cpu(cur_page->record_hdr.last_end_lsn);\n\t\tlog->ra->current_lsn = cur_page->record_hdr.last_end_lsn;\n\n\t\tif (log->record_header_len <=\n\t\t    log->page_size -\n\t\t\t    le16_to_cpu(cur_page->record_hdr.next_record_off)) {\n\t\t\tlog->l_flags |= NTFSLOG_REUSE_TAIL;\n\t\t\tlog->next_page = curpage_off;\n\t\t} else {\n\t\t\tlog->l_flags &= ~NTFSLOG_REUSE_TAIL;\n\t\t\tlog->next_page = nextpage_off;\n\t\t}\n\n\t\tif (wrapped_file)\n\t\t\tlog->l_flags |= NTFSLOG_WRAPPED;\n\n\t\tlast_ok_lsn = le64_to_cpu(cur_page->record_hdr.last_end_lsn);\n\t\tgoto next_page_1;\n\t}\n\n\t/*\n\t * If we are at the expected first page of a transfer check to see\n\t * if either tail copy is at this offset.\n\t * If this page is the last page of a transfer, check if we wrote\n\t * a subsequent tail copy.\n\t */\n\tif (page_cnt == page_pos || page_cnt == page_pos + 1) {\n\t\t/*\n\t\t * Check if the offset matches either the first or second\n\t\t * tail copy. It is possible it will match both.\n\t\t */\n\t\tif (curpage_off == final_off)\n\t\t\ttail_page = first_tail;\n\n\t\t/*\n\t\t * If we already matched on the first page then\n\t\t * check the ending lsn's.\n\t\t */\n\t\tif (curpage_off == second_off) {\n\t\t\tif (!tail_page ||\n\t\t\t    (second_tail &&\n\t\t\t     le64_to_cpu(second_tail->record_hdr.last_end_lsn) >\n\t\t\t\t     le64_to_cpu(first_tail->record_hdr\n\t\t\t\t\t\t\t .last_end_lsn))) {\n\t\t\t\ttail_page = second_tail;\n\t\t\t}\n\t\t}\n\t}\n\nuse_tail_page:\n\tif (tail_page) {\n\t\t/* We have a candidate for a tail copy. */\n\t\tlsn_cur = le64_to_cpu(tail_page->record_hdr.last_end_lsn);\n\n\t\tif (last_ok_lsn < lsn_cur) {\n\t\t\t/*\n\t\t\t * If the sequence number is not expected,\n\t\t\t * then don't use the tail copy.\n\t\t\t */\n\t\t\tif (expected_seq != (lsn_cur >> log->file_data_bits))\n\t\t\t\ttail_page = NULL;\n\t\t} else if (last_ok_lsn > lsn_cur) {\n\t\t\t/*\n\t\t\t * If the last lsn is greater than the one on\n\t\t\t * this page then forget this tail.\n\t\t\t */\n\t\t\ttail_page = NULL;\n\t\t}\n\t}\n\n\t/*\n\t *If we have an error on the current page,\n\t * we will break of this loop.\n\t */\n\tif (err || usa_error)\n\t\tgoto check_tail;\n\n\t/*\n\t * Done if the last lsn on this page doesn't match the previous known\n\t * last lsn or the sequence number is not expected.\n\t */\n\tlsn_cur = le64_to_cpu(page->rhdr.lsn);\n\tif (last_ok_lsn != lsn_cur &&\n\t    expected_seq != (lsn_cur >> log->file_data_bits)) {\n\t\tgoto check_tail;\n\t}\n\n\t/*\n\t * Check that the page position and page count values are correct.\n\t * If this is the first page of a transfer the position must be 1\n\t * and the count will be unknown.\n\t */\n\tif (page_cnt == page_pos) {\n\t\tif (page->page_pos != cpu_to_le16(1) &&\n\t\t    (!reuse_page || page->page_pos != page->page_count)) {\n\t\t\t/*\n\t\t\t * If the current page is the first page we are\n\t\t\t * looking at and we are reusing this page then\n\t\t\t * it can be either the first or last page of a\n\t\t\t * transfer. Otherwise it can only be the first.\n\t\t\t */\n\t\t\tgoto check_tail;\n\t\t}\n\t} else if (le16_to_cpu(page->page_count) != page_cnt ||\n\t\t   le16_to_cpu(page->page_pos) != page_pos + 1) {\n\t\t/*\n\t\t * The page position better be 1 more than the last page\n\t\t * position and the page count better match.\n\t\t */\n\t\tgoto check_tail;\n\t}\n\n\t/*\n\t * We have a valid page the file and may have a valid page\n\t * the tail copy area.\n\t * If the tail page was written after the page the file then\n\t * break of the loop.\n\t */\n\tif (tail_page &&\n\t    le64_to_cpu(tail_page->record_hdr.last_end_lsn) > lsn_cur) {\n\t\t/* Remember if we will replace the page. */\n\t\treplace_page = true;\n\t\tgoto check_tail;\n\t}\n\n\ttail_page = NULL;\n\n\tif (is_log_record_end(page)) {\n\t\t/*\n\t\t * Since we have read this page we know the sequence number\n\t\t * is the same as our expected value.\n\t\t */\n\t\tlog->seq_num = expected_seq;\n\t\tlog->last_lsn = le64_to_cpu(page->record_hdr.last_end_lsn);\n\t\tlog->ra->current_lsn = page->record_hdr.last_end_lsn;\n\t\tlog->l_flags &= ~NTFSLOG_NO_LAST_LSN;\n\n\t\t/*\n\t\t * If there is room on this page for another header then\n\t\t * remember we want to reuse the page.\n\t\t */\n\t\tif (log->record_header_len <=\n\t\t    log->page_size -\n\t\t\t    le16_to_cpu(page->record_hdr.next_record_off)) {\n\t\t\tlog->l_flags |= NTFSLOG_REUSE_TAIL;\n\t\t\tlog->next_page = curpage_off;\n\t\t} else {\n\t\t\tlog->l_flags &= ~NTFSLOG_REUSE_TAIL;\n\t\t\tlog->next_page = nextpage_off;\n\t\t}\n\n\t\t/* Remember if we wrapped the log file. */\n\t\tif (wrapped_file)\n\t\t\tlog->l_flags |= NTFSLOG_WRAPPED;\n\t}\n\n\t/*\n\t * Remember the last page count and position.\n\t * Also remember the last known lsn.\n\t */\n\tpage_cnt = le16_to_cpu(page->page_count);\n\tpage_pos = le16_to_cpu(page->page_pos);\n\tlast_ok_lsn = le64_to_cpu(page->rhdr.lsn);\n\nnext_page_1:\n\n\tif (wrapped) {\n\t\texpected_seq += 1;\n\t\twrapped_file = 1;\n\t}\n\n\tcurpage_off = nextpage_off;\n\tkfree(page);\n\tpage = NULL;\n\treuse_page = 0;\n\tgoto next_page;\n\ncheck_tail:\n\tif (tail_page) {\n\t\tlog->seq_num = expected_seq;\n\t\tlog->last_lsn = le64_to_cpu(tail_page->record_hdr.last_end_lsn);\n\t\tlog->ra->current_lsn = tail_page->record_hdr.last_end_lsn;\n\t\tlog->l_flags &= ~NTFSLOG_NO_LAST_LSN;\n\n\t\tif (log->page_size -\n\t\t\t    le16_to_cpu(\n\t\t\t\t    tail_page->record_hdr.next_record_off) >=\n\t\t    log->record_header_len) {\n\t\t\tlog->l_flags |= NTFSLOG_REUSE_TAIL;\n\t\t\tlog->next_page = curpage_off;\n\t\t} else {\n\t\t\tlog->l_flags &= ~NTFSLOG_REUSE_TAIL;\n\t\t\tlog->next_page = nextpage_off;\n\t\t}\n\n\t\tif (wrapped)\n\t\t\tlog->l_flags |= NTFSLOG_WRAPPED;\n\t}\n\n\t/* Remember that the partial IO will start at the next page. */\n\tsecond_off = nextpage_off;\n\n\t/*\n\t * If the next page is the first page of the file then update\n\t * the sequence number for log records which begon the next page.\n\t */\n\tif (wrapped)\n\t\texpected_seq += 1;\n\n\t/*\n\t * If we have a tail copy or are performing single page I/O we can\n\t * immediately look at the next page.\n\t */\n\tif (replace_page || (log->ra->flags & RESTART_SINGLE_PAGE_IO)) {\n\t\tpage_cnt = 2;\n\t\tpage_pos = 1;\n\t\tgoto check_valid;\n\t}\n\n\tif (page_pos != page_cnt)\n\t\tgoto check_valid;\n\t/*\n\t * If the next page causes us to wrap to the beginning of the log\n\t * file then we know which page to check next.\n\t */\n\tif (wrapped) {\n\t\tpage_cnt = 2;\n\t\tpage_pos = 1;\n\t\tgoto check_valid;\n\t}\n\n\tcur_pos = 2;\n\nnext_test_page:\n\tkfree(tst_page);\n\ttst_page = NULL;\n\n\t/* Walk through the file, reading log pages. */\n\terr = read_log_page(log, nextpage_off, &tst_page, &usa_error);\n\n\t/*\n\t * If we get a USA error then assume that we correctly found\n\t * the end of the original transfer.\n\t */\n\tif (usa_error)\n\t\tgoto file_is_valid;\n\n\t/*\n\t * If we were able to read the page, we examine it to see if it\n\t * is the same or different Io block.\n\t */\n\tif (err)\n\t\tgoto next_test_page_1;\n\n\tif (le16_to_cpu(tst_page->page_pos) == cur_pos &&\n\t    check_subseq_log_page(log, tst_page, nextpage_off, expected_seq)) {\n\t\tpage_cnt = le16_to_cpu(tst_page->page_count) + 1;\n\t\tpage_pos = le16_to_cpu(tst_page->page_pos);\n\t\tgoto check_valid;\n\t} else {\n\t\tgoto file_is_valid;\n\t}\n\nnext_test_page_1:\n\n\tnextpage_off = next_page_off(log, curpage_off);\n\twrapped = nextpage_off == log->first_page;\n\n\tif (wrapped) {\n\t\texpected_seq += 1;\n\t\tpage_cnt = 2;\n\t\tpage_pos = 1;\n\t}\n\n\tcur_pos += 1;\n\tpart_io_count += 1;\n\tif (!wrapped)\n\t\tgoto next_test_page;\n\ncheck_valid:\n\t/* Skip over the remaining pages this transfer. */\n\tremain_pages = page_cnt - page_pos - 1;\n\tpart_io_count += remain_pages;\n\n\twhile (remain_pages--) {\n\t\tnextpage_off = next_page_off(log, curpage_off);\n\t\twrapped = nextpage_off == log->first_page;\n\n\t\tif (wrapped)\n\t\t\texpected_seq += 1;\n\t}\n\n\t/* Call our routine to check this log page. */\n\tkfree(tst_page);\n\ttst_page = NULL;\n\n\terr = read_log_page(log, nextpage_off, &tst_page, &usa_error);\n\tif (!err && !usa_error &&\n\t    check_subseq_log_page(log, tst_page, nextpage_off, expected_seq)) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\nfile_is_valid:\n\n\t/* We have a valid file. */\n\tif (page_off1 || tail_page) {\n\t\tstruct RECORD_PAGE_HDR *tmp_page;\n\n\t\tif (sb_rdonly(log->ni->mi.sbi->sb)) {\n\t\t\terr = -EROFS;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (page_off1) {\n\t\t\ttmp_page = Add2Ptr(page_bufs, page_off1 - page_off);\n\t\t\ttails -= (page_off1 - page_off) / log->page_size;\n\t\t\tif (!tail_page)\n\t\t\t\ttails -= 1;\n\t\t} else {\n\t\t\ttmp_page = tail_page;\n\t\t\ttails = 1;\n\t\t}\n\n\t\twhile (tails--) {\n\t\t\tu64 off = hdr_file_off(log, tmp_page);\n\n\t\t\tif (!page) {\n\t\t\t\tpage = kmalloc(log->page_size, GFP_NOFS);\n\t\t\t\tif (!page)\n\t\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Correct page and copy the data from this page\n\t\t\t * into it and flush it to disk.\n\t\t\t */\n\t\t\tmemcpy(page, tmp_page, log->page_size);\n\n\t\t\t/* Fill last flushed lsn value flush the page. */\n\t\t\tif (log->major_ver < 2)\n\t\t\t\tpage->rhdr.lsn = page->record_hdr.last_end_lsn;\n\t\t\telse\n\t\t\t\tpage->file_off = 0;\n\n\t\t\tpage->page_pos = page->page_count = cpu_to_le16(1);\n\n\t\t\tntfs_fix_pre_write(&page->rhdr, log->page_size);\n\n\t\t\terr = ntfs_sb_write_run(log->ni->mi.sbi,\n\t\t\t\t\t\t&log->ni->file.run, off, page,\n\t\t\t\t\t\tlog->page_size, 0);\n\n\t\t\tif (err)\n\t\t\t\tgoto out;\n\n\t\t\tif (part_io_count && second_off == off) {\n\t\t\t\tsecond_off += log->page_size;\n\t\t\t\tpart_io_count -= 1;\n\t\t\t}\n\n\t\t\ttmp_page = Add2Ptr(tmp_page, log->page_size);\n\t\t}\n\t}\n\n\tif (part_io_count) {\n\t\tif (sb_rdonly(log->ni->mi.sbi->sb)) {\n\t\t\terr = -EROFS;\n\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\tkfree(second_tail);\n\tkfree(first_tail);\n\tkfree(page);\n\tkfree(tst_page);\n\tkfree(page_bufs);\n\n\treturn err;\n}",
        "static struct sk_buff *sja1110_rcv_meta(struct sk_buff *skb, u16 rx_header)\n{\n\tu8 *buf = dsa_etype_header_pos_rx(skb) + SJA1110_HEADER_LEN;\n\tint switch_id = SJA1110_RX_HEADER_SWITCH_ID(rx_header);\n\tint n_ts = SJA1110_RX_HEADER_N_TS(rx_header);": "static struct sk_buff *sja1110_rcv_meta(struct sk_buff *skb, u16 rx_header)\n{\n\tu8 *buf = dsa_etype_header_pos_rx(skb) + SJA1110_HEADER_LEN;\n\tint switch_id = SJA1110_RX_HEADER_SWITCH_ID(rx_header);\n\tint n_ts = SJA1110_RX_HEADER_N_TS(rx_header);\n\tstruct sja1105_tagger_data *tagger_data;\n\tstruct net_device *master = skb->dev;\n\tstruct dsa_port *cpu_dp;\n\tstruct dsa_switch *ds;\n\tint i;\n\n\tcpu_dp = master->dsa_ptr;\n\tds = dsa_switch_find(cpu_dp->dst->index, switch_id);\n\tif (!ds) {\n\t\tnet_err_ratelimited(\"%s: cannot find switch id %d\\n\",\n\t\t\t\t    master->name, switch_id);\n\t\treturn NULL;\n\t}\n\n\ttagger_data = sja1105_tagger_data(ds);\n\tif (!tagger_data->meta_tstamp_handler)\n\t\treturn NULL;\n\n\tfor (i = 0; i <= n_ts; i++) {\n\t\tu8 ts_id, source_port, dir;\n\t\tu64 tstamp;\n\n\t\tts_id = buf[0];\n\t\tsource_port = (buf[1] & GENMASK(7, 4)) >> 4;\n\t\tdir = (buf[1] & BIT(3)) >> 3;\n\t\ttstamp = be64_to_cpu(*(__be64 *)(buf + 2));\n\n\t\ttagger_data->meta_tstamp_handler(ds, source_port, ts_id, dir,\n\t\t\t\t\t\t tstamp);\n\n\t\tbuf += SJA1110_META_TSTAMP_SIZE;\n\t}\n\n\t/* Discard the meta frame, we've consumed the timestamps it contained */\n\treturn NULL;\n}",
        "static void isc_sama5d2_config_rlp(struct isc_device *isc)\n{\n\tstruct regmap *regmap = isc->regmap;\n\tu32 rlp_mode = isc->config.rlp_cfg_mode;\n": "static void isc_sama5d2_config_rlp(struct isc_device *isc)\n{\n\tstruct regmap *regmap = isc->regmap;\n\tu32 rlp_mode = isc->config.rlp_cfg_mode;\n\n\t/*\n\t * In sama5d2, the YUV planar modes and the YUYV modes are treated\n\t * in the same way in RLP register.\n\t * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n)\n\t * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n)\n\t * but in sama5d2, the YCYC mode does not exist, and YYCC must be\n\t * selected for both planar and interleaved modes, as in fact\n\t * both modes are supported.\n\t *\n\t * Thus, if the YCYC mode is selected, replace it with the\n\t * sama5d2-compliant mode which is YYCC .\n\t */\n\tif ((rlp_mode & ISC_RLP_CFG_MODE_MASK) == ISC_RLP_CFG_MODE_YCYC) {\n\t\trlp_mode &= ~ISC_RLP_CFG_MODE_MASK;\n\t\trlp_mode |= ISC_RLP_CFG_MODE_YYCC;\n\t}\n\n\tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n\t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n}",
        "static void test_sethwdebug_range_aligned(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info;\n\tunsigned long wp_addr;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW ALIGNED\";": "static void test_sethwdebug_range_aligned(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info;\n\tunsigned long wp_addr;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW ALIGNED\";\n\tint len;\n\tint wh;\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW ALIGNED, WO test */\n\twp_addr = (unsigned long)&gstruct.a;\n\tlen = A_LEN;\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_WRITE, wp_addr, len);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"WO\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW ALIGNED, RO test */\n\twp_addr = (unsigned long)&gstruct.a;\n\tlen = A_LEN;\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_READ, wp_addr, len);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RO\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW ALIGNED, RW test */\n\twp_addr = (unsigned long)&gstruct.a;\n\tlen = A_LEN;\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_RW, wp_addr, len);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RW\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n}",
        "static int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)\n{\n\tstatic const u32 max_weight = BIT(HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH) - 1;\n\t/* Scale factor is based on the number of bits in fractional portion */\n\tstatic const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);": "static int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)\n{\n\tstatic const u32 max_weight = BIT(HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH) - 1;\n\t/* Scale factor is based on the number of bits in fractional portion */\n\tstatic const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);\n\tstatic const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>\n\t\t\t\t    HW_ATL_TPS_DESC_RATE_Y_SHIFT;\n\tconst u32 link_speed = self->aq_link_status.mbps;\n\tstruct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;\n\tunsigned long num_min_rated_tcs = 0;\n\tu32 tc_weight[AQ_CFG_TCS_MAX];\n\tu32 fixed_max_credit;\n\tu8 min_rate_msk = 0;\n\tu32 sum_weight = 0;\n\tint tc;\n\n\t/* By default max_credit is based upon MTU (in unit of 64b) */\n\tfixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64;\n\n\tif (link_speed) {\n\t\tmin_rate_msk = nic_cfg->tc_min_rate_msk &\n\t\t\t       (BIT(nic_cfg->tcs) - 1);\n\t\tnum_min_rated_tcs = hweight8(min_rate_msk);\n\t}\n\n\t/* First, calculate weights where min_rate is specified */\n\tif (num_min_rated_tcs) {\n\t\tfor (tc = 0; tc != nic_cfg->tcs; tc++) {\n\t\t\tif (!nic_cfg->tc_min_rate[tc]) {\n\t\t\t\ttc_weight[tc] = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\ttc_weight[tc] = (-1L + link_speed +\n\t\t\t\t\t nic_cfg->tc_min_rate[tc] *\n\t\t\t\t\t max_weight) /\n\t\t\t\t\tlink_speed;\n\t\t\ttc_weight[tc] = min(tc_weight[tc], max_weight);\n\t\t\tsum_weight += tc_weight[tc];\n\t\t}\n\t}\n\n\t/* WSP, if min_rate is set for at least one TC.\n\t * RR otherwise.\n\t *\n\t * NB! MAC FW sets arb mode itself if PTP is enabled. We shouldn't\n\t * overwrite it here in that case.\n\t */\n\tif (!nic_cfg->is_ptp)\n\t\thw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U);\n\n\t/* Data TC Arbiter takes precedence over Descriptor TC Arbiter,\n\t * leave Descriptor TC Arbiter as RR.\n\t */\n\thw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);\n\n\thw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);\n\n\tfor (tc = 0; tc != nic_cfg->tcs; tc++) {\n\t\tconst u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;\n\t\tconst u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);\n\t\tu32 weight, max_credit;\n\n\t\thw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc,\n\t\t\t\t\t\t\t      fixed_max_credit);\n\t\thw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E);\n\n\t\tif (num_min_rated_tcs) {\n\t\t\tweight = tc_weight[tc];\n\n\t\t\tif (!weight && sum_weight < max_weight)\n\t\t\t\tweight = (max_weight - sum_weight) /\n\t\t\t\t\t (nic_cfg->tcs - num_min_rated_tcs);\n\t\t\telse if (!weight)\n\t\t\t\tweight = 0x64;\n\n\t\t\tmax_credit = max(8 * weight, fixed_max_credit);\n\t\t} else {\n\t\t\tweight = 0x64;\n\t\t\tmax_credit = 0xFFF;\n\t\t}\n\n\t\thw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight);\n\t\thw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc,\n\t\t\t\t\t\t\t      max_credit);\n\n\t\thw_atl_tps_tx_desc_rate_en_set(self, desc, en);\n\n\t\tif (en) {\n\t\t\t/* Nominal rate is always 10G */\n\t\t\tconst u32 rate = 10000U * scale /\n\t\t\t\t\t nic_cfg->tc_max_rate[tc];\n\t\t\tconst u32 rate_int = rate >>\n\t\t\t\t\t     HW_ATL_TPS_DESC_RATE_Y_WIDTH;\n\t\t\tconst u32 rate_frac = rate & frac_msk;\n\n\t\t\thw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int);\n\t\t\thw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac);\n\t\t} else {\n\t\t\t/* A value of 1 indicates the queue is not\n\t\t\t * rate controlled.\n\t\t\t */\n\t\t\thw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);\n\t\t\thw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);\n\t\t}\n\t}\n\tfor (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) {\n\t\tconst u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);\n\n\t\thw_atl_tps_tx_desc_rate_en_set(self, desc, 0U);\n\t\thw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);\n\t\thw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);\n\t}\n\n\treturn aq_hw_err_from_flags(self);\n}",
        "static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id)\n{\n\tstruct syscall_metadata *sys_data;\n\tstruct syscall_trace_enter *rec;\n\tstruct hlist_head *head;": "static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id)\n{\n\tstruct syscall_metadata *sys_data;\n\tstruct syscall_trace_enter *rec;\n\tstruct hlist_head *head;\n\tunsigned long args[6];\n\tbool valid_prog_array;\n\tint syscall_nr;\n\tint rctx;\n\tint size;\n\n\tsyscall_nr = trace_get_syscall_nr(current, regs);\n\tif (syscall_nr < 0 || syscall_nr >= NR_syscalls)\n\t\treturn;\n\tif (!test_bit(syscall_nr, enabled_perf_enter_syscalls))\n\t\treturn;\n\n\tsys_data = syscall_nr_to_meta(syscall_nr);\n\tif (!sys_data)\n\t\treturn;\n\n\thead = this_cpu_ptr(sys_data->enter_event->perf_events);\n\tvalid_prog_array = bpf_prog_array_valid(sys_data->enter_event);\n\tif (!valid_prog_array && hlist_empty(head))\n\t\treturn;\n\n\t/* get the size after alignment with the u32 buffer size field */\n\tsize = sizeof(unsigned long) * sys_data->nb_args + sizeof(*rec);\n\tsize = ALIGN(size + sizeof(u32), sizeof(u64));\n\tsize -= sizeof(u32);\n\n\trec = perf_trace_buf_alloc(size, NULL, &rctx);\n\tif (!rec)\n\t\treturn;\n\n\trec->nr = syscall_nr;\n\tsyscall_get_arguments(current, regs, args);\n\tmemcpy(&rec->args, args, sizeof(unsigned long) * sys_data->nb_args);\n\n\tif ((valid_prog_array &&\n\t     !perf_call_bpf_enter(sys_data->enter_event, regs, sys_data, rec)) ||\n\t    hlist_empty(head)) {\n\t\tperf_swevent_put_recursion_context(rctx);\n\t\treturn;\n\t}\n\n\tperf_trace_buf_submit(rec, size, rctx,\n\t\t\t      sys_data->enter_event->event.type, 1, regs,\n\t\t\t      head, NULL);\n}",
        "static void kprobe_multi_check(void *ctx, bool is_return)\n{\n\tif (bpf_get_current_pid_tgid() >> 32 != pid)\n\t\treturn;\n": "static void kprobe_multi_check(void *ctx, bool is_return)\n{\n\tif (bpf_get_current_pid_tgid() >> 32 != pid)\n\t\treturn;\n\n\t__u64 cookie = test_cookie ? bpf_get_attach_cookie(ctx) : 0;\n\t__u64 addr = bpf_get_func_ip(ctx) - (CONFIG_X86_KERNEL_IBT ? 4 : 0);\n\n#define SET(__var, __addr, __cookie) ({\t\t\t\\\n\tif (((const void *) addr == __addr) &&\t\t\\\n\t     (!test_cookie || (cookie == __cookie)))\t\\\n\t\t__var = 1;\t\t\t\t\\\n})\n\n\tif (is_return) {\n\t\tSET(kretprobe_test1_result, &bpf_fentry_test1, 8);\n\t\tSET(kretprobe_test2_result, &bpf_fentry_test2, 7);\n\t\tSET(kretprobe_test3_result, &bpf_fentry_test3, 6);\n\t\tSET(kretprobe_test4_result, &bpf_fentry_test4, 5);\n\t\tSET(kretprobe_test5_result, &bpf_fentry_test5, 4);\n\t\tSET(kretprobe_test6_result, &bpf_fentry_test6, 3);\n\t\tSET(kretprobe_test7_result, &bpf_fentry_test7, 2);\n\t\tSET(kretprobe_test8_result, &bpf_fentry_test8, 1);\n\t} else {\n\t\tSET(kprobe_test1_result, &bpf_fentry_test1, 1);\n\t\tSET(kprobe_test2_result, &bpf_fentry_test2, 2);\n\t\tSET(kprobe_test3_result, &bpf_fentry_test3, 3);\n\t\tSET(kprobe_test4_result, &bpf_fentry_test4, 4);\n\t\tSET(kprobe_test5_result, &bpf_fentry_test5, 5);\n\t\tSET(kprobe_test6_result, &bpf_fentry_test6, 6);\n\t\tSET(kprobe_test7_result, &bpf_fentry_test7, 7);\n\t\tSET(kprobe_test8_result, &bpf_fentry_test8, 8);\n\t}\n\n#undef SET\n}",
        "static void avs6eyes_init(struct zoran *zr)\n{\n\t// AverMedia 6-Eyes original driver by Christer Weinigel\n\n\t// Lifted straight from Christer's old driver and": "static void avs6eyes_init(struct zoran *zr)\n{\n\t// AverMedia 6-Eyes original driver by Christer Weinigel\n\n\t// Lifted straight from Christer's old driver and\n\t// modified slightly by Martin Samuelsson.\n\n\tint mux = default_mux; /* 1 = BT866, 7 = VID1 */\n\n\tGPIO(zr, 4, 1); /* Bt866 SLEEP on */\n\tudelay(2);\n\n\tGPIO(zr, 0, 1); /* ZR36060 /RESET on */\n\tGPIO(zr, 1, 0); /* ZR36060 /SLEEP on */\n\tGPIO(zr, 2, mux & 1);   /* MUX S0 */\n\tGPIO(zr, 3, 0); /* /FRAME on */\n\tGPIO(zr, 4, 0); /* Bt866 SLEEP off */\n\tGPIO(zr, 5, mux & 2);   /* MUX S1 */\n\tGPIO(zr, 6, 0); /* ? */\n\tGPIO(zr, 7, mux & 4);   /* MUX S2 */\n}",
        "static bool is_kcfg_value_in_range(const struct extern_desc *ext, __u64 v)\n{\n\tint bit_sz = ext->kcfg.sz * 8;\n\n\tif (ext->kcfg.sz == 8)": "static bool is_kcfg_value_in_range(const struct extern_desc *ext, __u64 v)\n{\n\tint bit_sz = ext->kcfg.sz * 8;\n\n\tif (ext->kcfg.sz == 8)\n\t\treturn true;\n\n\t/* Validate that value stored in u64 fits in integer of `ext->sz`\n\t * bytes size without any loss of information. If the target integer\n\t * is signed, we rely on the following limits of integer type of\n\t * Y bits and subsequent transformation:\n\t *\n\t *     -2^(Y-1) <= X           <= 2^(Y-1) - 1\n\t *            0 <= X + 2^(Y-1) <= 2^Y - 1\n\t *            0 <= X + 2^(Y-1) <  2^Y\n\t *\n\t *  For unsigned target integer, check that all the (64 - Y) bits are\n\t *  zero.\n\t */\n\tif (ext->kcfg.is_signed)\n\t\treturn v + (1ULL << (bit_sz - 1)) < (1ULL << bit_sz);\n\telse\n\t\treturn (v >> bit_sz) == 0;\n}",
        "static int test__dso_data_reopen(struct test_suite *test __maybe_unused, int subtest __maybe_unused)\n{\n\tstruct machine machine;\n\tlong nr_end, nr = open_files_cnt(), lim = new_limit(3);\n\tint fd, fd_extra;": "static int test__dso_data_reopen(struct test_suite *test __maybe_unused, int subtest __maybe_unused)\n{\n\tstruct machine machine;\n\tlong nr_end, nr = open_files_cnt(), lim = new_limit(3);\n\tint fd, fd_extra;\n\n#define dso_0 (dsos[0])\n#define dso_1 (dsos[1])\n#define dso_2 (dsos[2])\n\n\t/* Rest the internal dso open counter limit. */\n\treset_fd_limit();\n\n\tmemset(&machine, 0, sizeof(machine));\n\n\t/*\n\t * Test scenario:\n\t * - create 3 dso objects\n\t * - set process file descriptor limit to current\n\t *   files count + 3\n\t * - test that the first dso gets closed when we\n\t *   reach the files count limit\n\t */\n\n\t/* Make sure we are able to open 3 fds anyway */\n\tTEST_ASSERT_VAL(\"failed to set file limit\",\n\t\t\t!set_fd_limit((lim)));\n\n\tTEST_ASSERT_VAL(\"failed to create dsos\\n\", !dsos__create(3, TEST_FILE_SIZE));\n\n\t/* open dso_0 */\n\tfd = dso__data_fd(dso_0, &machine);\n\tTEST_ASSERT_VAL(\"failed to get fd\", fd > 0);\n\n\t/* open dso_1 */\n\tfd = dso__data_fd(dso_1, &machine);\n\tTEST_ASSERT_VAL(\"failed to get fd\", fd > 0);\n\n\t/*\n\t * open extra file descriptor and we just\n\t * reached the files count limit\n\t */\n\tfd_extra = open(\"/dev/null\", O_RDONLY);\n\tTEST_ASSERT_VAL(\"failed to open extra fd\", fd_extra > 0);\n\n\t/* open dso_2 */\n\tfd = dso__data_fd(dso_2, &machine);\n\tTEST_ASSERT_VAL(\"failed to get fd\", fd > 0);\n\n\t/*\n\t * dso_0 should get closed, because we reached\n\t * the file descriptor limit\n\t */\n\tTEST_ASSERT_VAL(\"failed to close dso_0\", dso_0->data.fd == -1);\n\n\t/* open dso_0 */\n\tfd = dso__data_fd(dso_0, &machine);\n\tTEST_ASSERT_VAL(\"failed to get fd\", fd > 0);\n\n\t/*\n\t * dso_1 should get closed, because we reached\n\t * the file descriptor limit\n\t */\n\tTEST_ASSERT_VAL(\"failed to close dso_1\", dso_1->data.fd == -1);\n\n\t/* cleanup everything */\n\tclose(fd_extra);\n\tdsos__delete(3);\n\n\t/* Make sure we did not leak any file descriptor. */\n\tnr_end = open_files_cnt();\n\tpr_debug(\"nr start %ld, nr stop %ld\\n\", nr, nr_end);\n\tTEST_ASSERT_VAL(\"failed leaking files\", nr == nr_end);\n\treturn 0;\n}",
        "static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)\n{\n\tunsigned wait;\n\n\tqh_unlink_periodic(oxu, qh);": "static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)\n{\n\tunsigned wait;\n\n\tqh_unlink_periodic(oxu, qh);\n\n\t/* simple/paranoid:  always delay, expecting the HC needs to read\n\t * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and\n\t * expect hub_wq to clean up after any CSPLITs we won't issue.\n\t * active high speed queues may need bigger delays...\n\t */\n\tif (list_empty(&qh->qtd_list)\n\t\t|| (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)\n\t\twait = 2;\n\telse\n\t\twait = 55;\t/* worst case: 3 * 1024 */\n\n\tudelay(wait);\n\tqh->qh_state = QH_STATE_IDLE;\n\tqh->hw_next = EHCI_LIST_END;\n\twmb();\n}",
        "static void samsung_nand_decode_id(struct nand_chip *chip)\n{\n\tstruct nand_device *base = &chip->base;\n\tstruct nand_ecc_props requirements = {};\n\tstruct mtd_info *mtd = nand_to_mtd(chip);": "static void samsung_nand_decode_id(struct nand_chip *chip)\n{\n\tstruct nand_device *base = &chip->base;\n\tstruct nand_ecc_props requirements = {};\n\tstruct mtd_info *mtd = nand_to_mtd(chip);\n\tstruct nand_memory_organization *memorg;\n\n\tmemorg = nanddev_get_memorg(&chip->base);\n\n\t/* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) */\n\tif (chip->id.len == 6 && !nand_is_slc(chip) &&\n\t    chip->id.data[5] != 0x00) {\n\t\tu8 extid = chip->id.data[3];\n\n\t\t/* Get pagesize */\n\t\tmemorg->pagesize = 2048 << (extid & 0x03);\n\t\tmtd->writesize = memorg->pagesize;\n\n\t\textid >>= 2;\n\n\t\t/* Get oobsize */\n\t\tswitch (((extid >> 2) & 0x4) | (extid & 0x3)) {\n\t\tcase 1:\n\t\t\tmemorg->oobsize = 128;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tmemorg->oobsize = 218;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tmemorg->oobsize = 400;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tmemorg->oobsize = 436;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tmemorg->oobsize = 512;\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tmemorg->oobsize = 640;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/*\n\t\t\t * We should never reach this case, but if that\n\t\t\t * happens, this probably means Samsung decided to use\n\t\t\t * a different extended ID format, and we should find\n\t\t\t * a way to support it.\n\t\t\t */\n\t\t\tWARN(1, \"Invalid OOB size value\");\n\t\t\tbreak;\n\t\t}\n\n\t\tmtd->oobsize = memorg->oobsize;\n\n\t\t/* Get blocksize */\n\t\textid >>= 2;\n\t\tmemorg->pages_per_eraseblock = (128 * 1024) <<\n\t\t\t\t\t       (((extid >> 1) & 0x04) |\n\t\t\t\t\t\t(extid & 0x03)) /\n\t\t\t\t\t       memorg->pagesize;\n\t\tmtd->erasesize = (128 * 1024) <<\n\t\t\t\t (((extid >> 1) & 0x04) | (extid & 0x03));\n\n\t\t/* Extract ECC requirements from 5th id byte*/\n\t\textid = (chip->id.data[4] >> 4) & 0x07;\n\t\tif (extid < 5) {\n\t\t\trequirements.step_size = 512;\n\t\t\trequirements.strength = 1 << extid;\n\t\t} else {\n\t\t\trequirements.step_size = 1024;\n\t\t\tswitch (extid) {\n\t\t\tcase 5:\n\t\t\t\trequirements.strength = 24;\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\trequirements.strength = 40;\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\trequirements.strength = 60;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tWARN(1, \"Could not decode ECC info\");\n\t\t\t\trequirements.step_size = 0;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tnand_decode_ext_id(chip);\n\n\t\tif (nand_is_slc(chip)) {\n\t\t\tswitch (chip->id.data[1]) {\n\t\t\t/* K9F4G08U0D-S[I|C]B0(T00) */\n\t\t\tcase 0xDC:\n\t\t\t\trequirements.step_size = 512;\n\t\t\t\trequirements.strength = 1;\n\t\t\t\tbreak;\n\n\t\t\t/* K9F1G08U0E 21nm chips do not support subpage write */\n\t\t\tcase 0xF1:\n\t\t\t\tif (chip->id.len > 4 &&\n\t\t\t\t    (chip->id.data[4] & GENMASK(1, 0)) == 0x1)\n\t\t\t\t\tchip->options |= NAND_NO_SUBPAGE_WRITE;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tnanddev_set_ecc_requirements(base, &requirements);\n}",
        "static bool ssh_rtl_cancel_pending(struct ssh_request *r)\n{\n\t/* If the packet is already locked, it's going to be removed shortly. */\n\tif (test_and_set_bit(SSH_REQUEST_SF_LOCKED_BIT, &r->state))\n\t\treturn true;": "static bool ssh_rtl_cancel_pending(struct ssh_request *r)\n{\n\t/* If the packet is already locked, it's going to be removed shortly. */\n\tif (test_and_set_bit(SSH_REQUEST_SF_LOCKED_BIT, &r->state))\n\t\treturn true;\n\n\t/*\n\t * Now that we have locked the packet, we have guaranteed that it can't\n\t * be added to the system any more. If ptl is NULL, the locked\n\t * check in ssh_rtl_submit() has not been run and any submission,\n\t * currently in progress or called later, won't add the packet. Thus we\n\t * can directly complete it.\n\t *\n\t * The implicit memory barrier of test_and_set_bit() should be enough\n\t * to ensure that the correct order (first lock, then check ptl) is\n\t * ensured. This is paired with the barrier in ssh_rtl_submit().\n\t */\n\tif (!READ_ONCE(r->packet.ptl)) {\n\t\tif (test_and_set_bit(SSH_REQUEST_SF_COMPLETED_BIT, &r->state))\n\t\t\treturn true;\n\n\t\tssh_rtl_complete_with_status(r, -ECANCELED);\n\t\treturn true;\n\t}\n\n\t/*\n\t * Try to cancel the packet. If the packet has not been completed yet,\n\t * this will subsequently (and synchronously) call the completion\n\t * callback of the packet, which will complete the request.\n\t */\n\tssh_ptl_cancel(&r->packet);\n\n\t/*\n\t * If the packet has been completed with success, i.e. has not been\n\t * canceled by the above call, the request may not have been completed\n\t * yet (may be waiting for a response). Check if we need to do this\n\t * here.\n\t */\n\tif (test_and_set_bit(SSH_REQUEST_SF_COMPLETED_BIT, &r->state))\n\t\treturn true;\n\n\tssh_rtl_queue_remove(r);\n\tssh_rtl_pending_remove(r);\n\tssh_rtl_complete_with_status(r, -ECANCELED);\n\n\treturn true;\n}",
        "static void ocfs2_xa_bucket_add_entry(struct ocfs2_xa_loc *loc, u32 name_hash)\n{\n\tstruct ocfs2_xattr_header *xh = loc->xl_header;\n\tint count = le16_to_cpu(xh->xh_count);\n\tint low = 0, high = count - 1, tmp;": "static void ocfs2_xa_bucket_add_entry(struct ocfs2_xa_loc *loc, u32 name_hash)\n{\n\tstruct ocfs2_xattr_header *xh = loc->xl_header;\n\tint count = le16_to_cpu(xh->xh_count);\n\tint low = 0, high = count - 1, tmp;\n\tstruct ocfs2_xattr_entry *tmp_xe;\n\n\t/*\n\t * We keep buckets sorted by name_hash, so we need to find\n\t * our insert place.\n\t */\n\twhile (low <= high && count) {\n\t\ttmp = (low + high) / 2;\n\t\ttmp_xe = &xh->xh_entries[tmp];\n\n\t\tif (name_hash > le32_to_cpu(tmp_xe->xe_name_hash))\n\t\t\tlow = tmp + 1;\n\t\telse if (name_hash < le32_to_cpu(tmp_xe->xe_name_hash))\n\t\t\thigh = tmp - 1;\n\t\telse {\n\t\t\tlow = tmp;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (low != count)\n\t\tmemmove(&xh->xh_entries[low + 1],\n\t\t\t&xh->xh_entries[low],\n\t\t\t((count - low) * sizeof(struct ocfs2_xattr_entry)));\n\n\tle16_add_cpu(&xh->xh_count, 1);\n\tloc->xl_entry = &xh->xh_entries[low];\n\tmemset(loc->xl_entry, 0, sizeof(struct ocfs2_xattr_entry));\n}",
        "static void cpu_map_free(struct bpf_map *map)\n{\n\tstruct bpf_cpu_map *cmap = container_of(map, struct bpf_cpu_map, map);\n\tu32 i;\n": "static void cpu_map_free(struct bpf_map *map)\n{\n\tstruct bpf_cpu_map *cmap = container_of(map, struct bpf_cpu_map, map);\n\tu32 i;\n\n\t/* At this point bpf_prog->aux->refcnt == 0 and this map->refcnt == 0,\n\t * so the bpf programs (can be more than one that used this map) were\n\t * disconnected from events. Wait for outstanding critical sections in\n\t * these programs to complete. The rcu critical section only guarantees\n\t * no further \"XDP/bpf-side\" reads against bpf_cpu_map->cpu_map.\n\t * It does __not__ ensure pending flush operations (if any) are\n\t * complete.\n\t */\n\n\tsynchronize_rcu();\n\n\t/* For cpu_map the remote CPUs can still be using the entries\n\t * (struct bpf_cpu_map_entry).\n\t */\n\tfor (i = 0; i < cmap->map.max_entries; i++) {\n\t\tstruct bpf_cpu_map_entry *rcpu;\n\n\t\trcpu = rcu_dereference_raw(cmap->cpu_map[i]);\n\t\tif (!rcpu)\n\t\t\tcontinue;\n\n\t\t/* bq flush and cleanup happens after RCU grace-period */\n\t\t__cpu_map_entry_replace(cmap, i, NULL); /* call_rcu */\n\t}\n\tbpf_map_area_free(cmap->cpu_map);\n\tkfree(cmap);\n}",
        "static inline void set_next_task_rt(struct rq *rq, struct task_struct *p, bool first)\n{\n\tstruct sched_rt_entity *rt_se = &p->rt;\n\tstruct rt_rq *rt_rq = &rq->rt;\n": "static inline void set_next_task_rt(struct rq *rq, struct task_struct *p, bool first)\n{\n\tstruct sched_rt_entity *rt_se = &p->rt;\n\tstruct rt_rq *rt_rq = &rq->rt;\n\n\tp->se.exec_start = rq_clock_task(rq);\n\tif (on_rt_rq(&p->rt))\n\t\tupdate_stats_wait_end_rt(rt_rq, rt_se);\n\n\t/* The running task is never eligible for pushing */\n\tdequeue_pushable_task(rq, p);\n\n\tif (!first)\n\t\treturn;\n\n\t/*\n\t * If prev task was rt, put_prev_task() has already updated the\n\t * utilization. We only care of the case where we start to schedule a\n\t * rt task\n\t */\n\tif (rq->curr->sched_class != &rt_sched_class)\n\t\tupdate_rt_rq_load_avg(rq_clock_pelt(rq), rq, 0);\n\n\trt_queue_push_tasks(rq);\n}",
        "static int ipc_server_config_on_startup(struct ksmbd_startup_request *req)\n{\n\tint ret;\n\n\tksmbd_set_fd_limit(req->file_max);": "static int ipc_server_config_on_startup(struct ksmbd_startup_request *req)\n{\n\tint ret;\n\n\tksmbd_set_fd_limit(req->file_max);\n\tserver_conf.flags = req->flags;\n\tserver_conf.signing = req->signing;\n\tserver_conf.tcp_port = req->tcp_port;\n\tserver_conf.ipc_timeout = req->ipc_timeout * HZ;\n\tserver_conf.deadtime = req->deadtime * SMB_ECHO_INTERVAL;\n\tserver_conf.share_fake_fscaps = req->share_fake_fscaps;\n\tksmbd_init_domain(req->sub_auth);\n\n\tif (req->smb2_max_read)\n\t\tinit_smb2_max_read_size(req->smb2_max_read);\n\tif (req->smb2_max_write)\n\t\tinit_smb2_max_write_size(req->smb2_max_write);\n\tif (req->smb2_max_trans)\n\t\tinit_smb2_max_trans_size(req->smb2_max_trans);\n\tif (req->smb2_max_credits)\n\t\tinit_smb2_max_credits(req->smb2_max_credits);\n\tif (req->smbd_max_io_size)\n\t\tinit_smbd_max_io_size(req->smbd_max_io_size);\n\n\tret = ksmbd_set_netbios_name(req->netbios_name);\n\tret |= ksmbd_set_server_string(req->server_string);\n\tret |= ksmbd_set_work_group(req->work_group);\n\tret |= ksmbd_tcp_set_interfaces(KSMBD_STARTUP_CONFIG_INTERFACES(req),\n\t\t\t\t\treq->ifc_list_sz);\n\tif (ret) {\n\t\tpr_err(\"Server configuration error: %s %s %s\\n\",\n\t\t       req->netbios_name, req->server_string,\n\t\t       req->work_group);\n\t\treturn ret;\n\t}\n\n\tif (req->min_prot[0]) {\n\t\tret = ksmbd_lookup_protocol_idx(req->min_prot);\n\t\tif (ret >= 0)\n\t\t\tserver_conf.min_protocol = ret;\n\t}\n\tif (req->max_prot[0]) {\n\t\tret = ksmbd_lookup_protocol_idx(req->max_prot);\n\t\tif (ret >= 0)\n\t\t\tserver_conf.max_protocol = ret;\n\t}\n\n\tif (server_conf.ipc_timeout)\n\t\tschedule_delayed_work(&ipc_timer_work, server_conf.ipc_timeout);\n\treturn 0;\n}",
        "static int ds_w1_init(struct ds_device *dev)\n{\n\tmemset(&dev->master, 0, sizeof(struct w1_bus_master));\n\n\t/* Reset the device as it can be in a bad state.": "static int ds_w1_init(struct ds_device *dev)\n{\n\tmemset(&dev->master, 0, sizeof(struct w1_bus_master));\n\n\t/* Reset the device as it can be in a bad state.\n\t * This is necessary because a block write will wait for data\n\t * to be placed in the output buffer and block any later\n\t * commands which will keep accumulating and the device will\n\t * not be idle.  Another case is removing the ds2490 module\n\t * while a bus search is in progress, somehow a few commands\n\t * get through, but the input transfers fail leaving data in\n\t * the input buffer.  This will cause the next read to fail\n\t * see the note in ds_recv_data.\n\t */\n\tds_reset_device(dev);\n\n\tdev->master.data\t= dev;\n\tdev->master.touch_bit\t= &ds9490r_touch_bit;\n\t/* read_bit and write_bit in w1_bus_master are expected to set and\n\t * sample the line level.  For write_bit that means it is expected to\n\t * set it to that value and leave it there.  ds2490 only supports an\n\t * individual time slot at the lowest level.  The requirement from\n\t * pulling the bus state down to reading the state is 15us, something\n\t * that isn't realistic on the USB bus anyway.\n\tdev->master.read_bit\t= &ds9490r_read_bit;\n\tdev->master.write_bit\t= &ds9490r_write_bit;\n\t*/\n\tdev->master.read_byte\t= &ds9490r_read_byte;\n\tdev->master.write_byte\t= &ds9490r_write_byte;\n\tdev->master.read_block\t= &ds9490r_read_block;\n\tdev->master.write_block\t= &ds9490r_write_block;\n\tdev->master.reset_bus\t= &ds9490r_reset;\n\tdev->master.set_pullup\t= &ds9490r_set_pullup;\n\tdev->master.search\t= &ds9490r_search;\n\n\treturn w1_add_master_device(&dev->master);\n}",
        "static void snd_trident_print_voice_regs(struct snd_trident *trident, int voice)\n{\n\tunsigned int val, tmp;\n\n\tdev_dbg(trident->card->dev, \"Trident voice %i:\\n\", voice);": "static void snd_trident_print_voice_regs(struct snd_trident *trident, int voice)\n{\n\tunsigned int val, tmp;\n\n\tdev_dbg(trident->card->dev, \"Trident voice %i:\\n\", voice);\n\toutb(voice, TRID_REG(trident, T4D_LFO_GC_CIR));\n\tval = inl(TRID_REG(trident, CH_LBA));\n\tdev_dbg(trident->card->dev, \"LBA: 0x%x\\n\", val);\n\tval = inl(TRID_REG(trident, CH_GVSEL_PAN_VOL_CTRL_EC));\n\tdev_dbg(trident->card->dev, \"GVSel: %i\\n\", val >> 31);\n\tdev_dbg(trident->card->dev, \"Pan: 0x%x\\n\", (val >> 24) & 0x7f);\n\tdev_dbg(trident->card->dev, \"Vol: 0x%x\\n\", (val >> 16) & 0xff);\n\tdev_dbg(trident->card->dev, \"CTRL: 0x%x\\n\", (val >> 12) & 0x0f);\n\tdev_dbg(trident->card->dev, \"EC: 0x%x\\n\", val & 0x0fff);\n\tif (trident->device != TRIDENT_DEVICE_ID_NX) {\n\t\tval = inl(TRID_REG(trident, CH_DX_CSO_ALPHA_FMS));\n\t\tdev_dbg(trident->card->dev, \"CSO: 0x%x\\n\", val >> 16);\n\t\tdev_dbg(trident->card->dev, \"Alpha: 0x%x\\n\", (val >> 4) & 0x0fff);\n\t\tdev_dbg(trident->card->dev, \"FMS: 0x%x\\n\", val & 0x0f);\n\t\tval = inl(TRID_REG(trident, CH_DX_ESO_DELTA));\n\t\tdev_dbg(trident->card->dev, \"ESO: 0x%x\\n\", val >> 16);\n\t\tdev_dbg(trident->card->dev, \"Delta: 0x%x\\n\", val & 0xffff);\n\t\tval = inl(TRID_REG(trident, CH_DX_FMC_RVOL_CVOL));\n\t} else {\t\t// TRIDENT_DEVICE_ID_NX\n\t\tval = inl(TRID_REG(trident, CH_NX_DELTA_CSO));\n\t\ttmp = (val >> 24) & 0xff;\n\t\tdev_dbg(trident->card->dev, \"CSO: 0x%x\\n\", val & 0x00ffffff);\n\t\tval = inl(TRID_REG(trident, CH_NX_DELTA_ESO));\n\t\ttmp |= (val >> 16) & 0xff00;\n\t\tdev_dbg(trident->card->dev, \"Delta: 0x%x\\n\", tmp);\n\t\tdev_dbg(trident->card->dev, \"ESO: 0x%x\\n\", val & 0x00ffffff);\n\t\tval = inl(TRID_REG(trident, CH_NX_ALPHA_FMS_FMC_RVOL_CVOL));\n\t\tdev_dbg(trident->card->dev, \"Alpha: 0x%x\\n\", val >> 20);\n\t\tdev_dbg(trident->card->dev, \"FMS: 0x%x\\n\", (val >> 16) & 0x0f);\n\t}\n\tdev_dbg(trident->card->dev, \"FMC: 0x%x\\n\", (val >> 14) & 3);\n\tdev_dbg(trident->card->dev, \"RVol: 0x%x\\n\", (val >> 7) & 0x7f);\n\tdev_dbg(trident->card->dev, \"CVol: 0x%x\\n\", val & 0x7f);\n}",
        "static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)\n{\n\tu32 dst_len, sect_len, offset = 0;\n\tstruct ice_prof_redir_section *pr;\n\tstruct ice_prof_id_section *pid;": "static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)\n{\n\tu32 dst_len, sect_len, offset = 0;\n\tstruct ice_prof_redir_section *pr;\n\tstruct ice_prof_id_section *pid;\n\tstruct ice_xlt1_section *xlt1;\n\tstruct ice_xlt2_section *xlt2;\n\tstruct ice_sw_fv_section *es;\n\tstruct ice_pkg_enum state;\n\tu8 *src, *dst;\n\tvoid *sect;\n\n\t/* if the HW segment pointer is null then the first iteration of\n\t * ice_pkg_enum_section() will fail. In this case the HW tables will\n\t * not be filled and return success.\n\t */\n\tif (!hw->seg) {\n\t\tice_debug(hw, ICE_DBG_PKG, \"hw->seg is NULL, tables are not filled\\n\");\n\t\treturn;\n\t}\n\n\tmemset(&state, 0, sizeof(state));\n\n\tsect = ice_pkg_enum_section(hw->seg, &state, sid);\n\n\twhile (sect) {\n\t\tswitch (sid) {\n\t\tcase ICE_SID_XLT1_SW:\n\t\tcase ICE_SID_XLT1_FD:\n\t\tcase ICE_SID_XLT1_RSS:\n\t\tcase ICE_SID_XLT1_ACL:\n\t\tcase ICE_SID_XLT1_PE:\n\t\t\txlt1 = sect;\n\t\t\tsrc = xlt1->value;\n\t\t\tsect_len = le16_to_cpu(xlt1->count) *\n\t\t\t\tsizeof(*hw->blk[block_id].xlt1.t);\n\t\t\tdst = hw->blk[block_id].xlt1.t;\n\t\t\tdst_len = hw->blk[block_id].xlt1.count *\n\t\t\t\tsizeof(*hw->blk[block_id].xlt1.t);\n\t\t\tbreak;\n\t\tcase ICE_SID_XLT2_SW:\n\t\tcase ICE_SID_XLT2_FD:\n\t\tcase ICE_SID_XLT2_RSS:\n\t\tcase ICE_SID_XLT2_ACL:\n\t\tcase ICE_SID_XLT2_PE:\n\t\t\txlt2 = sect;\n\t\t\tsrc = (__force u8 *)xlt2->value;\n\t\t\tsect_len = le16_to_cpu(xlt2->count) *\n\t\t\t\tsizeof(*hw->blk[block_id].xlt2.t);\n\t\t\tdst = (u8 *)hw->blk[block_id].xlt2.t;\n\t\t\tdst_len = hw->blk[block_id].xlt2.count *\n\t\t\t\tsizeof(*hw->blk[block_id].xlt2.t);\n\t\t\tbreak;\n\t\tcase ICE_SID_PROFID_TCAM_SW:\n\t\tcase ICE_SID_PROFID_TCAM_FD:\n\t\tcase ICE_SID_PROFID_TCAM_RSS:\n\t\tcase ICE_SID_PROFID_TCAM_ACL:\n\t\tcase ICE_SID_PROFID_TCAM_PE:\n\t\t\tpid = sect;\n\t\t\tsrc = (u8 *)pid->entry;\n\t\t\tsect_len = le16_to_cpu(pid->count) *\n\t\t\t\tsizeof(*hw->blk[block_id].prof.t);\n\t\t\tdst = (u8 *)hw->blk[block_id].prof.t;\n\t\t\tdst_len = hw->blk[block_id].prof.count *\n\t\t\t\tsizeof(*hw->blk[block_id].prof.t);\n\t\t\tbreak;\n\t\tcase ICE_SID_PROFID_REDIR_SW:\n\t\tcase ICE_SID_PROFID_REDIR_FD:\n\t\tcase ICE_SID_PROFID_REDIR_RSS:\n\t\tcase ICE_SID_PROFID_REDIR_ACL:\n\t\tcase ICE_SID_PROFID_REDIR_PE:\n\t\t\tpr = sect;\n\t\t\tsrc = pr->redir_value;\n\t\t\tsect_len = le16_to_cpu(pr->count) *\n\t\t\t\tsizeof(*hw->blk[block_id].prof_redir.t);\n\t\t\tdst = hw->blk[block_id].prof_redir.t;\n\t\t\tdst_len = hw->blk[block_id].prof_redir.count *\n\t\t\t\tsizeof(*hw->blk[block_id].prof_redir.t);\n\t\t\tbreak;\n\t\tcase ICE_SID_FLD_VEC_SW:\n\t\tcase ICE_SID_FLD_VEC_FD:\n\t\tcase ICE_SID_FLD_VEC_RSS:\n\t\tcase ICE_SID_FLD_VEC_ACL:\n\t\tcase ICE_SID_FLD_VEC_PE:\n\t\t\tes = sect;\n\t\t\tsrc = (u8 *)es->fv;\n\t\t\tsect_len = (u32)(le16_to_cpu(es->count) *\n\t\t\t\t\t hw->blk[block_id].es.fvw) *\n\t\t\t\tsizeof(*hw->blk[block_id].es.t);\n\t\t\tdst = (u8 *)hw->blk[block_id].es.t;\n\t\t\tdst_len = (u32)(hw->blk[block_id].es.count *\n\t\t\t\t\thw->blk[block_id].es.fvw) *\n\t\t\t\tsizeof(*hw->blk[block_id].es.t);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn;\n\t\t}\n\n\t\t/* if the section offset exceeds destination length, terminate\n\t\t * table fill.\n\t\t */\n\t\tif (offset > dst_len)\n\t\t\treturn;\n\n\t\t/* if the sum of section size and offset exceed destination size\n\t\t * then we are out of bounds of the HW table size for that PF.\n\t\t * Changing section length to fill the remaining table space\n\t\t * of that PF.\n\t\t */\n\t\tif ((offset + sect_len) > dst_len)\n\t\t\tsect_len = dst_len - offset;\n\n\t\tmemcpy(dst + offset, src, sect_len);\n\t\toffset += sect_len;\n\t\tsect = ice_pkg_enum_section(NULL, &state, sid);\n\t}\n}",
        "static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)\n{\n\tstruct nix_lso_format *field;\n\n\tfield = (struct nix_lso_format *)&lso->fields[0];": "static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)\n{\n\tstruct nix_lso_format *field;\n\n\tfield = (struct nix_lso_format *)&lso->fields[0];\n\tlso->field_mask = GENMASK(18, 0);\n\n\t/* IP's Length field */\n\tfield->layer = NIX_TXLAYER_OL3;\n\t/* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */\n\tfield->offset = v4 ? 2 : 4;\n\tfield->sizem1 = 1; /* i.e 2 bytes */\n\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n\tfield++;\n\n\t/* No ID field in IPv6 header */\n\tif (v4) {\n\t\t/* Increment IPID */\n\t\tfield->layer = NIX_TXLAYER_OL3;\n\t\tfield->offset = 4;\n\t\tfield->sizem1 = 1; /* i.e 2 bytes */\n\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n\t\tfield++;\n\t}\n\n\t/* Update length in UDP header */\n\tfield->layer = NIX_TXLAYER_OL4;\n\tfield->offset = 4;\n\tfield->sizem1 = 1;\n\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n}",
        "static int bd957x_probe(struct platform_device *pdev)\n{\n\tint i;\n\tunsigned int num_reg_data;\n\tbool vout_mode, ddr_sel, may_have_irqs = false;": "static int bd957x_probe(struct platform_device *pdev)\n{\n\tint i;\n\tunsigned int num_reg_data;\n\tbool vout_mode, ddr_sel, may_have_irqs = false;\n\tstruct regmap *regmap;\n\tstruct bd957x_data *ic_data;\n\tstruct regulator_config config = { 0 };\n\t/* All regulators are related to UVD and thermal IRQs... */\n\tstruct regulator_dev *rdevs[BD9576_NUM_REGULATORS];\n\t/* ...But VoutS1 is not flagged by OVD IRQ */\n\tstruct regulator_dev *ovd_devs[BD9576_NUM_OVD_REGULATORS];\n\tstatic const struct regulator_irq_desc bd9576_notif_uvd = {\n\t\t.name = \"bd9576-uvd\",\n\t\t.irq_off_ms = 1000,\n\t\t.map_event = bd9576_uvd_handler,\n\t\t.renable = bd9576_uvd_renable,\n\t\t.data = &bd957x_regulators,\n\t};\n\tstatic const struct regulator_irq_desc bd9576_notif_ovd = {\n\t\t.name = \"bd9576-ovd\",\n\t\t.irq_off_ms = 1000,\n\t\t.map_event = bd9576_ovd_handler,\n\t\t.renable = bd9576_ovd_renable,\n\t\t.data = &bd957x_regulators,\n\t};\n\tstatic const struct regulator_irq_desc bd9576_notif_temp = {\n\t\t.name = \"bd9576-temp\",\n\t\t.irq_off_ms = 1000,\n\t\t.map_event = bd9576_thermal_handler,\n\t\t.renable = bd9576_temp_renable,\n\t\t.data = &bd957x_regulators,\n\t};\n\tenum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;\n\n\tnum_reg_data = ARRAY_SIZE(bd957x_regulators.regulator_data);\n\n\tic_data = &bd957x_regulators;\n\n\tregmap = dev_get_regmap(pdev->dev.parent, NULL);\n\tif (!regmap) {\n\t\tdev_err(&pdev->dev, \"No regmap\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tic_data->regmap = regmap;\n\tvout_mode = of_property_read_bool(pdev->dev.parent->of_node,\n\t\t\t\t\t \"rohm,vout1-en-low\");\n\tif (vout_mode) {\n\t\tstruct gpio_desc *en;\n\n\t\tdev_dbg(&pdev->dev, \"GPIO controlled mode\\n\");\n\n\t\t/* VOUT1 enable state judged by VOUT1_EN pin */\n\t\t/* See if we have GPIO defined */\n\t\ten = devm_gpiod_get_from_of_node(&pdev->dev,\n\t\t\t\t\t\t pdev->dev.parent->of_node,\n\t\t\t\t\t\t \"rohm,vout1-en-gpios\", 0,\n\t\t\t\t\t\t GPIOD_OUT_LOW, \"vout1-en\");\n\t\tif (!IS_ERR(en)) {\n\t\t\t/* VOUT1_OPS gpio ctrl */\n\t\t\t/*\n\t\t\t * Regulator core prioritizes the ena_gpio over\n\t\t\t * enable/disable/is_enabled callbacks so no need to\n\t\t\t * clear them. We can still use same ops\n\t\t\t */\n\t\t\tconfig.ena_gpiod = en;\n\t\t} else {\n\t\t\t/*\n\t\t\t * In theory it is possible someone wants to set\n\t\t\t * vout1-en LOW during OTP loading and set VOUT1 to be\n\t\t\t * controlled by GPIO - but control the GPIO from some\n\t\t\t * where else than this driver. For that to work we\n\t\t\t * should unset the is_enabled callback here.\n\t\t\t *\n\t\t\t * I believe such case where rohm,vout1-en-low is set\n\t\t\t * and vout1-en-gpios is not is likely to be a\n\t\t\t * misconfiguration. So let's just err out for now.\n\t\t\t */\n\t\t\tdev_err(&pdev->dev,\n\t\t\t\t\"Failed to get VOUT1 control GPIO\\n\");\n\t\t\treturn PTR_ERR(en);\n\t\t}\n\t}\n\n\t/*\n\t * If more than one PMIC needs to be controlled by same processor then\n\t * allocate the regulator data array here and use bd9576_regulators as\n\t * template. At the moment I see no such use-case so I spare some\n\t * bytes and use bd9576_regulators directly for non-constant configs\n\t * like DDR voltage selection.\n\t */\n\tplatform_set_drvdata(pdev, ic_data);\n\tddr_sel =  of_property_read_bool(pdev->dev.parent->of_node,\n\t\t\t\t\t \"rohm,ddr-sel-low\");\n\tif (ddr_sel)\n\t\tic_data->regulator_data[2].desc.fixed_uV = 1350000;\n\telse\n\t\tic_data->regulator_data[2].desc.fixed_uV = 1500000;\n\n\tswitch (chip) {\n\tcase ROHM_CHIP_TYPE_BD9576:\n\t\tmay_have_irqs = true;\n\t\tdev_dbg(&pdev->dev, \"Found BD9576MUF\\n\");\n\t\tbreak;\n\tcase ROHM_CHIP_TYPE_BD9573:\n\t\tdev_dbg(&pdev->dev, \"Found BD9573MUF\\n\");\n\t\tbreak;\n\tdefault:\n\t\tdev_err(&pdev->dev, \"Unsupported chip type\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < num_reg_data; i++) {\n\t\tstruct regulator_desc *d;\n\n\t\td = &ic_data->regulator_data[i].desc;\n\n\n\t\tif (may_have_irqs) {\n\t\t\tif (d->id >= ARRAY_SIZE(bd9576_ops_arr))\n\t\t\t\treturn -EINVAL;\n\n\t\t\td->ops = bd9576_ops_arr[d->id];\n\t\t} else {\n\t\t\tif (d->id >= ARRAY_SIZE(bd9573_ops_arr))\n\t\t\t\treturn -EINVAL;\n\n\t\t\td->ops = bd9573_ops_arr[d->id];\n\t\t}\n\t}\n\n\tconfig.dev = pdev->dev.parent;\n\tconfig.regmap = regmap;\n\tconfig.driver_data = ic_data;\n\n\tfor (i = 0; i < num_reg_data; i++) {\n\n\t\tstruct bd957x_regulator_data *r = &ic_data->regulator_data[i];\n\t\tconst struct regulator_desc *desc = &r->desc;\n\n\t\tr->rdev = devm_regulator_register(&pdev->dev, desc,\n\t\t\t\t\t\t\t   &config);\n\t\tif (IS_ERR(r->rdev)) {\n\t\t\tdev_err(&pdev->dev,\n\t\t\t\t\"failed to register %s regulator\\n\",\n\t\t\t\tdesc->name);\n\t\t\treturn PTR_ERR(r->rdev);\n\t\t}\n\t\t/*\n\t\t * Clear the VOUT1 GPIO setting - rest of the regulators do not\n\t\t * support GPIO control\n\t\t */\n\t\tconfig.ena_gpiod = NULL;\n\n\t\tif (!may_have_irqs)\n\t\t\tcontinue;\n\n\t\trdevs[i] = r->rdev;\n\t\tif (i < BD957X_VOUTS1)\n\t\t\tovd_devs[i] = r->rdev;\n\t}\n\tif (may_have_irqs) {\n\t\tvoid *ret;\n\t\t/*\n\t\t * We can add both the possible error and warning flags here\n\t\t * because the core uses these only for status clearing and\n\t\t * if we use warnings - errors are always clear and the other\n\t\t * way around. We can also add CURRENT flag for all regulators\n\t\t * because it is never set if it is not supported. Same applies\n\t\t * to setting UVD for VoutS1 - it is not accidentally cleared\n\t\t * as it is never set.\n\t\t */\n\t\tint uvd_errs = REGULATOR_ERROR_UNDER_VOLTAGE |\n\t\t\t       REGULATOR_ERROR_UNDER_VOLTAGE_WARN |\n\t\t\t       REGULATOR_ERROR_OVER_CURRENT |\n\t\t\t       REGULATOR_ERROR_OVER_CURRENT_WARN;\n\t\tint ovd_errs = REGULATOR_ERROR_OVER_VOLTAGE_WARN |\n\t\t\t       REGULATOR_ERROR_REGULATION_OUT;\n\t\tint temp_errs = REGULATOR_ERROR_OVER_TEMP |\n\t\t\t\tREGULATOR_ERROR_OVER_TEMP_WARN;\n\t\tint irq;\n\n\t\tirq = platform_get_irq_byname(pdev, \"bd9576-uvd\");\n\n\t\t/* Register notifiers - can fail if IRQ is not given */\n\t\tret = devm_regulator_irq_helper(&pdev->dev, &bd9576_notif_uvd,\n\t\t\t\t\t\tirq, 0, uvd_errs, NULL,\n\t\t\t\t\t\t&rdevs[0],\n\t\t\t\t\t\tBD9576_NUM_REGULATORS);\n\t\tif (IS_ERR(ret)) {\n\t\t\tif (PTR_ERR(ret) == -EPROBE_DEFER)\n\t\t\t\treturn -EPROBE_DEFER;\n\n\t\t\tdev_warn(&pdev->dev, \"UVD disabled %pe\\n\", ret);\n\t\t}\n\n\t\tirq = platform_get_irq_byname(pdev, \"bd9576-ovd\");\n\n\t\tret = devm_regulator_irq_helper(&pdev->dev, &bd9576_notif_ovd,\n\t\t\t\t\t\tirq, 0, ovd_errs, NULL,\n\t\t\t\t\t\t&ovd_devs[0],\n\t\t\t\t\t\tBD9576_NUM_OVD_REGULATORS);\n\t\tif (IS_ERR(ret)) {\n\t\t\tif (PTR_ERR(ret) == -EPROBE_DEFER)\n\t\t\t\treturn -EPROBE_DEFER;\n\n\t\t\tdev_warn(&pdev->dev, \"OVD disabled %pe\\n\", ret);\n\t\t}\n\t\tirq = platform_get_irq_byname(pdev, \"bd9576-temp\");\n\n\t\tret = devm_regulator_irq_helper(&pdev->dev, &bd9576_notif_temp,\n\t\t\t\t\t\tirq, 0, temp_errs, NULL,\n\t\t\t\t\t\t&rdevs[0],\n\t\t\t\t\t\tBD9576_NUM_REGULATORS);\n\t\tif (IS_ERR(ret)) {\n\t\t\tif (PTR_ERR(ret) == -EPROBE_DEFER)\n\t\t\t\treturn -EPROBE_DEFER;\n\n\t\t\tdev_warn(&pdev->dev, \"Thermal warning disabled %pe\\n\",\n\t\t\t\t ret);\n\t\t}\n\t}\n\treturn 0;\n}",
        "static void test_sethwdebug_range_unaligned(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info;\n\tunsigned long wp_addr;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW UNALIGNED\";": "static void test_sethwdebug_range_unaligned(pid_t child_pid)\n{\n\tstruct ppc_hw_breakpoint info;\n\tunsigned long wp_addr;\n\tchar *name = \"PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW UNALIGNED\";\n\tint len;\n\tint wh;\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW UNALIGNED, WO test */\n\twp_addr = (unsigned long)&gstruct.b;\n\tlen = B_LEN;\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_WRITE, wp_addr, len);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"WO\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW UNALIGNED, RO test */\n\twp_addr = (unsigned long)&gstruct.b;\n\tlen = B_LEN;\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_READ, wp_addr, len);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RO\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n\t/* PPC_PTRACE_SETHWDEBUG, MODE_RANGE, DW UNALIGNED, RW test */\n\twp_addr = (unsigned long)&gstruct.b;\n\tlen = B_LEN;\n\tget_ppc_hw_breakpoint(&info, PPC_BREAKPOINT_TRIGGER_RW, wp_addr, len);\n\twh = ptrace_sethwdebug(child_pid, &info);\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(child_pid, name, \"RW\", wp_addr, len);\n\tptrace_delhwdebug(child_pid, wh);\n\n}",
        "static int stat_put(struct sk_buff *skb, u16 attrtype, u64 val)\n{\n\tstruct nlattr *nest;\n\tint ret;\n": "static int stat_put(struct sk_buff *skb, u16 attrtype, u64 val)\n{\n\tstruct nlattr *nest;\n\tint ret;\n\n\tif (val == ETHTOOL_STAT_NOT_SET)\n\t\treturn 0;\n\n\t/* We want to start stats attr types from 0, so we don't have a type\n\t * for pad inside ETHTOOL_A_STATS_GRP_STAT. Pad things on the outside\n\t * of ETHTOOL_A_STATS_GRP_STAT. Since we're one nest away from the\n\t * actual attr we're 4B off - nla_need_padding_for_64bit() & co.\n\t * can't be used.\n\t */\n#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n\tif (!IS_ALIGNED((unsigned long)skb_tail_pointer(skb), 8))\n\t\tif (!nla_reserve(skb, ETHTOOL_A_STATS_GRP_PAD, 0))\n\t\t\treturn -EMSGSIZE;\n#endif\n\n\tnest = nla_nest_start(skb, ETHTOOL_A_STATS_GRP_STAT);\n\tif (!nest)\n\t\treturn -EMSGSIZE;\n\n\tret = nla_put_u64_64bit(skb, attrtype, val, -1 /* not used */);\n\tif (ret) {\n\t\tnla_nest_cancel(skb, nest);\n\t\treturn ret;\n\t}\n\n\tnla_nest_end(skb, nest);\n\treturn 0;\n}",
        "static void cmpk_handle_tx_feedback(struct net_device *dev, u8 *pmsg)\n{\n\tstruct r8192_priv *priv = ieee80211_priv(dev);\n\tstruct cmd_pkt_tx_feedback rx_tx_fb;\n": "static void cmpk_handle_tx_feedback(struct net_device *dev, u8 *pmsg)\n{\n\tstruct r8192_priv *priv = ieee80211_priv(dev);\n\tstruct cmd_pkt_tx_feedback rx_tx_fb;\n\n\tpriv->stats.txfeedback++;\n\n\t/* 1. Extract TX feedback info from RFD to temp structure buffer. */\n\t/* It seems that FW use big endian(MIPS) and DRV use little endian in\n\t * windows OS. So we have to read the content byte by byte or transfer\n\t * endian type before copy the message copy.\n\t */\n\t/* Use pointer to transfer structure memory. */\n\tmemcpy((u8 *)&rx_tx_fb, pmsg, sizeof(struct cmd_pkt_tx_feedback));\n\t/* 2. Use tx feedback info to count TX statistics. */\n\tcmpk_count_txstatistic(dev, &rx_tx_fb);\n\t/* Comment previous method for TX statistic function. */\n\t/* Collect info TX feedback packet to fill TCB. */\n\t/* We can not know the packet length and transmit type: broadcast or uni\n\t * or multicast.\n\t */\n}",
        "static void test_gfpzero(struct kunit *test)\n{\n\tconst size_t size = PAGE_SIZE; /* PAGE_SIZE so we can use ALLOCATE_ANY. */\n\tchar *buf1, *buf2;\n\tint i;": "static void test_gfpzero(struct kunit *test)\n{\n\tconst size_t size = PAGE_SIZE; /* PAGE_SIZE so we can use ALLOCATE_ANY. */\n\tchar *buf1, *buf2;\n\tint i;\n\n\t/* Skip if we think it'd take too long. */\n\tKFENCE_TEST_REQUIRES(test, kfence_sample_interval <= 100);\n\n\tsetup_test_cache(test, size, 0, NULL);\n\tbuf1 = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY);\n\tfor (i = 0; i < size; i++)\n\t\tbuf1[i] = i + 1;\n\ttest_free(buf1);\n\n\t/* Try to get same address again -- this can take a while. */\n\tfor (i = 0;; i++) {\n\t\tbuf2 = test_alloc(test, size, GFP_KERNEL | __GFP_ZERO, ALLOCATE_ANY);\n\t\tif (buf1 == buf2)\n\t\t\tbreak;\n\t\ttest_free(buf2);\n\n\t\tif (kthread_should_stop() || (i == CONFIG_KFENCE_NUM_OBJECTS)) {\n\t\t\tkunit_warn(test, \"giving up ... cannot get same object back\\n\");\n\t\t\treturn;\n\t\t}\n\t\tcond_resched();\n\t}\n\n\tfor (i = 0; i < size; i++)\n\t\tKUNIT_EXPECT_EQ(test, buf2[i], (char)0);\n\n\ttest_free(buf2);\n\n\tKUNIT_EXPECT_FALSE(test, report_available());\n}",
        "static int lock_torture_reader(void *arg)\n{\n\tstruct lock_stress_stats *lrsp = arg;\n\tint tid = lrsp - cxt.lrsa;\n\tDEFINE_TORTURE_RANDOM(rand);": "static int lock_torture_reader(void *arg)\n{\n\tstruct lock_stress_stats *lrsp = arg;\n\tint tid = lrsp - cxt.lrsa;\n\tDEFINE_TORTURE_RANDOM(rand);\n\n\tVERBOSE_TOROUT_STRING(\"lock_torture_reader task started\");\n\tset_user_nice(current, MAX_NICE);\n\n\tdo {\n\t\tif ((torture_random(&rand) & 0xfffff) == 0)\n\t\t\tschedule_timeout_uninterruptible(1);\n\n\t\tcxt.cur_ops->readlock(tid);\n\t\tatomic_inc(&lock_is_read_held);\n\t\tif (WARN_ON_ONCE(lock_is_write_held))\n\t\t\tlrsp->n_lock_fail++; /* rare, but... */\n\n\t\tlrsp->n_lock_acquired++;\n\t\tcxt.cur_ops->read_delay(&rand);\n\t\tatomic_dec(&lock_is_read_held);\n\t\tcxt.cur_ops->readunlock(tid);\n\n\t\tstutter_wait(\"lock_torture_reader\");\n\t} while (!torture_must_stop());\n\ttorture_kthread_stopping(\"lock_torture_reader\");\n\treturn 0;\n}",
        "static int bd9576_renable(struct regulator_irq_data *rid, int reg, int mask)\n{\n\tint val, ret;\n\tstruct bd957x_data *d = (struct bd957x_data *)rid->data;\n": "static int bd9576_renable(struct regulator_irq_data *rid, int reg, int mask)\n{\n\tint val, ret;\n\tstruct bd957x_data *d = (struct bd957x_data *)rid->data;\n\n\tret = regmap_read(d->regmap, reg, &val);\n\tif (ret)\n\t\treturn REGULATOR_FAILED_RETRY;\n\n\tif (rid->opaque && rid->opaque == (val & mask)) {\n\t\t/*\n\t\t * It seems we stil have same status. Ack and return\n\t\t * information that we are still out of limits and core\n\t\t * should not enable IRQ\n\t\t */\n\t\tregmap_write(d->regmap, reg, mask & val);\n\t\treturn REGULATOR_ERROR_ON;\n\t}\n\trid->opaque = 0;\n\t/*\n\t * Status was changed. Either prolem was solved or we have new issues.\n\t * Let's re-enable IRQs and be prepared to report problems again\n\t */\n\treturn REGULATOR_ERROR_CLEARED;\n}",
        "static int inv_icm42600_i2c_bus_setup(struct inv_icm42600_state *st)\n{\n\tunsigned int mask, val;\n\tint ret;\n": "static int inv_icm42600_i2c_bus_setup(struct inv_icm42600_state *st)\n{\n\tunsigned int mask, val;\n\tint ret;\n\n\t/*\n\t * setup interface registers\n\t * This register write to REG_INTF_CONFIG6 enables a spike filter that\n\t * is impacting the line and can prevent the I2C ACK to be seen by the\n\t * controller. So we don't test the return value.\n\t */\n\tregmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG6,\n\t\t\t   INV_ICM42600_INTF_CONFIG6_MASK,\n\t\t\t   INV_ICM42600_INTF_CONFIG6_I3C_EN);\n\n\tret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG4,\n\t\t\t\t INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY, 0);\n\tif (ret)\n\t\treturn ret;\n\n\t/* set slew rates for I2C and SPI */\n\tmask = INV_ICM42600_DRIVE_CONFIG_I2C_MASK |\n\t       INV_ICM42600_DRIVE_CONFIG_SPI_MASK;\n\tval = INV_ICM42600_DRIVE_CONFIG_I2C(INV_ICM42600_SLEW_RATE_12_36NS) |\n\t      INV_ICM42600_DRIVE_CONFIG_SPI(INV_ICM42600_SLEW_RATE_12_36NS);\n\tret = regmap_update_bits(st->map, INV_ICM42600_REG_DRIVE_CONFIG,\n\t\t\t\t mask, val);\n\tif (ret)\n\t\treturn ret;\n\n\t/* disable SPI bus */\n\treturn regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG0,\n\t\t\t\t  INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK,\n\t\t\t\t  INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS);\n}",
        "static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)\n{\n\tif (enable) {\n\t\t/* Enable SSPD, STDI and CP locked/unlocked interrupts */\n\t\tio_write(sd, 0x46, 0x9c);": "static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)\n{\n\tif (enable) {\n\t\t/* Enable SSPD, STDI and CP locked/unlocked interrupts */\n\t\tio_write(sd, 0x46, 0x9c);\n\t\t/* ESDP_50HZ_DET interrupt */\n\t\tio_write(sd, 0x5a, 0x10);\n\t\t/* Enable CABLE_DET_A/B_ST (+5v) interrupt */\n\t\tio_write(sd, 0x73, 0x03);\n\t\t/* Enable V_LOCKED and DE_REGEN_LCK interrupts */\n\t\tio_write(sd, 0x78, 0x03);\n\t\t/* Enable SDP Standard Detection Change and SDP Video Detected */\n\t\tio_write(sd, 0xa0, 0x09);\n\t\t/* Enable HDMI_MODE interrupt */\n\t\tio_write(sd, 0x69, 0x08);\n\t} else {\n\t\tio_write(sd, 0x46, 0x0);\n\t\tio_write(sd, 0x5a, 0x0);\n\t\tio_write(sd, 0x73, 0x0);\n\t\tio_write(sd, 0x78, 0x0);\n\t\tio_write(sd, 0xa0, 0x0);\n\t\tio_write(sd, 0x69, 0x0);\n\t}\n}",
        "static int attach_meter(struct dp_meter_table *tbl, struct dp_meter *meter)\n{\n\tstruct dp_meter_instance *ti = rcu_dereference_ovsl(tbl->ti);\n\tu32 hash = meter_hash(ti, meter->id);\n\tint err;": "static int attach_meter(struct dp_meter_table *tbl, struct dp_meter *meter)\n{\n\tstruct dp_meter_instance *ti = rcu_dereference_ovsl(tbl->ti);\n\tu32 hash = meter_hash(ti, meter->id);\n\tint err;\n\n\t/* In generally, slots selected should be empty, because\n\t * OvS uses id-pool to fetch a available id.\n\t */\n\tif (unlikely(rcu_dereference_ovsl(ti->dp_meters[hash])))\n\t\treturn -EBUSY;\n\n\tdp_meter_instance_insert(ti, meter);\n\n\t/* That function is thread-safe. */\n\ttbl->count++;\n\tif (tbl->count >= tbl->max_meters_allowed) {\n\t\terr = -EFBIG;\n\t\tgoto attach_err;\n\t}\n\n\tif (tbl->count >= ti->n_meters &&\n\t    dp_meter_instance_realloc(tbl, ti->n_meters * 2)) {\n\t\terr = -ENOMEM;\n\t\tgoto attach_err;\n\t}\n\n\treturn 0;\n\nattach_err:\n\tdp_meter_instance_remove(ti, meter);\n\ttbl->count--;\n\treturn err;\n}",
        "static void get_board_id(void *vsd, char *board_id)\n{\n\tint i;\n\n#define VSD_OFFSET_SIG1\t\t0x00": "static void get_board_id(void *vsd, char *board_id)\n{\n\tint i;\n\n#define VSD_OFFSET_SIG1\t\t0x00\n#define VSD_OFFSET_SIG2\t\t0xde\n#define VSD_OFFSET_MLX_BOARD_ID\t0xd0\n#define VSD_OFFSET_TS_BOARD_ID\t0x20\n\n#define VSD_SIGNATURE_TOPSPIN\t0x5ad\n\n\tmemset(board_id, 0, MLX4_BOARD_ID_LEN);\n\n\tif (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&\n\t    be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {\n\t\tstrlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);\n\t} else {\n\t\t/*\n\t\t * The board ID is a string but the firmware byte\n\t\t * swaps each 4-byte word before passing it back to\n\t\t * us.  Therefore we need to swab it before printing.\n\t\t */\n\t\tu32 *bid_u32 = (u32 *)board_id;\n\n\t\tfor (i = 0; i < 4; ++i) {\n\t\t\tu32 *addr;\n\t\t\tu32 val;\n\n\t\t\taddr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4);\n\t\t\tval = get_unaligned(addr);\n\t\t\tval = swab32(val);\n\t\t\tput_unaligned(val, &bid_u32[i]);\n\t\t}\n\t}\n}",
        "static int test_second_attach(struct bpf_object *obj)\n{\n\tconst char *prog_name = \"security_new_get_constant\";\n\tconst char *tgt_name = \"get_constant\";\n\tconst char *tgt_obj_file = \"./test_pkt_access.o\";": "static int test_second_attach(struct bpf_object *obj)\n{\n\tconst char *prog_name = \"security_new_get_constant\";\n\tconst char *tgt_name = \"get_constant\";\n\tconst char *tgt_obj_file = \"./test_pkt_access.o\";\n\tstruct bpf_program *prog = NULL;\n\tstruct bpf_object *tgt_obj;\n\tstruct bpf_link *link;\n\tint err = 0, tgt_fd;\n\tLIBBPF_OPTS(bpf_test_run_opts, topts,\n\t\t.data_in = &pkt_v6,\n\t\t.data_size_in = sizeof(pkt_v6),\n\t\t.repeat = 1,\n\t);\n\n\tprog = bpf_object__find_program_by_name(obj, prog_name);\n\tif (!ASSERT_OK_PTR(prog, \"find_prog\"))\n\t\treturn -ENOENT;\n\n\terr = bpf_prog_test_load(tgt_obj_file, BPF_PROG_TYPE_UNSPEC,\n\t\t\t    &tgt_obj, &tgt_fd);\n\tif (!ASSERT_OK(err, \"second_prog_load\"))\n\t\treturn err;\n\n\tlink = bpf_program__attach_freplace(prog, tgt_fd, tgt_name);\n\tif (!ASSERT_OK_PTR(link, \"second_link\"))\n\t\tgoto out;\n\n\terr = bpf_prog_test_run_opts(tgt_fd, &topts);\n\tif (!ASSERT_OK(err, \"ipv6 test_run\"))\n\t\tgoto out;\n\tif (!ASSERT_OK(topts.retval, \"ipv6 retval\"))\n\t\tgoto out;\n\n\terr = check_data_map(obj, 1, true);\n\tif (err)\n\t\tgoto out;\n\nout:\n\tbpf_link__destroy(link);\n\tbpf_object__close(tgt_obj);\n\treturn err;\n}",
        "static int pvr_altera_load(struct bttv *btv, const u8 *micro, u32 microlen)\n{\n\tu32 n;\n\tu8 bits;\n\tint i;": "static int pvr_altera_load(struct bttv *btv, const u8 *micro, u32 microlen)\n{\n\tu32 n;\n\tu8 bits;\n\tint i;\n\n\tgpio_inout(0xffffff,BTTV_ALT_DATA|BTTV_ALT_DCLK|BTTV_ALT_NCONFIG);\n\tgpio_write(0);\n\tudelay(PVR_GPIO_DELAY);\n\n\tgpio_write(BTTV_ALT_NCONFIG);\n\tudelay(PVR_GPIO_DELAY);\n\n\tfor (n = 0; n < microlen; n++) {\n\t\tbits = micro[n];\n\t\tfor (i = 0 ; i < 8 ; i++) {\n\t\t\tgpio_bits(BTTV_ALT_DCLK,0);\n\t\t\tif (bits & 0x01)\n\t\t\t\tgpio_bits(BTTV_ALT_DATA,BTTV_ALT_DATA);\n\t\t\telse\n\t\t\t\tgpio_bits(BTTV_ALT_DATA,0);\n\t\t\tgpio_bits(BTTV_ALT_DCLK,BTTV_ALT_DCLK);\n\t\t\tbits >>= 1;\n\t\t}\n\t}\n\tgpio_bits(BTTV_ALT_DCLK,0);\n\tudelay(PVR_GPIO_DELAY);\n\n\t/* begin Altera init loop (Not necessary,but doesn't hurt) */\n\tfor (i = 0 ; i < 30 ; i++) {\n\t\tgpio_bits(BTTV_ALT_DCLK,0);\n\t\tgpio_bits(BTTV_ALT_DCLK,BTTV_ALT_DCLK);\n\t}\n\tgpio_bits(BTTV_ALT_DCLK,0);\n\treturn 0;\n}",
        "static int dsa_tag_8021q_port_setup(struct dsa_switch *ds, int port)\n{\n\tstruct dsa_8021q_context *ctx = ds->tag_8021q_ctx;\n\tstruct dsa_port *dp = dsa_to_port(ds, port);\n\tu16 vid = dsa_tag_8021q_standalone_vid(dp);": "static int dsa_tag_8021q_port_setup(struct dsa_switch *ds, int port)\n{\n\tstruct dsa_8021q_context *ctx = ds->tag_8021q_ctx;\n\tstruct dsa_port *dp = dsa_to_port(ds, port);\n\tu16 vid = dsa_tag_8021q_standalone_vid(dp);\n\tstruct net_device *master;\n\tint err;\n\n\t/* The CPU port is implicitly configured by\n\t * configuring the front-panel ports\n\t */\n\tif (!dsa_port_is_user(dp))\n\t\treturn 0;\n\n\tmaster = dp->cpu_dp->master;\n\n\terr = dsa_port_tag_8021q_vlan_add(dp, vid, false);\n\tif (err) {\n\t\tdev_err(ds->dev,\n\t\t\t\"Failed to apply standalone VID %d to port %d: %pe\\n\",\n\t\t\tvid, port, ERR_PTR(err));\n\t\treturn err;\n\t}\n\n\t/* Add the VLAN to the master's RX filter. */\n\tvlan_vid_add(master, ctx->proto, vid);\n\n\treturn err;\n}",
        "static struct recv_frame *portctrl(struct adapter *adapter, struct recv_frame *precv_frame)\n{\n\tu8   *psta_addr, *ptr;\n\tuint  auth_alg;\n\tstruct recv_frame *pfhdr;": "static struct recv_frame *portctrl(struct adapter *adapter, struct recv_frame *precv_frame)\n{\n\tu8   *psta_addr, *ptr;\n\tuint  auth_alg;\n\tstruct recv_frame *pfhdr;\n\tstruct sta_info *psta;\n\tstruct sta_priv *pstapriv;\n\tstruct recv_frame *prtnframe;\n\tu16 ether_type = 0;\n\tu16  eapol_type = 0x888e;/* for Funia BD's WPA issue */\n\tstruct rx_pkt_attrib *pattrib;\n\t__be16 be_tmp;\n\n\tpstapriv = &adapter->stapriv;\n\n\tauth_alg = adapter->securitypriv.dot11AuthAlgrthm;\n\n\tptr = precv_frame->rx_data;\n\tpfhdr = precv_frame;\n\tpattrib = &pfhdr->attrib;\n\tpsta_addr = pattrib->ta;\n\n\tprtnframe = NULL;\n\n\tpsta = rtw_get_stainfo(pstapriv, psta_addr);\n\n\tif (auth_alg == 2) {\n\t\tif (psta && psta->ieee8021x_blocked) {\n\t\t\t/* blocked */\n\t\t\t/* only accept EAPOL frame */\n\t\t\tprtnframe = precv_frame;\n\n\t\t\t/* get ether_type */\n\t\t\tptr = ptr + pfhdr->attrib.hdrlen + pfhdr->attrib.iv_len + LLC_HEADER_SIZE;\n\t\t\tmemcpy(&be_tmp, ptr, 2);\n\t\t\tether_type = ntohs(be_tmp);\n\n\t\t\tif (ether_type == eapol_type) {\n\t\t\t\tprtnframe = precv_frame;\n\t\t\t} else {\n\t\t\t\t/* free this frame */\n\t\t\t\trtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue);\n\t\t\t\tprtnframe = NULL;\n\t\t\t}\n\t\t} else {\n\t\t\t/* allowed */\n\t\t\t/* check decryption status, and decrypt the frame if needed */\n\t\t\tprtnframe = precv_frame;\n\t\t}\n\t} else {\n\t\tprtnframe = precv_frame;\n\t}\n\n\treturn prtnframe;\n}",
        "static int sdw_handle_slave_alerts(struct sdw_slave *slave)\n{\n\tstruct sdw_slave_intr_status slave_intr;\n\tu8 clear = 0, bit, port_status[15] = {0};\n\tint port_num, stat, ret, count = 0;": "static int sdw_handle_slave_alerts(struct sdw_slave *slave)\n{\n\tstruct sdw_slave_intr_status slave_intr;\n\tu8 clear = 0, bit, port_status[15] = {0};\n\tint port_num, stat, ret, count = 0;\n\tunsigned long port;\n\tbool slave_notify;\n\tu8 sdca_cascade = 0;\n\tu8 buf, buf2[2], _buf, _buf2[2];\n\tbool parity_check;\n\tbool parity_quirk;\n\n\tsdw_modify_slave_status(slave, SDW_SLAVE_ALERT);\n\n\tret = pm_runtime_resume_and_get(&slave->dev);\n\tif (ret < 0 && ret != -EACCES) {\n\t\tdev_err(&slave->dev, \"Failed to resume device: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\t/* Read Intstat 1, Intstat 2 and Intstat 3 registers */\n\tret = sdw_read_no_pm(slave, SDW_SCP_INT1);\n\tif (ret < 0) {\n\t\tdev_err(&slave->dev,\n\t\t\t\"SDW_SCP_INT1 read failed:%d\\n\", ret);\n\t\tgoto io_err;\n\t}\n\tbuf = ret;\n\n\tret = sdw_nread_no_pm(slave, SDW_SCP_INTSTAT2, 2, buf2);\n\tif (ret < 0) {\n\t\tdev_err(&slave->dev,\n\t\t\t\"SDW_SCP_INT2/3 read failed:%d\\n\", ret);\n\t\tgoto io_err;\n\t}\n\n\tif (slave->prop.is_sdca) {\n\t\tret = sdw_read_no_pm(slave, SDW_DP0_INT);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&slave->dev,\n\t\t\t\t\"SDW_DP0_INT read failed:%d\\n\", ret);\n\t\t\tgoto io_err;\n\t\t}\n\t\tsdca_cascade = ret & SDW_DP0_SDCA_CASCADE;\n\t}\n\n\tdo {\n\t\tslave_notify = false;\n\n\t\t/*\n\t\t * Check parity, bus clash and Slave (impl defined)\n\t\t * interrupt\n\t\t */\n\t\tif (buf & SDW_SCP_INT1_PARITY) {\n\t\t\tparity_check = slave->prop.scp_int1_mask & SDW_SCP_INT1_PARITY;\n\t\t\tparity_quirk = !slave->first_interrupt_done &&\n\t\t\t\t(slave->prop.quirks & SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY);\n\n\t\t\tif (parity_check && !parity_quirk)\n\t\t\t\tdev_err(&slave->dev, \"Parity error detected\\n\");\n\t\t\tclear |= SDW_SCP_INT1_PARITY;\n\t\t}\n\n\t\tif (buf & SDW_SCP_INT1_BUS_CLASH) {\n\t\t\tif (slave->prop.scp_int1_mask & SDW_SCP_INT1_BUS_CLASH)\n\t\t\t\tdev_err(&slave->dev, \"Bus clash detected\\n\");\n\t\t\tclear |= SDW_SCP_INT1_BUS_CLASH;\n\t\t}\n\n\t\t/*\n\t\t * When bus clash or parity errors are detected, such errors\n\t\t * are unlikely to be recoverable errors.\n\t\t * TODO: In such scenario, reset bus. Make this configurable\n\t\t * via sysfs property with bus reset being the default.\n\t\t */\n\n\t\tif (buf & SDW_SCP_INT1_IMPL_DEF) {\n\t\t\tif (slave->prop.scp_int1_mask & SDW_SCP_INT1_IMPL_DEF) {\n\t\t\t\tdev_dbg(&slave->dev, \"Slave impl defined interrupt\\n\");\n\t\t\t\tslave_notify = true;\n\t\t\t}\n\t\t\tclear |= SDW_SCP_INT1_IMPL_DEF;\n\t\t}\n\n\t\t/* the SDCA interrupts are cleared in the codec driver .interrupt_callback() */\n\t\tif (sdca_cascade)\n\t\t\tslave_notify = true;\n\n\t\t/* Check port 0 - 3 interrupts */\n\t\tport = buf & SDW_SCP_INT1_PORT0_3;\n\n\t\t/* To get port number corresponding to bits, shift it */\n\t\tport = FIELD_GET(SDW_SCP_INT1_PORT0_3, port);\n\t\tfor_each_set_bit(bit, &port, 8) {\n\t\t\tsdw_handle_port_interrupt(slave, bit,\n\t\t\t\t\t\t  &port_status[bit]);\n\t\t}\n\n\t\t/* Check if cascade 2 interrupt is present */\n\t\tif (buf & SDW_SCP_INT1_SCP2_CASCADE) {\n\t\t\tport = buf2[0] & SDW_SCP_INTSTAT2_PORT4_10;\n\t\t\tfor_each_set_bit(bit, &port, 8) {\n\t\t\t\t/* scp2 ports start from 4 */\n\t\t\t\tport_num = bit + 3;\n\t\t\t\tsdw_handle_port_interrupt(slave,\n\t\t\t\t\t\tport_num,\n\t\t\t\t\t\t&port_status[port_num]);\n\t\t\t}\n\t\t}\n\n\t\t/* now check last cascade */\n\t\tif (buf2[0] & SDW_SCP_INTSTAT2_SCP3_CASCADE) {\n\t\t\tport = buf2[1] & SDW_SCP_INTSTAT3_PORT11_14;\n\t\t\tfor_each_set_bit(bit, &port, 8) {\n\t\t\t\t/* scp3 ports start from 11 */\n\t\t\t\tport_num = bit + 10;\n\t\t\t\tsdw_handle_port_interrupt(slave,\n\t\t\t\t\t\tport_num,\n\t\t\t\t\t\t&port_status[port_num]);\n\t\t\t}\n\t\t}\n\n\t\t/* Update the Slave driver */\n\t\tif (slave_notify && slave->ops &&\n\t\t    slave->ops->interrupt_callback) {\n\t\t\tslave_intr.sdca_cascade = sdca_cascade;\n\t\t\tslave_intr.control_port = clear;\n\t\t\tmemcpy(slave_intr.port, &port_status,\n\t\t\t       sizeof(slave_intr.port));\n\n\t\t\tslave->ops->interrupt_callback(slave, &slave_intr);\n\t\t}\n\n\t\t/* Ack interrupt */\n\t\tret = sdw_write_no_pm(slave, SDW_SCP_INT1, clear);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&slave->dev,\n\t\t\t\t\"SDW_SCP_INT1 write failed:%d\\n\", ret);\n\t\t\tgoto io_err;\n\t\t}\n\n\t\t/* at this point all initial interrupt sources were handled */\n\t\tslave->first_interrupt_done = true;\n\n\t\t/*\n\t\t * Read status again to ensure no new interrupts arrived\n\t\t * while servicing interrupts.\n\t\t */\n\t\tret = sdw_read_no_pm(slave, SDW_SCP_INT1);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&slave->dev,\n\t\t\t\t\"SDW_SCP_INT1 recheck read failed:%d\\n\", ret);\n\t\t\tgoto io_err;\n\t\t}\n\t\t_buf = ret;\n\n\t\tret = sdw_nread_no_pm(slave, SDW_SCP_INTSTAT2, 2, _buf2);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&slave->dev,\n\t\t\t\t\"SDW_SCP_INT2/3 recheck read failed:%d\\n\", ret);\n\t\t\tgoto io_err;\n\t\t}\n\n\t\tif (slave->prop.is_sdca) {\n\t\t\tret = sdw_read_no_pm(slave, SDW_DP0_INT);\n\t\t\tif (ret < 0) {\n\t\t\t\tdev_err(&slave->dev,\n\t\t\t\t\t\"SDW_DP0_INT recheck read failed:%d\\n\", ret);\n\t\t\t\tgoto io_err;\n\t\t\t}\n\t\t\tsdca_cascade = ret & SDW_DP0_SDCA_CASCADE;\n\t\t}\n\n\t\t/*\n\t\t * Make sure no interrupts are pending, but filter to limit loop\n\t\t * to interrupts identified in the first status read\n\t\t */\n\t\tbuf &= _buf;\n\t\tbuf2[0] &= _buf2[0];\n\t\tbuf2[1] &= _buf2[1];\n\t\tstat = buf || buf2[0] || buf2[1] || sdca_cascade;\n\n\t\t/*\n\t\t * Exit loop if Slave is continuously in ALERT state even\n\t\t * after servicing the interrupt multiple times.\n\t\t */\n\t\tcount++;\n\n\t\t/* we can get alerts while processing so keep retrying */\n\t} while (stat != 0 && count < SDW_READ_INTR_CLEAR_RETRY);\n\n\tif (count == SDW_READ_INTR_CLEAR_RETRY)\n\t\tdev_warn(&slave->dev, \"Reached MAX_RETRY on alert read\\n\");\n\nio_err:\n\tpm_runtime_mark_last_busy(&slave->dev);\n\tpm_runtime_put_autosuspend(&slave->dev);\n\n\treturn ret;\n}",
        "static int pucan_set_std_filter(struct peak_canfd_priv *priv, u8 row, u32 mask)\n{\n\tstruct pucan_std_filter *cmd;\n\n\tcmd = pucan_add_cmd(pucan_init_cmd(priv), PUCAN_CMD_SET_STD_FILTER);": "static int pucan_set_std_filter(struct peak_canfd_priv *priv, u8 row, u32 mask)\n{\n\tstruct pucan_std_filter *cmd;\n\n\tcmd = pucan_add_cmd(pucan_init_cmd(priv), PUCAN_CMD_SET_STD_FILTER);\n\n\t/* all the 11-bits CAN ID values are represented by one bit in a\n\t * 64 rows array of 32 bits: the upper 6 bits of the CAN ID select the\n\t * row while the lowest 5 bits select the bit in that row.\n\t *\n\t * bit\tfilter\n\t * 1\tpassed\n\t * 0\tdiscarded\n\t */\n\n\t/* select the row */\n\tcmd->idx = row;\n\n\t/* set/unset bits in the row */\n\tcmd->mask = cpu_to_le32(mask);\n\n\treturn pucan_write_cmd(priv);\n}",
        "static int mtdswap_show(struct seq_file *s, void *data)\n{\n\tstruct mtdswap_dev *d = (struct mtdswap_dev *) s->private;\n\tunsigned long sum;\n\tunsigned int count[MTDSWAP_TREE_CNT];": "static int mtdswap_show(struct seq_file *s, void *data)\n{\n\tstruct mtdswap_dev *d = (struct mtdswap_dev *) s->private;\n\tunsigned long sum;\n\tunsigned int count[MTDSWAP_TREE_CNT];\n\tunsigned int min[MTDSWAP_TREE_CNT];\n\tunsigned int max[MTDSWAP_TREE_CNT];\n\tunsigned int i, cw = 0, cwp = 0, cwecount = 0, bb_cnt, mapped, pages;\n\tuint64_t use_size;\n\tstatic const char * const name[] = {\n\t\t\"clean\", \"used\", \"low\", \"high\", \"dirty\", \"bitflip\", \"failing\"\n\t};\n\n\tmutex_lock(&d->mbd_dev->lock);\n\n\tfor (i = 0; i < MTDSWAP_TREE_CNT; i++) {\n\t\tstruct rb_root *root = &d->trees[i].root;\n\n\t\tif (root->rb_node) {\n\t\t\tcount[i] = d->trees[i].count;\n\t\t\tmin[i] = MTDSWAP_ECNT_MIN(root);\n\t\t\tmax[i] = MTDSWAP_ECNT_MAX(root);\n\t\t} else\n\t\t\tcount[i] = 0;\n\t}\n\n\tif (d->curr_write) {\n\t\tcw = 1;\n\t\tcwp = d->curr_write_pos;\n\t\tcwecount = d->curr_write->erase_count;\n\t}\n\n\tsum = 0;\n\tfor (i = 0; i < d->eblks; i++)\n\t\tsum += d->eb_data[i].erase_count;\n\n\tuse_size = (uint64_t)d->eblks * d->mtd->erasesize;\n\tbb_cnt = mtdswap_badblocks(d->mtd, use_size);\n\n\tmapped = 0;\n\tpages = d->mbd_dev->size;\n\tfor (i = 0; i < pages; i++)\n\t\tif (d->page_data[i] != BLOCK_UNDEF)\n\t\t\tmapped++;\n\n\tmutex_unlock(&d->mbd_dev->lock);\n\n\tfor (i = 0; i < MTDSWAP_TREE_CNT; i++) {\n\t\tif (!count[i])\n\t\t\tcontinue;\n\n\t\tif (min[i] != max[i])\n\t\t\tseq_printf(s, \"%s:\\t%5d erase blocks, erased min %d, \"\n\t\t\t\t\"max %d times\\n\",\n\t\t\t\tname[i], count[i], min[i], max[i]);\n\t\telse\n\t\t\tseq_printf(s, \"%s:\\t%5d erase blocks, all erased %d \"\n\t\t\t\t\"times\\n\", name[i], count[i], min[i]);\n\t}\n\n\tif (bb_cnt)\n\t\tseq_printf(s, \"bad:\\t%5u erase blocks\\n\", bb_cnt);\n\n\tif (cw)\n\t\tseq_printf(s, \"current erase block: %u pages used, %u free, \"\n\t\t\t\"erased %u times\\n\",\n\t\t\tcwp, d->pages_per_eblk - cwp, cwecount);\n\n\tseq_printf(s, \"total erasures: %lu\\n\", sum);\n\n\tseq_puts(s, \"\\n\");\n\n\tseq_printf(s, \"mtdswap_readsect count: %llu\\n\", d->sect_read_count);\n\tseq_printf(s, \"mtdswap_writesect count: %llu\\n\", d->sect_write_count);\n\tseq_printf(s, \"mtdswap_discard count: %llu\\n\", d->discard_count);\n\tseq_printf(s, \"mtd read count: %llu\\n\", d->mtd_read_count);\n\tseq_printf(s, \"mtd write count: %llu\\n\", d->mtd_write_count);\n\tseq_printf(s, \"discarded pages count: %llu\\n\", d->discard_page_count);\n\n\tseq_puts(s, \"\\n\");\n\tseq_printf(s, \"total pages: %u\\n\", pages);\n\tseq_printf(s, \"pages mapped: %u\\n\", mapped);\n\n\treturn 0;\n}",
        "static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tstruct zone_entry *segment;\n\tbool defect_flag;": "static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tstruct zone_entry *segment;\n\tbool defect_flag;\n\tint retval, table_size, disable_cnt, i;\n\tu16 start, end, phy_blk, log_blk, tmp_blk, idx;\n\tu8 extra[MS_EXTRA_SIZE], us1, us2;\n\n\tdev_dbg(rtsx_dev(chip), \"%s: %d\\n\", __func__, seg_no);\n\n\tif (!ms_card->segment) {\n\t\tretval = ms_init_l2p_tbl(chip);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\treturn retval;\n\t}\n\n\tif (ms_card->segment[seg_no].build_flag) {\n\t\tdev_dbg(rtsx_dev(chip), \"l2p table of segment %d has been built\\n\",\n\t\t\tseg_no);\n\t\treturn STATUS_SUCCESS;\n\t}\n\n\tif (seg_no == 0)\n\t\ttable_size = 494;\n\telse\n\t\ttable_size = 496;\n\n\tsegment = &ms_card->segment[seg_no];\n\n\tif (!segment->l2p_table) {\n\t\tsegment->l2p_table = vmalloc(array_size(table_size, 2));\n\t\tif (!segment->l2p_table)\n\t\t\tgoto BUILD_FAIL;\n\t}\n\tmemset((u8 *)(segment->l2p_table), 0xff, array_size(table_size, 2));\n\n\tif (!segment->free_table) {\n\t\tsegment->free_table = vmalloc(array_size(MS_FREE_TABLE_CNT, 2));\n\t\tif (!segment->free_table)\n\t\t\tgoto BUILD_FAIL;\n\t}\n\tmemset((u8 *)(segment->free_table), 0xff, array_size(MS_FREE_TABLE_CNT, 2));\n\n\tstart = (u16)seg_no << 9;\n\tend = (u16)(seg_no + 1) << 9;\n\n\tdisable_cnt = segment->disable_count;\n\n\tsegment->get_index = 0;\n\tsegment->set_index = 0;\n\tsegment->unused_blk_cnt = 0;\n\n\tfor (phy_blk = start; phy_blk < end; phy_blk++) {\n\t\tif (disable_cnt) {\n\t\t\tdefect_flag = false;\n\t\t\tfor (i = 0; i < segment->disable_count; i++) {\n\t\t\t\tif (phy_blk == segment->defect_list[i]) {\n\t\t\t\t\tdefect_flag = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (defect_flag) {\n\t\t\t\tdisable_cnt--;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\tretval = ms_read_extra_data(chip, phy_blk, 0,\n\t\t\t\t\t    extra, MS_EXTRA_SIZE);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tdev_dbg(rtsx_dev(chip), \"read extra data fail\\n\");\n\t\t\tms_set_bad_block(chip, phy_blk);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (seg_no == ms_card->segment_cnt - 1) {\n\t\t\tif (!(extra[1] & NOT_TRANSLATION_TABLE)) {\n\t\t\t\tif (!(chip->card_wp & MS_CARD)) {\n\t\t\t\t\tretval = ms_erase_block(chip, phy_blk);\n\t\t\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\textra[2] = 0xff;\n\t\t\t\t\textra[3] = 0xff;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (!(extra[0] & BLOCK_OK))\n\t\t\tcontinue;\n\t\tif (!(extra[1] & NOT_BOOT_BLOCK))\n\t\t\tcontinue;\n\t\tif ((extra[0] & PAGE_OK) != PAGE_OK)\n\t\t\tcontinue;\n\n\t\tlog_blk = ((u16)extra[2] << 8) | extra[3];\n\n\t\tif (log_blk == 0xFFFF) {\n\t\t\tif (!(chip->card_wp & MS_CARD)) {\n\t\t\t\tretval = ms_erase_block(chip, phy_blk);\n\t\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tms_set_unused_block(chip, phy_blk);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (log_blk < ms_start_idx[seg_no] ||\n\t\t    log_blk >= ms_start_idx[seg_no + 1]) {\n\t\t\tif (!(chip->card_wp & MS_CARD)) {\n\t\t\t\tretval = ms_erase_block(chip, phy_blk);\n\t\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tms_set_unused_block(chip, phy_blk);\n\t\t\tcontinue;\n\t\t}\n\n\t\tidx = log_blk - ms_start_idx[seg_no];\n\n\t\tif (segment->l2p_table[idx] == 0xFFFF) {\n\t\t\tsegment->l2p_table[idx] = phy_blk;\n\t\t\tcontinue;\n\t\t}\n\n\t\tus1 = extra[0] & 0x10;\n\t\ttmp_blk = segment->l2p_table[idx];\n\t\tretval = ms_read_extra_data(chip, tmp_blk, 0,\n\t\t\t\t\t    extra, MS_EXTRA_SIZE);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tcontinue;\n\t\tus2 = extra[0] & 0x10;\n\n\t\t(void)ms_arbitrate_l2p(chip, phy_blk,\n\t\t\t\tlog_blk - ms_start_idx[seg_no], us1, us2);\n\t}\n\n\tsegment->build_flag = 1;\n\n\tdev_dbg(rtsx_dev(chip), \"unused block count: %d\\n\",\n\t\tsegment->unused_blk_cnt);\n\n\t/* Logical Address Confirmation Process */\n\tif (seg_no == ms_card->segment_cnt - 1) {\n\t\tif (segment->unused_blk_cnt < 2)\n\t\t\tchip->card_wp |= MS_CARD;\n\t} else {\n\t\tif (segment->unused_blk_cnt < 1)\n\t\t\tchip->card_wp |= MS_CARD;\n\t}\n\n\tif (chip->card_wp & MS_CARD)\n\t\treturn STATUS_SUCCESS;\n\n\tfor (log_blk = ms_start_idx[seg_no];\n\t     log_blk < ms_start_idx[seg_no + 1]; log_blk++) {\n\t\tidx = log_blk - ms_start_idx[seg_no];\n\t\tif (segment->l2p_table[idx] == 0xFFFF) {\n\t\t\tphy_blk = ms_get_unused_block(chip, seg_no);\n\t\t\tif (phy_blk == 0xFFFF) {\n\t\t\t\tchip->card_wp |= MS_CARD;\n\t\t\t\treturn STATUS_SUCCESS;\n\t\t\t}\n\t\t\tretval = ms_init_page(chip, phy_blk, log_blk, 0, 1);\n\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\tgoto BUILD_FAIL;\n\n\t\t\tsegment->l2p_table[idx] = phy_blk;\n\t\t\tif (seg_no == ms_card->segment_cnt - 1) {\n\t\t\t\tif (segment->unused_blk_cnt < 2) {\n\t\t\t\t\tchip->card_wp |= MS_CARD;\n\t\t\t\t\treturn STATUS_SUCCESS;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (segment->unused_blk_cnt < 1) {\n\t\t\t\t\tchip->card_wp |= MS_CARD;\n\t\t\t\t\treturn STATUS_SUCCESS;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Make boot block be the first normal block */\n\tif (seg_no == 0) {\n\t\tfor (log_blk = 0; log_blk < 494; log_blk++) {\n\t\t\ttmp_blk = segment->l2p_table[log_blk];\n\t\t\tif (tmp_blk < ms_card->boot_block) {\n\t\t\t\tdev_dbg(rtsx_dev(chip), \"Boot block is not the first normal block.\\n\");\n\n\t\t\t\tif (chip->card_wp & MS_CARD)\n\t\t\t\t\tbreak;\n\n\t\t\t\tphy_blk = ms_get_unused_block(chip, 0);\n\t\t\t\tretval = ms_copy_page(chip, tmp_blk, phy_blk,\n\t\t\t\t\t\t      log_blk, 0,\n\t\t\t\t\t\t      ms_card->page_off + 1);\n\t\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\t\treturn STATUS_FAIL;\n\n\t\t\t\tsegment->l2p_table[log_blk] = phy_blk;\n\n\t\t\t\tretval = ms_set_bad_block(chip, tmp_blk);\n\t\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn STATUS_SUCCESS;\n\nBUILD_FAIL:\n\tsegment->build_flag = 0;\n\tvfree(segment->l2p_table);\n\tsegment->l2p_table = NULL;\n\tvfree(segment->free_table);\n\tsegment->free_table = NULL;\n\n\treturn STATUS_FAIL;\n}",
        "static int rt711_sdca_set_fu1e_capture_ctl(struct rt711_sdca_priv *rt711)\n{\n\tint err;\n\tunsigned int ch_l, ch_r;\n": "static int rt711_sdca_set_fu1e_capture_ctl(struct rt711_sdca_priv *rt711)\n{\n\tint err;\n\tunsigned int ch_l, ch_r;\n\n\tch_l = (rt711->fu1e_dapm_mute || rt711->fu1e_mixer_l_mute) ? 0x01 : 0x00;\n\tch_r = (rt711->fu1e_dapm_mute || rt711->fu1e_mixer_r_mute) ? 0x01 : 0x00;\n\n\terr = regmap_write(rt711->regmap,\n\t\t\tSDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E,\n\t\t\tRT711_SDCA_CTL_FU_MUTE, CH_L), ch_l);\n\tif (err < 0)\n\t\treturn err;\n\n\terr = regmap_write(rt711->regmap,\n\t\t\tSDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E,\n\t\t\tRT711_SDCA_CTL_FU_MUTE, CH_R), ch_r);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn 0;\n}",
        "static void ipa_validate_build(void)\n{\n\t/* At one time we assumed a 64-bit build, allowing some do_div()\n\t * calls to be replaced by simple division or modulo operations.\n\t * We currently only perform divide and modulo operations on u32,": "static void ipa_validate_build(void)\n{\n\t/* At one time we assumed a 64-bit build, allowing some do_div()\n\t * calls to be replaced by simple division or modulo operations.\n\t * We currently only perform divide and modulo operations on u32,\n\t * u16, or size_t objects, and of those only size_t has any chance\n\t * of being a 64-bit value.  (It should be guaranteed 32 bits wide\n\t * on a 32-bit build, but there is no harm in verifying that.)\n\t */\n\tBUILD_BUG_ON(!IS_ENABLED(CONFIG_64BIT) && sizeof(size_t) != 4);\n\n\t/* Code assumes the EE ID for the AP is 0 (zeroed structure field) */\n\tBUILD_BUG_ON(GSI_EE_AP != 0);\n\n\t/* There's no point if we have no channels or event rings */\n\tBUILD_BUG_ON(!GSI_CHANNEL_COUNT_MAX);\n\tBUILD_BUG_ON(!GSI_EVT_RING_COUNT_MAX);\n\n\t/* GSI hardware design limits */\n\tBUILD_BUG_ON(GSI_CHANNEL_COUNT_MAX > 32);\n\tBUILD_BUG_ON(GSI_EVT_RING_COUNT_MAX > 31);\n\n\t/* The number of TREs in a transaction is limited by the channel's\n\t * TLV FIFO size.  A transaction structure uses 8-bit fields\n\t * to represents the number of TREs it has allocated and used.\n\t */\n\tBUILD_BUG_ON(GSI_TLV_MAX > U8_MAX);\n\n\t/* This is used as a divisor */\n\tBUILD_BUG_ON(!IPA_AGGR_GRANULARITY);\n\n\t/* Aggregation granularity value can't be 0, and must fit */\n\tBUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY));\n\tBUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) >\n\t\t\tfield_max(AGGR_GRANULARITY_FMASK));\n}",
        "static void encode_request_finish(struct ceph_msg *msg)\n{\n\tvoid *p = msg->front.iov_base;\n\tvoid *const partial_end = p + msg->front.iov_len;\n\tvoid *const end = p + msg->front_alloc_len;": "static void encode_request_finish(struct ceph_msg *msg)\n{\n\tvoid *p = msg->front.iov_base;\n\tvoid *const partial_end = p + msg->front.iov_len;\n\tvoid *const end = p + msg->front_alloc_len;\n\n\tif (CEPH_HAVE_FEATURE(msg->con->peer_features, RESEND_ON_SPLIT)) {\n\t\t/* luminous OSD -- encode features and be done */\n\t\tp = partial_end;\n\t\tceph_encode_64(&p, msg->con->peer_features);\n\t} else {\n\t\tstruct {\n\t\t\tchar spgid[CEPH_ENCODING_START_BLK_LEN +\n\t\t\t\t   CEPH_PGID_ENCODING_LEN + 1];\n\t\t\t__le32 hash;\n\t\t\t__le32 epoch;\n\t\t\t__le32 flags;\n\t\t\tchar reqid[CEPH_ENCODING_START_BLK_LEN +\n\t\t\t\t   sizeof(struct ceph_osd_reqid)];\n\t\t\tchar trace[sizeof(struct ceph_blkin_trace_info)];\n\t\t\t__le32 client_inc;\n\t\t\tstruct ceph_timespec mtime;\n\t\t} __packed head;\n\t\tstruct ceph_pg pgid;\n\t\tvoid *oloc, *oid, *tail;\n\t\tint oloc_len, oid_len, tail_len;\n\t\tint len;\n\n\t\t/*\n\t\t * Pre-luminous OSD -- reencode v8 into v4 using @head\n\t\t * as a temporary buffer.  Encode the raw PG; the rest\n\t\t * is just a matter of moving oloc, oid and tail blobs\n\t\t * around.\n\t\t */\n\t\tmemcpy(&head, p, sizeof(head));\n\t\tp += sizeof(head);\n\n\t\toloc = p;\n\t\tp += CEPH_ENCODING_START_BLK_LEN;\n\t\tpgid.pool = ceph_decode_64(&p);\n\t\tp += 4 + 4; /* preferred, key len */\n\t\tlen = ceph_decode_32(&p);\n\t\tp += len;   /* nspace */\n\t\toloc_len = p - oloc;\n\n\t\toid = p;\n\t\tlen = ceph_decode_32(&p);\n\t\tp += len;\n\t\toid_len = p - oid;\n\n\t\ttail = p;\n\t\ttail_len = partial_end - p;\n\n\t\tp = msg->front.iov_base;\n\t\tceph_encode_copy(&p, &head.client_inc, sizeof(head.client_inc));\n\t\tceph_encode_copy(&p, &head.epoch, sizeof(head.epoch));\n\t\tceph_encode_copy(&p, &head.flags, sizeof(head.flags));\n\t\tceph_encode_copy(&p, &head.mtime, sizeof(head.mtime));\n\n\t\t/* reassert_version */\n\t\tmemset(p, 0, sizeof(struct ceph_eversion));\n\t\tp += sizeof(struct ceph_eversion);\n\n\t\tBUG_ON(p >= oloc);\n\t\tmemmove(p, oloc, oloc_len);\n\t\tp += oloc_len;\n\n\t\tpgid.seed = le32_to_cpu(head.hash);\n\t\tencode_pgid(&p, &pgid); /* raw pg */\n\n\t\tBUG_ON(p >= oid);\n\t\tmemmove(p, oid, oid_len);\n\t\tp += oid_len;\n\n\t\t/* tail -- ops, snapid, snapc, retry_attempt */\n\t\tBUG_ON(p >= tail);\n\t\tmemmove(p, tail, tail_len);\n\t\tp += tail_len;\n\n\t\tmsg->hdr.version = cpu_to_le16(4); /* MOSDOp v4 */\n\t}\n\n\tBUG_ON(p > end);\n\tmsg->front.iov_len = p - msg->front.iov_base;\n\tmsg->hdr.front_len = cpu_to_le32(msg->front.iov_len);\n\n\tdout(\"%s msg %p tid %llu %u+%u+%u v%d\\n\", __func__, msg,\n\t     le64_to_cpu(msg->hdr.tid), le32_to_cpu(msg->hdr.front_len),\n\t     le32_to_cpu(msg->hdr.middle_len), le32_to_cpu(msg->hdr.data_len),\n\t     le16_to_cpu(msg->hdr.version));\n}",
        "static void mchip_vrj_setup(u8 mode)\n{\n\tmchip_set(MCHIP_VRJ_BUS_MODE, 5);\n\tmchip_set(MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL, 0x1f);\n\tmchip_set(MCHIP_VRJ_PDAT_USE, 1);": "static void mchip_vrj_setup(u8 mode)\n{\n\tmchip_set(MCHIP_VRJ_BUS_MODE, 5);\n\tmchip_set(MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL, 0x1f);\n\tmchip_set(MCHIP_VRJ_PDAT_USE, 1);\n\tmchip_set(MCHIP_VRJ_IRQ_FLAG, 0xa0);\n\tmchip_set(MCHIP_VRJ_MODE_SPECIFY, mode);\n\tmchip_set(MCHIP_VRJ_NUM_LINES, mchip_vsize());\n\tmchip_set(MCHIP_VRJ_NUM_PIXELS, mchip_hsize());\n\tmchip_set(MCHIP_VRJ_NUM_COMPONENTS, 0x1b);\n\tmchip_set(MCHIP_VRJ_LIMIT_COMPRESSED_LO, 0xFFFF);\n\tmchip_set(MCHIP_VRJ_LIMIT_COMPRESSED_HI, 0xFFFF);\n\tmchip_set(MCHIP_VRJ_COMP_DATA_FORMAT, 0xC);\n\tmchip_set(MCHIP_VRJ_RESTART_INTERVAL, 0);\n\tmchip_set(MCHIP_VRJ_SOF1, 0x601);\n\tmchip_set(MCHIP_VRJ_SOF2, 0x1502);\n\tmchip_set(MCHIP_VRJ_SOF3, 0x1503);\n\tmchip_set(MCHIP_VRJ_SOF4, 0x1596);\n\tmchip_set(MCHIP_VRJ_SOS, 0x0ed0);\n\n\tmchip_load_tables();\n}",
        "static int mmcr0_fc56_pmc56(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n": "static int mmcr0_fc56_pmc56(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\n\t /* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\n\t/* Init the event for the sampling test */\n\tevent_init_sampling(&event, 0x500fa);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop(10000);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/* Verify that fc56 is not set in MMCR0 when using PMC5 */\n\tFAIL_IF(get_mmcr0_fc56(get_reg_value(intr_regs, \"MMCR0\"), 5));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static void rxrpc_resend(struct rxrpc_call *call, unsigned long now_j)\n{\n\tstruct sk_buff *skb;\n\tunsigned long resend_at;\n\trxrpc_seq_t cursor, seq, top;": "static void rxrpc_resend(struct rxrpc_call *call, unsigned long now_j)\n{\n\tstruct sk_buff *skb;\n\tunsigned long resend_at;\n\trxrpc_seq_t cursor, seq, top;\n\tktime_t now, max_age, oldest, ack_ts;\n\tint ix;\n\tu8 annotation, anno_type, retrans = 0, unacked = 0;\n\n\t_enter(\"{%d,%d}\", call->tx_hard_ack, call->tx_top);\n\n\tnow = ktime_get_real();\n\tmax_age = ktime_sub(now, jiffies_to_usecs(call->peer->rto_j));\n\n\tspin_lock_bh(&call->lock);\n\n\tcursor = call->tx_hard_ack;\n\ttop = call->tx_top;\n\tASSERT(before_eq(cursor, top));\n\tif (cursor == top)\n\t\tgoto out_unlock;\n\n\t/* Scan the packet list without dropping the lock and decide which of\n\t * the packets in the Tx buffer we're going to resend and what the new\n\t * resend timeout will be.\n\t */\n\ttrace_rxrpc_resend(call, (cursor + 1) & RXRPC_RXTX_BUFF_MASK);\n\toldest = now;\n\tfor (seq = cursor + 1; before_eq(seq, top); seq++) {\n\t\tix = seq & RXRPC_RXTX_BUFF_MASK;\n\t\tannotation = call->rxtx_annotations[ix];\n\t\tanno_type = annotation & RXRPC_TX_ANNO_MASK;\n\t\tannotation &= ~RXRPC_TX_ANNO_MASK;\n\t\tif (anno_type == RXRPC_TX_ANNO_ACK)\n\t\t\tcontinue;\n\n\t\tskb = call->rxtx_buffer[ix];\n\t\trxrpc_see_skb(skb, rxrpc_skb_seen);\n\n\t\tif (anno_type == RXRPC_TX_ANNO_UNACK) {\n\t\t\tif (ktime_after(skb->tstamp, max_age)) {\n\t\t\t\tif (ktime_before(skb->tstamp, oldest))\n\t\t\t\t\toldest = skb->tstamp;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (!(annotation & RXRPC_TX_ANNO_RESENT))\n\t\t\t\tunacked++;\n\t\t}\n\n\t\t/* Okay, we need to retransmit a packet. */\n\t\tcall->rxtx_annotations[ix] = RXRPC_TX_ANNO_RETRANS | annotation;\n\t\tretrans++;\n\t\ttrace_rxrpc_retransmit(call, seq, annotation | anno_type,\n\t\t\t\t       ktime_to_ns(ktime_sub(skb->tstamp, max_age)));\n\t}\n\n\tresend_at = nsecs_to_jiffies(ktime_to_ns(ktime_sub(now, oldest)));\n\tresend_at += jiffies + rxrpc_get_rto_backoff(call->peer, retrans);\n\tWRITE_ONCE(call->resend_at, resend_at);\n\n\tif (unacked)\n\t\trxrpc_congestion_timeout(call);\n\n\t/* If there was nothing that needed retransmission then it's likely\n\t * that an ACK got lost somewhere.  Send a ping to find out instead of\n\t * retransmitting data.\n\t */\n\tif (!retrans) {\n\t\trxrpc_reduce_call_timer(call, resend_at, now_j,\n\t\t\t\t\trxrpc_timer_set_for_resend);\n\t\tspin_unlock_bh(&call->lock);\n\t\tack_ts = ktime_sub(now, call->acks_latest_ts);\n\t\tif (ktime_to_us(ack_ts) < (call->peer->srtt_us >> 3))\n\t\t\tgoto out;\n\t\trxrpc_propose_ACK(call, RXRPC_ACK_PING, 0, true, false,\n\t\t\t\t  rxrpc_propose_ack_ping_for_lost_ack);\n\t\trxrpc_send_ack_packet(call, true, NULL);\n\t\tgoto out;\n\t}\n\n\t/* Now go through the Tx window and perform the retransmissions.  We\n\t * have to drop the lock for each send.  If an ACK comes in whilst the\n\t * lock is dropped, it may clear some of the retransmission markers for\n\t * packets that it soft-ACKs.\n\t */\n\tfor (seq = cursor + 1; before_eq(seq, top); seq++) {\n\t\tix = seq & RXRPC_RXTX_BUFF_MASK;\n\t\tannotation = call->rxtx_annotations[ix];\n\t\tanno_type = annotation & RXRPC_TX_ANNO_MASK;\n\t\tif (anno_type != RXRPC_TX_ANNO_RETRANS)\n\t\t\tcontinue;\n\n\t\t/* We need to reset the retransmission state, but we need to do\n\t\t * so before we drop the lock as a new ACK/NAK may come in and\n\t\t * confuse things\n\t\t */\n\t\tannotation &= ~RXRPC_TX_ANNO_MASK;\n\t\tannotation |= RXRPC_TX_ANNO_UNACK | RXRPC_TX_ANNO_RESENT;\n\t\tcall->rxtx_annotations[ix] = annotation;\n\n\t\tskb = call->rxtx_buffer[ix];\n\t\tif (!skb)\n\t\t\tcontinue;\n\n\t\trxrpc_get_skb(skb, rxrpc_skb_got);\n\t\tspin_unlock_bh(&call->lock);\n\n\t\tif (rxrpc_send_data_packet(call, skb, true) < 0) {\n\t\t\trxrpc_free_skb(skb, rxrpc_skb_freed);\n\t\t\treturn;\n\t\t}\n\n\t\tif (rxrpc_is_client_call(call))\n\t\t\trxrpc_expose_client_call(call);\n\n\t\trxrpc_free_skb(skb, rxrpc_skb_freed);\n\t\tspin_lock_bh(&call->lock);\n\t\tif (after(call->tx_hard_ack, seq))\n\t\t\tseq = call->tx_hard_ack;\n\t}\n\nout_unlock:\n\tspin_unlock_bh(&call->lock);\nout:\n\t_leave(\"\");\n}",
        "static int mlx90632_calc_ambient_dsp105(struct mlx90632_data *data, int *val)\n{\n\ts32 ret;\n\tunsigned int read_tmp;\n\ts32 PT, PR, PG, PO;": "static int mlx90632_calc_ambient_dsp105(struct mlx90632_data *data, int *val)\n{\n\ts32 ret;\n\tunsigned int read_tmp;\n\ts32 PT, PR, PG, PO;\n\ts16 Gb;\n\ts16 ambient_new_raw, ambient_old_raw;\n\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_R, &PR);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_G, &PG);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_T, &PT);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_O, &PO);\n\tif (ret < 0)\n\t\treturn ret;\n\tret = regmap_read(data->regmap, MLX90632_EE_Gb, &read_tmp);\n\tif (ret < 0)\n\t\treturn ret;\n\tGb = (s16)read_tmp;\n\n\tret = mlx90632_read_ambient_raw(data->regmap, &ambient_new_raw,\n\t\t\t\t\t&ambient_old_raw);\n\tif (ret < 0)\n\t\treturn ret;\n\t*val = mlx90632_calc_temp_ambient(ambient_new_raw, ambient_old_raw,\n\t\t\t\t\t  PT, PR, PG, PO, Gb);\n\treturn ret;\n}",
        "static int p9_client_statsize(struct p9_wstat *wst, int proto_version)\n{\n\tint ret;\n\n\t/* NOTE: size shouldn't include its own length */": "static int p9_client_statsize(struct p9_wstat *wst, int proto_version)\n{\n\tint ret;\n\n\t/* NOTE: size shouldn't include its own length */\n\t/* size[2] type[2] dev[4] qid[13] */\n\t/* mode[4] atime[4] mtime[4] length[8]*/\n\t/* name[s] uid[s] gid[s] muid[s] */\n\tret = 2 + 4 + 13 + 4 + 4 + 4 + 8 + 2 + 2 + 2 + 2;\n\n\tif (wst->name)\n\t\tret += strlen(wst->name);\n\tif (wst->uid)\n\t\tret += strlen(wst->uid);\n\tif (wst->gid)\n\t\tret += strlen(wst->gid);\n\tif (wst->muid)\n\t\tret += strlen(wst->muid);\n\n\tif (proto_version == p9_proto_2000u ||\n\t    proto_version == p9_proto_2000L) {\n\t\t/* extension[s] n_uid[4] n_gid[4] n_muid[4] */\n\t\tret += 2 + 4 + 4 + 4;\n\t\tif (wst->extension)\n\t\t\tret += strlen(wst->extension);\n\t}\n\n\treturn ret;\n}",
        "static void kasan_bitops_generic(struct kunit *test)\n{\n\tlong *bits;\n\n\t/* This test is specifically crafted for the generic mode. */": "static void kasan_bitops_generic(struct kunit *test)\n{\n\tlong *bits;\n\n\t/* This test is specifically crafted for the generic mode. */\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_GENERIC);\n\n\t/*\n\t * Allocate 1 more byte, which causes kzalloc to round up to 16 bytes;\n\t * this way we do not actually corrupt other memory.\n\t */\n\tbits = kzalloc(sizeof(*bits) + 1, GFP_KERNEL);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, bits);\n\n\t/*\n\t * Below calls try to access bit within allocated memory; however, the\n\t * below accesses are still out-of-bounds, since bitops are defined to\n\t * operate on the whole long the bit is in.\n\t */\n\tkasan_bitops_modify(test, BITS_PER_LONG, bits);\n\n\t/*\n\t * Below calls try to access bit beyond allocated memory.\n\t */\n\tkasan_bitops_test_and_modify(test, BITS_PER_LONG + BITS_PER_BYTE, bits);\n\n\tkfree(bits);\n}",
        "static bool nl80211_can_set_dev_channel(struct wireless_dev *wdev)\n{\n\t/*\n\t * You can only set the channel explicitly for some interfaces,\n\t * most have their channel managed via their respective": "static bool nl80211_can_set_dev_channel(struct wireless_dev *wdev)\n{\n\t/*\n\t * You can only set the channel explicitly for some interfaces,\n\t * most have their channel managed via their respective\n\t * \"establish a connection\" command (connect, join, ...)\n\t *\n\t * For AP/GO and mesh mode, the channel can be set with the\n\t * channel userspace API, but is only stored and passed to the\n\t * low-level driver when the AP starts or the mesh is joined.\n\t * This is for backward compatibility, userspace can also give\n\t * the channel in the start-ap or join-mesh commands instead.\n\t *\n\t * Monitors are special as they are normally slaved to\n\t * whatever else is going on, so they have their own special\n\t * operation to set the monitor channel if possible.\n\t */\n\treturn !wdev ||\n\t\twdev->iftype == NL80211_IFTYPE_AP ||\n\t\twdev->iftype == NL80211_IFTYPE_MESH_POINT ||\n\t\twdev->iftype == NL80211_IFTYPE_MONITOR ||\n\t\twdev->iftype == NL80211_IFTYPE_P2P_GO;\n}",
        "static int flash_read (struct mtd_info *mtd,loff_t from,size_t len,size_t *retlen,u_char *buf)\n{\n#ifdef LART_DEBUG\n   printk (KERN_DEBUG \"%s(from = 0x%.8x, len = %d)\\n\", __func__, (__u32)from, len);\n#endif": "static int flash_read (struct mtd_info *mtd,loff_t from,size_t len,size_t *retlen,u_char *buf)\n{\n#ifdef LART_DEBUG\n   printk (KERN_DEBUG \"%s(from = 0x%.8x, len = %d)\\n\", __func__, (__u32)from, len);\n#endif\n\n   /* we always read len bytes */\n   *retlen = len;\n\n   /* first, we read bytes until we reach a dword boundary */\n   if (from & (BUSWIDTH - 1))\n\t {\n\t\tint gap = BUSWIDTH - (from & (BUSWIDTH - 1));\n\n\t\twhile (len && gap--) {\n\t\t\t*buf++ = read8 (from++);\n\t\t\tlen--;\n\t\t}\n\t }\n\n   /* now we read dwords until we reach a non-dword boundary */\n   while (len >= BUSWIDTH)\n\t {\n\t\t*((__u32 *) buf) = read32 (from);\n\n\t\tbuf += BUSWIDTH;\n\t\tfrom += BUSWIDTH;\n\t\tlen -= BUSWIDTH;\n\t }\n\n   /* top up the last unaligned bytes */\n   if (len & (BUSWIDTH - 1))\n\t while (len--) *buf++ = read8 (from++);\n\n   return (0);\n}",
        "static int set_qam64(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tstatic const u8 qam_dq_qual_fun[] = {": "static int set_qam64(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tstatic const u8 qam_dq_qual_fun[] = {\n\t\t/* this is hw reset value. no necessary to re-write */\n\t\tDRXJ_16TO8(4),\t/* fun0  */\n\t\tDRXJ_16TO8(4),\t/* fun1  */\n\t\tDRXJ_16TO8(4),\t/* fun2  */\n\t\tDRXJ_16TO8(4),\t/* fun3  */\n\t\tDRXJ_16TO8(6),\t/* fun4  */\n\t\tDRXJ_16TO8(6),\t/* fun5  */\n\t};\n\tstatic const u8 qam_eq_cma_rad[] = {\n\t\tDRXJ_16TO8(13336),\t/* RAD0  */\n\t\tDRXJ_16TO8(12618),\t/* RAD1  */\n\t\tDRXJ_16TO8(11988),\t/* RAD2  */\n\t\tDRXJ_16TO8(13809),\t/* RAD3  */\n\t\tDRXJ_16TO8(13809),\t/* RAD4  */\n\t\tDRXJ_16TO8(15609),\t/* RAD5  */\n\t};\n\n\trc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int cgw_chk_csum_parms(s8 fr, s8 to, s8 re, struct rtcanmsg *r)\n{\n\ts8 dlen = CAN_MAX_DLEN;\n\n\tif (r->flags & CGW_FLAGS_CAN_FD)": "static int cgw_chk_csum_parms(s8 fr, s8 to, s8 re, struct rtcanmsg *r)\n{\n\ts8 dlen = CAN_MAX_DLEN;\n\n\tif (r->flags & CGW_FLAGS_CAN_FD)\n\t\tdlen = CANFD_MAX_DLEN;\n\n\t/* absolute dlc values 0 .. 7 => 0 .. 7, e.g. data [0]\n\t * relative to received dlc -1 .. -8 :\n\t * e.g. for received dlc = 8\n\t * -1 => index = 7 (data[7])\n\t * -3 => index = 5 (data[5])\n\t * -8 => index = 0 (data[0])\n\t */\n\n\tif (fr >= -dlen && fr < dlen &&\n\t    to >= -dlen && to < dlen &&\n\t    re >= -dlen && re < dlen)\n\t\treturn 0;\n\telse\n\t\treturn -EINVAL;\n}",
        "static void sbz_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n": "static void sbz_exit_chip(struct hda_codec *codec)\n{\n\tchipio_set_stream_control(codec, 0x03, 0);\n\tchipio_set_stream_control(codec, 0x04, 0);\n\n\t/* Mess with GPIO */\n\tsbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);\n\tsbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);\n\tsbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);\n\n\tchipio_set_stream_control(codec, 0x14, 0);\n\tchipio_set_stream_control(codec, 0x0C, 0);\n\n\tchipio_set_conn_rate(codec, 0x41, SR_192_000);\n\tchipio_set_conn_rate(codec, 0x91, SR_192_000);\n\n\tchipio_write(codec, 0x18a020, 0x00000083);\n\n\tsbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);\n\tsbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);\n\tsbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);\n\n\tchipio_set_stream_control(codec, 0x0C, 0);\n\n\tchipio_set_control_param(codec, 0x0D, 0x24);\n\n\tca0132_clear_unsolicited(codec);\n\tsbz_set_pin_ctl_default(codec);\n\n\tsnd_hda_codec_write(codec, 0x0B, 0,\n\t\tAC_VERB_SET_EAPD_BTLENABLE, 0x00);\n\n\tsbz_region2_exit(codec);\n}",
        "static bool desc_reserve(struct printk_ringbuffer *rb, unsigned long *id_out)\n{\n\tstruct prb_desc_ring *desc_ring = &rb->desc_ring;\n\tunsigned long prev_state_val;\n\tunsigned long id_prev_wrap;": "static bool desc_reserve(struct printk_ringbuffer *rb, unsigned long *id_out)\n{\n\tstruct prb_desc_ring *desc_ring = &rb->desc_ring;\n\tunsigned long prev_state_val;\n\tunsigned long id_prev_wrap;\n\tstruct prb_desc *desc;\n\tunsigned long head_id;\n\tunsigned long id;\n\n\thead_id = atomic_long_read(&desc_ring->head_id); /* LMM(desc_reserve:A) */\n\n\tdo {\n\t\tid = DESC_ID(head_id + 1);\n\t\tid_prev_wrap = DESC_ID_PREV_WRAP(desc_ring, id);\n\n\t\t/*\n\t\t * Guarantee the head ID is read before reading the tail ID.\n\t\t * Since the tail ID is updated before the head ID, this\n\t\t * guarantees that @id_prev_wrap is never ahead of the tail\n\t\t * ID. This pairs with desc_reserve:D.\n\t\t *\n\t\t * Memory barrier involvement:\n\t\t *\n\t\t * If desc_reserve:A reads from desc_reserve:D, then\n\t\t * desc_reserve:C reads from desc_push_tail:B.\n\t\t *\n\t\t * Relies on:\n\t\t *\n\t\t * MB from desc_push_tail:B to desc_reserve:D\n\t\t *    matching\n\t\t * RMB from desc_reserve:A to desc_reserve:C\n\t\t *\n\t\t * Note: desc_push_tail:B and desc_reserve:D can be different\n\t\t *       CPUs. However, the desc_reserve:D CPU (which performs\n\t\t *       the full memory barrier) must have previously seen\n\t\t *       desc_push_tail:B.\n\t\t */\n\t\tsmp_rmb(); /* LMM(desc_reserve:B) */\n\n\t\tif (id_prev_wrap == atomic_long_read(&desc_ring->tail_id\n\t\t\t\t\t\t    )) { /* LMM(desc_reserve:C) */\n\t\t\t/*\n\t\t\t * Make space for the new descriptor by\n\t\t\t * advancing the tail.\n\t\t\t */\n\t\t\tif (!desc_push_tail(rb, id_prev_wrap))\n\t\t\t\treturn false;\n\t\t}\n\n\t\t/*\n\t\t * 1. Guarantee the tail ID is read before validating the\n\t\t *    recycled descriptor state. A read memory barrier is\n\t\t *    sufficient for this. This pairs with desc_push_tail:B.\n\t\t *\n\t\t *    Memory barrier involvement:\n\t\t *\n\t\t *    If desc_reserve:C reads from desc_push_tail:B, then\n\t\t *    desc_reserve:E reads from desc_make_reusable:A.\n\t\t *\n\t\t *    Relies on:\n\t\t *\n\t\t *    MB from desc_make_reusable:A to desc_push_tail:B\n\t\t *       matching\n\t\t *    RMB from desc_reserve:C to desc_reserve:E\n\t\t *\n\t\t *    Note: desc_make_reusable:A and desc_push_tail:B can be\n\t\t *          different CPUs. However, the desc_push_tail:B CPU\n\t\t *          (which performs the full memory barrier) must have\n\t\t *          previously seen desc_make_reusable:A.\n\t\t *\n\t\t * 2. Guarantee the tail ID is stored before storing the head\n\t\t *    ID. This pairs with desc_reserve:B.\n\t\t *\n\t\t * 3. Guarantee any data ring tail changes are stored before\n\t\t *    recycling the descriptor. Data ring tail changes can\n\t\t *    happen via desc_push_tail()->data_push_tail(). A full\n\t\t *    memory barrier is needed since another CPU may have\n\t\t *    pushed the data ring tails. This pairs with\n\t\t *    data_push_tail:B.\n\t\t *\n\t\t * 4. Guarantee a new tail ID is stored before recycling the\n\t\t *    descriptor. A full memory barrier is needed since\n\t\t *    another CPU may have pushed the tail ID. This pairs\n\t\t *    with desc_push_tail:C and this also pairs with\n\t\t *    prb_first_seq:C.\n\t\t *\n\t\t * 5. Guarantee the head ID is stored before trying to\n\t\t *    finalize the previous descriptor. This pairs with\n\t\t *    _prb_commit:B.\n\t\t */\n\t} while (!atomic_long_try_cmpxchg(&desc_ring->head_id, &head_id,\n\t\t\t\t\t  id)); /* LMM(desc_reserve:D) */\n\n\tdesc = to_desc(desc_ring, id);\n\n\t/*\n\t * If the descriptor has been recycled, verify the old state val.\n\t * See \"ABA Issues\" about why this verification is performed.\n\t */\n\tprev_state_val = atomic_long_read(&desc->state_var); /* LMM(desc_reserve:E) */\n\tif (prev_state_val &&\n\t    get_desc_state(id_prev_wrap, prev_state_val) != desc_reusable) {\n\t\tWARN_ON_ONCE(1);\n\t\treturn false;\n\t}\n\n\t/*\n\t * Assign the descriptor a new ID and set its state to reserved.\n\t * See \"ABA Issues\" about why cmpxchg() instead of set() is used.\n\t *\n\t * Guarantee the new descriptor ID and state is stored before making\n\t * any other changes. A write memory barrier is sufficient for this.\n\t * This pairs with desc_read:D.\n\t */\n\tif (!atomic_long_try_cmpxchg(&desc->state_var, &prev_state_val,\n\t\t\tDESC_SV(id, desc_reserved))) { /* LMM(desc_reserve:F) */\n\t\tWARN_ON_ONCE(1);\n\t\treturn false;\n\t}\n\n\t/* Now data in @desc can be modified: LMM(desc_reserve:G) */\n\n\t*id_out = id;\n\treturn true;\n}",
        "static int rt711_sdca_set_fu0f_capture_ctl(struct rt711_sdca_priv *rt711)\n{\n\tint err;\n\tunsigned int ch_l, ch_r;\n": "static int rt711_sdca_set_fu0f_capture_ctl(struct rt711_sdca_priv *rt711)\n{\n\tint err;\n\tunsigned int ch_l, ch_r;\n\n\tch_l = (rt711->fu0f_dapm_mute || rt711->fu0f_mixer_l_mute) ? 0x01 : 0x00;\n\tch_r = (rt711->fu0f_dapm_mute || rt711->fu0f_mixer_r_mute) ? 0x01 : 0x00;\n\n\terr = regmap_write(rt711->regmap,\n\t\t\tSDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F,\n\t\t\tRT711_SDCA_CTL_FU_MUTE, CH_L), ch_l);\n\tif (err < 0)\n\t\treturn err;\n\n\terr = regmap_write(rt711->regmap,\n\t\t\tSDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F,\n\t\t\tRT711_SDCA_CTL_FU_MUTE, CH_R), ch_r);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn 0;\n}",
        "static void test_setsockopt_default_zero(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_get_retval = NULL;\n": "static void test_setsockopt_default_zero(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_setsockopt *obj;\n\tstruct bpf_link *link_get_retval = NULL;\n\n\tobj = cgroup_getset_retval_setsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach setsockopt that gets the previously set errno.\n\t * Assert that, without anything setting one, we get 0.\n\t */\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_OK(setsockopt(sock_fd, SOL_SOCKET, SO_REUSEADDR,\n\t\t\t\t  &zero, sizeof(int)), \"setsockopt\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 1, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, 0, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_setsockopt__destroy(obj);\n}",
        "static unsigned int task_scan_max(struct task_struct *p)\n{\n\tunsigned long smin = task_scan_min(p);\n\tunsigned long smax;\n\tstruct numa_group *ng;": "static unsigned int task_scan_max(struct task_struct *p)\n{\n\tunsigned long smin = task_scan_min(p);\n\tunsigned long smax;\n\tstruct numa_group *ng;\n\n\t/* Watch for min being lower than max due to floor calculations */\n\tsmax = sysctl_numa_balancing_scan_period_max / task_nr_scan_windows(p);\n\n\t/* Scale the maximum scan period with the amount of shared memory. */\n\tng = deref_curr_numa_group(p);\n\tif (ng) {\n\t\tunsigned long shared = group_faults_shared(ng);\n\t\tunsigned long private = group_faults_priv(ng);\n\t\tunsigned long period = smax;\n\n\t\tperiod *= refcount_read(&ng->refcount);\n\t\tperiod *= shared + 1;\n\t\tperiod /= private + shared + 1;\n\n\t\tsmax = max(smax, period);\n\t}\n\n\treturn max(smin, smax);\n}",
        "static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)\n{\n\tu32 data, *rx32;\n\tu8 *rx8;\n\tunsigned int rxbv, shift;": "static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)\n{\n\tu32 data, *rx32;\n\tu8 *rx8;\n\tunsigned int rxbv, shift;\n\tunsigned int rx_fill = rx_fifo_level(spi);\n\n\t/*\n\t * In RX-only mode the bits per word value is ignored by HW. A value\n\t * of 32 is used instead. Thus all 4 bytes per FIFO must be read.\n\t * If remaining RX bytes are less than 4, the FIFO must be read\n\t * differently. The amount of received and valid bytes is indicated\n\t * by STAT.RXBV register value.\n\t */\n\twhile (rx_fill) {\n\t\tif (spi->rx_todo < 4)  {\n\t\t\trxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &\n\t\t\t\tLTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;\n\t\t\tdata = lantiq_ssc_readl(spi, LTQ_SPI_RB);\n\n\t\t\tshift = (rxbv - 1) * 8;\n\t\t\trx8 = spi->rx;\n\n\t\t\twhile (rxbv) {\n\t\t\t\t*rx8++ = (data >> shift) & 0xFF;\n\t\t\t\trxbv--;\n\t\t\t\tshift -= 8;\n\t\t\t\tspi->rx_todo--;\n\t\t\t\tspi->rx++;\n\t\t\t}\n\t\t} else {\n\t\t\tdata = lantiq_ssc_readl(spi, LTQ_SPI_RB);\n\t\t\trx32 = (u32 *) spi->rx;\n\n\t\t\t*rx32++ = data;\n\t\t\tspi->rx_todo -= 4;\n\t\t\tspi->rx += 4;\n\t\t}\n\t\trx_fill--;\n\t}\n}",
        "static void on_sample(void *ctx, int cpu, void *data, __u32 size)\n{\n\tstruct meta *meta = (struct meta *)data;\n\tstruct ipv4_packet *trace_pkt_v4 = data + sizeof(*meta);\n\tunsigned char *raw_pkt = data + sizeof(*meta);": "static void on_sample(void *ctx, int cpu, void *data, __u32 size)\n{\n\tstruct meta *meta = (struct meta *)data;\n\tstruct ipv4_packet *trace_pkt_v4 = data + sizeof(*meta);\n\tunsigned char *raw_pkt = data + sizeof(*meta);\n\tstruct test_ctx_s *tst_ctx = ctx;\n\n\tASSERT_GE(size, sizeof(pkt_v4) + sizeof(*meta), \"check_size\");\n\tASSERT_EQ(meta->ifindex, if_nametoindex(\"lo\"), \"check_meta_ifindex\");\n\tASSERT_EQ(meta->pkt_len, tst_ctx->pkt_size, \"check_meta_pkt_len\");\n\tASSERT_EQ(memcmp(trace_pkt_v4, &pkt_v4, sizeof(pkt_v4)), 0,\n\t\t  \"check_packet_content\");\n\n\tif (meta->pkt_len > sizeof(pkt_v4)) {\n\t\tfor (int i = 0; i < meta->pkt_len - sizeof(pkt_v4); i++)\n\t\t\tASSERT_EQ(raw_pkt[i + sizeof(pkt_v4)], (unsigned char)i,\n\t\t\t\t  \"check_packet_content\");\n\t}\n\n\ttst_ctx->passed = true;\n}",
        "static void copy_image_block_CrCb(const int *src, unsigned char *dst, unsigned int bytes_per_line, unsigned int scalebits)\n{\n#if UNROLL_LOOP_FOR_COPY\n\t/* Unroll all loops */\n\tconst unsigned char *cm = pwc_crop_table+MAX_OUTER_CROP_VALUE;": "static void copy_image_block_CrCb(const int *src, unsigned char *dst, unsigned int bytes_per_line, unsigned int scalebits)\n{\n#if UNROLL_LOOP_FOR_COPY\n\t/* Unroll all loops */\n\tconst unsigned char *cm = pwc_crop_table+MAX_OUTER_CROP_VALUE;\n\tconst int *c = src;\n\tunsigned char *d = dst;\n\n\t*d++ = cm[c[0] >> scalebits];\n\t*d++ = cm[c[4] >> scalebits];\n\t*d++ = cm[c[1] >> scalebits];\n\t*d++ = cm[c[5] >> scalebits];\n\t*d++ = cm[c[2] >> scalebits];\n\t*d++ = cm[c[6] >> scalebits];\n\t*d++ = cm[c[3] >> scalebits];\n\t*d++ = cm[c[7] >> scalebits];\n\n\td = dst + bytes_per_line;\n\t*d++ = cm[c[12] >> scalebits];\n\t*d++ = cm[c[8] >> scalebits];\n\t*d++ = cm[c[13] >> scalebits];\n\t*d++ = cm[c[9] >> scalebits];\n\t*d++ = cm[c[14] >> scalebits];\n\t*d++ = cm[c[10] >> scalebits];\n\t*d++ = cm[c[15] >> scalebits];\n\t*d++ = cm[c[11] >> scalebits];\n#else\n\tint i;\n\tconst int *c1 = src;\n\tconst int *c2 = src + 4;\n\tunsigned char *d = dst;\n\n\tfor (i = 0; i < 4; i++, c1++, c2++) {\n\t\t*d++ = CLAMP((*c1) >> scalebits);\n\t\t*d++ = CLAMP((*c2) >> scalebits);\n\t}\n\tc1 = src + 12;\n\td = dst + bytes_per_line;\n\tfor (i = 0; i < 4; i++, c1++, c2++) {\n\t\t*d++ = CLAMP((*c1) >> scalebits);\n\t\t*d++ = CLAMP((*c2) >> scalebits);\n\t}\n#endif\n}",
        "static int test_process_multi_same_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, same addr, one is RO, other is WO\";": "static int test_process_multi_same_addr_ro_wo(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, same addr, one is RO, other is WO\";\n\tsize_t res;\n\n\tfd1 = perf_process_event_open(HW_BREAKPOINT_R, (__u64)&a, (__u64)sizeof(a));\n\tif (fd1 < 0) {\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tfd2 = perf_process_event_open(HW_BREAKPOINT_W, (__u64)&a, (__u64)sizeof(a));\n\tif (fd2 < 0) {\n\t\tclose(fd1);\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tioctl(fd1, PERF_EVENT_IOC_RESET);\n\tioctl(fd2, PERF_EVENT_IOC_RESET);\n\tioctl(fd1, PERF_EVENT_IOC_ENABLE);\n\tioctl(fd2, PERF_EVENT_IOC_ENABLE);\n\tmulti_dawr_workload();\n\tioctl(fd1, PERF_EVENT_IOC_DISABLE);\n\tioctl(fd2, PERF_EVENT_IOC_DISABLE);\n\n\tres = read(fd1, &breaks1, sizeof(breaks1));\n\tassert(res == sizeof(unsigned long long));\n\tres = read(fd2, &breaks2, sizeof(breaks2));\n\tassert(res == sizeof(unsigned long long));\n\n\tclose(fd1);\n\tclose(fd2);\n\n\tif (breaks1 != 1 || breaks2 != 1) {\n\t\tprintf(\"FAILED: %s: %lld != 1 || %lld != 1\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static int write_fw(struct adapter *padapter, u8 *buffer, u32 size)\n{\n\t/*  Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */\n\t/*  We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */\n\tint ret = _SUCCESS;": "static int write_fw(struct adapter *padapter, u8 *buffer, u32 size)\n{\n\t/*  Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */\n\t/*  We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */\n\tint ret = _SUCCESS;\n\tu32\tpageNums, remainSize;\n\tu32\tpage, offset;\n\n\tpageNums = size / MAX_PAGE_SIZE;\n\tremainSize = size % MAX_PAGE_SIZE;\n\n\tfor (page = 0; page < pageNums; page++) {\n\t\toffset = page * MAX_PAGE_SIZE;\n\t\tret = page_write(padapter, page, buffer + offset, MAX_PAGE_SIZE);\n\n\t\tif (ret == _FAIL)\n\t\t\tgoto exit;\n\t}\n\tif (remainSize) {\n\t\toffset = pageNums * MAX_PAGE_SIZE;\n\t\tpage = pageNums;\n\t\tret = page_write(padapter, page, buffer + offset, remainSize);\n\n\t\tif (ret == _FAIL)\n\t\t\tgoto exit;\n\t}\nexit:\n\treturn ret;\n}",
        "static void test_fmod_ret_freplace(void)\n{\n\tstruct bpf_object *freplace_obj = NULL, *pkt_obj, *fmod_obj = NULL;\n\tconst char *freplace_name = \"./freplace_get_constant.o\";\n\tconst char *fmod_ret_name = \"./fmod_ret_freplace.o\";": "static void test_fmod_ret_freplace(void)\n{\n\tstruct bpf_object *freplace_obj = NULL, *pkt_obj, *fmod_obj = NULL;\n\tconst char *freplace_name = \"./freplace_get_constant.o\";\n\tconst char *fmod_ret_name = \"./fmod_ret_freplace.o\";\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, opts);\n\tconst char *tgt_name = \"./test_pkt_access.o\";\n\tstruct bpf_link *freplace_link = NULL;\n\tstruct bpf_program *prog;\n\t__u32 duration = 0;\n\tint err, pkt_fd, attach_prog_fd;\n\n\terr = bpf_prog_test_load(tgt_name, BPF_PROG_TYPE_UNSPEC,\n\t\t\t    &pkt_obj, &pkt_fd);\n\t/* the target prog should load fine */\n\tif (CHECK(err, \"tgt_prog_load\", \"file %s err %d errno %d\\n\",\n\t\t  tgt_name, err, errno))\n\t\treturn;\n\n\tfreplace_obj = bpf_object__open_file(freplace_name, NULL);\n\tif (!ASSERT_OK_PTR(freplace_obj, \"freplace_obj_open\"))\n\t\tgoto out;\n\n\tprog = bpf_object__next_program(freplace_obj, NULL);\n\terr = bpf_program__set_attach_target(prog, pkt_fd, NULL);\n\tASSERT_OK(err, \"freplace__set_attach_target\");\n\n\terr = bpf_object__load(freplace_obj);\n\tif (CHECK(err, \"freplace_obj_load\", \"err %d\\n\", err))\n\t\tgoto out;\n\n\tfreplace_link = bpf_program__attach_trace(prog);\n\tif (!ASSERT_OK_PTR(freplace_link, \"freplace_attach_trace\"))\n\t\tgoto out;\n\n\tfmod_obj = bpf_object__open_file(fmod_ret_name, NULL);\n\tif (!ASSERT_OK_PTR(fmod_obj, \"fmod_obj_open\"))\n\t\tgoto out;\n\n\tattach_prog_fd = bpf_program__fd(prog);\n\tprog = bpf_object__next_program(fmod_obj, NULL);\n\terr = bpf_program__set_attach_target(prog, attach_prog_fd, NULL);\n\tASSERT_OK(err, \"fmod_ret_set_attach_target\");\n\n\terr = bpf_object__load(fmod_obj);\n\tif (CHECK(!err, \"fmod_obj_load\", \"loading fmod_ret should fail\\n\"))\n\t\tgoto out;\n\nout:\n\tbpf_link__destroy(freplace_link);\n\tbpf_object__close(freplace_obj);\n\tbpf_object__close(fmod_obj);\n\tbpf_object__close(pkt_obj);\n}",
        "static void gtp1u_build_echo_msg(struct gtp1_header_long *hdr, __u8 msg_type)\n{\n\tint len_pkt, len_hdr;\n\n\t/* S flag must be set to 1 */": "static void gtp1u_build_echo_msg(struct gtp1_header_long *hdr, __u8 msg_type)\n{\n\tint len_pkt, len_hdr;\n\n\t/* S flag must be set to 1 */\n\thdr->flags = 0x32; /* v1, GTP-non-prime. */\n\thdr->type = msg_type;\n\t/* 3GPP TS 29.281 5.1 - TEID has to be set to 0 */\n\thdr->tid = 0;\n\n\t/* seq, npdu and next should be counted to the length of the GTP packet\n\t * that's why szie of gtp1_header should be subtracted,\n\t * not size of gtp1_header_long.\n\t */\n\n\tlen_hdr = sizeof(struct gtp1_header);\n\n\tif (msg_type == GTP_ECHO_RSP) {\n\t\tlen_pkt = sizeof(struct gtp1u_packet);\n\t\thdr->length = htons(len_pkt - len_hdr);\n\t} else {\n\t\t/* GTP_ECHO_REQ does not carry GTP Information Element,\n\t\t * the why gtp1_header_long is used here.\n\t\t */\n\t\tlen_pkt = sizeof(struct gtp1_header_long);\n\t\thdr->length = htons(len_pkt - len_hdr);\n\t}\n}",
        "static void smc_listen_work(struct work_struct *work)\n{\n\tstruct smc_sock *new_smc = container_of(work, struct smc_sock,\n\t\t\t\t\t\tsmc_listen_work);\n\tstruct socket *newclcsock = new_smc->clcsock;": "static void smc_listen_work(struct work_struct *work)\n{\n\tstruct smc_sock *new_smc = container_of(work, struct smc_sock,\n\t\t\t\t\t\tsmc_listen_work);\n\tstruct socket *newclcsock = new_smc->clcsock;\n\tstruct smc_clc_msg_accept_confirm *cclc;\n\tstruct smc_clc_msg_proposal_area *buf;\n\tstruct smc_clc_msg_proposal *pclc;\n\tstruct smc_init_info *ini = NULL;\n\tu8 proposal_version = SMC_V1;\n\tu8 accept_version;\n\tint rc = 0;\n\n\tif (new_smc->listen_smc->sk.sk_state != SMC_LISTEN)\n\t\treturn smc_listen_out_err(new_smc);\n\n\tif (new_smc->use_fallback) {\n\t\tsmc_listen_out_connected(new_smc);\n\t\treturn;\n\t}\n\n\t/* check if peer is smc capable */\n\tif (!tcp_sk(newclcsock->sk)->syn_smc) {\n\t\trc = smc_switch_to_fallback(new_smc, SMC_CLC_DECL_PEERNOSMC);\n\t\tif (rc)\n\t\t\tsmc_listen_out_err(new_smc);\n\t\telse\n\t\t\tsmc_listen_out_connected(new_smc);\n\t\treturn;\n\t}\n\n\t/* do inband token exchange -\n\t * wait for and receive SMC Proposal CLC message\n\t */\n\tbuf = kzalloc(sizeof(*buf), GFP_KERNEL);\n\tif (!buf) {\n\t\trc = SMC_CLC_DECL_MEM;\n\t\tgoto out_decl;\n\t}\n\tpclc = (struct smc_clc_msg_proposal *)buf;\n\trc = smc_clc_wait_msg(new_smc, pclc, sizeof(*buf),\n\t\t\t      SMC_CLC_PROPOSAL, CLC_WAIT_TIME);\n\tif (rc)\n\t\tgoto out_decl;\n\n\tif (pclc->hdr.version > SMC_V1)\n\t\tproposal_version = SMC_V2;\n\n\t/* IPSec connections opt out of SMC optimizations */\n\tif (using_ipsec(new_smc)) {\n\t\trc = SMC_CLC_DECL_IPSEC;\n\t\tgoto out_decl;\n\t}\n\n\tini = kzalloc(sizeof(*ini), GFP_KERNEL);\n\tif (!ini) {\n\t\trc = SMC_CLC_DECL_MEM;\n\t\tgoto out_decl;\n\t}\n\n\t/* initial version checking */\n\trc = smc_listen_v2_check(new_smc, pclc, ini);\n\tif (rc)\n\t\tgoto out_decl;\n\n\tmutex_lock(&smc_server_lgr_pending);\n\tsmc_close_init(new_smc);\n\tsmc_rx_init(new_smc);\n\tsmc_tx_init(new_smc);\n\n\t/* determine ISM or RoCE device used for connection */\n\trc = smc_listen_find_device(new_smc, pclc, ini);\n\tif (rc)\n\t\tgoto out_unlock;\n\n\t/* send SMC Accept CLC message */\n\taccept_version = ini->is_smcd ? ini->smcd_version : ini->smcr_version;\n\trc = smc_clc_send_accept(new_smc, ini->first_contact_local,\n\t\t\t\t accept_version, ini->negotiated_eid);\n\tif (rc)\n\t\tgoto out_unlock;\n\n\t/* SMC-D does not need this lock any more */\n\tif (ini->is_smcd)\n\t\tmutex_unlock(&smc_server_lgr_pending);\n\n\t/* receive SMC Confirm CLC message */\n\tmemset(buf, 0, sizeof(*buf));\n\tcclc = (struct smc_clc_msg_accept_confirm *)buf;\n\trc = smc_clc_wait_msg(new_smc, cclc, sizeof(*buf),\n\t\t\t      SMC_CLC_CONFIRM, CLC_WAIT_TIME);\n\tif (rc) {\n\t\tif (!ini->is_smcd)\n\t\t\tgoto out_unlock;\n\t\tgoto out_decl;\n\t}\n\n\t/* finish worker */\n\tif (!ini->is_smcd) {\n\t\trc = smc_listen_rdma_finish(new_smc, cclc,\n\t\t\t\t\t    ini->first_contact_local, ini);\n\t\tif (rc)\n\t\t\tgoto out_unlock;\n\t\tmutex_unlock(&smc_server_lgr_pending);\n\t}\n\tsmc_conn_save_peer_info(new_smc, cclc);\n\tsmc_listen_out_connected(new_smc);\n\tSMC_STAT_SERV_SUCC_INC(sock_net(newclcsock->sk), ini);\n\tgoto out_free;\n\nout_unlock:\n\tmutex_unlock(&smc_server_lgr_pending);\nout_decl:\n\tsmc_listen_decline(new_smc, rc, ini ? ini->first_contact_local : 0,\n\t\t\t   proposal_version);\nout_free:\n\tkfree(ini);\n\tkfree(buf);\n}",
        "static int fsm_routine_starting(struct t7xx_fsm_ctl *ctl)\n{\n\tstruct t7xx_modem *md = ctl->md;\n\tstruct device *dev;\n": "static int fsm_routine_starting(struct t7xx_fsm_ctl *ctl)\n{\n\tstruct t7xx_modem *md = ctl->md;\n\tstruct device *dev;\n\n\tctl->curr_state = FSM_STATE_STARTING;\n\n\tt7xx_fsm_broadcast_state(ctl, MD_STATE_WAITING_FOR_HS1);\n\tt7xx_md_event_notify(md, FSM_START);\n\n\twait_event_interruptible_timeout(ctl->async_hk_wq, md->core_md.ready || ctl->exp_flg,\n\t\t\t\t\t HZ * 60);\n\tdev = &md->t7xx_dev->pdev->dev;\n\n\tif (ctl->exp_flg)\n\t\tdev_err(dev, \"MD exception is captured during handshake\\n\");\n\n\tif (!md->core_md.ready) {\n\t\tdev_err(dev, \"MD handshake timeout\\n\");\n\t\tif (md->core_md.handshake_ongoing)\n\t\t\tt7xx_fsm_append_event(ctl, FSM_EVENT_MD_HS2_EXIT, NULL, 0);\n\n\t\tfsm_routine_exception(ctl, NULL, EXCEPTION_HS_TIMEOUT);\n\t\treturn -ETIMEDOUT;\n\t}\n\n\tt7xx_pci_pm_init_late(md->t7xx_dev);\n\tfsm_routine_ready(ctl);\n\treturn 0;\n}",
        "static int alloc_try_nid_reserved_all_generic_check(void)\n{\n\tvoid *allocated_ptr = NULL;\n\tstruct region r1, r2;\n": "static int alloc_try_nid_reserved_all_generic_check(void)\n{\n\tvoid *allocated_ptr = NULL;\n\tstruct region r1, r2;\n\n\tphys_addr_t r3_size = SZ_256;\n\tphys_addr_t gap_size = SMP_CACHE_BYTES;\n\tphys_addr_t max_addr;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES;\n\tr1.size = SMP_CACHE_BYTES;\n\n\tr2.size = MEM_SIZE - (r1.size + gap_size);\n\tr2.base = memblock_start_of_DRAM();\n\n\tmin_addr = r2.base + r2.size;\n\tmax_addr = r1.base;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\n\tassert(!allocated_ptr);\n\n\treturn 0;\n}",
        "static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)\n{\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tunsigned int link_id = sdw->instance;\n\tu16 ioctl;": "static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)\n{\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tunsigned int link_id = sdw->instance;\n\tu16 ioctl;\n\n\t/* Switch to MIP from Glue logic */\n\tioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));\n\n\tioctl &= ~(SDW_SHIM_IOCTL_DOE);\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tioctl &= ~(SDW_SHIM_IOCTL_DO);\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tioctl |= (SDW_SHIM_IOCTL_MIF);\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tioctl &= ~(SDW_SHIM_IOCTL_BKE);\n\tioctl &= ~(SDW_SHIM_IOCTL_COE);\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\t/* at this point Master IP has full control of the I/Os */\n}",
        "static int snd_trident_4d_dx_init(struct snd_trident *trident)\n{\n\tstruct pci_dev *pci = trident->pci;\n\tunsigned long end_time;\n": "static int snd_trident_4d_dx_init(struct snd_trident *trident)\n{\n\tstruct pci_dev *pci = trident->pci;\n\tunsigned long end_time;\n\n\t/* reset the legacy configuration and whole audio/wavetable block */\n\tpci_write_config_dword(pci, 0x40, 0);\t/* DDMA */\n\tpci_write_config_byte(pci, 0x44, 0);\t/* ports */\n\tpci_write_config_byte(pci, 0x45, 0);\t/* Legacy DMA */\n\tpci_write_config_byte(pci, 0x46, 4); /* reset */\n\tudelay(100);\n\tpci_write_config_byte(pci, 0x46, 0); /* release reset */\n\tudelay(100);\n\t\n\t/* warm reset of the AC'97 codec */\n\toutl(0x00000001, TRID_REG(trident, DX_ACR2_AC97_COM_STAT));\n\tudelay(100);\n\toutl(0x00000000, TRID_REG(trident, DX_ACR2_AC97_COM_STAT));\n\t/* DAC on, disable SB IRQ and try to force ADC valid signal */\n\ttrident->ac97_ctrl = 0x0000004a;\n\toutl(trident->ac97_ctrl, TRID_REG(trident, DX_ACR2_AC97_COM_STAT));\n\t/* wait, until the codec is ready */\n\tend_time = (jiffies + (HZ * 3) / 4) + 1;\n\tdo {\n\t\tif ((inl(TRID_REG(trident, DX_ACR2_AC97_COM_STAT)) & 0x0010) != 0)\n\t\t\tgoto __dx_ok;\n\t\tdo_delay(trident);\n\t} while (time_after_eq(end_time, jiffies));\n\tdev_err(trident->card->dev, \"AC'97 codec ready error\\n\");\n\treturn -EIO;\n\n __dx_ok:\n\tsnd_trident_stop_all_voices(trident);\n\n\treturn 0;\n}",
        "static int tls_read_size(struct strparser *strp, struct sk_buff *skb)\n{\n\tstruct tls_context *tls_ctx = tls_get_ctx(strp->sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tchar header[TLS_HEADER_SIZE + MAX_IV_SIZE];": "static int tls_read_size(struct strparser *strp, struct sk_buff *skb)\n{\n\tstruct tls_context *tls_ctx = tls_get_ctx(strp->sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tchar header[TLS_HEADER_SIZE + MAX_IV_SIZE];\n\tstruct strp_msg *rxm = strp_msg(skb);\n\tstruct tls_msg *tlm = tls_msg(skb);\n\tsize_t cipher_overhead;\n\tsize_t data_len = 0;\n\tint ret;\n\n\t/* Verify that we have a full TLS header, or wait for more data */\n\tif (rxm->offset + prot->prepend_size > skb->len)\n\t\treturn 0;\n\n\t/* Sanity-check size of on-stack buffer. */\n\tif (WARN_ON(prot->prepend_size > sizeof(header))) {\n\t\tret = -EINVAL;\n\t\tgoto read_failure;\n\t}\n\n\t/* Linearize header to local buffer */\n\tret = skb_copy_bits(skb, rxm->offset, header, prot->prepend_size);\n\tif (ret < 0)\n\t\tgoto read_failure;\n\n\ttlm->decrypted = 0;\n\ttlm->control = header[0];\n\n\tdata_len = ((header[4] & 0xFF) | (header[3] << 8));\n\n\tcipher_overhead = prot->tag_size;\n\tif (prot->version != TLS_1_3_VERSION &&\n\t    prot->cipher_type != TLS_CIPHER_CHACHA20_POLY1305)\n\t\tcipher_overhead += prot->iv_size;\n\n\tif (data_len > TLS_MAX_PAYLOAD_SIZE + cipher_overhead +\n\t    prot->tail_size) {\n\t\tret = -EMSGSIZE;\n\t\tgoto read_failure;\n\t}\n\tif (data_len < cipher_overhead) {\n\t\tret = -EBADMSG;\n\t\tgoto read_failure;\n\t}\n\n\t/* Note that both TLS1.3 and TLS1.2 use TLS_1_2 version here */\n\tif (header[1] != TLS_1_2_VERSION_MINOR ||\n\t    header[2] != TLS_1_2_VERSION_MAJOR) {\n\t\tret = -EINVAL;\n\t\tgoto read_failure;\n\t}\n\n\ttls_device_rx_resync_new_rec(strp->sk, data_len + TLS_HEADER_SIZE,\n\t\t\t\t     TCP_SKB_CB(skb)->seq + rxm->offset);\n\treturn data_len + TLS_HEADER_SIZE;\n\nread_failure:\n\ttls_err_abort(strp->sk, ret);\n\n\treturn ret;\n}",
        "static int ocfs2_xattr_find_divide_pos(struct ocfs2_xattr_header *xh)\n{\n\tstruct ocfs2_xattr_entry *entries = xh->xh_entries;\n\tint count = le16_to_cpu(xh->xh_count);\n\tint delta, middle = count / 2;": "static int ocfs2_xattr_find_divide_pos(struct ocfs2_xattr_header *xh)\n{\n\tstruct ocfs2_xattr_entry *entries = xh->xh_entries;\n\tint count = le16_to_cpu(xh->xh_count);\n\tint delta, middle = count / 2;\n\n\t/*\n\t * We start at the middle.  Each step gets farther away in both\n\t * directions.  We therefore hit the change in hash value\n\t * nearest to the middle.  Note that this loop does not execute for\n\t * count < 2.\n\t */\n\tfor (delta = 0; delta < middle; delta++) {\n\t\t/* Let's check delta earlier than middle */\n\t\tif (cmp_xe(&entries[middle - delta - 1],\n\t\t\t   &entries[middle - delta]))\n\t\t\treturn middle - delta;\n\n\t\t/* For even counts, don't walk off the end */\n\t\tif ((middle + delta + 1) == count)\n\t\t\tcontinue;\n\n\t\t/* Now try delta past middle */\n\t\tif (cmp_xe(&entries[middle + delta],\n\t\t\t   &entries[middle + delta + 1]))\n\t\t\treturn middle + delta + 1;\n\t}\n\n\t/* Every entry had the same hash */\n\treturn count;\n}",
        "static int alc269_parse_auto_config(struct hda_codec *codec)\n{\n\tstatic const hda_nid_t alc269_ignore[] = { 0x1d, 0 };\n\tstatic const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 };\n\tstatic const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 };": "static int alc269_parse_auto_config(struct hda_codec *codec)\n{\n\tstatic const hda_nid_t alc269_ignore[] = { 0x1d, 0 };\n\tstatic const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 };\n\tstatic const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 };\n\tstruct alc_spec *spec = codec->spec;\n\tconst hda_nid_t *ssids;\n\n\tswitch (spec->codec_variant) {\n\tcase ALC269_TYPE_ALC269VA:\n\tcase ALC269_TYPE_ALC269VC:\n\tcase ALC269_TYPE_ALC280:\n\tcase ALC269_TYPE_ALC284:\n\tcase ALC269_TYPE_ALC293:\n\t\tssids = alc269va_ssids;\n\t\tbreak;\n\tcase ALC269_TYPE_ALC269VB:\n\tcase ALC269_TYPE_ALC269VD:\n\tcase ALC269_TYPE_ALC282:\n\tcase ALC269_TYPE_ALC283:\n\tcase ALC269_TYPE_ALC286:\n\tcase ALC269_TYPE_ALC298:\n\tcase ALC269_TYPE_ALC255:\n\tcase ALC269_TYPE_ALC256:\n\tcase ALC269_TYPE_ALC257:\n\tcase ALC269_TYPE_ALC215:\n\tcase ALC269_TYPE_ALC225:\n\tcase ALC269_TYPE_ALC245:\n\tcase ALC269_TYPE_ALC287:\n\tcase ALC269_TYPE_ALC294:\n\tcase ALC269_TYPE_ALC300:\n\tcase ALC269_TYPE_ALC623:\n\tcase ALC269_TYPE_ALC700:\n\t\tssids = alc269_ssids;\n\t\tbreak;\n\tdefault:\n\t\tssids = alc269_ssids;\n\t\tbreak;\n\t}\n\n\treturn alc_parse_auto_config(codec, alc269_ignore, ssids);\n}",
        "static int t7xx_dpmaif_add_skb_to_ring(struct dpmaif_ctrl *dpmaif_ctrl, struct sk_buff *skb)\n{\n\tstruct dpmaif_callbacks *cb = dpmaif_ctrl->callbacks;\n\tunsigned int wr_cnt, send_cnt, payload_cnt;\n\tunsigned int cur_idx, drb_wr_idx_backup;": "static int t7xx_dpmaif_add_skb_to_ring(struct dpmaif_ctrl *dpmaif_ctrl, struct sk_buff *skb)\n{\n\tstruct dpmaif_callbacks *cb = dpmaif_ctrl->callbacks;\n\tunsigned int wr_cnt, send_cnt, payload_cnt;\n\tunsigned int cur_idx, drb_wr_idx_backup;\n\tstruct skb_shared_info *shinfo;\n\tstruct dpmaif_tx_queue *txq;\n\tstruct t7xx_skb_cb *skb_cb;\n\tunsigned long flags;\n\n\tskb_cb = T7XX_SKB_CB(skb);\n\ttxq = &dpmaif_ctrl->txq[skb_cb->txq_number];\n\tif (!txq->que_started || dpmaif_ctrl->state != DPMAIF_STATE_PWRON)\n\t\treturn -ENODEV;\n\n\tatomic_set(&txq->tx_processing, 1);\n\t /* Ensure tx_processing is changed to 1 before actually begin TX flow */\n\tsmp_mb();\n\n\tshinfo = skb_shinfo(skb);\n\tif (shinfo->frag_list)\n\t\tdev_warn_ratelimited(dpmaif_ctrl->dev, \"frag_list not supported\\n\");\n\n\tpayload_cnt = shinfo->nr_frags + 1;\n\t/* nr_frags: frag cnt, 1: skb->data, 1: msg DRB */\n\tsend_cnt = payload_cnt + 1;\n\n\tspin_lock_irqsave(&txq->tx_lock, flags);\n\tcur_idx = txq->drb_wr_idx;\n\tdrb_wr_idx_backup = cur_idx;\n\ttxq->drb_wr_idx += send_cnt;\n\tif (txq->drb_wr_idx >= txq->drb_size_cnt)\n\t\ttxq->drb_wr_idx -= txq->drb_size_cnt;\n\tt7xx_setup_msg_drb(dpmaif_ctrl, txq->index, cur_idx, skb->len, 0, skb_cb->netif_idx);\n\tt7xx_record_drb_skb(dpmaif_ctrl, txq->index, cur_idx, skb, true, 0, 0, 0, 0);\n\tspin_unlock_irqrestore(&txq->tx_lock, flags);\n\n\tfor (wr_cnt = 0; wr_cnt < payload_cnt; wr_cnt++) {\n\t\tbool is_frag, is_last_one = wr_cnt == payload_cnt - 1;\n\t\tunsigned int data_len;\n\t\tdma_addr_t bus_addr;\n\t\tvoid *data_addr;\n\n\t\tif (!wr_cnt) {\n\t\t\tdata_len = skb_headlen(skb);\n\t\t\tdata_addr = skb->data;\n\t\t\tis_frag = false;\n\t\t} else {\n\t\t\tskb_frag_t *frag = shinfo->frags + wr_cnt - 1;\n\n\t\t\tdata_len = skb_frag_size(frag);\n\t\t\tdata_addr = skb_frag_address(frag);\n\t\t\tis_frag = true;\n\t\t}\n\n\t\tbus_addr = dma_map_single(dpmaif_ctrl->dev, data_addr, data_len, DMA_TO_DEVICE);\n\t\tif (dma_mapping_error(dpmaif_ctrl->dev, bus_addr))\n\t\t\tgoto unmap_buffers;\n\n\t\tcur_idx = t7xx_ring_buf_get_next_wr_idx(txq->drb_size_cnt, cur_idx);\n\n\t\tspin_lock_irqsave(&txq->tx_lock, flags);\n\t\tt7xx_setup_payload_drb(dpmaif_ctrl, txq->index, cur_idx, bus_addr, data_len,\n\t\t\t\t       is_last_one);\n\t\tt7xx_record_drb_skb(dpmaif_ctrl, txq->index, cur_idx, skb, false, is_frag,\n\t\t\t\t    is_last_one, bus_addr, data_len);\n\t\tspin_unlock_irqrestore(&txq->tx_lock, flags);\n\t}\n\n\tif (atomic_sub_return(send_cnt, &txq->tx_budget) <= (MAX_SKB_FRAGS + 2))\n\t\tcb->state_notify(dpmaif_ctrl->t7xx_dev, DMPAIF_TXQ_STATE_FULL, txq->index);\n\n\tatomic_set(&txq->tx_processing, 0);\n\n\treturn 0;\n\nunmap_buffers:\n\twhile (wr_cnt--) {\n\t\tstruct dpmaif_drb_skb *drb_skb = txq->drb_skb_base;\n\n\t\tcur_idx = cur_idx ? cur_idx - 1 : txq->drb_size_cnt - 1;\n\t\tdrb_skb += cur_idx;\n\t\tdma_unmap_single(dpmaif_ctrl->dev, drb_skb->bus_addr,\n\t\t\t\t drb_skb->data_len, DMA_TO_DEVICE);\n\t}\n\n\ttxq->drb_wr_idx = drb_wr_idx_backup;\n\tatomic_set(&txq->tx_processing, 0);\n\n\treturn -ENOMEM;\n}",
        "static void set_lvb_lock(struct dlm_rsb *r, struct dlm_lkb *lkb)\n{\n\tint b, len = r->res_ls->ls_lvblen;\n\n\t/* b=1 lvb returned to caller": "static void set_lvb_lock(struct dlm_rsb *r, struct dlm_lkb *lkb)\n{\n\tint b, len = r->res_ls->ls_lvblen;\n\n\t/* b=1 lvb returned to caller\n\t   b=0 lvb written to rsb or invalidated\n\t   b=-1 do nothing */\n\n\tb =  dlm_lvb_operations[lkb->lkb_grmode + 1][lkb->lkb_rqmode + 1];\n\n\tif (b == 1) {\n\t\tif (!lkb->lkb_lvbptr)\n\t\t\treturn;\n\n\t\tif (!(lkb->lkb_exflags & DLM_LKF_VALBLK))\n\t\t\treturn;\n\n\t\tif (!r->res_lvbptr)\n\t\t\treturn;\n\n\t\tmemcpy(lkb->lkb_lvbptr, r->res_lvbptr, len);\n\t\tlkb->lkb_lvbseq = r->res_lvbseq;\n\n\t} else if (b == 0) {\n\t\tif (lkb->lkb_exflags & DLM_LKF_IVVALBLK) {\n\t\t\trsb_set_flag(r, RSB_VALNOTVALID);\n\t\t\treturn;\n\t\t}\n\n\t\tif (!lkb->lkb_lvbptr)\n\t\t\treturn;\n\n\t\tif (!(lkb->lkb_exflags & DLM_LKF_VALBLK))\n\t\t\treturn;\n\n\t\tif (!r->res_lvbptr)\n\t\t\tr->res_lvbptr = dlm_allocate_lvb(r->res_ls);\n\n\t\tif (!r->res_lvbptr)\n\t\t\treturn;\n\n\t\tmemcpy(r->res_lvbptr, lkb->lkb_lvbptr, len);\n\t\tr->res_lvbseq++;\n\t\tlkb->lkb_lvbseq = r->res_lvbseq;\n\t\trsb_clear_flag(r, RSB_VALNOTVALID);\n\t}\n\n\tif (rsb_flag(r, RSB_VALNOTVALID))\n\t\tlkb->lkb_sbflags |= DLM_SBF_VALNOTVALID;\n}",
        "static int btfgen_record_obj(struct btfgen_info *info, const char *obj_path)\n{\n\tconst struct btf_ext_info_sec *sec;\n\tconst struct bpf_core_relo *relo;\n\tconst struct btf_ext_info *seg;": "static int btfgen_record_obj(struct btfgen_info *info, const char *obj_path)\n{\n\tconst struct btf_ext_info_sec *sec;\n\tconst struct bpf_core_relo *relo;\n\tconst struct btf_ext_info *seg;\n\tstruct hashmap_entry *entry;\n\tstruct hashmap *cand_cache = NULL;\n\tstruct btf_ext *btf_ext = NULL;\n\tunsigned int relo_idx;\n\tstruct btf *btf = NULL;\n\tsize_t i;\n\tint err;\n\n\tbtf = btf__parse(obj_path, &btf_ext);\n\tif (!btf) {\n\t\terr = -errno;\n\t\tp_err(\"failed to parse BPF object '%s': %s\", obj_path, strerror(errno));\n\t\treturn err;\n\t}\n\n\tif (!btf_ext) {\n\t\tp_err(\"failed to parse BPF object '%s': section %s not found\",\n\t\t      obj_path, BTF_EXT_ELF_SEC);\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tif (btf_ext->core_relo_info.len == 0) {\n\t\terr = 0;\n\t\tgoto out;\n\t}\n\n\tcand_cache = hashmap__new(btfgen_hash_fn, btfgen_equal_fn, NULL);\n\tif (IS_ERR(cand_cache)) {\n\t\terr = PTR_ERR(cand_cache);\n\t\tgoto out;\n\t}\n\n\tseg = &btf_ext->core_relo_info;\n\tfor_each_btf_ext_sec(seg, sec) {\n\t\tfor_each_btf_ext_rec(seg, sec, relo_idx, relo) {\n\t\t\tstruct bpf_core_spec specs_scratch[3] = {};\n\t\t\tstruct bpf_core_relo_res targ_res = {};\n\t\t\tstruct bpf_core_cand_list *cands = NULL;\n\t\t\tconst void *type_key = u32_as_hash_key(relo->type_id);\n\t\t\tconst char *sec_name = btf__name_by_offset(btf, sec->sec_name_off);\n\n\t\t\tif (relo->kind != BPF_CORE_TYPE_ID_LOCAL &&\n\t\t\t    !hashmap__find(cand_cache, type_key, (void **)&cands)) {\n\t\t\t\tcands = btfgen_find_cands(btf, info->src_btf, relo->type_id);\n\t\t\t\tif (!cands) {\n\t\t\t\t\terr = -errno;\n\t\t\t\t\tgoto out;\n\t\t\t\t}\n\n\t\t\t\terr = hashmap__set(cand_cache, type_key, cands, NULL, NULL);\n\t\t\t\tif (err)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\terr = bpf_core_calc_relo_insn(sec_name, relo, relo_idx, btf, cands,\n\t\t\t\t\t\t      specs_scratch, &targ_res);\n\t\t\tif (err)\n\t\t\t\tgoto out;\n\n\t\t\t/* specs_scratch[2] is the target spec */\n\t\t\terr = btfgen_record_reloc(info, &specs_scratch[2]);\n\t\t\tif (err)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\tbtf__free(btf);\n\tbtf_ext__free(btf_ext);\n\n\tif (!IS_ERR_OR_NULL(cand_cache)) {\n\t\thashmap__for_each_entry(cand_cache, entry, i) {\n\t\t\tbpf_core_free_cands(entry->value);\n\t\t}\n\t\thashmap__free(cand_cache);\n\t}\n\n\treturn err;\n}",
        "static int prepare_image(struct memory_bitmap *new_bm, struct memory_bitmap *bm)\n{\n\tunsigned int nr_pages, nr_highmem;\n\tstruct linked_page *lp;\n\tint error;": "static int prepare_image(struct memory_bitmap *new_bm, struct memory_bitmap *bm)\n{\n\tunsigned int nr_pages, nr_highmem;\n\tstruct linked_page *lp;\n\tint error;\n\n\t/* If there is no highmem, the buffer will not be necessary */\n\tfree_image_page(buffer, PG_UNSAFE_CLEAR);\n\tbuffer = NULL;\n\n\tnr_highmem = count_highmem_image_pages(bm);\n\tmark_unsafe_pages(bm);\n\n\terror = memory_bm_create(new_bm, GFP_ATOMIC, PG_SAFE);\n\tif (error)\n\t\tgoto Free;\n\n\tduplicate_memory_bitmap(new_bm, bm);\n\tmemory_bm_free(bm, PG_UNSAFE_KEEP);\n\tif (nr_highmem > 0) {\n\t\terror = prepare_highmem_image(bm, &nr_highmem);\n\t\tif (error)\n\t\t\tgoto Free;\n\t}\n\t/*\n\t * Reserve some safe pages for potential later use.\n\t *\n\t * NOTE: This way we make sure there will be enough safe pages for the\n\t * chain_alloc() in get_buffer().  It is a bit wasteful, but\n\t * nr_copy_pages cannot be greater than 50% of the memory anyway.\n\t *\n\t * nr_copy_pages cannot be less than allocated_unsafe_pages too.\n\t */\n\tnr_pages = nr_copy_pages - nr_highmem - allocated_unsafe_pages;\n\tnr_pages = DIV_ROUND_UP(nr_pages, PBES_PER_LINKED_PAGE);\n\twhile (nr_pages > 0) {\n\t\tlp = get_image_page(GFP_ATOMIC, PG_SAFE);\n\t\tif (!lp) {\n\t\t\terror = -ENOMEM;\n\t\t\tgoto Free;\n\t\t}\n\t\tlp->next = safe_pages_list;\n\t\tsafe_pages_list = lp;\n\t\tnr_pages--;\n\t}\n\t/* Preallocate memory for the image */\n\tnr_pages = nr_copy_pages - nr_highmem - allocated_unsafe_pages;\n\twhile (nr_pages > 0) {\n\t\tlp = (struct linked_page *)get_zeroed_page(GFP_ATOMIC);\n\t\tif (!lp) {\n\t\t\terror = -ENOMEM;\n\t\t\tgoto Free;\n\t\t}\n\t\tif (!swsusp_page_is_free(virt_to_page(lp))) {\n\t\t\t/* The page is \"safe\", add it to the list */\n\t\t\tlp->next = safe_pages_list;\n\t\t\tsafe_pages_list = lp;\n\t\t}\n\t\t/* Mark the page as allocated */\n\t\tswsusp_set_page_forbidden(virt_to_page(lp));\n\t\tswsusp_set_page_free(virt_to_page(lp));\n\t\tnr_pages--;\n\t}\n\treturn 0;\n\n Free:\n\tswsusp_free();\n\treturn error;\n}",
        "static int init_agc(struct drxk_state *state, bool is_dtv)\n{\n\tu16 ingain_tgt = 0;\n\tu16 ingain_tgt_min = 0;\n\tu16 ingain_tgt_max = 0;": "static int init_agc(struct drxk_state *state, bool is_dtv)\n{\n\tu16 ingain_tgt = 0;\n\tu16 ingain_tgt_min = 0;\n\tu16 ingain_tgt_max = 0;\n\tu16 clp_cyclen = 0;\n\tu16 clp_sum_min = 0;\n\tu16 clp_dir_to = 0;\n\tu16 sns_sum_min = 0;\n\tu16 sns_sum_max = 0;\n\tu16 clp_sum_max = 0;\n\tu16 sns_dir_to = 0;\n\tu16 ki_innergain_min = 0;\n\tu16 if_iaccu_hi_tgt = 0;\n\tu16 if_iaccu_hi_tgt_min = 0;\n\tu16 if_iaccu_hi_tgt_max = 0;\n\tu16 data = 0;\n\tu16 fast_clp_ctrl_delay = 0;\n\tu16 clp_ctrl_mode = 0;\n\tint status = 0;\n\n\tdprintk(1, \"\\n\");\n\n\t/* Common settings */\n\tsns_sum_max = 1023;\n\tif_iaccu_hi_tgt_min = 2047;\n\tclp_cyclen = 500;\n\tclp_sum_max = 1023;\n\n\t/* AGCInit() not available for DVBT; init done in microcode */\n\tif (!is_qam(state)) {\n\t\tpr_err(\"%s: mode %d is not DVB-C\\n\",\n\t\t       __func__, state->m_operation_mode);\n\t\treturn -EINVAL;\n\t}\n\n\t/* FIXME: Analog TV AGC require different settings */\n\n\t/* Standard specific settings */\n\tclp_sum_min = 8;\n\tclp_dir_to = (u16) -9;\n\tclp_ctrl_mode = 0;\n\tsns_sum_min = 8;\n\tsns_dir_to = (u16) -9;\n\tki_innergain_min = (u16) -1030;\n\tif_iaccu_hi_tgt_max = 0x2380;\n\tif_iaccu_hi_tgt = 0x2380;\n\tingain_tgt_min = 0x0511;\n\tingain_tgt = 0x0511;\n\tingain_tgt_max = 5119;\n\tfast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;\n\n\tstatus = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,\n\t\t\t fast_clp_ctrl_delay);\n\tif (status < 0)\n\t\tgoto error;\n\n\tstatus = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,\n\t\t\t if_iaccu_hi_tgt_min);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,\n\t\t\t if_iaccu_hi_tgt_max);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);\n\tif (status < 0)\n\t\tgoto error;\n\n\tstatus = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,\n\t\t\t ki_innergain_min);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,\n\t\t\t if_iaccu_hi_tgt);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);\n\tif (status < 0)\n\t\tgoto error;\n\n\tstatus = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);\n\tif (status < 0)\n\t\tgoto error;\n\n\tstatus = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);\n\tif (status < 0)\n\t\tgoto error;\n\n\t/* Initialize inner-loop KI gain factors */\n\tstatus = read16(state, SCU_RAM_AGC_KI__A, &data);\n\tif (status < 0)\n\t\tgoto error;\n\n\tdata = 0x0657;\n\tdata &= ~SCU_RAM_AGC_KI_RF__M;\n\tdata |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);\n\tdata &= ~SCU_RAM_AGC_KI_IF__M;\n\tdata |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);\n\n\tstatus = write16(state, SCU_RAM_AGC_KI__A, data);\nerror:\n\tif (status < 0)\n\t\tpr_err(\"Error %d on %s\\n\", status, __func__);\n\treturn status;\n}",
        "static int t7xx_port_ctrl_tx(struct wwan_port *port, struct sk_buff *skb)\n{\n\tstruct t7xx_port *port_private = wwan_port_get_drvdata(port);\n\tsize_t len, offset, chunk_len = 0, txq_mtu = CLDMA_MTU;\n\tconst struct t7xx_port_conf *port_conf;": "static int t7xx_port_ctrl_tx(struct wwan_port *port, struct sk_buff *skb)\n{\n\tstruct t7xx_port *port_private = wwan_port_get_drvdata(port);\n\tsize_t len, offset, chunk_len = 0, txq_mtu = CLDMA_MTU;\n\tconst struct t7xx_port_conf *port_conf;\n\tstruct t7xx_fsm_ctl *ctl;\n\tenum md_state md_state;\n\n\tlen = skb->len;\n\tif (!len || !port_private->chan_enable)\n\t\treturn -EINVAL;\n\n\tport_conf = port_private->port_conf;\n\tctl = port_private->t7xx_dev->md->fsm_ctl;\n\tmd_state = t7xx_fsm_get_md_state(ctl);\n\tif (md_state == MD_STATE_WAITING_FOR_HS1 || md_state == MD_STATE_WAITING_FOR_HS2) {\n\t\tdev_warn(port_private->dev, \"Cannot write to %s port when md_state=%d\\n\",\n\t\t\t port_conf->name, md_state);\n\t\treturn -ENODEV;\n\t}\n\n\tfor (offset = 0; offset < len; offset += chunk_len) {\n\t\tstruct sk_buff *skb_ccci;\n\t\tint ret;\n\n\t\tchunk_len = min(len - offset, txq_mtu - sizeof(struct ccci_header));\n\t\tskb_ccci = t7xx_port_alloc_skb(chunk_len);\n\t\tif (!skb_ccci)\n\t\t\treturn -ENOMEM;\n\n\t\tskb_put_data(skb_ccci, skb->data + offset, chunk_len);\n\t\tret = t7xx_port_send_skb(port_private, skb_ccci, 0, 0);\n\t\tif (ret) {\n\t\t\tdev_kfree_skb_any(skb_ccci);\n\t\t\tdev_err(port_private->dev, \"Write error on %s port, %d\\n\",\n\t\t\t\tport_conf->name, ret);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tdev_kfree_skb(skb);\n\treturn 0;\n}",
        "static void halbtc8723b1ant_MonitorBtCtr(struct btc_coexist *pBtCoexist)\n{\n\tu32 regHPTxRx, regLPTxRx, u4Tmp;\n\tu32 regHPTx = 0, regHPRx = 0, regLPTx = 0, regLPRx = 0;\n\tstatic u8 NumOfBtCounterChk;": "static void halbtc8723b1ant_MonitorBtCtr(struct btc_coexist *pBtCoexist)\n{\n\tu32 regHPTxRx, regLPTxRx, u4Tmp;\n\tu32 regHPTx = 0, regHPRx = 0, regLPTx = 0, regLPRx = 0;\n\tstatic u8 NumOfBtCounterChk;\n\n       /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */\n\t/* if (! (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e) & 0x8)) */\n\n\tif (pCoexSta->bUnderIps) {\n\t\tpCoexSta->highPriorityTx = 65535;\n\t\tpCoexSta->highPriorityRx = 65535;\n\t\tpCoexSta->lowPriorityTx = 65535;\n\t\tpCoexSta->lowPriorityRx = 65535;\n\t\treturn;\n\t}\n\n\tregHPTxRx = 0x770;\n\tregLPTxRx = 0x774;\n\n\tu4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx);\n\tregHPTx = u4Tmp & bMaskLWord;\n\tregHPRx = (u4Tmp & bMaskHWord) >> 16;\n\n\tu4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx);\n\tregLPTx = u4Tmp & bMaskLWord;\n\tregLPRx = (u4Tmp & bMaskHWord) >> 16;\n\n\tpCoexSta->highPriorityTx = regHPTx;\n\tpCoexSta->highPriorityRx = regHPRx;\n\tpCoexSta->lowPriorityTx = regLPTx;\n\tpCoexSta->lowPriorityRx = regLPRx;\n\n\tif ((pCoexSta->lowPriorityTx >= 1050) && (!pCoexSta->bC2hBtInquiryPage))\n\t\tpCoexSta->popEventCnt++;\n\n\t/*  reset counter */\n\tpBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc);\n\n\tif ((regHPTx == 0) && (regHPRx == 0) && (regLPTx == 0) && (regLPRx == 0)) {\n\t\tNumOfBtCounterChk++;\n\t\tif (NumOfBtCounterChk >= 3) {\n\t\t\thalbtc8723b1ant_QueryBtInfo(pBtCoexist);\n\t\t\tNumOfBtCounterChk = 0;\n\t\t}\n\t}\n}",
        "static int set_var(struct fbtft_par *par)\n{\n\t/* MADCTL - Memory data access control */\n\t/* RGB/BGR can be set with H/W pin SRGB and MADCTL BGR bit */\n#define MY BIT(7)": "static int set_var(struct fbtft_par *par)\n{\n\t/* MADCTL - Memory data access control */\n\t/* RGB/BGR can be set with H/W pin SRGB and MADCTL BGR bit */\n#define MY BIT(7)\n#define MX BIT(6)\n#define MV BIT(5)\n\tswitch (par->info->var.rotate) {\n\tcase 0:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE, par->bgr << 3);\n\t\tbreak;\n\tcase 270:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MX | MV | (par->bgr << 3));\n\t\tbreak;\n\tcase 180:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MX | MY | (par->bgr << 3));\n\t\tbreak;\n\tcase 90:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MY | MV | (par->bgr << 3));\n\t\tbreak;\n\t}\n\n\treturn 0;\n}",
        "static int pt3_fetch_thread(void *data)\n{\n\tstruct pt3_adapter *adap = data;\n\tktime_t delay;\n\tbool was_frozen;": "static int pt3_fetch_thread(void *data)\n{\n\tstruct pt3_adapter *adap = data;\n\tktime_t delay;\n\tbool was_frozen;\n\n#define PT3_INITIAL_BUF_DROPS 4\n#define PT3_FETCH_DELAY 10\n#define PT3_FETCH_DELAY_DELTA 2\n\n\tpt3_init_dmabuf(adap);\n\tadap->num_discard = PT3_INITIAL_BUF_DROPS;\n\n\tdev_dbg(adap->dvb_adap.device, \"PT3: [%s] started\\n\",\n\t\tadap->thread->comm);\n\tset_freezable();\n\twhile (!kthread_freezable_should_stop(&was_frozen)) {\n\t\tif (was_frozen)\n\t\t\tadap->num_discard = PT3_INITIAL_BUF_DROPS;\n\n\t\tpt3_proc_dma(adap);\n\n\t\tdelay = ktime_set(0, PT3_FETCH_DELAY * NSEC_PER_MSEC);\n\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n\t\tfreezable_schedule_hrtimeout_range(&delay,\n\t\t\t\t\tPT3_FETCH_DELAY_DELTA * NSEC_PER_MSEC,\n\t\t\t\t\tHRTIMER_MODE_REL);\n\t}\n\tdev_dbg(adap->dvb_adap.device, \"PT3: [%s] exited\\n\",\n\t\tadap->thread->comm);\n\treturn 0;\n}",
        "static int seg6_local_get_encap_size(struct lwtunnel_state *lwt)\n{\n\tstruct seg6_local_lwt *slwt = seg6_local_lwtunnel(lwt);\n\tunsigned long attrs;\n\tint nlsize;": "static int seg6_local_get_encap_size(struct lwtunnel_state *lwt)\n{\n\tstruct seg6_local_lwt *slwt = seg6_local_lwtunnel(lwt);\n\tunsigned long attrs;\n\tint nlsize;\n\n\tnlsize = nla_total_size(4); /* action */\n\n\tattrs = slwt->desc->attrs | slwt->parsed_optattrs;\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_SRH))\n\t\tnlsize += nla_total_size((slwt->srh->hdrlen + 1) << 3);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_TABLE))\n\t\tnlsize += nla_total_size(4);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_NH4))\n\t\tnlsize += nla_total_size(4);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_NH6))\n\t\tnlsize += nla_total_size(16);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_IIF))\n\t\tnlsize += nla_total_size(4);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_OIF))\n\t\tnlsize += nla_total_size(4);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_BPF))\n\t\tnlsize += nla_total_size(sizeof(struct nlattr)) +\n\t\t       nla_total_size(MAX_PROG_NAME) +\n\t\t       nla_total_size(4);\n\n\tif (attrs & SEG6_F_ATTR(SEG6_LOCAL_VRFTABLE))\n\t\tnlsize += nla_total_size(4);\n\n\tif (attrs & SEG6_F_LOCAL_COUNTERS)\n\t\tnlsize += nla_total_size(0) + /* nest SEG6_LOCAL_COUNTERS */\n\t\t\t  /* SEG6_LOCAL_CNT_PACKETS */\n\t\t\t  nla_total_size_64bit(sizeof(__u64)) +\n\t\t\t  /* SEG6_LOCAL_CNT_BYTES */\n\t\t\t  nla_total_size_64bit(sizeof(__u64)) +\n\t\t\t  /* SEG6_LOCAL_CNT_ERRORS */\n\t\t\t  nla_total_size_64bit(sizeof(__u64));\n\n\treturn nlsize;\n}",
        "static void pipapo_gc(const struct nft_set *set, struct nft_pipapo_match *m)\n{\n\tstruct nft_pipapo *priv = nft_set_priv(set);\n\tint rules_f0, first_rule = 0;\n\tstruct nft_pipapo_elem *e;": "static void pipapo_gc(const struct nft_set *set, struct nft_pipapo_match *m)\n{\n\tstruct nft_pipapo *priv = nft_set_priv(set);\n\tint rules_f0, first_rule = 0;\n\tstruct nft_pipapo_elem *e;\n\n\twhile ((rules_f0 = pipapo_rules_same_key(m->f, first_rule))) {\n\t\tunion nft_pipapo_map_bucket rulemap[NFT_PIPAPO_MAX_FIELDS];\n\t\tstruct nft_pipapo_field *f;\n\t\tint i, start, rules_fx;\n\n\t\tstart = first_rule;\n\t\trules_fx = rules_f0;\n\n\t\tnft_pipapo_for_each_field(f, i, m) {\n\t\t\trulemap[i].to = start;\n\t\t\trulemap[i].n = rules_fx;\n\n\t\t\tif (i < m->field_count - 1) {\n\t\t\t\trules_fx = f->mt[start].n;\n\t\t\t\tstart = f->mt[start].to;\n\t\t\t}\n\t\t}\n\n\t\t/* Pick the last field, and its last index */\n\t\tf--;\n\t\ti--;\n\t\te = f->mt[rulemap[i].to].e;\n\t\tif (nft_set_elem_expired(&e->ext) &&\n\t\t    !nft_set_elem_mark_busy(&e->ext)) {\n\t\t\tpriv->dirty = true;\n\t\t\tpipapo_drop(m, rulemap);\n\n\t\t\trcu_barrier();\n\t\t\tnft_set_elem_destroy(set, e, true);\n\n\t\t\t/* And check again current first rule, which is now the\n\t\t\t * first we haven't checked.\n\t\t\t */\n\t\t} else {\n\t\t\tfirst_rule += rules_f0;\n\t\t}\n\t}\n\n\te = nft_set_catchall_gc(set);\n\tif (e)\n\t\tnft_set_elem_destroy(set, e, true);\n\n\tpriv->last_gc = jiffies;\n}",
        "static void xsk_mmap_offsets_v1(struct xdp_mmap_offsets *off)\n{\n\tstruct xdp_mmap_offsets_v1 off_v1;\n\n\t/* getsockopt on a kernel <= 5.3 has no flags fields.": "static void xsk_mmap_offsets_v1(struct xdp_mmap_offsets *off)\n{\n\tstruct xdp_mmap_offsets_v1 off_v1;\n\n\t/* getsockopt on a kernel <= 5.3 has no flags fields.\n\t * Copy over the offsets to the correct places in the >=5.4 format\n\t * and put the flags where they would have been on that kernel.\n\t */\n\tmemcpy(&off_v1, off, sizeof(off_v1));\n\n\toff->rx.producer = off_v1.rx.producer;\n\toff->rx.consumer = off_v1.rx.consumer;\n\toff->rx.desc = off_v1.rx.desc;\n\toff->rx.flags = off_v1.rx.consumer + sizeof(__u32);\n\n\toff->tx.producer = off_v1.tx.producer;\n\toff->tx.consumer = off_v1.tx.consumer;\n\toff->tx.desc = off_v1.tx.desc;\n\toff->tx.flags = off_v1.tx.consumer + sizeof(__u32);\n\n\toff->fr.producer = off_v1.fr.producer;\n\toff->fr.consumer = off_v1.fr.consumer;\n\toff->fr.desc = off_v1.fr.desc;\n\toff->fr.flags = off_v1.fr.consumer + sizeof(__u32);\n\n\toff->cr.producer = off_v1.cr.producer;\n\toff->cr.consumer = off_v1.cr.consumer;\n\toff->cr.desc = off_v1.cr.desc;\n\toff->cr.flags = off_v1.cr.consumer + sizeof(__u32);\n}",
        "static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line)\n{\n\tu32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat;\n\tu32 reg;\n\tu16 input, output;": "static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line)\n{\n\tu32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat;\n\tu32 reg;\n\tu16 input, output;\n\tu8 interp_reso;\n\tu32 phase_mult;\n\n\twritel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);\n\n\tinput = line->fmt[MSM_VFE_PAD_SINK].width;\n\toutput = line->compose.width;\n\treg = (output << 16) | input;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);\n\n\tinterp_reso = vfe_calc_interp_reso(input, output);\n\tphase_mult = input * (1 << (13 + interp_reso)) / output;\n\treg = (interp_reso << 20) | phase_mult;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);\n\n\tinput = line->fmt[MSM_VFE_PAD_SINK].height;\n\toutput = line->compose.height;\n\treg = (output << 16) | input;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);\n\n\tinterp_reso = vfe_calc_interp_reso(input, output);\n\tphase_mult = input * (1 << (13 + interp_reso)) / output;\n\treg = (interp_reso << 20) | phase_mult;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);\n\n\twritel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);\n\n\tinput = line->fmt[MSM_VFE_PAD_SINK].width;\n\toutput = line->compose.width / 2;\n\treg = (output << 16) | input;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);\n\n\tinterp_reso = vfe_calc_interp_reso(input, output);\n\tphase_mult = input * (1 << (13 + interp_reso)) / output;\n\treg = (interp_reso << 20) | phase_mult;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);\n\n\tinput = line->fmt[MSM_VFE_PAD_SINK].height;\n\toutput = line->compose.height;\n\tif (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21)\n\t\toutput = line->compose.height / 2;\n\treg = (output << 16) | input;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);\n\n\tinterp_reso = vfe_calc_interp_reso(input, output);\n\tphase_mult = input * (1 << (13 + interp_reso)) / output;\n\treg = (interp_reso << 20) | phase_mult;\n\twritel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);\n}",
        "static void ssh_rtl_tx_work_fn(struct work_struct *work)\n{\n\tstruct ssh_rtl *rtl = to_ssh_rtl(work, tx.work);\n\tunsigned int iterations = SSH_RTL_TX_BATCH;\n\tint status;": "static void ssh_rtl_tx_work_fn(struct work_struct *work)\n{\n\tstruct ssh_rtl *rtl = to_ssh_rtl(work, tx.work);\n\tunsigned int iterations = SSH_RTL_TX_BATCH;\n\tint status;\n\n\t/*\n\t * Try to be nice and not block/live-lock the workqueue: Run a maximum\n\t * of 10 tries, then re-submit if necessary. This should not be\n\t * necessary for normal execution, but guarantee it anyway.\n\t */\n\tdo {\n\t\tstatus = ssh_rtl_tx_try_process_one(rtl);\n\t\tif (status == -ENOENT || status == -EBUSY)\n\t\t\treturn;\t\t/* No more requests to process. */\n\n\t\tif (status == -ESHUTDOWN) {\n\t\t\t/*\n\t\t\t * Packet system shutting down. No new packets can be\n\t\t\t * transmitted. Return silently, the party initiating\n\t\t\t * the shutdown should handle the rest.\n\t\t\t */\n\t\t\treturn;\n\t\t}\n\n\t\tWARN_ON(status != 0 && status != -EAGAIN);\n\t} while (--iterations);\n\n\t/* Out of tries, reschedule. */\n\tssh_rtl_tx_schedule(rtl);\n}",
        "static long ionic_phc_aux_work(struct ptp_clock_info *info)\n{\n\tstruct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);\n\tstruct ionic_admin_ctx ctx = {};\n\tunsigned long irqflags;": "static long ionic_phc_aux_work(struct ptp_clock_info *info)\n{\n\tstruct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);\n\tstruct ionic_admin_ctx ctx = {};\n\tunsigned long irqflags;\n\tint err;\n\n\t/* Do not update phc during device upgrade, but keep polling to resume\n\t * after upgrade.  Since we don't update the point in time basis, there\n\t * is no expectation that we are maintaining the phc time during the\n\t * upgrade.  After upgrade, it will need to be readjusted back to the\n\t * correct time by the ptp daemon.\n\t */\n\tif (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))\n\t\treturn phc->aux_work_delay;\n\n\tspin_lock_irqsave(&phc->lock, irqflags);\n\n\t/* update point-in-time basis to now */\n\ttimecounter_read(&phc->tc);\n\n\t/* Setphc commands are posted in-order, sequenced by phc->lock.  We\n\t * need to drop the lock before waiting for the command to complete.\n\t */\n\terr = ionic_setphc_cmd(phc, &ctx);\n\n\tspin_unlock_irqrestore(&phc->lock, irqflags);\n\n\tionic_adminq_wait(phc->lif, &ctx, err, true);\n\n\treturn phc->aux_work_delay;\n}",
        "static int do_misc_fixups(struct bpf_verifier_env *env)\n{\n\tstruct bpf_prog *prog = env->prog;\n\tenum bpf_attach_type eatype = prog->expected_attach_type;\n\tenum bpf_prog_type prog_type = resolve_prog_type(prog);": "static int do_misc_fixups(struct bpf_verifier_env *env)\n{\n\tstruct bpf_prog *prog = env->prog;\n\tenum bpf_attach_type eatype = prog->expected_attach_type;\n\tenum bpf_prog_type prog_type = resolve_prog_type(prog);\n\tstruct bpf_insn *insn = prog->insnsi;\n\tconst struct bpf_func_proto *fn;\n\tconst int insn_cnt = prog->len;\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_insn_aux_data *aux;\n\tstruct bpf_insn insn_buf[16];\n\tstruct bpf_prog *new_prog;\n\tstruct bpf_map *map_ptr;\n\tint i, ret, cnt, delta = 0;\n\n\tfor (i = 0; i < insn_cnt; i++, insn++) {\n\t\t/* Make divide-by-zero exceptions impossible. */\n\t\tif (insn->code == (BPF_ALU64 | BPF_MOD | BPF_X) ||\n\t\t    insn->code == (BPF_ALU64 | BPF_DIV | BPF_X) ||\n\t\t    insn->code == (BPF_ALU | BPF_MOD | BPF_X) ||\n\t\t    insn->code == (BPF_ALU | BPF_DIV | BPF_X)) {\n\t\t\tbool is64 = BPF_CLASS(insn->code) == BPF_ALU64;\n\t\t\tbool isdiv = BPF_OP(insn->code) == BPF_DIV;\n\t\t\tstruct bpf_insn *patchlet;\n\t\t\tstruct bpf_insn chk_and_div[] = {\n\t\t\t\t/* [R,W]x div 0 -> 0 */\n\t\t\t\tBPF_RAW_INSN((is64 ? BPF_JMP : BPF_JMP32) |\n\t\t\t\t\t     BPF_JNE | BPF_K, insn->src_reg,\n\t\t\t\t\t     0, 2, 0),\n\t\t\t\tBPF_ALU32_REG(BPF_XOR, insn->dst_reg, insn->dst_reg),\n\t\t\t\tBPF_JMP_IMM(BPF_JA, 0, 0, 1),\n\t\t\t\t*insn,\n\t\t\t};\n\t\t\tstruct bpf_insn chk_and_mod[] = {\n\t\t\t\t/* [R,W]x mod 0 -> [R,W]x */\n\t\t\t\tBPF_RAW_INSN((is64 ? BPF_JMP : BPF_JMP32) |\n\t\t\t\t\t     BPF_JEQ | BPF_K, insn->src_reg,\n\t\t\t\t\t     0, 1 + (is64 ? 0 : 1), 0),\n\t\t\t\t*insn,\n\t\t\t\tBPF_JMP_IMM(BPF_JA, 0, 0, 1),\n\t\t\t\tBPF_MOV32_REG(insn->dst_reg, insn->dst_reg),\n\t\t\t};\n\n\t\t\tpatchlet = isdiv ? chk_and_div : chk_and_mod;\n\t\t\tcnt = isdiv ? ARRAY_SIZE(chk_and_div) :\n\t\t\t\t      ARRAY_SIZE(chk_and_mod) - (is64 ? 2 : 0);\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, patchlet, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Implement LD_ABS and LD_IND with a rewrite, if supported by the program type. */\n\t\tif (BPF_CLASS(insn->code) == BPF_LD &&\n\t\t    (BPF_MODE(insn->code) == BPF_ABS ||\n\t\t     BPF_MODE(insn->code) == BPF_IND)) {\n\t\t\tcnt = env->ops->gen_ld_abs(insn, insn_buf);\n\t\t\tif (cnt == 0 || cnt >= ARRAY_SIZE(insn_buf)) {\n\t\t\t\tverbose(env, \"bpf verifier is misconfigured\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Rewrite pointer arithmetic to mitigate speculation attacks. */\n\t\tif (insn->code == (BPF_ALU64 | BPF_ADD | BPF_X) ||\n\t\t    insn->code == (BPF_ALU64 | BPF_SUB | BPF_X)) {\n\t\t\tconst u8 code_add = BPF_ALU64 | BPF_ADD | BPF_X;\n\t\t\tconst u8 code_sub = BPF_ALU64 | BPF_SUB | BPF_X;\n\t\t\tstruct bpf_insn *patch = &insn_buf[0];\n\t\t\tbool issrc, isneg, isimm;\n\t\t\tu32 off_reg;\n\n\t\t\taux = &env->insn_aux_data[i + delta];\n\t\t\tif (!aux->alu_state ||\n\t\t\t    aux->alu_state == BPF_ALU_NON_POINTER)\n\t\t\t\tcontinue;\n\n\t\t\tisneg = aux->alu_state & BPF_ALU_NEG_VALUE;\n\t\t\tissrc = (aux->alu_state & BPF_ALU_SANITIZE) ==\n\t\t\t\tBPF_ALU_SANITIZE_SRC;\n\t\t\tisimm = aux->alu_state & BPF_ALU_IMMEDIATE;\n\n\t\t\toff_reg = issrc ? insn->src_reg : insn->dst_reg;\n\t\t\tif (isimm) {\n\t\t\t\t*patch++ = BPF_MOV32_IMM(BPF_REG_AX, aux->alu_limit);\n\t\t\t} else {\n\t\t\t\tif (isneg)\n\t\t\t\t\t*patch++ = BPF_ALU64_IMM(BPF_MUL, off_reg, -1);\n\t\t\t\t*patch++ = BPF_MOV32_IMM(BPF_REG_AX, aux->alu_limit);\n\t\t\t\t*patch++ = BPF_ALU64_REG(BPF_SUB, BPF_REG_AX, off_reg);\n\t\t\t\t*patch++ = BPF_ALU64_REG(BPF_OR, BPF_REG_AX, off_reg);\n\t\t\t\t*patch++ = BPF_ALU64_IMM(BPF_NEG, BPF_REG_AX, 0);\n\t\t\t\t*patch++ = BPF_ALU64_IMM(BPF_ARSH, BPF_REG_AX, 63);\n\t\t\t\t*patch++ = BPF_ALU64_REG(BPF_AND, BPF_REG_AX, off_reg);\n\t\t\t}\n\t\t\tif (!issrc)\n\t\t\t\t*patch++ = BPF_MOV64_REG(insn->dst_reg, insn->src_reg);\n\t\t\tinsn->src_reg = BPF_REG_AX;\n\t\t\tif (isneg)\n\t\t\t\tinsn->code = insn->code == code_add ?\n\t\t\t\t\t     code_sub : code_add;\n\t\t\t*patch++ = *insn;\n\t\t\tif (issrc && isneg && !isimm)\n\t\t\t\t*patch++ = BPF_ALU64_IMM(BPF_MUL, off_reg, -1);\n\t\t\tcnt = patch - insn_buf;\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (insn->code != (BPF_JMP | BPF_CALL))\n\t\t\tcontinue;\n\t\tif (insn->src_reg == BPF_PSEUDO_CALL)\n\t\t\tcontinue;\n\t\tif (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) {\n\t\t\tret = fixup_kfunc_call(env, insn);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (insn->imm == BPF_FUNC_get_route_realm)\n\t\t\tprog->dst_needed = 1;\n\t\tif (insn->imm == BPF_FUNC_get_prandom_u32)\n\t\t\tbpf_user_rnd_init_once();\n\t\tif (insn->imm == BPF_FUNC_override_return)\n\t\t\tprog->kprobe_override = 1;\n\t\tif (insn->imm == BPF_FUNC_tail_call) {\n\t\t\t/* If we tail call into other programs, we\n\t\t\t * cannot make any assumptions since they can\n\t\t\t * be replaced dynamically during runtime in\n\t\t\t * the program array.\n\t\t\t */\n\t\t\tprog->cb_access = 1;\n\t\t\tif (!allow_tail_call_in_subprogs(env))\n\t\t\t\tprog->aux->stack_depth = MAX_BPF_STACK;\n\t\t\tprog->aux->max_pkt_offset = MAX_PACKET_OFF;\n\n\t\t\t/* mark bpf_tail_call as different opcode to avoid\n\t\t\t * conditional branch in the interpreter for every normal\n\t\t\t * call and to prevent accidental JITing by JIT compiler\n\t\t\t * that doesn't support bpf_tail_call yet\n\t\t\t */\n\t\t\tinsn->imm = 0;\n\t\t\tinsn->code = BPF_JMP | BPF_TAIL_CALL;\n\n\t\t\taux = &env->insn_aux_data[i + delta];\n\t\t\tif (env->bpf_capable && !prog->blinding_requested &&\n\t\t\t    prog->jit_requested &&\n\t\t\t    !bpf_map_key_poisoned(aux) &&\n\t\t\t    !bpf_map_ptr_poisoned(aux) &&\n\t\t\t    !bpf_map_ptr_unpriv(aux)) {\n\t\t\t\tstruct bpf_jit_poke_descriptor desc = {\n\t\t\t\t\t.reason = BPF_POKE_REASON_TAIL_CALL,\n\t\t\t\t\t.tail_call.map = BPF_MAP_PTR(aux->map_ptr_state),\n\t\t\t\t\t.tail_call.key = bpf_map_key_immediate(aux),\n\t\t\t\t\t.insn_idx = i + delta,\n\t\t\t\t};\n\n\t\t\t\tret = bpf_jit_add_poke_descriptor(prog, &desc);\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tverbose(env, \"adding tail call poke descriptor failed\\n\");\n\t\t\t\t\treturn ret;\n\t\t\t\t}\n\n\t\t\t\tinsn->imm = ret + 1;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (!bpf_map_ptr_unpriv(aux))\n\t\t\t\tcontinue;\n\n\t\t\t/* instead of changing every JIT dealing with tail_call\n\t\t\t * emit two extra insns:\n\t\t\t * if (index >= max_entries) goto out;\n\t\t\t * index &= array->index_mask;\n\t\t\t * to avoid out-of-bounds cpu speculation\n\t\t\t */\n\t\t\tif (bpf_map_ptr_poisoned(aux)) {\n\t\t\t\tverbose(env, \"tail_call abusing map_ptr\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tmap_ptr = BPF_MAP_PTR(aux->map_ptr_state);\n\t\t\tinsn_buf[0] = BPF_JMP_IMM(BPF_JGE, BPF_REG_3,\n\t\t\t\t\t\t  map_ptr->max_entries, 2);\n\t\t\tinsn_buf[1] = BPF_ALU32_IMM(BPF_AND, BPF_REG_3,\n\t\t\t\t\t\t    container_of(map_ptr,\n\t\t\t\t\t\t\t\t struct bpf_array,\n\t\t\t\t\t\t\t\t map)->index_mask);\n\t\t\tinsn_buf[2] = *insn;\n\t\t\tcnt = 3;\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (insn->imm == BPF_FUNC_timer_set_callback) {\n\t\t\t/* The verifier will process callback_fn as many times as necessary\n\t\t\t * with different maps and the register states prepared by\n\t\t\t * set_timer_callback_state will be accurate.\n\t\t\t *\n\t\t\t * The following use case is valid:\n\t\t\t *   map1 is shared by prog1, prog2, prog3.\n\t\t\t *   prog1 calls bpf_timer_init for some map1 elements\n\t\t\t *   prog2 calls bpf_timer_set_callback for some map1 elements.\n\t\t\t *     Those that were not bpf_timer_init-ed will return -EINVAL.\n\t\t\t *   prog3 calls bpf_timer_start for some map1 elements.\n\t\t\t *     Those that were not both bpf_timer_init-ed and\n\t\t\t *     bpf_timer_set_callback-ed will return -EINVAL.\n\t\t\t */\n\t\t\tstruct bpf_insn ld_addrs[2] = {\n\t\t\t\tBPF_LD_IMM64(BPF_REG_3, (long)prog->aux),\n\t\t\t};\n\n\t\t\tinsn_buf[0] = ld_addrs[0];\n\t\t\tinsn_buf[1] = ld_addrs[1];\n\t\t\tinsn_buf[2] = *insn;\n\t\t\tcnt = 3;\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tgoto patch_call_imm;\n\t\t}\n\n\t\tif (insn->imm == BPF_FUNC_task_storage_get ||\n\t\t    insn->imm == BPF_FUNC_sk_storage_get ||\n\t\t    insn->imm == BPF_FUNC_inode_storage_get) {\n\t\t\tif (env->prog->aux->sleepable)\n\t\t\t\tinsn_buf[0] = BPF_MOV64_IMM(BPF_REG_5, (__force __s32)GFP_KERNEL);\n\t\t\telse\n\t\t\t\tinsn_buf[0] = BPF_MOV64_IMM(BPF_REG_5, (__force __s32)GFP_ATOMIC);\n\t\t\tinsn_buf[1] = *insn;\n\t\t\tcnt = 2;\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn = new_prog->insnsi + i + delta;\n\t\t\tgoto patch_call_imm;\n\t\t}\n\n\t\t/* BPF_EMIT_CALL() assumptions in some of the map_gen_lookup\n\t\t * and other inlining handlers are currently limited to 64 bit\n\t\t * only.\n\t\t */\n\t\tif (prog->jit_requested && BITS_PER_LONG == 64 &&\n\t\t    (insn->imm == BPF_FUNC_map_lookup_elem ||\n\t\t     insn->imm == BPF_FUNC_map_update_elem ||\n\t\t     insn->imm == BPF_FUNC_map_delete_elem ||\n\t\t     insn->imm == BPF_FUNC_map_push_elem   ||\n\t\t     insn->imm == BPF_FUNC_map_pop_elem    ||\n\t\t     insn->imm == BPF_FUNC_map_peek_elem   ||\n\t\t     insn->imm == BPF_FUNC_redirect_map    ||\n\t\t     insn->imm == BPF_FUNC_for_each_map_elem ||\n\t\t     insn->imm == BPF_FUNC_map_lookup_percpu_elem)) {\n\t\t\taux = &env->insn_aux_data[i + delta];\n\t\t\tif (bpf_map_ptr_poisoned(aux))\n\t\t\t\tgoto patch_call_imm;\n\n\t\t\tmap_ptr = BPF_MAP_PTR(aux->map_ptr_state);\n\t\t\tops = map_ptr->ops;\n\t\t\tif (insn->imm == BPF_FUNC_map_lookup_elem &&\n\t\t\t    ops->map_gen_lookup) {\n\t\t\t\tcnt = ops->map_gen_lookup(map_ptr, insn_buf);\n\t\t\t\tif (cnt == -EOPNOTSUPP)\n\t\t\t\t\tgoto patch_map_ops_generic;\n\t\t\t\tif (cnt <= 0 || cnt >= ARRAY_SIZE(insn_buf)) {\n\t\t\t\t\tverbose(env, \"bpf verifier is misconfigured\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\n\t\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta,\n\t\t\t\t\t\t\t       insn_buf, cnt);\n\t\t\t\tif (!new_prog)\n\t\t\t\t\treturn -ENOMEM;\n\n\t\t\t\tdelta    += cnt - 1;\n\t\t\t\tenv->prog = prog = new_prog;\n\t\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_lookup_elem,\n\t\t\t\t     (void *(*)(struct bpf_map *map, void *key))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_delete_elem,\n\t\t\t\t     (int (*)(struct bpf_map *map, void *key))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_update_elem,\n\t\t\t\t     (int (*)(struct bpf_map *map, void *key, void *value,\n\t\t\t\t\t      u64 flags))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_push_elem,\n\t\t\t\t     (int (*)(struct bpf_map *map, void *value,\n\t\t\t\t\t      u64 flags))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_pop_elem,\n\t\t\t\t     (int (*)(struct bpf_map *map, void *value))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_peek_elem,\n\t\t\t\t     (int (*)(struct bpf_map *map, void *value))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_redirect,\n\t\t\t\t     (int (*)(struct bpf_map *map, u32 ifindex, u64 flags))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_for_each_callback,\n\t\t\t\t     (int (*)(struct bpf_map *map,\n\t\t\t\t\t      bpf_callback_t callback_fn,\n\t\t\t\t\t      void *callback_ctx,\n\t\t\t\t\t      u64 flags))NULL));\n\t\t\tBUILD_BUG_ON(!__same_type(ops->map_lookup_percpu_elem,\n\t\t\t\t     (void *(*)(struct bpf_map *map, void *key, u32 cpu))NULL));\n\npatch_map_ops_generic:\n\t\t\tswitch (insn->imm) {\n\t\t\tcase BPF_FUNC_map_lookup_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_lookup_elem);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_map_update_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_update_elem);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_map_delete_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_delete_elem);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_map_push_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_push_elem);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_map_pop_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_pop_elem);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_map_peek_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_peek_elem);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_redirect_map:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_redirect);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_for_each_map_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_for_each_callback);\n\t\t\t\tcontinue;\n\t\t\tcase BPF_FUNC_map_lookup_percpu_elem:\n\t\t\t\tinsn->imm = BPF_CALL_IMM(ops->map_lookup_percpu_elem);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tgoto patch_call_imm;\n\t\t}\n\n\t\t/* Implement bpf_jiffies64 inline. */\n\t\tif (prog->jit_requested && BITS_PER_LONG == 64 &&\n\t\t    insn->imm == BPF_FUNC_jiffies64) {\n\t\t\tstruct bpf_insn ld_jiffies_addr[2] = {\n\t\t\t\tBPF_LD_IMM64(BPF_REG_0,\n\t\t\t\t\t     (unsigned long)&jiffies),\n\t\t\t};\n\n\t\t\tinsn_buf[0] = ld_jiffies_addr[0];\n\t\t\tinsn_buf[1] = ld_jiffies_addr[1];\n\t\t\tinsn_buf[2] = BPF_LDX_MEM(BPF_DW, BPF_REG_0,\n\t\t\t\t\t\t  BPF_REG_0, 0);\n\t\t\tcnt = 3;\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf,\n\t\t\t\t\t\t       cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Implement bpf_get_func_arg inline. */\n\t\tif (prog_type == BPF_PROG_TYPE_TRACING &&\n\t\t    insn->imm == BPF_FUNC_get_func_arg) {\n\t\t\t/* Load nr_args from ctx - 8 */\n\t\t\tinsn_buf[0] = BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1, -8);\n\t\t\tinsn_buf[1] = BPF_JMP32_REG(BPF_JGE, BPF_REG_2, BPF_REG_0, 6);\n\t\t\tinsn_buf[2] = BPF_ALU64_IMM(BPF_LSH, BPF_REG_2, 3);\n\t\t\tinsn_buf[3] = BPF_ALU64_REG(BPF_ADD, BPF_REG_2, BPF_REG_1);\n\t\t\tinsn_buf[4] = BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_2, 0);\n\t\t\tinsn_buf[5] = BPF_STX_MEM(BPF_DW, BPF_REG_3, BPF_REG_0, 0);\n\t\t\tinsn_buf[6] = BPF_MOV64_IMM(BPF_REG_0, 0);\n\t\t\tinsn_buf[7] = BPF_JMP_A(1);\n\t\t\tinsn_buf[8] = BPF_MOV64_IMM(BPF_REG_0, -EINVAL);\n\t\t\tcnt = 9;\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Implement bpf_get_func_ret inline. */\n\t\tif (prog_type == BPF_PROG_TYPE_TRACING &&\n\t\t    insn->imm == BPF_FUNC_get_func_ret) {\n\t\t\tif (eatype == BPF_TRACE_FEXIT ||\n\t\t\t    eatype == BPF_MODIFY_RETURN) {\n\t\t\t\t/* Load nr_args from ctx - 8 */\n\t\t\t\tinsn_buf[0] = BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1, -8);\n\t\t\t\tinsn_buf[1] = BPF_ALU64_IMM(BPF_LSH, BPF_REG_0, 3);\n\t\t\t\tinsn_buf[2] = BPF_ALU64_REG(BPF_ADD, BPF_REG_0, BPF_REG_1);\n\t\t\t\tinsn_buf[3] = BPF_LDX_MEM(BPF_DW, BPF_REG_3, BPF_REG_0, 0);\n\t\t\t\tinsn_buf[4] = BPF_STX_MEM(BPF_DW, BPF_REG_2, BPF_REG_3, 0);\n\t\t\t\tinsn_buf[5] = BPF_MOV64_IMM(BPF_REG_0, 0);\n\t\t\t\tcnt = 6;\n\t\t\t} else {\n\t\t\t\tinsn_buf[0] = BPF_MOV64_IMM(BPF_REG_0, -EOPNOTSUPP);\n\t\t\t\tcnt = 1;\n\t\t\t}\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, cnt);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tdelta    += cnt - 1;\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Implement get_func_arg_cnt inline. */\n\t\tif (prog_type == BPF_PROG_TYPE_TRACING &&\n\t\t    insn->imm == BPF_FUNC_get_func_arg_cnt) {\n\t\t\t/* Load nr_args from ctx - 8 */\n\t\t\tinsn_buf[0] = BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1, -8);\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, 1);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Implement bpf_get_func_ip inline. */\n\t\tif (prog_type == BPF_PROG_TYPE_TRACING &&\n\t\t    insn->imm == BPF_FUNC_get_func_ip) {\n\t\t\t/* Load IP address from ctx - 16 */\n\t\t\tinsn_buf[0] = BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1, -16);\n\n\t\t\tnew_prog = bpf_patch_insn_data(env, i + delta, insn_buf, 1);\n\t\t\tif (!new_prog)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tenv->prog = prog = new_prog;\n\t\t\tinsn      = new_prog->insnsi + i + delta;\n\t\t\tcontinue;\n\t\t}\n\npatch_call_imm:\n\t\tfn = env->ops->get_func_proto(insn->imm, env->prog);\n\t\t/* all functions that have prototype and verifier allowed\n\t\t * programs to call them, must be real in-kernel functions\n\t\t */\n\t\tif (!fn->func) {\n\t\t\tverbose(env,\n\t\t\t\t\"kernel subsystem misconfigured func %s#%d\\n\",\n\t\t\t\tfunc_id_name(insn->imm), insn->imm);\n\t\t\treturn -EFAULT;\n\t\t}\n\t\tinsn->imm = fn->func - __bpf_call_base;\n\t}\n\n\t/* Since poke tab is now finalized, publish aux to tracker. */\n\tfor (i = 0; i < prog->aux->size_poke_tab; i++) {\n\t\tmap_ptr = prog->aux->poke_tab[i].tail_call.map;\n\t\tif (!map_ptr->ops->map_poke_track ||\n\t\t    !map_ptr->ops->map_poke_untrack ||\n\t\t    !map_ptr->ops->map_poke_run) {\n\t\t\tverbose(env, \"bpf verifier is misconfigured\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tret = map_ptr->ops->map_poke_track(map_ptr, prog->aux);\n\t\tif (ret < 0) {\n\t\t\tverbose(env, \"tracking tail call prog failed\\n\");\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tsort_kfunc_descs_by_imm(env->prog);\n\n\treturn 0;\n}",
        "static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)\n{\n\tstruct regmap *regmap = isc->regmap;\n\tstruct isc_ctrls *ctrls = &isc->ctrls;\n\tu32 val, bay_cfg;": "static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)\n{\n\tstruct regmap *regmap = isc->regmap;\n\tstruct isc_ctrls *ctrls = &isc->ctrls;\n\tu32 val, bay_cfg;\n\tconst u32 *gamma;\n\tunsigned int i;\n\n\t/* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */\n\tfor (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {\n\t\tval = pipeline & BIT(i) ? 1 : 0;\n\t\tregmap_field_write(isc->pipeline[i], val);\n\t}\n\n\tif (!pipeline)\n\t\treturn;\n\n\tbay_cfg = isc->config.sd_format->cfa_baycfg;\n\n\tregmap_write(regmap, ISC_WB_CFG, bay_cfg);\n\tisc_update_awb_ctrls(isc);\n\tisc_update_v4l2_ctrls(isc);\n\n\tregmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);\n\n\tgamma = &isc->gamma_table[ctrls->gamma_index][0];\n\tregmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);\n\tregmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);\n\tregmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);\n\n\tisc->config_dpc(isc);\n\tisc->config_csc(isc);\n\tisc->config_cbc(isc);\n\tisc->config_cc(isc);\n\tisc->config_gam(isc);\n}",
        "static void *vidtv_s302m_encode(struct vidtv_encoder *e)\n{\n\tstruct vidtv_s302m_ctx *ctx = e->ctx;\n\n\t/*": "static void *vidtv_s302m_encode(struct vidtv_encoder *e)\n{\n\tstruct vidtv_s302m_ctx *ctx = e->ctx;\n\n\t/*\n\t * According to SMPTE 302M, an audio access unit is specified as those\n\t * AES3 words that are associated with a corresponding video frame.\n\t * Therefore, there is one audio access unit for every video access unit\n\t * in the corresponding video encoder ('sync'), using the same values\n\t * for PTS as used by the video encoder.\n\t *\n\t * Assuming that it is also possible to send audio without any\n\t * associated video, as in a radio-like service, a single audio access unit\n\t * is created with values for 'num_samples' and 'pts' taken empirically from\n\t * ffmpeg\n\t */\n\n\tvidtv_s302m_access_unit_destroy(e);\n\tvidtv_s302m_alloc_au(e);\n\n\tif (e->sync && e->sync->is_video_encoder) {\n\t\tvidtv_s302m_compute_sample_count_from_video(e);\n\t\tvidtv_s302m_compute_pts_from_video(e);\n\t} else {\n\t\te->access_units->num_samples = FF_S302M_DEFAULT_NUM_FRAMES;\n\t\te->access_units->pts = (ctx->au_count * FF_S302M_DEFAULT_PTS_INCREMENT) +\n\t\t\t\t       FF_S302M_DEFAULT_PTS_OFFSET;\n\t}\n\n\tvidtv_s302m_write_frames(e);\n\n\treturn e->encoder_buf;\n}",
        "static int check_results(int span)\n{\n\tunsigned long bw_imc[NUM_OF_RUNS], bw_resc[NUM_OF_RUNS];\n\tchar temp[1024], *token_array[8];\n\tchar output[] = RESULT_FILE_NAME;": "static int check_results(int span)\n{\n\tunsigned long bw_imc[NUM_OF_RUNS], bw_resc[NUM_OF_RUNS];\n\tchar temp[1024], *token_array[8];\n\tchar output[] = RESULT_FILE_NAME;\n\tint runs, ret;\n\tFILE *fp;\n\n\tksft_print_msg(\"Checking for pass/fail\\n\");\n\n\tfp = fopen(output, \"r\");\n\tif (!fp) {\n\t\tperror(output);\n\n\t\treturn errno;\n\t}\n\n\truns = 0;\n\twhile (fgets(temp, sizeof(temp), fp)) {\n\t\tchar *token = strtok(temp, \":\\t\");\n\t\tint i = 0;\n\n\t\twhile (token) {\n\t\t\ttoken_array[i++] = token;\n\t\t\ttoken = strtok(NULL, \":\\t\");\n\t\t}\n\n\t\tbw_resc[runs] = strtoul(token_array[5], NULL, 0);\n\t\tbw_imc[runs] = strtoul(token_array[3], NULL, 0);\n\t\truns++;\n\t}\n\n\tret = show_bw_info(bw_imc, bw_resc, span);\n\n\tfclose(fp);\n\n\treturn ret;\n}",
        "static inline int input_state_high(struct logical_input *input)\n{\n#if 0\n\t/* FIXME:\n\t * this is an invalid test. It tries to catch": "static inline int input_state_high(struct logical_input *input)\n{\n#if 0\n\t/* FIXME:\n\t * this is an invalid test. It tries to catch\n\t * transitions from single-key to multiple-key, but\n\t * doesn't take into account the contacts polarity.\n\t * The only solution to the problem is to parse keys\n\t * from the most complex to the simplest combinations,\n\t * and mark them as 'caught' once a combination\n\t * matches, then unmatch it for all other ones.\n\t */\n\n\t/* try to catch dangerous transitions cases :\n\t * someone adds a bit, so this signal was a false\n\t * positive resulting from a transition. We should\n\t * invalidate the signal immediately and not call the\n\t * release function.\n\t * eg: 0 -(press A)-> A -(press B)-> AB : don't match A's release.\n\t */\n\tif (((phys_prev & input->mask) == input->value) &&\n\t    ((phys_curr & input->mask) >  input->value)) {\n\t\tinput->state = INPUT_ST_LOW; /* invalidate */\n\t\treturn 1;\n\t}\n#endif\n\n\tif ((phys_curr & input->mask) == input->value) {\n\t\tif ((input->type == INPUT_TYPE_STD) &&\n\t\t    (input->high_timer == 0)) {\n\t\t\tinput->high_timer++;\n\t\t\tif (input->u.std.press_fct)\n\t\t\t\tinput->u.std.press_fct(input->u.std.press_data);\n\t\t} else if (input->type == INPUT_TYPE_KBD) {\n\t\t\t/* will turn on the light */\n\t\t\tkeypressed = 1;\n\n\t\t\tif (input->high_timer == 0) {\n\t\t\t\tchar *press_str = input->u.kbd.press_str;\n\n\t\t\t\tif (press_str[0]) {\n\t\t\t\t\tint s = sizeof(input->u.kbd.press_str);\n\n\t\t\t\t\tkeypad_send_key(press_str, s);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (input->u.kbd.repeat_str[0]) {\n\t\t\t\tchar *repeat_str = input->u.kbd.repeat_str;\n\n\t\t\t\tif (input->high_timer >= KEYPAD_REP_START) {\n\t\t\t\t\tint s = sizeof(input->u.kbd.repeat_str);\n\n\t\t\t\t\tinput->high_timer -= KEYPAD_REP_DELAY;\n\t\t\t\t\tkeypad_send_key(repeat_str, s);\n\t\t\t\t}\n\t\t\t\t/* we will need to come back here soon */\n\t\t\t\tinputs_stable = 0;\n\t\t\t}\n\n\t\t\tif (input->high_timer < 255)\n\t\t\t\tinput->high_timer++;\n\t\t}\n\t\treturn 1;\n\t}\n\n\t/* else signal falling down. Let's fall through. */\n\tinput->state = INPUT_ST_FALLING;\n\tinput->fall_timer = 0;\n\n\treturn 0;\n}",
        "static void eip197_trc_cache_setupvirt(struct safexcel_crypto_priv *priv)\n{\n\tint i;\n\n\t/*": "static void eip197_trc_cache_setupvirt(struct safexcel_crypto_priv *priv)\n{\n\tint i;\n\n\t/*\n\t * Map all interfaces/rings to register index 0\n\t * so they can share contexts. Without this, the EIP197 will\n\t * assume each interface/ring to be in its own memory domain\n\t * i.e. have its own subset of UNIQUE memory addresses.\n\t * Which would cause records with the SAME memory address to\n\t * use DIFFERENT cache buffers, causing both poor cache utilization\n\t * AND serious coherence/invalidation issues.\n\t */\n\tfor (i = 0; i < 4; i++)\n\t\twritel(0, priv->base + EIP197_FLUE_IFC_LUT(i));\n\n\t/*\n\t * Initialize other virtualization regs for cache\n\t * These may not be in their reset state ...\n\t */\n\tfor (i = 0; i < priv->config.rings; i++) {\n\t\twritel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i));\n\t\twritel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i));\n\t\twritel(EIP197_FLUE_CONFIG_MAGIC,\n\t\t       priv->base + EIP197_FLUE_CONFIG(i));\n\t}\n\twritel(0, priv->base + EIP197_FLUE_OFFSETS);\n\twritel(0, priv->base + EIP197_FLUE_ARC4_OFFSET);\n}",
        "static int dvbt_start(struct drxk_state *state)\n{\n\tu16 param1;\n\tint status;\n\t/* drxk_ofdm_sc_cmd_t scCmd; */": "static int dvbt_start(struct drxk_state *state)\n{\n\tu16 param1;\n\tint status;\n\t/* drxk_ofdm_sc_cmd_t scCmd; */\n\n\tdprintk(1, \"\\n\");\n\t/* start correct processes to get in lock */\n\t/* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */\n\tparam1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;\n\tstatus = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,\n\t\t\t\t OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,\n\t\t\t\t 0, 0, 0);\n\tif (status < 0)\n\t\tgoto error;\n\t/* start FEC OC */\n\tstatus = mpegts_start(state);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);\n\tif (status < 0)\n\t\tgoto error;\nerror:\n\tif (status < 0)\n\t\tpr_err(\"Error %d on %s\\n\", status, __func__);\n\treturn status;\n}",
        "static int ila_xlat_addr(struct sk_buff *skb, bool sir2ila)\n{\n\tstruct ila_map *ila;\n\tstruct ipv6hdr *ip6h = ipv6_hdr(skb);\n\tstruct net *net = dev_net(skb->dev);": "static int ila_xlat_addr(struct sk_buff *skb, bool sir2ila)\n{\n\tstruct ila_map *ila;\n\tstruct ipv6hdr *ip6h = ipv6_hdr(skb);\n\tstruct net *net = dev_net(skb->dev);\n\tstruct ila_net *ilan = net_generic(net, ila_net_id);\n\tstruct ila_addr *iaddr = ila_a2i(&ip6h->daddr);\n\n\t/* Assumes skb contains a valid IPv6 header that is pulled */\n\n\t/* No check here that ILA type in the mapping matches what is in the\n\t * address. We assume that whatever sender gaves us can be translated.\n\t * The checksum mode however is relevant.\n\t */\n\n\trcu_read_lock();\n\n\tila = ila_lookup_wildcards(iaddr, skb->dev->ifindex, ilan);\n\tif (ila)\n\t\tila_update_ipv6_locator(skb, &ila->xp.ip, sir2ila);\n\n\trcu_read_unlock();\n\n\treturn 0;\n}",
        "static int hp03_update_temp_pressure(struct hp03_priv *priv)\n{\n\tstruct device *dev = &priv->client->dev;\n\tu8 coefs[18];\n\tu16 cx_val[7];": "static int hp03_update_temp_pressure(struct hp03_priv *priv)\n{\n\tstruct device *dev = &priv->client->dev;\n\tu8 coefs[18];\n\tu16 cx_val[7];\n\tint ab_val, d1_val, d2_val, diff_val, dut, off, sens, x;\n\tint i, ret;\n\n\t/* Sample coefficients from EEPROM */\n\tret = regmap_bulk_read(priv->eeprom_regmap, HP03_EEPROM_CX_OFFSET,\n\t\t\t       coefs, sizeof(coefs));\n\tif (ret < 0) {\n\t\tdev_err(dev, \"Failed to read EEPROM (reg=%02x)\\n\",\n\t\t\tHP03_EEPROM_CX_OFFSET);\n\t\treturn ret;\n\t}\n\n\t/* Sample Temperature and Pressure */\n\tgpiod_set_value_cansleep(priv->xclr_gpio, 1);\n\n\tret = hp03_get_temp_pressure(priv, HP03_ADC_READ_PRESSURE);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"Failed to read pressure\\n\");\n\t\tgoto err_adc;\n\t}\n\td1_val = ret;\n\n\tret = hp03_get_temp_pressure(priv, HP03_ADC_READ_TEMP);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"Failed to read temperature\\n\");\n\t\tgoto err_adc;\n\t}\n\td2_val = ret;\n\n\tgpiod_set_value_cansleep(priv->xclr_gpio, 0);\n\n\t/* The Cx coefficients and Temp/Pressure values are MSB first. */\n\tfor (i = 0; i < 7; i++)\n\t\tcx_val[i] = (coefs[2 * i] << 8) | (coefs[(2 * i) + 1] << 0);\n\td1_val = ((d1_val >> 8) & 0xff) | ((d1_val & 0xff) << 8);\n\td2_val = ((d2_val >> 8) & 0xff) | ((d2_val & 0xff) << 8);\n\n\t/* Coefficient voodoo from the HP03 datasheet. */\n\tif (d2_val >= cx_val[4])\n\t\tab_val = coefs[14];\t/* A-value */\n\telse\n\t\tab_val = coefs[15];\t/* B-value */\n\n\tdiff_val = d2_val - cx_val[4];\n\tdut = (ab_val * (diff_val >> 7) * (diff_val >> 7)) >> coefs[16];\n\tdut = diff_val - dut;\n\n\toff = (cx_val[1] + (((cx_val[3] - 1024) * dut) >> 14)) * 4;\n\tsens = cx_val[0] + ((cx_val[2] * dut) >> 10);\n\tx = ((sens * (d1_val - 7168)) >> 14) - off;\n\n\tpriv->pressure = ((x * 100) >> 5) + (cx_val[6] * 10);\n\tpriv->temp = 250 + ((dut * cx_val[5]) >> 16) - (dut >> coefs[17]);\n\n\treturn 0;\n\nerr_adc:\n\tgpiod_set_value_cansleep(priv->xclr_gpio, 0);\n\treturn ret;\n}",
        "static int br_cfm_frame_rx(struct net_bridge_port *port, struct sk_buff *skb)\n{\n\tu32 mdlevel, interval, size, index, max;\n\tconst struct br_cfm_common_hdr *hdr;\n\tstruct br_cfm_peer_mep *peer_mep;": "static int br_cfm_frame_rx(struct net_bridge_port *port, struct sk_buff *skb)\n{\n\tu32 mdlevel, interval, size, index, max;\n\tconst struct br_cfm_common_hdr *hdr;\n\tstruct br_cfm_peer_mep *peer_mep;\n\tconst struct br_cfm_maid *maid;\n\tstruct br_cfm_common_hdr _hdr;\n\tstruct br_cfm_maid _maid;\n\tstruct br_cfm_mep *mep;\n\tstruct net_bridge *br;\n\t__be32 *snumber;\n\t__be32 _snumber;\n\t__be16 *mepid;\n\t__be16 _mepid;\n\n\tif (port->state == BR_STATE_DISABLED)\n\t\treturn 0;\n\n\thdr = skb_header_pointer(skb, 0, sizeof(_hdr), &_hdr);\n\tif (!hdr)\n\t\treturn 1;\n\n\tbr = port->br;\n\tmep = br_mep_find_ifindex(br, port->dev->ifindex);\n\tif (unlikely(!mep))\n\t\t/* No MEP on this port - must be forwarded */\n\t\treturn 0;\n\n\tmdlevel = hdr->mdlevel_version >> 5;\n\tif (mdlevel > mep->config.mdlevel)\n\t\t/* The level is above this MEP level - must be forwarded */\n\t\treturn 0;\n\n\tif ((hdr->mdlevel_version & 0x1F) != 0) {\n\t\t/* Invalid version */\n\t\tmep->status.version_unexp_seen = true;\n\t\treturn 1;\n\t}\n\n\tif (mdlevel < mep->config.mdlevel) {\n\t\t/* The level is below this MEP level */\n\t\tmep->status.rx_level_low_seen = true;\n\t\treturn 1;\n\t}\n\n\tif (hdr->opcode == BR_CFM_OPCODE_CCM) {\n\t\t/* CCM PDU received. */\n\t\t/* MA ID is after common header + sequence number + MEP ID */\n\t\tmaid = skb_header_pointer(skb,\n\t\t\t\t\t  CFM_CCM_PDU_MAID_OFFSET,\n\t\t\t\t\t  sizeof(_maid), &_maid);\n\t\tif (!maid)\n\t\t\treturn 1;\n\t\tif (memcmp(maid->data, mep->cc_config.exp_maid.data,\n\t\t\t   sizeof(maid->data)))\n\t\t\t/* MA ID not as expected */\n\t\t\treturn 1;\n\n\t\t/* MEP ID is after common header + sequence number */\n\t\tmepid = skb_header_pointer(skb,\n\t\t\t\t\t   CFM_CCM_PDU_MEPID_OFFSET,\n\t\t\t\t\t   sizeof(_mepid), &_mepid);\n\t\tif (!mepid)\n\t\t\treturn 1;\n\t\tpeer_mep = br_peer_mep_find(mep, (u32)ntohs(*mepid));\n\t\tif (!peer_mep)\n\t\t\treturn 1;\n\n\t\t/* Interval is in common header flags */\n\t\tinterval = hdr->flags & 0x07;\n\t\tif (mep->cc_config.exp_interval != pdu_to_interval(interval))\n\t\t\t/* Interval not as expected */\n\t\t\treturn 1;\n\n\t\t/* A valid CCM frame is received */\n\t\tif (peer_mep->cc_status.ccm_defect) {\n\t\t\tpeer_mep->cc_status.ccm_defect = false;\n\n\t\t\t/* Change in CCM defect status - notify */\n\t\t\tbr_cfm_notify(RTM_NEWLINK, port);\n\n\t\t\t/* Start CCM RX timer */\n\t\t\tccm_rx_timer_start(peer_mep);\n\t\t}\n\n\t\tpeer_mep->cc_status.seen = true;\n\t\tpeer_mep->ccm_rx_count_miss = 0;\n\n\t\t/* RDI is in common header flags */\n\t\tpeer_mep->cc_status.rdi = (hdr->flags & 0x80) ? true : false;\n\n\t\t/* Sequence number is after common header */\n\t\tsnumber = skb_header_pointer(skb,\n\t\t\t\t\t     CFM_CCM_PDU_SEQNR_OFFSET,\n\t\t\t\t\t     sizeof(_snumber), &_snumber);\n\t\tif (!snumber)\n\t\t\treturn 1;\n\t\tif (ntohl(*snumber) != (mep->ccm_rx_snumber + 1))\n\t\t\t/* Unexpected sequence number */\n\t\t\tpeer_mep->cc_status.seq_unexp_seen = true;\n\n\t\tmep->ccm_rx_snumber = ntohl(*snumber);\n\n\t\t/* TLV end is after common header + sequence number + MEP ID +\n\t\t * MA ID + ITU reserved\n\t\t */\n\t\tindex = CFM_CCM_PDU_TLV_OFFSET;\n\t\tmax = 0;\n\t\tdo { /* Handle all TLVs */\n\t\t\tsize = ccm_tlv_extract(skb, index, peer_mep);\n\t\t\tindex += size;\n\t\t\tmax += 1;\n\t\t} while (size != 0 && max < 4); /* Max four TLVs possible */\n\n\t\treturn 1;\n\t}\n\n\tmep->status.opcode_unexp_seen = true;\n\n\treturn 1;\n}",
        "static int redirty_blocks(struct inode *inode, pgoff_t page_idx, int len)\n{\n\tDEFINE_READAHEAD(ractl, NULL, NULL, inode->i_mapping, page_idx);\n\tstruct address_space *mapping = inode->i_mapping;\n\tstruct page *page;": "static int redirty_blocks(struct inode *inode, pgoff_t page_idx, int len)\n{\n\tDEFINE_READAHEAD(ractl, NULL, NULL, inode->i_mapping, page_idx);\n\tstruct address_space *mapping = inode->i_mapping;\n\tstruct page *page;\n\tpgoff_t redirty_idx = page_idx;\n\tint i, page_len = 0, ret = 0;\n\n\tpage_cache_ra_unbounded(&ractl, len, 0);\n\n\tfor (i = 0; i < len; i++, page_idx++) {\n\t\tpage = read_cache_page(mapping, page_idx, NULL, NULL);\n\t\tif (IS_ERR(page)) {\n\t\t\tret = PTR_ERR(page);\n\t\t\tbreak;\n\t\t}\n\t\tpage_len++;\n\t}\n\n\tfor (i = 0; i < page_len; i++, redirty_idx++) {\n\t\tpage = find_lock_page(mapping, redirty_idx);\n\t\tif (!page) {\n\t\t\tret = -ENOMEM;\n\t\t\tbreak;\n\t\t}\n\t\tset_page_dirty(page);\n\t\tf2fs_put_page(page, 1);\n\t\tf2fs_put_page(page, 0);\n\t}\n\n\treturn ret;\n}",
        "static int run_exercise(struct etab *e)\n{\n\tint nn = (1 << e->symsize) - 1;\n\tint kk = nn - e->nroots;\n\tstruct rs_control *rsc;": "static int run_exercise(struct etab *e)\n{\n\tint nn = (1 << e->symsize) - 1;\n\tint kk = nn - e->nroots;\n\tstruct rs_control *rsc;\n\tint retval = -ENOMEM;\n\tint max_pad = kk - 1;\n\tint prev_pad = -1;\n\tstruct wspace *ws;\n\tint i;\n\n\trsc = init_rs(e->symsize, e->genpoly, e->fcs, e->prim, e->nroots);\n\tif (!rsc)\n\t\treturn retval;\n\n\tws = alloc_ws(rsc->codec);\n\tif (!ws)\n\t\tgoto err;\n\n\tretval = 0;\n\tfor (i = 0; i < ARRAY_SIZE(pad_coef); i++) {\n\t\tint pad = (pad_coef[i].mult * max_pad) >> pad_coef[i].shift;\n\t\tint len = nn - pad;\n\n\t\tif (pad == prev_pad)\n\t\t\tcontinue;\n\n\t\tprev_pad = pad;\n\t\tif (v >= V_PROGRESS) {\n\t\t\tpr_info(\"Testing (%d,%d)_%d code...\\n\",\n\t\t\t\t\tlen, kk - pad, nn + 1);\n\t\t}\n\n\t\tretval |= exercise_rs(rsc, ws, len, e->ntrials);\n\t\tif (bc)\n\t\t\tretval |= exercise_rs_bc(rsc, ws, len, e->ntrials);\n\t}\n\n\tfree_ws(ws);\n\nerr:\n\tfree_rs(rsc);\n\treturn retval;\n}",
        "static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg)\n{\n\tint ret;\n\tstruct test_params *p = arg;\n\tstruct vcpu_args *vcpu_args;": "static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg)\n{\n\tint ret;\n\tstruct test_params *p = arg;\n\tstruct vcpu_args *vcpu_args;\n\tenum vm_mem_backing_src_type src_type = p->src_type;\n\tuint64_t large_page_size = get_backing_src_pagesz(src_type);\n\tuint64_t guest_page_size = vm_guest_mode_params[mode].page_size;\n\tuint64_t host_page_size = getpagesize();\n\tuint64_t test_mem_size = p->test_mem_size;\n\tuint64_t guest_num_pages;\n\tuint64_t alignment;\n\tvoid *host_test_mem;\n\tstruct kvm_vm *vm;\n\tint vcpu_id;\n\n\t/* Align up the test memory size */\n\talignment = max(large_page_size, guest_page_size);\n\ttest_mem_size = (test_mem_size + alignment - 1) & ~(alignment - 1);\n\n\t/* Create a VM with enough guest pages */\n\tguest_num_pages = test_mem_size / guest_page_size;\n\tvm = vm_create_with_vcpus(mode, nr_vcpus, DEFAULT_GUEST_PHY_PAGES,\n\t\t\t\t  guest_num_pages, 0, guest_code, NULL);\n\n\t/* Align down GPA of the testing memslot */\n\tif (!p->phys_offset)\n\t\tguest_test_phys_mem = (vm_get_max_gfn(vm) - guest_num_pages) *\n\t\t\t\t       guest_page_size;\n\telse\n\t\tguest_test_phys_mem = p->phys_offset;\n#ifdef __s390x__\n\talignment = max(0x100000UL, alignment);\n#endif\n\tguest_test_phys_mem = align_down(guest_test_phys_mem, alignment);\n\n\t/* Set up the shared data structure test_args */\n\ttest_args.vm = vm;\n\ttest_args.guest_test_virt_mem = guest_test_virt_mem;\n\ttest_args.host_page_size = host_page_size;\n\ttest_args.host_num_pages = test_mem_size / host_page_size;\n\ttest_args.large_page_size = large_page_size;\n\ttest_args.large_num_pages = test_mem_size / large_page_size;\n\ttest_args.host_pages_per_lpage = large_page_size / host_page_size;\n\ttest_args.src_type = src_type;\n\n\tfor (vcpu_id = 0; vcpu_id < KVM_MAX_VCPUS; vcpu_id++) {\n\t\tvcpu_args = &test_args.vcpu_args[vcpu_id];\n\t\tvcpu_args->vcpu_id = vcpu_id;\n\t\tvcpu_args->vcpu_write = !(vcpu_id % 2);\n\t}\n\n\t/* Add an extra memory slot with specified backing src type */\n\tvm_userspace_mem_region_add(vm, src_type, guest_test_phys_mem,\n\t\t\t\t    TEST_MEM_SLOT_INDEX, guest_num_pages, 0);\n\n\t/* Do mapping(GVA->GPA) for the testing memory slot */\n\tvirt_map(vm, guest_test_virt_mem, guest_test_phys_mem, guest_num_pages);\n\n\t/* Cache the HVA pointer of the region */\n\thost_test_mem = addr_gpa2hva(vm, (vm_paddr_t)guest_test_phys_mem);\n\n\t/* Export shared structure test_args to guest */\n\tucall_init(vm, NULL);\n\tsync_global_to_guest(vm, test_args);\n\n\tret = sem_init(&test_stage_updated, 0, 0);\n\tTEST_ASSERT(ret == 0, \"Error in sem_init\");\n\n\tret = sem_init(&test_stage_completed, 0, 0);\n\tTEST_ASSERT(ret == 0, \"Error in sem_init\");\n\n\tcurrent_stage = addr_gva2hva(vm, (vm_vaddr_t)(&guest_test_stage));\n\t*current_stage = NUM_TEST_STAGES;\n\n\tpr_info(\"Testing guest mode: %s\\n\", vm_guest_mode_string(mode));\n\tpr_info(\"Testing memory backing src type: %s\\n\",\n\t\tvm_mem_backing_src_alias(src_type)->name);\n\tpr_info(\"Testing memory backing src granularity: 0x%lx\\n\",\n\t\tlarge_page_size);\n\tpr_info(\"Testing memory size(aligned): 0x%lx\\n\", test_mem_size);\n\tpr_info(\"Guest physical test memory offset: 0x%lx\\n\",\n\t\tguest_test_phys_mem);\n\tpr_info(\"Host  virtual  test memory offset: 0x%lx\\n\",\n\t\t(uint64_t)host_test_mem);\n\tpr_info(\"Number of testing vCPUs: %d\\n\", nr_vcpus);\n\n\treturn vm;\n}",
        "static int reset_ring_pair(void __iomem *csr, u32 bank_number)\n{\n\tu32 status;\n\tint ret;\n": "static int reset_ring_pair(void __iomem *csr, u32 bank_number)\n{\n\tu32 status;\n\tint ret;\n\n\t/* Write rpresetctl register BIT(0) as 1\n\t * Since rpresetctl registers have no RW fields, no need to preserve\n\t * values for other bits. Just write directly.\n\t */\n\tADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),\n\t\t   ADF_WQM_CSR_RPRESETCTL_RESET);\n\n\t/* Read rpresetsts register and wait for rp reset to complete */\n\tret = read_poll_timeout(ADF_CSR_RD, status,\n\t\t\t\tstatus & ADF_WQM_CSR_RPRESETSTS_STATUS,\n\t\t\t\tADF_RPRESET_POLL_DELAY_US,\n\t\t\t\tADF_RPRESET_POLL_TIMEOUT_US, true,\n\t\t\t\tcsr, ADF_WQM_CSR_RPRESETSTS(bank_number));\n\tif (!ret) {\n\t\t/* When rp reset is done, clear rpresetsts */\n\t\tADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number),\n\t\t\t   ADF_WQM_CSR_RPRESETSTS_STATUS);\n\t}\n\n\treturn ret;\n}",
        "static int test_klp_shadow_vars_init(void)\n{\n\tstruct test_object objs[NUM_OBJS];\n\tchar nfields1[NUM_OBJS], *pnfields1[NUM_OBJS], **sv1[NUM_OBJS];\n\tchar *pndup[NUM_OBJS];": "static int test_klp_shadow_vars_init(void)\n{\n\tstruct test_object objs[NUM_OBJS];\n\tchar nfields1[NUM_OBJS], *pnfields1[NUM_OBJS], **sv1[NUM_OBJS];\n\tchar *pndup[NUM_OBJS];\n\tint nfields2[NUM_OBJS], *pnfields2[NUM_OBJS], **sv2[NUM_OBJS];\n\tvoid **sv;\n\tint ret;\n\tint i;\n\n\tptr_id(NULL);\n\n\t/*\n\t * With an empty shadow variable hash table, expect not to find\n\t * any matches.\n\t */\n\tsv = shadow_get(&objs[0], SV_ID1);\n\tif (!sv)\n\t\tpr_info(\"  got expected NULL result\\n\");\n\n\t/* pass 1: init & alloc a char+int pair of svars for each objs */\n\tfor (i = 0; i < NUM_OBJS; i++) {\n\t\tpnfields1[i] = &nfields1[i];\n\t\tptr_id(pnfields1[i]);\n\n\t\tif (i % 2) {\n\t\t\tsv1[i] = shadow_alloc(&objs[i], SV_ID1,\n\t\t\t\t\tsizeof(pnfields1[i]), GFP_KERNEL,\n\t\t\t\t\tshadow_ctor, &pnfields1[i]);\n\t\t} else {\n\t\t\tsv1[i] = shadow_get_or_alloc(&objs[i], SV_ID1,\n\t\t\t\t\tsizeof(pnfields1[i]), GFP_KERNEL,\n\t\t\t\t\tshadow_ctor, &pnfields1[i]);\n\t\t}\n\t\tif (!sv1[i]) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out;\n\t\t}\n\n\t\tpnfields2[i] = &nfields2[i];\n\t\tptr_id(pnfields2[i]);\n\t\tsv2[i] = shadow_alloc(&objs[i], SV_ID2, sizeof(pnfields2[i]),\n\t\t\t\t\tGFP_KERNEL, shadow_ctor, &pnfields2[i]);\n\t\tif (!sv2[i]) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/* pass 2: verify we find allocated svars and where they point to */\n\tfor (i = 0; i < NUM_OBJS; i++) {\n\t\t/* check the \"char\" svar for all objects */\n\t\tsv = shadow_get(&objs[i], SV_ID1);\n\t\tif (!sv) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\t\tif ((char **)sv == sv1[i] && *sv1[i] == pnfields1[i])\n\t\t\tpr_info(\"  got expected PTR%d -> PTR%d result\\n\",\n\t\t\t\tptr_id(sv1[i]), ptr_id(*sv1[i]));\n\n\t\t/* check the \"int\" svar for all objects */\n\t\tsv = shadow_get(&objs[i], SV_ID2);\n\t\tif (!sv) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\t\tif ((int **)sv == sv2[i] && *sv2[i] == pnfields2[i])\n\t\t\tpr_info(\"  got expected PTR%d -> PTR%d result\\n\",\n\t\t\t\tptr_id(sv2[i]), ptr_id(*sv2[i]));\n\t}\n\n\t/* pass 3: verify that 'get_or_alloc' returns already allocated svars */\n\tfor (i = 0; i < NUM_OBJS; i++) {\n\t\tpndup[i] = &nfields1[i];\n\t\tptr_id(pndup[i]);\n\n\t\tsv = shadow_get_or_alloc(&objs[i], SV_ID1, sizeof(pndup[i]),\n\t\t\t\t\tGFP_KERNEL, shadow_ctor, &pndup[i]);\n\t\tif (!sv) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\t\tif ((char **)sv == sv1[i] && *sv1[i] == pnfields1[i])\n\t\t\tpr_info(\"  got expected PTR%d -> PTR%d result\\n\",\n\t\t\t\t\tptr_id(sv1[i]), ptr_id(*sv1[i]));\n\t}\n\n\t/* pass 4: free <objs[*], SV_ID1> pairs of svars, verify removal */\n\tfor (i = 0; i < NUM_OBJS; i++) {\n\t\tshadow_free(&objs[i], SV_ID1, shadow_dtor); /* 'char' pairs */\n\t\tsv = shadow_get(&objs[i], SV_ID1);\n\t\tif (!sv)\n\t\t\tpr_info(\"  got expected NULL result\\n\");\n\t}\n\n\t/* pass 5: check we still find <objs[*], SV_ID2> svar pairs */\n\tfor (i = 0; i < NUM_OBJS; i++) {\n\t\tsv = shadow_get(&objs[i], SV_ID2);\t/* 'int' pairs */\n\t\tif (!sv) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\t\tif ((int **)sv == sv2[i] && *sv2[i] == pnfields2[i])\n\t\t\tpr_info(\"  got expected PTR%d -> PTR%d result\\n\",\n\t\t\t\t\tptr_id(sv2[i]), ptr_id(*sv2[i]));\n\t}\n\n\t/* pass 6: free all the <objs[*], SV_ID2> svar pairs too. */\n\tshadow_free_all(SV_ID2, NULL);\t\t/* 'int' pairs */\n\tfor (i = 0; i < NUM_OBJS; i++) {\n\t\tsv = shadow_get(&objs[i], SV_ID2);\n\t\tif (!sv)\n\t\t\tpr_info(\"  got expected NULL result\\n\");\n\t}\n\n\tfree_ptr_list();\n\n\treturn 0;\nout:\n\tshadow_free_all(SV_ID1, NULL);\t\t/* 'char' pairs */\n\tshadow_free_all(SV_ID2, NULL);\t\t/* 'int' pairs */\n\tfree_ptr_list();\n\n\treturn ret;\n}",
        "static int madera_fllhj_disable(struct madera_fll *fll)\n{\n\tstruct madera *madera = fll->madera;\n\tbool change;\n": "static int madera_fllhj_disable(struct madera_fll *fll)\n{\n\tstruct madera *madera = fll->madera;\n\tbool change;\n\n\tmadera_fll_dbg(fll, \"Disabling FLL\\n\");\n\n\t/* Disable lockdet, but don't set ctrl_upd update but.  This allows the\n\t * lock status bit to clear as normal, but should the FLL be enabled\n\t * again due to a control clock being required, the lock won't re-assert\n\t * as the FLL config registers are automatically applied when the FLL\n\t * enables.\n\t */\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_11_OFFS,\n\t\t\t   MADERA_FLL1_LOCKDET_MASK, 0);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_1_OFFS,\n\t\t\t   MADERA_FLL1_HOLD_MASK, MADERA_FLL1_HOLD_MASK);\n\tregmap_update_bits_check(madera->regmap,\n\t\t\t\t fll->base + MADERA_FLL_CONTROL_1_OFFS,\n\t\t\t\t MADERA_FLL1_ENA_MASK, 0, &change);\n\n\tmadera_wait_for_fll(fll, false);\n\n\t/* ctrl_up gates the writes to all the fll's registers, setting it to 0\n\t * here ensures that after a runtime suspend/resume cycle when one\n\t * enables the fll then ctrl_up is the last bit that is configured\n\t * by the fll enable code rather than the cache sync operation which\n\t * would have updated it much earlier before writing out all fll\n\t * registers\n\t */\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_2_OFFS,\n\t\t\t   MADERA_FLL1_CTRL_UPD_MASK, 0);\n\n\tif (change) {\n\t\tmadera_set_fllhj_clks(fll, fll->base, false);\n\t\tpm_runtime_put_autosuspend(madera->dev);\n\t}\n\n\treturn 0;\n}",
        "static int lock_comm(struct md_cluster_info *cinfo, bool mddev_locked)\n{\n\tint rv, set_bit = 0;\n\tstruct mddev *mddev = cinfo->mddev;\n": "static int lock_comm(struct md_cluster_info *cinfo, bool mddev_locked)\n{\n\tint rv, set_bit = 0;\n\tstruct mddev *mddev = cinfo->mddev;\n\n\t/*\n\t * If resync thread run after raid1d thread, then process_metadata_update\n\t * could not continue if raid1d held reconfig_mutex (and raid1d is blocked\n\t * since another node already got EX on Token and waitting the EX of Ack),\n\t * so let resync wake up thread in case flag is set.\n\t */\n\tif (mddev_locked && !test_bit(MD_CLUSTER_HOLDING_MUTEX_FOR_RECVD,\n\t\t\t\t      &cinfo->state)) {\n\t\trv = test_and_set_bit_lock(MD_CLUSTER_HOLDING_MUTEX_FOR_RECVD,\n\t\t\t\t\t      &cinfo->state);\n\t\tWARN_ON_ONCE(rv);\n\t\tmd_wakeup_thread(mddev->thread);\n\t\tset_bit = 1;\n\t}\n\n\twait_event(cinfo->wait,\n\t\t   !test_and_set_bit(MD_CLUSTER_SEND_LOCK, &cinfo->state));\n\trv = lock_token(cinfo);\n\tif (set_bit)\n\t\tclear_bit_unlock(MD_CLUSTER_HOLDING_MUTEX_FOR_RECVD, &cinfo->state);\n\treturn rv;\n}",
        "static bool bfqq_request_over_limit(struct bfq_queue *bfqq, int limit)\n{\n\tstruct bfq_data *bfqd = bfqq->bfqd;\n\tstruct bfq_entity *entity = &bfqq->entity;\n\tstruct bfq_entity *inline_entities[BFQ_LIMIT_INLINE_DEPTH];": "static bool bfqq_request_over_limit(struct bfq_queue *bfqq, int limit)\n{\n\tstruct bfq_data *bfqd = bfqq->bfqd;\n\tstruct bfq_entity *entity = &bfqq->entity;\n\tstruct bfq_entity *inline_entities[BFQ_LIMIT_INLINE_DEPTH];\n\tstruct bfq_entity **entities = inline_entities;\n\tint depth, level, alloc_depth = BFQ_LIMIT_INLINE_DEPTH;\n\tint class_idx = bfqq->ioprio_class - 1;\n\tstruct bfq_sched_data *sched_data;\n\tunsigned long wsum;\n\tbool ret = false;\n\n\tif (!entity->on_st_or_in_serv)\n\t\treturn false;\n\nretry:\n\tspin_lock_irq(&bfqd->lock);\n\t/* +1 for bfqq entity, root cgroup not included */\n\tdepth = bfqg_to_blkg(bfqq_group(bfqq))->blkcg->css.cgroup->level + 1;\n\tif (depth > alloc_depth) {\n\t\tspin_unlock_irq(&bfqd->lock);\n\t\tif (entities != inline_entities)\n\t\t\tkfree(entities);\n\t\tentities = kmalloc_array(depth, sizeof(*entities), GFP_NOIO);\n\t\tif (!entities)\n\t\t\treturn false;\n\t\talloc_depth = depth;\n\t\tgoto retry;\n\t}\n\n\tsched_data = entity->sched_data;\n\t/* Gather our ancestors as we need to traverse them in reverse order */\n\tlevel = 0;\n\tfor_each_entity(entity) {\n\t\t/*\n\t\t * If at some level entity is not even active, allow request\n\t\t * queueing so that BFQ knows there's work to do and activate\n\t\t * entities.\n\t\t */\n\t\tif (!entity->on_st_or_in_serv)\n\t\t\tgoto out;\n\t\t/* Uh, more parents than cgroup subsystem thinks? */\n\t\tif (WARN_ON_ONCE(level >= depth))\n\t\t\tbreak;\n\t\tentities[level++] = entity;\n\t}\n\tWARN_ON_ONCE(level != depth);\n\tfor (level--; level >= 0; level--) {\n\t\tentity = entities[level];\n\t\tif (level > 0) {\n\t\t\twsum = bfq_entity_service_tree(entity)->wsum;\n\t\t} else {\n\t\t\tint i;\n\t\t\t/*\n\t\t\t * For bfqq itself we take into account service trees\n\t\t\t * of all higher priority classes and multiply their\n\t\t\t * weights so that low prio queue from higher class\n\t\t\t * gets more requests than high prio queue from lower\n\t\t\t * class.\n\t\t\t */\n\t\t\twsum = 0;\n\t\t\tfor (i = 0; i <= class_idx; i++) {\n\t\t\t\twsum = wsum * IOPRIO_BE_NR +\n\t\t\t\t\tsched_data->service_tree[i].wsum;\n\t\t\t}\n\t\t}\n\t\tlimit = DIV_ROUND_CLOSEST(limit * entity->weight, wsum);\n\t\tif (entity->allocated >= limit) {\n\t\t\tbfq_log_bfqq(bfqq->bfqd, bfqq,\n\t\t\t\t\"too many requests: allocated %d limit %d level %d\",\n\t\t\t\tentity->allocated, limit, level);\n\t\t\tret = true;\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\tspin_unlock_irq(&bfqd->lock);\n\tif (entities != inline_entities)\n\t\tkfree(entities);\n\treturn ret;\n}",
        "static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)\n{\n\tstruct drxuio_cfg uio_cfg;\n\tstruct drxuio_data uio_data;\n\tint result;": "static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)\n{\n\tstruct drxuio_cfg uio_cfg;\n\tstruct drxuio_data uio_data;\n\tint result;\n\n\tuio_cfg.uio = DRX_UIO1;\n\tuio_cfg.mode = DRX_UIO_MODE_READWRITE;\n\t/* Configure user-I/O #3: enable read/write */\n\tresult = ctrl_set_uio_cfg(demod, &uio_cfg);\n\tif (result) {\n\t\tpr_err(\"Failed to setup LNA GPIO!\\n\");\n\t\treturn result;\n\t}\n\n\tuio_data.uio = DRX_UIO1;\n\tuio_data.value = state;\n\tresult = ctrl_uio_write(demod, &uio_data);\n\tif (result != 0) {\n\t\tpr_err(\"Failed to %sable LNA!\\n\",\n\t\t       state ? \"en\" : \"dis\");\n\t\treturn result;\n\t}\n\treturn 0;\n}",
        "static int __sys_bpf(int cmd, bpfptr_t uattr, unsigned int size)\n{\n\tunion bpf_attr attr;\n\tbool capable;\n\tint err;": "static int __sys_bpf(int cmd, bpfptr_t uattr, unsigned int size)\n{\n\tunion bpf_attr attr;\n\tbool capable;\n\tint err;\n\n\tcapable = bpf_capable() || !sysctl_unprivileged_bpf_disabled;\n\n\t/* Intent here is for unprivileged_bpf_disabled to block key object\n\t * creation commands for unprivileged users; other actions depend\n\t * of fd availability and access to bpffs, so are dependent on\n\t * object creation success.  Capabilities are later verified for\n\t * operations such as load and map create, so even with unprivileged\n\t * BPF disabled, capability checks are still carried out for these\n\t * and other operations.\n\t */\n\tif (!capable &&\n\t    (cmd == BPF_MAP_CREATE || cmd == BPF_PROG_LOAD))\n\t\treturn -EPERM;\n\n\terr = bpf_check_uarg_tail_zero(uattr, sizeof(attr), size);\n\tif (err)\n\t\treturn err;\n\tsize = min_t(u32, size, sizeof(attr));\n\n\t/* copy attributes from user space, may be less than sizeof(bpf_attr) */\n\tmemset(&attr, 0, sizeof(attr));\n\tif (copy_from_bpfptr(&attr, uattr, size) != 0)\n\t\treturn -EFAULT;\n\n\terr = security_bpf(cmd, &attr, size);\n\tif (err < 0)\n\t\treturn err;\n\n\tswitch (cmd) {\n\tcase BPF_MAP_CREATE:\n\t\terr = map_create(&attr);\n\t\tbreak;\n\tcase BPF_MAP_LOOKUP_ELEM:\n\t\terr = map_lookup_elem(&attr);\n\t\tbreak;\n\tcase BPF_MAP_UPDATE_ELEM:\n\t\terr = map_update_elem(&attr, uattr);\n\t\tbreak;\n\tcase BPF_MAP_DELETE_ELEM:\n\t\terr = map_delete_elem(&attr);\n\t\tbreak;\n\tcase BPF_MAP_GET_NEXT_KEY:\n\t\terr = map_get_next_key(&attr);\n\t\tbreak;\n\tcase BPF_MAP_FREEZE:\n\t\terr = map_freeze(&attr);\n\t\tbreak;\n\tcase BPF_PROG_LOAD:\n\t\terr = bpf_prog_load(&attr, uattr);\n\t\tbreak;\n\tcase BPF_OBJ_PIN:\n\t\terr = bpf_obj_pin(&attr);\n\t\tbreak;\n\tcase BPF_OBJ_GET:\n\t\terr = bpf_obj_get(&attr);\n\t\tbreak;\n\tcase BPF_PROG_ATTACH:\n\t\terr = bpf_prog_attach(&attr);\n\t\tbreak;\n\tcase BPF_PROG_DETACH:\n\t\terr = bpf_prog_detach(&attr);\n\t\tbreak;\n\tcase BPF_PROG_QUERY:\n\t\terr = bpf_prog_query(&attr, uattr.user);\n\t\tbreak;\n\tcase BPF_PROG_TEST_RUN:\n\t\terr = bpf_prog_test_run(&attr, uattr.user);\n\t\tbreak;\n\tcase BPF_PROG_GET_NEXT_ID:\n\t\terr = bpf_obj_get_next_id(&attr, uattr.user,\n\t\t\t\t\t  &prog_idr, &prog_idr_lock);\n\t\tbreak;\n\tcase BPF_MAP_GET_NEXT_ID:\n\t\terr = bpf_obj_get_next_id(&attr, uattr.user,\n\t\t\t\t\t  &map_idr, &map_idr_lock);\n\t\tbreak;\n\tcase BPF_BTF_GET_NEXT_ID:\n\t\terr = bpf_obj_get_next_id(&attr, uattr.user,\n\t\t\t\t\t  &btf_idr, &btf_idr_lock);\n\t\tbreak;\n\tcase BPF_PROG_GET_FD_BY_ID:\n\t\terr = bpf_prog_get_fd_by_id(&attr);\n\t\tbreak;\n\tcase BPF_MAP_GET_FD_BY_ID:\n\t\terr = bpf_map_get_fd_by_id(&attr);\n\t\tbreak;\n\tcase BPF_OBJ_GET_INFO_BY_FD:\n\t\terr = bpf_obj_get_info_by_fd(&attr, uattr.user);\n\t\tbreak;\n\tcase BPF_RAW_TRACEPOINT_OPEN:\n\t\terr = bpf_raw_tracepoint_open(&attr);\n\t\tbreak;\n\tcase BPF_BTF_LOAD:\n\t\terr = bpf_btf_load(&attr, uattr);\n\t\tbreak;\n\tcase BPF_BTF_GET_FD_BY_ID:\n\t\terr = bpf_btf_get_fd_by_id(&attr);\n\t\tbreak;\n\tcase BPF_TASK_FD_QUERY:\n\t\terr = bpf_task_fd_query(&attr, uattr.user);\n\t\tbreak;\n\tcase BPF_MAP_LOOKUP_AND_DELETE_ELEM:\n\t\terr = map_lookup_and_delete_elem(&attr);\n\t\tbreak;\n\tcase BPF_MAP_LOOKUP_BATCH:\n\t\terr = bpf_map_do_batch(&attr, uattr.user, BPF_MAP_LOOKUP_BATCH);\n\t\tbreak;\n\tcase BPF_MAP_LOOKUP_AND_DELETE_BATCH:\n\t\terr = bpf_map_do_batch(&attr, uattr.user,\n\t\t\t\t       BPF_MAP_LOOKUP_AND_DELETE_BATCH);\n\t\tbreak;\n\tcase BPF_MAP_UPDATE_BATCH:\n\t\terr = bpf_map_do_batch(&attr, uattr.user, BPF_MAP_UPDATE_BATCH);\n\t\tbreak;\n\tcase BPF_MAP_DELETE_BATCH:\n\t\terr = bpf_map_do_batch(&attr, uattr.user, BPF_MAP_DELETE_BATCH);\n\t\tbreak;\n\tcase BPF_LINK_CREATE:\n\t\terr = link_create(&attr, uattr);\n\t\tbreak;\n\tcase BPF_LINK_UPDATE:\n\t\terr = link_update(&attr);\n\t\tbreak;\n\tcase BPF_LINK_GET_FD_BY_ID:\n\t\terr = bpf_link_get_fd_by_id(&attr);\n\t\tbreak;\n\tcase BPF_LINK_GET_NEXT_ID:\n\t\terr = bpf_obj_get_next_id(&attr, uattr.user,\n\t\t\t\t\t  &link_idr, &link_idr_lock);\n\t\tbreak;\n\tcase BPF_ENABLE_STATS:\n\t\terr = bpf_enable_stats(&attr);\n\t\tbreak;\n\tcase BPF_ITER_CREATE:\n\t\terr = bpf_iter_create(&attr);\n\t\tbreak;\n\tcase BPF_LINK_DETACH:\n\t\terr = link_detach(&attr);\n\t\tbreak;\n\tcase BPF_PROG_BIND_MAP:\n\t\terr = bpf_prog_bind_map(&attr);\n\t\tbreak;\n\tdefault:\n\t\terr = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn err;\n}",
        "static void test_shared(int parent_cgroup_fd, int child_cgroup_fd)\n{\n\tstruct cg_storage_multi_shared *obj;\n\tstruct cgroup_value expected_cgroup_value;\n\t__u64 key;": "static void test_shared(int parent_cgroup_fd, int child_cgroup_fd)\n{\n\tstruct cg_storage_multi_shared *obj;\n\tstruct cgroup_value expected_cgroup_value;\n\t__u64 key;\n\tstruct bpf_link *parent_egress1_link = NULL, *parent_egress2_link = NULL;\n\tstruct bpf_link *child_egress1_link = NULL, *child_egress2_link = NULL;\n\tstruct bpf_link *parent_ingress_link = NULL, *child_ingress_link = NULL;\n\tbool err;\n\n\tobj = cg_storage_multi_shared__open_and_load();\n\tif (CHECK(!obj, \"skel-load\", \"errno %d\", errno))\n\t\treturn;\n\n\t/* Attach to parent cgroup, trigger packet from child.\n\t * Assert that there is three runs, two with parent cgroup egress and\n\t * one with parent cgroup ingress.\n\t * Also assert that child cgroup's storage does not exist\n\t */\n\tparent_egress1_link = bpf_program__attach_cgroup(obj->progs.egress1,\n\t\t\t\t\t\t\t parent_cgroup_fd);\n\tif (!ASSERT_OK_PTR(parent_egress1_link, \"parent-egress1-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tparent_egress2_link = bpf_program__attach_cgroup(obj->progs.egress2,\n\t\t\t\t\t\t\t parent_cgroup_fd);\n\tif (!ASSERT_OK_PTR(parent_egress2_link, \"parent-egress2-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tparent_ingress_link = bpf_program__attach_cgroup(obj->progs.ingress,\n\t\t\t\t\t\t\t parent_cgroup_fd);\n\tif (!ASSERT_OK_PTR(parent_ingress_link, \"parent-ingress-cg-attach\"))\n\t\tgoto close_bpf_object;\n\terr = connect_send(CHILD_CGROUP);\n\tif (CHECK(err, \"first-connect-send\", \"errno %d\", errno))\n\t\tgoto close_bpf_object;\n\tif (CHECK(obj->bss->invocations != 3,\n\t\t  \"first-invoke\", \"invocations=%d\", obj->bss->invocations))\n\t\tgoto close_bpf_object;\n\tkey = get_cgroup_id(PARENT_CGROUP);\n\texpected_cgroup_value = (struct cgroup_value) {\n\t\t.egress_pkts = 2,\n\t\t.ingress_pkts = 1,\n\t};\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey = get_cgroup_id(CHILD_CGROUP);\n\tif (assert_storage_noexist(obj->maps.cgroup_storage, &key))\n\t\tgoto close_bpf_object;\n\n\t/* Attach to parent and child cgroup, trigger packet from child.\n\t * Assert that there is six additional runs, parent cgroup egresses and\n\t * ingress, child cgroup egresses and ingress.\n\t */\n\tchild_egress1_link = bpf_program__attach_cgroup(obj->progs.egress1,\n\t\t\t\t\t\t\tchild_cgroup_fd);\n\tif (!ASSERT_OK_PTR(child_egress1_link, \"child-egress1-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tchild_egress2_link = bpf_program__attach_cgroup(obj->progs.egress2,\n\t\t\t\t\t\t\tchild_cgroup_fd);\n\tif (!ASSERT_OK_PTR(child_egress2_link, \"child-egress2-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tchild_ingress_link = bpf_program__attach_cgroup(obj->progs.ingress,\n\t\t\t\t\t\t\tchild_cgroup_fd);\n\tif (!ASSERT_OK_PTR(child_ingress_link, \"child-ingress-cg-attach\"))\n\t\tgoto close_bpf_object;\n\terr = connect_send(CHILD_CGROUP);\n\tif (CHECK(err, \"second-connect-send\", \"errno %d\", errno))\n\t\tgoto close_bpf_object;\n\tif (CHECK(obj->bss->invocations != 9,\n\t\t  \"second-invoke\", \"invocations=%d\", obj->bss->invocations))\n\t\tgoto close_bpf_object;\n\tkey = get_cgroup_id(PARENT_CGROUP);\n\texpected_cgroup_value = (struct cgroup_value) {\n\t\t.egress_pkts = 4,\n\t\t.ingress_pkts = 2,\n\t};\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey = get_cgroup_id(CHILD_CGROUP);\n\texpected_cgroup_value = (struct cgroup_value) {\n\t\t.egress_pkts = 2,\n\t\t.ingress_pkts = 1,\n\t};\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(parent_egress1_link);\n\tbpf_link__destroy(parent_egress2_link);\n\tbpf_link__destroy(parent_ingress_link);\n\tbpf_link__destroy(child_egress1_link);\n\tbpf_link__destroy(child_egress2_link);\n\tbpf_link__destroy(child_ingress_link);\n\n\tcg_storage_multi_shared__destroy(obj);\n}",
        "static int do_check(struct bpf_verifier_env *env)\n{\n\tbool pop_log = !(env->log.level & BPF_LOG_LEVEL2);\n\tstruct bpf_verifier_state *state = env->cur_state;\n\tstruct bpf_insn *insns = env->prog->insnsi;": "static int do_check(struct bpf_verifier_env *env)\n{\n\tbool pop_log = !(env->log.level & BPF_LOG_LEVEL2);\n\tstruct bpf_verifier_state *state = env->cur_state;\n\tstruct bpf_insn *insns = env->prog->insnsi;\n\tstruct bpf_reg_state *regs;\n\tint insn_cnt = env->prog->len;\n\tbool do_print_state = false;\n\tint prev_insn_idx = -1;\n\n\tfor (;;) {\n\t\tstruct bpf_insn *insn;\n\t\tu8 class;\n\t\tint err;\n\n\t\tenv->prev_insn_idx = prev_insn_idx;\n\t\tif (env->insn_idx >= insn_cnt) {\n\t\t\tverbose(env, \"invalid insn idx %d insn_cnt %d\\n\",\n\t\t\t\tenv->insn_idx, insn_cnt);\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tinsn = &insns[env->insn_idx];\n\t\tclass = BPF_CLASS(insn->code);\n\n\t\tif (++env->insn_processed > BPF_COMPLEXITY_LIMIT_INSNS) {\n\t\t\tverbose(env,\n\t\t\t\t\"BPF program is too large. Processed %d insn\\n\",\n\t\t\t\tenv->insn_processed);\n\t\t\treturn -E2BIG;\n\t\t}\n\n\t\terr = is_state_visited(env, env->insn_idx);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\tif (err == 1) {\n\t\t\t/* found equivalent state, can prune the search */\n\t\t\tif (env->log.level & BPF_LOG_LEVEL) {\n\t\t\t\tif (do_print_state)\n\t\t\t\t\tverbose(env, \"\\nfrom %d to %d%s: safe\\n\",\n\t\t\t\t\t\tenv->prev_insn_idx, env->insn_idx,\n\t\t\t\t\t\tenv->cur_state->speculative ?\n\t\t\t\t\t\t\" (speculative execution)\" : \"\");\n\t\t\t\telse\n\t\t\t\t\tverbose(env, \"%d: safe\\n\", env->insn_idx);\n\t\t\t}\n\t\t\tgoto process_bpf_exit;\n\t\t}\n\n\t\tif (signal_pending(current))\n\t\t\treturn -EAGAIN;\n\n\t\tif (need_resched())\n\t\t\tcond_resched();\n\n\t\tif (env->log.level & BPF_LOG_LEVEL2 && do_print_state) {\n\t\t\tverbose(env, \"\\nfrom %d to %d%s:\",\n\t\t\t\tenv->prev_insn_idx, env->insn_idx,\n\t\t\t\tenv->cur_state->speculative ?\n\t\t\t\t\" (speculative execution)\" : \"\");\n\t\t\tprint_verifier_state(env, state->frame[state->curframe], true);\n\t\t\tdo_print_state = false;\n\t\t}\n\n\t\tif (env->log.level & BPF_LOG_LEVEL) {\n\t\t\tconst struct bpf_insn_cbs cbs = {\n\t\t\t\t.cb_call\t= disasm_kfunc_name,\n\t\t\t\t.cb_print\t= verbose,\n\t\t\t\t.private_data\t= env,\n\t\t\t};\n\n\t\t\tif (verifier_state_scratched(env))\n\t\t\t\tprint_insn_state(env, state->frame[state->curframe]);\n\n\t\t\tverbose_linfo(env, env->insn_idx, \"; \");\n\t\t\tenv->prev_log_len = env->log.len_used;\n\t\t\tverbose(env, \"%d: \", env->insn_idx);\n\t\t\tprint_bpf_insn(&cbs, insn, env->allow_ptr_leaks);\n\t\t\tenv->prev_insn_print_len = env->log.len_used - env->prev_log_len;\n\t\t\tenv->prev_log_len = env->log.len_used;\n\t\t}\n\n\t\tif (bpf_prog_is_dev_bound(env->prog->aux)) {\n\t\t\terr = bpf_prog_offload_verify_insn(env, env->insn_idx,\n\t\t\t\t\t\t\t   env->prev_insn_idx);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\n\t\tregs = cur_regs(env);\n\t\tsanitize_mark_insn_seen(env);\n\t\tprev_insn_idx = env->insn_idx;\n\n\t\tif (class == BPF_ALU || class == BPF_ALU64) {\n\t\t\terr = check_alu_op(env, insn);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t} else if (class == BPF_LDX) {\n\t\t\tenum bpf_reg_type *prev_src_type, src_reg_type;\n\n\t\t\t/* check for reserved fields is already done */\n\n\t\t\t/* check src operand */\n\t\t\terr = check_reg_arg(env, insn->src_reg, SRC_OP);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\terr = check_reg_arg(env, insn->dst_reg, DST_OP_NO_MARK);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tsrc_reg_type = regs[insn->src_reg].type;\n\n\t\t\t/* check that memory (src_reg + off) is readable,\n\t\t\t * the state of dst_reg will be updated by this func\n\t\t\t */\n\t\t\terr = check_mem_access(env, env->insn_idx, insn->src_reg,\n\t\t\t\t\t       insn->off, BPF_SIZE(insn->code),\n\t\t\t\t\t       BPF_READ, insn->dst_reg, false);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tprev_src_type = &env->insn_aux_data[env->insn_idx].ptr_type;\n\n\t\t\tif (*prev_src_type == NOT_INIT) {\n\t\t\t\t/* saw a valid insn\n\t\t\t\t * dst_reg = *(u32 *)(src_reg + off)\n\t\t\t\t * save type to validate intersecting paths\n\t\t\t\t */\n\t\t\t\t*prev_src_type = src_reg_type;\n\n\t\t\t} else if (reg_type_mismatch(src_reg_type, *prev_src_type)) {\n\t\t\t\t/* ABuser program is trying to use the same insn\n\t\t\t\t * dst_reg = *(u32*) (src_reg + off)\n\t\t\t\t * with different pointer types:\n\t\t\t\t * src_reg == ctx in one branch and\n\t\t\t\t * src_reg == stack|map in some other branch.\n\t\t\t\t * Reject it.\n\t\t\t\t */\n\t\t\t\tverbose(env, \"same insn cannot be used with different pointers\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t} else if (class == BPF_STX) {\n\t\t\tenum bpf_reg_type *prev_dst_type, dst_reg_type;\n\n\t\t\tif (BPF_MODE(insn->code) == BPF_ATOMIC) {\n\t\t\t\terr = check_atomic(env, env->insn_idx, insn);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\n\t\t\t\tenv->insn_idx++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (BPF_MODE(insn->code) != BPF_MEM || insn->imm != 0) {\n\t\t\t\tverbose(env, \"BPF_STX uses reserved fields\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\t/* check src1 operand */\n\t\t\terr = check_reg_arg(env, insn->src_reg, SRC_OP);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\t/* check src2 operand */\n\t\t\terr = check_reg_arg(env, insn->dst_reg, SRC_OP);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tdst_reg_type = regs[insn->dst_reg].type;\n\n\t\t\t/* check that memory (dst_reg + off) is writeable */\n\t\t\terr = check_mem_access(env, env->insn_idx, insn->dst_reg,\n\t\t\t\t\t       insn->off, BPF_SIZE(insn->code),\n\t\t\t\t\t       BPF_WRITE, insn->src_reg, false);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tprev_dst_type = &env->insn_aux_data[env->insn_idx].ptr_type;\n\n\t\t\tif (*prev_dst_type == NOT_INIT) {\n\t\t\t\t*prev_dst_type = dst_reg_type;\n\t\t\t} else if (reg_type_mismatch(dst_reg_type, *prev_dst_type)) {\n\t\t\t\tverbose(env, \"same insn cannot be used with different pointers\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t} else if (class == BPF_ST) {\n\t\t\tif (BPF_MODE(insn->code) != BPF_MEM ||\n\t\t\t    insn->src_reg != BPF_REG_0) {\n\t\t\t\tverbose(env, \"BPF_ST uses reserved fields\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\t/* check src operand */\n\t\t\terr = check_reg_arg(env, insn->dst_reg, SRC_OP);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tif (is_ctx_reg(env, insn->dst_reg)) {\n\t\t\t\tverbose(env, \"BPF_ST stores into R%d %s is not allowed\\n\",\n\t\t\t\t\tinsn->dst_reg,\n\t\t\t\t\treg_type_str(env, reg_state(env, insn->dst_reg)->type));\n\t\t\t\treturn -EACCES;\n\t\t\t}\n\n\t\t\t/* check that memory (dst_reg + off) is writeable */\n\t\t\terr = check_mem_access(env, env->insn_idx, insn->dst_reg,\n\t\t\t\t\t       insn->off, BPF_SIZE(insn->code),\n\t\t\t\t\t       BPF_WRITE, -1, false);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t} else if (class == BPF_JMP || class == BPF_JMP32) {\n\t\t\tu8 opcode = BPF_OP(insn->code);\n\n\t\t\tenv->jmps_processed++;\n\t\t\tif (opcode == BPF_CALL) {\n\t\t\t\tif (BPF_SRC(insn->code) != BPF_K ||\n\t\t\t\t    (insn->src_reg != BPF_PSEUDO_KFUNC_CALL\n\t\t\t\t     && insn->off != 0) ||\n\t\t\t\t    (insn->src_reg != BPF_REG_0 &&\n\t\t\t\t     insn->src_reg != BPF_PSEUDO_CALL &&\n\t\t\t\t     insn->src_reg != BPF_PSEUDO_KFUNC_CALL) ||\n\t\t\t\t    insn->dst_reg != BPF_REG_0 ||\n\t\t\t\t    class == BPF_JMP32) {\n\t\t\t\t\tverbose(env, \"BPF_CALL uses reserved fields\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\n\t\t\t\tif (env->cur_state->active_spin_lock &&\n\t\t\t\t    (insn->src_reg == BPF_PSEUDO_CALL ||\n\t\t\t\t     insn->imm != BPF_FUNC_spin_unlock)) {\n\t\t\t\t\tverbose(env, \"function calls are not allowed while holding a lock\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\t\t\t\tif (insn->src_reg == BPF_PSEUDO_CALL)\n\t\t\t\t\terr = check_func_call(env, insn, &env->insn_idx);\n\t\t\t\telse if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL)\n\t\t\t\t\terr = check_kfunc_call(env, insn, &env->insn_idx);\n\t\t\t\telse\n\t\t\t\t\terr = check_helper_call(env, insn, &env->insn_idx);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\n\t\t\t} else if (opcode == BPF_JA) {\n\t\t\t\tif (BPF_SRC(insn->code) != BPF_K ||\n\t\t\t\t    insn->imm != 0 ||\n\t\t\t\t    insn->src_reg != BPF_REG_0 ||\n\t\t\t\t    insn->dst_reg != BPF_REG_0 ||\n\t\t\t\t    class == BPF_JMP32) {\n\t\t\t\t\tverbose(env, \"BPF_JA uses reserved fields\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\n\t\t\t\tenv->insn_idx += insn->off + 1;\n\t\t\t\tcontinue;\n\n\t\t\t} else if (opcode == BPF_EXIT) {\n\t\t\t\tif (BPF_SRC(insn->code) != BPF_K ||\n\t\t\t\t    insn->imm != 0 ||\n\t\t\t\t    insn->src_reg != BPF_REG_0 ||\n\t\t\t\t    insn->dst_reg != BPF_REG_0 ||\n\t\t\t\t    class == BPF_JMP32) {\n\t\t\t\t\tverbose(env, \"BPF_EXIT uses reserved fields\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\n\t\t\t\tif (env->cur_state->active_spin_lock) {\n\t\t\t\t\tverbose(env, \"bpf_spin_unlock is missing\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\n\t\t\t\tif (state->curframe) {\n\t\t\t\t\t/* exit from nested function */\n\t\t\t\t\terr = prepare_func_exit(env, &env->insn_idx);\n\t\t\t\t\tif (err)\n\t\t\t\t\t\treturn err;\n\t\t\t\t\tdo_print_state = true;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\terr = check_reference_leak(env);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\n\n\t\t\t\terr = check_return_code(env);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\nprocess_bpf_exit:\n\t\t\t\tmark_verifier_state_scratched(env);\n\t\t\t\tupdate_branch_counts(env, env->cur_state);\n\t\t\t\terr = pop_stack(env, &prev_insn_idx,\n\t\t\t\t\t\t&env->insn_idx, pop_log);\n\t\t\t\tif (err < 0) {\n\t\t\t\t\tif (err != -ENOENT)\n\t\t\t\t\t\treturn err;\n\t\t\t\t\tbreak;\n\t\t\t\t} else {\n\t\t\t\t\tdo_print_state = true;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\terr = check_cond_jmp_op(env, insn, &env->insn_idx);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\n\t\t\t}\n\t\t} else if (class == BPF_LD) {\n\t\t\tu8 mode = BPF_MODE(insn->code);\n\n\t\t\tif (mode == BPF_ABS || mode == BPF_IND) {\n\t\t\t\terr = check_ld_abs(env, insn);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\n\n\t\t\t} else if (mode == BPF_IMM) {\n\t\t\t\terr = check_ld_imm(env, insn);\n\t\t\t\tif (err)\n\t\t\t\t\treturn err;\n\n\t\t\t\tenv->insn_idx++;\n\t\t\t\tsanitize_mark_insn_seen(env);\n\t\t\t} else {\n\t\t\t\tverbose(env, \"invalid BPF_LD mode\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t} else {\n\t\t\tverbose(env, \"unknown insn class %d\\n\", class);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tenv->insn_idx++;\n\t}\n\n\treturn 0;\n}",
        "static int wwan_hwsim_port_tx(struct wwan_port *wport, struct sk_buff *in)\n{\n\tstruct wwan_hwsim_port *port = wwan_port_get_drvdata(wport);\n\tstruct sk_buff *out;\n\tint i, n, s;": "static int wwan_hwsim_port_tx(struct wwan_port *wport, struct sk_buff *in)\n{\n\tstruct wwan_hwsim_port *port = wwan_port_get_drvdata(wport);\n\tstruct sk_buff *out;\n\tint i, n, s;\n\n\t/* Estimate a max possible number of commands by counting the number of\n\t * termination chars (S3 param, CR by default). And then allocate the\n\t * output buffer that will be enough to fit the echo and result codes of\n\t * all commands.\n\t */\n\tfor (i = 0, n = 0; i < in->len; ++i)\n\t\tif (in->data[i] == '\\r')\n\t\t\tn++;\n\tn = in->len + n * (2 + 2 + 2);\t/* Output buffer size */\n\tout = alloc_skb(n, GFP_KERNEL);\n\tif (!out)\n\t\treturn -ENOMEM;\n\n\tfor (i = 0, s = 0; i < in->len; ++i) {\n\t\tchar c = in->data[i];\n\n\t\tif (port->pstate == AT_PARSER_WAIT_A) {\n\t\t\tif (c == 'A' || c == 'a')\n\t\t\t\tport->pstate = AT_PARSER_WAIT_T;\n\t\t\telse if (c != '\\n')\t/* Ignore formating char */\n\t\t\t\tport->pstate = AT_PARSER_SKIP_LINE;\n\t\t} else if (port->pstate == AT_PARSER_WAIT_T) {\n\t\t\tif (c == 'T' || c == 't')\n\t\t\t\tport->pstate = AT_PARSER_WAIT_TERM;\n\t\t\telse\n\t\t\t\tport->pstate = AT_PARSER_SKIP_LINE;\n\t\t} else if (port->pstate == AT_PARSER_WAIT_TERM) {\n\t\t\tif (c != '\\r')\n\t\t\t\tcontinue;\n\t\t\t/* Consume the trailing formatting char as well */\n\t\t\tif ((i + 1) < in->len && in->data[i + 1] == '\\n')\n\t\t\t\ti++;\n\t\t\tn = i - s + 1;\n\t\t\tmemcpy(skb_put(out, n), &in->data[s], n);/* Echo */\n\t\t\tmemcpy(skb_put(out, 6), \"\\r\\nOK\\r\\n\", 6);\n\t\t\ts = i + 1;\n\t\t\tport->pstate = AT_PARSER_WAIT_A;\n\t\t} else if (port->pstate == AT_PARSER_SKIP_LINE) {\n\t\t\tif (c != '\\r')\n\t\t\t\tcontinue;\n\t\t\tport->pstate = AT_PARSER_WAIT_A;\n\t\t}\n\t}\n\n\tif (i > s) {\n\t\t/* Echo the processed portion of a not yet completed command */\n\t\tn = i - s;\n\t\tmemcpy(skb_put(out, n), &in->data[s], n);\n\t}\n\n\tconsume_skb(in);\n\n\twwan_port_rx(wport, out);\n\n\treturn 0;\n}",
        "static int process_recorded_refs(struct send_ctx *sctx, int *pending_move)\n{\n\tstruct btrfs_fs_info *fs_info = sctx->send_root->fs_info;\n\tint ret = 0;\n\tstruct recorded_ref *cur;": "static int process_recorded_refs(struct send_ctx *sctx, int *pending_move)\n{\n\tstruct btrfs_fs_info *fs_info = sctx->send_root->fs_info;\n\tint ret = 0;\n\tstruct recorded_ref *cur;\n\tstruct recorded_ref *cur2;\n\tstruct list_head check_dirs;\n\tstruct fs_path *valid_path = NULL;\n\tu64 ow_inode = 0;\n\tu64 ow_gen;\n\tu64 ow_mode;\n\tint did_overwrite = 0;\n\tint is_orphan = 0;\n\tu64 last_dir_ino_rm = 0;\n\tbool can_rename = true;\n\tbool orphanized_dir = false;\n\tbool orphanized_ancestor = false;\n\n\tbtrfs_debug(fs_info, \"process_recorded_refs %llu\", sctx->cur_ino);\n\n\t/*\n\t * This should never happen as the root dir always has the same ref\n\t * which is always '..'\n\t */\n\tBUG_ON(sctx->cur_ino <= BTRFS_FIRST_FREE_OBJECTID);\n\tINIT_LIST_HEAD(&check_dirs);\n\n\tvalid_path = fs_path_alloc();\n\tif (!valid_path) {\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * First, check if the first ref of the current inode was overwritten\n\t * before. If yes, we know that the current inode was already orphanized\n\t * and thus use the orphan name. If not, we can use get_cur_path to\n\t * get the path of the first ref as it would like while receiving at\n\t * this point in time.\n\t * New inodes are always orphan at the beginning, so force to use the\n\t * orphan name in this case.\n\t * The first ref is stored in valid_path and will be updated if it\n\t * gets moved around.\n\t */\n\tif (!sctx->cur_inode_new) {\n\t\tret = did_overwrite_first_ref(sctx, sctx->cur_ino,\n\t\t\t\tsctx->cur_inode_gen);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (ret)\n\t\t\tdid_overwrite = 1;\n\t}\n\tif (sctx->cur_inode_new || did_overwrite) {\n\t\tret = gen_unique_name(sctx, sctx->cur_ino,\n\t\t\t\tsctx->cur_inode_gen, valid_path);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tis_orphan = 1;\n\t} else {\n\t\tret = get_cur_path(sctx, sctx->cur_ino, sctx->cur_inode_gen,\n\t\t\t\tvalid_path);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t}\n\n\t/*\n\t * Before doing any rename and link operations, do a first pass on the\n\t * new references to orphanize any unprocessed inodes that may have a\n\t * reference that conflicts with one of the new references of the current\n\t * inode. This needs to happen first because a new reference may conflict\n\t * with the old reference of a parent directory, so we must make sure\n\t * that the path used for link and rename commands don't use an\n\t * orphanized name when an ancestor was not yet orphanized.\n\t *\n\t * Example:\n\t *\n\t * Parent snapshot:\n\t *\n\t * .                                                      (ino 256)\n\t * |----- testdir/                                        (ino 259)\n\t * |          |----- a                                    (ino 257)\n\t * |\n\t * |----- b                                               (ino 258)\n\t *\n\t * Send snapshot:\n\t *\n\t * .                                                      (ino 256)\n\t * |----- testdir_2/                                      (ino 259)\n\t * |          |----- a                                    (ino 260)\n\t * |\n\t * |----- testdir                                         (ino 257)\n\t * |----- b                                               (ino 257)\n\t * |----- b2                                              (ino 258)\n\t *\n\t * Processing the new reference for inode 257 with name \"b\" may happen\n\t * before processing the new reference with name \"testdir\". If so, we\n\t * must make sure that by the time we send a link command to create the\n\t * hard link \"b\", inode 259 was already orphanized, since the generated\n\t * path in \"valid_path\" already contains the orphanized name for 259.\n\t * We are processing inode 257, so only later when processing 259 we do\n\t * the rename operation to change its temporary (orphanized) name to\n\t * \"testdir_2\".\n\t */\n\tlist_for_each_entry(cur, &sctx->new_refs, list) {\n\t\tret = get_cur_inode_state(sctx, cur->dir, cur->dir_gen);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (ret == inode_state_will_create)\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * Check if this new ref would overwrite the first ref of another\n\t\t * unprocessed inode. If yes, orphanize the overwritten inode.\n\t\t * If we find an overwritten ref that is not the first ref,\n\t\t * simply unlink it.\n\t\t */\n\t\tret = will_overwrite_ref(sctx, cur->dir, cur->dir_gen,\n\t\t\t\tcur->name, cur->name_len,\n\t\t\t\t&ow_inode, &ow_gen, &ow_mode);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (ret) {\n\t\t\tret = is_first_ref(sctx->parent_root,\n\t\t\t\t\t   ow_inode, cur->dir, cur->name,\n\t\t\t\t\t   cur->name_len);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tif (ret) {\n\t\t\t\tstruct name_cache_entry *nce;\n\t\t\t\tstruct waiting_dir_move *wdm;\n\n\t\t\t\tif (orphanized_dir) {\n\t\t\t\t\tret = refresh_ref_path(sctx, cur);\n\t\t\t\t\tif (ret < 0)\n\t\t\t\t\t\tgoto out;\n\t\t\t\t}\n\n\t\t\t\tret = orphanize_inode(sctx, ow_inode, ow_gen,\n\t\t\t\t\t\tcur->full_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t\tif (S_ISDIR(ow_mode))\n\t\t\t\t\torphanized_dir = true;\n\n\t\t\t\t/*\n\t\t\t\t * If ow_inode has its rename operation delayed\n\t\t\t\t * make sure that its orphanized name is used in\n\t\t\t\t * the source path when performing its rename\n\t\t\t\t * operation.\n\t\t\t\t */\n\t\t\t\tif (is_waiting_for_move(sctx, ow_inode)) {\n\t\t\t\t\twdm = get_waiting_dir_move(sctx,\n\t\t\t\t\t\t\t\t   ow_inode);\n\t\t\t\t\tASSERT(wdm);\n\t\t\t\t\twdm->orphanized = true;\n\t\t\t\t}\n\n\t\t\t\t/*\n\t\t\t\t * Make sure we clear our orphanized inode's\n\t\t\t\t * name from the name cache. This is because the\n\t\t\t\t * inode ow_inode might be an ancestor of some\n\t\t\t\t * other inode that will be orphanized as well\n\t\t\t\t * later and has an inode number greater than\n\t\t\t\t * sctx->send_progress. We need to prevent\n\t\t\t\t * future name lookups from using the old name\n\t\t\t\t * and get instead the orphan name.\n\t\t\t\t */\n\t\t\t\tnce = name_cache_search(sctx, ow_inode, ow_gen);\n\t\t\t\tif (nce) {\n\t\t\t\t\tname_cache_delete(sctx, nce);\n\t\t\t\t\tkfree(nce);\n\t\t\t\t}\n\n\t\t\t\t/*\n\t\t\t\t * ow_inode might currently be an ancestor of\n\t\t\t\t * cur_ino, therefore compute valid_path (the\n\t\t\t\t * current path of cur_ino) again because it\n\t\t\t\t * might contain the pre-orphanization name of\n\t\t\t\t * ow_inode, which is no longer valid.\n\t\t\t\t */\n\t\t\t\tret = is_ancestor(sctx->parent_root,\n\t\t\t\t\t\t  ow_inode, ow_gen,\n\t\t\t\t\t\t  sctx->cur_ino, NULL);\n\t\t\t\tif (ret > 0) {\n\t\t\t\t\torphanized_ancestor = true;\n\t\t\t\t\tfs_path_reset(valid_path);\n\t\t\t\t\tret = get_cur_path(sctx, sctx->cur_ino,\n\t\t\t\t\t\t\t   sctx->cur_inode_gen,\n\t\t\t\t\t\t\t   valid_path);\n\t\t\t\t}\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t} else {\n\t\t\t\t/*\n\t\t\t\t * If we previously orphanized a directory that\n\t\t\t\t * collided with a new reference that we already\n\t\t\t\t * processed, recompute the current path because\n\t\t\t\t * that directory may be part of the path.\n\t\t\t\t */\n\t\t\t\tif (orphanized_dir) {\n\t\t\t\t\tret = refresh_ref_path(sctx, cur);\n\t\t\t\t\tif (ret < 0)\n\t\t\t\t\t\tgoto out;\n\t\t\t\t}\n\t\t\t\tret = send_unlink(sctx, cur->full_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t}\n\n\tlist_for_each_entry(cur, &sctx->new_refs, list) {\n\t\t/*\n\t\t * We may have refs where the parent directory does not exist\n\t\t * yet. This happens if the parent directories inum is higher\n\t\t * than the current inum. To handle this case, we create the\n\t\t * parent directory out of order. But we need to check if this\n\t\t * did already happen before due to other refs in the same dir.\n\t\t */\n\t\tret = get_cur_inode_state(sctx, cur->dir, cur->dir_gen);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (ret == inode_state_will_create) {\n\t\t\tret = 0;\n\t\t\t/*\n\t\t\t * First check if any of the current inodes refs did\n\t\t\t * already create the dir.\n\t\t\t */\n\t\t\tlist_for_each_entry(cur2, &sctx->new_refs, list) {\n\t\t\t\tif (cur == cur2)\n\t\t\t\t\tbreak;\n\t\t\t\tif (cur2->dir == cur->dir) {\n\t\t\t\t\tret = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * If that did not happen, check if a previous inode\n\t\t\t * did already create the dir.\n\t\t\t */\n\t\t\tif (!ret)\n\t\t\t\tret = did_create_dir(sctx, cur->dir);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tif (!ret) {\n\t\t\t\tret = send_create_inode(sctx, cur->dir);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\n\t\tif (S_ISDIR(sctx->cur_inode_mode) && sctx->parent_root) {\n\t\t\tret = wait_for_dest_dir_move(sctx, cur, is_orphan);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tif (ret == 1) {\n\t\t\t\tcan_rename = false;\n\t\t\t\t*pending_move = 1;\n\t\t\t}\n\t\t}\n\n\t\tif (S_ISDIR(sctx->cur_inode_mode) && sctx->parent_root &&\n\t\t    can_rename) {\n\t\t\tret = wait_for_parent_move(sctx, cur, is_orphan);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tif (ret == 1) {\n\t\t\t\tcan_rename = false;\n\t\t\t\t*pending_move = 1;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * link/move the ref to the new place. If we have an orphan\n\t\t * inode, move it and update valid_path. If not, link or move\n\t\t * it depending on the inode mode.\n\t\t */\n\t\tif (is_orphan && can_rename) {\n\t\t\tret = send_rename(sctx, valid_path, cur->full_path);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tis_orphan = 0;\n\t\t\tret = fs_path_copy(valid_path, cur->full_path);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t} else if (can_rename) {\n\t\t\tif (S_ISDIR(sctx->cur_inode_mode)) {\n\t\t\t\t/*\n\t\t\t\t * Dirs can't be linked, so move it. For moved\n\t\t\t\t * dirs, we always have one new and one deleted\n\t\t\t\t * ref. The deleted ref is ignored later.\n\t\t\t\t */\n\t\t\t\tret = send_rename(sctx, valid_path,\n\t\t\t\t\t\t  cur->full_path);\n\t\t\t\tif (!ret)\n\t\t\t\t\tret = fs_path_copy(valid_path,\n\t\t\t\t\t\t\t   cur->full_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t} else {\n\t\t\t\t/*\n\t\t\t\t * We might have previously orphanized an inode\n\t\t\t\t * which is an ancestor of our current inode,\n\t\t\t\t * so our reference's full path, which was\n\t\t\t\t * computed before any such orphanizations, must\n\t\t\t\t * be updated.\n\t\t\t\t */\n\t\t\t\tif (orphanized_dir) {\n\t\t\t\t\tret = update_ref_path(sctx, cur);\n\t\t\t\t\tif (ret < 0)\n\t\t\t\t\t\tgoto out;\n\t\t\t\t}\n\t\t\t\tret = send_link(sctx, cur->full_path,\n\t\t\t\t\t\tvalid_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t\tret = dup_ref(cur, &check_dirs);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t}\n\n\tif (S_ISDIR(sctx->cur_inode_mode) && sctx->cur_inode_deleted) {\n\t\t/*\n\t\t * Check if we can already rmdir the directory. If not,\n\t\t * orphanize it. For every dir item inside that gets deleted\n\t\t * later, we do this check again and rmdir it then if possible.\n\t\t * See the use of check_dirs for more details.\n\t\t */\n\t\tret = can_rmdir(sctx, sctx->cur_ino, sctx->cur_inode_gen,\n\t\t\t\tsctx->cur_ino);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t\tif (ret) {\n\t\t\tret = send_rmdir(sctx, valid_path);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t} else if (!is_orphan) {\n\t\t\tret = orphanize_inode(sctx, sctx->cur_ino,\n\t\t\t\t\tsctx->cur_inode_gen, valid_path);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tis_orphan = 1;\n\t\t}\n\n\t\tlist_for_each_entry(cur, &sctx->deleted_refs, list) {\n\t\t\tret = dup_ref(cur, &check_dirs);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t}\n\t} else if (S_ISDIR(sctx->cur_inode_mode) &&\n\t\t   !list_empty(&sctx->deleted_refs)) {\n\t\t/*\n\t\t * We have a moved dir. Add the old parent to check_dirs\n\t\t */\n\t\tcur = list_entry(sctx->deleted_refs.next, struct recorded_ref,\n\t\t\t\tlist);\n\t\tret = dup_ref(cur, &check_dirs);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\t} else if (!S_ISDIR(sctx->cur_inode_mode)) {\n\t\t/*\n\t\t * We have a non dir inode. Go through all deleted refs and\n\t\t * unlink them if they were not already overwritten by other\n\t\t * inodes.\n\t\t */\n\t\tlist_for_each_entry(cur, &sctx->deleted_refs, list) {\n\t\t\tret = did_overwrite_ref(sctx, cur->dir, cur->dir_gen,\n\t\t\t\t\tsctx->cur_ino, sctx->cur_inode_gen,\n\t\t\t\t\tcur->name, cur->name_len);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tif (!ret) {\n\t\t\t\t/*\n\t\t\t\t * If we orphanized any ancestor before, we need\n\t\t\t\t * to recompute the full path for deleted names,\n\t\t\t\t * since any such path was computed before we\n\t\t\t\t * processed any references and orphanized any\n\t\t\t\t * ancestor inode.\n\t\t\t\t */\n\t\t\t\tif (orphanized_ancestor) {\n\t\t\t\t\tret = update_ref_path(sctx, cur);\n\t\t\t\t\tif (ret < 0)\n\t\t\t\t\t\tgoto out;\n\t\t\t\t}\n\t\t\t\tret = send_unlink(sctx, cur->full_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tret = dup_ref(cur, &check_dirs);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t}\n\t\t/*\n\t\t * If the inode is still orphan, unlink the orphan. This may\n\t\t * happen when a previous inode did overwrite the first ref\n\t\t * of this inode and no new refs were added for the current\n\t\t * inode. Unlinking does not mean that the inode is deleted in\n\t\t * all cases. There may still be links to this inode in other\n\t\t * places.\n\t\t */\n\t\tif (is_orphan) {\n\t\t\tret = send_unlink(sctx, valid_path);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/*\n\t * We did collect all parent dirs where cur_inode was once located. We\n\t * now go through all these dirs and check if they are pending for\n\t * deletion and if it's finally possible to perform the rmdir now.\n\t * We also update the inode stats of the parent dirs here.\n\t */\n\tlist_for_each_entry(cur, &check_dirs, list) {\n\t\t/*\n\t\t * In case we had refs into dirs that were not processed yet,\n\t\t * we don't need to do the utime and rmdir logic for these dirs.\n\t\t * The dir will be processed later.\n\t\t */\n\t\tif (cur->dir > sctx->cur_ino)\n\t\t\tcontinue;\n\n\t\tret = get_cur_inode_state(sctx, cur->dir, cur->dir_gen);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\n\t\tif (ret == inode_state_did_create ||\n\t\t    ret == inode_state_no_change) {\n\t\t\t/* TODO delayed utimes */\n\t\t\tret = send_utimes(sctx, cur->dir, cur->dir_gen);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t} else if (ret == inode_state_did_delete &&\n\t\t\t   cur->dir != last_dir_ino_rm) {\n\t\t\tret = can_rmdir(sctx, cur->dir, cur->dir_gen,\n\t\t\t\t\tsctx->cur_ino);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out;\n\t\t\tif (ret) {\n\t\t\t\tret = get_cur_path(sctx, cur->dir,\n\t\t\t\t\t\t   cur->dir_gen, valid_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t\tret = send_rmdir(sctx, valid_path);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tgoto out;\n\t\t\t\tlast_dir_ino_rm = cur->dir;\n\t\t\t}\n\t\t}\n\t}\n\n\tret = 0;\n\nout:\n\t__free_recorded_refs(&check_dirs);\n\tfree_recorded_refs(sctx);\n\tfs_path_free(valid_path);\n\treturn ret;\n}",
        "static int poison_channel(struct most_interface *most_iface, int ch_idx)\n{\n\tstruct dim2_hdm *dev = iface_to_hdm(most_iface);\n\tstruct hdm_channel *hdm_ch = dev->hch + ch_idx;\n\tunsigned long flags;": "static int poison_channel(struct most_interface *most_iface, int ch_idx)\n{\n\tstruct dim2_hdm *dev = iface_to_hdm(most_iface);\n\tstruct hdm_channel *hdm_ch = dev->hch + ch_idx;\n\tunsigned long flags;\n\tu8 hal_ret;\n\tint ret = 0;\n\n\tBUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);\n\n\tif (!hdm_ch->is_initialized)\n\t\treturn -EPERM;\n\n\tspin_lock_irqsave(&dim_lock, flags);\n\thal_ret = dim_destroy_channel(&hdm_ch->ch);\n\thdm_ch->is_initialized = false;\n\tif (ch_idx == dev->atx_idx)\n\t\tdev->atx_idx = -1;\n\tspin_unlock_irqrestore(&dim_lock, flags);\n\tif (hal_ret != DIM_NO_ERROR) {\n\t\tpr_err(\"HAL Failed to close channel %s\\n\", hdm_ch->name);\n\t\tret = -EFAULT;\n\t}\n\n\tcomplete_all_mbos(&hdm_ch->started_list);\n\tcomplete_all_mbos(&hdm_ch->pending_list);\n\tif (hdm_ch->reset_dbr_size)\n\t\t*hdm_ch->reset_dbr_size = 0;\n\n\treturn ret;\n}",
        "static void frwr_wc_localinv_done(struct ib_cq *cq, struct ib_wc *wc)\n{\n\tstruct ib_cqe *cqe = wc->wr_cqe;\n\tstruct rpcrdma_mr *mr = container_of(cqe, struct rpcrdma_mr, mr_cqe);\n\tstruct rpcrdma_rep *rep;": "static void frwr_wc_localinv_done(struct ib_cq *cq, struct ib_wc *wc)\n{\n\tstruct ib_cqe *cqe = wc->wr_cqe;\n\tstruct rpcrdma_mr *mr = container_of(cqe, struct rpcrdma_mr, mr_cqe);\n\tstruct rpcrdma_rep *rep;\n\n\t/* WARNING: Only wr_cqe and status are reliable at this point */\n\ttrace_xprtrdma_wc_li_done(wc, &mr->mr_cid);\n\n\t/* Ensure that @rep is generated before the MR is released */\n\trep = mr->mr_req->rl_reply;\n\tsmp_rmb();\n\n\tif (wc->status != IB_WC_SUCCESS) {\n\t\tif (rep)\n\t\t\trpcrdma_unpin_rqst(rep);\n\t\trpcrdma_flush_disconnect(cq->cq_context, wc);\n\t\treturn;\n\t}\n\tfrwr_mr_put(mr);\n\trpcrdma_complete_rqst(rep);\n}",
        "static int ksm_merge_time(int mapping, int prot, int timeout, size_t map_size)\n{\n\tvoid *map_ptr;\n\tstruct timespec start_time, end_time;\n\tunsigned long scan_time_ns;": "static int ksm_merge_time(int mapping, int prot, int timeout, size_t map_size)\n{\n\tvoid *map_ptr;\n\tstruct timespec start_time, end_time;\n\tunsigned long scan_time_ns;\n\n\tmap_size *= MB;\n\n\tmap_ptr = allocate_memory(NULL, prot, mapping, '*', map_size);\n\tif (!map_ptr)\n\t\treturn KSFT_FAIL;\n\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &start_time)) {\n\t\tperror(\"clock_gettime\");\n\t\tgoto err_out;\n\t}\n\tif (ksm_merge_pages(map_ptr, map_size, start_time, timeout))\n\t\tgoto err_out;\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &end_time)) {\n\t\tperror(\"clock_gettime\");\n\t\tgoto err_out;\n\t}\n\n\tscan_time_ns = (end_time.tv_sec - start_time.tv_sec) * NSEC_PER_SEC +\n\t\t       (end_time.tv_nsec - start_time.tv_nsec);\n\n\tprintf(\"Total size:    %lu MiB\\n\", map_size / MB);\n\tprintf(\"Total time:    %ld.%09ld s\\n\", scan_time_ns / NSEC_PER_SEC,\n\t       scan_time_ns % NSEC_PER_SEC);\n\tprintf(\"Average speed:  %.3f MiB/s\\n\", (map_size / MB) /\n\t\t\t\t\t       ((double)scan_time_ns / NSEC_PER_SEC));\n\n\tmunmap(map_ptr, map_size);\n\treturn KSFT_PASS;\n\nerr_out:\n\tprintf(\"Not OK\\n\");\n\tmunmap(map_ptr, map_size);\n\treturn KSFT_FAIL;\n}",
        "static void wm8775_set_audio(struct v4l2_subdev *sd, int quietly)\n{\n\tstruct wm8775_state *state = to_state(sd);\n\tu8 vol_l, vol_r;\n\tint muted = 0 != state->mute->val;": "static void wm8775_set_audio(struct v4l2_subdev *sd, int quietly)\n{\n\tstruct wm8775_state *state = to_state(sd);\n\tu8 vol_l, vol_r;\n\tint muted = 0 != state->mute->val;\n\tu16 volume = (u16)state->vol->val;\n\tu16 balance = (u16)state->bal->val;\n\n\t/* normalize ( 65535 to 0 -> 255 to 0 (+24dB to -103dB) ) */\n\tvol_l = (min(65536 - balance, 32768) * volume) >> 23;\n\tvol_r = (min(balance, (u16)32768) * volume) >> 23;\n\n\t/* Mute */\n\tif (muted || quietly)\n\t\twm8775_write(sd, R21, 0x0c0 | state->input);\n\n\twm8775_write(sd, R14, vol_l | 0x100); /* 0x100= Left channel ADC zero cross enable */\n\twm8775_write(sd, R15, vol_r | 0x100); /* 0x100= Right channel ADC zero cross enable */\n\n\t/* Un-mute */\n\tif (!muted)\n\t\twm8775_write(sd, R21, state->input);\n}",
        "static int vc032x_probe_sensor(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint i, n;\n\tu16 value;": "static int vc032x_probe_sensor(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint i, n;\n\tu16 value;\n\tconst struct sensor_info *ptsensor_info;\n\n/*fixme: should also check the other sensor (back mi1320_soc, front mc501cb)*/\n\tif (sd->flags & FL_SAMSUNG) {\n\t\treg_w(gspca_dev, 0xa0, 0x01, 0xb301);\n\t\treg_w(gspca_dev, 0x89, 0xf0ff, 0xffff);\n\t\t\t\t\t\t/* select the back sensor */\n\t}\n\n\treg_r(gspca_dev, 0xa1, 0xbfcf, 1);\n\tgspca_dbg(gspca_dev, D_PROBE, \"vc032%d check sensor header %02x\\n\",\n\t\t  sd->bridge == BRIDGE_VC0321 ? 1 : 3, gspca_dev->usb_buf[0]);\n\tif (sd->bridge == BRIDGE_VC0321) {\n\t\tptsensor_info = vc0321_probe_data;\n\t\tn = ARRAY_SIZE(vc0321_probe_data);\n\t} else {\n\t\tptsensor_info = vc0323_probe_data;\n\t\tn = ARRAY_SIZE(vc0323_probe_data);\n\t}\n\tfor (i = 0; i < n; i++) {\n\t\treg_w(gspca_dev, 0xa0, 0x02, 0xb334);\n\t\treg_w(gspca_dev, 0xa0, ptsensor_info->m1, 0xb300);\n\t\treg_w(gspca_dev, 0xa0, ptsensor_info->m2, 0xb300);\n\t\treg_w(gspca_dev, 0xa0, 0x01, 0xb308);\n\t\treg_w(gspca_dev, 0xa0, 0x0c, 0xb309);\n\t\treg_w(gspca_dev, 0xa0, ptsensor_info->I2cAdd, 0xb335);\n\t\treg_w(gspca_dev, 0xa0, ptsensor_info->op, 0xb301);\n\t\tvalue = read_sensor_register(gspca_dev, ptsensor_info->IdAdd);\n\t\tif (value == 0 && ptsensor_info->IdAdd == 0x82)\n\t\t\tvalue = read_sensor_register(gspca_dev, 0x83);\n\t\tif (value != 0) {\n\t\t\tgspca_dbg(gspca_dev, D_PROBE, \"Sensor ID %04x (%d)\\n\",\n\t\t\t\t  value, i);\n\t\t\tif (value == ptsensor_info->VpId)\n\t\t\t\treturn ptsensor_info->sensorId;\n\n\t\t\tswitch (value) {\n\t\t\tcase 0x3130:\n\t\t\t\treturn SENSOR_PO3130NC;\n\t\t\tcase 0x7673:\n\t\t\t\treturn SENSOR_OV7670;\n\t\t\tcase 0x8243:\n\t\t\t\treturn SENSOR_MI0360;\n\t\t\t}\n\t\t}\n\t\tptsensor_info++;\n\t}\n\treturn -1;\n}",
        "static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, int sev)\n{\n\tstruct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);\n\tbool queued = false;\n\tint sec_sev, i;": "static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, int sev)\n{\n\tstruct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);\n\tbool queued = false;\n\tint sec_sev, i;\n\tchar *p;\n\n\tlog_arm_hw_error(err);\n\n\tsec_sev = ghes_severity(gdata->error_severity);\n\tif (sev != GHES_SEV_RECOVERABLE || sec_sev != GHES_SEV_RECOVERABLE)\n\t\treturn false;\n\n\tp = (char *)(err + 1);\n\tfor (i = 0; i < err->err_info_num; i++) {\n\t\tstruct cper_arm_err_info *err_info = (struct cper_arm_err_info *)p;\n\t\tbool is_cache = (err_info->type == CPER_ARM_CACHE_ERROR);\n\t\tbool has_pa = (err_info->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR);\n\t\tconst char *error_type = \"unknown error\";\n\n\t\t/*\n\t\t * The field (err_info->error_info & BIT(26)) is fixed to set to\n\t\t * 1 in some old firmware of HiSilicon Kunpeng920. We assume that\n\t\t * firmware won't mix corrected errors in an uncorrected section,\n\t\t * and don't filter out 'corrected' error here.\n\t\t */\n\t\tif (is_cache && has_pa) {\n\t\t\tqueued = ghes_do_memory_failure(err_info->physical_fault_addr, 0);\n\t\t\tp += err_info->length;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (err_info->type < ARRAY_SIZE(cper_proc_error_type_strs))\n\t\t\terror_type = cper_proc_error_type_strs[err_info->type];\n\n\t\tpr_warn_ratelimited(FW_WARN GHES_PFX\n\t\t\t\t    \"Unhandled processor error type: %s\\n\",\n\t\t\t\t    error_type);\n\t\tp += err_info->length;\n\t}\n\n\treturn queued;\n}",
        "static int imgu_css_map_init(struct imgu_css *css, unsigned int pipe)\n{\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tunsigned int p, q, i;": "static int imgu_css_map_init(struct imgu_css *css, unsigned int pipe)\n{\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tunsigned int p, q, i;\n\n\t/* Allocate and map common structures with imgu hardware */\n\tfor (p = 0; p < IPU3_CSS_PIPE_ID_NUM; p++)\n\t\tfor (i = 0; i < IMGU_ABI_MAX_STAGES; i++) {\n\t\t\tif (!imgu_dmamap_alloc(imgu,\n\t\t\t\t\t       &css_pipe->\n\t\t\t\t\t       xmem_sp_stage_ptrs[p][i],\n\t\t\t\t\t       sizeof(struct imgu_abi_sp_stage)))\n\t\t\t\treturn -ENOMEM;\n\t\t\tif (!imgu_dmamap_alloc(imgu,\n\t\t\t\t\t       &css_pipe->\n\t\t\t\t\t       xmem_isp_stage_ptrs[p][i],\n\t\t\t\t\t       sizeof(struct imgu_abi_isp_stage)))\n\t\t\t\treturn -ENOMEM;\n\t\t}\n\n\tif (!imgu_dmamap_alloc(imgu, &css_pipe->sp_ddr_ptrs,\n\t\t\t       ALIGN(sizeof(struct imgu_abi_ddr_address_map),\n\t\t\t\t     IMGU_ABI_ISP_DDR_WORD_BYTES)))\n\t\treturn -ENOMEM;\n\n\tfor (q = 0; q < IPU3_CSS_QUEUES; q++) {\n\t\tunsigned int abi_buf_num = ARRAY_SIZE(css_pipe->abi_buffers[q]);\n\n\t\tfor (i = 0; i < abi_buf_num; i++)\n\t\t\tif (!imgu_dmamap_alloc(imgu,\n\t\t\t\t\t       &css_pipe->abi_buffers[q][i],\n\t\t\t\t\t       sizeof(struct imgu_abi_buffer)))\n\t\t\t\treturn -ENOMEM;\n\t}\n\n\tif (imgu_css_binary_preallocate(css, pipe)) {\n\t\timgu_css_binary_cleanup(css, pipe);\n\t\treturn -ENOMEM;\n\t}\n\n\treturn 0;\n}",
        "static int io_tee(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_splice *sp = &req->splice;\n\tstruct file *out = sp->file_out;\n\tunsigned int flags = sp->flags & ~SPLICE_F_FD_IN_FIXED;": "static int io_tee(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_splice *sp = &req->splice;\n\tstruct file *out = sp->file_out;\n\tunsigned int flags = sp->flags & ~SPLICE_F_FD_IN_FIXED;\n\tstruct file *in;\n\tlong ret = 0;\n\n\tif (issue_flags & IO_URING_F_NONBLOCK)\n\t\treturn -EAGAIN;\n\n\tif (sp->flags & SPLICE_F_FD_IN_FIXED)\n\t\tin = io_file_get_fixed(req, sp->splice_fd_in, issue_flags);\n\telse\n\t\tin = io_file_get_normal(req, sp->splice_fd_in);\n\tif (!in) {\n\t\tret = -EBADF;\n\t\tgoto done;\n\t}\n\n\tif (sp->len)\n\t\tret = do_tee(in, out, sp->len, flags);\n\n\tif (!(sp->flags & SPLICE_F_FD_IN_FIXED))\n\t\tio_put_file(in);\ndone:\n\tif (ret != sp->len)\n\t\treq_set_fail(req);\n\t__io_req_complete(req, 0, ret, 0);\n\treturn 0;\n}",
        "static void dtDeleteEntry(dtpage_t * p, int fi, struct dt_lock ** dtlock)\n{\n\tint fsi;\t\t/* free entry slot index */\n\ts8 *stbl;\n\tstruct dtslot *t;": "static void dtDeleteEntry(dtpage_t * p, int fi, struct dt_lock ** dtlock)\n{\n\tint fsi;\t\t/* free entry slot index */\n\ts8 *stbl;\n\tstruct dtslot *t;\n\tint si, freecnt;\n\tstruct dt_lock *dtlck = *dtlock;\n\tstruct lv *lv;\n\tint xsi, n;\n\n\t/* get free entry slot index */\n\tstbl = DT_GETSTBL(p);\n\tfsi = stbl[fi];\n\n\t/* open new linelock */\n\tif (dtlck->index >= dtlck->maxcnt)\n\t\tdtlck = (struct dt_lock *) txLinelock(dtlck);\n\tlv = & dtlck->lv[dtlck->index];\n\n\tlv->offset = fsi;\n\n\t/* get the head/only segment */\n\tt = &p->slot[fsi];\n\tif (p->header.flag & BT_LEAF)\n\t\tsi = ((struct ldtentry *) t)->next;\n\telse\n\t\tsi = ((struct idtentry *) t)->next;\n\tt->next = si;\n\tt->cnt = 1;\n\n\tn = freecnt = 1;\n\txsi = fsi;\n\n\t/* find the last/only segment */\n\twhile (si >= 0) {\n\t\t/* is next slot contiguous ? */\n\t\tif (si != xsi + 1) {\n\t\t\t/* close current linelock */\n\t\t\tlv->length = n;\n\t\t\tdtlck->index++;\n\n\t\t\t/* open new linelock */\n\t\t\tif (dtlck->index < dtlck->maxcnt)\n\t\t\t\tlv++;\n\t\t\telse {\n\t\t\t\tdtlck = (struct dt_lock *) txLinelock(dtlck);\n\t\t\t\tlv = & dtlck->lv[0];\n\t\t\t}\n\n\t\t\tlv->offset = si;\n\t\t\tn = 0;\n\t\t}\n\n\t\tn++;\n\t\txsi = si;\n\t\tfreecnt++;\n\n\t\tt = &p->slot[si];\n\t\tt->cnt = 1;\n\t\tsi = t->next;\n\t}\n\n\t/* close current linelock */\n\tlv->length = n;\n\tdtlck->index++;\n\n\t*dtlock = dtlck;\n\n\t/* update freelist */\n\tt->next = p->header.freelist;\n\tp->header.freelist = fsi;\n\tp->header.freecnt += freecnt;\n\n\t/* if delete from middle,\n\t * shift left the succedding entries in the stbl\n\t */\n\tsi = p->header.nextindex;\n\tif (fi < si - 1)\n\t\tmemmove(&stbl[fi], &stbl[fi + 1], si - fi - 1);\n\n\tp->header.nextindex--;\n}",
        "static int oplock_break(struct oplock_info *brk_opinfo, int req_op_level)\n{\n\tint err = 0;\n\n\t/* Need to break exclusive/batch oplock, write lease or overwrite_if */": "static int oplock_break(struct oplock_info *brk_opinfo, int req_op_level)\n{\n\tint err = 0;\n\n\t/* Need to break exclusive/batch oplock, write lease or overwrite_if */\n\tksmbd_debug(OPLOCK,\n\t\t    \"request to send oplock(level : 0x%x) break notification\\n\",\n\t\t    brk_opinfo->level);\n\n\tif (brk_opinfo->is_lease) {\n\t\tstruct lease *lease = brk_opinfo->o_lease;\n\n\t\tatomic_inc(&brk_opinfo->breaking_cnt);\n\n\t\terr = oplock_break_pending(brk_opinfo, req_op_level);\n\t\tif (err)\n\t\t\treturn err < 0 ? err : 0;\n\n\t\tif (brk_opinfo->open_trunc) {\n\t\t\t/*\n\t\t\t * Create overwrite break trigger the lease break to\n\t\t\t * none.\n\t\t\t */\n\t\t\tlease->new_state = SMB2_LEASE_NONE_LE;\n\t\t} else {\n\t\t\tif (lease->state & SMB2_LEASE_WRITE_CACHING_LE) {\n\t\t\t\tif (lease->state & SMB2_LEASE_HANDLE_CACHING_LE)\n\t\t\t\t\tlease->new_state =\n\t\t\t\t\t\tSMB2_LEASE_READ_CACHING_LE |\n\t\t\t\t\t\tSMB2_LEASE_HANDLE_CACHING_LE;\n\t\t\t\telse\n\t\t\t\t\tlease->new_state =\n\t\t\t\t\t\tSMB2_LEASE_READ_CACHING_LE;\n\t\t\t} else {\n\t\t\t\tif (lease->state & SMB2_LEASE_HANDLE_CACHING_LE)\n\t\t\t\t\tlease->new_state =\n\t\t\t\t\t\tSMB2_LEASE_READ_CACHING_LE;\n\t\t\t\telse\n\t\t\t\t\tlease->new_state = SMB2_LEASE_NONE_LE;\n\t\t\t}\n\t\t}\n\n\t\tif (lease->state & (SMB2_LEASE_WRITE_CACHING_LE |\n\t\t\t\tSMB2_LEASE_HANDLE_CACHING_LE))\n\t\t\tbrk_opinfo->op_state = OPLOCK_ACK_WAIT;\n\t\telse\n\t\t\tatomic_dec(&brk_opinfo->breaking_cnt);\n\t} else {\n\t\terr = oplock_break_pending(brk_opinfo, req_op_level);\n\t\tif (err)\n\t\t\treturn err < 0 ? err : 0;\n\n\t\tif (brk_opinfo->level == SMB2_OPLOCK_LEVEL_BATCH ||\n\t\t    brk_opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE)\n\t\t\tbrk_opinfo->op_state = OPLOCK_ACK_WAIT;\n\t}\n\n\tif (brk_opinfo->is_lease)\n\t\terr = smb2_lease_break_noti(brk_opinfo);\n\telse\n\t\terr = smb2_oplock_break_noti(brk_opinfo);\n\n\tksmbd_debug(OPLOCK, \"oplock granted = %d\\n\", brk_opinfo->level);\n\tif (brk_opinfo->op_state == OPLOCK_CLOSING)\n\t\terr = -ENOENT;\n\twake_up_oplock_break(brk_opinfo);\n\n\twait_lease_breaking(brk_opinfo);\n\n\treturn err;\n}",
        "static void nv_mac_reset(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 temp1, temp2, temp3;": "static void nv_mac_reset(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 temp1, temp2, temp3;\n\n\twritel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);\n\tpci_push(base);\n\n\t/* save registers since they will be cleared on reset */\n\ttemp1 = readl(base + NvRegMacAddrA);\n\ttemp2 = readl(base + NvRegMacAddrB);\n\ttemp3 = readl(base + NvRegTransmitPoll);\n\n\twritel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);\n\tpci_push(base);\n\tudelay(NV_MAC_RESET_DELAY);\n\twritel(0, base + NvRegMacReset);\n\tpci_push(base);\n\tudelay(NV_MAC_RESET_DELAY);\n\n\t/* restore saved registers */\n\twritel(temp1, base + NvRegMacAddrA);\n\twritel(temp2, base + NvRegMacAddrB);\n\twritel(temp3, base + NvRegTransmitPoll);\n\n\twritel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);\n\tpci_push(base);\n}",
        "static void alc5505_dsp_init(struct hda_codec *codec)\n{\n\tunsigned int val;\n\n\talc5505_dsp_halt(codec);": "static void alc5505_dsp_init(struct hda_codec *codec)\n{\n\tunsigned int val;\n\n\talc5505_dsp_halt(codec);\n\talc5505_dsp_back_from_halt(codec);\n\talc5505_coef_set(codec, 0x61b0, 0x5b14); /* PLL1 control */\n\talc5505_coef_set(codec, 0x61b0, 0x5b16);\n\talc5505_coef_set(codec, 0x61b4, 0x04132b00); /* PLL2 control */\n\talc5505_coef_set(codec, 0x61b4, 0x04132b02);\n\talc5505_coef_set(codec, 0x61b8, 0x041f3300); /* PLL3 control*/\n\talc5505_coef_set(codec, 0x61b8, 0x041f3302);\n\tsnd_hda_codec_write(codec, 0x51, 0, AC_VERB_SET_CODEC_RESET, 0); /* Function reset */\n\talc5505_coef_set(codec, 0x61b8, 0x041b3302);\n\talc5505_coef_set(codec, 0x61b8, 0x04173302);\n\talc5505_coef_set(codec, 0x61b8, 0x04163302);\n\talc5505_coef_set(codec, 0x8800, 0x348b328b); /* DRAM control */\n\talc5505_coef_set(codec, 0x8808, 0x00020022); /* DRAM control */\n\talc5505_coef_set(codec, 0x8818, 0x00000400); /* DRAM control */\n\n\tval = alc5505_coef_get(codec, 0x6200) >> 16; /* Read revision ID */\n\tif (val <= 3)\n\t\talc5505_coef_set(codec, 0x6220, 0x2002010f); /* I/O PAD Configuration */\n\telse\n\t\talc5505_coef_set(codec, 0x6220, 0x6002018f);\n\n\talc5505_coef_set(codec, 0x61ac, 0x055525f0); /**/\n\talc5505_coef_set(codec, 0x61c0, 0x12230080); /* Clock control */\n\talc5505_coef_set(codec, 0x61b4, 0x040e2b02); /* PLL2 control */\n\talc5505_coef_set(codec, 0x61bc, 0x010234f8); /* OSC Control */\n\talc5505_coef_set(codec, 0x880c, 0x00000004); /* DRAM Function control */\n\talc5505_coef_set(codec, 0x880c, 0x00000003);\n\talc5505_coef_set(codec, 0x880c, 0x00000010);\n\n#ifdef HALT_REALTEK_ALC5505\n\talc5505_dsp_halt(codec);\n#endif\n}",
        "static int cvmx_wait_tx_rx(struct octeon_hcd *usb, int fflsh_type)\n{\n\tint result;\n\tu64 address = CVMX_USBCX_GRSTCTL(usb->index);\n\tu64 done = cvmx_get_cycle() + 100 *": "static int cvmx_wait_tx_rx(struct octeon_hcd *usb, int fflsh_type)\n{\n\tint result;\n\tu64 address = CVMX_USBCX_GRSTCTL(usb->index);\n\tu64 done = cvmx_get_cycle() + 100 *\n\t\t   (u64)octeon_get_clock_rate / 1000000;\n\tunion cvmx_usbcx_grstctl c;\n\n\twhile (1) {\n\t\tc.u32 = cvmx_usb_read_csr32(usb, address);\n\t\tif (fflsh_type == 0 && c.s.txfflsh == 0) {\n\t\t\tresult = 0;\n\t\t\tbreak;\n\t\t} else if (fflsh_type == 1 && c.s.rxfflsh == 0) {\n\t\t\tresult = 0;\n\t\t\tbreak;\n\t\t} else if (cvmx_get_cycle() > done) {\n\t\t\tresult = -1;\n\t\t\tbreak;\n\t\t}\n\n\t\t__delay(100);\n\t}\n\treturn result;\n}",
        "static int io_do_iopoll(struct io_ring_ctx *ctx, bool force_nonspin)\n{\n\tstruct io_wq_work_node *pos, *start, *prev;\n\tunsigned int poll_flags = BLK_POLL_NOSLEEP;\n\tDEFINE_IO_COMP_BATCH(iob);": "static int io_do_iopoll(struct io_ring_ctx *ctx, bool force_nonspin)\n{\n\tstruct io_wq_work_node *pos, *start, *prev;\n\tunsigned int poll_flags = BLK_POLL_NOSLEEP;\n\tDEFINE_IO_COMP_BATCH(iob);\n\tint nr_events = 0;\n\n\t/*\n\t * Only spin for completions if we don't have multiple devices hanging\n\t * off our complete list.\n\t */\n\tif (ctx->poll_multi_queue || force_nonspin)\n\t\tpoll_flags |= BLK_POLL_ONESHOT;\n\n\twq_list_for_each(pos, start, &ctx->iopoll_list) {\n\t\tstruct io_kiocb *req = container_of(pos, struct io_kiocb, comp_list);\n\t\tstruct kiocb *kiocb = &req->rw.kiocb;\n\t\tint ret;\n\n\t\t/*\n\t\t * Move completed and retryable entries to our local lists.\n\t\t * If we find a request that requires polling, break out\n\t\t * and complete those lists first, if we have entries there.\n\t\t */\n\t\tif (READ_ONCE(req->iopoll_completed))\n\t\t\tbreak;\n\n\t\tret = kiocb->ki_filp->f_op->iopoll(kiocb, &iob, poll_flags);\n\t\tif (unlikely(ret < 0))\n\t\t\treturn ret;\n\t\telse if (ret)\n\t\t\tpoll_flags |= BLK_POLL_ONESHOT;\n\n\t\t/* iopoll may have completed current req */\n\t\tif (!rq_list_empty(iob.req_list) ||\n\t\t    READ_ONCE(req->iopoll_completed))\n\t\t\tbreak;\n\t}\n\n\tif (!rq_list_empty(iob.req_list))\n\t\tiob.complete(&iob);\n\telse if (!pos)\n\t\treturn 0;\n\n\tprev = start;\n\twq_list_for_each_resume(pos, prev) {\n\t\tstruct io_kiocb *req = container_of(pos, struct io_kiocb, comp_list);\n\n\t\t/* order with io_complete_rw_iopoll(), e.g. ->result updates */\n\t\tif (!smp_load_acquire(&req->iopoll_completed))\n\t\t\tbreak;\n\t\tnr_events++;\n\t\tif (unlikely(req->flags & REQ_F_CQE_SKIP))\n\t\t\tcontinue;\n\t\t__io_fill_cqe_req(req, req->cqe.res, io_put_kbuf(req, 0));\n\t}\n\n\tif (unlikely(!nr_events))\n\t\treturn 0;\n\n\tio_commit_cqring(ctx);\n\tio_cqring_ev_posted_iopoll(ctx);\n\tpos = start ? start->next : ctx->iopoll_list.first;\n\twq_list_cut(&ctx->iopoll_list, prev, start);\n\tio_free_batch_list(ctx, pos);\n\treturn nr_events;\n}",
        "static int rcu_torture_fwd_prog(void *args)\n{\n\tbool firsttime = true;\n\tlong max_cbs;\n\tint oldnice = task_nice(current);": "static int rcu_torture_fwd_prog(void *args)\n{\n\tbool firsttime = true;\n\tlong max_cbs;\n\tint oldnice = task_nice(current);\n\tunsigned long oldseq = READ_ONCE(rcu_fwd_seq);\n\tstruct rcu_fwd *rfp = args;\n\tint tested = 0;\n\tint tested_tries = 0;\n\n\tVERBOSE_TOROUT_STRING(\"rcu_torture_fwd_progress task started\");\n\trcu_bind_current_to_nocb();\n\tif (!IS_ENABLED(CONFIG_SMP) || !IS_ENABLED(CONFIG_RCU_BOOST))\n\t\tset_user_nice(current, MAX_NICE);\n\tdo {\n\t\tif (!rfp->rcu_fwd_id) {\n\t\t\tschedule_timeout_interruptible(fwd_progress_holdoff * HZ);\n\t\t\tWRITE_ONCE(rcu_fwd_emergency_stop, false);\n\t\t\tif (!firsttime) {\n\t\t\t\tmax_cbs = atomic_long_xchg(&rcu_fwd_max_cbs, 0);\n\t\t\t\tpr_alert(\"%s n_max_cbs: %ld\\n\", __func__, max_cbs);\n\t\t\t}\n\t\t\tfirsttime = false;\n\t\t\tWRITE_ONCE(rcu_fwd_seq, rcu_fwd_seq + 1);\n\t\t} else {\n\t\t\twhile (READ_ONCE(rcu_fwd_seq) == oldseq && !torture_must_stop())\n\t\t\t\tschedule_timeout_interruptible(1);\n\t\t\toldseq = READ_ONCE(rcu_fwd_seq);\n\t\t}\n\t\tpr_alert(\"%s: Starting forward-progress test %d\\n\", __func__, rfp->rcu_fwd_id);\n\t\tif (rcu_inkernel_boot_has_ended() && torture_num_online_cpus() > rfp->rcu_fwd_id)\n\t\t\trcu_torture_fwd_prog_cr(rfp);\n\t\tif ((cur_ops->stall_dur && cur_ops->stall_dur() > 0) &&\n\t\t    (!IS_ENABLED(CONFIG_TINY_RCU) ||\n\t\t     (rcu_inkernel_boot_has_ended() &&\n\t\t      torture_num_online_cpus() > rfp->rcu_fwd_id)))\n\t\t\trcu_torture_fwd_prog_nr(rfp, &tested, &tested_tries);\n\n\t\t/* Avoid slow periods, better to test when busy. */\n\t\tif (stutter_wait(\"rcu_torture_fwd_prog\"))\n\t\t\tsched_set_normal(current, oldnice);\n\t} while (!torture_must_stop());\n\t/* Short runs might not contain a valid forward-progress attempt. */\n\tif (!rfp->rcu_fwd_id) {\n\t\tWARN_ON(!tested && tested_tries >= 5);\n\t\tpr_alert(\"%s: tested %d tested_tries %d\\n\", __func__, tested, tested_tries);\n\t}\n\ttorture_kthread_stopping(\"rcu_torture_fwd_prog\");\n\treturn 0;\n}",
        "static int sendmsg_test(struct sockmap_options *opt)\n{\n\tfloat sent_Bps = 0, recvd_Bps = 0;\n\tint rx_fd, txpid, rxpid, err = 0;\n\tstruct msg_stats s = {0};": "static int sendmsg_test(struct sockmap_options *opt)\n{\n\tfloat sent_Bps = 0, recvd_Bps = 0;\n\tint rx_fd, txpid, rxpid, err = 0;\n\tstruct msg_stats s = {0};\n\tint iov_count = opt->iov_count;\n\tint iov_buf = opt->iov_length;\n\tint rx_status, tx_status;\n\tint cnt = opt->rate;\n\n\terrno = 0;\n\n\tif (opt->base)\n\t\trx_fd = p1;\n\telse\n\t\trx_fd = p2;\n\n\tif (ktls) {\n\t\t/* Redirecting into non-TLS socket which sends into a TLS\n\t\t * socket is not a valid test. So in this case lets not\n\t\t * enable kTLS but still run the test.\n\t\t */\n\t\tif (!txmsg_redir || txmsg_ingress) {\n\t\t\terr = sockmap_init_ktls(opt->verbose, rx_fd);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\t\terr = sockmap_init_ktls(opt->verbose, c1);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\trxpid = fork();\n\tif (rxpid == 0) {\n\t\tif (txmsg_pop || txmsg_start_pop)\n\t\t\tiov_buf -= (txmsg_pop - txmsg_start_pop + 1);\n\t\tif (opt->drop_expected || txmsg_ktls_skb_drop)\n\t\t\t_exit(0);\n\n\t\tif (!iov_buf) /* zero bytes sent case */\n\t\t\t_exit(0);\n\n\t\tif (opt->sendpage)\n\t\t\tiov_count = 1;\n\t\terr = msg_loop(rx_fd, iov_count, iov_buf,\n\t\t\t       cnt, &s, false, opt);\n\t\tif (opt->verbose > 1)\n\t\t\tfprintf(stderr,\n\t\t\t\t\"msg_loop_rx: iov_count %i iov_buf %i cnt %i err %i\\n\",\n\t\t\t\tiov_count, iov_buf, cnt, err);\n\t\tif (s.end.tv_sec - s.start.tv_sec) {\n\t\t\tsent_Bps = sentBps(s);\n\t\t\trecvd_Bps = recvdBps(s);\n\t\t}\n\t\tif (opt->verbose > 1)\n\t\t\tfprintf(stdout,\n\t\t\t\t\"rx_sendmsg: TX: %zuB %fB/s %fGB/s RX: %zuB %fB/s %fGB/s %s\\n\",\n\t\t\t\ts.bytes_sent, sent_Bps, sent_Bps/giga,\n\t\t\t\ts.bytes_recvd, recvd_Bps, recvd_Bps/giga,\n\t\t\t\tpeek_flag ? \"(peek_msg)\" : \"\");\n\t\tif (err && txmsg_cork)\n\t\t\terr = 0;\n\t\texit(err ? 1 : 0);\n\t} else if (rxpid == -1) {\n\t\tperror(\"msg_loop_rx\");\n\t\treturn errno;\n\t}\n\n\ttxpid = fork();\n\tif (txpid == 0) {\n\t\tif (opt->sendpage)\n\t\t\terr = msg_loop_sendpage(c1, iov_buf, cnt, &s, opt);\n\t\telse\n\t\t\terr = msg_loop(c1, iov_count, iov_buf,\n\t\t\t\t       cnt, &s, true, opt);\n\n\t\tif (err)\n\t\t\tfprintf(stderr,\n\t\t\t\t\"msg_loop_tx: iov_count %i iov_buf %i cnt %i err %i\\n\",\n\t\t\t\tiov_count, iov_buf, cnt, err);\n\t\tif (s.end.tv_sec - s.start.tv_sec) {\n\t\t\tsent_Bps = sentBps(s);\n\t\t\trecvd_Bps = recvdBps(s);\n\t\t}\n\t\tif (opt->verbose > 1)\n\t\t\tfprintf(stdout,\n\t\t\t\t\"tx_sendmsg: TX: %zuB %fB/s %f GB/s RX: %zuB %fB/s %fGB/s\\n\",\n\t\t\t\ts.bytes_sent, sent_Bps, sent_Bps/giga,\n\t\t\t\ts.bytes_recvd, recvd_Bps, recvd_Bps/giga);\n\t\texit(err ? 1 : 0);\n\t} else if (txpid == -1) {\n\t\tperror(\"msg_loop_tx\");\n\t\treturn errno;\n\t}\n\n\tassert(waitpid(rxpid, &rx_status, 0) == rxpid);\n\tassert(waitpid(txpid, &tx_status, 0) == txpid);\n\tif (WIFEXITED(rx_status)) {\n\t\terr = WEXITSTATUS(rx_status);\n\t\tif (err) {\n\t\t\tfprintf(stderr, \"rx thread exited with err %d.\\n\", err);\n\t\t\tgoto out;\n\t\t}\n\t}\n\tif (WIFEXITED(tx_status)) {\n\t\terr = WEXITSTATUS(tx_status);\n\t\tif (err)\n\t\t\tfprintf(stderr, \"tx thread exited with err %d.\\n\", err);\n\t}\nout:\n\treturn err;\n}",
        "static int add_kfunc_call(struct bpf_verifier_env *env, u32 func_id, s16 offset)\n{\n\tconst struct btf_type *func, *func_proto;\n\tstruct bpf_kfunc_btf_tab *btf_tab;\n\tstruct bpf_kfunc_desc_tab *tab;": "static int add_kfunc_call(struct bpf_verifier_env *env, u32 func_id, s16 offset)\n{\n\tconst struct btf_type *func, *func_proto;\n\tstruct bpf_kfunc_btf_tab *btf_tab;\n\tstruct bpf_kfunc_desc_tab *tab;\n\tstruct bpf_prog_aux *prog_aux;\n\tstruct bpf_kfunc_desc *desc;\n\tconst char *func_name;\n\tstruct btf *desc_btf;\n\tunsigned long call_imm;\n\tunsigned long addr;\n\tint err;\n\n\tprog_aux = env->prog->aux;\n\ttab = prog_aux->kfunc_tab;\n\tbtf_tab = prog_aux->kfunc_btf_tab;\n\tif (!tab) {\n\t\tif (!btf_vmlinux) {\n\t\t\tverbose(env, \"calling kernel function is not supported without CONFIG_DEBUG_INFO_BTF\\n\");\n\t\t\treturn -ENOTSUPP;\n\t\t}\n\n\t\tif (!env->prog->jit_requested) {\n\t\t\tverbose(env, \"JIT is required for calling kernel function\\n\");\n\t\t\treturn -ENOTSUPP;\n\t\t}\n\n\t\tif (!bpf_jit_supports_kfunc_call()) {\n\t\t\tverbose(env, \"JIT does not support calling kernel function\\n\");\n\t\t\treturn -ENOTSUPP;\n\t\t}\n\n\t\tif (!env->prog->gpl_compatible) {\n\t\t\tverbose(env, \"cannot call kernel function from non-GPL compatible program\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\ttab = kzalloc(sizeof(*tab), GFP_KERNEL);\n\t\tif (!tab)\n\t\t\treturn -ENOMEM;\n\t\tprog_aux->kfunc_tab = tab;\n\t}\n\n\t/* func_id == 0 is always invalid, but instead of returning an error, be\n\t * conservative and wait until the code elimination pass before returning\n\t * error, so that invalid calls that get pruned out can be in BPF programs\n\t * loaded from userspace.  It is also required that offset be untouched\n\t * for such calls.\n\t */\n\tif (!func_id && !offset)\n\t\treturn 0;\n\n\tif (!btf_tab && offset) {\n\t\tbtf_tab = kzalloc(sizeof(*btf_tab), GFP_KERNEL);\n\t\tif (!btf_tab)\n\t\t\treturn -ENOMEM;\n\t\tprog_aux->kfunc_btf_tab = btf_tab;\n\t}\n\n\tdesc_btf = find_kfunc_desc_btf(env, offset);\n\tif (IS_ERR(desc_btf)) {\n\t\tverbose(env, \"failed to find BTF for kernel function\\n\");\n\t\treturn PTR_ERR(desc_btf);\n\t}\n\n\tif (find_kfunc_desc(env->prog, func_id, offset))\n\t\treturn 0;\n\n\tif (tab->nr_descs == MAX_KFUNC_DESCS) {\n\t\tverbose(env, \"too many different kernel function calls\\n\");\n\t\treturn -E2BIG;\n\t}\n\n\tfunc = btf_type_by_id(desc_btf, func_id);\n\tif (!func || !btf_type_is_func(func)) {\n\t\tverbose(env, \"kernel btf_id %u is not a function\\n\",\n\t\t\tfunc_id);\n\t\treturn -EINVAL;\n\t}\n\tfunc_proto = btf_type_by_id(desc_btf, func->type);\n\tif (!func_proto || !btf_type_is_func_proto(func_proto)) {\n\t\tverbose(env, \"kernel function btf_id %u does not have a valid func_proto\\n\",\n\t\t\tfunc_id);\n\t\treturn -EINVAL;\n\t}\n\n\tfunc_name = btf_name_by_offset(desc_btf, func->name_off);\n\taddr = kallsyms_lookup_name(func_name);\n\tif (!addr) {\n\t\tverbose(env, \"cannot find address for kernel function %s\\n\",\n\t\t\tfunc_name);\n\t\treturn -EINVAL;\n\t}\n\n\tcall_imm = BPF_CALL_IMM(addr);\n\t/* Check whether or not the relative offset overflows desc->imm */\n\tif ((unsigned long)(s32)call_imm != call_imm) {\n\t\tverbose(env, \"address of kernel function %s is out of range\\n\",\n\t\t\tfunc_name);\n\t\treturn -EINVAL;\n\t}\n\n\tdesc = &tab->descs[tab->nr_descs++];\n\tdesc->func_id = func_id;\n\tdesc->imm = call_imm;\n\tdesc->offset = offset;\n\terr = btf_distill_func_proto(&env->log, desc_btf,\n\t\t\t\t     func_proto, func_name,\n\t\t\t\t     &desc->func_model);\n\tif (!err)\n\t\tsort(tab->descs, tab->nr_descs, sizeof(tab->descs[0]),\n\t\t     kfunc_desc_cmp_by_id_off, NULL);\n\treturn err;\n}",
        "static void at91_calc_twi_clock(struct at91_twi_dev *dev)\n{\n\tint ckdiv, cdiv, div, hold = 0, filter_width = 0;\n\tstruct at91_twi_pdata *pdata = dev->pdata;\n\tint offset = pdata->clk_offset;": "static void at91_calc_twi_clock(struct at91_twi_dev *dev)\n{\n\tint ckdiv, cdiv, div, hold = 0, filter_width = 0;\n\tstruct at91_twi_pdata *pdata = dev->pdata;\n\tint offset = pdata->clk_offset;\n\tint max_ckdiv = pdata->clk_max_div;\n\tstruct i2c_timings timings, *t = &timings;\n\n\ti2c_parse_fw_timings(dev->dev, t, true);\n\n\tdiv = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),\n\t\t\t\t       2 * t->bus_freq_hz) - offset);\n\tckdiv = fls(div >> 8);\n\tcdiv = div >> ckdiv;\n\n\tif (ckdiv > max_ckdiv) {\n\t\tdev_warn(dev->dev, \"%d exceeds ckdiv max value which is %d.\\n\",\n\t\t\t ckdiv, max_ckdiv);\n\t\tckdiv = max_ckdiv;\n\t\tcdiv = 255;\n\t}\n\n\tif (pdata->has_hold_field) {\n\t\t/*\n\t\t * hold time = HOLD + 3 x T_peripheral_clock\n\t\t * Use clk rate in kHz to prevent overflows when computing\n\t\t * hold.\n\t\t */\n\t\thold = DIV_ROUND_UP(t->sda_hold_ns\n\t\t\t\t    * (clk_get_rate(dev->clk) / 1000), 1000000);\n\t\thold -= 3;\n\t\tif (hold < 0)\n\t\t\thold = 0;\n\t\tif (hold > AT91_TWI_CWGR_HOLD_MAX) {\n\t\t\tdev_warn(dev->dev,\n\t\t\t\t \"HOLD field set to its maximum value (%d instead of %d)\\n\",\n\t\t\t\t AT91_TWI_CWGR_HOLD_MAX, hold);\n\t\t\thold = AT91_TWI_CWGR_HOLD_MAX;\n\t\t}\n\t}\n\n\tif (pdata->has_adv_dig_filtr) {\n\t\t/*\n\t\t * filter width = 0 to AT91_TWI_FILTR_THRES_MAX\n\t\t * peripheral clocks\n\t\t */\n\t\tfilter_width = DIV_ROUND_UP(t->digital_filter_width_ns\n\t\t\t\t* (clk_get_rate(dev->clk) / 1000), 1000000);\n\t\tif (filter_width > AT91_TWI_FILTR_THRES_MAX) {\n\t\t\tdev_warn(dev->dev,\n\t\t\t\t\"Filter threshold set to its maximum value (%d instead of %d)\\n\",\n\t\t\t\tAT91_TWI_FILTR_THRES_MAX, filter_width);\n\t\t\tfilter_width = AT91_TWI_FILTR_THRES_MAX;\n\t\t}\n\t}\n\n\tdev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv\n\t\t\t    | AT91_TWI_CWGR_HOLD(hold);\n\n\tdev->filter_width = filter_width;\n\n\tdev_dbg(dev->dev, \"cdiv %d ckdiv %d hold %d (%d ns), filter_width %d (%d ns)\\n\",\n\t\tcdiv, ckdiv, hold, t->sda_hold_ns, filter_width,\n\t\tt->digital_filter_width_ns);\n}",
        "static void test_bpf_mod_race_config(const struct test_config *config)\n{\n\tvoid *fault_addr, *skel_fail;\n\tstruct bpf_mod_race *skel;\n\tstruct uffd_msg uffd_msg;": "static void test_bpf_mod_race_config(const struct test_config *config)\n{\n\tvoid *fault_addr, *skel_fail;\n\tstruct bpf_mod_race *skel;\n\tstruct uffd_msg uffd_msg;\n\tpthread_t load_mod_thrd;\n\t_Atomic int *blockingp;\n\tint uffd, ret;\n\n\tfault_addr = mmap(0, 4096, PROT_READ, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);\n\tif (!ASSERT_NEQ(fault_addr, MAP_FAILED, \"mmap for uffd registration\"))\n\t\treturn;\n\n\tif (!ASSERT_OK(sys_delete_module(\"bpf_testmod\", 0), \"unload bpf_testmod\"))\n\t\tgoto end_mmap;\n\n\tskel = bpf_mod_race__open();\n\tif (!ASSERT_OK_PTR(skel, \"bpf_mod_kfunc_race__open\"))\n\t\tgoto end_module;\n\n\tskel->rodata->bpf_mod_race_config.tgid = getpid();\n\tskel->rodata->bpf_mod_race_config.inject_error = -4242;\n\tskel->rodata->bpf_mod_race_config.fault_addr = fault_addr;\n\tif (!ASSERT_OK(bpf_mod_race__load(skel), \"bpf_mod___load\"))\n\t\tgoto end_destroy;\n\tblockingp = (_Atomic int *)&skel->bss->bpf_blocking;\n\n\tif (!ASSERT_OK(bpf_mod_race__attach(skel), \"bpf_mod_kfunc_race__attach\"))\n\t\tgoto end_destroy;\n\n\tuffd = test_setup_uffd(fault_addr);\n\tif (!ASSERT_GE(uffd, 0, \"userfaultfd open + register address\"))\n\t\tgoto end_destroy;\n\n\tif (!ASSERT_OK(pthread_create(&load_mod_thrd, NULL, load_module_thread, NULL),\n\t\t       \"load module thread\"))\n\t\tgoto end_uffd;\n\n\t/* Now, we either fail loading module, or block in bpf prog, spin to find out */\n\twhile (!atomic_load(&state) && !atomic_load(blockingp))\n\t\t;\n\tif (!ASSERT_EQ(state, _TS_INVALID, \"module load should block\"))\n\t\tgoto end_join;\n\tif (!ASSERT_EQ(*blockingp, 1, \"module load blocked\")) {\n\t\tpthread_kill(load_mod_thrd, SIGKILL);\n\t\tgoto end_uffd;\n\t}\n\n\t/* We might have set bpf_blocking to 1, but may have not blocked in\n\t * bpf_copy_from_user. Read userfaultfd descriptor to verify that.\n\t */\n\tif (!ASSERT_EQ(read(uffd, &uffd_msg, sizeof(uffd_msg)), sizeof(uffd_msg),\n\t\t       \"read uffd block event\"))\n\t\tgoto end_join;\n\tif (!ASSERT_EQ(uffd_msg.event, UFFD_EVENT_PAGEFAULT, \"read uffd event is pagefault\"))\n\t\tgoto end_join;\n\n\t/* We know that load_mod_thrd is blocked in the fmod_ret program, the\n\t * module state is still MODULE_STATE_COMING because mod->init hasn't\n\t * returned. This is the time we try to load a program calling kfunc and\n\t * check if we get ENXIO from verifier.\n\t */\n\tskel_fail = config->bpf_open_and_load();\n\tret = errno;\n\tif (!ASSERT_EQ(skel_fail, NULL, config->str_open)) {\n\t\t/* Close uffd to unblock load_mod_thrd */\n\t\tclose(uffd);\n\t\tuffd = -1;\n\t\twhile (atomic_load(blockingp) != 2)\n\t\t\t;\n\t\tASSERT_OK(kern_sync_rcu(), \"kern_sync_rcu\");\n\t\tconfig->bpf_destroy(skel_fail);\n\t\tgoto end_join;\n\n\t}\n\tASSERT_EQ(ret, ENXIO, \"verifier returns ENXIO\");\n\tASSERT_EQ(skel->data->res_try_get_module, false, \"btf_try_get_module == false\");\n\n\tclose(uffd);\n\tuffd = -1;\nend_join:\n\tpthread_join(load_mod_thrd, NULL);\n\tif (uffd < 0)\n\t\tASSERT_EQ(atomic_load(&state), TS_MODULE_LOAD_FAIL, \"load_mod_thrd success\");\nend_uffd:\n\tif (uffd >= 0)\n\t\tclose(uffd);\nend_destroy:\n\tbpf_mod_race__destroy(skel);\n\tASSERT_OK(kern_sync_rcu(), \"kern_sync_rcu\");\nend_module:\n\tsys_delete_module(\"bpf_testmod\", 0);\n\tASSERT_OK(load_module(\"bpf_testmod.ko\"), \"restore bpf_testmod\");\nend_mmap:\n\tmunmap(fault_addr, 4096);\n\tatomic_store(&state, _TS_INVALID);\n}",
        "static void kgdbfdc_push_one(void)\n{\n\tconst char *bufs[1] = { kgdbfdc_wbuf };\n\tstruct fdc_word word;\n\tvoid __iomem *regs;": "static void kgdbfdc_push_one(void)\n{\n\tconst char *bufs[1] = { kgdbfdc_wbuf };\n\tstruct fdc_word word;\n\tvoid __iomem *regs;\n\tunsigned int i;\n\n\t/* Construct a word from any data in buffer */\n\tword = mips_ejtag_fdc_encode(bufs, &kgdbfdc_wbuflen, 1);\n\t/* Relocate any remaining data to beginnning of buffer */\n\tkgdbfdc_wbuflen -= word.bytes;\n\tfor (i = 0; i < kgdbfdc_wbuflen; ++i)\n\t\tkgdbfdc_wbuf[i] = kgdbfdc_wbuf[i + word.bytes];\n\n\tregs = kgdbfdc_setup();\n\tif (IS_ERR(regs))\n\t\treturn;\n\n\t/* Busy wait until there's space in fifo */\n\twhile (__raw_readl(regs + REG_FDSTAT) & REG_FDSTAT_TXF)\n\t\t;\n\t__raw_writel(word.word,\n\t\t     regs + REG_FDTX(CONFIG_MIPS_EJTAG_FDC_KGDB_CHAN));\n}",
        "static void rtl_hw_start_8402(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8402[] = {\n\t\t{ 0x19,\t0xffff, 0xff64 },\n\t\t{ 0x1e,\t0, 0x4000 }": "static void rtl_hw_start_8402(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8402[] = {\n\t\t{ 0x19,\t0xffff, 0xff64 },\n\t\t{ 0x1e,\t0, 0x4000 }\n\t};\n\n\trtl_set_def_aspm_entry_latency(tp);\n\n\t/* Force LAN exit from ASPM if Rx/Tx are not idle */\n\tRTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);\n\n\tRTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);\n\n\trtl_ephy_init(tp, e_info_8402);\n\n\trtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);\n\trtl_reset_packet_filter(tp);\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);\n\trtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);\n\trtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);\n\n\t/* disable EEE */\n\trtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);\n\n\trtl_pcie_state_l2l3_disable(tp);\n}",
        "static unsigned long *ms_putsec(int drive, unsigned long *raw, int cnt)\n{\n\tstatic struct dos_header hdr={0,0,0,2,0,\n\t  {78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78}};\n\tint i;": "static unsigned long *ms_putsec(int drive, unsigned long *raw, int cnt)\n{\n\tstatic struct dos_header hdr={0,0,0,2,0,\n\t  {78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78,78}};\n\tint i;\n\tstatic ushort crc[2]={0,0x4e4e};\n\n\tdrive&=3;\n/* id gap 1 */\n/* the MFM word before is always 9254 */\n\tfor(i=0;i<6;i++)\n\t\t*raw++=0xaaaaaaaa;\n/* 3 sync + 1 headermark */\n\t*raw++=0x44894489;\n\t*raw++=0x44895554;\n\n/* fill in the variable parts of the header */\n\thdr.track=unit[drive].track/unit[drive].type->heads;\n\thdr.side=unit[drive].track%unit[drive].type->heads;\n\thdr.sec=cnt+1;\n\thdr.crc=dos_hdr_crc(&hdr);\n\n/* header (without \"magic\") and id gap 2*/\n\tdos_encode_block((ushort *)raw,(unsigned char *) &hdr.track,28);\n\traw+=14;\n\n/*id gap 3 */\n\tfor(i=0;i<6;i++)\n\t\t*raw++=0xaaaaaaaa;\n\n/* 3 syncs and 1 datamark */\n\t*raw++=0x44894489;\n\t*raw++=0x44895545;\n\n/* data */\n\tdos_encode_block((ushort *)raw,\n\t\t\t (unsigned char *)unit[drive].trackbuf+cnt*512,512);\n\traw+=256;\n\n/*data crc + jd's special gap (long words :-/) */\n\tcrc[0]=dos_data_crc(unit[drive].trackbuf+cnt*512);\n\tdos_encode_block((ushort *) raw,(unsigned char *)crc,4);\n\traw+=2;\n\n/* data gap */\n\tfor(i=0;i<38;i++)\n\t\t*raw++=0x92549254;\n\n\treturn raw; /* wrote 652 MFM words */\n}",
        "static void revoke_at_prepare_read_data_cont(struct ceph_connection *con)\n{\n\tint recved, resid;  /* current piece of data */\n\tint remaining;\n": "static void revoke_at_prepare_read_data_cont(struct ceph_connection *con)\n{\n\tint recved, resid;  /* current piece of data */\n\tint remaining;\n\n\tWARN_ON(con_secure(con));\n\tWARN_ON(!data_len(con->in_msg));\n\tWARN_ON(!iov_iter_is_bvec(&con->v2.in_iter));\n\tresid = iov_iter_count(&con->v2.in_iter);\n\tWARN_ON(!resid || resid > con->v2.in_bvec.bv_len);\n\trecved = con->v2.in_bvec.bv_len - resid;\n\tdout(\"%s con %p recved %d resid %d\\n\", __func__, con, recved, resid);\n\n\tif (recved)\n\t\tceph_msg_data_advance(&con->v2.in_cursor, recved);\n\tWARN_ON(resid > con->v2.in_cursor.total_resid);\n\n\tremaining = CEPH_EPILOGUE_PLAIN_LEN;\n\tdout(\"%s con %p total_resid %zu remaining %d\\n\", __func__, con,\n\t     con->v2.in_cursor.total_resid, remaining);\n\tcon->v2.in_iter.count -= resid;\n\tset_in_skip(con, con->v2.in_cursor.total_resid + remaining);\n\tcon->v2.in_state = IN_S_FINISH_SKIP;\n}",
        "static void *__bpf_map_area_alloc(u64 size, int numa_node, bool mmapable)\n{\n\t/* We really just want to fail instead of triggering OOM killer\n\t * under memory pressure, therefore we set __GFP_NORETRY to kmalloc,\n\t * which is used for lower order allocation requests.": "static void *__bpf_map_area_alloc(u64 size, int numa_node, bool mmapable)\n{\n\t/* We really just want to fail instead of triggering OOM killer\n\t * under memory pressure, therefore we set __GFP_NORETRY to kmalloc,\n\t * which is used for lower order allocation requests.\n\t *\n\t * It has been observed that higher order allocation requests done by\n\t * vmalloc with __GFP_NORETRY being set might fail due to not trying\n\t * to reclaim memory from the page cache, thus we set\n\t * __GFP_RETRY_MAYFAIL to avoid such situations.\n\t */\n\n\tconst gfp_t gfp = __GFP_NOWARN | __GFP_ZERO | __GFP_ACCOUNT;\n\tunsigned int flags = 0;\n\tunsigned long align = 1;\n\tvoid *area;\n\n\tif (size >= SIZE_MAX)\n\t\treturn NULL;\n\n\t/* kmalloc()'ed memory can't be mmap()'ed */\n\tif (mmapable) {\n\t\tBUG_ON(!PAGE_ALIGNED(size));\n\t\talign = SHMLBA;\n\t\tflags = VM_USERMAP;\n\t} else if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER)) {\n\t\tarea = kmalloc_node(size, gfp | GFP_USER | __GFP_NORETRY,\n\t\t\t\t    numa_node);\n\t\tif (area != NULL)\n\t\t\treturn area;\n\t}\n\n\treturn __vmalloc_node_range(size, align, VMALLOC_START, VMALLOC_END,\n\t\t\tgfp | GFP_KERNEL | __GFP_RETRY_MAYFAIL, PAGE_KERNEL,\n\t\t\tflags, numa_node, __builtin_return_address(0));\n}",
        "static void wcd_correct_swch_plug(struct work_struct *work)\n{\n\tstruct wcd_mbhc *mbhc;\n\tstruct snd_soc_component *component;\n\tenum wcd_mbhc_plug_type plug_type = MBHC_PLUG_TYPE_INVALID;": "static void wcd_correct_swch_plug(struct work_struct *work)\n{\n\tstruct wcd_mbhc *mbhc;\n\tstruct snd_soc_component *component;\n\tenum wcd_mbhc_plug_type plug_type = MBHC_PLUG_TYPE_INVALID;\n\tunsigned long timeout;\n\tint pt_gnd_mic_swap_cnt = 0;\n\tint output_mv, cross_conn, hs_threshold, try = 0, micbias_mv;\n\tbool is_spl_hs = false;\n\tbool is_pa_on;\n\tint ret;\n\n\tmbhc = container_of(work, struct wcd_mbhc, correct_plug_swch);\n\tcomponent = mbhc->component;\n\n\tret = pm_runtime_get_sync(component->dev);\n\tif (ret < 0 && ret != -EACCES) {\n\t\tdev_err_ratelimited(component->dev,\n\t\t\t\t    \"pm_runtime_get_sync failed in %s, ret %d\\n\",\n\t\t\t\t    __func__, ret);\n\t\tpm_runtime_put_noidle(component->dev);\n\t\treturn;\n\t}\n\tmicbias_mv = wcd_mbhc_get_micbias(mbhc);\n\ths_threshold = wcd_mbhc_adc_get_hs_thres(mbhc);\n\n\t/* Mask ADC COMPLETE interrupt */\n\tdisable_irq_nosync(mbhc->intr_ids->mbhc_hs_ins_intr);\n\n\t/* Check for cross connection */\n\tdo {\n\t\tcross_conn = wcd_check_cross_conn(mbhc);\n\t\ttry++;\n\t} while (try < GND_MIC_SWAP_THRESHOLD);\n\n\tif (cross_conn > 0) {\n\t\tplug_type = MBHC_PLUG_TYPE_GND_MIC_SWAP;\n\t\tdev_err(mbhc->dev, \"cross connection found, Plug type %d\\n\",\n\t\t\tplug_type);\n\t\tgoto correct_plug_type;\n\t}\n\n\t/* Find plug type */\n\toutput_mv = wcd_measure_adc_continuous(mbhc);\n\tplug_type = wcd_mbhc_get_plug_from_adc(mbhc, output_mv);\n\n\t/*\n\t * Report plug type if it is either headset or headphone\n\t * else start the 3 sec loop\n\t */\n\tswitch (plug_type) {\n\tcase MBHC_PLUG_TYPE_HEADPHONE:\n\t\twcd_mbhc_find_plug_and_report(mbhc, plug_type);\n\t\tbreak;\n\tcase MBHC_PLUG_TYPE_HEADSET:\n\t\twcd_mbhc_find_plug_and_report(mbhc, plug_type);\n\t\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 0);\n\t\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);\n\t\twcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 1);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\ncorrect_plug_type:\n\n\t/* Disable BCS slow insertion detection */\n\twcd_mbhc_bcs_enable(mbhc, plug_type, false);\n\n\ttimeout = jiffies + msecs_to_jiffies(HS_DETECT_PLUG_TIME_MS);\n\n\twhile (!time_after(jiffies, timeout)) {\n\t\tif (mbhc->hs_detect_work_stop) {\n\t\t\twcd_micbias_disable(mbhc);\n\t\t\tgoto exit;\n\t\t}\n\n\t\tmsleep(180);\n\t\t/*\n\t\t * Use ADC single mode to minimize the chance of missing out\n\t\t * btn press/release for HEADSET type during correct work.\n\t\t */\n\t\toutput_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);\n\t\tplug_type = wcd_mbhc_get_plug_from_adc(mbhc, output_mv);\n\t\tis_pa_on = wcd_mbhc_read_field(mbhc, WCD_MBHC_HPH_PA_EN);\n\n\t\tif (output_mv > hs_threshold && !is_spl_hs) {\n\t\t\tis_spl_hs = wcd_mbhc_check_for_spl_headset(mbhc);\n\t\t\toutput_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);\n\n\t\t\tif (is_spl_hs) {\n\t\t\t\ths_threshold *= wcd_mbhc_get_micbias(mbhc);\n\t\t\t\ths_threshold /= micbias_mv;\n\t\t\t}\n\t\t}\n\n\t\tif ((output_mv <= hs_threshold) && !is_pa_on) {\n\t\t\t/* Check for cross connection*/\n\t\t\tcross_conn = wcd_check_cross_conn(mbhc);\n\t\t\tif (cross_conn > 0) { /* cross-connection */\n\t\t\t\tpt_gnd_mic_swap_cnt++;\n\t\t\t\tif (pt_gnd_mic_swap_cnt < GND_MIC_SWAP_THRESHOLD)\n\t\t\t\t\tcontinue;\n\t\t\t\telse\n\t\t\t\t\tplug_type = MBHC_PLUG_TYPE_GND_MIC_SWAP;\n\t\t\t} else if (!cross_conn) { /* no cross connection */\n\t\t\t\tpt_gnd_mic_swap_cnt = 0;\n\t\t\t\tplug_type = wcd_mbhc_get_plug_from_adc(mbhc, output_mv);\n\t\t\t\tcontinue;\n\t\t\t} else if (cross_conn < 0) /* Error */\n\t\t\t\tcontinue;\n\n\t\t\tif (pt_gnd_mic_swap_cnt == GND_MIC_SWAP_THRESHOLD) {\n\t\t\t\t/* US_EU gpio present, flip switch */\n\t\t\t\tif (mbhc->cfg->swap_gnd_mic) {\n\t\t\t\t\tif (mbhc->cfg->swap_gnd_mic(component, true))\n\t\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* cable is extension cable */\n\t\tif (output_mv > hs_threshold || mbhc->force_linein)\n\t\t\tplug_type = MBHC_PLUG_TYPE_HIGH_HPH;\n\t}\n\n\twcd_mbhc_bcs_enable(mbhc, plug_type, true);\n\n\tif (plug_type == MBHC_PLUG_TYPE_HIGH_HPH) {\n\t\tif (is_spl_hs)\n\t\t\tplug_type = MBHC_PLUG_TYPE_HEADSET;\n\t\telse\n\t\t\twcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_ISRC_EN, 1);\n\t}\n\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 0);\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);\n\twcd_mbhc_find_plug_and_report(mbhc, plug_type);\n\n\t/*\n\t * Set DETECTION_DONE bit for HEADSET\n\t * so that btn press/release interrupt can be generated.\n\t * For other plug type, clear the bit.\n\t */\n\tif (plug_type == MBHC_PLUG_TYPE_HEADSET)\n\t\twcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 1);\n\telse\n\t\twcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 0);\n\n\tif (mbhc->mbhc_cb->mbhc_micbias_control)\n\t\twcd_mbhc_adc_update_fsm_source(mbhc, plug_type);\n\nexit:\n\tif (mbhc->mbhc_cb->mbhc_micbias_control/* &&  !mbhc->micbias_enable*/)\n\t\tmbhc->mbhc_cb->mbhc_micbias_control(component, MIC_BIAS_2, MICB_DISABLE);\n\n\t/*\n\t * If plug type is corrected from special headset to headphone,\n\t * clear the micbias enable flag, set micbias back to 1.8V and\n\t * disable micbias.\n\t */\n\tif (plug_type == MBHC_PLUG_TYPE_HEADPHONE) {\n\t\twcd_micbias_disable(mbhc);\n\t\t/*\n\t\t * Enable ADC COMPLETE interrupt for HEADPHONE.\n\t\t * Btn release may happen after the correct work, ADC COMPLETE\n\t\t * interrupt needs to be captured to correct plug type.\n\t\t */\n\t\tenable_irq(mbhc->intr_ids->mbhc_hs_ins_intr);\n\t}\n\n\tif (mbhc->mbhc_cb->hph_pull_down_ctrl)\n\t\tmbhc->mbhc_cb->hph_pull_down_ctrl(component, true);\n\n\tpm_runtime_mark_last_busy(component->dev);\n\tpm_runtime_put_autosuspend(component->dev);\n}",
        "static void alc225_init(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\thda_nid_t hp_pin = alc_get_hp_pin(spec);\n\tbool hp1_pin_sense, hp2_pin_sense;": "static void alc225_init(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\thda_nid_t hp_pin = alc_get_hp_pin(spec);\n\tbool hp1_pin_sense, hp2_pin_sense;\n\n\tif (spec->codec_variant != ALC269_TYPE_ALC287 &&\n\t\tspec->codec_variant != ALC269_TYPE_ALC245)\n\t\t/* required only at boot or S3 and S4 resume time */\n\t\tif (!spec->done_hp_init ||\n\t\t\tis_s3_resume(codec) ||\n\t\t\tis_s4_resume(codec)) {\n\t\t\talc285_hp_init(codec);\n\t\t\tspec->done_hp_init = true;\n\t\t}\n\n\tif (!hp_pin)\n\t\thp_pin = 0x21;\n\tmsleep(30);\n\n\thp1_pin_sense = snd_hda_jack_detect(codec, hp_pin);\n\thp2_pin_sense = snd_hda_jack_detect(codec, 0x16);\n\n\tif (hp1_pin_sense || hp2_pin_sense)\n\t\tmsleep(2);\n\n\talc_update_coefex_idx(codec, 0x57, 0x04, 0x0007, 0x1); /* Low power */\n\tif (spec->ultra_low_power) {\n\t\talc_update_coef_idx(codec, 0x08, 0x0f << 2, 3<<2);\n\t\talc_update_coef_idx(codec, 0x0e, 7<<6, 7<<6);\n\t\talc_update_coef_idx(codec, 0x33, 1<<11, 0);\n\t\tmsleep(30);\n\t}\n\n\tif (hp1_pin_sense || spec->ultra_low_power)\n\t\tsnd_hda_codec_write(codec, hp_pin, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);\n\tif (hp2_pin_sense)\n\t\tsnd_hda_codec_write(codec, 0x16, 0,\n\t\t\t    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE);\n\n\tif (hp1_pin_sense || hp2_pin_sense || spec->ultra_low_power)\n\t\tmsleep(85);\n\n\tif (hp1_pin_sense || spec->ultra_low_power)\n\t\tsnd_hda_codec_write(codec, hp_pin, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);\n\tif (hp2_pin_sense)\n\t\tsnd_hda_codec_write(codec, 0x16, 0,\n\t\t\t    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);\n\n\tif (hp1_pin_sense || hp2_pin_sense || spec->ultra_low_power)\n\t\tmsleep(100);\n\n\talc_update_coef_idx(codec, 0x4a, 3 << 10, 0);\n\talc_update_coefex_idx(codec, 0x57, 0x04, 0x0007, 0x4); /* Hight power */\n}",
        "static void tipc_bcbase_select_primary(struct net *net)\n{\n\tstruct tipc_bc_base *bb = tipc_bc_base(net);\n\tint all_dests =  tipc_link_bc_peers(bb->link);\n\tint max_win = tipc_link_max_win(bb->link);": "static void tipc_bcbase_select_primary(struct net *net)\n{\n\tstruct tipc_bc_base *bb = tipc_bc_base(net);\n\tint all_dests =  tipc_link_bc_peers(bb->link);\n\tint max_win = tipc_link_max_win(bb->link);\n\tint min_win = tipc_link_min_win(bb->link);\n\tint i, mtu, prim;\n\n\tbb->primary_bearer = INVALID_BEARER_ID;\n\tbb->bcast_support = true;\n\n\tif (!all_dests)\n\t\treturn;\n\n\tfor (i = 0; i < MAX_BEARERS; i++) {\n\t\tif (!bb->dests[i])\n\t\t\tcontinue;\n\n\t\tmtu = tipc_bearer_mtu(net, i);\n\t\tif (mtu < tipc_link_mtu(bb->link)) {\n\t\t\ttipc_link_set_mtu(bb->link, mtu);\n\t\t\ttipc_link_set_queue_limits(bb->link,\n\t\t\t\t\t\t   min_win,\n\t\t\t\t\t\t   max_win);\n\t\t}\n\t\tbb->bcast_support &= tipc_bearer_bcast_support(net, i);\n\t\tif (bb->dests[i] < all_dests)\n\t\t\tcontinue;\n\n\t\tbb->primary_bearer = i;\n\n\t\t/* Reduce risk that all nodes select same primary */\n\t\tif ((i ^ tipc_own_addr(net)) & 1)\n\t\t\tbreak;\n\t}\n\tprim = bb->primary_bearer;\n\tif (prim != INVALID_BEARER_ID)\n\t\tbb->bcast_support = tipc_bearer_bcast_support(net, prim);\n}",
        "static int ftrace_update_code(struct module *mod, struct ftrace_page *new_pgs)\n{\n\tbool init_nop = ftrace_need_init_nop();\n\tstruct ftrace_page *pg;\n\tstruct dyn_ftrace *p;": "static int ftrace_update_code(struct module *mod, struct ftrace_page *new_pgs)\n{\n\tbool init_nop = ftrace_need_init_nop();\n\tstruct ftrace_page *pg;\n\tstruct dyn_ftrace *p;\n\tu64 start, stop;\n\tunsigned long update_cnt = 0;\n\tunsigned long rec_flags = 0;\n\tint i;\n\n\tstart = ftrace_now(raw_smp_processor_id());\n\n\t/*\n\t * When a module is loaded, this function is called to convert\n\t * the calls to mcount in its text to nops, and also to create\n\t * an entry in the ftrace data. Now, if ftrace is activated\n\t * after this call, but before the module sets its text to\n\t * read-only, the modification of enabling ftrace can fail if\n\t * the read-only is done while ftrace is converting the calls.\n\t * To prevent this, the module's records are set as disabled\n\t * and will be enabled after the call to set the module's text\n\t * to read-only.\n\t */\n\tif (mod)\n\t\trec_flags |= FTRACE_FL_DISABLED;\n\n\tfor (pg = new_pgs; pg; pg = pg->next) {\n\n\t\tfor (i = 0; i < pg->index; i++) {\n\n\t\t\t/* If something went wrong, bail without enabling anything */\n\t\t\tif (unlikely(ftrace_disabled))\n\t\t\t\treturn -1;\n\n\t\t\tp = &pg->records[i];\n\t\t\tp->flags = rec_flags;\n\n\t\t\t/*\n\t\t\t * Do the initial record conversion from mcount jump\n\t\t\t * to the NOP instructions.\n\t\t\t */\n\t\t\tif (init_nop && !ftrace_nop_initialize(mod, p))\n\t\t\t\tbreak;\n\n\t\t\tupdate_cnt++;\n\t\t}\n\t}\n\n\tstop = ftrace_now(raw_smp_processor_id());\n\tftrace_update_time = stop - start;\n\tftrace_update_tot_cnt += update_cnt;\n\n\treturn 0;\n}",
        "static int bpf_fill_ld_imm64_magn(struct bpf_test *self)\n{\n\tint block = 64; /* Increase for more tests per MSB position */\n\tint len = 3 + 8 * 63 * block * 2;\n\tstruct bpf_insn *insn;": "static int bpf_fill_ld_imm64_magn(struct bpf_test *self)\n{\n\tint block = 64; /* Increase for more tests per MSB position */\n\tint len = 3 + 8 * 63 * block * 2;\n\tstruct bpf_insn *insn;\n\tint bit, adj, sign;\n\tint i = 0;\n\n\tinsn = kmalloc_array(len, sizeof(*insn), GFP_KERNEL);\n\tif (!insn)\n\t\treturn -ENOMEM;\n\n\tinsn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, 0);\n\n\tfor (bit = 0; bit <= 62; bit++) {\n\t\tfor (adj = -block / 2; adj < block / 2; adj++) {\n\t\t\tfor (sign = -1; sign <= 1; sign += 2) {\n\t\t\t\ts64 imm = sign * ((1LL << bit) + adj);\n\n\t\t\t\t/* Perform operation */\n\t\t\t\ti += __bpf_ld_imm64(&insn[i], R1, imm);\n\n\t\t\t\t/* Load reference */\n\t\t\t\tinsn[i++] = BPF_ALU32_IMM(BPF_MOV, R2, imm);\n\t\t\t\tinsn[i++] = BPF_ALU32_IMM(BPF_MOV, R3,\n\t\t\t\t\t\t\t  (u32)(imm >> 32));\n\t\t\t\tinsn[i++] = BPF_ALU64_IMM(BPF_LSH, R3, 32);\n\t\t\t\tinsn[i++] = BPF_ALU64_REG(BPF_OR, R2, R3);\n\n\t\t\t\t/* Check result */\n\t\t\t\tinsn[i++] = BPF_JMP_REG(BPF_JEQ, R1, R2, 1);\n\t\t\t\tinsn[i++] = BPF_EXIT_INSN();\n\t\t\t}\n\t\t}\n\t}\n\n\tinsn[i++] = BPF_ALU64_IMM(BPF_MOV, R0, 1);\n\tinsn[i++] = BPF_EXIT_INSN();\n\n\tself->u.ptr.insns = insn;\n\tself->u.ptr.len = len;\n\tBUG_ON(i != len);\n\n\treturn 0;\n}",
        "static void dib8000_set_13seg_channel(struct dib8000_state *state)\n{\n\tu16 i;\n\tu16 coff_pow = 0x2800;\n": "static void dib8000_set_13seg_channel(struct dib8000_state *state)\n{\n\tu16 i;\n\tu16 coff_pow = 0x2800;\n\n\tstate->seg_mask = 0x1fff; /* All 13 segments enabled */\n\n\t/* ---- COFF ---- Carloff, the most robust --- */\n\tif (state->isdbt_cfg_loaded == 0) {  /* if not Sound Broadcasting mode : put default values for 13 segments */\n\t\tdib8000_write_word(state, 180, (16 << 6) | 9);\n\t\tdib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);\n\t\tcoff_pow = 0x2800;\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tdib8000_write_word(state, 181+i, coff_pow);\n\n\t\t/* P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1 */\n\t\t/* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 */\n\t\tdib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);\n\n\t\t/* P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 */\n\t\tdib8000_write_word(state, 340, (8 << 6) | (6 << 0));\n\t\t/* P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 */\n\t\tdib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));\n\n\t\tdib8000_write_word(state, 228, 0);  /* default value */\n\t\tdib8000_write_word(state, 265, 31); /* default value */\n\t\tdib8000_write_word(state, 205, 0x200f); /* init value */\n\t}\n\n\t/*\n\t * make the cpil_coff_lock more robust but slower p_coff_winlen\n\t * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)\n\t */\n\n\tif (state->cfg.pll->ifreq == 0)\n\t\tdib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */\n\n\tdib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);\n}",
        "static int nl802154_add_llsec_key(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct cfg802154_registered_device *rdev = info->user_ptr[0];\n\tstruct net_device *dev = info->user_ptr[1];\n\tstruct wpan_dev *wpan_dev = dev->ieee802154_ptr;": "static int nl802154_add_llsec_key(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct cfg802154_registered_device *rdev = info->user_ptr[0];\n\tstruct net_device *dev = info->user_ptr[1];\n\tstruct wpan_dev *wpan_dev = dev->ieee802154_ptr;\n\tstruct nlattr *attrs[NL802154_KEY_ATTR_MAX + 1];\n\tstruct ieee802154_llsec_key key = { };\n\tstruct ieee802154_llsec_key_id id = { };\n\tu32 commands[NL802154_CMD_FRAME_NR_IDS / 32] = { };\n\n\tif (wpan_dev->iftype == NL802154_IFTYPE_MONITOR)\n\t\treturn -EOPNOTSUPP;\n\n\tif (!info->attrs[NL802154_ATTR_SEC_KEY] ||\n\t    nla_parse_nested_deprecated(attrs, NL802154_KEY_ATTR_MAX, info->attrs[NL802154_ATTR_SEC_KEY], nl802154_key_policy, info->extack))\n\t\treturn -EINVAL;\n\n\tif (!attrs[NL802154_KEY_ATTR_USAGE_FRAMES] ||\n\t    !attrs[NL802154_KEY_ATTR_BYTES])\n\t\treturn -EINVAL;\n\n\tif (ieee802154_llsec_parse_key_id(attrs[NL802154_KEY_ATTR_ID], &id) < 0)\n\t\treturn -ENOBUFS;\n\n\tkey.frame_types = nla_get_u8(attrs[NL802154_KEY_ATTR_USAGE_FRAMES]);\n\tif (key.frame_types > BIT(NL802154_FRAME_MAX) ||\n\t    ((key.frame_types & BIT(NL802154_FRAME_CMD)) &&\n\t     !attrs[NL802154_KEY_ATTR_USAGE_CMDS]))\n\t\treturn -EINVAL;\n\n\tif (attrs[NL802154_KEY_ATTR_USAGE_CMDS]) {\n\t\t/* TODO for each nested */\n\t\tnla_memcpy(commands, attrs[NL802154_KEY_ATTR_USAGE_CMDS],\n\t\t\t   NL802154_CMD_FRAME_NR_IDS / 8);\n\n\t\t/* TODO understand the -EINVAL logic here? last condition */\n\t\tif (commands[0] || commands[1] || commands[2] || commands[3] ||\n\t\t    commands[4] || commands[5] || commands[6] ||\n\t\t    commands[7] > BIT(NL802154_CMD_FRAME_MAX))\n\t\t\treturn -EINVAL;\n\n\t\tkey.cmd_frame_ids = commands[7];\n\t} else {\n\t\tkey.cmd_frame_ids = 0;\n\t}\n\n\tnla_memcpy(key.key, attrs[NL802154_KEY_ATTR_BYTES], NL802154_KEY_SIZE);\n\n\tif (ieee802154_llsec_parse_key_id(attrs[NL802154_KEY_ATTR_ID], &id) < 0)\n\t\treturn -ENOBUFS;\n\n\treturn rdev_add_llsec_key(rdev, wpan_dev, &id, &key);\n}",
        "static void perf_syscall_exit(void *ignore, struct pt_regs *regs, long ret)\n{\n\tstruct syscall_metadata *sys_data;\n\tstruct syscall_trace_exit *rec;\n\tstruct hlist_head *head;": "static void perf_syscall_exit(void *ignore, struct pt_regs *regs, long ret)\n{\n\tstruct syscall_metadata *sys_data;\n\tstruct syscall_trace_exit *rec;\n\tstruct hlist_head *head;\n\tbool valid_prog_array;\n\tint syscall_nr;\n\tint rctx;\n\tint size;\n\n\tsyscall_nr = trace_get_syscall_nr(current, regs);\n\tif (syscall_nr < 0 || syscall_nr >= NR_syscalls)\n\t\treturn;\n\tif (!test_bit(syscall_nr, enabled_perf_exit_syscalls))\n\t\treturn;\n\n\tsys_data = syscall_nr_to_meta(syscall_nr);\n\tif (!sys_data)\n\t\treturn;\n\n\thead = this_cpu_ptr(sys_data->exit_event->perf_events);\n\tvalid_prog_array = bpf_prog_array_valid(sys_data->exit_event);\n\tif (!valid_prog_array && hlist_empty(head))\n\t\treturn;\n\n\t/* We can probably do that at build time */\n\tsize = ALIGN(sizeof(*rec) + sizeof(u32), sizeof(u64));\n\tsize -= sizeof(u32);\n\n\trec = perf_trace_buf_alloc(size, NULL, &rctx);\n\tif (!rec)\n\t\treturn;\n\n\trec->nr = syscall_nr;\n\trec->ret = syscall_get_return_value(current, regs);\n\n\tif ((valid_prog_array &&\n\t     !perf_call_bpf_exit(sys_data->exit_event, regs, rec)) ||\n\t    hlist_empty(head)) {\n\t\tperf_swevent_put_recursion_context(rctx);\n\t\treturn;\n\t}\n\n\tperf_trace_buf_submit(rec, size, rctx, sys_data->exit_event->event.type,\n\t\t\t      1, regs, head, NULL);\n}",
        "static int snd_trident_4d_nx_init(struct snd_trident *trident)\n{\n\tstruct pci_dev *pci = trident->pci;\n\tunsigned long end_time;\n": "static int snd_trident_4d_nx_init(struct snd_trident *trident)\n{\n\tstruct pci_dev *pci = trident->pci;\n\tunsigned long end_time;\n\n\t/* reset the legacy configuration and whole audio/wavetable block */\n\tpci_write_config_dword(pci, 0x40, 0);\t/* DDMA */\n\tpci_write_config_byte(pci, 0x44, 0);\t/* ports */\n\tpci_write_config_byte(pci, 0x45, 0);\t/* Legacy DMA */\n\n\tpci_write_config_byte(pci, 0x46, 1); /* reset */\n\tudelay(100);\n\tpci_write_config_byte(pci, 0x46, 0); /* release reset */\n\tudelay(100);\n\n\t/* warm reset of the AC'97 codec */\n\toutl(0x00000001, TRID_REG(trident, NX_ACR0_AC97_COM_STAT));\n\tudelay(100);\n\toutl(0x00000000, TRID_REG(trident, NX_ACR0_AC97_COM_STAT));\n\t/* wait, until the codec is ready */\n\tend_time = (jiffies + (HZ * 3) / 4) + 1;\n\tdo {\n\t\tif ((inl(TRID_REG(trident, NX_ACR0_AC97_COM_STAT)) & 0x0008) != 0)\n\t\t\tgoto __nx_ok;\n\t\tdo_delay(trident);\n\t} while (time_after_eq(end_time, jiffies));\n\tdev_err(trident->card->dev, \"AC'97 codec ready error [0x%x]\\n\",\n\t\tinl(TRID_REG(trident, NX_ACR0_AC97_COM_STAT)));\n\treturn -EIO;\n\n __nx_ok:\n\t/* DAC on */\n\ttrident->ac97_ctrl = 0x00000002;\n\toutl(trident->ac97_ctrl, TRID_REG(trident, NX_ACR0_AC97_COM_STAT));\n\t/* disable SB IRQ */\n\toutl(NX_SB_IRQ_DISABLE, TRID_REG(trident, T4D_MISCINT));\n\n\tsnd_trident_stop_all_voices(trident);\n\n\tif (trident->tlb.entries != NULL) {\n\t\tunsigned int i;\n\t\t/* enable virtual addressing via TLB */\n\t\ti = trident->tlb.entries_dmaaddr;\n\t\ti |= 0x00000001;\n\t\toutl(i, TRID_REG(trident, NX_TLBC));\n\t} else {\n\t\toutl(0, TRID_REG(trident, NX_TLBC));\n\t}\n\t/* initialize S/PDIF */\n\toutl(trident->spdif_bits, TRID_REG(trident, NX_SPCSTATUS));\n\toutb(trident->spdif_ctrl, TRID_REG(trident, NX_SPCTRL_SPCSO + 3));\n\n\treturn 0;\n}",
        "static void build_posix_ctxt(struct smb2_posix_neg_context *pneg_ctxt)\n{\n\tpneg_ctxt->ContextType = SMB2_POSIX_EXTENSIONS_AVAILABLE;\n\tpneg_ctxt->DataLength = cpu_to_le16(POSIX_CTXT_DATA_LEN);\n\t/* SMB2_CREATE_TAG_POSIX is \"0x93AD25509CB411E7B42383DE968BCD7C\" */": "static void build_posix_ctxt(struct smb2_posix_neg_context *pneg_ctxt)\n{\n\tpneg_ctxt->ContextType = SMB2_POSIX_EXTENSIONS_AVAILABLE;\n\tpneg_ctxt->DataLength = cpu_to_le16(POSIX_CTXT_DATA_LEN);\n\t/* SMB2_CREATE_TAG_POSIX is \"0x93AD25509CB411E7B42383DE968BCD7C\" */\n\tpneg_ctxt->Name[0] = 0x93;\n\tpneg_ctxt->Name[1] = 0xAD;\n\tpneg_ctxt->Name[2] = 0x25;\n\tpneg_ctxt->Name[3] = 0x50;\n\tpneg_ctxt->Name[4] = 0x9C;\n\tpneg_ctxt->Name[5] = 0xB4;\n\tpneg_ctxt->Name[6] = 0x11;\n\tpneg_ctxt->Name[7] = 0xE7;\n\tpneg_ctxt->Name[8] = 0xB4;\n\tpneg_ctxt->Name[9] = 0x23;\n\tpneg_ctxt->Name[10] = 0x83;\n\tpneg_ctxt->Name[11] = 0xDE;\n\tpneg_ctxt->Name[12] = 0x96;\n\tpneg_ctxt->Name[13] = 0x8B;\n\tpneg_ctxt->Name[14] = 0xCD;\n\tpneg_ctxt->Name[15] = 0x7C;\n}",
        "static void dos_write(int disk)\n{\n\tint cnt;\n\tunsigned long raw = (unsigned long) raw_buf;\n\tunsigned long *ptr=(unsigned long *)raw;": "static void dos_write(int disk)\n{\n\tint cnt;\n\tunsigned long raw = (unsigned long) raw_buf;\n\tunsigned long *ptr=(unsigned long *)raw;\n\n\tdisk&=3;\n/* really gap4 + indexgap , but we write it first and round it up */\n\tfor (cnt=0;cnt<425;cnt++)\n\t\t*ptr++=0x92549254;\n\n/* the following is just guessed */\n\tif (unit[disk].type->sect_mult==2)  /* check for HD-Disks */\n\t\tfor(cnt=0;cnt<473;cnt++)\n\t\t\t*ptr++=0x92549254;\n\n/* now the index marks...*/\n\tfor (cnt=0;cnt<20;cnt++)\n\t\t*ptr++=0x92549254;\n\tfor (cnt=0;cnt<6;cnt++)\n\t\t*ptr++=0xaaaaaaaa;\n\t*ptr++=0x52245224;\n\t*ptr++=0x52245552;\n\tfor (cnt=0;cnt<20;cnt++)\n\t\t*ptr++=0x92549254;\n\n/* sectors */\n\tfor(cnt = 0; cnt < unit[disk].dtype->sects * unit[disk].type->sect_mult; cnt++)\n\t\tptr=ms_putsec(disk,ptr,cnt);\n\n\t*(ushort *)ptr = 0xaaa8; /* MFM word before is always 0x9254 */\n}",
        "static void INFTL_trydeletechain(struct INFTLrecord *inftl, unsigned thisVUC)\n{\n\tstruct mtd_info *mtd = inftl->mbd.mtd;\n\tunsigned char BlockUsed[MAX_SECTORS_PER_UNIT];\n\tunsigned char BlockDeleted[MAX_SECTORS_PER_UNIT];": "static void INFTL_trydeletechain(struct INFTLrecord *inftl, unsigned thisVUC)\n{\n\tstruct mtd_info *mtd = inftl->mbd.mtd;\n\tunsigned char BlockUsed[MAX_SECTORS_PER_UNIT];\n\tunsigned char BlockDeleted[MAX_SECTORS_PER_UNIT];\n\tunsigned int thisEUN, status;\n\tint block, silly;\n\tstruct inftl_bci bci;\n\tsize_t retlen;\n\n\tpr_debug(\"INFTL: INFTL_trydeletechain(inftl=%p,\"\n\t\t\"thisVUC=%d)\\n\", inftl, thisVUC);\n\n\tmemset(BlockUsed, 0, sizeof(BlockUsed));\n\tmemset(BlockDeleted, 0, sizeof(BlockDeleted));\n\n\tthisEUN = inftl->VUtable[thisVUC];\n\tif (thisEUN == BLOCK_NIL) {\n\t\tprintk(KERN_WARNING \"INFTL: trying to delete non-existent \"\n\t\t       \"Virtual Unit Chain %d!\\n\", thisVUC);\n\t\treturn;\n\t}\n\n\t/*\n\t * Scan through the Erase Units to determine whether any data is in\n\t * each of the 512-byte blocks within the Chain.\n\t */\n\tsilly = MAX_LOOPS;\n\twhile (thisEUN < inftl->nb_blocks) {\n\t\tfor (block = 0; block < inftl->EraseSize/SECTORSIZE; block++) {\n\t\t\tif (BlockUsed[block] || BlockDeleted[block])\n\t\t\t\tcontinue;\n\n\t\t\tif (inftl_read_oob(mtd, (thisEUN * inftl->EraseSize)\n\t\t\t\t\t   + (block * SECTORSIZE), 8 , &retlen,\n\t\t\t\t\t  (char *)&bci) < 0)\n\t\t\t\tstatus = SECTOR_IGNORE;\n\t\t\telse\n\t\t\t\tstatus = bci.Status | bci.Status1;\n\n\t\t\tswitch(status) {\n\t\t\tcase SECTOR_FREE:\n\t\t\tcase SECTOR_IGNORE:\n\t\t\t\tbreak;\n\t\t\tcase SECTOR_USED:\n\t\t\t\tBlockUsed[block] = 1;\n\t\t\t\tcontinue;\n\t\t\tcase SECTOR_DELETED:\n\t\t\t\tBlockDeleted[block] = 1;\n\t\t\t\tcontinue;\n\t\t\tdefault:\n\t\t\t\tprintk(KERN_WARNING \"INFTL: unknown status \"\n\t\t\t\t\t\"for block %d in EUN %d: 0x%x\\n\",\n\t\t\t\t\tblock, thisEUN, status);\n\t\t\t}\n\t\t}\n\n\t\tif (!silly--) {\n\t\t\tprintk(KERN_WARNING \"INFTL: infinite loop in Virtual \"\n\t\t\t\t\"Unit Chain 0x%x\\n\", thisVUC);\n\t\t\treturn;\n\t\t}\n\n\t\tthisEUN = inftl->PUtable[thisEUN];\n\t}\n\n\tfor (block = 0; block < inftl->EraseSize/SECTORSIZE; block++)\n\t\tif (BlockUsed[block])\n\t\t\treturn;\n\n\t/*\n\t * For each block in the chain free it and make it available\n\t * for future use. Erase from the oldest unit first.\n\t */\n\tpr_debug(\"INFTL: deleting empty VUC %d\\n\", thisVUC);\n\n\tfor (;;) {\n\t\tu16 *prevEUN = &inftl->VUtable[thisVUC];\n\t\tthisEUN = *prevEUN;\n\n\t\t/* If the chain is all gone already, we're done */\n\t\tif (thisEUN == BLOCK_NIL) {\n\t\t\tpr_debug(\"INFTL: Empty VUC %d for deletion was already absent\\n\", thisEUN);\n\t\t\treturn;\n\t\t}\n\n\t\t/* Find oldest unit in chain. */\n\t\twhile (inftl->PUtable[thisEUN] != BLOCK_NIL) {\n\t\t\tBUG_ON(thisEUN >= inftl->nb_blocks);\n\n\t\t\tprevEUN = &inftl->PUtable[thisEUN];\n\t\t\tthisEUN = *prevEUN;\n\t\t}\n\n\t\tpr_debug(\"Deleting EUN %d from VUC %d\\n\",\n\t\t      thisEUN, thisVUC);\n\n\t\tif (INFTL_formatblock(inftl, thisEUN) < 0) {\n\t\t\t/*\n\t\t\t * Could not erase : mark block as reserved.\n\t\t\t */\n\t\t\tinftl->PUtable[thisEUN] = BLOCK_RESERVED;\n\t\t} else {\n\t\t\t/* Correctly erased : mark it as free */\n\t\t\tinftl->PUtable[thisEUN] = BLOCK_FREE;\n\t\t\tinftl->numfreeEUNs++;\n\t\t}\n\n\t\t/* Now sort out whatever was pointing to it... */\n\t\t*prevEUN = BLOCK_NIL;\n\n\t\t/* Ideally we'd actually be responsive to new\n\t\t   requests while we're doing this -- if there's\n\t\t   free space why should others be made to wait? */\n\t\tcond_resched();\n\t}\n\n\tinftl->VUtable[thisVUC] = BLOCK_NIL;\n}",
        "static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf)\n{\n\tstruct vdec_fb *fb;\n\tu64 vdec_fb_va;\n\tu64 y_fb_dma, c_fb_dma;": "static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf)\n{\n\tstruct vdec_fb *fb;\n\tu64 vdec_fb_va;\n\tu64 y_fb_dma, c_fb_dma;\n\tint err, timeout, i;\n\tstruct mtk_vcodec_ctx *ctx = lat_buf->ctx;\n\tstruct vdec_h264_slice_inst *inst = ctx->drv_handle;\n\tstruct vb2_v4l2_buffer *vb2_v4l2;\n\tstruct vdec_h264_slice_share_info *share_info = lat_buf->private_data;\n\tstruct mtk_vcodec_mem *mem;\n\tstruct vdec_vpu_inst *vpu = &inst->vpu;\n\n\tmtk_vcodec_debug(inst, \"[h264-core] vdec_h264 core decode\");\n\tmemcpy(&inst->vsi_core->h264_slice_params, &share_info->h264_slice_params,\n\t       sizeof(share_info->h264_slice_params));\n\n\tfb = ctx->dev->vdec_pdata->get_cap_buffer(ctx);\n\ty_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0;\n\tvdec_fb_va = (unsigned long)fb;\n\n\tif (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1)\n\t\tc_fb_dma =\n\t\t\ty_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h;\n\telse\n\t\tc_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0;\n\n\tmtk_vcodec_debug(inst, \"[h264-core] y/c addr = 0x%llx 0x%llx\", y_fb_dma,\n\t\t\t c_fb_dma);\n\n\tinst->vsi_core->dec.y_fb_dma = y_fb_dma;\n\tinst->vsi_core->dec.c_fb_dma = c_fb_dma;\n\tinst->vsi_core->dec.vdec_fb_va = vdec_fb_va;\n\tinst->vsi_core->dec.nal_info = share_info->nal_info;\n\tinst->vsi_core->wdma_start_addr =\n\t\tlat_buf->ctx->msg_queue.wdma_addr.dma_addr;\n\tinst->vsi_core->wdma_end_addr =\n\t\tlat_buf->ctx->msg_queue.wdma_addr.dma_addr +\n\t\tlat_buf->ctx->msg_queue.wdma_addr.size;\n\tinst->vsi_core->wdma_err_addr = lat_buf->wdma_err_addr.dma_addr;\n\tinst->vsi_core->slice_bc_start_addr = lat_buf->slice_bc_addr.dma_addr;\n\tinst->vsi_core->slice_bc_end_addr = lat_buf->slice_bc_addr.dma_addr +\n\t\tlat_buf->slice_bc_addr.size;\n\tinst->vsi_core->trans_start = share_info->trans_start;\n\tinst->vsi_core->trans_end = share_info->trans_end;\n\tfor (i = 0; i < H264_MAX_MV_NUM; i++) {\n\t\tmem = &inst->mv_buf[i];\n\t\tinst->vsi_core->mv_buf_dma[i] = mem->dma_addr;\n\t}\n\n\tvb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);\n\tv4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true);\n\n\tvdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core->h264_slice_params,\n\t\t\t\t\t    share_info);\n\n\terr = vpu_dec_core(vpu);\n\tif (err) {\n\t\tmtk_vcodec_err(inst, \"core decode err=%d\", err);\n\t\tgoto vdec_dec_end;\n\t}\n\n\t/* wait decoder done interrupt */\n\ttimeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,\n\t\t\t\t\t       WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE);\n\tif (timeout)\n\t\tmtk_vcodec_err(inst, \"core decode timeout: pic_%d\",\n\t\t\t       ctx->decoded_frame_cnt);\n\tinst->vsi_core->dec.timeout = !!timeout;\n\n\tvpu_dec_core_end(vpu);\n\tmtk_vcodec_debug(inst, \"pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\",\n\t\t\t ctx->decoded_frame_cnt,\n\t\t\t inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1],\n\t\t\t inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3],\n\t\t\t inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5],\n\t\t\t inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]);\n\nvdec_dec_end:\n\tvdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->trans_end);\n\tctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req);\n\tmtk_vcodec_debug(inst, \"core decode done err=%d\", err);\n\tctx->decoded_frame_cnt++;\n\treturn 0;\n}",
        "static void ipa_cmd_validate_build(void)\n{\n\t/* The sizes of a filter and route tables need to fit into fields\n\t * in the ipa_cmd_hw_ip_fltrt_init structure.  Although hashed tables\n\t * might not be used, non-hashed and hashed tables have the same": "static void ipa_cmd_validate_build(void)\n{\n\t/* The sizes of a filter and route tables need to fit into fields\n\t * in the ipa_cmd_hw_ip_fltrt_init structure.  Although hashed tables\n\t * might not be used, non-hashed and hashed tables have the same\n\t * maximum size.  IPv4 and IPv6 filter tables have the same number\n\t * of entries, as and IPv4 and IPv6 route tables have the same number\n\t * of entries.\n\t */\n#define TABLE_SIZE\t(TABLE_COUNT_MAX * sizeof(__le64))\n#define TABLE_COUNT_MAX\tmax_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX)\n\tBUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK));\n\tBUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));\n#undef TABLE_COUNT_MAX\n#undef TABLE_SIZE\n\n\t/* Hashed and non-hashed fields are assumed to be the same size */\n\tBUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK) !=\n\t\t     field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));\n\tBUILD_BUG_ON(field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) !=\n\t\t     field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK));\n\n\t/* Valid endpoint numbers must fit in the IP packet init command */\n\tBUILD_BUG_ON(field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK) <\n\t\t     IPA_ENDPOINT_MAX - 1);\n}",
        "static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, uint32_t opcode)\n{\n\tstruct audioreach_graph_info *info = graph->info;\n\tint num_sub_graphs = info->num_sub_graphs;\n\tstruct apm_module_param_data *param_data;": "static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, uint32_t opcode)\n{\n\tstruct audioreach_graph_info *info = graph->info;\n\tint num_sub_graphs = info->num_sub_graphs;\n\tstruct apm_module_param_data *param_data;\n\tstruct apm_graph_mgmt_cmd *mgmt_cmd;\n\tstruct audioreach_sub_graph *sg;\n\tstruct q6apm *apm = graph->apm;\n\tint i = 0, rc, payload_size;\n\tstruct gpr_pkt *pkt;\n\n\tpayload_size = APM_GRAPH_MGMT_PSIZE(mgmt_cmd, num_sub_graphs);\n\n\tpkt = audioreach_alloc_apm_cmd_pkt(payload_size, opcode, 0);\n\tif (IS_ERR(pkt))\n\t\treturn PTR_ERR(pkt);\n\n\tmgmt_cmd = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;\n\n\tmgmt_cmd->num_sub_graphs = num_sub_graphs;\n\n\tparam_data = &mgmt_cmd->param_data;\n\tparam_data->module_instance_id = APM_MODULE_INSTANCE_ID;\n\tparam_data->param_id = APM_PARAM_ID_SUB_GRAPH_LIST;\n\tparam_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;\n\n\tlist_for_each_entry(sg, &info->sg_list, node)\n\t\tmgmt_cmd->sub_graph_id_list[i++] = sg->sub_graph_id;\n\n\trc = q6apm_send_cmd_sync(apm, pkt, 0);\n\n\tkfree(pkt);\n\n\treturn rc;\n}",
        "static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)\n{\n\tstruct q6prm *prm = dev_get_drvdata(dev->parent);\n\tstruct apm_module_param_data *param_data;\n\tstruct prm_cmd_request_hw_core *req;": "static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)\n{\n\tstruct q6prm *prm = dev_get_drvdata(dev->parent);\n\tstruct apm_module_param_data *param_data;\n\tstruct prm_cmd_request_hw_core *req;\n\tgpr_device_t *gdev = prm->gdev;\n\tuint32_t opcode, rsp_opcode;\n\tstruct gpr_pkt *pkt;\n\tint rc;\n\n\tif (enable) {\n\t\topcode = PRM_CMD_REQUEST_HW_RSC;\n\t\trsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC;\n\t} else {\n\t\topcode = PRM_CMD_RELEASE_HW_RSC;\n\t\trsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC;\n\t}\n\n\tpkt = audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->svc.id, GPR_PRM_MODULE_IID);\n\tif (IS_ERR(pkt))\n\t\treturn PTR_ERR(pkt);\n\n\treq = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;\n\n\tparam_data = &req->param_data;\n\n\tparam_data->module_instance_id = GPR_PRM_MODULE_IID;\n\tparam_data->error_code = 0;\n\tparam_data->param_id = PARAM_ID_RSC_HW_CORE;\n\tparam_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;\n\n\treq->hw_clk_id = hw_block_id;\n\n\trc = q6prm_send_cmd_sync(prm, pkt, rsp_opcode);\n\n\tkfree(pkt);\n\n\treturn rc;\n}",
        "static bool page_pool_dma_map(struct page_pool *pool, struct page *page)\n{\n\tdma_addr_t dma;\n\n\t/* Setup DMA mapping: use 'struct page' area for storing DMA-addr": "static bool page_pool_dma_map(struct page_pool *pool, struct page *page)\n{\n\tdma_addr_t dma;\n\n\t/* Setup DMA mapping: use 'struct page' area for storing DMA-addr\n\t * since dma_addr_t can be either 32 or 64 bits and does not always fit\n\t * into page private data (i.e 32bit cpu with 64bit DMA caps)\n\t * This mapping is kept for lifetime of page, until leaving pool.\n\t */\n\tdma = dma_map_page_attrs(pool->p.dev, page, 0,\n\t\t\t\t (PAGE_SIZE << pool->p.order),\n\t\t\t\t pool->p.dma_dir, DMA_ATTR_SKIP_CPU_SYNC);\n\tif (dma_mapping_error(pool->p.dev, dma))\n\t\treturn false;\n\n\tpage_pool_set_dma_addr(page, dma);\n\n\tif (pool->p.flags & PP_FLAG_DMA_SYNC_DEV)\n\t\tpage_pool_dma_sync_for_device(pool, page, pool->p.max_len);\n\n\treturn true;\n}",
        "static int power_down_vsb(struct drx_demod_instance *demod, bool primary)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tstruct drxjscu_cmd cmd_scu = { /* command     */ 0,\n\t\t/* parameter_len */ 0,": "static int power_down_vsb(struct drx_demod_instance *demod, bool primary)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tstruct drxjscu_cmd cmd_scu = { /* command     */ 0,\n\t\t/* parameter_len */ 0,\n\t\t/* result_len    */ 0,\n\t\t/* *parameter   */ NULL,\n\t\t/* *result      */ NULL\n\t};\n\tstruct drx_cfg_mpeg_output cfg_mpeg_output;\n\tint rc;\n\tu16 cmd_result = 0;\n\n\t/*\n\t   STOP demodulator\n\t   reset of FEC and VSB HW\n\t */\n\tcmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |\n\t    SCU_RAM_COMMAND_CMD_DEMOD_STOP;\n\tcmd_scu.parameter_len = 0;\n\tcmd_scu.result_len = 1;\n\tcmd_scu.parameter = NULL;\n\tcmd_scu.result = &cmd_result;\n\trc = scu_command(dev_addr, &cmd_scu);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* stop all comm_exec */\n\trc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (primary) {\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = set_iqm_af(demod, false);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t} else {\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t\trc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);\n\t\tif (rc != 0) {\n\t\t\tpr_err(\"error %d\\n\", rc);\n\t\t\tgoto rw_error;\n\t\t}\n\t}\n\n\tcfg_mpeg_output.enable_mpeg_output = false;\n\trc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int isc_configure(struct isc_device *isc)\n{\n\tstruct regmap *regmap = isc->regmap;\n\tu32 pfe_cfg0, dcfg, mask, pipeline;\n\tstruct isc_subdev_entity *subdev = isc->current_subdev;": "static int isc_configure(struct isc_device *isc)\n{\n\tstruct regmap *regmap = isc->regmap;\n\tu32 pfe_cfg0, dcfg, mask, pipeline;\n\tstruct isc_subdev_entity *subdev = isc->current_subdev;\n\n\tpfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;\n\tpipeline = isc->config.bits_pipeline;\n\n\tdcfg = isc->config.dcfg_imode | isc->dcfg;\n\n\tpfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;\n\tmask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |\n\t       ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |\n\t       ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |\n\t       ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;\n\n\tregmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);\n\n\tisc->config_rlp(isc);\n\n\tregmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);\n\n\t/* Set the pipeline */\n\tisc_set_pipeline(isc, pipeline);\n\n\t/*\n\t * The current implemented histogram is available for RAW R, B, GB, GR\n\t * channels. We need to check if sensor is outputting RAW BAYER\n\t */\n\tif (isc->ctrls.awb &&\n\t    ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))\n\t\tisc_set_histogram(isc, true);\n\telse\n\t\tisc_set_histogram(isc, false);\n\n\t/* Update profile */\n\treturn isc_update_profile(isc);\n}",
        "static int m88rs6000t_get_rf_strength(struct dvb_frontend *fe, u16 *strength)\n{\n\tstruct m88rs6000t_dev *dev = fe->tuner_priv;\n\tunsigned int val, i;\n\tint ret;": "static int m88rs6000t_get_rf_strength(struct dvb_frontend *fe, u16 *strength)\n{\n\tstruct m88rs6000t_dev *dev = fe->tuner_priv;\n\tunsigned int val, i;\n\tint ret;\n\tu16 gain;\n\tu32 PGA2_cri_GS = 46, PGA2_crf_GS = 290, TIA_GS = 290;\n\tu32 RF_GC = 1200, IF_GC = 1100, BB_GC = 300;\n\tu32 PGA2_GC = 300, TIA_GC = 300, PGA2_cri = 0, PGA2_crf = 0;\n\tu32 RFG = 0, IFG = 0, BBG = 0, PGA2G = 0, TIAG = 0;\n\tu32 RFGS[13] = {0, 245, 266, 268, 270, 285,\n\t\t\t298, 295, 283, 285, 285, 300, 300};\n\tu32 IFGS[12] = {0, 300, 230, 270, 270, 285,\n\t\t\t295, 285, 290, 295, 295, 310};\n\tu32 BBGS[14] = {0, 286, 275, 290, 294, 300, 290,\n\t\t\t290, 285, 283, 260, 295, 290, 260};\n\n\tret = regmap_read(dev->regmap, 0x5A, &val);\n\tif (ret)\n\t\tgoto err;\n\tRF_GC = val & 0x0f;\n\n\tret = regmap_read(dev->regmap, 0x5F, &val);\n\tif (ret)\n\t\tgoto err;\n\tIF_GC = val & 0x0f;\n\n\tret = regmap_read(dev->regmap, 0x3F, &val);\n\tif (ret)\n\t\tgoto err;\n\tTIA_GC = (val >> 4) & 0x07;\n\n\tret = regmap_read(dev->regmap, 0x77, &val);\n\tif (ret)\n\t\tgoto err;\n\tBB_GC = (val >> 4) & 0x0f;\n\n\tret = regmap_read(dev->regmap, 0x76, &val);\n\tif (ret)\n\t\tgoto err;\n\tPGA2_GC = val & 0x3f;\n\tPGA2_cri = PGA2_GC >> 2;\n\tPGA2_crf = PGA2_GC & 0x03;\n\n\tfor (i = 0; i <= RF_GC && i < ARRAY_SIZE(RFGS); i++)\n\t\tRFG += RFGS[i];\n\n\tif (RF_GC == 0)\n\t\tRFG += 400;\n\tif (RF_GC == 1)\n\t\tRFG += 300;\n\tif (RF_GC == 2)\n\t\tRFG += 200;\n\tif (RF_GC == 3)\n\t\tRFG += 100;\n\n\tfor (i = 0; i <= IF_GC && i < ARRAY_SIZE(IFGS); i++)\n\t\tIFG += IFGS[i];\n\n\tTIAG = TIA_GC * TIA_GS;\n\n\tfor (i = 0; i <= BB_GC && i < ARRAY_SIZE(BBGS); i++)\n\t\tBBG += BBGS[i];\n\n\tPGA2G = PGA2_cri * PGA2_cri_GS + PGA2_crf * PGA2_crf_GS;\n\n\tgain = RFG + IFG - TIAG + BBG + PGA2G;\n\n\t/* scale value to 0x0000-0xffff */\n\tgain = clamp_val(gain, 1000U, 10500U);\n\t*strength = (10500 - gain) * 0xffff / (10500 - 1000);\nerr:\n\tif (ret)\n\t\tdev_dbg(&dev->client->dev, \"failed=%d\\n\", ret);\n\treturn ret;\n}",
        "static int dccp_msghdr_parse(struct msghdr *msg, struct sk_buff *skb)\n{\n\tstruct cmsghdr *cmsg;\n\n\t/*": "static int dccp_msghdr_parse(struct msghdr *msg, struct sk_buff *skb)\n{\n\tstruct cmsghdr *cmsg;\n\n\t/*\n\t * Assign an (opaque) qpolicy priority value to skb->priority.\n\t *\n\t * We are overloading this skb field for use with the qpolicy subystem.\n\t * The skb->priority is normally used for the SO_PRIORITY option, which\n\t * is initialised from sk_priority. Since the assignment of sk_priority\n\t * to skb->priority happens later (on layer 3), we overload this field\n\t * for use with queueing priorities as long as the skb is on layer 4.\n\t * The default priority value (if nothing is set) is 0.\n\t */\n\tskb->priority = 0;\n\n\tfor_each_cmsghdr(cmsg, msg) {\n\t\tif (!CMSG_OK(msg, cmsg))\n\t\t\treturn -EINVAL;\n\n\t\tif (cmsg->cmsg_level != SOL_DCCP)\n\t\t\tcontinue;\n\n\t\tif (cmsg->cmsg_type <= DCCP_SCM_QPOLICY_MAX &&\n\t\t    !dccp_qpolicy_param_ok(skb->sk, cmsg->cmsg_type))\n\t\t\treturn -EINVAL;\n\n\t\tswitch (cmsg->cmsg_type) {\n\t\tcase DCCP_SCM_PRIORITY:\n\t\t\tif (cmsg->cmsg_len != CMSG_LEN(sizeof(__u32)))\n\t\t\t\treturn -EINVAL;\n\t\t\tskb->priority = *(__u32 *)CMSG_DATA(cmsg);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static void tick_nohz_kick_task(struct task_struct *tsk)\n{\n\tint cpu;\n\n\t/*": "static void tick_nohz_kick_task(struct task_struct *tsk)\n{\n\tint cpu;\n\n\t/*\n\t * If the task is not running, run_posix_cpu_timers()\n\t * has nothing to elapse, IPI can then be spared.\n\t *\n\t * activate_task()                      STORE p->tick_dep_mask\n\t *   STORE p->on_rq\n\t * __schedule() (switch to task 'p')    smp_mb() (atomic_fetch_or())\n\t *   LOCK rq->lock                      LOAD p->on_rq\n\t *   smp_mb__after_spin_lock()\n\t *   tick_nohz_task_switch()\n\t *     LOAD p->tick_dep_mask\n\t */\n\tif (!sched_task_on_rq(tsk))\n\t\treturn;\n\n\t/*\n\t * If the task concurrently migrates to another CPU,\n\t * we guarantee it sees the new tick dependency upon\n\t * schedule.\n\t *\n\t * set_task_cpu(p, cpu);\n\t *   STORE p->cpu = @cpu\n\t * __schedule() (switch to task 'p')\n\t *   LOCK rq->lock\n\t *   smp_mb__after_spin_lock()          STORE p->tick_dep_mask\n\t *   tick_nohz_task_switch()            smp_mb() (atomic_fetch_or())\n\t *      LOAD p->tick_dep_mask           LOAD p->cpu\n\t */\n\tcpu = task_cpu(tsk);\n\n\tpreempt_disable();\n\tif (cpu_online(cpu))\n\t\ttick_nohz_full_kick_cpu(cpu);\n\tpreempt_enable();\n}",
        "static void test_errors(void)\n{\n\tstruct test_default t = test_default_init(guest_idle);\n\tint rv;\n": "static void test_errors(void)\n{\n\tstruct test_default t = test_default_init(guest_idle);\n\tint rv;\n\n\tHOST_SYNC(t.vcpu, STAGE_INITED);\n\n\t_test_errors_common(t.vcpu, LOGICAL, t.size);\n\t_test_errors_common(t.vm, ABSOLUTE, t.size);\n\n\t/* Bad operation: */\n\trv = ERR_MOP(t.vcpu, INVALID, WRITE, mem1, t.size, GADDR_V(mem1));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL, \"ioctl allows bad operations\");\n\t/* virtual addresses are not translated when passing INVALID */\n\trv = ERR_MOP(t.vm, INVALID, WRITE, mem1, PAGE_SIZE, GADDR(0));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL, \"ioctl allows bad operations\");\n\n\t/* Bad access register: */\n\tt.run->psw_mask &= ~(3UL << (63 - 17));\n\tt.run->psw_mask |= 1UL << (63 - 17);  /* Enable AR mode */\n\tHOST_SYNC(t.vcpu, STAGE_IDLED); /* To sync new state to SIE block */\n\trv = ERR_MOP(t.vcpu, LOGICAL, WRITE, mem1, t.size, GADDR_V(mem1), AR(17));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL, \"ioctl allows ARs > 15\");\n\tt.run->psw_mask &= ~(3UL << (63 - 17));   /* Disable AR mode */\n\tHOST_SYNC(t.vcpu, STAGE_IDLED); /* Run to sync new state */\n\n\t/* Check that the SIDA calls are rejected for non-protected guests */\n\trv = ERR_MOP(t.vcpu, SIDA, READ, mem1, 8, GADDR(0), SIDA_OFFSET(0x1c0));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL,\n\t\t    \"ioctl does not reject SIDA_READ in non-protected mode\");\n\trv = ERR_MOP(t.vcpu, SIDA, WRITE, mem1, 8, GADDR(0), SIDA_OFFSET(0x1c0));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL,\n\t\t    \"ioctl does not reject SIDA_WRITE in non-protected mode\");\n\n\tkvm_vm_free(t.kvm_vm);\n}",
        "static inline void ocfs2_generic_handle_convert_action(struct ocfs2_lock_res *lockres)\n{\n\tBUG_ON(!(lockres->l_flags & OCFS2_LOCK_BUSY));\n\tBUG_ON(!(lockres->l_flags & OCFS2_LOCK_ATTACHED));\n": "static inline void ocfs2_generic_handle_convert_action(struct ocfs2_lock_res *lockres)\n{\n\tBUG_ON(!(lockres->l_flags & OCFS2_LOCK_BUSY));\n\tBUG_ON(!(lockres->l_flags & OCFS2_LOCK_ATTACHED));\n\n\t/* Convert from RO to EX doesn't really need anything as our\n\t * information is already up to data. Convert from NL to\n\t * *anything* however should mark ourselves as needing an\n\t * update */\n\tif (lockres->l_level == DLM_LOCK_NL &&\n\t    lockres->l_ops->flags & LOCK_TYPE_REQUIRES_REFRESH)\n\t\tlockres_or_flags(lockres, OCFS2_LOCK_NEEDS_REFRESH);\n\n\tlockres->l_level = lockres->l_requested;\n\n\t/*\n\t * We set the OCFS2_LOCK_UPCONVERT_FINISHING flag before clearing\n\t * the OCFS2_LOCK_BUSY flag to prevent the dc thread from\n\t * downconverting the lock before the upconvert has fully completed.\n\t * Do not prevent the dc thread from downconverting if NONBLOCK lock\n\t * had already returned.\n\t */\n\tif (!(lockres->l_flags & OCFS2_LOCK_NONBLOCK_FINISHED))\n\t\tlockres_or_flags(lockres, OCFS2_LOCK_UPCONVERT_FINISHING);\n\telse\n\t\tlockres_clear_flags(lockres, OCFS2_LOCK_NONBLOCK_FINISHED);\n\n\tlockres_clear_flags(lockres, OCFS2_LOCK_BUSY);\n}",
        "static void set_next_task_dl(struct rq *rq, struct task_struct *p, bool first)\n{\n\tstruct sched_dl_entity *dl_se = &p->dl;\n\tstruct dl_rq *dl_rq = &rq->dl;\n": "static void set_next_task_dl(struct rq *rq, struct task_struct *p, bool first)\n{\n\tstruct sched_dl_entity *dl_se = &p->dl;\n\tstruct dl_rq *dl_rq = &rq->dl;\n\n\tp->se.exec_start = rq_clock_task(rq);\n\tif (on_dl_rq(&p->dl))\n\t\tupdate_stats_wait_end_dl(dl_rq, dl_se);\n\n\t/* You can't push away the running task */\n\tdequeue_pushable_dl_task(rq, p);\n\n\tif (!first)\n\t\treturn;\n\n\tif (hrtick_enabled_dl(rq))\n\t\tstart_hrtick_dl(rq, p);\n\n\tif (rq->curr->sched_class != &dl_sched_class)\n\t\tupdate_dl_rq_load_avg(rq_clock_pelt(rq), rq, 0);\n\n\tdeadline_queue_push_tasks(rq);\n}",
        "static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)\n{\n\tint status = 0;\n\tunsigned int dummy = 0;\n": "static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)\n{\n\tint status = 0;\n\tunsigned int dummy = 0;\n\n\tcodec_dbg(codec, \"     dspio_free_dma_chan() -- begin\\n\");\n\tcodec_dbg(codec, \"dspio_free_dma_chan: chan=%d\\n\", dma_chan);\n\n\tstatus = dspio_scp(codec, MASTERCONTROL, 0x20,\n\t\t\tMASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,\n\t\t\tsizeof(dma_chan), NULL, &dummy);\n\n\tif (status < 0) {\n\t\tcodec_dbg(codec, \"dspio_free_dma_chan: SCP Failed\\n\");\n\t\treturn status;\n\t}\n\n\tcodec_dbg(codec, \"     dspio_free_dma_chan() -- complete\\n\");\n\n\treturn status;\n}",
        "static void prepare_table(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;\n\tconst struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;\n\tconst struct v4l2_ctrl_h264_sps *sps = ctrls->sps;": "static void prepare_table(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;\n\tconst struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;\n\tconst struct v4l2_ctrl_h264_sps *sps = ctrls->sps;\n\tstruct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;\n\tconst struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;\n\tu32 dpb_longterm = 0;\n\tu32 dpb_valid = 0;\n\tint i;\n\n\tfor (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {\n\t\ttbl->poc[i * 2] = dpb[i].top_field_order_cnt;\n\t\ttbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;\n\n\t\tif (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * Set up bit maps of valid and long term DPBs.\n\t\t * NOTE: The bits are reversed, i.e. MSb is DPB 0. For frame\n\t\t * decoding, bit 31 to 15 are used, while for field decoding,\n\t\t * all bits are used, with bit 31 being a top field, 30 a bottom\n\t\t * field and so on.\n\t\t */\n\t\tif (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) {\n\t\t\tif (dpb[i].fields & V4L2_H264_TOP_FIELD_REF)\n\t\t\t\tdpb_valid |= REF_BIT(i * 2);\n\n\t\t\tif (dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF)\n\t\t\t\tdpb_valid |= REF_BIT(i * 2 + 1);\n\n\t\t\tif (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) {\n\t\t\t\tdpb_longterm |= REF_BIT(i * 2);\n\t\t\t\tdpb_longterm |= REF_BIT(i * 2 + 1);\n\t\t\t}\n\t\t} else {\n\t\t\tdpb_valid |= REF_BIT(i);\n\n\t\t\tif (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)\n\t\t\t\tdpb_longterm |= REF_BIT(i);\n\t\t}\n\t}\n\tctx->h264_dec.dpb_valid = dpb_valid;\n\tctx->h264_dec.dpb_longterm = dpb_longterm;\n\n\tif ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) ||\n\t    !(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {\n\t\ttbl->poc[32] = ctx->h264_dec.cur_poc;\n\t\ttbl->poc[33] = 0;\n\t} else {\n\t\ttbl->poc[32] = dec_param->top_field_order_cnt;\n\t\ttbl->poc[33] = dec_param->bottom_field_order_cnt;\n\t}\n\n\tassemble_scaling_list(ctx);\n}",
        "static int check_max_stack_depth(struct bpf_verifier_env *env)\n{\n\tint depth = 0, frame = 0, idx = 0, i = 0, subprog_end;\n\tstruct bpf_subprog_info *subprog = env->subprog_info;\n\tstruct bpf_insn *insn = env->prog->insnsi;": "static int check_max_stack_depth(struct bpf_verifier_env *env)\n{\n\tint depth = 0, frame = 0, idx = 0, i = 0, subprog_end;\n\tstruct bpf_subprog_info *subprog = env->subprog_info;\n\tstruct bpf_insn *insn = env->prog->insnsi;\n\tbool tail_call_reachable = false;\n\tint ret_insn[MAX_CALL_FRAMES];\n\tint ret_prog[MAX_CALL_FRAMES];\n\tint j;\n\nprocess_func:\n\t/* protect against potential stack overflow that might happen when\n\t * bpf2bpf calls get combined with tailcalls. Limit the caller's stack\n\t * depth for such case down to 256 so that the worst case scenario\n\t * would result in 8k stack size (32 which is tailcall limit * 256 =\n\t * 8k).\n\t *\n\t * To get the idea what might happen, see an example:\n\t * func1 -> sub rsp, 128\n\t *  subfunc1 -> sub rsp, 256\n\t *  tailcall1 -> add rsp, 256\n\t *   func2 -> sub rsp, 192 (total stack size = 128 + 192 = 320)\n\t *   subfunc2 -> sub rsp, 64\n\t *   subfunc22 -> sub rsp, 128\n\t *   tailcall2 -> add rsp, 128\n\t *    func3 -> sub rsp, 32 (total stack size 128 + 192 + 64 + 32 = 416)\n\t *\n\t * tailcall will unwind the current stack frame but it will not get rid\n\t * of caller's stack as shown on the example above.\n\t */\n\tif (idx && subprog[idx].has_tail_call && depth >= 256) {\n\t\tverbose(env,\n\t\t\t\"tail_calls are not allowed when call stack of previous frames is %d bytes. Too large\\n\",\n\t\t\tdepth);\n\t\treturn -EACCES;\n\t}\n\t/* round up to 32-bytes, since this is granularity\n\t * of interpreter stack size\n\t */\n\tdepth += round_up(max_t(u32, subprog[idx].stack_depth, 1), 32);\n\tif (depth > MAX_BPF_STACK) {\n\t\tverbose(env, \"combined stack size of %d calls is %d. Too large\\n\",\n\t\t\tframe + 1, depth);\n\t\treturn -EACCES;\n\t}\ncontinue_func:\n\tsubprog_end = subprog[idx + 1].start;\n\tfor (; i < subprog_end; i++) {\n\t\tint next_insn;\n\n\t\tif (!bpf_pseudo_call(insn + i) && !bpf_pseudo_func(insn + i))\n\t\t\tcontinue;\n\t\t/* remember insn and function to return to */\n\t\tret_insn[frame] = i + 1;\n\t\tret_prog[frame] = idx;\n\n\t\t/* find the callee */\n\t\tnext_insn = i + insn[i].imm + 1;\n\t\tidx = find_subprog(env, next_insn);\n\t\tif (idx < 0) {\n\t\t\tWARN_ONCE(1, \"verifier bug. No program starts at insn %d\\n\",\n\t\t\t\t  next_insn);\n\t\t\treturn -EFAULT;\n\t\t}\n\t\tif (subprog[idx].is_async_cb) {\n\t\t\tif (subprog[idx].has_tail_call) {\n\t\t\t\tverbose(env, \"verifier bug. subprog has tail_call and async cb\\n\");\n\t\t\t\treturn -EFAULT;\n\t\t\t}\n\t\t\t /* async callbacks don't increase bpf prog stack size */\n\t\t\tcontinue;\n\t\t}\n\t\ti = next_insn;\n\n\t\tif (subprog[idx].has_tail_call)\n\t\t\ttail_call_reachable = true;\n\n\t\tframe++;\n\t\tif (frame >= MAX_CALL_FRAMES) {\n\t\t\tverbose(env, \"the call stack of %d frames is too deep !\\n\",\n\t\t\t\tframe);\n\t\t\treturn -E2BIG;\n\t\t}\n\t\tgoto process_func;\n\t}\n\t/* if tail call got detected across bpf2bpf calls then mark each of the\n\t * currently present subprog frames as tail call reachable subprogs;\n\t * this info will be utilized by JIT so that we will be preserving the\n\t * tail call counter throughout bpf2bpf calls combined with tailcalls\n\t */\n\tif (tail_call_reachable)\n\t\tfor (j = 0; j < frame; j++)\n\t\t\tsubprog[ret_prog[j]].tail_call_reachable = true;\n\tif (subprog[0].tail_call_reachable)\n\t\tenv->prog->aux->tail_call_reachable = true;\n\n\t/* end of for() loop means the last insn of the 'subprog'\n\t * was reached. Doesn't matter whether it was JA or EXIT\n\t */\n\tif (frame == 0)\n\t\treturn 0;\n\tdepth -= round_up(max_t(u32, subprog[idx].stack_depth, 1), 32);\n\tframe--;\n\ti = ret_insn[frame];\n\tidx = ret_prog[frame];\n\tgoto continue_func;\n}",
        "static void do_test_parallel_lru_loss(int task, void *data)\n{\n\tconst unsigned int nr_stable_elems = 1000;\n\tconst unsigned int nr_repeats = 100000;\n": "static void do_test_parallel_lru_loss(int task, void *data)\n{\n\tconst unsigned int nr_stable_elems = 1000;\n\tconst unsigned int nr_repeats = 100000;\n\n\tint map_fd = *(int *)data;\n\tunsigned long long stable_base;\n\tunsigned long long key, value[nr_cpus];\n\tunsigned long long next_ins_key;\n\tunsigned int nr_losses = 0;\n\tunsigned int i;\n\n\tstable_base = task * nr_repeats * 2 + 1;\n\tnext_ins_key = stable_base;\n\tvalue[0] = 1234;\n\tfor (i = 0; i < nr_stable_elems; i++) {\n\t\tassert(bpf_map_update_elem(map_fd, &next_ins_key, value,\n\t\t\t\t       BPF_NOEXIST) == 0);\n\t\tnext_ins_key++;\n\t}\n\n\tfor (i = 0; i < nr_repeats; i++) {\n\t\tint rn;\n\n\t\trn = rand();\n\n\t\tif (rn % 10) {\n\t\t\tkey = rn % nr_stable_elems + stable_base;\n\t\t\tbpf_map_lookup_elem(map_fd, &key, value);\n\t\t} else {\n\t\t\tbpf_map_update_elem(map_fd, &next_ins_key, value,\n\t\t\t\t\tBPF_NOEXIST);\n\t\t\tnext_ins_key++;\n\t\t}\n\t}\n\n\tkey = stable_base;\n\tfor (i = 0; i < nr_stable_elems; i++) {\n\t\tif (bpf_map_lookup_elem(map_fd, &key, value))\n\t\t\tnr_losses++;\n\t\tkey++;\n\t}\n\n\tprintf(\"    task:%d nr_losses:%u\\n\", task, nr_losses);\n}",
        "static bool __update_blocked_others(struct rq *rq, bool *done)\n{\n\tconst struct sched_class *curr_class;\n\tu64 now = rq_clock_pelt(rq);\n\tunsigned long thermal_pressure;": "static bool __update_blocked_others(struct rq *rq, bool *done)\n{\n\tconst struct sched_class *curr_class;\n\tu64 now = rq_clock_pelt(rq);\n\tunsigned long thermal_pressure;\n\tbool decayed;\n\n\t/*\n\t * update_load_avg() can call cpufreq_update_util(). Make sure that RT,\n\t * DL and IRQ signals have been updated before updating CFS.\n\t */\n\tcurr_class = rq->curr->sched_class;\n\n\tthermal_pressure = arch_scale_thermal_pressure(cpu_of(rq));\n\n\tdecayed = update_rt_rq_load_avg(now, rq, curr_class == &rt_sched_class) |\n\t\t  update_dl_rq_load_avg(now, rq, curr_class == &dl_sched_class) |\n\t\t  update_thermal_load_avg(rq_clock_thermal(rq), rq, thermal_pressure) |\n\t\t  update_irq_load_avg(rq, 0);\n\n\tif (others_have_blocked(rq))\n\t\t*done = false;\n\n\treturn decayed;\n}",
        "static unsigned long calibrate_delay_direct(void)\n{\n\tunsigned long pre_start, start, post_start;\n\tunsigned long pre_end, end, post_end;\n\tunsigned long start_jiffies;": "static unsigned long calibrate_delay_direct(void)\n{\n\tunsigned long pre_start, start, post_start;\n\tunsigned long pre_end, end, post_end;\n\tunsigned long start_jiffies;\n\tunsigned long timer_rate_min, timer_rate_max;\n\tunsigned long good_timer_sum = 0;\n\tunsigned long good_timer_count = 0;\n\tunsigned long measured_times[MAX_DIRECT_CALIBRATION_RETRIES];\n\tint max = -1; /* index of measured_times with max/min values or not set */\n\tint min = -1;\n\tint i;\n\n\tif (read_current_timer(&pre_start) < 0 )\n\t\treturn 0;\n\n\t/*\n\t * A simple loop like\n\t *\twhile ( jiffies < start_jiffies+1)\n\t *\t\tstart = read_current_timer();\n\t * will not do. As we don't really know whether jiffy switch\n\t * happened first or timer_value was read first. And some asynchronous\n\t * event can happen between these two events introducing errors in lpj.\n\t *\n\t * So, we do\n\t * 1. pre_start <- When we are sure that jiffy switch hasn't happened\n\t * 2. check jiffy switch\n\t * 3. start <- timer value before or after jiffy switch\n\t * 4. post_start <- When we are sure that jiffy switch has happened\n\t *\n\t * Note, we don't know anything about order of 2 and 3.\n\t * Now, by looking at post_start and pre_start difference, we can\n\t * check whether any asynchronous event happened or not\n\t */\n\n\tfor (i = 0; i < MAX_DIRECT_CALIBRATION_RETRIES; i++) {\n\t\tpre_start = 0;\n\t\tread_current_timer(&start);\n\t\tstart_jiffies = jiffies;\n\t\twhile (time_before_eq(jiffies, start_jiffies + 1)) {\n\t\t\tpre_start = start;\n\t\t\tread_current_timer(&start);\n\t\t}\n\t\tread_current_timer(&post_start);\n\n\t\tpre_end = 0;\n\t\tend = post_start;\n\t\twhile (time_before_eq(jiffies, start_jiffies + 1 +\n\t\t\t\t\t       DELAY_CALIBRATION_TICKS)) {\n\t\t\tpre_end = end;\n\t\t\tread_current_timer(&end);\n\t\t}\n\t\tread_current_timer(&post_end);\n\n\t\ttimer_rate_max = (post_end - pre_start) /\n\t\t\t\t\tDELAY_CALIBRATION_TICKS;\n\t\ttimer_rate_min = (pre_end - post_start) /\n\t\t\t\t\tDELAY_CALIBRATION_TICKS;\n\n\t\t/*\n\t\t * If the upper limit and lower limit of the timer_rate is\n\t\t * >= 12.5% apart, redo calibration.\n\t\t */\n\t\tif (start >= post_end)\n\t\t\tprintk(KERN_NOTICE \"calibrate_delay_direct() ignoring \"\n\t\t\t\t\t\"timer_rate as we had a TSC wrap around\"\n\t\t\t\t\t\" start=%lu >=post_end=%lu\\n\",\n\t\t\t\tstart, post_end);\n\t\tif (start < post_end && pre_start != 0 && pre_end != 0 &&\n\t\t    (timer_rate_max - timer_rate_min) < (timer_rate_max >> 3)) {\n\t\t\tgood_timer_count++;\n\t\t\tgood_timer_sum += timer_rate_max;\n\t\t\tmeasured_times[i] = timer_rate_max;\n\t\t\tif (max < 0 || timer_rate_max > measured_times[max])\n\t\t\t\tmax = i;\n\t\t\tif (min < 0 || timer_rate_max < measured_times[min])\n\t\t\t\tmin = i;\n\t\t} else\n\t\t\tmeasured_times[i] = 0;\n\n\t}\n\n\t/*\n\t * Find the maximum & minimum - if they differ too much throw out the\n\t * one with the largest difference from the mean and try again...\n\t */\n\twhile (good_timer_count > 1) {\n\t\tunsigned long estimate;\n\t\tunsigned long maxdiff;\n\n\t\t/* compute the estimate */\n\t\testimate = (good_timer_sum/good_timer_count);\n\t\tmaxdiff = estimate >> 3;\n\n\t\t/* if range is within 12% let's take it */\n\t\tif ((measured_times[max] - measured_times[min]) < maxdiff)\n\t\t\treturn estimate;\n\n\t\t/* ok - drop the worse value and try again... */\n\t\tgood_timer_sum = 0;\n\t\tgood_timer_count = 0;\n\t\tif ((measured_times[max] - estimate) <\n\t\t\t\t(estimate - measured_times[min])) {\n\t\t\tprintk(KERN_NOTICE \"calibrate_delay_direct() dropping \"\n\t\t\t\t\t\"min bogoMips estimate %d = %lu\\n\",\n\t\t\t\tmin, measured_times[min]);\n\t\t\tmeasured_times[min] = 0;\n\t\t\tmin = max;\n\t\t} else {\n\t\t\tprintk(KERN_NOTICE \"calibrate_delay_direct() dropping \"\n\t\t\t\t\t\"max bogoMips estimate %d = %lu\\n\",\n\t\t\t\tmax, measured_times[max]);\n\t\t\tmeasured_times[max] = 0;\n\t\t\tmax = min;\n\t\t}\n\n\t\tfor (i = 0; i < MAX_DIRECT_CALIBRATION_RETRIES; i++) {\n\t\t\tif (measured_times[i] == 0)\n\t\t\t\tcontinue;\n\t\t\tgood_timer_count++;\n\t\t\tgood_timer_sum += measured_times[i];\n\t\t\tif (measured_times[i] < measured_times[min])\n\t\t\t\tmin = i;\n\t\t\tif (measured_times[i] > measured_times[max])\n\t\t\t\tmax = i;\n\t\t}\n\n\t}\n\n\tprintk(KERN_NOTICE \"calibrate_delay_direct() failed to get a good \"\n\t       \"estimate for loops_per_jiffy.\\nProbably due to long platform \"\n\t\t\"interrupts. Consider using \\\"lpj=\\\" boot option.\\n\");\n\treturn 0;\n}",
        "static void ftrace_dump_buf(int skip_entries, long cpu_file)\n{\n\tstruct trace_array *tr;\n\tunsigned int old_userobj;\n\tint cnt = 0, cpu;": "static void ftrace_dump_buf(int skip_entries, long cpu_file)\n{\n\tstruct trace_array *tr;\n\tunsigned int old_userobj;\n\tint cnt = 0, cpu;\n\n\ttr = iter.tr;\n\n\told_userobj = tr->trace_flags;\n\n\t/* don't look at user memory in panic mode */\n\ttr->trace_flags &= ~TRACE_ITER_SYM_USEROBJ;\n\n\tkdb_printf(\"Dumping ftrace buffer:\\n\");\n\tif (skip_entries)\n\t\tkdb_printf(\"(skipping %d entries)\\n\", skip_entries);\n\n\ttrace_iterator_reset(&iter);\n\titer.iter_flags |= TRACE_FILE_LAT_FMT;\n\n\tif (cpu_file == RING_BUFFER_ALL_CPUS) {\n\t\tfor_each_tracing_cpu(cpu) {\n\t\t\titer.buffer_iter[cpu] =\n\t\t\tring_buffer_read_prepare(iter.array_buffer->buffer,\n\t\t\t\t\t\t cpu, GFP_ATOMIC);\n\t\t\tring_buffer_read_start(iter.buffer_iter[cpu]);\n\t\t\ttracing_iter_reset(&iter, cpu);\n\t\t}\n\t} else {\n\t\titer.cpu_file = cpu_file;\n\t\titer.buffer_iter[cpu_file] =\n\t\t\tring_buffer_read_prepare(iter.array_buffer->buffer,\n\t\t\t\t\t\t cpu_file, GFP_ATOMIC);\n\t\tring_buffer_read_start(iter.buffer_iter[cpu_file]);\n\t\ttracing_iter_reset(&iter, cpu_file);\n\t}\n\n\twhile (trace_find_next_entry_inc(&iter)) {\n\t\tif (!cnt)\n\t\t\tkdb_printf(\"---------------------------------\\n\");\n\t\tcnt++;\n\n\t\tif (!skip_entries) {\n\t\t\tprint_trace_line(&iter);\n\t\t\ttrace_printk_seq(&iter.seq);\n\t\t} else {\n\t\t\tskip_entries--;\n\t\t}\n\n\t\tif (KDB_FLAG(CMD_INTERRUPT))\n\t\t\tgoto out;\n\t}\n\n\tif (!cnt)\n\t\tkdb_printf(\"   (ftrace buffer empty)\\n\");\n\telse\n\t\tkdb_printf(\"---------------------------------\\n\");\n\nout:\n\ttr->trace_flags = old_userobj;\n\n\tfor_each_tracing_cpu(cpu) {\n\t\tif (iter.buffer_iter[cpu]) {\n\t\t\tring_buffer_read_finish(iter.buffer_iter[cpu]);\n\t\t\titer.buffer_iter[cpu] = NULL;\n\t\t}\n\t}\n}",
        "static int pfkey_spdget(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tunsigned int dir;\n\tint err = 0, delete;": "static int pfkey_spdget(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tunsigned int dir;\n\tint err = 0, delete;\n\tstruct sadb_x_policy *pol;\n\tstruct xfrm_policy *xp;\n\tstruct km_event c;\n\n\tif ((pol = ext_hdrs[SADB_X_EXT_POLICY-1]) == NULL)\n\t\treturn -EINVAL;\n\n\tdir = xfrm_policy_id2dir(pol->sadb_x_policy_id);\n\tif (dir >= XFRM_POLICY_MAX)\n\t\treturn -EINVAL;\n\n\tdelete = (hdr->sadb_msg_type == SADB_X_SPDDELETE2);\n\txp = xfrm_policy_byid(net, &dummy_mark, 0, XFRM_POLICY_TYPE_MAIN,\n\t\t\t      dir, pol->sadb_x_policy_id, delete, &err);\n\tif (xp == NULL)\n\t\treturn -ENOENT;\n\n\tif (delete) {\n\t\txfrm_audit_policy_delete(xp, err ? 0 : 1, true);\n\n\t\tif (err)\n\t\t\tgoto out;\n\t\tc.seq = hdr->sadb_msg_seq;\n\t\tc.portid = hdr->sadb_msg_pid;\n\t\tc.data.byid = 1;\n\t\tc.event = XFRM_MSG_DELPOLICY;\n\t\tkm_policy_notify(xp, dir, &c);\n\t} else {\n\t\terr = key_pol_get_resp(sk, xp, hdr, dir);\n\t}\n\nout:\n\txfrm_pol_put(xp);\n\treturn err;\n}",
        "static int tw5864_enable_input(struct tw5864_input *input)\n{\n\tstruct tw5864_dev *dev = input->root;\n\tint nr = input->nr;\n\tunsigned long flags;": "static int tw5864_enable_input(struct tw5864_input *input)\n{\n\tstruct tw5864_dev *dev = input->root;\n\tint nr = input->nr;\n\tunsigned long flags;\n\tint d1_width = 720;\n\tint d1_height;\n\tint frame_width_bus_value = 0;\n\tint frame_height_bus_value = 0;\n\tint reg_frame_bus = 0x1c;\n\tint fmt_reg_value = 0;\n\tint downscale_enabled = 0;\n\n\tdev_dbg(&dev->pci->dev, \"Enabling channel %d\\n\", nr);\n\n\tinput->frame_seqno = 0;\n\tinput->frame_gop_seqno = 0;\n\tinput->h264_idr_pic_id = 0;\n\n\tinput->reg_dsp_qp = input->qp;\n\tinput->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];\n\tinput->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];\n\tinput->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST\n\t\t| TW5864_EMU_EN_SEN | TW5864_EMU_EN_ME | TW5864_EMU_EN_DDR;\n\tinput->reg_dsp = nr /* channel id */\n\t\t| TW5864_DSP_CHROM_SW\n\t\t| ((0xa << 8) & TW5864_DSP_MB_DELAY)\n\t\t;\n\n\tinput->resolution = D1;\n\n\td1_height = (input->std == STD_NTSC) ? 480 : 576;\n\n\tinput->width = d1_width;\n\tinput->height = d1_height;\n\n\tinput->reg_interlacing = 0x4;\n\n\tswitch (input->resolution) {\n\tcase D1:\n\t\tframe_width_bus_value = 0x2cf;\n\t\tframe_height_bus_value = input->height - 1;\n\t\treg_frame_bus = 0x1c;\n\t\tfmt_reg_value = 0;\n\t\tdownscale_enabled = 0;\n\t\tinput->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD;\n\t\tinput->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;\n\t\tinput->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST;\n\n\t\ttw_setl(TW5864_FULL_HALF_FLAG, 1 << nr);\n\t\tbreak;\n\tcase HD1:\n\t\tinput->height /= 2;\n\t\tinput->width /= 2;\n\t\tframe_width_bus_value = 0x2cf;\n\t\tframe_height_bus_value = input->height * 2 - 1;\n\t\treg_frame_bus = 0x1c;\n\t\tfmt_reg_value = 0;\n\t\tdownscale_enabled = 0;\n\t\tinput->reg_dsp_codec |= TW5864_HD1_MAP_MD;\n\t\tinput->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;\n\n\t\ttw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);\n\n\t\tbreak;\n\tcase CIF:\n\t\tinput->height /= 4;\n\t\tinput->width /= 2;\n\t\tframe_width_bus_value = 0x15f;\n\t\tframe_height_bus_value = input->height * 2 - 1;\n\t\treg_frame_bus = 0x07;\n\t\tfmt_reg_value = 1;\n\t\tdownscale_enabled = 1;\n\t\tinput->reg_dsp_codec |= TW5864_CIF_MAP_MD;\n\n\t\ttw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);\n\t\tbreak;\n\tcase QCIF:\n\t\tinput->height /= 4;\n\t\tinput->width /= 4;\n\t\tframe_width_bus_value = 0x15f;\n\t\tframe_height_bus_value = input->height * 2 - 1;\n\t\treg_frame_bus = 0x07;\n\t\tfmt_reg_value = 1;\n\t\tdownscale_enabled = 1;\n\t\tinput->reg_dsp_codec |= TW5864_CIF_MAP_MD;\n\n\t\ttw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);\n\t\tbreak;\n\t}\n\n\t/* analog input width / 4 */\n\ttw_indir_writeb(TW5864_INDIR_IN_PIC_WIDTH(nr), d1_width / 4);\n\ttw_indir_writeb(TW5864_INDIR_IN_PIC_HEIGHT(nr), d1_height / 4);\n\n\t/* output width / 4 */\n\ttw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4);\n\ttw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4);\n\n\t/*\n\t * Crop width from 720 to 704.\n\t * Above register settings need value 720 involved.\n\t */\n\tinput->width = 704;\n\ttw_indir_writeb(TW5864_INDIR_CROP_ETC,\n\t\t\ttw_indir_readb(TW5864_INDIR_CROP_ETC) |\n\t\t\tTW5864_INDIR_CROP_ETC_CROP_EN);\n\n\ttw_writel(TW5864_DSP_PIC_MAX_MB,\n\t\t  ((input->width / 16) << 8) | (input->height / 16));\n\n\ttw_writel(TW5864_FRAME_WIDTH_BUS_A(nr),\n\t\t  frame_width_bus_value);\n\ttw_writel(TW5864_FRAME_WIDTH_BUS_B(nr),\n\t\t  frame_width_bus_value);\n\ttw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr),\n\t\t  frame_height_bus_value);\n\ttw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr),\n\t\t  (frame_height_bus_value + 1) / 2 - 1);\n\n\ttw5864_frame_interval_set(input);\n\n\tif (downscale_enabled)\n\t\ttw_setl(TW5864_H264EN_CH_DNS, 1 << nr);\n\n\ttw_mask_shift_writel(TW5864_H264EN_CH_FMT_REG1, 0x3, 2 * nr,\n\t\t\t     fmt_reg_value);\n\n\ttw_mask_shift_writel((nr < 2\n\t\t\t      ? TW5864_H264EN_RATE_MAX_LINE_REG1\n\t\t\t      : TW5864_H264EN_RATE_MAX_LINE_REG2),\n\t\t\t     0x1f, 5 * (nr % 2),\n\t\t\t     input->std == STD_NTSC ? 29 : 24);\n\n\ttw_mask_shift_writel((nr < 2) ? TW5864_FRAME_BUS1 :\n\t\t\t     TW5864_FRAME_BUS2, 0xff, (nr % 2) * 8,\n\t\t\t     reg_frame_bus);\n\n\tspin_lock_irqsave(&dev->slock, flags);\n\tinput->enabled = 1;\n\tspin_unlock_irqrestore(&dev->slock, flags);\n\n\treturn 0;\n}",
        "static int test7_rw_aligned_14963bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t  ((start_addr[range_count - 1] + 0xF000) & ~(ADI_BLKSZ - 1)) + 39;": "static int test7_rw_aligned_14963bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t  ((start_addr[range_count - 1] + 0xF000) & ~(ADI_BLKSZ - 1)) + 39;\n\tunsigned char version[TEST7_VERSION_SZ],\n\t\t      expected_version[TEST7_VERSION_SZ];\n\tloff_t offset;\n\toff_t oret;\n\tint ret, i;\n\n\toffset = paddr / ADI_BLKSZ;\n\tfor (i = 0; i < TEST7_VERSION_SZ; i++) {\n\t\tversion[i] = random_version();\n\t\texpected_version[i] = version[i];\n\t}\n\n\toret = seek_adi(fd, offset, SEEK_SET);\n\tif (oret != offset) {\n\t\tret = -1;\n\t\tTEST_STEP_FAILURE(ret);\n\t}\n\n\tret = write_adi(fd, version, sizeof(version));\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tmemset(version, 0, TEST7_VERSION_SZ);\n\n\toret = seek_adi(fd, offset, SEEK_SET);\n\tif (oret != offset) {\n\t\tret = -1;\n\t\tTEST_STEP_FAILURE(ret);\n\t}\n\n\tret = read_adi(fd, version, sizeof(version));\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tfor (i = 0; i < TEST7_VERSION_SZ; i++) {\n\t\tif (expected_version[i] != version[i]) {\n\t\t\tDEBUG_PRINT_L2(\n\t\t\t\t\"\\tExpected version %d but read version %d\\n\",\n\t\t\t\texpected_version[i], version[i]);\n\t\t\tTEST_STEP_FAILURE(-expected_version[i]);\n\t\t}\n\n\t\tpaddr += ADI_BLKSZ;\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc)\n{\n\tstruct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);\n\tu32 p; /* panic code */\n\tint ret;": "static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc)\n{\n\tstruct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);\n\tu32 p; /* panic code */\n\tint ret;\n\n\t/* Read the message from the debug box. */\n\tsof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,\n\t\t\t &p, sizeof(p));\n\n\t/* Check to see if the message is a panic code 0x0dead*** */\n\tif ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {\n\t\tsnd_sof_dsp_panic(priv->sdev, p, true);\n\t} else {\n\t\tsnd_sof_ipc_msgs_rx(priv->sdev);\n\n\t\t/* tell DSP cmd is done */\n\t\tret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);\n\t\tif (ret)\n\t\t\tdev_err(priv->dev, \"request send ipc failed\");\n\t}\n}",
        "static int finalize_btf_ext(struct bpf_linker *linker)\n{\n\tsize_t funcs_sz = 0, lines_sz = 0, core_relos_sz = 0, total_sz = 0;\n\tsize_t func_rec_sz = 0, line_rec_sz = 0, core_relo_rec_sz = 0;\n\tstruct btf_ext_header *hdr;": "static int finalize_btf_ext(struct bpf_linker *linker)\n{\n\tsize_t funcs_sz = 0, lines_sz = 0, core_relos_sz = 0, total_sz = 0;\n\tsize_t func_rec_sz = 0, line_rec_sz = 0, core_relo_rec_sz = 0;\n\tstruct btf_ext_header *hdr;\n\tvoid *data, *cur;\n\tint i, err, sz;\n\n\t/* validate that all sections have the same .BTF.ext record sizes\n\t * and calculate total data size for each type of data (func info,\n\t * line info, core relos)\n\t */\n\tfor (i = 1; i < linker->sec_cnt; i++) {\n\t\tstruct dst_sec *sec = &linker->secs[i];\n\n\t\tif (sec->func_info.rec_cnt) {\n\t\t\tif (func_rec_sz == 0)\n\t\t\t\tfunc_rec_sz = sec->func_info.rec_sz;\n\t\t\tif (func_rec_sz != sec->func_info.rec_sz) {\n\t\t\t\tpr_warn(\"mismatch in func_info record size %zu != %u\\n\",\n\t\t\t\t\tfunc_rec_sz, sec->func_info.rec_sz);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tfuncs_sz += sizeof(struct btf_ext_info_sec) + func_rec_sz * sec->func_info.rec_cnt;\n\t\t}\n\t\tif (sec->line_info.rec_cnt) {\n\t\t\tif (line_rec_sz == 0)\n\t\t\t\tline_rec_sz = sec->line_info.rec_sz;\n\t\t\tif (line_rec_sz != sec->line_info.rec_sz) {\n\t\t\t\tpr_warn(\"mismatch in line_info record size %zu != %u\\n\",\n\t\t\t\t\tline_rec_sz, sec->line_info.rec_sz);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tlines_sz += sizeof(struct btf_ext_info_sec) + line_rec_sz * sec->line_info.rec_cnt;\n\t\t}\n\t\tif (sec->core_relo_info.rec_cnt) {\n\t\t\tif (core_relo_rec_sz == 0)\n\t\t\t\tcore_relo_rec_sz = sec->core_relo_info.rec_sz;\n\t\t\tif (core_relo_rec_sz != sec->core_relo_info.rec_sz) {\n\t\t\t\tpr_warn(\"mismatch in core_relo_info record size %zu != %u\\n\",\n\t\t\t\t\tcore_relo_rec_sz, sec->core_relo_info.rec_sz);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tcore_relos_sz += sizeof(struct btf_ext_info_sec) + core_relo_rec_sz * sec->core_relo_info.rec_cnt;\n\t\t}\n\t}\n\n\tif (!funcs_sz && !lines_sz && !core_relos_sz)\n\t\treturn 0;\n\n\ttotal_sz += sizeof(struct btf_ext_header);\n\tif (funcs_sz) {\n\t\tfuncs_sz += sizeof(__u32); /* record size prefix */\n\t\ttotal_sz += funcs_sz;\n\t}\n\tif (lines_sz) {\n\t\tlines_sz += sizeof(__u32); /* record size prefix */\n\t\ttotal_sz += lines_sz;\n\t}\n\tif (core_relos_sz) {\n\t\tcore_relos_sz += sizeof(__u32); /* record size prefix */\n\t\ttotal_sz += core_relos_sz;\n\t}\n\n\tcur = data = calloc(1, total_sz);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\thdr = cur;\n\thdr->magic = BTF_MAGIC;\n\thdr->version = BTF_VERSION;\n\thdr->flags = 0;\n\thdr->hdr_len = sizeof(struct btf_ext_header);\n\tcur += sizeof(struct btf_ext_header);\n\n\t/* All offsets are in bytes relative to the end of this header */\n\thdr->func_info_off = 0;\n\thdr->func_info_len = funcs_sz;\n\thdr->line_info_off = funcs_sz;\n\thdr->line_info_len = lines_sz;\n\thdr->core_relo_off = funcs_sz + lines_sz;\n\thdr->core_relo_len = core_relos_sz;\n\n\tif (funcs_sz) {\n\t\t*(__u32 *)cur = func_rec_sz;\n\t\tcur += sizeof(__u32);\n\n\t\tfor (i = 1; i < linker->sec_cnt; i++) {\n\t\t\tstruct dst_sec *sec = &linker->secs[i];\n\n\t\t\tsz = emit_btf_ext_data(linker, cur, sec->sec_name, &sec->func_info);\n\t\t\tif (sz < 0) {\n\t\t\t\terr = sz;\n\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\tcur += sz;\n\t\t}\n\t}\n\n\tif (lines_sz) {\n\t\t*(__u32 *)cur = line_rec_sz;\n\t\tcur += sizeof(__u32);\n\n\t\tfor (i = 1; i < linker->sec_cnt; i++) {\n\t\t\tstruct dst_sec *sec = &linker->secs[i];\n\n\t\t\tsz = emit_btf_ext_data(linker, cur, sec->sec_name, &sec->line_info);\n\t\t\tif (sz < 0) {\n\t\t\t\terr = sz;\n\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\tcur += sz;\n\t\t}\n\t}\n\n\tif (core_relos_sz) {\n\t\t*(__u32 *)cur = core_relo_rec_sz;\n\t\tcur += sizeof(__u32);\n\n\t\tfor (i = 1; i < linker->sec_cnt; i++) {\n\t\t\tstruct dst_sec *sec = &linker->secs[i];\n\n\t\t\tsz = emit_btf_ext_data(linker, cur, sec->sec_name, &sec->core_relo_info);\n\t\t\tif (sz < 0) {\n\t\t\t\terr = sz;\n\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\tcur += sz;\n\t\t}\n\t}\n\n\tlinker->btf_ext = btf_ext__new(data, total_sz);\n\terr = libbpf_get_error(linker->btf_ext);\n\tif (err) {\n\t\tlinker->btf_ext = NULL;\n\t\tpr_warn(\"failed to parse final .BTF.ext data: %d\\n\", err);\n\t\tgoto out;\n\t}\n\nout:\n\tfree(data);\n\treturn err;\n}",
        "static void halter_guest_code(struct test_data_page *data)\n{\n\tverify_apic_base_addr();\n\txapic_enable();\n": "static void halter_guest_code(struct test_data_page *data)\n{\n\tverify_apic_base_addr();\n\txapic_enable();\n\n\tdata->halter_apic_id = GET_APIC_ID_FIELD(xapic_read_reg(APIC_ID));\n\tdata->halter_lvr = xapic_read_reg(APIC_LVR);\n\n\t/*\n\t * Loop forever HLTing and recording halts & wakes. Disable interrupts\n\t * each time around to minimize window between signaling the pending\n\t * halt to the sender vCPU and executing the halt. No need to disable on\n\t * first run as this vCPU executes first and the host waits for it to\n\t * signal going into first halt before starting the sender vCPU. Record\n\t * TPR and PPR for diagnostic purposes in case the test fails.\n\t */\n\tfor (;;) {\n\t\tdata->halter_tpr = xapic_read_reg(APIC_TASKPRI);\n\t\tdata->halter_ppr = xapic_read_reg(APIC_PROCPRI);\n\t\tdata->hlt_count++;\n\t\tasm volatile(\"sti; hlt; cli\");\n\t\tdata->wake_count++;\n\t}\n}",
        "static void macii_queue_poll(void)\n{\n\tstatic struct adb_request req;\n\tunsigned char poll_command;\n\tunsigned int poll_addr;": "static void macii_queue_poll(void)\n{\n\tstatic struct adb_request req;\n\tunsigned char poll_command;\n\tunsigned int poll_addr;\n\n\t/* This only polls devices in the autopoll list, which assumes that\n\t * unprobed devices never assert SRQ. That could happen if a device was\n\t * plugged in after the adb bus scan. Unplugging it again will resolve\n\t * the problem. This behaviour is similar to MacOS.\n\t */\n\tif (!autopoll_devs)\n\t\treturn;\n\n\t/* The device most recently polled may not be the best device to poll\n\t * right now. Some other device(s) may have signalled SRQ (the active\n\t * device won't do that). Or the autopoll list may have been changed.\n\t * Try polling the next higher address.\n\t */\n\tpoll_addr = (last_poll_cmd & ADDR_MASK) >> 4;\n\tif ((srq_asserted && last_cmd == last_poll_cmd) ||\n\t    !(autopoll_devs & (1 << poll_addr))) {\n\t\tunsigned int higher_devs;\n\n\t\thigher_devs = autopoll_devs & -(1 << (poll_addr + 1));\n\t\tpoll_addr = ffs(higher_devs ? higher_devs : autopoll_devs) - 1;\n\t}\n\n\t/* Send a Talk Register 0 command */\n\tpoll_command = ADB_READREG(poll_addr, 0);\n\n\t/* No need to repeat this Talk command. The transceiver will do that\n\t * as long as it is idle.\n\t */\n\tif (poll_command == last_cmd)\n\t\treturn;\n\n\tadb_request(&req, NULL, ADBREQ_NOSEND, 1, poll_command);\n\n\treq.sent = 0;\n\treq.complete = 0;\n\treq.reply_len = 0;\n\treq.next = current_req;\n\n\tif (WARN_ON(current_req)) {\n\t\tcurrent_req = &req;\n\t} else {\n\t\tcurrent_req = &req;\n\t\tlast_req = &req;\n\t}\n}",
        "static int dr_dump_rule(struct seq_file *file, struct mlx5dr_rule *rule)\n{\n\tstruct mlx5dr_rule_action_member *action_mem;\n\tconst u64 rule_id = DR_DBG_PTR_TO_ID(rule);\n\tstruct mlx5dr_rule_rx_tx *rx = &rule->rx;": "static int dr_dump_rule(struct seq_file *file, struct mlx5dr_rule *rule)\n{\n\tstruct mlx5dr_rule_action_member *action_mem;\n\tconst u64 rule_id = DR_DBG_PTR_TO_ID(rule);\n\tstruct mlx5dr_rule_rx_tx *rx = &rule->rx;\n\tstruct mlx5dr_rule_rx_tx *tx = &rule->tx;\n\tu8 format_ver;\n\tint ret;\n\n\tformat_ver = rule->matcher->tbl->dmn->info.caps.sw_format_ver;\n\n\tseq_printf(file, \"%d,0x%llx,0x%llx\\n\", DR_DUMP_REC_TYPE_RULE, rule_id,\n\t\t   DR_DBG_PTR_TO_ID(rule->matcher));\n\n\tif (rx->nic_matcher) {\n\t\tret = dr_dump_rule_rx_tx(file, rx, true, rule_id, format_ver);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\tif (tx->nic_matcher) {\n\t\tret = dr_dump_rule_rx_tx(file, tx, false, rule_id, format_ver);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\tlist_for_each_entry(action_mem, &rule->rule_actions_list, list) {\n\t\tret = dr_dump_rule_action_mem(file, rule_id, action_mem);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}",
        "static int netns_setup_links_and_routes(struct netns_setup_result *result)\n{\n\tstruct nstoken *nstoken = NULL;\n\tchar veth_src_fwd_addr[IFADDR_STR_LEN+1] = {};\n": "static int netns_setup_links_and_routes(struct netns_setup_result *result)\n{\n\tstruct nstoken *nstoken = NULL;\n\tchar veth_src_fwd_addr[IFADDR_STR_LEN+1] = {};\n\n\tSYS(\"ip link add veth_src type veth peer name veth_src_fwd\");\n\tSYS(\"ip link add veth_dst type veth peer name veth_dst_fwd\");\n\n\tSYS(\"ip link set veth_dst_fwd address \" MAC_DST_FWD);\n\tSYS(\"ip link set veth_dst address \" MAC_DST);\n\n\tif (get_ifaddr(\"veth_src_fwd\", veth_src_fwd_addr))\n\t\tgoto fail;\n\n\tresult->ifindex_veth_src_fwd = get_ifindex(\"veth_src_fwd\");\n\tif (result->ifindex_veth_src_fwd < 0)\n\t\tgoto fail;\n\tresult->ifindex_veth_dst_fwd = get_ifindex(\"veth_dst_fwd\");\n\tif (result->ifindex_veth_dst_fwd < 0)\n\t\tgoto fail;\n\n\tSYS(\"ip link set veth_src netns \" NS_SRC);\n\tSYS(\"ip link set veth_src_fwd netns \" NS_FWD);\n\tSYS(\"ip link set veth_dst_fwd netns \" NS_FWD);\n\tSYS(\"ip link set veth_dst netns \" NS_DST);\n\n\t/** setup in 'src' namespace */\n\tnstoken = open_netns(NS_SRC);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns src\"))\n\t\tgoto fail;\n\n\tSYS(\"ip addr add \" IP4_SRC \"/32 dev veth_src\");\n\tSYS(\"ip addr add \" IP6_SRC \"/128 dev veth_src nodad\");\n\tSYS(\"ip link set dev veth_src up\");\n\n\tSYS(\"ip route add \" IP4_DST \"/32 dev veth_src scope global\");\n\tSYS(\"ip route add \" IP4_NET \"/16 dev veth_src scope global\");\n\tSYS(\"ip route add \" IP6_DST \"/128 dev veth_src scope global\");\n\n\tSYS(\"ip neigh add \" IP4_DST \" dev veth_src lladdr %s\",\n\t    veth_src_fwd_addr);\n\tSYS(\"ip neigh add \" IP6_DST \" dev veth_src lladdr %s\",\n\t    veth_src_fwd_addr);\n\n\tclose_netns(nstoken);\n\n\t/** setup in 'fwd' namespace */\n\tnstoken = open_netns(NS_FWD);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns fwd\"))\n\t\tgoto fail;\n\n\t/* The fwd netns automatically gets a v6 LL address / routes, but also\n\t * needs v4 one in order to start ARP probing. IP4_NET route is added\n\t * to the endpoints so that the ARP processing will reply.\n\t */\n\tSYS(\"ip addr add \" IP4_SLL \"/32 dev veth_src_fwd\");\n\tSYS(\"ip addr add \" IP4_DLL \"/32 dev veth_dst_fwd\");\n\tSYS(\"ip link set dev veth_src_fwd up\");\n\tSYS(\"ip link set dev veth_dst_fwd up\");\n\n\tSYS(\"ip route add \" IP4_SRC \"/32 dev veth_src_fwd scope global\");\n\tSYS(\"ip route add \" IP6_SRC \"/128 dev veth_src_fwd scope global\");\n\tSYS(\"ip route add \" IP4_DST \"/32 dev veth_dst_fwd scope global\");\n\tSYS(\"ip route add \" IP6_DST \"/128 dev veth_dst_fwd scope global\");\n\n\tclose_netns(nstoken);\n\n\t/** setup in 'dst' namespace */\n\tnstoken = open_netns(NS_DST);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns dst\"))\n\t\tgoto fail;\n\n\tSYS(\"ip addr add \" IP4_DST \"/32 dev veth_dst\");\n\tSYS(\"ip addr add \" IP6_DST \"/128 dev veth_dst nodad\");\n\tSYS(\"ip link set dev veth_dst up\");\n\n\tSYS(\"ip route add \" IP4_SRC \"/32 dev veth_dst scope global\");\n\tSYS(\"ip route add \" IP4_NET \"/16 dev veth_dst scope global\");\n\tSYS(\"ip route add \" IP6_SRC \"/128 dev veth_dst scope global\");\n\n\tSYS(\"ip neigh add \" IP4_SRC \" dev veth_dst lladdr \" MAC_DST_FWD);\n\tSYS(\"ip neigh add \" IP6_SRC \" dev veth_dst lladdr \" MAC_DST_FWD);\n\n\tclose_netns(nstoken);\n\n\treturn 0;\nfail:\n\tif (nstoken)\n\t\tclose_netns(nstoken);\n\treturn -1;\n}",
        "static void ssh_rtl_timeout_reap(struct work_struct *work)\n{\n\tstruct ssh_rtl *rtl = to_ssh_rtl(work, rtx_timeout.reaper.work);\n\tstruct ssh_request *r, *n;\n\tLIST_HEAD(claimed);": "static void ssh_rtl_timeout_reap(struct work_struct *work)\n{\n\tstruct ssh_rtl *rtl = to_ssh_rtl(work, rtx_timeout.reaper.work);\n\tstruct ssh_request *r, *n;\n\tLIST_HEAD(claimed);\n\tktime_t now = ktime_get_coarse_boottime();\n\tktime_t timeout = rtl->rtx_timeout.timeout;\n\tktime_t next = KTIME_MAX;\n\n\ttrace_ssam_rtl_timeout_reap(atomic_read(&rtl->pending.count));\n\n\t/*\n\t * Mark reaper as \"not pending\". This is done before checking any\n\t * requests to avoid lost-update type problems.\n\t */\n\tspin_lock(&rtl->rtx_timeout.lock);\n\trtl->rtx_timeout.expires = KTIME_MAX;\n\tspin_unlock(&rtl->rtx_timeout.lock);\n\n\tspin_lock(&rtl->pending.lock);\n\tlist_for_each_entry_safe(r, n, &rtl->pending.head, node) {\n\t\tktime_t expires = ssh_request_get_expiration(r, timeout);\n\n\t\t/*\n\t\t * Check if the timeout hasn't expired yet. Find out next\n\t\t * expiration date to be handled after this run.\n\t\t */\n\t\tif (ktime_after(expires, now)) {\n\t\t\tnext = ktime_before(expires, next) ? expires : next;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Avoid further transitions if locked. */\n\t\tif (test_and_set_bit(SSH_REQUEST_SF_LOCKED_BIT, &r->state))\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * We have now marked the packet as locked. Thus it cannot be\n\t\t * added to the pending or queued lists again after we've\n\t\t * removed it here. We can therefore re-use the node of this\n\t\t * packet temporarily.\n\t\t */\n\n\t\tclear_bit(SSH_REQUEST_SF_PENDING_BIT, &r->state);\n\n\t\tatomic_dec(&rtl->pending.count);\n\t\tlist_move_tail(&r->node, &claimed);\n\t}\n\tspin_unlock(&rtl->pending.lock);\n\n\t/* Cancel and complete the request. */\n\tlist_for_each_entry_safe(r, n, &claimed, node) {\n\t\ttrace_ssam_request_timeout(r);\n\n\t\t/*\n\t\t * At this point we've removed the packet from pending. This\n\t\t * means that we've obtained the last (only) reference of the\n\t\t * system to it. Thus we can just complete it.\n\t\t */\n\t\tif (!test_and_set_bit(SSH_REQUEST_SF_COMPLETED_BIT, &r->state))\n\t\t\tssh_rtl_complete_with_status(r, -ETIMEDOUT);\n\n\t\t/*\n\t\t * Drop the reference we've obtained by removing it from the\n\t\t * pending set.\n\t\t */\n\t\tlist_del(&r->node);\n\t\tssh_request_put(r);\n\t}\n\n\t/* Ensure that the reaper doesn't run again immediately. */\n\tnext = max(next, ktime_add(now, SSH_RTL_REQUEST_TIMEOUT_RESOLUTION));\n\tif (next != KTIME_MAX)\n\t\tssh_rtl_timeout_reaper_mod(rtl, now, next);\n\n\tssh_rtl_tx_schedule(rtl);\n}",
        "static void set_ov_sensor_window(struct sd *sd)\n{\n\tstruct gspca_dev *gspca_dev;\n\tint qvga, crop;\n\tint hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;": "static void set_ov_sensor_window(struct sd *sd)\n{\n\tstruct gspca_dev *gspca_dev;\n\tint qvga, crop;\n\tint hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;\n\n\t/* mode setup is fully handled in mode_init_ov_sensor_regs for these */\n\tswitch (sd->sensor) {\n\tcase SEN_OV2610:\n\tcase SEN_OV2610AE:\n\tcase SEN_OV3610:\n\tcase SEN_OV7670:\n\tcase SEN_OV9600:\n\t\tmode_init_ov_sensor_regs(sd);\n\t\treturn;\n\tcase SEN_OV7660:\n\t\tov519_set_mode(sd);\n\t\tov519_set_fr(sd);\n\t\treturn;\n\t}\n\n\tgspca_dev = &sd->gspca_dev;\n\tqvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;\n\tcrop = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 2;\n\n\t/* The different sensor ICs handle setting up of window differently.\n\t * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */\n\tswitch (sd->sensor) {\n\tcase SEN_OV8610:\n\t\thwsbase = 0x1e;\n\t\thwebase = 0x1e;\n\t\tvwsbase = 0x02;\n\t\tvwebase = 0x02;\n\t\tbreak;\n\tcase SEN_OV7610:\n\tcase SEN_OV76BE:\n\t\thwsbase = 0x38;\n\t\thwebase = 0x3a;\n\t\tvwsbase = vwebase = 0x05;\n\t\tbreak;\n\tcase SEN_OV6620:\n\tcase SEN_OV6630:\n\tcase SEN_OV66308AF:\n\t\thwsbase = 0x38;\n\t\thwebase = 0x3a;\n\t\tvwsbase = 0x05;\n\t\tvwebase = 0x06;\n\t\tif (sd->sensor == SEN_OV66308AF && qvga)\n\t\t\t/* HDG: this fixes U and V getting swapped */\n\t\t\thwsbase++;\n\t\tif (crop) {\n\t\t\thwsbase += 8;\n\t\t\thwebase += 8;\n\t\t\tvwsbase += 11;\n\t\t\tvwebase += 11;\n\t\t}\n\t\tbreak;\n\tcase SEN_OV7620:\n\tcase SEN_OV7620AE:\n\t\thwsbase = 0x2f;\t\t/* From 7620.SET (spec is wrong) */\n\t\thwebase = 0x2f;\n\t\tvwsbase = vwebase = 0x05;\n\t\tbreak;\n\tcase SEN_OV7640:\n\tcase SEN_OV7648:\n\t\thwsbase = 0x1a;\n\t\thwebase = 0x1a;\n\t\tvwsbase = vwebase = 0x03;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tswitch (sd->sensor) {\n\tcase SEN_OV6620:\n\tcase SEN_OV6630:\n\tcase SEN_OV66308AF:\n\t\tif (qvga) {\t\t/* QCIF */\n\t\t\thwscale = 0;\n\t\t\tvwscale = 0;\n\t\t} else {\t\t/* CIF */\n\t\t\thwscale = 1;\n\t\t\tvwscale = 1;\t/* The datasheet says 0;\n\t\t\t\t\t * it's wrong */\n\t\t}\n\t\tbreak;\n\tcase SEN_OV8610:\n\t\tif (qvga) {\t\t/* QSVGA */\n\t\t\thwscale = 1;\n\t\t\tvwscale = 1;\n\t\t} else {\t\t/* SVGA */\n\t\t\thwscale = 2;\n\t\t\tvwscale = 2;\n\t\t}\n\t\tbreak;\n\tdefault:\t\t\t/* SEN_OV7xx0 */\n\t\tif (qvga) {\t\t/* QVGA */\n\t\t\thwscale = 1;\n\t\t\tvwscale = 0;\n\t\t} else {\t\t/* VGA */\n\t\t\thwscale = 2;\n\t\t\tvwscale = 1;\n\t\t}\n\t}\n\n\tmode_init_ov_sensor_regs(sd);\n\n\ti2c_w(sd, 0x17, hwsbase);\n\ti2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));\n\ti2c_w(sd, 0x19, vwsbase);\n\ti2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));\n}",
        "static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)\n{\n\tstruct v4l2_queryctrl qctrl = {};\n\tstruct pvr2_ctl_info *info;\n\tqctrl.id = cptr->info->v4l_id;": "static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)\n{\n\tstruct v4l2_queryctrl qctrl = {};\n\tstruct pvr2_ctl_info *info;\n\tqctrl.id = cptr->info->v4l_id;\n\tcx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);\n\t/* Strip out the const so we can adjust a function pointer.  It's\n\t   OK to do this here because we know this is a dynamically created\n\t   control, so the underlying storage for the info pointer is (a)\n\t   private to us, and (b) not in read-only storage.  Either we do\n\t   this or we significantly complicate the underlying control\n\t   implementation. */\n\tinfo = (struct pvr2_ctl_info *)(cptr->info);\n\tif (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {\n\t\tif (info->set_value) {\n\t\t\tinfo->set_value = NULL;\n\t\t}\n\t} else {\n\t\tif (!(info->set_value)) {\n\t\t\tinfo->set_value = ctrl_cx2341x_set;\n\t\t}\n\t}\n\treturn qctrl.flags;\n}",
        "static int rcu_torture_boost(void *arg)\n{\n\tunsigned long endtime;\n\tunsigned long gp_state;\n\tunsigned long gp_state_time;": "static int rcu_torture_boost(void *arg)\n{\n\tunsigned long endtime;\n\tunsigned long gp_state;\n\tunsigned long gp_state_time;\n\tunsigned long oldstarttime;\n\n\tVERBOSE_TOROUT_STRING(\"rcu_torture_boost started\");\n\n\t/* Set real-time priority. */\n\tsched_set_fifo_low(current);\n\n\t/* Each pass through the following loop does one boost-test cycle. */\n\tdo {\n\t\tbool failed = false; // Test failed already in this test interval\n\t\tbool gp_initiated = false;\n\n\t\tif (kthread_should_stop())\n\t\t\tgoto checkwait;\n\n\t\t/* Wait for the next test interval. */\n\t\toldstarttime = READ_ONCE(boost_starttime);\n\t\twhile (time_before(jiffies, oldstarttime)) {\n\t\t\tschedule_timeout_interruptible(oldstarttime - jiffies);\n\t\t\tif (stutter_wait(\"rcu_torture_boost\"))\n\t\t\t\tsched_set_fifo_low(current);\n\t\t\tif (torture_must_stop())\n\t\t\t\tgoto checkwait;\n\t\t}\n\n\t\t// Do one boost-test interval.\n\t\tendtime = oldstarttime + test_boost_duration * HZ;\n\t\twhile (time_before(jiffies, endtime)) {\n\t\t\t// Has current GP gone too long?\n\t\t\tif (gp_initiated && !failed && !cur_ops->poll_gp_state(gp_state))\n\t\t\t\tfailed = rcu_torture_boost_failed(gp_state, &gp_state_time);\n\t\t\t// If we don't have a grace period in flight, start one.\n\t\t\tif (!gp_initiated || cur_ops->poll_gp_state(gp_state)) {\n\t\t\t\tgp_state = cur_ops->start_gp_poll();\n\t\t\t\tgp_initiated = true;\n\t\t\t\tgp_state_time = jiffies;\n\t\t\t}\n\t\t\tif (stutter_wait(\"rcu_torture_boost\")) {\n\t\t\t\tsched_set_fifo_low(current);\n\t\t\t\t// If the grace period already ended,\n\t\t\t\t// we don't know when that happened, so\n\t\t\t\t// start over.\n\t\t\t\tif (cur_ops->poll_gp_state(gp_state))\n\t\t\t\t\tgp_initiated = false;\n\t\t\t}\n\t\t\tif (torture_must_stop())\n\t\t\t\tgoto checkwait;\n\t\t}\n\n\t\t// In case the grace period extended beyond the end of the loop.\n\t\tif (gp_initiated && !failed && !cur_ops->poll_gp_state(gp_state))\n\t\t\trcu_torture_boost_failed(gp_state, &gp_state_time);\n\n\t\t/*\n\t\t * Set the start time of the next test interval.\n\t\t * Yes, this is vulnerable to long delays, but such\n\t\t * delays simply cause a false negative for the next\n\t\t * interval.  Besides, we are running at RT priority,\n\t\t * so delays should be relatively rare.\n\t\t */\n\t\twhile (oldstarttime == READ_ONCE(boost_starttime) && !kthread_should_stop()) {\n\t\t\tif (mutex_trylock(&boost_mutex)) {\n\t\t\t\tif (oldstarttime == boost_starttime) {\n\t\t\t\t\tWRITE_ONCE(boost_starttime,\n\t\t\t\t\t\t   jiffies + test_boost_interval * HZ);\n\t\t\t\t\tn_rcu_torture_boosts++;\n\t\t\t\t}\n\t\t\t\tmutex_unlock(&boost_mutex);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tschedule_timeout_uninterruptible(1);\n\t\t}\n\n\t\t/* Go do the stutter. */\ncheckwait:\tif (stutter_wait(\"rcu_torture_boost\"))\n\t\t\tsched_set_fifo_low(current);\n\t} while (!torture_must_stop());\n\n\t/* Clean up and exit. */\n\twhile (!kthread_should_stop()) {\n\t\ttorture_shutdown_absorb(\"rcu_torture_boost\");\n\t\tschedule_timeout_uninterruptible(1);\n\t}\n\ttorture_kthread_stopping(\"rcu_torture_boost\");\n\treturn 0;\n}",
        "static int demod_attach_cxd28xx(struct ddb_input *input, int par, int osc24)\n{\n\tstruct i2c_adapter *i2c = &input->port->i2c->adap;\n\tstruct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];\n\tstruct device *dev = input->port->dev->dev;": "static int demod_attach_cxd28xx(struct ddb_input *input, int par, int osc24)\n{\n\tstruct i2c_adapter *i2c = &input->port->i2c->adap;\n\tstruct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];\n\tstruct device *dev = input->port->dev->dev;\n\tstruct cxd2841er_config cfg;\n\n\t/* the cxd2841er driver expects 8bit/shifted I2C addresses */\n\tcfg.i2c_addr = ((input->nr & 1) ? 0x6d : 0x6c) << 1;\n\n\tcfg.xtal = osc24 ? SONY_XTAL_24000 : SONY_XTAL_20500;\n\tcfg.flags = CXD2841ER_AUTO_IFHZ | CXD2841ER_EARLY_TUNE |\n\t\tCXD2841ER_NO_WAIT_LOCK | CXD2841ER_NO_AGCNEG |\n\t\tCXD2841ER_TSBITS;\n\n\tif (!par)\n\t\tcfg.flags |= CXD2841ER_TS_SERIAL;\n\n\t/* attach frontend */\n\tdvb->fe = dvb_attach(cxd2841er_attach_t_c, &cfg, i2c);\n\n\tif (!dvb->fe) {\n\t\tdev_err(dev, \"No cxd2837/38/43/54 found!\\n\");\n\t\treturn -ENODEV;\n\t}\n\tdvb->fe->sec_priv = input;\n\tdvb->i2c_gate_ctrl = dvb->fe->ops.i2c_gate_ctrl;\n\tdvb->fe->ops.i2c_gate_ctrl = locked_gate_ctrl;\n\treturn 0;\n}",
        "static void jent_memaccess(struct rand_data *ec, __u64 loop_cnt)\n{\n\tunsigned int wrap = 0;\n\t__u64 i = 0;\n#define MAX_ACC_LOOP_BIT 7": "static void jent_memaccess(struct rand_data *ec, __u64 loop_cnt)\n{\n\tunsigned int wrap = 0;\n\t__u64 i = 0;\n#define MAX_ACC_LOOP_BIT 7\n#define MIN_ACC_LOOP_BIT 0\n\t__u64 acc_loop_cnt =\n\t\tjent_loop_shuffle(ec, MAX_ACC_LOOP_BIT, MIN_ACC_LOOP_BIT);\n\n\tif (NULL == ec || NULL == ec->mem)\n\t\treturn;\n\twrap = ec->memblocksize * ec->memblocks;\n\n\t/*\n\t * testing purposes -- allow test app to set the counter, not\n\t * needed during runtime\n\t */\n\tif (loop_cnt)\n\t\tacc_loop_cnt = loop_cnt;\n\n\tfor (i = 0; i < (ec->memaccessloops + acc_loop_cnt); i++) {\n\t\tunsigned char *tmpval = ec->mem + ec->memlocation;\n\t\t/*\n\t\t * memory access: just add 1 to one byte,\n\t\t * wrap at 255 -- memory access implies read\n\t\t * from and write to memory location\n\t\t */\n\t\t*tmpval = (*tmpval + 1) & 0xff;\n\t\t/*\n\t\t * Addition of memblocksize - 1 to pointer\n\t\t * with wrap around logic to ensure that every\n\t\t * memory location is hit evenly\n\t\t */\n\t\tec->memlocation = ec->memlocation + ec->memblocksize - 1;\n\t\tec->memlocation = ec->memlocation % wrap;\n\t}\n}",
        "static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)\n{\n\tstruct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;\n\tstruct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 };\n\tu32  max_desc_num = AM65_CPSW_MAX_RX_DESC;": "static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)\n{\n\tstruct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;\n\tstruct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 };\n\tu32  max_desc_num = AM65_CPSW_MAX_RX_DESC;\n\tstruct device *dev = common->dev;\n\tu32 hdesc_size;\n\tu32 fdqring_id;\n\tint i, ret = 0;\n\n\thdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,\n\t\t\t\t\t   AM65_CPSW_NAV_SW_DATA_SIZE);\n\n\trx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;\n\trx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS;\n\trx_cfg.flow_id_base = common->rx_flow_id_base;\n\n\t/* init all flows */\n\trx_chn->dev = dev;\n\trx_chn->descs_num = max_desc_num;\n\n\trx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, \"rx\", &rx_cfg);\n\tif (IS_ERR(rx_chn->rx_chn)) {\n\t\tret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn),\n\t\t\t\t    \"Failed to request rx dma channel\\n\");\n\t\tgoto err;\n\t}\n\trx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn);\n\n\trx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev,\n\t\t\t\t\t\t\t  rx_chn->descs_num,\n\t\t\t\t\t\t\t  hdesc_size, \"rx\");\n\tif (IS_ERR(rx_chn->desc_pool)) {\n\t\tret = PTR_ERR(rx_chn->desc_pool);\n\t\tdev_err(dev, \"Failed to create rx poll %d\\n\", ret);\n\t\tgoto err;\n\t}\n\n\tcommon->rx_flow_id_base =\n\t\t\tk3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);\n\tdev_info(dev, \"set new flow-id-base %u\\n\", common->rx_flow_id_base);\n\n\tfdqring_id = K3_RINGACC_RING_ID_ANY;\n\tfor (i = 0; i < rx_cfg.flow_id_num; i++) {\n\t\tstruct k3_ring_cfg rxring_cfg = {\n\t\t\t.elm_size = K3_RINGACC_RING_ELSIZE_8,\n\t\t\t.mode = K3_RINGACC_RING_MODE_RING,\n\t\t\t.flags = 0,\n\t\t};\n\t\tstruct k3_ring_cfg fdqring_cfg = {\n\t\t\t.elm_size = K3_RINGACC_RING_ELSIZE_8,\n\t\t\t.flags = K3_RINGACC_RING_SHARED,\n\t\t};\n\t\tstruct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {\n\t\t\t.rx_cfg = rxring_cfg,\n\t\t\t.rxfdq_cfg = fdqring_cfg,\n\t\t\t.ring_rxq_id = K3_RINGACC_RING_ID_ANY,\n\t\t\t.src_tag_lo_sel =\n\t\t\t\tK3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,\n\t\t};\n\n\t\trx_flow_cfg.ring_rxfdq0_id = fdqring_id;\n\t\trx_flow_cfg.rx_cfg.size = max_desc_num;\n\t\trx_flow_cfg.rxfdq_cfg.size = max_desc_num;\n\t\trx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode;\n\n\t\tret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,\n\t\t\t\t\t\ti, &rx_flow_cfg);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"Failed to init rx flow%d %d\\n\", i, ret);\n\t\t\tgoto err;\n\t\t}\n\t\tif (!i)\n\t\t\tfdqring_id =\n\t\t\t\tk3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,\n\t\t\t\t\t\t\t\ti);\n\n\t\trx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);\n\n\t\tif (rx_chn->irq <= 0) {\n\t\t\tdev_err(dev, \"Failed to get rx dma irq %d\\n\",\n\t\t\t\trx_chn->irq);\n\t\t\tret = -ENXIO;\n\t\t\tgoto err;\n\t\t}\n\t}\n\nerr:\n\ti = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common);\n\tif (i) {\n\t\tdev_err(dev, \"Failed to add free_rx_chns action %d\\n\", i);\n\t\treturn i;\n\t}\n\n\treturn ret;\n}",
        "static int io_recvmsg(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_async_msghdr iomsg, *kmsg;\n\tstruct io_sr_msg *sr = &req->sr_msg;\n\tstruct socket *sock;": "static int io_recvmsg(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_async_msghdr iomsg, *kmsg;\n\tstruct io_sr_msg *sr = &req->sr_msg;\n\tstruct socket *sock;\n\tunsigned int cflags;\n\tunsigned flags;\n\tint ret, min_ret = 0;\n\tbool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;\n\n\tsock = sock_from_file(req->file);\n\tif (unlikely(!sock))\n\t\treturn -ENOTSOCK;\n\n\tif (req_has_async_data(req)) {\n\t\tkmsg = req->async_data;\n\t} else {\n\t\tret = io_recvmsg_copy_hdr(req, &iomsg);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tkmsg = &iomsg;\n\t}\n\n\tif (!(req->flags & REQ_F_POLLED) &&\n\t    (sr->flags & IORING_RECVSEND_POLL_FIRST))\n\t\treturn io_setup_async_msg(req, kmsg);\n\n\tif (io_do_buffer_select(req)) {\n\t\tvoid __user *buf;\n\n\t\tbuf = io_buffer_select(req, &sr->len, issue_flags);\n\t\tif (!buf)\n\t\t\treturn -ENOBUFS;\n\t\tkmsg->fast_iov[0].iov_base = buf;\n\t\tkmsg->fast_iov[0].iov_len = sr->len;\n\t\tiov_iter_init(&kmsg->msg.msg_iter, READ, kmsg->fast_iov, 1,\n\t\t\t\tsr->len);\n\t}\n\n\tflags = sr->msg_flags;\n\tif (force_nonblock)\n\t\tflags |= MSG_DONTWAIT;\n\tif (flags & MSG_WAITALL)\n\t\tmin_ret = iov_iter_count(&kmsg->msg.msg_iter);\n\n\tkmsg->msg.msg_get_inq = 1;\n\tret = __sys_recvmsg_sock(sock, &kmsg->msg, sr->umsg, kmsg->uaddr, flags);\n\tif (ret < min_ret) {\n\t\tif (ret == -EAGAIN && force_nonblock)\n\t\t\treturn io_setup_async_msg(req, kmsg);\n\t\tif (ret == -ERESTARTSYS)\n\t\t\tret = -EINTR;\n\t\tif (ret > 0 && io_net_retry(sock, flags)) {\n\t\t\tsr->done_io += ret;\n\t\t\treq->flags |= REQ_F_PARTIAL_IO;\n\t\t\treturn io_setup_async_msg(req, kmsg);\n\t\t}\n\t\treq_set_fail(req);\n\t} else if ((flags & MSG_WAITALL) && (kmsg->msg.msg_flags & (MSG_TRUNC | MSG_CTRUNC))) {\n\t\treq_set_fail(req);\n\t}\n\n\t/* fast path, check for non-NULL to avoid function call */\n\tif (kmsg->free_iov)\n\t\tkfree(kmsg->free_iov);\n\treq->flags &= ~REQ_F_NEED_CLEANUP;\n\tif (ret >= 0)\n\t\tret += sr->done_io;\n\telse if (sr->done_io)\n\t\tret = sr->done_io;\n\tcflags = io_put_kbuf(req, issue_flags);\n\tif (kmsg->msg.msg_inq)\n\t\tcflags |= IORING_CQE_F_SOCK_NONEMPTY;\n\t__io_req_complete(req, issue_flags, ret, cflags);\n\treturn 0;\n}",
        "static int uwb_set_status(enum tpacpi_rfkill_state state)\n{\n\tint status;\n\n\tvdbg_printk(TPACPI_DBG_RFKILL,": "static int uwb_set_status(enum tpacpi_rfkill_state state)\n{\n\tint status;\n\n\tvdbg_printk(TPACPI_DBG_RFKILL,\n\t\t\"will attempt to %s UWB\\n\",\n\t\t(state == TPACPI_RFK_RADIO_ON) ? \"enable\" : \"disable\");\n\n#ifdef CONFIG_THINKPAD_ACPI_DEBUGFACILITIES\n\tif (dbg_uwbemul) {\n\t\ttpacpi_uwb_emulstate = (state == TPACPI_RFK_RADIO_ON);\n\t\treturn 0;\n\t}\n#endif\n\n\tif (state == TPACPI_RFK_RADIO_ON)\n\t\tstatus = TP_ACPI_UWB_RADIOSSW;\n\telse\n\t\tstatus = 0;\n\n\tif (!acpi_evalf(hkey_handle, NULL, \"SUWB\", \"vd\", status))\n\t\treturn -EIO;\n\n\treturn 0;\n}",
        "static inline u8 iic_clckdiv(unsigned int opb)\n{\n\t/* Compatibility kludge, should go away after all cards\n\t * are fixed to fill correct value for opbfreq.\n\t * Previous driver version used hardcoded divider value 4,": "static inline u8 iic_clckdiv(unsigned int opb)\n{\n\t/* Compatibility kludge, should go away after all cards\n\t * are fixed to fill correct value for opbfreq.\n\t * Previous driver version used hardcoded divider value 4,\n\t * it corresponds to OPB frequency from the range (40, 50] MHz\n\t */\n\tif (!opb){\n\t\tprintk(KERN_WARNING \"ibm-iic: using compatibility value for OPB freq,\"\n\t\t\t\" fix your board specific setup\\n\");\n\t\topb = 50000000;\n\t}\n\n\t/* Convert to MHz */\n\topb /= 1000000;\n\n\tif (opb < 20 || opb > 150){\n\t\tprintk(KERN_WARNING \"ibm-iic: invalid OPB clock frequency %u MHz\\n\",\n\t\t\topb);\n\t\topb = opb < 20 ? 20 : 150;\n\t}\n\treturn (u8)((opb + 9) / 10 - 1);\n}",
        "static int nl80211_set_coalesce(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct cfg80211_registered_device *rdev = info->user_ptr[0];\n\tconst struct wiphy_coalesce_support *coalesce = rdev->wiphy.coalesce;\n\tstruct cfg80211_coalesce new_coalesce = {};": "static int nl80211_set_coalesce(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct cfg80211_registered_device *rdev = info->user_ptr[0];\n\tconst struct wiphy_coalesce_support *coalesce = rdev->wiphy.coalesce;\n\tstruct cfg80211_coalesce new_coalesce = {};\n\tstruct cfg80211_coalesce *n_coalesce;\n\tint err, rem_rule, n_rules = 0, i, j;\n\tstruct nlattr *rule;\n\tstruct cfg80211_coalesce_rules *tmp_rule;\n\n\tif (!rdev->wiphy.coalesce || !rdev->ops->set_coalesce)\n\t\treturn -EOPNOTSUPP;\n\n\tif (!info->attrs[NL80211_ATTR_COALESCE_RULE]) {\n\t\tcfg80211_rdev_free_coalesce(rdev);\n\t\trdev_set_coalesce(rdev, NULL);\n\t\treturn 0;\n\t}\n\n\tnla_for_each_nested(rule, info->attrs[NL80211_ATTR_COALESCE_RULE],\n\t\t\t    rem_rule)\n\t\tn_rules++;\n\tif (n_rules > coalesce->n_rules)\n\t\treturn -EINVAL;\n\n\tnew_coalesce.rules = kcalloc(n_rules, sizeof(new_coalesce.rules[0]),\n\t\t\t\t     GFP_KERNEL);\n\tif (!new_coalesce.rules)\n\t\treturn -ENOMEM;\n\n\tnew_coalesce.n_rules = n_rules;\n\ti = 0;\n\n\tnla_for_each_nested(rule, info->attrs[NL80211_ATTR_COALESCE_RULE],\n\t\t\t    rem_rule) {\n\t\terr = nl80211_parse_coalesce_rule(rdev, rule,\n\t\t\t\t\t\t  &new_coalesce.rules[i]);\n\t\tif (err)\n\t\t\tgoto error;\n\n\t\ti++;\n\t}\n\n\terr = rdev_set_coalesce(rdev, &new_coalesce);\n\tif (err)\n\t\tgoto error;\n\n\tn_coalesce = kmemdup(&new_coalesce, sizeof(new_coalesce), GFP_KERNEL);\n\tif (!n_coalesce) {\n\t\terr = -ENOMEM;\n\t\tgoto error;\n\t}\n\tcfg80211_rdev_free_coalesce(rdev);\n\trdev->coalesce = n_coalesce;\n\n\treturn 0;\nerror:\n\tfor (i = 0; i < new_coalesce.n_rules; i++) {\n\t\ttmp_rule = &new_coalesce.rules[i];\n\t\tfor (j = 0; j < tmp_rule->n_patterns; j++)\n\t\t\tkfree(tmp_rule->patterns[j].mask);\n\t\tkfree(tmp_rule->patterns);\n\t}\n\tkfree(new_coalesce.rules);\n\n\treturn err;\n}",
        "static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)\n{\n\tif (do_ac3) {\n\t\t/* AC3EN for 037 */\n\t\tsnd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);": "static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)\n{\n\tif (do_ac3) {\n\t\t/* AC3EN for 037 */\n\t\tsnd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);\n\t\t/* AC3EN for 039 */\n\t\tsnd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);\n\t\n\t\tif (cm->can_ac3_hw) {\n\t\t\t/* SPD24SEL for 037, 0x02 */\n\t\t\t/* SPD24SEL for 039, 0x20, but cannot be set */\n\t\t\tsnd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);\n\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);\n\t\t} else { /* can_ac3_sw */\n\t\t\t/* SPD32SEL for 037 & 039, 0x20 */\n\t\t\tsnd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);\n\t\t\t/* set 176K sample rate to fix 033 HW bug */\n\t\t\tif (cm->chip_version == 33) {\n\t\t\t\tif (rate >= 48000) {\n\t\t\t\t\tsnd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);\n\t\t\t\t} else {\n\t\t\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t} else {\n\t\tsnd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);\n\t\tsnd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);\n\n\t\tif (cm->can_ac3_hw) {\n\t\t\t/* chip model >= 37 */\n\t\t\tif (snd_pcm_format_width(subs->runtime->format) > 16) {\n\t\t\t\tsnd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);\n\t\t\t\tsnd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);\n\t\t\t} else {\n\t\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);\n\t\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);\n\t\t\t}\n\t\t} else {\n\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);\n\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);\n\t\t\tsnd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);\n\t\t}\n\t}\n}",
        "static void super_90_sync(struct mddev *mddev, struct md_rdev *rdev)\n{\n\tmdp_super_t *sb;\n\tstruct md_rdev *rdev2;\n\tint next_spare = mddev->raid_disks;": "static void super_90_sync(struct mddev *mddev, struct md_rdev *rdev)\n{\n\tmdp_super_t *sb;\n\tstruct md_rdev *rdev2;\n\tint next_spare = mddev->raid_disks;\n\n\t/* make rdev->sb match mddev data..\n\t *\n\t * 1/ zero out disks\n\t * 2/ Add info for each disk, keeping track of highest desc_nr (next_spare);\n\t * 3/ any empty disks < next_spare become removed\n\t *\n\t * disks[0] gets initialised to REMOVED because\n\t * we cannot be sure from other fields if it has\n\t * been initialised or not.\n\t */\n\tint i;\n\tint active=0, working=0,failed=0,spare=0,nr_disks=0;\n\n\trdev->sb_size = MD_SB_BYTES;\n\n\tsb = page_address(rdev->sb_page);\n\n\tmemset(sb, 0, sizeof(*sb));\n\n\tsb->md_magic = MD_SB_MAGIC;\n\tsb->major_version = mddev->major_version;\n\tsb->patch_version = mddev->patch_version;\n\tsb->gvalid_words  = 0; /* ignored */\n\tmemcpy(&sb->set_uuid0, mddev->uuid+0, 4);\n\tmemcpy(&sb->set_uuid1, mddev->uuid+4, 4);\n\tmemcpy(&sb->set_uuid2, mddev->uuid+8, 4);\n\tmemcpy(&sb->set_uuid3, mddev->uuid+12,4);\n\n\tsb->ctime = clamp_t(time64_t, mddev->ctime, 0, U32_MAX);\n\tsb->level = mddev->level;\n\tsb->size = mddev->dev_sectors / 2;\n\tsb->raid_disks = mddev->raid_disks;\n\tsb->md_minor = mddev->md_minor;\n\tsb->not_persistent = 0;\n\tsb->utime = clamp_t(time64_t, mddev->utime, 0, U32_MAX);\n\tsb->state = 0;\n\tsb->events_hi = (mddev->events>>32);\n\tsb->events_lo = (u32)mddev->events;\n\n\tif (mddev->reshape_position == MaxSector)\n\t\tsb->minor_version = 90;\n\telse {\n\t\tsb->minor_version = 91;\n\t\tsb->reshape_position = mddev->reshape_position;\n\t\tsb->new_level = mddev->new_level;\n\t\tsb->delta_disks = mddev->delta_disks;\n\t\tsb->new_layout = mddev->new_layout;\n\t\tsb->new_chunk = mddev->new_chunk_sectors << 9;\n\t}\n\tmddev->minor_version = sb->minor_version;\n\tif (mddev->in_sync)\n\t{\n\t\tsb->recovery_cp = mddev->recovery_cp;\n\t\tsb->cp_events_hi = (mddev->events>>32);\n\t\tsb->cp_events_lo = (u32)mddev->events;\n\t\tif (mddev->recovery_cp == MaxSector)\n\t\t\tsb->state = (1<< MD_SB_CLEAN);\n\t} else\n\t\tsb->recovery_cp = 0;\n\n\tsb->layout = mddev->layout;\n\tsb->chunk_size = mddev->chunk_sectors << 9;\n\n\tif (mddev->bitmap && mddev->bitmap_info.file == NULL)\n\t\tsb->state |= (1<<MD_SB_BITMAP_PRESENT);\n\n\tsb->disks[0].state = (1<<MD_DISK_REMOVED);\n\trdev_for_each(rdev2, mddev) {\n\t\tmdp_disk_t *d;\n\t\tint desc_nr;\n\t\tint is_active = test_bit(In_sync, &rdev2->flags);\n\n\t\tif (rdev2->raid_disk >= 0 &&\n\t\t    sb->minor_version >= 91)\n\t\t\t/* we have nowhere to store the recovery_offset,\n\t\t\t * but if it is not below the reshape_position,\n\t\t\t * we can piggy-back on that.\n\t\t\t */\n\t\t\tis_active = 1;\n\t\tif (rdev2->raid_disk < 0 ||\n\t\t    test_bit(Faulty, &rdev2->flags))\n\t\t\tis_active = 0;\n\t\tif (is_active)\n\t\t\tdesc_nr = rdev2->raid_disk;\n\t\telse\n\t\t\tdesc_nr = next_spare++;\n\t\trdev2->desc_nr = desc_nr;\n\t\td = &sb->disks[rdev2->desc_nr];\n\t\tnr_disks++;\n\t\td->number = rdev2->desc_nr;\n\t\td->major = MAJOR(rdev2->bdev->bd_dev);\n\t\td->minor = MINOR(rdev2->bdev->bd_dev);\n\t\tif (is_active)\n\t\t\td->raid_disk = rdev2->raid_disk;\n\t\telse\n\t\t\td->raid_disk = rdev2->desc_nr; /* compatibility */\n\t\tif (test_bit(Faulty, &rdev2->flags))\n\t\t\td->state = (1<<MD_DISK_FAULTY);\n\t\telse if (is_active) {\n\t\t\td->state = (1<<MD_DISK_ACTIVE);\n\t\t\tif (test_bit(In_sync, &rdev2->flags))\n\t\t\t\td->state |= (1<<MD_DISK_SYNC);\n\t\t\tactive++;\n\t\t\tworking++;\n\t\t} else {\n\t\t\td->state = 0;\n\t\t\tspare++;\n\t\t\tworking++;\n\t\t}\n\t\tif (test_bit(WriteMostly, &rdev2->flags))\n\t\t\td->state |= (1<<MD_DISK_WRITEMOSTLY);\n\t\tif (test_bit(FailFast, &rdev2->flags))\n\t\t\td->state |= (1<<MD_DISK_FAILFAST);\n\t}\n\t/* now set the \"removed\" and \"faulty\" bits on any missing devices */\n\tfor (i=0 ; i < mddev->raid_disks ; i++) {\n\t\tmdp_disk_t *d = &sb->disks[i];\n\t\tif (d->state == 0 && d->number == 0) {\n\t\t\td->number = i;\n\t\t\td->raid_disk = i;\n\t\t\td->state = (1<<MD_DISK_REMOVED);\n\t\t\td->state |= (1<<MD_DISK_FAULTY);\n\t\t\tfailed++;\n\t\t}\n\t}\n\tsb->nr_disks = nr_disks;\n\tsb->active_disks = active;\n\tsb->working_disks = working;\n\tsb->failed_disks = failed;\n\tsb->spare_disks = spare;\n\n\tsb->this_disk = sb->disks[rdev->desc_nr];\n\tsb->sb_csum = calc_sb_csum(sb);\n}",
        "static int cgroup_vet_subtree_control_enable(struct cgroup *cgrp, u16 enable)\n{\n\tu16 domain_enable = enable & ~cgrp_dfl_threaded_ss_mask;\n\n\t/* if nothing is getting enabled, nothing to worry about */": "static int cgroup_vet_subtree_control_enable(struct cgroup *cgrp, u16 enable)\n{\n\tu16 domain_enable = enable & ~cgrp_dfl_threaded_ss_mask;\n\n\t/* if nothing is getting enabled, nothing to worry about */\n\tif (!enable)\n\t\treturn 0;\n\n\t/* can @cgrp host any resources? */\n\tif (!cgroup_is_valid_domain(cgrp->dom_cgrp))\n\t\treturn -EOPNOTSUPP;\n\n\t/* mixables don't care */\n\tif (cgroup_is_mixable(cgrp))\n\t\treturn 0;\n\n\tif (domain_enable) {\n\t\t/* can't enable domain controllers inside a thread subtree */\n\t\tif (cgroup_is_thread_root(cgrp) || cgroup_is_threaded(cgrp))\n\t\t\treturn -EOPNOTSUPP;\n\t} else {\n\t\t/*\n\t\t * Threaded controllers can handle internal competitions\n\t\t * and are always allowed inside a (prospective) thread\n\t\t * subtree.\n\t\t */\n\t\tif (cgroup_can_be_thread_root(cgrp) || cgroup_is_threaded(cgrp))\n\t\t\treturn 0;\n\t}\n\n\t/*\n\t * Controllers can't be enabled for a cgroup with tasks to avoid\n\t * child cgroups competing against tasks.\n\t */\n\tif (cgroup_has_tasks(cgrp))\n\t\treturn -EBUSY;\n\n\treturn 0;\n}",
        "static int power_up_device(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tu8 data = 0;\n\tu16 retry_count = 0;": "static int power_up_device(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tu8 data = 0;\n\tu16 retry_count = 0;\n\tstruct i2c_device_addr wake_up_addr;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\twake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;\n\twake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;\n\twake_up_addr.user_data = dev_addr->user_data;\n\t/*\n\t * I2C access may fail in this case: no ack\n\t * dummy write must be used to wake uop device, dummy read must be used to\n\t * reset HI state machine (avoiding actual writes)\n\t */\n\tdo {\n\t\tdata = 0;\n\t\tdrxbsp_i2c_write_read(&wake_up_addr, 1, &data,\n\t\t\t\t      (struct i2c_device_addr *)(NULL), 0,\n\t\t\t\t     (u8 *)(NULL));\n\t\tmsleep(10);\n\t\tretry_count++;\n\t} while ((drxbsp_i2c_write_read\n\t\t  ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,\n\t\t   &data)\n\t\t  != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));\n\n\t/* Need some recovery time .... */\n\tmsleep(10);\n\n\tif (retry_count == DRXJ_MAX_RETRIES_POWERUP)\n\t\treturn -EIO;\n\n\treturn 0;\n}",
        "static int start_child(unsigned int nr, char *veth, int test_desc_fd[2])\n{\n\tint cmd_sock[2];\n\tvoid *data_map;\n\tpid_t child;": "static int start_child(unsigned int nr, char *veth, int test_desc_fd[2])\n{\n\tint cmd_sock[2];\n\tvoid *data_map;\n\tpid_t child;\n\n\tif (init_child(nsfd_childa, veth, child_ip(nr), grchild_ip(nr)))\n\t\treturn -1;\n\n\tif (init_child(nsfd_childb, veth, grchild_ip(nr), child_ip(nr)))\n\t\treturn -1;\n\n\tchild = fork();\n\tif (child < 0) {\n\t\tpr_err(\"fork()\");\n\t\treturn -1;\n\t} else if (child) {\n\t\t/* in parent - selftest */\n\t\treturn switch_ns(nsfd_parent);\n\t}\n\n\tif (close(test_desc_fd[1])) {\n\t\tpr_err(\"close()\");\n\t\treturn -1;\n\t}\n\n\t/* child */\n\tdata_map = mmap(0, page_size, PROT_READ | PROT_WRITE,\n\t\t\tMAP_SHARED | MAP_ANONYMOUS, -1, 0);\n\tif (data_map == MAP_FAILED) {\n\t\tpr_err(\"mmap()\");\n\t\treturn -1;\n\t}\n\n\trandomize_buffer(data_map, page_size);\n\n\tif (socketpair(PF_LOCAL, SOCK_SEQPACKET, 0, cmd_sock)) {\n\t\tpr_err(\"socketpair()\");\n\t\treturn -1;\n\t}\n\n\tchild = fork();\n\tif (child < 0) {\n\t\tpr_err(\"fork()\");\n\t\treturn -1;\n\t} else if (child) {\n\t\tif (close(cmd_sock[0])) {\n\t\t\tpr_err(\"close()\");\n\t\t\treturn -1;\n\t\t}\n\t\treturn child_f(nr, test_desc_fd[0], cmd_sock[1], data_map);\n\t}\n\tif (close(cmd_sock[1])) {\n\t\tpr_err(\"close()\");\n\t\treturn -1;\n\t}\n\treturn grand_child_f(nr, cmd_sock[0], data_map);\n}",
        "static void osnoise_hist_usage(char *usage)\n{\n\tint i;\n\n\tstatic const char * const msg[] = {": "static void osnoise_hist_usage(char *usage)\n{\n\tint i;\n\n\tstatic const char * const msg[] = {\n\t\t\"\",\n\t\t\"  usage: rtla osnoise hist [-h] [-D] [-d s] [-a us] [-p us] [-r us] [-s us] [-S us] \\\\\",\n\t\t\"\t  [-T us] [-t[=file]] [-e sys[:event]] [--filter <filter>] [--trigger <trigger>] \\\\\",\n\t\t\"\t  [-c cpu-list] [-P priority] [-b N] [-E N] [--no-header] [--no-summary] [--no-index] \\\\\",\n\t\t\"\t  [--with-zeros]\",\n\t\t\"\",\n\t\t\"\t  -h/--help: print this menu\",\n\t\t\"\t  -a/--auto: set automatic trace mode, stopping the session if argument in us sample is hit\",\n\t\t\"\t  -p/--period us: osnoise period in us\",\n\t\t\"\t  -r/--runtime us: osnoise runtime in us\",\n\t\t\"\t  -s/--stop us: stop trace if a single sample is higher than the argument in us\",\n\t\t\"\t  -S/--stop-total us: stop trace if the total sample is higher than the argument in us\",\n\t\t\"\t  -T/--threshold us: the minimum delta to be considered a noise\",\n\t\t\"\t  -c/--cpus cpu-list: list of cpus to run osnoise threads\",\n\t\t\"\t  -d/--duration time[s|m|h|d]: duration of the session\",\n\t\t\"\t  -D/--debug: print debug info\",\n\t\t\"\t  -t/--trace[=file]: save the stopped trace to [file|osnoise_trace.txt]\",\n\t\t\"\t  -e/--event <sys:event>: enable the <sys:event> in the trace instance, multiple -e are allowed\",\n\t\t\"\t     --filter <filter>: enable a trace event filter to the previous -e event\",\n\t\t\"\t     --trigger <trigger>: enable a trace event trigger to the previous -e event\",\n\t\t\"\t  -b/--bucket-size N: set the histogram bucket size (default 1)\",\n\t\t\"\t  -E/--entries N: set the number of entries of the histogram (default 256)\",\n\t\t\"\t     --no-header: do not print header\",\n\t\t\"\t     --no-summary: do not print summary\",\n\t\t\"\t     --no-index: do not print index\",\n\t\t\"\t     --with-zeros: print zero only entries\",\n\t\t\"\t  -P/--priority o:prio|r:prio|f:prio|d:runtime:period: set scheduling parameters\",\n\t\t\"\t\to:prio - use SCHED_OTHER with prio\",\n\t\t\"\t\tr:prio - use SCHED_RR with prio\",\n\t\t\"\t\tf:prio - use SCHED_FIFO with prio\",\n\t\t\"\t\td:runtime[us|ms|s]:period[us|ms|s] - use SCHED_DEADLINE with runtime and period\",\n\t\t\"\t\t\t\t\t\t       in nanoseconds\",\n\t\tNULL,\n\t};\n\n\tif (usage)\n\t\tfprintf(stderr, \"%s\\n\", usage);\n\n\tfprintf(stderr, \"rtla osnoise hist: a per-cpu histogram of the OS noise (version %s)\\n\",\n\t\t\tVERSION);\n\n\tfor (i = 0; msg[i]; i++)\n\t\tfprintf(stderr, \"%s\\n\", msg[i]);\n\texit(1);\n}",
        "static int handle_one_ule_extension( struct dvb_net_priv *p )\n{\n\t/* Table of mandatory extension header handlers.  The header type is the index. */\n\tstatic int (*ule_mandatory_ext_handlers[255])( struct dvb_net_priv *p ) =\n\t\t{ [0] = ule_test_sndu, [1] = ule_bridged_sndu, [2] = NULL,  };": "static int handle_one_ule_extension( struct dvb_net_priv *p )\n{\n\t/* Table of mandatory extension header handlers.  The header type is the index. */\n\tstatic int (*ule_mandatory_ext_handlers[255])( struct dvb_net_priv *p ) =\n\t\t{ [0] = ule_test_sndu, [1] = ule_bridged_sndu, [2] = NULL,  };\n\n\t/* Table of optional extension header handlers.  The header type is the index. */\n\tstatic int (*ule_optional_ext_handlers[255])( struct dvb_net_priv *p ) =\n\t\t{ [0] = ule_exthdr_padding, [1] = NULL, };\n\n\tint ext_len = 0;\n\tunsigned char hlen = (p->ule_sndu_type & 0x0700) >> 8;\n\tunsigned char htype = p->ule_sndu_type & 0x00FF;\n\n\t/* Discriminate mandatory and optional extension headers. */\n\tif (hlen == 0) {\n\t\t/* Mandatory extension header */\n\t\tif (ule_mandatory_ext_handlers[htype]) {\n\t\t\text_len = ule_mandatory_ext_handlers[htype]( p );\n\t\t\tif(ext_len >= 0) {\n\t\t\t\tp->ule_next_hdr += ext_len;\n\t\t\t\tif (!p->ule_bridged) {\n\t\t\t\t\tp->ule_sndu_type = ntohs(*(__be16 *)p->ule_next_hdr);\n\t\t\t\t\tp->ule_next_hdr += 2;\n\t\t\t\t} else {\n\t\t\t\t\tp->ule_sndu_type = ntohs(*(__be16 *)(p->ule_next_hdr + ((p->ule_dbit ? 2 : 3) * ETH_ALEN)));\n\t\t\t\t\t/* This assures the extension handling loop will terminate. */\n\t\t\t\t}\n\t\t\t}\n\t\t\t// else: extension handler failed or SNDU should be discarded\n\t\t} else\n\t\t\text_len = -1;\t/* SNDU has to be discarded. */\n\t} else {\n\t\t/* Optional extension header.  Calculate the length. */\n\t\text_len = hlen << 1;\n\t\t/* Process the optional extension header according to its type. */\n\t\tif (ule_optional_ext_handlers[htype])\n\t\t\t(void)ule_optional_ext_handlers[htype]( p );\n\t\tp->ule_next_hdr += ext_len;\n\t\tp->ule_sndu_type = ntohs( *(__be16 *)(p->ule_next_hdr-2) );\n\t\t/*\n\t\t * note: the length of the next header type is included in the\n\t\t * length of THIS optional extension header\n\t\t */\n\t}\n\n\treturn ext_len;\n}",
        "static int probe_tsb41ba3d(struct fw_ohci *ohci)\n{\n\t/* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */\n\tstatic const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };\n\tint reg, i;": "static int probe_tsb41ba3d(struct fw_ohci *ohci)\n{\n\t/* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */\n\tstatic const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };\n\tint reg, i;\n\n\treg = read_phy_reg(ohci, 2);\n\tif (reg < 0)\n\t\treturn reg;\n\tif ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)\n\t\treturn 0;\n\n\tfor (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {\n\t\treg = read_paged_phy_reg(ohci, 1, i + 10);\n\t\tif (reg < 0)\n\t\t\treturn reg;\n\t\tif (reg != id[i])\n\t\t\treturn 0;\n\t}\n\treturn 1;\n}",
        "static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)\n{\n\tu32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld;\n\tu32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;\n\tstruct qed_mcp_link_speed_params *ext_speed;": "static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)\n{\n\tu32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld;\n\tu32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;\n\tstruct qed_mcp_link_speed_params *ext_speed;\n\tstruct qed_mcp_link_capabilities *p_caps;\n\tstruct qed_mcp_link_params *link;\n\tint i;\n\n\t/* Read global nvm_cfg address */\n\tnvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);\n\n\t/* Verify MCP has initialized it */\n\tif (!nvm_cfg_addr) {\n\t\tDP_NOTICE(p_hwfn, \"Shared memory not initialized\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */\n\tnvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);\n\n\taddr = MCP_REG_SCRATCH + nvm_cfg1_offset +\n\t       offsetof(struct nvm_cfg1, glob) +\n\t       offsetof(struct nvm_cfg1_glob, core_cfg);\n\n\tcore_cfg = qed_rd(p_hwfn, p_ptt, addr);\n\n\tswitch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>\n\t\tNVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2:\n\tcase NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4:\n\t\tbreak;\n\tdefault:\n\t\tDP_NOTICE(p_hwfn, \"Unknown port mode in 0x%08x\\n\", core_cfg);\n\t\tbreak;\n\t}\n\n\t/* Read default link configuration */\n\tlink = &p_hwfn->mcp_info->link_input;\n\tp_caps = &p_hwfn->mcp_info->link_capabilities;\n\tport_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +\n\t\t\toffsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);\n\tlink_temp = qed_rd(p_hwfn, p_ptt,\n\t\t\t   port_cfg_addr +\n\t\t\t   offsetof(struct nvm_cfg1_port, speed_cap_mask));\n\tlink_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;\n\tlink->speed.advertised_speeds = link_temp;\n\n\tp_caps->speed_capabilities = link->speed.advertised_speeds;\n\n\tlink_temp = qed_rd(p_hwfn, p_ptt,\n\t\t\t   port_cfg_addr +\n\t\t\t   offsetof(struct nvm_cfg1_port, link_settings));\n\tswitch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>\n\t\tNVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:\n\t\tlink->speed.autoneg = true;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_1G:\n\t\tlink->speed.forced_speed = 1000;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_10G:\n\t\tlink->speed.forced_speed = 10000;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_20G:\n\t\tlink->speed.forced_speed = 20000;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_25G:\n\t\tlink->speed.forced_speed = 25000;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_40G:\n\t\tlink->speed.forced_speed = 40000;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_50G:\n\t\tlink->speed.forced_speed = 50000;\n\t\tbreak;\n\tcase NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:\n\t\tlink->speed.forced_speed = 100000;\n\t\tbreak;\n\tdefault:\n\t\tDP_NOTICE(p_hwfn, \"Unknown Speed in 0x%08x\\n\", link_temp);\n\t}\n\n\tp_caps->default_speed_autoneg = link->speed.autoneg;\n\n\tfld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL);\n\tlink->pause.autoneg = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);\n\tlink->pause.forced_rx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);\n\tlink->pause.forced_tx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);\n\tlink->loopback_mode = 0;\n\n\tif (p_hwfn->mcp_info->capabilities &\n\t    FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) {\n\t\tswitch (GET_MFW_FIELD(link_temp,\n\t\t\t\t      NVM_CFG1_PORT_FEC_FORCE_MODE)) {\n\t\tcase NVM_CFG1_PORT_FEC_FORCE_MODE_NONE:\n\t\t\tp_caps->fec_default |= QED_FEC_MODE_NONE;\n\t\t\tbreak;\n\t\tcase NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE:\n\t\t\tp_caps->fec_default |= QED_FEC_MODE_FIRECODE;\n\t\t\tbreak;\n\t\tcase NVM_CFG1_PORT_FEC_FORCE_MODE_RS:\n\t\t\tp_caps->fec_default |= QED_FEC_MODE_RS;\n\t\t\tbreak;\n\t\tcase NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO:\n\t\t\tp_caps->fec_default |= QED_FEC_MODE_AUTO;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDP_VERBOSE(p_hwfn, NETIF_MSG_LINK,\n\t\t\t\t   \"unknown FEC mode in 0x%08x\\n\", link_temp);\n\t\t}\n\t} else {\n\t\tp_caps->fec_default = QED_FEC_MODE_UNSUPPORTED;\n\t}\n\n\tlink->fec = p_caps->fec_default;\n\n\tif (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {\n\t\tlink_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +\n\t\t\t\t   offsetof(struct nvm_cfg1_port, ext_phy));\n\t\tlink_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;\n\t\tlink_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;\n\t\tp_caps->default_eee = QED_MCP_EEE_ENABLED;\n\t\tlink->eee.enable = true;\n\t\tswitch (link_temp) {\n\t\tcase NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:\n\t\t\tp_caps->default_eee = QED_MCP_EEE_DISABLED;\n\t\t\tlink->eee.enable = false;\n\t\t\tbreak;\n\t\tcase NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:\n\t\t\tp_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;\n\t\t\tbreak;\n\t\tcase NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:\n\t\t\tp_caps->eee_lpi_timer =\n\t\t\t    EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;\n\t\t\tbreak;\n\t\tcase NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:\n\t\t\tp_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;\n\t\t\tbreak;\n\t\t}\n\n\t\tlink->eee.tx_lpi_timer = p_caps->eee_lpi_timer;\n\t\tlink->eee.tx_lpi_enable = link->eee.enable;\n\t\tlink->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;\n\t} else {\n\t\tp_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;\n\t}\n\n\tif (p_hwfn->mcp_info->capabilities &\n\t    FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) {\n\t\text_speed = &link->ext_speed;\n\n\t\tlink_temp = qed_rd(p_hwfn, p_ptt,\n\t\t\t\t   port_cfg_addr +\n\t\t\t\t   offsetof(struct nvm_cfg1_port,\n\t\t\t\t\t    extended_speed));\n\n\t\tfld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_EXTENDED_SPEED);\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN)\n\t\t\text_speed->autoneg = true;\n\n\t\text_speed->forced_speed = 0;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_1G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_10G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_20G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_25G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_40G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_50G_R;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_50G_R2;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_100G_R2;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_100G_R4;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4)\n\t\t\text_speed->forced_speed |= QED_EXT_SPEED_100G_P4;\n\n\t\tfld = GET_MFW_FIELD(link_temp,\n\t\t\t\t    NVM_CFG1_PORT_EXTENDED_SPEED_CAP);\n\n\t\text_speed->advertised_speeds = 0;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED)\n\t\t\text_speed->advertised_speeds |= QED_EXT_SPEED_MASK_RES;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G)\n\t\t\text_speed->advertised_speeds |= QED_EXT_SPEED_MASK_1G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G)\n\t\t\text_speed->advertised_speeds |= QED_EXT_SPEED_MASK_10G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G)\n\t\t\text_speed->advertised_speeds |= QED_EXT_SPEED_MASK_20G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G)\n\t\t\text_speed->advertised_speeds |= QED_EXT_SPEED_MASK_25G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G)\n\t\t\text_speed->advertised_speeds |= QED_EXT_SPEED_MASK_40G;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R)\n\t\t\text_speed->advertised_speeds |=\n\t\t\t\tQED_EXT_SPEED_MASK_50G_R;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2)\n\t\t\text_speed->advertised_speeds |=\n\t\t\t\tQED_EXT_SPEED_MASK_50G_R2;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2)\n\t\t\text_speed->advertised_speeds |=\n\t\t\t\tQED_EXT_SPEED_MASK_100G_R2;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4)\n\t\t\text_speed->advertised_speeds |=\n\t\t\t\tQED_EXT_SPEED_MASK_100G_R4;\n\t\tif (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4)\n\t\t\text_speed->advertised_speeds |=\n\t\t\t\tQED_EXT_SPEED_MASK_100G_P4;\n\n\t\tlink_temp = qed_rd(p_hwfn, p_ptt,\n\t\t\t\t   port_cfg_addr +\n\t\t\t\t   offsetof(struct nvm_cfg1_port,\n\t\t\t\t\t    extended_fec_mode));\n\t\tlink->ext_fec_mode = link_temp;\n\n\t\tp_caps->default_ext_speed_caps = ext_speed->advertised_speeds;\n\t\tp_caps->default_ext_speed = ext_speed->forced_speed;\n\t\tp_caps->default_ext_autoneg = ext_speed->autoneg;\n\t\tp_caps->default_ext_fec = link->ext_fec_mode;\n\n\t\tDP_VERBOSE(p_hwfn, NETIF_MSG_LINK,\n\t\t\t   \"Read default extended link config: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, FEC: 0x%02x\\n\",\n\t\t\t   ext_speed->forced_speed,\n\t\t\t   ext_speed->advertised_speeds, ext_speed->autoneg,\n\t\t\t   p_caps->default_ext_fec);\n\t}\n\n\tDP_VERBOSE(p_hwfn, NETIF_MSG_LINK,\n\t\t   \"Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x, EEE: 0x%02x [0x%08x usec], FEC: 0x%02x\\n\",\n\t\t   link->speed.forced_speed, link->speed.advertised_speeds,\n\t\t   link->speed.autoneg, link->pause.autoneg,\n\t\t   p_caps->default_eee, p_caps->eee_lpi_timer,\n\t\t   p_caps->fec_default);\n\n\tif (IS_LEAD_HWFN(p_hwfn)) {\n\t\tstruct qed_dev *cdev = p_hwfn->cdev;\n\n\t\t/* Read Multi-function information from shmem */\n\t\taddr = MCP_REG_SCRATCH + nvm_cfg1_offset +\n\t\t       offsetof(struct nvm_cfg1, glob) +\n\t\t       offsetof(struct nvm_cfg1_glob, generic_cont0);\n\n\t\tgeneric_cont0 = qed_rd(p_hwfn, p_ptt, addr);\n\n\t\tmf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>\n\t\t\t  NVM_CFG1_GLOB_MF_MODE_OFFSET;\n\n\t\tswitch (mf_mode) {\n\t\tcase NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:\n\t\t\tcdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);\n\t\t\tbreak;\n\t\tcase NVM_CFG1_GLOB_MF_MODE_UFP:\n\t\t\tcdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |\n\t\t\t\t\tBIT(QED_MF_LLH_PROTO_CLSS) |\n\t\t\t\t\tBIT(QED_MF_UFP_SPECIFIC) |\n\t\t\t\t\tBIT(QED_MF_8021Q_TAGGING) |\n\t\t\t\t\tBIT(QED_MF_DONT_ADD_VLAN0_TAG);\n\t\t\tbreak;\n\t\tcase NVM_CFG1_GLOB_MF_MODE_BD:\n\t\t\tcdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |\n\t\t\t\t\tBIT(QED_MF_LLH_PROTO_CLSS) |\n\t\t\t\t\tBIT(QED_MF_8021AD_TAGGING) |\n\t\t\t\t\tBIT(QED_MF_DONT_ADD_VLAN0_TAG);\n\t\t\tbreak;\n\t\tcase NVM_CFG1_GLOB_MF_MODE_NPAR1_0:\n\t\t\tcdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |\n\t\t\t\t\tBIT(QED_MF_LLH_PROTO_CLSS) |\n\t\t\t\t\tBIT(QED_MF_LL2_NON_UNICAST) |\n\t\t\t\t\tBIT(QED_MF_INTER_PF_SWITCH) |\n\t\t\t\t\tBIT(QED_MF_DISABLE_ARFS);\n\t\t\tbreak;\n\t\tcase NVM_CFG1_GLOB_MF_MODE_DEFAULT:\n\t\t\tcdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |\n\t\t\t\t\tBIT(QED_MF_LLH_PROTO_CLSS) |\n\t\t\t\t\tBIT(QED_MF_LL2_NON_UNICAST);\n\t\t\tif (QED_IS_BB(p_hwfn->cdev))\n\t\t\t\tcdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);\n\t\t\tbreak;\n\t\t}\n\n\t\tDP_INFO(p_hwfn, \"Multi function mode is 0x%lx\\n\",\n\t\t\tcdev->mf_bits);\n\n\t\t/* In CMT the PF is unknown when the GFS block processes the\n\t\t * packet. Therefore cannot use searcher as it has a per PF\n\t\t * database, and thus ARFS must be disabled.\n\t\t *\n\t\t */\n\t\tif (QED_IS_CMT(cdev))\n\t\t\tcdev->mf_bits |= BIT(QED_MF_DISABLE_ARFS);\n\t}\n\n\tDP_INFO(p_hwfn, \"Multi function mode is 0x%lx\\n\",\n\t\tp_hwfn->cdev->mf_bits);\n\n\t/* Read device capabilities information from shmem */\n\taddr = MCP_REG_SCRATCH + nvm_cfg1_offset +\n\t\toffsetof(struct nvm_cfg1, glob) +\n\t\toffsetof(struct nvm_cfg1_glob, device_capabilities);\n\n\tdevice_capabilities = qed_rd(p_hwfn, p_ptt, addr);\n\tif (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)\n\t\t__set_bit(QED_DEV_CAP_ETH,\n\t\t\t  &p_hwfn->hw_info.device_capabilities);\n\tif (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)\n\t\t__set_bit(QED_DEV_CAP_FCOE,\n\t\t\t  &p_hwfn->hw_info.device_capabilities);\n\tif (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)\n\t\t__set_bit(QED_DEV_CAP_ISCSI,\n\t\t\t  &p_hwfn->hw_info.device_capabilities);\n\tif (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)\n\t\t__set_bit(QED_DEV_CAP_ROCE,\n\t\t\t  &p_hwfn->hw_info.device_capabilities);\n\n\t/* Read device serial number information from shmem */\n\taddr = MCP_REG_SCRATCH + nvm_cfg1_offset +\n\t\toffsetof(struct nvm_cfg1, glob) +\n\t\toffsetof(struct nvm_cfg1_glob, serial_number);\n\n\tfor (i = 0; i < 4; i++)\n\t\tp_hwfn->hw_info.part_num[i] = qed_rd(p_hwfn, p_ptt, addr + i * 4);\n\n\treturn qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);\n}",
        "static void dbAdjTree(dmtree_t * tp, int leafno, int newval)\n{\n\tint lp, pp, k;\n\tint max;\n": "static void dbAdjTree(dmtree_t * tp, int leafno, int newval)\n{\n\tint lp, pp, k;\n\tint max;\n\n\t/* pick up the index of the leaf for this leafno.\n\t */\n\tlp = leafno + le32_to_cpu(tp->dmt_leafidx);\n\n\t/* is the current value the same as the old value ?  if so,\n\t * there is nothing to do.\n\t */\n\tif (tp->dmt_stree[lp] == newval)\n\t\treturn;\n\n\t/* set the new value.\n\t */\n\ttp->dmt_stree[lp] = newval;\n\n\t/* bubble the new value up the tree as required.\n\t */\n\tfor (k = 0; k < le32_to_cpu(tp->dmt_height); k++) {\n\t\t/* get the index of the first leaf of the 4 leaf\n\t\t * group containing the specified leaf (leafno).\n\t\t */\n\t\tlp = ((lp - 1) & ~0x03) + 1;\n\n\t\t/* get the index of the parent of this 4 leaf group.\n\t\t */\n\t\tpp = (lp - 1) >> 2;\n\n\t\t/* determine the maximum of the 4 leaves.\n\t\t */\n\t\tmax = TREEMAX(&tp->dmt_stree[lp]);\n\n\t\t/* if the maximum of the 4 is the same as the\n\t\t * parent's value, we're done.\n\t\t */\n\t\tif (tp->dmt_stree[pp] == max)\n\t\t\tbreak;\n\n\t\t/* parent gets new value.\n\t\t */\n\t\ttp->dmt_stree[pp] = max;\n\n\t\t/* parent becomes leaf for next go-round.\n\t\t */\n\t\tlp = pp;\n\t}\n}",
        "static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)\n{\n\tstruct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);\n\tu32 p; /* panic code */\n\tint ret;": "static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)\n{\n\tstruct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);\n\tu32 p; /* panic code */\n\tint ret;\n\n\t/* Read the message from the debug box. */\n\tsof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,\n\t\t\t &p, sizeof(p));\n\n\t/* Check to see if the message is a panic code 0x0dead*** */\n\tif ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {\n\t\tsnd_sof_dsp_panic(priv->sdev, p, true);\n\t} else {\n\t\tsnd_sof_ipc_msgs_rx(priv->sdev);\n\n\t\t/* tell DSP cmd is done */\n\t\tret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);\n\t\tif (ret)\n\t\t\tdev_err(priv->dev, \"request send ipc failed\");\n\t}\n}",
        "static int qup_i2c_probe(struct platform_device *pdev)\n{\n\tstatic const int blk_sizes[] = {4, 16, 32};\n\tstruct qup_i2c_dev *qup;\n\tunsigned long one_bit_t;": "static int qup_i2c_probe(struct platform_device *pdev)\n{\n\tstatic const int blk_sizes[] = {4, 16, 32};\n\tstruct qup_i2c_dev *qup;\n\tunsigned long one_bit_t;\n\tu32 io_mode, hw_ver, size;\n\tint ret, fs_div, hs_div;\n\tu32 src_clk_freq = DEFAULT_SRC_CLK;\n\tu32 clk_freq = DEFAULT_CLK_FREQ;\n\tint blocks;\n\tbool is_qup_v1;\n\n\tqup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);\n\tif (!qup)\n\t\treturn -ENOMEM;\n\n\tqup->dev = &pdev->dev;\n\tinit_completion(&qup->xfer);\n\tplatform_set_drvdata(pdev, qup);\n\n\tif (scl_freq) {\n\t\tdev_notice(qup->dev, \"Using override frequency of %u\\n\", scl_freq);\n\t\tclk_freq = scl_freq;\n\t} else {\n\t\tret = device_property_read_u32(qup->dev, \"clock-frequency\", &clk_freq);\n\t\tif (ret) {\n\t\t\tdev_notice(qup->dev, \"using default clock-frequency %d\",\n\t\t\t\tDEFAULT_CLK_FREQ);\n\t\t}\n\t}\n\n\tif (of_device_is_compatible(pdev->dev.of_node, \"qcom,i2c-qup-v1.1.1\")) {\n\t\tqup->adap.algo = &qup_i2c_algo;\n\t\tqup->adap.quirks = &qup_i2c_quirks;\n\t\tis_qup_v1 = true;\n\t} else {\n\t\tqup->adap.algo = &qup_i2c_algo_v2;\n\t\tqup->adap.quirks = &qup_i2c_quirks_v2;\n\t\tis_qup_v1 = false;\n\t\tif (acpi_match_device(qup_i2c_acpi_match, qup->dev))\n\t\t\tgoto nodma;\n\t\telse\n\t\t\tret = qup_i2c_req_dma(qup);\n\n\t\tif (ret == -EPROBE_DEFER)\n\t\t\tgoto fail_dma;\n\t\telse if (ret != 0)\n\t\t\tgoto nodma;\n\n\t\tqup->max_xfer_sg_len = (MX_BLOCKS << 1);\n\t\tblocks = (MX_DMA_BLOCKS << 1) + 1;\n\t\tqup->btx.sg = devm_kcalloc(&pdev->dev,\n\t\t\t\t\t   blocks, sizeof(*qup->btx.sg),\n\t\t\t\t\t   GFP_KERNEL);\n\t\tif (!qup->btx.sg) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto fail_dma;\n\t\t}\n\t\tsg_init_table(qup->btx.sg, blocks);\n\n\t\tqup->brx.sg = devm_kcalloc(&pdev->dev,\n\t\t\t\t\t   blocks, sizeof(*qup->brx.sg),\n\t\t\t\t\t   GFP_KERNEL);\n\t\tif (!qup->brx.sg) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto fail_dma;\n\t\t}\n\t\tsg_init_table(qup->brx.sg, blocks);\n\n\t\t/* 2 tag bytes for each block + 5 for start, stop tags */\n\t\tsize = blocks * 2 + 5;\n\n\t\tqup->start_tag.start = devm_kzalloc(&pdev->dev,\n\t\t\t\t\t\t    size, GFP_KERNEL);\n\t\tif (!qup->start_tag.start) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto fail_dma;\n\t\t}\n\n\t\tqup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);\n\t\tif (!qup->brx.tag.start) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto fail_dma;\n\t\t}\n\n\t\tqup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);\n\t\tif (!qup->btx.tag.start) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto fail_dma;\n\t\t}\n\t\tqup->is_dma = true;\n\t}\n\nnodma:\n\t/* We support frequencies up to FAST Mode Plus (1MHz) */\n\tif (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {\n\t\tdev_err(qup->dev, \"clock frequency not supported %d\\n\",\n\t\t\tclk_freq);\n\t\treturn -EINVAL;\n\t}\n\n\tqup->base = devm_platform_ioremap_resource(pdev, 0);\n\tif (IS_ERR(qup->base))\n\t\treturn PTR_ERR(qup->base);\n\n\tqup->irq = platform_get_irq(pdev, 0);\n\tif (qup->irq < 0)\n\t\treturn qup->irq;\n\n\tif (has_acpi_companion(qup->dev)) {\n\t\tret = device_property_read_u32(qup->dev,\n\t\t\t\t\"src-clock-hz\", &src_clk_freq);\n\t\tif (ret) {\n\t\t\tdev_notice(qup->dev, \"using default src-clock-hz %d\",\n\t\t\t\tDEFAULT_SRC_CLK);\n\t\t}\n\t\tACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));\n\t} else {\n\t\tqup->clk = devm_clk_get(qup->dev, \"core\");\n\t\tif (IS_ERR(qup->clk)) {\n\t\t\tdev_err(qup->dev, \"Could not get core clock\\n\");\n\t\t\treturn PTR_ERR(qup->clk);\n\t\t}\n\n\t\tqup->pclk = devm_clk_get(qup->dev, \"iface\");\n\t\tif (IS_ERR(qup->pclk)) {\n\t\t\tdev_err(qup->dev, \"Could not get iface clock\\n\");\n\t\t\treturn PTR_ERR(qup->pclk);\n\t\t}\n\t\tqup_i2c_enable_clocks(qup);\n\t\tsrc_clk_freq = clk_get_rate(qup->clk);\n\t}\n\n\t/*\n\t * Bootloaders might leave a pending interrupt on certain QUP's,\n\t * so we reset the core before registering for interrupts.\n\t */\n\twritel(1, qup->base + QUP_SW_RESET);\n\tret = qup_i2c_poll_state_valid(qup);\n\tif (ret)\n\t\tgoto fail;\n\n\tret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,\n\t\t\t       IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,\n\t\t\t       \"i2c_qup\", qup);\n\tif (ret) {\n\t\tdev_err(qup->dev, \"Request %d IRQ failed\\n\", qup->irq);\n\t\tgoto fail;\n\t}\n\n\thw_ver = readl(qup->base + QUP_HW_VERSION);\n\tdev_dbg(qup->dev, \"Revision %x\\n\", hw_ver);\n\n\tio_mode = readl(qup->base + QUP_IO_MODE);\n\n\t/*\n\t * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'\n\t * associated with each byte written/received\n\t */\n\tsize = QUP_OUTPUT_BLOCK_SIZE(io_mode);\n\tif (size >= ARRAY_SIZE(blk_sizes)) {\n\t\tret = -EIO;\n\t\tgoto fail;\n\t}\n\tqup->out_blk_sz = blk_sizes[size];\n\n\tsize = QUP_INPUT_BLOCK_SIZE(io_mode);\n\tif (size >= ARRAY_SIZE(blk_sizes)) {\n\t\tret = -EIO;\n\t\tgoto fail;\n\t}\n\tqup->in_blk_sz = blk_sizes[size];\n\n\tif (is_qup_v1) {\n\t\t/*\n\t\t * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a\n\t\t * single transfer but the block size is in bytes so divide the\n\t\t * in_blk_sz and out_blk_sz by 2\n\t\t */\n\t\tqup->in_blk_sz /= 2;\n\t\tqup->out_blk_sz /= 2;\n\t\tqup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;\n\t\tqup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;\n\t\tqup->write_rx_tags = qup_i2c_write_rx_tags_v1;\n\t} else {\n\t\tqup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;\n\t\tqup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;\n\t\tqup->write_rx_tags = qup_i2c_write_rx_tags_v2;\n\t}\n\n\tsize = QUP_OUTPUT_FIFO_SIZE(io_mode);\n\tqup->out_fifo_sz = qup->out_blk_sz * (2 << size);\n\n\tsize = QUP_INPUT_FIFO_SIZE(io_mode);\n\tqup->in_fifo_sz = qup->in_blk_sz * (2 << size);\n\n\ths_div = 3;\n\tif (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {\n\t\tfs_div = ((src_clk_freq / clk_freq) / 2) - 3;\n\t\tqup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);\n\t} else {\n\t\t/* 33%/66% duty cycle */\n\t\tfs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;\n\t\tqup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);\n\t}\n\n\t/*\n\t * Time it takes for a byte to be clocked out on the bus.\n\t * Each byte takes 9 clock cycles (8 bits + 1 ack).\n\t */\n\tone_bit_t = (USEC_PER_SEC / clk_freq) + 1;\n\tqup->one_byte_t = one_bit_t * 9;\n\tqup->xfer_timeout = TOUT_MIN * HZ +\n\t\tusecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);\n\n\tdev_dbg(qup->dev, \"IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\\n\",\n\t\tqup->in_blk_sz, qup->in_fifo_sz,\n\t\tqup->out_blk_sz, qup->out_fifo_sz);\n\n\ti2c_set_adapdata(&qup->adap, qup);\n\tqup->adap.dev.parent = qup->dev;\n\tqup->adap.dev.of_node = pdev->dev.of_node;\n\tqup->is_last = true;\n\n\tstrlcpy(qup->adap.name, \"QUP I2C adapter\", sizeof(qup->adap.name));\n\n\tpm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);\n\tpm_runtime_use_autosuspend(qup->dev);\n\tpm_runtime_set_active(qup->dev);\n\tpm_runtime_enable(qup->dev);\n\n\tret = i2c_add_adapter(&qup->adap);\n\tif (ret)\n\t\tgoto fail_runtime;\n\n\treturn 0;\n\nfail_runtime:\n\tpm_runtime_disable(qup->dev);\n\tpm_runtime_set_suspended(qup->dev);\nfail:\n\tqup_i2c_disable_clocks(qup);\nfail_dma:\n\tif (qup->btx.dma)\n\t\tdma_release_channel(qup->btx.dma);\n\tif (qup->brx.dma)\n\t\tdma_release_channel(qup->brx.dma);\n\treturn ret;\n}",
        "static void __evlist__disable(struct evlist *evlist, char *evsel_name)\n{\n\tstruct evsel *pos;\n\tstruct evlist_cpu_iterator evlist_cpu_itr;\n\tstruct affinity saved_affinity, *affinity = NULL;": "static void __evlist__disable(struct evlist *evlist, char *evsel_name)\n{\n\tstruct evsel *pos;\n\tstruct evlist_cpu_iterator evlist_cpu_itr;\n\tstruct affinity saved_affinity, *affinity = NULL;\n\tbool has_imm = false;\n\n\t// See explanation in evlist__close()\n\tif (!cpu_map__is_dummy(evlist->core.user_requested_cpus)) {\n\t\tif (affinity__setup(&saved_affinity) < 0)\n\t\t\treturn;\n\t\taffinity = &saved_affinity;\n\t}\n\n\t/* Disable 'immediate' events last */\n\tfor (int imm = 0; imm <= 1; imm++) {\n\t\tevlist__for_each_cpu(evlist_cpu_itr, evlist, affinity) {\n\t\t\tpos = evlist_cpu_itr.evsel;\n\t\t\tif (evsel__strcmp(pos, evsel_name))\n\t\t\t\tcontinue;\n\t\t\tif (pos->disabled || !evsel__is_group_leader(pos) || !pos->core.fd)\n\t\t\t\tcontinue;\n\t\t\tif (pos->immediate)\n\t\t\t\thas_imm = true;\n\t\t\tif (pos->immediate != imm)\n\t\t\t\tcontinue;\n\t\t\tevsel__disable_cpu(pos, evlist_cpu_itr.cpu_map_idx);\n\t\t}\n\t\tif (!has_imm)\n\t\t\tbreak;\n\t}\n\n\taffinity__cleanup(affinity);\n\tevlist__for_each_entry(evlist, pos) {\n\t\tif (evsel__strcmp(pos, evsel_name))\n\t\t\tcontinue;\n\t\tif (!evsel__is_group_leader(pos) || !pos->core.fd)\n\t\t\tcontinue;\n\t\tpos->disabled = true;\n\t}\n\n\t/*\n\t * If we disabled only single event, we need to check\n\t * the enabled state of the evlist manually.\n\t */\n\tif (evsel_name)\n\t\tevlist->enabled = evlist__is_enabled(evlist);\n\telse\n\t\tevlist->enabled = false;\n}",
        "static void envelope_detector_setup_compare(struct envelope *env)\n{\n\tint ret;\n\n\t/*": "static void envelope_detector_setup_compare(struct envelope *env)\n{\n\tint ret;\n\n\t/*\n\t * Do a binary search for the peak input level, and stop\n\t * when that level is \"trapped\" between two adjacent DAC\n\t * values.\n\t * When invert is active, use the midpoint floor so that\n\t * env->level ends up as env->low when the termination\n\t * criteria below is fulfilled, and use the midpoint\n\t * ceiling when invert is not active so that env->level\n\t * ends up as env->high in that case.\n\t */\n\tenv->level = (env->high + env->low + !env->invert) / 2;\n\n\tif (env->high == env->low + 1) {\n\t\tcomplete(&env->done);\n\t\treturn;\n\t}\n\n\t/* Set a \"safe\" DAC level (if there is such a thing)... */\n\tret = iio_write_channel_raw(env->dac, env->invert ? 0 : env->dac_max);\n\tif (ret < 0)\n\t\tgoto err;\n\n\t/* ...clear the comparison result... */\n\tenvelope_detector_comp_latch(env);\n\n\t/* ...set the real DAC level... */\n\tret = iio_write_channel_raw(env->dac, env->level);\n\tif (ret < 0)\n\t\tgoto err;\n\n\t/* ...and wait for a bit to see if the latch catches anything. */\n\tschedule_delayed_work(&env->comp_timeout,\n\t\t\t      msecs_to_jiffies(env->comp_interval));\n\treturn;\n\nerr:\n\tenv->level = ret;\n\tcomplete(&env->done);\n}",
        "static int netdev_queue_add_kobject(struct net_device *dev, int index)\n{\n\tstruct netdev_queue *queue = dev->_tx + index;\n\tstruct kobject *kobj = &queue->kobj;\n\tint error = 0;": "static int netdev_queue_add_kobject(struct net_device *dev, int index)\n{\n\tstruct netdev_queue *queue = dev->_tx + index;\n\tstruct kobject *kobj = &queue->kobj;\n\tint error = 0;\n\n\t/* Kobject_put later will trigger netdev_queue_release call\n\t * which decreases dev refcount: Take that reference here\n\t */\n\tdev_hold_track(queue->dev, &queue->dev_tracker, GFP_KERNEL);\n\n\tkobj->kset = dev->queues_kset;\n\terror = kobject_init_and_add(kobj, &netdev_queue_ktype, NULL,\n\t\t\t\t     \"tx-%u\", index);\n\tif (error)\n\t\tgoto err;\n\n#ifdef CONFIG_BQL\n\terror = sysfs_create_group(kobj, &dql_group);\n\tif (error)\n\t\tgoto err;\n#endif\n\n\tkobject_uevent(kobj, KOBJ_ADD);\n\treturn 0;\n\nerr:\n\tkobject_put(kobj);\n\treturn error;\n}",
        "static void ccid3_hc_tx_update_x(struct sock *sk, ktime_t *stamp)\n{\n\tstruct ccid3_hc_tx_sock *hc = ccid3_hc_tx_sk(sk);\n\t__u64 min_rate = 2 * hc->tx_x_recv;\n\tconst __u64 old_x = hc->tx_x;": "static void ccid3_hc_tx_update_x(struct sock *sk, ktime_t *stamp)\n{\n\tstruct ccid3_hc_tx_sock *hc = ccid3_hc_tx_sk(sk);\n\t__u64 min_rate = 2 * hc->tx_x_recv;\n\tconst __u64 old_x = hc->tx_x;\n\tktime_t now = stamp ? *stamp : ktime_get_real();\n\n\t/*\n\t * Handle IDLE periods: do not reduce below RFC3390 initial sending rate\n\t * when idling [RFC 4342, 5.1]. Definition of idling is from rfc3448bis:\n\t * a sender is idle if it has not sent anything over a 2-RTT-period.\n\t * For consistency with X and X_recv, min_rate is also scaled by 2^6.\n\t */\n\tif (ccid3_hc_tx_idle_rtt(hc, now) >= 2) {\n\t\tmin_rate = rfc3390_initial_rate(sk);\n\t\tmin_rate = max(min_rate, 2 * hc->tx_x_recv);\n\t}\n\n\tif (hc->tx_p > 0) {\n\n\t\thc->tx_x = min(((__u64)hc->tx_x_calc) << 6, min_rate);\n\t\thc->tx_x = max(hc->tx_x, (((__u64)hc->tx_s) << 6) / TFRC_T_MBI);\n\n\t} else if (ktime_us_delta(now, hc->tx_t_ld) - (s64)hc->tx_rtt >= 0) {\n\n\t\thc->tx_x = min(2 * hc->tx_x, min_rate);\n\t\thc->tx_x = max(hc->tx_x,\n\t\t\t       scaled_div(((__u64)hc->tx_s) << 6, hc->tx_rtt));\n\t\thc->tx_t_ld = now;\n\t}\n\n\tif (hc->tx_x != old_x) {\n\t\tccid3_pr_debug(\"X_prev=%u, X_now=%u, X_calc=%u, \"\n\t\t\t       \"X_recv=%u\\n\", (unsigned int)(old_x >> 6),\n\t\t\t       (unsigned int)(hc->tx_x >> 6), hc->tx_x_calc,\n\t\t\t       (unsigned int)(hc->tx_x_recv >> 6));\n\n\t\tccid3_update_send_interval(hc);\n\t}\n}",
        "static int hydra_init(struct zorro_dev *z)\n{\n    struct net_device *dev;\n    unsigned long board = (unsigned long)ZTWO_VADDR(z->resource.start);\n    unsigned long ioaddr = board+HYDRA_NIC_BASE;": "static int hydra_init(struct zorro_dev *z)\n{\n    struct net_device *dev;\n    unsigned long board = (unsigned long)ZTWO_VADDR(z->resource.start);\n    unsigned long ioaddr = board+HYDRA_NIC_BASE;\n    const char name[] = \"NE2000\";\n    int start_page, stop_page;\n    u8 macaddr[ETH_ALEN];\n    int j;\n    int err;\n\n    static u32 hydra_offsets[16] = {\n\t0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,\n\t0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,\n    };\n\n    dev = ____alloc_ei_netdev(0);\n    if (!dev)\n\treturn -ENOMEM;\n\n    for (j = 0; j < ETH_ALEN; j++)\n\tmacaddr[j] = *((u8 *)(board + HYDRA_ADDRPROM + 2*j));\n    eth_hw_addr_set(dev, macaddr);\n\n    /* We must set the 8390 for word mode. */\n    z_writeb(0x4b, ioaddr + NE_EN0_DCFG);\n    start_page = NESM_START_PG;\n    stop_page = NESM_STOP_PG;\n\n    dev->base_addr = ioaddr;\n    dev->irq = IRQ_AMIGA_PORTS;\n\n    /* Install the Interrupt handler */\n    if (request_irq(IRQ_AMIGA_PORTS, __ei_interrupt, IRQF_SHARED, \"Hydra Ethernet\",\n\t\t    dev)) {\n\tfree_netdev(dev);\n\treturn -EAGAIN;\n    }\n\n    ei_status.name = name;\n    ei_status.tx_start_page = start_page;\n    ei_status.stop_page = stop_page;\n    ei_status.word16 = 1;\n    ei_status.bigendian = 1;\n\n    ei_status.rx_start_page = start_page + TX_PAGES;\n\n    ei_status.reset_8390 = hydra_reset_8390;\n    ei_status.block_input = hydra_block_input;\n    ei_status.block_output = hydra_block_output;\n    ei_status.get_8390_hdr = hydra_get_8390_hdr;\n    ei_status.reg_offset = hydra_offsets;\n\n    dev->netdev_ops = &hydra_netdev_ops;\n    __NS8390_init(dev, 0);\n\n    err = register_netdev(dev);\n    if (err) {\n\tfree_irq(IRQ_AMIGA_PORTS, dev);\n\tfree_netdev(dev);\n\treturn err;\n    }\n\n    zorro_set_drvdata(z, dev);\n\n    pr_info(\"%s: Hydra at %pR, address %pM (hydra.c \" HYDRA_VERSION \")\\n\",\n\t    dev->name, &z->resource, dev->dev_addr);\n\n    return 0;\n}",
        "static void tw5864_frame_interval_set(struct tw5864_input *input)\n{\n\t/*\n\t * This register value seems to follow such approach: In each second\n\t * interval, when processing Nth frame, it checks Nth bit of register": "static void tw5864_frame_interval_set(struct tw5864_input *input)\n{\n\t/*\n\t * This register value seems to follow such approach: In each second\n\t * interval, when processing Nth frame, it checks Nth bit of register\n\t * value and, if the bit is 1, it processes the frame, otherwise the\n\t * frame is discarded.\n\t * So unary representation would work, but more or less equal gaps\n\t * between the frames should be preserved.\n\t *\n\t * For 1 FPS - 0x00000001\n\t * 00000000 00000000 00000000 00000001\n\t *\n\t * For max FPS - set all 25/30 lower bits:\n\t * 00111111 11111111 11111111 11111111 (NTSC)\n\t * 00000001 11111111 11111111 11111111 (PAL)\n\t *\n\t * For half of max FPS - use such pattern:\n\t * 00010101 01010101 01010101 01010101 (NTSC)\n\t * 00000001 01010101 01010101 01010101 (PAL)\n\t *\n\t * Et cetera.\n\t *\n\t * The value supplied to hardware is capped by mask of 25/30 lower bits.\n\t */\n\tstruct tw5864_dev *dev = input->root;\n\tu32 unary_framerate = 0;\n\tint shift = 0;\n\tint std_max_fps = input->std == STD_NTSC ? 30 : 25;\n\n\tfor (shift = 0; shift < std_max_fps; shift += input->frame_interval)\n\t\tunary_framerate |= 0x00000001 << shift;\n\n\ttw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),\n\t\t  unary_framerate >> 16);\n\ttw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),\n\t\t  unary_framerate & 0xffff);\n}",
        "static void ccid2_hc_tx_packet_recv(struct sock *sk, struct sk_buff *skb)\n{\n\tstruct dccp_sock *dp = dccp_sk(sk);\n\tstruct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);\n\tconst bool sender_was_blocked = ccid2_cwnd_network_limited(hc);": "static void ccid2_hc_tx_packet_recv(struct sock *sk, struct sk_buff *skb)\n{\n\tstruct dccp_sock *dp = dccp_sk(sk);\n\tstruct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);\n\tconst bool sender_was_blocked = ccid2_cwnd_network_limited(hc);\n\tstruct dccp_ackvec_parsed *avp;\n\tu64 ackno, seqno;\n\tstruct ccid2_seq *seqp;\n\tint done = 0;\n\tunsigned int maxincr = 0;\n\n\t/* check reverse path congestion */\n\tseqno = DCCP_SKB_CB(skb)->dccpd_seq;\n\n\t/* XXX this whole \"algorithm\" is broken.  Need to fix it to keep track\n\t * of the seqnos of the dupacks so that rpseq and rpdupack are correct\n\t * -sorbo.\n\t */\n\t/* need to bootstrap */\n\tif (hc->tx_rpdupack == -1) {\n\t\thc->tx_rpdupack = 0;\n\t\thc->tx_rpseq    = seqno;\n\t} else {\n\t\t/* check if packet is consecutive */\n\t\tif (dccp_delta_seqno(hc->tx_rpseq, seqno) == 1)\n\t\t\thc->tx_rpseq = seqno;\n\t\t/* it's a later packet */\n\t\telse if (after48(seqno, hc->tx_rpseq)) {\n\t\t\thc->tx_rpdupack++;\n\n\t\t\t/* check if we got enough dupacks */\n\t\t\tif (hc->tx_rpdupack >= NUMDUPACK) {\n\t\t\t\thc->tx_rpdupack = -1; /* XXX lame */\n\t\t\t\thc->tx_rpseq    = 0;\n#ifdef __CCID2_COPES_GRACEFULLY_WITH_ACK_CONGESTION_CONTROL__\n\t\t\t\t/*\n\t\t\t\t * FIXME: Ack Congestion Control is broken; in\n\t\t\t\t * the current state instabilities occurred with\n\t\t\t\t * Ack Ratios greater than 1; causing hang-ups\n\t\t\t\t * and long RTO timeouts. This needs to be fixed\n\t\t\t\t * before opening up dynamic changes. -- gerrit\n\t\t\t\t */\n\t\t\t\tccid2_change_l_ack_ratio(sk, 2 * dp->dccps_l_ack_ratio);\n#endif\n\t\t\t}\n\t\t}\n\t}\n\n\t/* check forward path congestion */\n\tif (dccp_packet_without_ack(skb))\n\t\treturn;\n\n\t/* still didn't send out new data packets */\n\tif (hc->tx_seqh == hc->tx_seqt)\n\t\tgoto done;\n\n\tackno = DCCP_SKB_CB(skb)->dccpd_ack_seq;\n\tif (after48(ackno, hc->tx_high_ack))\n\t\thc->tx_high_ack = ackno;\n\n\tseqp = hc->tx_seqt;\n\twhile (before48(seqp->ccid2s_seq, ackno)) {\n\t\tseqp = seqp->ccid2s_next;\n\t\tif (seqp == hc->tx_seqh) {\n\t\t\tseqp = hc->tx_seqh->ccid2s_prev;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*\n\t * In slow-start, cwnd can increase up to a maximum of Ack Ratio/2\n\t * packets per acknowledgement. Rounding up avoids that cwnd is not\n\t * advanced when Ack Ratio is 1 and gives a slight edge otherwise.\n\t */\n\tif (hc->tx_cwnd < hc->tx_ssthresh)\n\t\tmaxincr = DIV_ROUND_UP(dp->dccps_l_ack_ratio, 2);\n\n\t/* go through all ack vectors */\n\tlist_for_each_entry(avp, &hc->tx_av_chunks, node) {\n\t\t/* go through this ack vector */\n\t\tfor (; avp->len--; avp->vec++) {\n\t\t\tu64 ackno_end_rl = SUB48(ackno,\n\t\t\t\t\t\t dccp_ackvec_runlen(avp->vec));\n\n\t\t\tccid2_pr_debug(\"ackvec %llu |%u,%u|\\n\",\n\t\t\t\t       (unsigned long long)ackno,\n\t\t\t\t       dccp_ackvec_state(avp->vec) >> 6,\n\t\t\t\t       dccp_ackvec_runlen(avp->vec));\n\t\t\t/* if the seqno we are analyzing is larger than the\n\t\t\t * current ackno, then move towards the tail of our\n\t\t\t * seqnos.\n\t\t\t */\n\t\t\twhile (after48(seqp->ccid2s_seq, ackno)) {\n\t\t\t\tif (seqp == hc->tx_seqt) {\n\t\t\t\t\tdone = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tseqp = seqp->ccid2s_prev;\n\t\t\t}\n\t\t\tif (done)\n\t\t\t\tbreak;\n\n\t\t\t/* check all seqnos in the range of the vector\n\t\t\t * run length\n\t\t\t */\n\t\t\twhile (between48(seqp->ccid2s_seq,ackno_end_rl,ackno)) {\n\t\t\t\tconst u8 state = dccp_ackvec_state(avp->vec);\n\n\t\t\t\t/* new packet received or marked */\n\t\t\t\tif (state != DCCPAV_NOT_RECEIVED &&\n\t\t\t\t    !seqp->ccid2s_acked) {\n\t\t\t\t\tif (state == DCCPAV_ECN_MARKED)\n\t\t\t\t\t\tccid2_congestion_event(sk,\n\t\t\t\t\t\t\t\t       seqp);\n\t\t\t\t\telse\n\t\t\t\t\t\tccid2_new_ack(sk, seqp,\n\t\t\t\t\t\t\t      &maxincr);\n\n\t\t\t\t\tseqp->ccid2s_acked = 1;\n\t\t\t\t\tccid2_pr_debug(\"Got ack for %llu\\n\",\n\t\t\t\t\t\t       (unsigned long long)seqp->ccid2s_seq);\n\t\t\t\t\thc->tx_pipe--;\n\t\t\t\t}\n\t\t\t\tif (seqp == hc->tx_seqt) {\n\t\t\t\t\tdone = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tseqp = seqp->ccid2s_prev;\n\t\t\t}\n\t\t\tif (done)\n\t\t\t\tbreak;\n\n\t\t\tackno = SUB48(ackno_end_rl, 1);\n\t\t}\n\t\tif (done)\n\t\t\tbreak;\n\t}\n\n\t/* The state about what is acked should be correct now\n\t * Check for NUMDUPACK\n\t */\n\tseqp = hc->tx_seqt;\n\twhile (before48(seqp->ccid2s_seq, hc->tx_high_ack)) {\n\t\tseqp = seqp->ccid2s_next;\n\t\tif (seqp == hc->tx_seqh) {\n\t\t\tseqp = hc->tx_seqh->ccid2s_prev;\n\t\t\tbreak;\n\t\t}\n\t}\n\tdone = 0;\n\twhile (1) {\n\t\tif (seqp->ccid2s_acked) {\n\t\t\tdone++;\n\t\t\tif (done == NUMDUPACK)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (seqp == hc->tx_seqt)\n\t\t\tbreak;\n\t\tseqp = seqp->ccid2s_prev;\n\t}\n\n\t/* If there are at least 3 acknowledgements, anything unacknowledged\n\t * below the last sequence number is considered lost\n\t */\n\tif (done == NUMDUPACK) {\n\t\tstruct ccid2_seq *last_acked = seqp;\n\n\t\t/* check for lost packets */\n\t\twhile (1) {\n\t\t\tif (!seqp->ccid2s_acked) {\n\t\t\t\tccid2_pr_debug(\"Packet lost: %llu\\n\",\n\t\t\t\t\t       (unsigned long long)seqp->ccid2s_seq);\n\t\t\t\t/* XXX need to traverse from tail -> head in\n\t\t\t\t * order to detect multiple congestion events in\n\t\t\t\t * one ack vector.\n\t\t\t\t */\n\t\t\t\tccid2_congestion_event(sk, seqp);\n\t\t\t\thc->tx_pipe--;\n\t\t\t}\n\t\t\tif (seqp == hc->tx_seqt)\n\t\t\t\tbreak;\n\t\t\tseqp = seqp->ccid2s_prev;\n\t\t}\n\n\t\thc->tx_seqt = last_acked;\n\t}\n\n\t/* trim acked packets in tail */\n\twhile (hc->tx_seqt != hc->tx_seqh) {\n\t\tif (!hc->tx_seqt->ccid2s_acked)\n\t\t\tbreak;\n\n\t\thc->tx_seqt = hc->tx_seqt->ccid2s_next;\n\t}\n\n\t/* restart RTO timer if not all outstanding data has been acked */\n\tif (hc->tx_pipe == 0)\n\t\tsk_stop_timer(sk, &hc->tx_rtotimer);\n\telse\n\t\tsk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);\ndone:\n\t/* check if incoming Acks allow pending packets to be sent */\n\tif (sender_was_blocked && !ccid2_cwnd_network_limited(hc))\n\t\tdccp_tasklet_schedule(sk);\n\tdccp_ackvec_parsed_cleanup(&hc->tx_av_chunks);\n}",
        "static int otx2_add_flow_msg(struct otx2_nic *pfvf, struct otx2_flow *flow)\n{\n\tu64 ring_cookie = flow->flow_spec.ring_cookie;\n#ifdef CONFIG_DCB\n\tint vlan_prio, qidx, pfc_rule = 0;": "static int otx2_add_flow_msg(struct otx2_nic *pfvf, struct otx2_flow *flow)\n{\n\tu64 ring_cookie = flow->flow_spec.ring_cookie;\n#ifdef CONFIG_DCB\n\tint vlan_prio, qidx, pfc_rule = 0;\n#endif\n\tstruct npc_install_flow_req *req;\n\tint err, vf = 0;\n\n\tmutex_lock(&pfvf->mbox.lock);\n\treq = otx2_mbox_alloc_msg_npc_install_flow(&pfvf->mbox);\n\tif (!req) {\n\t\tmutex_unlock(&pfvf->mbox.lock);\n\t\treturn -ENOMEM;\n\t}\n\n\terr = otx2_prepare_flow_request(&flow->flow_spec, req);\n\tif (err) {\n\t\t/* free the allocated msg above */\n\t\totx2_mbox_reset(&pfvf->mbox.mbox, 0);\n\t\tmutex_unlock(&pfvf->mbox.lock);\n\t\treturn err;\n\t}\n\n\treq->entry = flow->entry;\n\treq->intf = NIX_INTF_RX;\n\treq->set_cntr = 1;\n\treq->channel = pfvf->hw.rx_chan_base;\n\tif (ring_cookie == RX_CLS_FLOW_DISC) {\n\t\treq->op = NIX_RX_ACTIONOP_DROP;\n\t} else {\n\t\t/* change to unicast only if action of default entry is not\n\t\t * requested by user\n\t\t */\n\t\tif (flow->flow_spec.flow_type & FLOW_RSS) {\n\t\t\treq->op = NIX_RX_ACTIONOP_RSS;\n\t\t\treq->index = flow->rss_ctx_id;\n\t\t\treq->flow_key_alg = pfvf->hw.flowkey_alg_idx;\n\t\t} else {\n\t\t\treq->op = NIX_RX_ACTIONOP_UCAST;\n\t\t\treq->index = ethtool_get_flow_spec_ring(ring_cookie);\n\t\t}\n\t\tvf = ethtool_get_flow_spec_ring_vf(ring_cookie);\n\t\tif (vf > pci_num_vf(pfvf->pdev)) {\n\t\t\tmutex_unlock(&pfvf->mbox.lock);\n\t\t\treturn -EINVAL;\n\t\t}\n\n#ifdef CONFIG_DCB\n\t\t/* Identify PFC rule if PFC enabled and ntuple rule is vlan */\n\t\tif (!vf && (req->features & BIT_ULL(NPC_OUTER_VID)) &&\n\t\t    pfvf->pfc_en && req->op != NIX_RX_ACTIONOP_RSS) {\n\t\t\tvlan_prio = ntohs(req->packet.vlan_tci) &\n\t\t\t\t    ntohs(req->mask.vlan_tci);\n\n\t\t\t/* Get the priority */\n\t\t\tvlan_prio >>= 13;\n\t\t\tflow->rule_type |= PFC_FLOWCTRL_RULE;\n\t\t\t/* Check if PFC enabled for this priority */\n\t\t\tif (pfvf->pfc_en & BIT(vlan_prio)) {\n\t\t\t\tpfc_rule = true;\n\t\t\t\tqidx = req->index;\n\t\t\t}\n\t\t}\n#endif\n\t}\n\n\t/* ethtool ring_cookie has (VF + 1) for VF */\n\tif (vf) {\n\t\treq->vf = vf;\n\t\tflow->is_vf = true;\n\t\tflow->vf = vf;\n\t}\n\n\t/* Send message to AF */\n\terr = otx2_sync_mbox_msg(&pfvf->mbox);\n\n#ifdef CONFIG_DCB\n\tif (!err && pfc_rule)\n\t\totx2_update_bpid_in_rqctx(pfvf, vlan_prio, qidx, true);\n#endif\n\n\tmutex_unlock(&pfvf->mbox.lock);\n\treturn err;\n}",
        "static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct msm8974_icc_node *src_qn, *dst_qn;\n\tstruct msm8974_icc_provider *qp;\n\tu64 sum_bw, max_peak_bw, rate;": "static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct msm8974_icc_node *src_qn, *dst_qn;\n\tstruct msm8974_icc_provider *qp;\n\tu64 sum_bw, max_peak_bw, rate;\n\tu32 agg_avg = 0, agg_peak = 0;\n\tstruct icc_provider *provider;\n\tstruct icc_node *n;\n\tint ret, i;\n\n\tsrc_qn = src->data;\n\tdst_qn = dst->data;\n\tprovider = src->provider;\n\tqp = to_msm8974_icc_provider(provider);\n\n\tlist_for_each_entry(n, &provider->nodes, node_list)\n\t\tprovider->aggregate(n, 0, n->avg_bw, n->peak_bw,\n\t\t\t\t    &agg_avg, &agg_peak);\n\n\tsum_bw = icc_units_to_bps(agg_avg);\n\tmax_peak_bw = icc_units_to_bps(agg_peak);\n\n\t/* Set bandwidth on source node */\n\tmsm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,\n\t\t\t\t src_qn->name, src_qn->mas_rpm_id, sum_bw);\n\n\tmsm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,\n\t\t\t\t src_qn->name, src_qn->slv_rpm_id, sum_bw);\n\n\t/* Set bandwidth on destination node */\n\tmsm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,\n\t\t\t\t dst_qn->name, dst_qn->mas_rpm_id, sum_bw);\n\n\tmsm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,\n\t\t\t\t dst_qn->name, dst_qn->slv_rpm_id, sum_bw);\n\n\trate = max(sum_bw, max_peak_bw);\n\n\tdo_div(rate, src_qn->buswidth);\n\n\trate = min_t(u32, rate, INT_MAX);\n\n\tif (src_qn->rate == rate)\n\t\treturn 0;\n\n\tfor (i = 0; i < qp->num_clks; i++) {\n\t\tret = clk_set_rate(qp->bus_clks[i].clk, rate);\n\t\tif (ret) {\n\t\t\tdev_err(provider->dev, \"%s clk_set_rate error: %d\\n\",\n\t\t\t\tqp->bus_clks[i].id, ret);\n\t\t\tret = 0;\n\t\t}\n\t}\n\n\tsrc_qn->rate = rate;\n\n\treturn 0;\n}",
        "static int task_fn_mbox(struct anybuss_host *cd, struct ab_task *t)\n{\n\tstruct mbox_priv *pd = &t->mbox_pd;\n\tunsigned int ind_ap;\n\tint ret;": "static int task_fn_mbox(struct anybuss_host *cd, struct ab_task *t)\n{\n\tstruct mbox_priv *pd = &t->mbox_pd;\n\tunsigned int ind_ap;\n\tint ret;\n\n\tif (!cd->power_on)\n\t\treturn -EIO;\n\tregmap_read(cd->regmap, REG_IND_AP, &ind_ap);\n\tif ((atomic_read(&cd->ind_ab) ^ ind_ap) & IND_AX_MIN) {\n\t\t/* mbox input area busy */\n\t\tif (time_after(jiffies, t->start_jiffies + TIMEOUT))\n\t\t\treturn -ETIMEDOUT;\n\t\treturn -EINPROGRESS;\n\t}\n\t/* write the header and msg to input area */\n\tregmap_bulk_write(cd->regmap, MBOX_IN_AREA, &pd->hdr,\n\t\t\t  sizeof(pd->hdr));\n\tregmap_bulk_write(cd->regmap, MBOX_IN_AREA + sizeof(pd->hdr),\n\t\t\t  pd->msg, pd->msg_out_sz);\n\t/* tell anybus we gave it a message */\n\tind_ap ^= IND_AX_MIN;\n\tret = write_ind_ap(cd->regmap, ind_ap);\n\tif (ret)\n\t\treturn ret;\n\tt->start_jiffies = jiffies;\n\tt->task_fn = task_fn_mbox_2;\n\treturn -EINPROGRESS;\n}",
        "static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)\n{\n\tunsigned int i, tmp;\n\tint status;\n": "static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)\n{\n\tunsigned int i, tmp;\n\tint status;\n\n\t/* Read active DSPDMAC channel register. */\n\tstatus = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);\n\tif (status >= 0) {\n\t\t/* AND against 0xfff to get the active channel bits. */\n\t\ttmp = tmp & 0xfff;\n\n\t\t/* If there are no active channels, nothing to free. */\n\t\tif (!tmp)\n\t\t\treturn;\n\t} else {\n\t\tcodec_dbg(codec, \"%s: Failed to read active DSP DMA channel register.\\n\",\n\t\t\t\t__func__);\n\t\treturn;\n\t}\n\n\t/*\n\t * Check each DSP DMA channel for activity, and if the channel is\n\t * active, free it.\n\t */\n\tfor (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {\n\t\tif (dsp_is_dma_active(codec, i)) {\n\t\t\tstatus = dspio_free_dma_chan(codec, i);\n\t\t\tif (status < 0)\n\t\t\t\tcodec_dbg(codec, \"%s: Failed to free active DSP DMA channel %d.\\n\",\n\t\t\t\t\t\t__func__, i);\n\t\t}\n\t}\n}",
        "static unsigned int rt711_sdca_button_detect(struct rt711_sdca_priv *rt711)\n{\n\tunsigned int btn_type = 0, offset, idx, val, owner;\n\tint ret;\n\tunsigned char buf[3];": "static unsigned int rt711_sdca_button_detect(struct rt711_sdca_priv *rt711)\n{\n\tunsigned int btn_type = 0, offset, idx, val, owner;\n\tint ret;\n\tunsigned char buf[3];\n\n\t/* get current UMP message owner */\n\tret = regmap_read(rt711->regmap,\n\t\tSDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_CURRENT_OWNER, 0),\n\t\t&owner);\n\tif (ret < 0)\n\t\treturn 0;\n\n\t/* if owner is device then there is no button event from device */\n\tif (owner == 1)\n\t\treturn 0;\n\n\t/* read UMP message offset */\n\tret = regmap_read(rt711->regmap,\n\t\tSDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0),\n\t\t&offset);\n\tif (ret < 0)\n\t\tgoto _end_btn_det_;\n\n\tfor (idx = 0; idx < sizeof(buf); idx++) {\n\t\tret = regmap_read(rt711->regmap,\n\t\t\tRT711_BUF_ADDR_HID1 + offset + idx, &val);\n\t\tif (ret < 0)\n\t\t\tgoto _end_btn_det_;\n\t\tbuf[idx] = val & 0xff;\n\t}\n\n\tif (buf[0] == 0x11) {\n\t\tswitch (buf[1] & 0xf0) {\n\t\tcase 0x10:\n\t\t\tbtn_type |= SND_JACK_BTN_2;\n\t\t\tbreak;\n\t\tcase 0x20:\n\t\t\tbtn_type |= SND_JACK_BTN_3;\n\t\t\tbreak;\n\t\tcase 0x40:\n\t\t\tbtn_type |= SND_JACK_BTN_0;\n\t\t\tbreak;\n\t\tcase 0x80:\n\t\t\tbtn_type |= SND_JACK_BTN_1;\n\t\t\tbreak;\n\t\t}\n\t\tswitch (buf[2]) {\n\t\tcase 0x01:\n\t\tcase 0x10:\n\t\t\tbtn_type |= SND_JACK_BTN_2;\n\t\t\tbreak;\n\t\tcase 0x02:\n\t\tcase 0x20:\n\t\t\tbtn_type |= SND_JACK_BTN_3;\n\t\t\tbreak;\n\t\tcase 0x04:\n\t\tcase 0x40:\n\t\t\tbtn_type |= SND_JACK_BTN_0;\n\t\t\tbreak;\n\t\tcase 0x08:\n\t\tcase 0x80:\n\t\t\tbtn_type |= SND_JACK_BTN_1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n_end_btn_det_:\n\t/* Host is owner, so set back to device */\n\tif (owner == 0)\n\t\t/* set owner to device */\n\t\tregmap_write(rt711->regmap,\n\t\t\tSDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01,\n\t\t\t\tRT711_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE, 0), 0x01);\n\n\treturn btn_type;\n}",
        "static int scftorture_invoker(void *arg)\n{\n\tint cpu;\n\tint curcpu;\n\tDEFINE_TORTURE_RANDOM(rand);": "static int scftorture_invoker(void *arg)\n{\n\tint cpu;\n\tint curcpu;\n\tDEFINE_TORTURE_RANDOM(rand);\n\tstruct scf_statistics *scfp = (struct scf_statistics *)arg;\n\tbool was_offline = false;\n\n\tVERBOSE_SCFTORTOUT(\"scftorture_invoker %d: task started\", scfp->cpu);\n\tcpu = scfp->cpu % nr_cpu_ids;\n\tWARN_ON_ONCE(set_cpus_allowed_ptr(current, cpumask_of(cpu)));\n\tset_user_nice(current, MAX_NICE);\n\tif (holdoff)\n\t\tschedule_timeout_interruptible(holdoff * HZ);\n\n\tVERBOSE_SCFTORTOUT(\"scftorture_invoker %d: Waiting for all SCF torturers from cpu %d\", scfp->cpu, raw_smp_processor_id());\n\n\t// Make sure that the CPU is affinitized appropriately during testing.\n\tcurcpu = raw_smp_processor_id();\n\tWARN_ONCE(curcpu != scfp->cpu % nr_cpu_ids,\n\t\t  \"%s: Wanted CPU %d, running on %d, nr_cpu_ids = %d\\n\",\n\t\t  __func__, scfp->cpu, curcpu, nr_cpu_ids);\n\n\tif (!atomic_dec_return(&n_started))\n\t\twhile (atomic_read_acquire(&n_started)) {\n\t\t\tif (torture_must_stop()) {\n\t\t\t\tVERBOSE_SCFTORTOUT(\"scftorture_invoker %d ended before starting\", scfp->cpu);\n\t\t\t\tgoto end;\n\t\t\t}\n\t\t\tschedule_timeout_uninterruptible(1);\n\t\t}\n\n\tVERBOSE_SCFTORTOUT(\"scftorture_invoker %d started\", scfp->cpu);\n\n\tdo {\n\t\tscftorture_invoke_one(scfp, &rand);\n\t\twhile (cpu_is_offline(cpu) && !torture_must_stop()) {\n\t\t\tschedule_timeout_interruptible(HZ / 5);\n\t\t\twas_offline = true;\n\t\t}\n\t\tif (was_offline) {\n\t\t\tset_cpus_allowed_ptr(current, cpumask_of(cpu));\n\t\t\twas_offline = false;\n\t\t}\n\t\tcond_resched();\n\t\tstutter_wait(\"scftorture_invoker\");\n\t} while (!torture_must_stop());\n\n\tVERBOSE_SCFTORTOUT(\"scftorture_invoker %d ended\", scfp->cpu);\nend:\n\ttorture_kthread_stopping(\"scftorture_invoker\");\n\treturn 0;\n}",
        "static int rs_setup_takeover(struct raid_set *rs)\n{\n\tstruct mddev *mddev = &rs->md;\n\tstruct md_rdev *rdev;\n\tunsigned int d = mddev->raid_disks = rs->raid_disks;": "static int rs_setup_takeover(struct raid_set *rs)\n{\n\tstruct mddev *mddev = &rs->md;\n\tstruct md_rdev *rdev;\n\tunsigned int d = mddev->raid_disks = rs->raid_disks;\n\tsector_t new_data_offset = rs->dev[0].rdev.data_offset ? 0 : rs->data_offset;\n\n\tif (rt_is_raid10(rs->raid_type)) {\n\t\tif (rs_is_raid0(rs)) {\n\t\t\t/* Userpace reordered disks -> adjust raid_disk indexes */\n\t\t\t__reorder_raid_disk_indexes(rs);\n\n\t\t\t/* raid0 -> raid10_far layout */\n\t\t\tmddev->layout = raid10_format_to_md_layout(rs, ALGORITHM_RAID10_FAR,\n\t\t\t\t\t\t\t\t   rs->raid10_copies);\n\t\t} else if (rs_is_raid1(rs))\n\t\t\t/* raid1 -> raid10_near layout */\n\t\t\tmddev->layout = raid10_format_to_md_layout(rs, ALGORITHM_RAID10_NEAR,\n\t\t\t\t\t\t\t\t   rs->raid_disks);\n\t\telse\n\t\t\treturn -EINVAL;\n\n\t}\n\n\tclear_bit(MD_ARRAY_FIRST_USE, &mddev->flags);\n\tmddev->recovery_cp = MaxSector;\n\n\twhile (d--) {\n\t\trdev = &rs->dev[d].rdev;\n\n\t\tif (test_bit(d, (void *) rs->rebuild_disks)) {\n\t\t\tclear_bit(In_sync, &rdev->flags);\n\t\t\tclear_bit(Faulty, &rdev->flags);\n\t\t\tmddev->recovery_cp = rdev->recovery_offset = 0;\n\t\t\t/* Bitmap has to be created when we do an \"up\" takeover */\n\t\t\tset_bit(MD_ARRAY_FIRST_USE, &mddev->flags);\n\t\t}\n\n\t\trdev->new_data_offset = new_data_offset;\n\t}\n\n\treturn 0;\n}",
        "static int check_mte_memory(char *ptr, int size, int mode, int tag_check)\n{\n\tmte_initialize_current_context(mode, (uintptr_t)ptr, size);\n\tmemset(ptr, '1', size);\n\tmte_wait_after_trig();": "static int check_mte_memory(char *ptr, int size, int mode, int tag_check)\n{\n\tmte_initialize_current_context(mode, (uintptr_t)ptr, size);\n\tmemset(ptr, '1', size);\n\tmte_wait_after_trig();\n\tif (cur_mte_cxt.fault_valid == true)\n\t\treturn KSFT_FAIL;\n\n\tmte_initialize_current_context(mode, (uintptr_t)ptr, -UNDERFLOW);\n\tmemset(ptr - UNDERFLOW, '2', UNDERFLOW);\n\tmte_wait_after_trig();\n\tif (cur_mte_cxt.fault_valid == false && tag_check == TAG_CHECK_ON)\n\t\treturn KSFT_FAIL;\n\tif (cur_mte_cxt.fault_valid == true && tag_check == TAG_CHECK_OFF)\n\t\treturn KSFT_FAIL;\n\n\tmte_initialize_current_context(mode, (uintptr_t)ptr, size + OVERFLOW);\n\tmemset(ptr + size, '3', OVERFLOW);\n\tmte_wait_after_trig();\n\tif (cur_mte_cxt.fault_valid == false && tag_check == TAG_CHECK_ON)\n\t\treturn KSFT_FAIL;\n\tif (cur_mte_cxt.fault_valid == true && tag_check == TAG_CHECK_OFF)\n\t\treturn KSFT_FAIL;\n\n\treturn KSFT_PASS;\n}",
        "static void check_good_sample(struct test_perf_branches *skel)\n{\n\tint written_global = skel->bss->written_global_out;\n\tint required_size = skel->bss->required_size_out;\n\tint written_stack = skel->bss->written_stack_out;": "static void check_good_sample(struct test_perf_branches *skel)\n{\n\tint written_global = skel->bss->written_global_out;\n\tint required_size = skel->bss->required_size_out;\n\tint written_stack = skel->bss->written_stack_out;\n\tint pbe_size = sizeof(struct perf_branch_entry);\n\tint duration = 0;\n\n\tif (CHECK(!skel->bss->valid, \"output not valid\",\n\t\t \"no valid sample from prog\"))\n\t\treturn;\n\n\t/*\n\t * It's hard to validate the contents of the branch entries b/c it\n\t * would require some kind of disassembler and also encoding the\n\t * valid jump instructions for supported architectures. So just check\n\t * the easy stuff for now.\n\t */\n\tCHECK(required_size <= 0, \"read_branches_size\", \"err %d\\n\", required_size);\n\tCHECK(written_stack < 0, \"read_branches_stack\", \"err %d\\n\", written_stack);\n\tCHECK(written_stack % pbe_size != 0, \"read_branches_stack\",\n\t      \"stack bytes written=%d not multiple of struct size=%d\\n\",\n\t      written_stack, pbe_size);\n\tCHECK(written_global < 0, \"read_branches_global\", \"err %d\\n\", written_global);\n\tCHECK(written_global % pbe_size != 0, \"read_branches_global\",\n\t      \"global bytes written=%d not multiple of struct size=%d\\n\",\n\t      written_global, pbe_size);\n\tCHECK(written_global < written_stack, \"read_branches_size\",\n\t      \"written_global=%d < written_stack=%d\\n\", written_global, written_stack);\n}",
        "static bool set_watchpoint(pid_t pid, int size, int wp)\n{\n\tconst volatile uint8_t *addr = &var[32 + wp];\n\tconst int offset = (uintptr_t)addr % 8;\n\tconst unsigned int byte_mask = ((1 << size) - 1) << offset;": "static bool set_watchpoint(pid_t pid, int size, int wp)\n{\n\tconst volatile uint8_t *addr = &var[32 + wp];\n\tconst int offset = (uintptr_t)addr % 8;\n\tconst unsigned int byte_mask = ((1 << size) - 1) << offset;\n\tconst unsigned int type = 2; /* Write */\n\tconst unsigned int enable = 1;\n\tconst unsigned int control = byte_mask << 5 | type << 3 | enable;\n\tstruct user_hwdebug_state dreg_state;\n\tstruct iovec iov;\n\n\tmemset(&dreg_state, 0, sizeof(dreg_state));\n\tdreg_state.dbg_regs[0].addr = (uintptr_t)(addr - offset);\n\tdreg_state.dbg_regs[0].ctrl = control;\n\tiov.iov_base = &dreg_state;\n\tiov.iov_len = offsetof(struct user_hwdebug_state, dbg_regs) +\n\t\t\t\tsizeof(dreg_state.dbg_regs[0]);\n\tif (ptrace(PTRACE_SETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0)\n\t\treturn true;\n\n\tif (errno == EIO)\n\t\tksft_print_msg(\n\t\t\t\"ptrace(PTRACE_SETREGSET, NT_ARM_HW_WATCH) not supported on this hardware: %s\\n\",\n\t\t\tstrerror(errno));\n\n\tksft_print_msg(\n\t\t\"ptrace(PTRACE_SETREGSET, NT_ARM_HW_WATCH) failed: %s\\n\",\n\t\tstrerror(errno));\n\treturn false;\n}",
        "static int stfsm_s25fl_config(struct stfsm *fsm)\n{\n\tstruct flash_info *info = fsm->info;\n\tuint32_t flags = info->flags;\n\tuint32_t data_pads;": "static int stfsm_s25fl_config(struct stfsm *fsm)\n{\n\tstruct flash_info *info = fsm->info;\n\tuint32_t flags = info->flags;\n\tuint32_t data_pads;\n\tuint32_t offs;\n\tuint16_t sta_wr;\n\tuint8_t sr1, cr1, dyb;\n\tint update_sr = 0;\n\tint ret;\n\n\tif (flags & FLASH_FLAG_32BIT_ADDR) {\n\t\t/*\n\t\t * Prepare Read/Write/Erase sequences according to S25FLxxx\n\t\t * 32-bit address command set\n\t\t */\n\t\tret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,\n\t\t\t\t\t\t  stfsm_s25fl_read4_configs);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,\n\t\t\t\t\t\t  stfsm_s25fl_write4_configs);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tstfsm_s25fl_prepare_erasesec_seq_32(&stfsm_seq_erase_sector);\n\n\t} else {\n\t\t/* Use default configurations for 24-bit addressing */\n\t\tret = stfsm_prepare_rwe_seqs_default(fsm);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\t/*\n\t * For devices that support 'DYB' sector locking, check lock status and\n\t * unlock sectors if necessary (some variants power-on with sectors\n\t * locked by default)\n\t */\n\tif (flags & FLASH_FLAG_DYB_LOCKING) {\n\t\toffs = 0;\n\t\tfor (offs = 0; offs < info->sector_size * info->n_sectors;) {\n\t\t\tstfsm_s25fl_read_dyb(fsm, offs, &dyb);\n\t\t\tif (dyb == 0x00)\n\t\t\t\tstfsm_s25fl_write_dyb(fsm, offs, 0xff);\n\n\t\t\t/* Handle bottom/top 4KiB parameter sectors */\n\t\t\tif ((offs < info->sector_size * 2) ||\n\t\t\t    (offs >= (info->sector_size - info->n_sectors * 4)))\n\t\t\t\toffs += 0x1000;\n\t\t\telse\n\t\t\t\toffs += 0x10000;\n\t\t}\n\t}\n\n\t/* Check status of 'QE' bit, update if required. */\n\tstfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1);\n\tdata_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;\n\tif (data_pads == 4) {\n\t\tif (!(cr1 & STFSM_S25FL_CONFIG_QE)) {\n\t\t\t/* Set 'QE' */\n\t\t\tcr1 |= STFSM_S25FL_CONFIG_QE;\n\n\t\t\tupdate_sr = 1;\n\t\t}\n\t} else {\n\t\tif (cr1 & STFSM_S25FL_CONFIG_QE) {\n\t\t\t/* Clear 'QE' */\n\t\t\tcr1 &= ~STFSM_S25FL_CONFIG_QE;\n\n\t\t\tupdate_sr = 1;\n\t\t}\n\t}\n\tif (update_sr) {\n\t\tstfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);\n\t\tsta_wr = ((uint16_t)cr1  << 8) | sr1;\n\t\tstfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1);\n\t}\n\n\t/*\n\t * S25FLxxx devices support Program and Error error flags.\n\t * Configure driver to check flags and clear if necessary.\n\t */\n\tfsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS;\n\n\treturn 0;\n}",
        "static void misc(void)\n{\n\tconst char send_msg[] = \"MISC!!!\";\n\tchar recv_msg[sizeof(send_msg)];\n\tconst unsigned int nr_data = 2;": "static void misc(void)\n{\n\tconst char send_msg[] = \"MISC!!!\";\n\tchar recv_msg[sizeof(send_msg)];\n\tconst unsigned int nr_data = 2;\n\tstruct bpf_link *link;\n\tstruct sk_fds sk_fds;\n\tint i, ret;\n\n\tlport_linum_map_fd = bpf_map__fd(misc_skel->maps.lport_linum_map);\n\n\tif (write_sysctl(\"/proc/sys/net/ipv4/tcp_syncookies\", \"1\"))\n\t\treturn;\n\n\tlink = bpf_program__attach_cgroup(misc_skel->progs.misc_estab, cg_fd);\n\tif (!ASSERT_OK_PTR(link, \"attach_cgroup(misc_estab)\"))\n\t\treturn;\n\n\tif (sk_fds_connect(&sk_fds, false)) {\n\t\tbpf_link__destroy(link);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < nr_data; i++) {\n\t\t/* MSG_EOR to ensure skb will not be combined */\n\t\tret = send(sk_fds.active_fd, send_msg, sizeof(send_msg),\n\t\t\t   MSG_EOR);\n\t\tif (CHECK(ret != sizeof(send_msg), \"send(msg)\", \"ret:%d\\n\",\n\t\t\t  ret))\n\t\t\tgoto check_linum;\n\n\t\tret = read(sk_fds.passive_fd, recv_msg, sizeof(recv_msg));\n\t\tif (CHECK(ret != sizeof(send_msg), \"read(msg)\", \"ret:%d\\n\",\n\t\t\t  ret))\n\t\t\tgoto check_linum;\n\t}\n\n\tif (sk_fds_shutdown(&sk_fds))\n\t\tgoto check_linum;\n\n\tCHECK(misc_skel->bss->nr_syn != 1, \"unexpected nr_syn\",\n\t      \"expected (1) != actual (%u)\\n\",\n\t\tmisc_skel->bss->nr_syn);\n\n\tCHECK(misc_skel->bss->nr_data != nr_data, \"unexpected nr_data\",\n\t      \"expected (%u) != actual (%u)\\n\",\n\t      nr_data, misc_skel->bss->nr_data);\n\n\t/* The last ACK may have been delayed, so it is either 1 or 2. */\n\tCHECK(misc_skel->bss->nr_pure_ack != 1 &&\n\t      misc_skel->bss->nr_pure_ack != 2,\n\t      \"unexpected nr_pure_ack\",\n\t      \"expected (1 or 2) != actual (%u)\\n\",\n\t\tmisc_skel->bss->nr_pure_ack);\n\n\tCHECK(misc_skel->bss->nr_fin != 1, \"unexpected nr_fin\",\n\t      \"expected (1) != actual (%u)\\n\",\n\t      misc_skel->bss->nr_fin);\n\ncheck_linum:\n\tCHECK_FAIL(check_error_linum(&sk_fds));\n\tsk_fds_close(&sk_fds);\n\tbpf_link__destroy(link);\n}",
        "static inline bool is_rst_area_valid(const struct RESTART_HDR *rhdr)\n{\n\tconst struct RESTART_AREA *ra;\n\tu16 cl, fl, ul;\n\tu32 off, l_size, file_dat_bits, file_size_round;": "static inline bool is_rst_area_valid(const struct RESTART_HDR *rhdr)\n{\n\tconst struct RESTART_AREA *ra;\n\tu16 cl, fl, ul;\n\tu32 off, l_size, file_dat_bits, file_size_round;\n\tu16 ro = le16_to_cpu(rhdr->ra_off);\n\tu32 sys_page = le32_to_cpu(rhdr->sys_page_size);\n\n\tif (ro + offsetof(struct RESTART_AREA, l_size) >\n\t    SECTOR_SIZE - sizeof(short))\n\t\treturn false;\n\n\tra = Add2Ptr(rhdr, ro);\n\tcl = le16_to_cpu(ra->log_clients);\n\n\tif (cl > 1)\n\t\treturn false;\n\n\toff = le16_to_cpu(ra->client_off);\n\n\tif (!IS_ALIGNED(off, 8) || ro + off > SECTOR_SIZE - sizeof(short))\n\t\treturn false;\n\n\toff += cl * sizeof(struct CLIENT_REC);\n\n\tif (off > sys_page)\n\t\treturn false;\n\n\t/*\n\t * Check the restart length field and whether the entire\n\t * restart area is contained that length.\n\t */\n\tif (le16_to_cpu(rhdr->ra_off) + le16_to_cpu(ra->ra_len) > sys_page ||\n\t    off > le16_to_cpu(ra->ra_len)) {\n\t\treturn false;\n\t}\n\n\t/*\n\t * As a final check make sure that the use list and the free list\n\t * are either empty or point to a valid client.\n\t */\n\tfl = le16_to_cpu(ra->client_idx[0]);\n\tul = le16_to_cpu(ra->client_idx[1]);\n\tif ((fl != LFS_NO_CLIENT && fl >= cl) ||\n\t    (ul != LFS_NO_CLIENT && ul >= cl))\n\t\treturn false;\n\n\t/* Make sure the sequence number bits match the log file size. */\n\tl_size = le64_to_cpu(ra->l_size);\n\n\tfile_dat_bits = sizeof(u64) * 8 - le32_to_cpu(ra->seq_num_bits);\n\tfile_size_round = 1u << (file_dat_bits + 3);\n\tif (file_size_round != l_size &&\n\t    (file_size_round < l_size || (file_size_round / 2) > l_size)) {\n\t\treturn false;\n\t}\n\n\t/* The log page data offset and record header length must be quad-aligned. */\n\tif (!IS_ALIGNED(le16_to_cpu(ra->data_off), 8) ||\n\t    !IS_ALIGNED(le16_to_cpu(ra->rec_hdr_len), 8))\n\t\treturn false;\n\n\treturn true;\n}",
        "static inline unsigned long metadata_to_pageaddr(const struct kfence_metadata *meta)\n{\n\tunsigned long offset = (meta - kfence_metadata + 1) * PAGE_SIZE * 2;\n\tunsigned long pageaddr = (unsigned long)&__kfence_pool[offset];\n": "static inline unsigned long metadata_to_pageaddr(const struct kfence_metadata *meta)\n{\n\tunsigned long offset = (meta - kfence_metadata + 1) * PAGE_SIZE * 2;\n\tunsigned long pageaddr = (unsigned long)&__kfence_pool[offset];\n\n\t/* The checks do not affect performance; only called from slow-paths. */\n\n\t/* Only call with a pointer into kfence_metadata. */\n\tif (KFENCE_WARN_ON(meta < kfence_metadata ||\n\t\t\t   meta >= kfence_metadata + CONFIG_KFENCE_NUM_OBJECTS))\n\t\treturn 0;\n\n\t/*\n\t * This metadata object only ever maps to 1 page; verify that the stored\n\t * address is in the expected range.\n\t */\n\tif (KFENCE_WARN_ON(ALIGN_DOWN(meta->addr, PAGE_SIZE) != pageaddr))\n\t\treturn 0;\n\n\treturn pageaddr;\n}",
        "static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)\n{\n\tstruct mt8195_afe_private *afe_priv = afe->platform_priv;\n\tstruct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];\n\tunsigned int reg = 0;": "static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)\n{\n\tstruct mt8195_afe_private *afe_priv = afe->platform_priv;\n\tstruct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];\n\tunsigned int reg = 0;\n\tunsigned int mask;\n\tunsigned int val;\n\tint cowork_source_sel;\n\n\tif (etdm_data->cowork_source_id == COWORK_ETDM_NONE)\n\t\treturn 0;\n\n\tcowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id,\n\t\t\t\t\t\tetdm_data->slave_mode);\n\tif (cowork_source_sel < 0)\n\t\treturn cowork_source_sel;\n\n\tswitch (dai_id) {\n\tcase MT8195_AFE_IO_ETDM1_IN:\n\t\treg = ETDM_COWORK_CON1;\n\t\tmask = ETDM_IN1_SLAVE_SEL_MASK;\n\t\tval = ETDM_IN1_SLAVE_SEL(cowork_source_sel);\n\t\tbreak;\n\tcase MT8195_AFE_IO_ETDM2_IN:\n\t\treg = ETDM_COWORK_CON2;\n\t\tmask = ETDM_IN2_SLAVE_SEL_MASK;\n\t\tval = ETDM_IN2_SLAVE_SEL(cowork_source_sel);\n\t\tbreak;\n\tcase MT8195_AFE_IO_ETDM1_OUT:\n\t\treg = ETDM_COWORK_CON0;\n\t\tmask = ETDM_OUT1_SLAVE_SEL_MASK;\n\t\tval = ETDM_OUT1_SLAVE_SEL(cowork_source_sel);\n\t\tbreak;\n\tcase MT8195_AFE_IO_ETDM2_OUT:\n\t\treg = ETDM_COWORK_CON2;\n\t\tmask = ETDM_OUT2_SLAVE_SEL_MASK;\n\t\tval = ETDM_OUT2_SLAVE_SEL(cowork_source_sel);\n\t\tbreak;\n\tcase MT8195_AFE_IO_ETDM3_OUT:\n\t\treg = ETDM_COWORK_CON2;\n\t\tmask = ETDM_OUT3_SLAVE_SEL_MASK;\n\t\tval = ETDM_OUT3_SLAVE_SEL(cowork_source_sel);\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\n\tregmap_update_bits(afe->regmap, reg, mask, val);\n\n\treturn 0;\n}",
        "static int sa_sha_setup(struct sa_tfm_ctx *ctx, struct  algo_data *ad)\n{\n\tint bs = crypto_shash_blocksize(ctx->shash);\n\tint cmdl_len;\n\tstruct sa_cmdl_cfg cfg;": "static int sa_sha_setup(struct sa_tfm_ctx *ctx, struct  algo_data *ad)\n{\n\tint bs = crypto_shash_blocksize(ctx->shash);\n\tint cmdl_len;\n\tstruct sa_cmdl_cfg cfg;\n\n\tad->enc_eng.sc_size = SA_CTX_ENC_TYPE1_SZ;\n\tad->auth_eng.eng_id = SA_ENG_ID_AM1;\n\tad->auth_eng.sc_size = SA_CTX_AUTH_TYPE2_SZ;\n\n\tmemset(ctx->authkey, 0, bs);\n\tmemset(&cfg, 0, sizeof(cfg));\n\tcfg.aalg = ad->aalg_id;\n\tcfg.enc_eng_id = ad->enc_eng.eng_id;\n\tcfg.auth_eng_id = ad->auth_eng.eng_id;\n\tcfg.iv_size = 0;\n\tcfg.akey = NULL;\n\tcfg.akey_len = 0;\n\n\tctx->dev_data = dev_get_drvdata(sa_k3_dev);\n\t/* Setup Encryption Security Context & Command label template */\n\tif (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, NULL, 0, NULL, 0,\n\t\t       ad, 0, &ctx->enc.epib[1]))\n\t\tgoto badkey;\n\n\tcmdl_len = sa_format_cmdl_gen(&cfg,\n\t\t\t\t      (u8 *)ctx->enc.cmdl,\n\t\t\t\t      &ctx->enc.cmdl_upd_info);\n\tif (cmdl_len <= 0 || (cmdl_len > SA_MAX_CMDL_WORDS * sizeof(u32)))\n\t\tgoto badkey;\n\n\tctx->enc.cmdl_size = cmdl_len;\n\n\treturn 0;\n\nbadkey:\n\tdev_err(sa_k3_dev, \"%s: badkey\\n\", __func__);\n\treturn -EINVAL;\n}",
        "static void rvu_lbk_set_channels(struct rvu *rvu)\n{\n\tstruct pci_dev *pdev = NULL;\n\tvoid __iomem *base;\n\tu64 lbk_const;": "static void rvu_lbk_set_channels(struct rvu *rvu)\n{\n\tstruct pci_dev *pdev = NULL;\n\tvoid __iomem *base;\n\tu64 lbk_const;\n\tu8 src, dst;\n\tu16 chans;\n\n\t/* To loopback packets between multiple NIX blocks\n\t * mutliple LBK blocks are needed. With two NIX blocks,\n\t * four LBK blocks are needed and each LBK block\n\t * source and destination are as follows:\n\t * LBK0 - source NIX0 and destination NIX1\n\t * LBK1 - source NIX0 and destination NIX1\n\t * LBK2 - source NIX1 and destination NIX0\n\t * LBK3 - source NIX1 and destination NIX1\n\t * As per the HRM channel numbers should be programmed as:\n\t * P2X and X2P of LBK0 as same\n\t * P2X and X2P of LBK3 as same\n\t * P2X of LBK1 and X2P of LBK2 as same\n\t * P2X of LBK2 and X2P of LBK1 as same\n\t */\n\twhile (true) {\n\t\tpdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,\n\t\t\t\t      PCI_DEVID_OCTEONTX2_LBK, pdev);\n\t\tif (!pdev)\n\t\t\treturn;\n\n\t\tbase = pci_ioremap_bar(pdev, 0);\n\t\tif (!base)\n\t\t\tgoto err_put;\n\n\t\tlbk_const = readq(base + LBK_CONST);\n\t\tchans = FIELD_GET(LBK_CONST_CHANS, lbk_const);\n\t\tdst = FIELD_GET(LBK_CONST_DST, lbk_const);\n\t\tsrc = FIELD_GET(LBK_CONST_SRC, lbk_const);\n\n\t\tif (src == dst) {\n\t\t\tif (src == LBK_CONNECT_NIXX(0)) { /* LBK0 */\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,\n\t\t\t\t\t\t    0, chans);\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,\n\t\t\t\t\t\t    0, chans);\n\t\t\t} else if (src == LBK_CONNECT_NIXX(1)) { /* LBK3 */\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,\n\t\t\t\t\t\t    1, chans);\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,\n\t\t\t\t\t\t    1, chans);\n\t\t\t}\n\t\t} else {\n\t\t\tif (src == LBK_CONNECT_NIXX(0)) { /* LBK1 */\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,\n\t\t\t\t\t\t    0, chans);\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,\n\t\t\t\t\t\t    1, chans);\n\t\t\t} else if (src == LBK_CONNECT_NIXX(1)) { /* LBK2 */\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,\n\t\t\t\t\t\t    1, chans);\n\t\t\t\t__rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,\n\t\t\t\t\t\t    0, chans);\n\t\t\t}\n\t\t}\n\t\tiounmap(base);\n\t}\nerr_put:\n\tpci_dev_put(pdev);\n}",
        "static void zxr_pre_dsp_setup(struct hda_codec *codec)\n{\n\tstatic const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };\n\tstatic const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };\n\tunsigned int i;": "static void zxr_pre_dsp_setup(struct hda_codec *codec)\n{\n\tstatic const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };\n\tstatic const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };\n\tunsigned int i;\n\n\tchipio_write(codec, 0x189000, 0x0001f100);\n\tmsleep(50);\n\tchipio_write(codec, 0x18900c, 0x0001f100);\n\tmsleep(50);\n\n\t/*\n\t * This writes a RET instruction at the entry point of the function at\n\t * 0xfa92 in exram. This function seems to have something to do with\n\t * ASI. Might be some way to prevent the card from reconfiguring the\n\t * ASI stuff itself.\n\t */\n\tchipio_8051_write_exram(codec, 0xfa92, 0x22);\n\n\tchipio_8051_write_pll_pmu(codec, 0x51, 0x98);\n\n\tsnd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);\n\tchipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);\n\n\tchipio_write(codec, 0x18902c, 0x00000000);\n\tmsleep(50);\n\tchipio_write(codec, 0x18902c, 0x00000003);\n\tmsleep(50);\n\n\tfor (i = 0; i < ARRAY_SIZE(addr); i++)\n\t\tchipio_8051_write_pll_pmu(codec, addr[i], data[i]);\n}",
        "static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)\n{\n\tstruct ice_sbq_msg_input msg = {0};\n\tint err;\n": "static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)\n{\n\tstruct ice_sbq_msg_input msg = {0};\n\tint err;\n\n\tmsg.msg_addr_low = lower_16_bits(addr);\n\tmsg.msg_addr_high = upper_16_bits(addr);\n\tmsg.opcode = ice_sbq_msg_rd;\n\tmsg.dest_dev = rmn_0;\n\n\terr = ice_sbq_rw_reg(hw, &msg);\n\tif (err) {\n\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to PHY, err %d\\n\",\n\t\t\t  err);\n\t\treturn err;\n\t}\n\n\t*val = msg.data;\n\n\treturn 0;\n}",
        "static int ti_ads7950_init_hw(struct ti_ads7950_state *st)\n{\n\tint ret = 0;\n\n\tmutex_lock(&st->slock);": "static int ti_ads7950_init_hw(struct ti_ads7950_state *st)\n{\n\tint ret = 0;\n\n\tmutex_lock(&st->slock);\n\n\t/* Settings for Manual/Auto1/Auto2 commands */\n\t/* Default to 5v ref */\n\tst->cmd_settings_bitmask = TI_ADS7950_CR_RANGE_5V;\n\tst->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);\n\tret = spi_sync(st->spi, &st->scan_single_msg);\n\tif (ret)\n\t\tgoto out;\n\n\t/* Settings for GPIO command */\n\tst->gpio_cmd_settings_bitmask = 0x0;\n\tst->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);\n\tret = spi_sync(st->spi, &st->scan_single_msg);\n\nout:\n\tmutex_unlock(&st->slock);\n\n\treturn ret;\n}",
        "static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tregister u64 temp64 = 0, intr_mask = 0;\n": "static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tregister u64 temp64 = 0, intr_mask = 0;\n\n\tintr_mask = nic->general_int_mask;\n\n\t/*  Top level interrupt classification */\n\t/*  PIC Interrupts */\n\tif (mask & TX_PIC_INTR) {\n\t\t/*  Enable PIC Intrs in the general intr mask register */\n\t\tintr_mask |= TXPIC_INT_M;\n\t\tif (flag == ENABLE_INTRS) {\n\t\t\t/*\n\t\t\t * If Hercules adapter enable GPIO otherwise\n\t\t\t * disable all PCIX, Flash, MDIO, IIC and GPIO\n\t\t\t * interrupts for now.\n\t\t\t * TODO\n\t\t\t */\n\t\t\tif (s2io_link_fault_indication(nic) ==\n\t\t\t    LINK_UP_DOWN_INTERRUPT) {\n\t\t\t\tdo_s2io_write_bits(PIC_INT_GPIO, flag,\n\t\t\t\t\t\t   &bar0->pic_int_mask);\n\t\t\t\tdo_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,\n\t\t\t\t\t\t   &bar0->gpio_int_mask);\n\t\t\t} else\n\t\t\t\twriteq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);\n\t\t} else if (flag == DISABLE_INTRS) {\n\t\t\t/*\n\t\t\t * Disable PIC Intrs in the general\n\t\t\t * intr mask register\n\t\t\t */\n\t\t\twriteq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);\n\t\t}\n\t}\n\n\t/*  Tx traffic interrupts */\n\tif (mask & TX_TRAFFIC_INTR) {\n\t\tintr_mask |= TXTRAFFIC_INT_M;\n\t\tif (flag == ENABLE_INTRS) {\n\t\t\t/*\n\t\t\t * Enable all the Tx side interrupts\n\t\t\t * writing 0 Enables all 64 TX interrupt levels\n\t\t\t */\n\t\t\twriteq(0x0, &bar0->tx_traffic_mask);\n\t\t} else if (flag == DISABLE_INTRS) {\n\t\t\t/*\n\t\t\t * Disable Tx Traffic Intrs in the general intr mask\n\t\t\t * register.\n\t\t\t */\n\t\t\twriteq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);\n\t\t}\n\t}\n\n\t/*  Rx traffic interrupts */\n\tif (mask & RX_TRAFFIC_INTR) {\n\t\tintr_mask |= RXTRAFFIC_INT_M;\n\t\tif (flag == ENABLE_INTRS) {\n\t\t\t/* writing 0 Enables all 8 RX interrupt levels */\n\t\t\twriteq(0x0, &bar0->rx_traffic_mask);\n\t\t} else if (flag == DISABLE_INTRS) {\n\t\t\t/*\n\t\t\t * Disable Rx Traffic Intrs in the general intr mask\n\t\t\t * register.\n\t\t\t */\n\t\t\twriteq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);\n\t\t}\n\t}\n\n\ttemp64 = readq(&bar0->general_int_mask);\n\tif (flag == ENABLE_INTRS)\n\t\ttemp64 &= ~((u64)intr_mask);\n\telse\n\t\ttemp64 = DISABLE_ALL_INTRS;\n\twriteq(temp64, &bar0->general_int_mask);\n\n\tnic->general_int_mask = readq(&bar0->general_int_mask);\n}",
        "static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_eth_dev *ethdev = cp->ethdev;\n\tstruct cnic_uio_dev *udev = cp->udev;": "static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_eth_dev *ethdev = cp->ethdev;\n\tstruct cnic_uio_dev *udev = cp->udev;\n\tu32 cid_addr, sb_id, val, coal_reg, coal_val;\n\tint i;\n\tstruct bnx2_rx_bd *rxbd;\n\tstruct status_block *s_blk = cp->status_blk.gen;\n\tdma_addr_t ring_map = udev->l2_ring_map;\n\n\tsb_id = cp->status_blk_num;\n\tcnic_init_context(dev, 2);\n\tcp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;\n\tcoal_reg = BNX2_HC_COMMAND;\n\tcoal_val = CNIC_RD(dev, coal_reg);\n\tif (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {\n\t\tstruct status_block_msix *sblk = cp->status_blk.bnx2;\n\n\t\tcp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;\n\t\tcoal_reg = BNX2_HC_COALESCE_NOW;\n\t\tcoal_val = 1 << (11 + sb_id);\n\t}\n\ti = 0;\n\twhile (!(*cp->rx_cons_ptr != 0) && i < 10) {\n\t\tCNIC_WR(dev, coal_reg, coal_val);\n\t\tudelay(10);\n\t\ti++;\n\t\tbarrier();\n\t}\n\tcp->rx_cons = *cp->rx_cons_ptr;\n\n\tcid_addr = GET_CID_ADDR(2);\n\tval = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |\n\t      BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);\n\tcnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);\n\n\tif (sb_id == 0)\n\t\tval = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;\n\telse\n\t\tval = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);\n\tcnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);\n\n\trxbd = udev->l2_ring + CNIC_PAGE_SIZE;\n\tfor (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {\n\t\tdma_addr_t buf_map;\n\t\tint n = (i % cp->l2_rx_ring_size) + 1;\n\n\t\tbuf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);\n\t\trxbd->rx_bd_len = cp->l2_single_buf_size;\n\t\trxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;\n\t\trxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;\n\t\trxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;\n\t}\n\tval = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;\n\tcnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);\n\trxbd->rx_bd_haddr_hi = val;\n\n\tval = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;\n\tcnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);\n\trxbd->rx_bd_haddr_lo = val;\n\n\tval = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);\n\tcnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));\n}",
        "static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)\n{\n\t/*\n\t * Find the amount and size of buffers allocated by the current caller;\n\t * The idea is that once we cross the threshold, whoever is responsible": "static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)\n{\n\t/*\n\t * Find the amount and size of buffers allocated by the current caller;\n\t * The idea is that once we cross the threshold, whoever is responsible\n\t * for the low async space is likely to try to send another async txn,\n\t * and at some point we'll catch them in the act. This is more efficient\n\t * than keeping a map per pid.\n\t */\n\tstruct rb_node *n;\n\tstruct binder_buffer *buffer;\n\tsize_t total_alloc_size = 0;\n\tsize_t num_buffers = 0;\n\n\tfor (n = rb_first(&alloc->allocated_buffers); n != NULL;\n\t\t n = rb_next(n)) {\n\t\tbuffer = rb_entry(n, struct binder_buffer, rb_node);\n\t\tif (buffer->pid != pid)\n\t\t\tcontinue;\n\t\tif (!buffer->async_transaction)\n\t\t\tcontinue;\n\t\ttotal_alloc_size += binder_alloc_buffer_size(alloc, buffer)\n\t\t\t+ sizeof(struct binder_buffer);\n\t\tnum_buffers++;\n\t}\n\n\t/*\n\t * Warn if this pid has more than 50 transactions, or more than 50% of\n\t * async space (which is 25% of total buffer size). Oneway spam is only\n\t * detected when the threshold is exceeded.\n\t */\n\tif (num_buffers > 50 || total_alloc_size > alloc->buffer_size / 4) {\n\t\tbinder_alloc_debug(BINDER_DEBUG_USER_ERROR,\n\t\t\t     \"%d: pid %d spamming oneway? %zd buffers allocated for a total size of %zd\\n\",\n\t\t\t      alloc->pid, pid, num_buffers, total_alloc_size);\n\t\tif (!alloc->oneway_spam_detected) {\n\t\t\talloc->oneway_spam_detected = true;\n\t\t\treturn true;\n\t\t}\n\t}\n\treturn false;\n}",
        "static bool qede_poll_is_more_work(struct qede_fastpath *fp)\n{\n\tqed_sb_update_sb_idx(fp->sb_info);\n\n\t/* *_has_*_work() reads the status block, thus we need to ensure that": "static bool qede_poll_is_more_work(struct qede_fastpath *fp)\n{\n\tqed_sb_update_sb_idx(fp->sb_info);\n\n\t/* *_has_*_work() reads the status block, thus we need to ensure that\n\t * status block indices have been actually read (qed_sb_update_sb_idx)\n\t * prior to this check (*_has_*_work) so that we won't write the\n\t * \"newer\" value of the status block to HW (if there was a DMA right\n\t * after qede_has_rx_work and if there is no rmb, the memory reading\n\t * (qed_sb_update_sb_idx) may be postponed to right before *_ack_sb).\n\t * In this case there will never be another interrupt until there is\n\t * another update of the status block, while there is still unhandled\n\t * work.\n\t */\n\trmb();\n\n\tif (likely(fp->type & QEDE_FASTPATH_RX))\n\t\tif (qede_has_rx_work(fp->rxq))\n\t\t\treturn true;\n\n\tif (fp->type & QEDE_FASTPATH_XDP)\n\t\tif (qede_txq_has_work(fp->xdp_tx))\n\t\t\treturn true;\n\n\tif (likely(fp->type & QEDE_FASTPATH_TX)) {\n\t\tint cos;\n\n\t\tfor_each_cos_in_txq(fp->edev, cos) {\n\t\t\tif (qede_txq_has_work(&fp->txq[cos]))\n\t\t\t\treturn true;\n\t\t}\n\t}\n\n\treturn false;\n}",
        "static void run_test(__u32 input_retval, __u16 want_side_effect, __s16 want_ret)\n{\n\tstruct modify_return *skel = NULL;\n\tint err, prog_fd;\n\t__u16 side_effect;": "static void run_test(__u32 input_retval, __u16 want_side_effect, __s16 want_ret)\n{\n\tstruct modify_return *skel = NULL;\n\tint err, prog_fd;\n\t__u16 side_effect;\n\t__s16 ret;\n\tLIBBPF_OPTS(bpf_test_run_opts, topts);\n\n\tskel = modify_return__open_and_load();\n\tif (!ASSERT_OK_PTR(skel, \"skel_load\"))\n\t\tgoto cleanup;\n\n\terr = modify_return__attach(skel);\n\tif (!ASSERT_OK(err, \"modify_return__attach failed\"))\n\t\tgoto cleanup;\n\n\tskel->bss->input_retval = input_retval;\n\tprog_fd = bpf_program__fd(skel->progs.fmod_ret_test);\n\terr = bpf_prog_test_run_opts(prog_fd, &topts);\n\tASSERT_OK(err, \"test_run\");\n\n\tside_effect = UPPER(topts.retval);\n\tret = LOWER(topts.retval);\n\n\tASSERT_EQ(ret, want_ret, \"test_run ret\");\n\tASSERT_EQ(side_effect, want_side_effect, \"modify_return side_effect\");\n\tASSERT_EQ(skel->bss->fentry_result, 1, \"modify_return fentry_result\");\n\tASSERT_EQ(skel->bss->fexit_result, 1, \"modify_return fexit_result\");\n\tASSERT_EQ(skel->bss->fmod_ret_result, 1, \"modify_return fmod_ret_result\");\n\ncleanup:\n\tmodify_return__destroy(skel);\n}",
        "static void ipc_imem_device_ipc_uninit(struct iosm_imem *ipc_imem)\n{\n\tint timeout = IPC_MODEM_UNINIT_TIMEOUT_MS;\n\tenum ipc_mem_device_ipc_state ipc_state;\n": "static void ipc_imem_device_ipc_uninit(struct iosm_imem *ipc_imem)\n{\n\tint timeout = IPC_MODEM_UNINIT_TIMEOUT_MS;\n\tenum ipc_mem_device_ipc_state ipc_state;\n\n\t/* When PCIe link is up set IPC_UNINIT\n\t * of the modem otherwise ignore it when PCIe link down happens.\n\t */\n\tif (ipc_pcie_check_data_link_active(ipc_imem->pcie)) {\n\t\t/* set modem to UNINIT\n\t\t * (in case we want to reload the AP driver without resetting\n\t\t * the modem)\n\t\t */\n\t\tipc_doorbell_fire(ipc_imem->pcie, IPC_DOORBELL_IRQ_IPC,\n\t\t\t\t  IPC_MEM_DEVICE_IPC_UNINIT);\n\t\tipc_state = ipc_mmio_get_ipc_state(ipc_imem->mmio);\n\n\t\t/* Wait for maximum 30ms to allow the Modem to uninitialize the\n\t\t * protocol.\n\t\t */\n\t\twhile ((ipc_state <= IPC_MEM_DEVICE_IPC_DONT_CARE) &&\n\t\t       (ipc_state != IPC_MEM_DEVICE_IPC_UNINIT) &&\n\t\t       (timeout > 0)) {\n\t\t\tusleep_range(1000, 1250);\n\t\t\ttimeout--;\n\t\t\tipc_state = ipc_mmio_get_ipc_state(ipc_imem->mmio);\n\t\t}\n\t}\n}",
        "static int load_scale_v4(struct venus_inst *inst)\n{\n\tstruct venus_core *core = inst->core;\n\tconst struct freq_tbl *table = core->res->freq_tbl;\n\tunsigned int num_rows = core->res->freq_tbl_size;": "static int load_scale_v4(struct venus_inst *inst)\n{\n\tstruct venus_core *core = inst->core;\n\tconst struct freq_tbl *table = core->res->freq_tbl;\n\tunsigned int num_rows = core->res->freq_tbl_size;\n\tstruct device *dev = core->dev;\n\tunsigned long freq = 0, freq_core1 = 0, freq_core2 = 0;\n\tunsigned long filled_len = 0;\n\tint i, ret = 0;\n\n\tfor (i = 0; i < inst->num_input_bufs; i++)\n\t\tfilled_len = max(filled_len, inst->payloads[i]);\n\n\tif (inst->session_type == VIDC_SESSION_TYPE_DEC && !filled_len)\n\t\treturn ret;\n\n\tfreq = calculate_inst_freq(inst, filled_len);\n\tinst->clk_data.freq = freq;\n\n\tmutex_lock(&core->lock);\n\tlist_for_each_entry(inst, &core->instances, list) {\n\t\tif (inst->clk_data.core_id == VIDC_CORE_ID_1) {\n\t\t\tfreq_core1 += inst->clk_data.freq;\n\t\t} else if (inst->clk_data.core_id == VIDC_CORE_ID_2) {\n\t\t\tfreq_core2 += inst->clk_data.freq;\n\t\t} else if (inst->clk_data.core_id == VIDC_CORE_ID_3) {\n\t\t\tfreq_core1 += inst->clk_data.freq;\n\t\t\tfreq_core2 += inst->clk_data.freq;\n\t\t}\n\t}\n\n\tfreq = max(freq_core1, freq_core2);\n\n\tif (freq > table[0].freq) {\n\t\tdev_dbg(dev, VDBGL \"requested clock rate: %lu scaling clock rate : %lu\\n\",\n\t\t\tfreq, table[0].freq);\n\n\t\tfreq = table[0].freq;\n\t\tgoto set_freq;\n\t}\n\n\tfor (i = num_rows - 1 ; i >= 0; i--) {\n\t\tif (freq <= table[i].freq) {\n\t\t\tfreq = table[i].freq;\n\t\t\tbreak;\n\t\t}\n\t}\n\nset_freq:\n\n\tret = core_clks_set_rate(core, freq);\n\tif (ret) {\n\t\tdev_err(dev, \"failed to set clock rate %lu (%d)\\n\",\n\t\t\tfreq, ret);\n\t\tgoto exit;\n\t}\n\n\tret = load_scale_bw(core);\n\tif (ret) {\n\t\tdev_err(dev, \"failed to set bandwidth (%d)\\n\",\n\t\t\tret);\n\t\tgoto exit;\n\t}\n\nexit:\n\tmutex_unlock(&core->lock);\n\treturn ret;\n}",
        "static int bc_set_next(ktime_t expires, struct clock_event_device *bc)\n{\n\t/*\n\t * This is called either from enter/exit idle code or from the\n\t * broadcast handler. In all cases tick_broadcast_lock is held.": "static int bc_set_next(ktime_t expires, struct clock_event_device *bc)\n{\n\t/*\n\t * This is called either from enter/exit idle code or from the\n\t * broadcast handler. In all cases tick_broadcast_lock is held.\n\t *\n\t * hrtimer_cancel() cannot be called here neither from the\n\t * broadcast handler nor from the enter/exit idle code. The idle\n\t * code can run into the problem described in bc_shutdown() and the\n\t * broadcast handler cannot wait for itself to complete for obvious\n\t * reasons.\n\t *\n\t * Each caller tries to arm the hrtimer on its own CPU, but if the\n\t * hrtimer callback function is currently running, then\n\t * hrtimer_start() cannot move it and the timer stays on the CPU on\n\t * which it is assigned at the moment.\n\t *\n\t * As this can be called from idle code, the hrtimer_start()\n\t * invocation has to be wrapped with RCU_NONIDLE() as\n\t * hrtimer_start() can call into tracing.\n\t */\n\tRCU_NONIDLE( {\n\t\thrtimer_start(&bctimer, expires, HRTIMER_MODE_ABS_PINNED_HARD);\n\t\t/*\n\t\t * The core tick broadcast mode expects bc->bound_on to be set\n\t\t * correctly to prevent a CPU which has the broadcast hrtimer\n\t\t * armed from going deep idle.\n\t\t *\n\t\t * As tick_broadcast_lock is held, nothing can change the cpu\n\t\t * base which was just established in hrtimer_start() above. So\n\t\t * the below access is safe even without holding the hrtimer\n\t\t * base lock.\n\t\t */\n\t\tbc->bound_on = bctimer.base->cpu_base->cpu;\n\t} );\n\treturn 0;\n}",
        "static int vdec_set_properties(struct venus_inst *inst)\n{\n\tstruct vdec_controls *ctr = &inst->controls.dec;\n\tstruct hfi_enable en = { .enable = 1 };\n\tu32 ptype, decode_order, conceal;": "static int vdec_set_properties(struct venus_inst *inst)\n{\n\tstruct vdec_controls *ctr = &inst->controls.dec;\n\tstruct hfi_enable en = { .enable = 1 };\n\tu32 ptype, decode_order, conceal;\n\tint ret;\n\n\tif (ctr->post_loop_deb_mode) {\n\t\tptype = HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER;\n\t\tret = hfi_session_set_property(inst, ptype, &en);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tif (ctr->display_delay_enable && ctr->display_delay == 0) {\n\t\tptype = HFI_PROPERTY_PARAM_VDEC_OUTPUT_ORDER;\n\t\tdecode_order = HFI_OUTPUT_ORDER_DECODE;\n\t\tret = hfi_session_set_property(inst, ptype, &decode_order);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tptype = HFI_PROPERTY_PARAM_VDEC_CONCEAL_COLOR;\n\tconceal = ctr->conceal_color & 0xffff;\n\tconceal |= ((ctr->conceal_color >> 16) & 0xffff) << 10;\n\tconceal |= ((ctr->conceal_color >> 32) & 0xffff) << 20;\n\n\tret = hfi_session_set_property(inst, ptype, &conceal);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}",
        "static void __amd_mp2_process_event(struct amd_i2c_common *i2c_common)\n{\n\tstruct amd_mp2_dev *privdata = i2c_common->mp2_dev;\n\tstruct pci_dev *pdev = privdata->pci_dev;\n\tenum status_type sts = i2c_common->eventval.r.status;": "static void __amd_mp2_process_event(struct amd_i2c_common *i2c_common)\n{\n\tstruct amd_mp2_dev *privdata = i2c_common->mp2_dev;\n\tstruct pci_dev *pdev = privdata->pci_dev;\n\tenum status_type sts = i2c_common->eventval.r.status;\n\tenum response_type res = i2c_common->eventval.r.response;\n\tint len = i2c_common->eventval.r.length;\n\n\tif (res != command_success) {\n\t\tif (res != command_failed)\n\t\t\tpci_err(pdev, \"invalid response to i2c command!\\n\");\n\t\treturn;\n\t}\n\n\tswitch (i2c_common->reqcmd) {\n\tcase i2c_read:\n\t\tif (sts == i2c_readcomplete_event) {\n\t\t\tamd_mp2_pci_check_rw_event(i2c_common);\n\t\t\tif (len <= 32)\n\t\t\t\tmemcpy_fromio(i2c_common->msg->buf,\n\t\t\t\t\t      privdata->mmio + AMD_C2P_MSG2,\n\t\t\t\t\t      len);\n\t\t} else if (sts != i2c_readfail_event) {\n\t\t\tpci_err(pdev, \"invalid i2c status after read (%d)!\\n\", sts);\n\t\t}\n\t\tbreak;\n\tcase i2c_write:\n\t\tif (sts == i2c_writecomplete_event)\n\t\t\tamd_mp2_pci_check_rw_event(i2c_common);\n\t\telse if (sts != i2c_writefail_event)\n\t\t\tpci_err(pdev, \"invalid i2c status after write (%d)!\\n\", sts);\n\t\tbreak;\n\tcase i2c_enable:\n\t\tif (sts == i2c_busenable_complete)\n\t\t\ti2c_common->cmd_success = true;\n\t\telse if (sts != i2c_busenable_failed)\n\t\t\tpci_err(pdev, \"invalid i2c status after bus enable (%d)!\\n\", sts);\n\t\tbreak;\n\tcase i2c_disable:\n\t\tif (sts == i2c_busdisable_complete)\n\t\t\ti2c_common->cmd_success = true;\n\t\telse if (sts != i2c_busdisable_failed)\n\t\t\tpci_err(pdev, \"invalid i2c status after bus disable (%d)!\\n\", sts);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}",
        "static int thermal_get_sensor(int idx, s32 *value)\n{\n\tint t;\n\ts8 tmp;\n\tchar tmpi[5];": "static int thermal_get_sensor(int idx, s32 *value)\n{\n\tint t;\n\ts8 tmp;\n\tchar tmpi[5];\n\n\tt = TP_EC_THERMAL_TMP0;\n\n\tswitch (thermal_read_mode) {\n#if TPACPI_MAX_THERMAL_SENSORS >= 16\n\tcase TPACPI_THERMAL_TPEC_16:\n\t\tif (idx >= 8 && idx <= 15) {\n\t\t\tt = TP_EC_THERMAL_TMP8;\n\t\t\tidx -= 8;\n\t\t}\n#endif\n\t\tfallthrough;\n\tcase TPACPI_THERMAL_TPEC_8:\n\t\tif (idx <= 7) {\n\t\t\tif (!acpi_ec_read(t + idx, &tmp))\n\t\t\t\treturn -EIO;\n\t\t\t*value = tmp * 1000;\n\t\t\treturn 0;\n\t\t}\n\t\tbreak;\n\n\tcase TPACPI_THERMAL_ACPI_UPDT:\n\t\tif (idx <= 7) {\n\t\t\tsnprintf(tmpi, sizeof(tmpi), \"TMP%c\", '0' + idx);\n\t\t\tif (!acpi_evalf(ec_handle, NULL, \"UPDT\", \"v\"))\n\t\t\t\treturn -EIO;\n\t\t\tif (!acpi_evalf(ec_handle, &t, tmpi, \"d\"))\n\t\t\t\treturn -EIO;\n\t\t\t*value = (t - 2732) * 100;\n\t\t\treturn 0;\n\t\t}\n\t\tbreak;\n\n\tcase TPACPI_THERMAL_ACPI_TMP07:\n\t\tif (idx <= 7) {\n\t\t\tsnprintf(tmpi, sizeof(tmpi), \"TMP%c\", '0' + idx);\n\t\t\tif (!acpi_evalf(ec_handle, &t, tmpi, \"d\"))\n\t\t\t\treturn -EIO;\n\t\t\tif (t > 127 || t < -127)\n\t\t\t\tt = TP_EC_THERMAL_TMP_NA;\n\t\t\t*value = t * 1000;\n\t\t\treturn 0;\n\t\t}\n\t\tbreak;\n\n\tcase TPACPI_THERMAL_NONE:\n\tdefault:\n\t\treturn -ENOSYS;\n\t}\n\n\treturn -EINVAL;\n}",
        "static int md_thread(void *arg)\n{\n\tstruct md_thread *thread = arg;\n\n\t/*": "static int md_thread(void *arg)\n{\n\tstruct md_thread *thread = arg;\n\n\t/*\n\t * md_thread is a 'system-thread', it's priority should be very\n\t * high. We avoid resource deadlocks individually in each\n\t * raid personality. (RAID5 does preallocation) We also use RR and\n\t * the very same RT priority as kswapd, thus we will never get\n\t * into a priority inversion deadlock.\n\t *\n\t * we definitely have to have equal or higher priority than\n\t * bdflush, otherwise bdflush will deadlock if there are too\n\t * many dirty RAID5 blocks.\n\t */\n\n\tallow_signal(SIGKILL);\n\twhile (!kthread_should_stop()) {\n\n\t\t/* We need to wait INTERRUPTIBLE so that\n\t\t * we don't add to the load-average.\n\t\t * That means we need to be sure no signals are\n\t\t * pending\n\t\t */\n\t\tif (signal_pending(current))\n\t\t\tflush_signals(current);\n\n\t\twait_event_interruptible_timeout\n\t\t\t(thread->wqueue,\n\t\t\t test_bit(THREAD_WAKEUP, &thread->flags)\n\t\t\t || kthread_should_stop() || kthread_should_park(),\n\t\t\t thread->timeout);\n\n\t\tclear_bit(THREAD_WAKEUP, &thread->flags);\n\t\tif (kthread_should_park())\n\t\t\tkthread_parkme();\n\t\tif (!kthread_should_stop())\n\t\t\tthread->run(thread);\n\t}\n\n\treturn 0;\n}",
        "static int mhz_3288_power(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct smc_private *smc = netdev_priv(dev);\n    u_char tmp;": "static int mhz_3288_power(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct smc_private *smc = netdev_priv(dev);\n    u_char tmp;\n\n    /* Read the ISR twice... */\n    readb(smc->base+MEGAHERTZ_ISR);\n    udelay(5);\n    readb(smc->base+MEGAHERTZ_ISR);\n\n    /* Pause 200ms... */\n    mdelay(200);\n\n    /* Now read and write the COR... */\n    tmp = readb(smc->base + link->config_base + CISREG_COR);\n    udelay(5);\n    writeb(tmp, smc->base + link->config_base + CISREG_COR);\n\n    return 0;\n}",
        "static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)\n{\n\tstruct qspi_trans tp;\n\tint slot = 0, tstatus = 0;\n\tu32 mspi_cdram = 0;": "static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)\n{\n\tstruct qspi_trans tp;\n\tint slot = 0, tstatus = 0;\n\tu32 mspi_cdram = 0;\n\n\tbcm_qspi_disable_bspi(qspi);\n\ttp = qspi->trans_pos;\n\tbcm_qspi_update_parms(qspi, spi, tp.trans);\n\n\t/* Run until end of transfer or reached the max data */\n\twhile (!tstatus && slot < MSPI_NUM_CDRAM) {\n\t\tmspi_cdram = MSPI_CDRAM_CONT_BIT;\n\t\tif (tp.trans->bits_per_word <= 8) {\n\t\t\tconst u8 *buf = tp.trans->tx_buf;\n\t\t\tu8 val = buf ? buf[tp.byte] : 0x00;\n\n\t\t\twrite_txram_slot_u8(qspi, slot, val);\n\t\t\tdev_dbg(&qspi->pdev->dev, \"WR %02x\\n\", val);\n\t\t} else if (tp.trans->bits_per_word <= 16) {\n\t\t\tconst u16 *buf = tp.trans->tx_buf;\n\t\t\tu16 val = buf ? buf[tp.byte / 2] : 0x0000;\n\n\t\t\twrite_txram_slot_u16(qspi, slot, val);\n\t\t\tdev_dbg(&qspi->pdev->dev, \"WR %04x\\n\", val);\n\t\t} else if (tp.trans->bits_per_word <= 32) {\n\t\t\tconst u32 *buf = tp.trans->tx_buf;\n\t\t\tu32 val = buf ? buf[tp.byte/4] : 0x0;\n\n\t\t\twrite_txram_slot_u32(qspi, slot, val);\n\t\t\tdev_dbg(&qspi->pdev->dev, \"WR %08x\\n\", val);\n\t\t} else if (tp.trans->bits_per_word <= 64) {\n\t\t\tconst u64 *buf = tp.trans->tx_buf;\n\t\t\tu64 val = (buf ? buf[tp.byte/8] : 0x0);\n\n\t\t\t/* use the length of delay from SPCR1_LSB */\n\t\t\tif (bcm_qspi_has_fastbr(qspi))\n\t\t\t\tmspi_cdram |= MSPI_CDRAM_DT_BIT;\n\n\t\t\twrite_txram_slot_u64(qspi, slot, val);\n\t\t\tdev_dbg(&qspi->pdev->dev, \"WR %llx\\n\", val);\n\t\t}\n\n\t\tmspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :\n\t\t\t       MSPI_CDRAM_BITSE_BIT);\n\n\t\t/* set 3wrire halfduplex mode data from master to slave */\n\t\tif ((spi->mode & SPI_3WIRE) && tp.trans->tx_buf)\n\t\t\tmspi_cdram |= MSPI_CDRAM_OUTP;\n\n\t\tif (has_bspi(qspi))\n\t\t\tmspi_cdram &= ~1;\n\t\telse\n\t\t\tmspi_cdram |= (~(1 << spi->chip_select) &\n\t\t\t\t       MSPI_CDRAM_PCS);\n\n\t\twrite_cdram_slot(qspi, slot, mspi_cdram);\n\n\t\ttstatus = update_qspi_trans_byte_count(qspi, &tp,\n\t\t\t\t\t\t       TRANS_STATUS_BREAK_TX);\n\t\tslot++;\n\t}\n\n\tif (!slot) {\n\t\tdev_err(&qspi->pdev->dev, \"%s: no data to send?\", __func__);\n\t\tgoto done;\n\t}\n\n\tdev_dbg(&qspi->pdev->dev, \"submitting %d slots\\n\", slot);\n\tbcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);\n\tbcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);\n\n\t/*\n\t *  case 1) EOM =1, cs_change =0: SSb inactive\n\t *  case 2) EOM =1, cs_change =1: SSb stay active\n\t *  case 3) EOM =0, cs_change =0: SSb stay active\n\t *  case 4) EOM =0, cs_change =1: SSb inactive\n\t */\n\tif (((tstatus & TRANS_STATUS_BREAK_DESELECT)\n\t     == TRANS_STATUS_BREAK_CS_CHANGE) ||\n\t    ((tstatus & TRANS_STATUS_BREAK_DESELECT)\n\t     == TRANS_STATUS_BREAK_EOM)) {\n\t\tmspi_cdram = read_cdram_slot(qspi, slot - 1) &\n\t\t\t~MSPI_CDRAM_CONT_BIT;\n\t\twrite_cdram_slot(qspi, slot - 1, mspi_cdram);\n\t}\n\n\tif (has_bspi(qspi))\n\t\tbcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);\n\n\t/* Must flush previous writes before starting MSPI operation */\n\tmb();\n\t/* Set cont | spe | spifie */\n\tbcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);\n\ndone:\n\treturn slot;\n}",
        "static int hynix_get_majority(const u8 *in, int repeat, u8 *out)\n{\n\tint i, j, half = repeat / 2;\n\n\t/*": "static int hynix_get_majority(const u8 *in, int repeat, u8 *out)\n{\n\tint i, j, half = repeat / 2;\n\n\t/*\n\t * We only test the first half of the in array because we must ensure\n\t * that the value is at least occurring repeat / 2 times.\n\t *\n\t * This loop is suboptimal since we may count the occurrences of the\n\t * same value several time, but we are doing that on small sets, which\n\t * makes it acceptable.\n\t */\n\tfor (i = 0; i < half; i++) {\n\t\tint cnt = 0;\n\t\tu8 val = in[i];\n\n\t\t/* Count all values that are matching the one at index i. */\n\t\tfor (j = i + 1; j < repeat; j++) {\n\t\t\tif (in[j] == val)\n\t\t\t\tcnt++;\n\t\t}\n\n\t\t/* We found a value occurring more than repeat / 2. */\n\t\tif (cnt > half) {\n\t\t\t*out = val;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\treturn -EIO;\n}",
        "static int fib6_nh_mtu_change(struct fib6_nh *nh, void *_arg)\n{\n\tstruct rt6_mtu_change_arg *arg = (struct rt6_mtu_change_arg *)_arg;\n\tstruct fib6_info *f6i = arg->f6i;\n": "static int fib6_nh_mtu_change(struct fib6_nh *nh, void *_arg)\n{\n\tstruct rt6_mtu_change_arg *arg = (struct rt6_mtu_change_arg *)_arg;\n\tstruct fib6_info *f6i = arg->f6i;\n\n\t/* For administrative MTU increase, there is no way to discover\n\t * IPv6 PMTU increase, so PMTU increase should be updated here.\n\t * Since RFC 1981 doesn't include administrative MTU increase\n\t * update PMTU increase is a MUST. (i.e. jumbo frame)\n\t */\n\tif (nh->fib_nh_dev == arg->dev) {\n\t\tstruct inet6_dev *idev = __in6_dev_get(arg->dev);\n\t\tu32 mtu = f6i->fib6_pmtu;\n\n\t\tif (mtu >= arg->mtu ||\n\t\t    (mtu < arg->mtu && mtu == idev->cnf.mtu6))\n\t\t\tfib6_metric_set(f6i, RTAX_MTU, arg->mtu);\n\n\t\tspin_lock_bh(&rt6_exception_lock);\n\t\trt6_exceptions_update_pmtu(idev, nh, arg->mtu);\n\t\tspin_unlock_bh(&rt6_exception_lock);\n\t}\n\n\treturn 0;\n}",
        "static int test5_rw_aligned_1byte(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0xF000) & ~(ADI_BLKSZ - 1);": "static int test5_rw_aligned_1byte(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0xF000) & ~(ADI_BLKSZ - 1);\n\tunsigned char version, expected_version;\n\tloff_t offset;\n\toff_t oret;\n\tint ret;\n\n\toffset = paddr / ADI_BLKSZ;\n\tversion = expected_version = random_version();\n\n\toret = seek_adi(fd, offset, SEEK_SET);\n\tif (oret != offset) {\n\t\tret = -1;\n\t\tTEST_STEP_FAILURE(ret);\n\t}\n\n\tret = write_adi(fd, &version, sizeof(version));\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\toret = seek_adi(fd, offset, SEEK_SET);\n\tif (oret != offset) {\n\t\tret = -1;\n\t\tTEST_STEP_FAILURE(ret);\n\t}\n\n\tret = read_adi(fd, &version, sizeof(version));\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tif (expected_version != version) {\n\t\tDEBUG_PRINT_L2(\"\\tExpected version %d but read version %d\\n\",\n\t\t\t       expected_version, version);\n\t\tTEST_STEP_FAILURE(-expected_version);\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static int imgu_dummybufs_init(struct imgu_device *imgu, unsigned int pipe)\n{\n\tconst struct v4l2_pix_format_mplane *mpix;\n\tconst struct v4l2_meta_format\t*meta;\n\tunsigned int i, k, node;": "static int imgu_dummybufs_init(struct imgu_device *imgu, unsigned int pipe)\n{\n\tconst struct v4l2_pix_format_mplane *mpix;\n\tconst struct v4l2_meta_format\t*meta;\n\tunsigned int i, k, node;\n\tsize_t size;\n\tstruct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];\n\n\t/* Allocate a dummy buffer for each queue where buffer is optional */\n\tfor (i = 0; i < IPU3_CSS_QUEUES; i++) {\n\t\tnode = imgu_map_node(imgu, i);\n\t\tif (!imgu_pipe->queue_enabled[node] || i == IMGU_QUEUE_MASTER)\n\t\t\tcontinue;\n\n\t\tif (!imgu_pipe->nodes[IMGU_NODE_VF].enabled &&\n\t\t    i == IPU3_CSS_QUEUE_VF)\n\t\t\t/*\n\t\t\t * Do not enable dummy buffers for VF if it is not\n\t\t\t * requested by the user.\n\t\t\t */\n\t\t\tcontinue;\n\n\t\tmeta = &imgu_pipe->nodes[node].vdev_fmt.fmt.meta;\n\t\tmpix = &imgu_pipe->nodes[node].vdev_fmt.fmt.pix_mp;\n\n\t\tif (node == IMGU_NODE_STAT_3A || node == IMGU_NODE_PARAMS)\n\t\t\tsize = meta->buffersize;\n\t\telse\n\t\t\tsize = mpix->plane_fmt[0].sizeimage;\n\n\t\tif (imgu_css_dma_buffer_resize(imgu,\n\t\t\t\t\t       &imgu_pipe->queues[i].dmap,\n\t\t\t\t\t       size)) {\n\t\t\timgu_dummybufs_cleanup(imgu, pipe);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\tfor (k = 0; k < IMGU_MAX_QUEUE_DEPTH; k++)\n\t\t\timgu_css_buf_init(&imgu_pipe->queues[i].dummybufs[k], i,\n\t\t\t\t\t  imgu_pipe->queues[i].dmap.daddr);\n\t}\n\n\treturn 0;\n}",
        "static void flexcan_ram_init(struct net_device *dev)\n{\n\tstruct flexcan_priv *priv = netdev_priv(dev);\n\tstruct flexcan_regs __iomem *regs = priv->regs;\n\tu32 reg_ctrl2;": "static void flexcan_ram_init(struct net_device *dev)\n{\n\tstruct flexcan_priv *priv = netdev_priv(dev);\n\tstruct flexcan_regs __iomem *regs = priv->regs;\n\tu32 reg_ctrl2;\n\n\t/* 11.8.3.13 Detection and correction of memory errors:\n\t * CTRL2[WRMFRZ] grants write access to all memory positions\n\t * that require initialization, ranging from 0x080 to 0xADF\n\t * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.\n\t * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers\n\t * need to be initialized as well. MCR[RFEN] must not be set\n\t * during memory initialization.\n\t */\n\treg_ctrl2 = priv->read(&regs->ctrl2);\n\treg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;\n\tpriv->write(reg_ctrl2, &regs->ctrl2);\n\n\tmemset_io(&regs->init, 0, sizeof(regs->init));\n\n\tif (priv->can.ctrlmode & CAN_CTRLMODE_FD)\n\t\tmemset_io(&regs->init_fd, 0, sizeof(regs->init_fd));\n\n\treg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;\n\tpriv->write(reg_ctrl2, &regs->ctrl2);\n}",
        "static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)\n{\n\tu8 buf, count = 0;\n\n\tdprintk(\"%s\\n\", __func__);": "static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)\n{\n\tu8 buf, count = 0;\n\n\tdprintk(\"%s\\n\", __func__);\n\n\tdprintk(\"Tuner Bytes: %*ph\\n\", 4, data + 1);\n\n\t/* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip.\n\t * direct write is required for Philips TUV1236D and ALPS TDHU2 */\n\tswitch (state->demod_chip) {\n\t\tcase NXT2004:\n\t\t\tif (i2c_writebytes(state, data[0], data+1, 4))\n\t\t\t\tpr_warn(\"error writing to tuner\\n\");\n\t\t\t/* wait until we have a lock */\n\t\t\twhile (count < 20) {\n\t\t\t\ti2c_readbytes(state, data[0], &buf, 1);\n\t\t\t\tif (buf & 0x40)\n\t\t\t\t\treturn 0;\n\t\t\t\tmsleep(100);\n\t\t\t\tcount++;\n\t\t\t}\n\t\t\tpr_warn(\"timeout waiting for tuner lock\\n\");\n\t\t\tbreak;\n\t\tcase NXT2002:\n\t\t\t/* set the i2c transfer speed to the tuner */\n\t\t\tbuf = 0x03;\n\t\t\tnxt200x_writebytes(state, 0x20, &buf, 1);\n\n\t\t\t/* setup to transfer 4 bytes via i2c */\n\t\t\tbuf = 0x04;\n\t\t\tnxt200x_writebytes(state, 0x34, &buf, 1);\n\n\t\t\t/* write actual tuner bytes */\n\t\t\tnxt200x_writebytes(state, 0x36, data+1, 4);\n\n\t\t\t/* set tuner i2c address */\n\t\t\tbuf = data[0] << 1;\n\t\t\tnxt200x_writebytes(state, 0x35, &buf, 1);\n\n\t\t\t/* write UC Opmode to begin transfer */\n\t\t\tbuf = 0x80;\n\t\t\tnxt200x_writebytes(state, 0x21, &buf, 1);\n\n\t\t\twhile (count < 20) {\n\t\t\t\tnxt200x_readbytes(state, 0x21, &buf, 1);\n\t\t\t\tif ((buf & 0x80)== 0x00)\n\t\t\t\t\treturn 0;\n\t\t\t\tmsleep(100);\n\t\t\t\tcount++;\n\t\t\t}\n\t\t\tpr_warn(\"timeout error writing to tuner\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t}\n\treturn 0;\n}",
        "static int vdec_vp8_slice_get_decode_parameters(struct vdec_vp8_slice_inst *inst)\n{\n\tconst struct v4l2_ctrl_vp8_frame *frame_header;\n\tstruct mtk_vcodec_ctx *ctx = inst->ctx;\n\tstruct vb2_queue *vq;": "static int vdec_vp8_slice_get_decode_parameters(struct vdec_vp8_slice_inst *inst)\n{\n\tconst struct v4l2_ctrl_vp8_frame *frame_header;\n\tstruct mtk_vcodec_ctx *ctx = inst->ctx;\n\tstruct vb2_queue *vq;\n\tstruct vb2_buffer *vb;\n\tu64 referenct_ts;\n\tint index, vb2_index;\n\n\tframe_header = vdec_vp8_slice_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_VP8_FRAME);\n\tif (IS_ERR(frame_header))\n\t\treturn PTR_ERR(frame_header);\n\n\tvq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);\n\tfor (index = 0; index < 3; index++) {\n\t\treferenct_ts = vdec_vp8_slice_get_ref_by_ts(frame_header, index);\n\t\tvb2_index = vb2_find_timestamp(vq, referenct_ts, 0);\n\t\tif (vb2_index < 0) {\n\t\t\tif (!V4L2_VP8_FRAME_IS_KEY_FRAME(frame_header))\n\t\t\t\tmtk_vcodec_err(inst, \"reference invalid: index(%d) ts(%lld)\",\n\t\t\t\t\t       index, referenct_ts);\n\t\t\tinst->vsi->vp8_dpb_info[index].reference_flag = 0;\n\t\t\tcontinue;\n\t\t}\n\t\tinst->vsi->vp8_dpb_info[index].reference_flag = 1;\n\n\t\tvb = vq->bufs[vb2_index];\n\t\tinst->vsi->vp8_dpb_info[index].y_dma_addr =\n\t\t\tvb2_dma_contig_plane_dma_addr(vb, 0);\n\t\tif (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2)\n\t\t\tinst->vsi->vp8_dpb_info[index].c_dma_addr =\n\t\t\t\tvb2_dma_contig_plane_dma_addr(vb, 1);\n\t\telse\n\t\t\tinst->vsi->vp8_dpb_info[index].c_dma_addr =\n\t\t\t\tinst->vsi->vp8_dpb_info[index].y_dma_addr +\n\t\t\t\tctx->picinfo.fb_sz[0];\n\t}\n\n\tinst->vsi->dec.frame_header_type = frame_header->flags >> 1;\n\n\treturn 0;\n}",
        "static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)\n{\n\tstruct dw_i2c_dev *dev = i2c_get_adapdata(adap);\n\tint msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;\n\tint cmd = 0, status;": "static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)\n{\n\tstruct dw_i2c_dev *dev = i2c_get_adapdata(adap);\n\tint msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;\n\tint cmd = 0, status;\n\tu8 *tx_buf;\n\tu32 val;\n\n\t/*\n\t * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,\n\t * it is mandatory to set the right value in specific register\n\t * (offset:0x474) as per the hardware IP specification.\n\t */\n\tregmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);\n\n\tdev->msgs = msgs;\n\tdev->msgs_num = num_msgs;\n\ti2c_dw_xfer_init(dev);\n\ti2c_dw_disable_int(dev);\n\n\t/* Initiate messages read/write transaction */\n\tfor (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {\n\t\ttx_buf = msgs[msg_wrt_idx].buf;\n\t\tbuf_len = msgs[msg_wrt_idx].len;\n\n\t\tif (!(msgs[msg_wrt_idx].flags & I2C_M_RD))\n\t\t\tregmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);\n\t\t/*\n\t\t * Initiate the i2c read/write transaction of buffer length,\n\t\t * and poll for bus busy status. For the last message transfer,\n\t\t * update the command with stopbit enable.\n\t\t */\n\t\tfor (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {\n\t\t\tif (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)\n\t\t\t\tcmd |= BIT(9);\n\n\t\t\tif (msgs[msg_wrt_idx].flags & I2C_M_RD) {\n\t\t\t\t/* Due to hardware bug, need to write the same command twice. */\n\t\t\t\tregmap_write(dev->map, DW_IC_DATA_CMD, 0x100);\n\t\t\t\tregmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);\n\t\t\t\tif (cmd) {\n\t\t\t\t\tregmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));\n\t\t\t\t\tregmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));\n\t\t\t\t\t/*\n\t\t\t\t\t * Need to check the stop bit. However, it cannot be\n\t\t\t\t\t * detected from the registers so we check it always\n\t\t\t\t\t * when read/write the last byte.\n\t\t\t\t\t */\n\t\t\t\t\tstatus = i2c_dw_status(dev);\n\t\t\t\t\tif (status)\n\t\t\t\t\t\treturn status;\n\n\t\t\t\t\tfor (data_idx = 0; data_idx < buf_len; data_idx++) {\n\t\t\t\t\t\tregmap_read(dev->map, DW_IC_DATA_CMD, &val);\n\t\t\t\t\t\ttx_buf[data_idx] = val;\n\t\t\t\t\t}\n\t\t\t\t\tstatus = i2c_dw_check_stopbit(dev);\n\t\t\t\t\tif (status)\n\t\t\t\t\t\treturn status;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tregmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);\n\t\t\t\tusleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US);\n\t\t\t}\n\t\t}\n\t\tstatus = i2c_dw_check_stopbit(dev);\n\t\tif (status)\n\t\t\treturn status;\n\t}\n\n\treturn 0;\n}",
        "static int jt8ev1_post_poweron(struct ccs_sensor *sensor)\n{\n\tstruct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);\n\tint rval;\n\tstatic const struct ccs_reg_8 regs[] = {": "static int jt8ev1_post_poweron(struct ccs_sensor *sensor)\n{\n\tstruct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);\n\tint rval;\n\tstatic const struct ccs_reg_8 regs[] = {\n\t\t{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */\n\t\t{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */\n\t\t{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */\n\t\t{ 0x3238, 0x43 },\n\t\t{ 0x3301, 0x06 }, /* For analog bias for sensor */\n\t\t{ 0x3302, 0x06 },\n\t\t{ 0x3304, 0x00 },\n\t\t{ 0x3305, 0x88 },\n\t\t{ 0x332a, 0x14 },\n\t\t{ 0x332c, 0x6b },\n\t\t{ 0x3336, 0x01 },\n\t\t{ 0x333f, 0x1f },\n\t\t{ 0x3355, 0x00 },\n\t\t{ 0x3356, 0x20 },\n\t\t{ 0x33bf, 0x20 }, /* Adjust the FBC speed */\n\t\t{ 0x33c9, 0x20 },\n\t\t{ 0x33ce, 0x30 }, /* Adjust the parameter for logic function */\n\t\t{ 0x33cf, 0xec }, /* For Black sun */\n\t\t{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */\n\t};\n\tstatic const struct ccs_reg_8 regs_96[] = {\n\t\t{ 0x30ae, 0x00 }, /* For control of ADC clock */\n\t\t{ 0x30af, 0xd0 },\n\t\t{ 0x30b0, 0x01 },\n\t};\n\n\trval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));\n\tif (rval < 0)\n\t\treturn rval;\n\n\tswitch (sensor->hwcfg.ext_clk) {\n\tcase 9600000:\n\t\treturn ccs_write_addr_8s(sensor, regs_96,\n\t\t\t\t       ARRAY_SIZE(regs_96));\n\tdefault:\n\t\tdev_warn(&client->dev, \"no MSRs for %d Hz ext_clk\\n\",\n\t\t\t sensor->hwcfg.ext_clk);\n\t\treturn 0;\n\t}\n}",
        "static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)\n{\n\tstruct pcie_port *pp = &pcie->pci.pp;\n\tstruct pci_bus *child, *root_bus = NULL;\n\tstruct pci_dev *pdev;": "static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)\n{\n\tstruct pcie_port *pp = &pcie->pci.pp;\n\tstruct pci_bus *child, *root_bus = NULL;\n\tstruct pci_dev *pdev;\n\n\t/*\n\t * link doesn't go into L2 state with some of the endpoints with Tegra\n\t * if they are not in D0 state. So, need to make sure that immediate\n\t * downstream devices are in D0 state before sending PME_TurnOff to put\n\t * link into L2 state.\n\t * This is as per PCI Express Base r4.0 v1.0 September 27-2017,\n\t * 5.2 Link State Power Management (Page #428).\n\t */\n\n\tlist_for_each_entry(child, &pp->bridge->bus->children, node) {\n\t\t/* Bring downstream devices to D0 if they are not already in */\n\t\tif (child->parent == pp->bridge->bus) {\n\t\t\troot_bus = child;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!root_bus) {\n\t\tdev_err(pcie->dev, \"Failed to find downstream devices\\n\");\n\t\treturn;\n\t}\n\n\tlist_for_each_entry(pdev, &root_bus->devices, bus_list) {\n\t\tif (PCI_SLOT(pdev->devfn) == 0) {\n\t\t\tif (pci_set_power_state(pdev, PCI_D0))\n\t\t\t\tdev_err(pcie->dev,\n\t\t\t\t\t\"Failed to transition %s to D0 state\\n\",\n\t\t\t\t\tdev_name(&pdev->dev));\n\t\t}\n\t}\n}",
        "static enum wdrr_bucket_idx hhf_classify(struct sk_buff *skb, struct Qdisc *sch)\n{\n\tstruct hhf_sched_data *q = qdisc_priv(sch);\n\tu32 tmp_hash, hash;\n\tu32 xorsum, filter_pos[HHF_ARRAYS_CNT], flow_pos;": "static enum wdrr_bucket_idx hhf_classify(struct sk_buff *skb, struct Qdisc *sch)\n{\n\tstruct hhf_sched_data *q = qdisc_priv(sch);\n\tu32 tmp_hash, hash;\n\tu32 xorsum, filter_pos[HHF_ARRAYS_CNT], flow_pos;\n\tstruct hh_flow_state *flow;\n\tu32 pkt_len, min_hhf_val;\n\tint i;\n\tu32 prev;\n\tu32 now = hhf_time_stamp();\n\n\t/* Reset the HHF counter arrays if this is the right time. */\n\tprev = q->hhf_arrays_reset_timestamp + q->hhf_reset_timeout;\n\tif (hhf_time_before(prev, now)) {\n\t\tfor (i = 0; i < HHF_ARRAYS_CNT; i++)\n\t\t\tbitmap_zero(q->hhf_valid_bits[i], HHF_ARRAYS_LEN);\n\t\tq->hhf_arrays_reset_timestamp = now;\n\t}\n\n\t/* Get hashed flow-id of the skb. */\n\thash = skb_get_hash_perturb(skb, &q->perturbation);\n\n\t/* Check if this packet belongs to an already established HH flow. */\n\tflow_pos = hash & HHF_BIT_MASK;\n\tflow = seek_list(hash, &q->hh_flows[flow_pos], q);\n\tif (flow) { /* found its HH flow */\n\t\tflow->hit_timestamp = now;\n\t\treturn WDRR_BUCKET_FOR_HH;\n\t}\n\n\t/* Now pass the packet through the multi-stage filter. */\n\ttmp_hash = hash;\n\txorsum = 0;\n\tfor (i = 0; i < HHF_ARRAYS_CNT - 1; i++) {\n\t\t/* Split the skb_hash into three 10-bit chunks. */\n\t\tfilter_pos[i] = tmp_hash & HHF_BIT_MASK;\n\t\txorsum ^= filter_pos[i];\n\t\ttmp_hash >>= HHF_BIT_MASK_LEN;\n\t}\n\t/* The last chunk is computed as XOR sum of other chunks. */\n\tfilter_pos[HHF_ARRAYS_CNT - 1] = xorsum ^ tmp_hash;\n\n\tpkt_len = qdisc_pkt_len(skb);\n\tmin_hhf_val = ~0U;\n\tfor (i = 0; i < HHF_ARRAYS_CNT; i++) {\n\t\tu32 val;\n\n\t\tif (!test_bit(filter_pos[i], q->hhf_valid_bits[i])) {\n\t\t\tq->hhf_arrays[i][filter_pos[i]] = 0;\n\t\t\t__set_bit(filter_pos[i], q->hhf_valid_bits[i]);\n\t\t}\n\n\t\tval = q->hhf_arrays[i][filter_pos[i]] + pkt_len;\n\t\tif (min_hhf_val > val)\n\t\t\tmin_hhf_val = val;\n\t}\n\n\t/* Found a new HH iff all counter values > HH admit threshold. */\n\tif (min_hhf_val > q->hhf_admit_bytes) {\n\t\t/* Just captured a new heavy-hitter. */\n\t\tflow = alloc_new_hh(&q->hh_flows[flow_pos], q);\n\t\tif (!flow) /* memory alloc problem */\n\t\t\treturn WDRR_BUCKET_FOR_NON_HH;\n\t\tflow->hash_id = hash;\n\t\tflow->hit_timestamp = now;\n\t\tq->hh_flows_total_cnt++;\n\n\t\t/* By returning without updating counters in q->hhf_arrays,\n\t\t * we implicitly implement \"shielding\" (see Optimization O1).\n\t\t */\n\t\treturn WDRR_BUCKET_FOR_HH;\n\t}\n\n\t/* Conservative update of HHF arrays (see Optimization O2). */\n\tfor (i = 0; i < HHF_ARRAYS_CNT; i++) {\n\t\tif (q->hhf_arrays[i][filter_pos[i]] < min_hhf_val)\n\t\t\tq->hhf_arrays[i][filter_pos[i]] = min_hhf_val;\n\t}\n\treturn WDRR_BUCKET_FOR_NON_HH;\n}",
        "static int set_ref(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;\n\tconst struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;": "static int set_ref(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;\n\tconst struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;\n\tconst struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;\n\tdma_addr_t luma_addr, chroma_addr, mv_addr = 0;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tstruct vb2_v4l2_buffer *vb2_dst;\n\tstruct hantro_decoded_buffer *dst;\n\tsize_t cr_offset = hantro_hevc_chroma_offset(ctx);\n\tsize_t mv_offset = hantro_hevc_motion_vectors_offset(ctx);\n\tu32 max_ref_frames;\n\tu16 dpb_longterm_e;\n\tstatic const struct hantro_reg cur_poc[] = {\n\t\thevc_cur_poc_00,\n\t\thevc_cur_poc_01,\n\t\thevc_cur_poc_02,\n\t\thevc_cur_poc_03,\n\t\thevc_cur_poc_04,\n\t\thevc_cur_poc_05,\n\t\thevc_cur_poc_06,\n\t\thevc_cur_poc_07,\n\t\thevc_cur_poc_08,\n\t\thevc_cur_poc_09,\n\t\thevc_cur_poc_10,\n\t\thevc_cur_poc_11,\n\t\thevc_cur_poc_12,\n\t\thevc_cur_poc_13,\n\t\thevc_cur_poc_14,\n\t\thevc_cur_poc_15,\n\t};\n\tunsigned int i;\n\n\tmax_ref_frames = decode_params->num_poc_lt_curr +\n\t\tdecode_params->num_poc_st_curr_before +\n\t\tdecode_params->num_poc_st_curr_after;\n\t/*\n\t * Set max_ref_frames to non-zero to avoid HW hang when decoding\n\t * badly marked I-frames.\n\t */\n\tmax_ref_frames = max_ref_frames ? max_ref_frames : 1;\n\thantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames);\n\thantro_reg_write(vpu, &g2_filter_over_slices,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));\n\thantro_reg_write(vpu, &g2_filter_over_tiles,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));\n\n\t/*\n\t * Write POC count diff from current pic. For frame decoding only compute\n\t * pic_order_cnt[0] and ignore pic_order_cnt[1] used in field-coding.\n\t */\n\tfor (i = 0; i < decode_params->num_active_dpb_entries && i < ARRAY_SIZE(cur_poc); i++) {\n\t\tchar poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt[0];\n\n\t\thantro_reg_write(vpu, &cur_poc[i], poc_diff);\n\t}\n\n\tif (i < ARRAY_SIZE(cur_poc)) {\n\t\t/*\n\t\t * After the references, fill one entry pointing to itself,\n\t\t * i.e. difference is zero.\n\t\t */\n\t\thantro_reg_write(vpu, &cur_poc[i], 0);\n\t\ti++;\n\t}\n\n\t/* Fill the rest with the current picture */\n\tfor (; i < ARRAY_SIZE(cur_poc); i++)\n\t\thantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val);\n\n\tset_ref_pic_list(ctx);\n\n\t/* We will only keep the reference pictures that are still used */\n\thantro_hevc_ref_init(ctx);\n\n\t/* Set up addresses of DPB buffers */\n\tdpb_longterm_e = 0;\n\tfor (i = 0; i < decode_params->num_active_dpb_entries &&\n\t     i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {\n\t\tluma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt[0]);\n\t\tif (!luma_addr)\n\t\t\treturn -ENOMEM;\n\n\t\tchroma_addr = luma_addr + cr_offset;\n\t\tmv_addr = luma_addr + mv_offset;\n\n\t\tif (dpb[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)\n\t\t\tdpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);\n\n\t\thantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);\n\t\thantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);\n\t\thantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);\n\t}\n\n\tvb2_dst = hantro_get_dst_buf(ctx);\n\tdst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);\n\tluma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);\n\tif (!luma_addr)\n\t\treturn -ENOMEM;\n\n\tif (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr))\n\t\treturn -EINVAL;\n\n\tchroma_addr = luma_addr + cr_offset;\n\tmv_addr = luma_addr + mv_offset;\n\n\thantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);\n\thantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);\n\thantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr);\n\n\thantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);\n\thantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);\n\thantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);\n\n\tfor (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {\n\t\thantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);\n\t\thantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);\n\t\thantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);\n\t}\n\n\thantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);\n\n\treturn 0;\n}",
        "static int check_clear_prot_mte_flag(int mem_type, int mode, int mapping)\n{\n\tchar *ptr, *map_ptr;\n\tint run, prot_flag, result, fd, map_size;\n\tint total = sizeof(sizes)/sizeof(int);": "static int check_clear_prot_mte_flag(int mem_type, int mode, int mapping)\n{\n\tchar *ptr, *map_ptr;\n\tint run, prot_flag, result, fd, map_size;\n\tint total = sizeof(sizes)/sizeof(int);\n\n\tprot_flag = PROT_READ | PROT_WRITE;\n\tmte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG);\n\tfor (run = 0; run < total; run++) {\n\t\tmap_size = sizes[run] + OVERFLOW + UNDERFLOW;\n\t\tptr = (char *)mte_allocate_memory_tag_range(sizes[run], mem_type, mapping,\n\t\t\t\t\t\t\t    UNDERFLOW, OVERFLOW);\n\t\tif (check_allocated_memory_range(ptr, sizes[run], mem_type,\n\t\t\t\t\t\t UNDERFLOW, OVERFLOW) != KSFT_PASS)\n\t\t\treturn KSFT_FAIL;\n\t\tmap_ptr = ptr - UNDERFLOW;\n\t\t/* Try to clear PROT_MTE property and verify it by tag checking */\n\t\tif (mprotect(map_ptr, map_size, prot_flag)) {\n\t\t\tmte_free_memory_tag_range((void *)ptr, sizes[run], mem_type,\n\t\t\t\t\t\t  UNDERFLOW, OVERFLOW);\n\t\t\tksft_print_msg(\"FAIL: mprotect not ignoring clear PROT_MTE property\\n\");\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tresult = check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON);\n\t\tmte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, OVERFLOW);\n\t\tif (result != KSFT_PASS)\n\t\t\treturn KSFT_FAIL;\n\n\t\tfd = create_temp_file();\n\t\tif (fd == -1)\n\t\t\treturn KSFT_FAIL;\n\t\tptr = (char *)mte_allocate_file_memory_tag_range(sizes[run], mem_type, mapping,\n\t\t\t\t\t\t\t\t UNDERFLOW, OVERFLOW, fd);\n\t\tif (check_allocated_memory_range(ptr, sizes[run], mem_type,\n\t\t\t\t\t\t UNDERFLOW, OVERFLOW) != KSFT_PASS) {\n\t\t\tclose(fd);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tmap_ptr = ptr - UNDERFLOW;\n\t\t/* Try to clear PROT_MTE property and verify it by tag checking */\n\t\tif (mprotect(map_ptr, map_size, prot_flag)) {\n\t\t\tksft_print_msg(\"FAIL: mprotect not ignoring clear PROT_MTE property\\n\");\n\t\t\tmte_free_memory_tag_range((void *)ptr, sizes[run], mem_type,\n\t\t\t\t\t\t  UNDERFLOW, OVERFLOW);\n\t\t\tclose(fd);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tresult = check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON);\n\t\tmte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, OVERFLOW);\n\t\tclose(fd);\n\t\tif (result != KSFT_PASS)\n\t\t\treturn KSFT_FAIL;\n\t}\n\treturn KSFT_PASS;\n}",
        "static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)\n{\n\tstruct lpass_data *drvdata = dev_get_drvdata(dev);\n\tstruct lpass_variant *v = drvdata->variant;\n\tunsigned int i;": "static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)\n{\n\tstruct lpass_data *drvdata = dev_get_drvdata(dev);\n\tstruct lpass_variant *v = drvdata->variant;\n\tunsigned int i;\n\tstruct lpass_hdmi_tx_ctl *tx_ctl;\n\tstruct regmap_field *legacy_en;\n\tstruct lpass_vbit_ctrl *vbit_ctl;\n\tstruct regmap_field *tx_parity;\n\tstruct lpass_dp_metadata_ctl *meta_ctl;\n\tstruct lpass_sstream_ctl *sstream_ctl;\n\tstruct regmap_field *ch_msb;\n\tstruct regmap_field *ch_lsb;\n\tstruct lpass_hdmitx_dmactl *tx_dmactl;\n\tint rval;\n\n\ttx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);\n\tif (!tx_ctl)\n\t\treturn -ENOMEM;\n\n\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);\n\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);\n\tdrvdata->tx_ctl = tx_ctl;\n\n\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);\n\tdrvdata->hdmitx_legacy_en = legacy_en;\n\n\tvbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);\n\tif (!vbit_ctl)\n\t\treturn -ENOMEM;\n\n\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);\n\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);\n\tdrvdata->vbit_ctl = vbit_ctl;\n\n\n\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);\n\tdrvdata->hdmitx_parity_calc_en = tx_parity;\n\n\tmeta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);\n\tif (!meta_ctl)\n\t\treturn -ENOMEM;\n\n\trval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);\n\tif (rval)\n\t\treturn rval;\n\tdrvdata->meta_ctl = meta_ctl;\n\n\tsstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);\n\tif (!sstream_ctl)\n\t\treturn -ENOMEM;\n\n\trval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);\n\tif (rval)\n\t\treturn rval;\n\n\tdrvdata->sstream_ctl = sstream_ctl;\n\n\tfor (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {\n\t\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);\n\t\tdrvdata->hdmitx_ch_msb[i] = ch_msb;\n\n\t\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);\n\t\tdrvdata->hdmitx_ch_lsb[i] = ch_lsb;\n\n\t\ttx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);\n\t\tif (!tx_dmactl)\n\t\t\treturn -ENOMEM;\n\n\t\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);\n\t\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);\n\t\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);\n\t\tQCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);\n\t\tdrvdata->hdmi_tx_dmactl[i] = tx_dmactl;\n\t}\n\treturn 0;\n}",
        "static void io_wqe_enqueue(struct io_wqe *wqe, struct io_wq_work *work)\n{\n\tstruct io_wqe_acct *acct = io_work_get_acct(wqe, work);\n\tstruct io_cb_cancel_data match;\n\tunsigned work_flags = work->flags;": "static void io_wqe_enqueue(struct io_wqe *wqe, struct io_wq_work *work)\n{\n\tstruct io_wqe_acct *acct = io_work_get_acct(wqe, work);\n\tstruct io_cb_cancel_data match;\n\tunsigned work_flags = work->flags;\n\tbool do_create;\n\n\t/*\n\t * If io-wq is exiting for this task, or if the request has explicitly\n\t * been marked as one that should not get executed, cancel it here.\n\t */\n\tif (test_bit(IO_WQ_BIT_EXIT, &wqe->wq->state) ||\n\t    (work->flags & IO_WQ_WORK_CANCEL)) {\n\t\tio_run_cancel(work, wqe);\n\t\treturn;\n\t}\n\n\traw_spin_lock(&acct->lock);\n\tio_wqe_insert_work(wqe, work);\n\tclear_bit(IO_ACCT_STALLED_BIT, &acct->flags);\n\traw_spin_unlock(&acct->lock);\n\n\traw_spin_lock(&wqe->lock);\n\trcu_read_lock();\n\tdo_create = !io_wqe_activate_free_worker(wqe, acct);\n\trcu_read_unlock();\n\n\traw_spin_unlock(&wqe->lock);\n\n\tif (do_create && ((work_flags & IO_WQ_WORK_CONCURRENT) ||\n\t    !atomic_read(&acct->nr_running))) {\n\t\tbool did_create;\n\n\t\tdid_create = io_wqe_create_worker(wqe, acct);\n\t\tif (likely(did_create))\n\t\t\treturn;\n\n\t\traw_spin_lock(&wqe->lock);\n\t\tif (acct->nr_workers) {\n\t\t\traw_spin_unlock(&wqe->lock);\n\t\t\treturn;\n\t\t}\n\t\traw_spin_unlock(&wqe->lock);\n\n\t\t/* fatal condition, failed to create the first worker */\n\t\tmatch.fn\t\t= io_wq_work_match_item,\n\t\tmatch.data\t\t= work,\n\t\tmatch.cancel_all\t= false,\n\n\t\tio_acct_cancel_pending_work(wqe, acct, &match);\n\t}\n}",
        "static void reset_fdc(void)\n{\n\tunsigned long flags;\n\n\tdo_floppy = reset_interrupt;": "static void reset_fdc(void)\n{\n\tunsigned long flags;\n\n\tdo_floppy = reset_interrupt;\n\tfdc_state[current_fdc].reset = 0;\n\treset_fdc_info(current_fdc, 0);\n\n\t/* Pseudo-DMA may intercept 'reset finished' interrupt.  */\n\t/* Irrelevant for systems with true DMA (i386).          */\n\n\tflags = claim_dma_lock();\n\tfd_disable_dma();\n\trelease_dma_lock(flags);\n\n\tif (fdc_state[current_fdc].version >= FDC_82072A)\n\t\tfdc_outb(0x80 | (fdc_state[current_fdc].dtr & 3),\n\t\t\t current_fdc, FD_STATUS);\n\telse {\n\t\tfdc_outb(fdc_state[current_fdc].dor & ~0x04, current_fdc, FD_DOR);\n\t\tudelay(FD_RESET_DELAY);\n\t\tfdc_outb(fdc_state[current_fdc].dor, current_fdc, FD_DOR);\n\t}\n}",
        "static int set_var(struct fbtft_par *par)\n{\n\t/*\n\t * Memory data access control (0x36h)\n\t * RGB/BGR:": "static int set_var(struct fbtft_par *par)\n{\n\t/*\n\t * Memory data access control (0x36h)\n\t * RGB/BGR:\n\t *\t1. Mode selection pin SRGB\n\t *\t\tRGB H/W pin for color filter setting: 0=RGB, 1=BGR\n\t *\t2. MADCTL RGB bit\n\t *\t\tRGB-BGR ORDER color filter panel: 0=RGB, 1=BGR\n\t */\n\tswitch (par->info->var.rotate) {\n\tcase 0:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MX | MY | (par->bgr << 3));\n\t\tbreak;\n\tcase 270:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MY | MV | (par->bgr << 3));\n\t\tbreak;\n\tcase 180:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  par->bgr << 3);\n\t\tbreak;\n\tcase 90:\n\t\twrite_reg(par, MIPI_DCS_SET_ADDRESS_MODE,\n\t\t\t  MX | MV | (par->bgr << 3));\n\t\tbreak;\n\t}\n\n\treturn 0;\n}",
        "static int INFTL_deleteblock(struct INFTLrecord *inftl, unsigned block)\n{\n\tunsigned int thisEUN = inftl->VUtable[block / (inftl->EraseSize / SECTORSIZE)];\n\tunsigned long blockofs = (block * SECTORSIZE) & (inftl->EraseSize - 1);\n\tstruct mtd_info *mtd = inftl->mbd.mtd;": "static int INFTL_deleteblock(struct INFTLrecord *inftl, unsigned block)\n{\n\tunsigned int thisEUN = inftl->VUtable[block / (inftl->EraseSize / SECTORSIZE)];\n\tunsigned long blockofs = (block * SECTORSIZE) & (inftl->EraseSize - 1);\n\tstruct mtd_info *mtd = inftl->mbd.mtd;\n\tunsigned int status;\n\tint silly = MAX_LOOPS;\n\tsize_t retlen;\n\tstruct inftl_bci bci;\n\n\tpr_debug(\"INFTL: INFTL_deleteblock(inftl=%p,\"\n\t\t\"block=%d)\\n\", inftl, block);\n\n\twhile (thisEUN < inftl->nb_blocks) {\n\t\tif (inftl_read_oob(mtd, (thisEUN * inftl->EraseSize) +\n\t\t\t\t   blockofs, 8, &retlen, (char *)&bci) < 0)\n\t\t\tstatus = SECTOR_IGNORE;\n\t\telse\n\t\t\tstatus = bci.Status | bci.Status1;\n\n\t\tswitch (status) {\n\t\tcase SECTOR_FREE:\n\t\tcase SECTOR_IGNORE:\n\t\t\tbreak;\n\t\tcase SECTOR_DELETED:\n\t\t\tthisEUN = BLOCK_NIL;\n\t\t\tgoto foundit;\n\t\tcase SECTOR_USED:\n\t\t\tgoto foundit;\n\t\tdefault:\n\t\t\tprintk(KERN_WARNING \"INFTL: unknown status for \"\n\t\t\t\t\"block %d in EUN %d: 0x%x\\n\",\n\t\t\t\tblock, thisEUN, status);\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!silly--) {\n\t\t\tprintk(KERN_WARNING \"INFTL: infinite loop in Virtual \"\n\t\t\t\t\"Unit Chain 0x%x\\n\",\n\t\t\t\tblock / (inftl->EraseSize / SECTORSIZE));\n\t\t\treturn 1;\n\t\t}\n\t\tthisEUN = inftl->PUtable[thisEUN];\n\t}\n\nfoundit:\n\tif (thisEUN != BLOCK_NIL) {\n\t\tloff_t ptr = (thisEUN * inftl->EraseSize) + blockofs;\n\n\t\tif (inftl_read_oob(mtd, ptr, 8, &retlen, (char *)&bci) < 0)\n\t\t\treturn -EIO;\n\t\tbci.Status = bci.Status1 = SECTOR_DELETED;\n\t\tif (inftl_write_oob(mtd, ptr, 8, &retlen, (char *)&bci) < 0)\n\t\t\treturn -EIO;\n\t\tINFTL_trydeletechain(inftl, block / (inftl->EraseSize / SECTORSIZE));\n\t}\n\treturn 0;\n}",
        "static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter)\n{\n\tif (!napi_schedule_prep(&adapter->napi))\n\t\t/* It is possible in case even the RX/TX ints are disabled via IMR\n\t\t * register the ISR bits are set anyway (but do not produce IRQ).": "static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter)\n{\n\tif (!napi_schedule_prep(&adapter->napi))\n\t\t/* It is possible in case even the RX/TX ints are disabled via IMR\n\t\t * register the ISR bits are set anyway (but do not produce IRQ).\n\t\t * To handle such situation the napi functions used to check is\n\t\t * something scheduled or not.\n\t\t */\n\t\treturn 0;\n\n\t__napi_schedule(&adapter->napi);\n\n\t/*\n\t * Disable RX/TX ints via IMR register if it is\n\t * allowed. NAPI handler must reenable them in same\n\t * way.\n\t */\n\tif (!adapter->int_enabled)\n\t\treturn 1;\n\n\tatlx_imr_set(adapter, IMR_NORXTX_MASK);\n\treturn 1;\n}",
        "static int ds_recv_data(struct ds_device *dev, unsigned char *buf, int size)\n{\n\tint count, err;\n\n\t/* Careful on size.  If size is less than what is available in": "static int ds_recv_data(struct ds_device *dev, unsigned char *buf, int size)\n{\n\tint count, err;\n\n\t/* Careful on size.  If size is less than what is available in\n\t * the input buffer, the device fails the bulk transfer and\n\t * clears the input buffer.  It could read the maximum size of\n\t * the data buffer, but then do you return the first, last, or\n\t * some set of the middle size bytes?  As long as the rest of\n\t * the code is correct there will be size bytes waiting.  A\n\t * call to ds_wait_status will wait until the device is idle\n\t * and any data to be received would have been available.\n\t */\n\tcount = 0;\n\terr = usb_bulk_msg(dev->udev, usb_rcvbulkpipe(dev->udev, dev->ep[EP_DATA_IN]),\n\t\t\t\tbuf, size, &count, 1000);\n\tif (err < 0) {\n\t\tint recv_len;\n\n\t\tdev_info(&dev->udev->dev, \"Clearing ep0x%x.\\n\", dev->ep[EP_DATA_IN]);\n\t\tusb_clear_halt(dev->udev, usb_rcvbulkpipe(dev->udev, dev->ep[EP_DATA_IN]));\n\n\t\t/* status might tell us why endpoint is stuck? */\n\t\trecv_len = ds_recv_status(dev, NULL);\n\t\tif (recv_len >= 0)\n\t\t\tds_dump_status(dev, dev->st_buf, recv_len);\n\n\t\treturn err;\n\t}\n\n#if 0\n\t{\n\t\tint i;\n\n\t\tprintk(\"%s: count=%d: \", __func__, count);\n\t\tfor (i = 0; i < count; ++i)\n\t\t\tprintk(\"%02x \", buf[i]);\n\t\tprintk(\"\\n\");\n\t}\n#endif\n\treturn count;\n}",
        "static void tipc_crypto_key_synch(struct tipc_crypto *rx, struct sk_buff *skb)\n{\n\tstruct tipc_ehdr *ehdr = (struct tipc_ehdr *)skb_network_header(skb);\n\tstruct tipc_crypto *tx = tipc_net(rx->net)->crypto_tx;\n\tstruct tipc_msg *hdr = buf_msg(skb);": "static void tipc_crypto_key_synch(struct tipc_crypto *rx, struct sk_buff *skb)\n{\n\tstruct tipc_ehdr *ehdr = (struct tipc_ehdr *)skb_network_header(skb);\n\tstruct tipc_crypto *tx = tipc_net(rx->net)->crypto_tx;\n\tstruct tipc_msg *hdr = buf_msg(skb);\n\tu32 self = tipc_own_addr(rx->net);\n\tu8 cur, new;\n\tunsigned long delay;\n\n\t/* Update RX 'key_master' flag according to peer, also mark \"legacy\" if\n\t * a peer has no master key.\n\t */\n\trx->key_master = ehdr->master_key;\n\tif (!rx->key_master)\n\t\ttx->legacy_user = 1;\n\n\t/* For later cases, apply only if message is destined to this node */\n\tif (!ehdr->destined || msg_short(hdr) || msg_destnode(hdr) != self)\n\t\treturn;\n\n\t/* Case 1: Peer has no keys, let's make master key take over */\n\tif (ehdr->rx_nokey) {\n\t\t/* Set or extend grace period */\n\t\ttx->timer2 = jiffies;\n\t\t/* Schedule key distributing for the peer if not yet */\n\t\tif (tx->key.keys &&\n\t\t    !atomic_cmpxchg(&rx->key_distr, 0, KEY_DISTR_SCHED)) {\n\t\t\tget_random_bytes(&delay, 2);\n\t\t\tdelay %= 5;\n\t\t\tdelay = msecs_to_jiffies(500 * ++delay);\n\t\t\tif (queue_delayed_work(tx->wq, &rx->work, delay))\n\t\t\t\ttipc_node_get(rx->node);\n\t\t}\n\t} else {\n\t\t/* Cancel a pending key distributing if any */\n\t\tatomic_xchg(&rx->key_distr, 0);\n\t}\n\n\t/* Case 2: Peer RX active key has changed, let's update own TX users */\n\tcur = atomic_read(&rx->peer_rx_active);\n\tnew = ehdr->rx_key_active;\n\tif (tx->key.keys &&\n\t    cur != new &&\n\t    atomic_cmpxchg(&rx->peer_rx_active, cur, new) == cur) {\n\t\tif (new)\n\t\t\ttipc_aead_users_inc(tx->aead[new], INT_MAX);\n\t\tif (cur)\n\t\t\ttipc_aead_users_dec(tx->aead[cur], 0);\n\n\t\tatomic64_set(&rx->sndnxt, 0);\n\t\t/* Mark the point TX key users changed */\n\t\ttx->timer1 = jiffies;\n\n\t\tpr_debug(\"%s: key users changed %d-- %d++, peer %s\\n\",\n\t\t\t tx->name, cur, new, rx->name);\n\t}\n}",
        "static int ti_opp_supply_set_opp(struct dev_pm_set_opp_data *data)\n{\n\tstruct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];\n\tstruct dev_pm_opp_supply *old_supply_vbb = &data->old_opp.supplies[1];\n\tstruct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];": "static int ti_opp_supply_set_opp(struct dev_pm_set_opp_data *data)\n{\n\tstruct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];\n\tstruct dev_pm_opp_supply *old_supply_vbb = &data->old_opp.supplies[1];\n\tstruct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];\n\tstruct dev_pm_opp_supply *new_supply_vbb = &data->new_opp.supplies[1];\n\tstruct device *dev = data->dev;\n\tunsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;\n\tstruct clk *clk = data->clk;\n\tstruct regulator *vdd_reg = data->regulators[0];\n\tstruct regulator *vbb_reg = data->regulators[1];\n\tint vdd_uv;\n\tint ret;\n\n\tvdd_uv = _get_optimal_vdd_voltage(dev, &opp_data,\n\t\t\t\t\t  new_supply_vdd->u_volt);\n\n\tif (new_supply_vdd->u_volt_min < vdd_uv)\n\t\tnew_supply_vdd->u_volt_min = vdd_uv;\n\n\t/* Scaling up? Scale voltage before frequency */\n\tif (freq > old_freq) {\n\t\tret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,\n\t\t\t\t       \"vdd\");\n\t\tif (ret)\n\t\t\tgoto restore_voltage;\n\n\t\tret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, \"vbb\");\n\t\tif (ret)\n\t\t\tgoto restore_voltage;\n\t}\n\n\t/* Change frequency */\n\tdev_dbg(dev, \"%s: switching OPP: %lu Hz --> %lu Hz\\n\",\n\t\t__func__, old_freq, freq);\n\n\tret = clk_set_rate(clk, freq);\n\tif (ret) {\n\t\tdev_err(dev, \"%s: failed to set clock rate: %d\\n\", __func__,\n\t\t\tret);\n\t\tgoto restore_voltage;\n\t}\n\n\t/* Scaling down? Scale voltage after frequency */\n\tif (freq < old_freq) {\n\t\tret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, \"vbb\");\n\t\tif (ret)\n\t\t\tgoto restore_freq;\n\n\t\tret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,\n\t\t\t\t       \"vdd\");\n\t\tif (ret)\n\t\t\tgoto restore_freq;\n\t}\n\n\treturn 0;\n\nrestore_freq:\n\tret = clk_set_rate(clk, old_freq);\n\tif (ret)\n\t\tdev_err(dev, \"%s: failed to restore old-freq (%lu Hz)\\n\",\n\t\t\t__func__, old_freq);\nrestore_voltage:\n\t/* This shouldn't harm even if the voltages weren't updated earlier */\n\tif (old_supply_vdd->u_volt) {\n\t\tret = _opp_set_voltage(dev, old_supply_vbb, 0, vbb_reg, \"vbb\");\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = _opp_set_voltage(dev, old_supply_vdd, 0, vdd_reg,\n\t\t\t\t       \"vdd\");\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn ret;\n}",
        "static void cops_reset(struct net_device *dev, int sleep)\n{\n        struct cops_local *lp = netdev_priv(dev);\n        int ioaddr=dev->base_addr;\n": "static void cops_reset(struct net_device *dev, int sleep)\n{\n        struct cops_local *lp = netdev_priv(dev);\n        int ioaddr=dev->base_addr;\n\n        if(lp->board==TANGENT)\n        {\n                inb(ioaddr);\t\t/* Clear request latch. */\n                outb(0,ioaddr);\t\t/* Clear the TANG_TX_READY flop. */\n                outb(0, ioaddr+TANG_RESET);\t/* Reset the adapter. */\n\n\t\ttangent_wait_reset(ioaddr);\n                outb(0, ioaddr+TANG_CLEAR_INT);\n        }\n        if(lp->board==DAYNA)\n        {\n                outb(0, ioaddr+DAYNA_RESET);\t/* Assert the reset port */\n                inb(ioaddr+DAYNA_RESET);\t/* Clear the reset */\n\t\tif (sleep)\n\t\t\tmsleep(333);\n\t\telse\n\t\t\tmdelay(333);\n        }\n\n\tnetif_wake_queue(dev);\n}",
        "static int init_hi(const struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);": "static int init_hi(const struct drx_demod_instance *demod)\n{\n\tstruct drxj_data *ext_attr = (struct drxj_data *) (NULL);\n\tstruct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);\n\tstruct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);\n\tint rc;\n\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\tcommon_attr = (struct drx_common_attr *) demod->my_common_attr;\n\tdev_addr = demod->my_i2c_dev_addr;\n\n\t/* PATCH for bug 5003, HI ucode v3.1.0 */\n\trc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Timing div, 250ns/Psys */\n\t/* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */\n\text_attr->hi_cfg_timing_div =\n\t    (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;\n\t/* Clipping */\n\tif ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)\n\t\text_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;\n\t/* Bridge delay, uses oscilator clock */\n\t/* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */\n\t/* SDA brdige delay */\n\text_attr->hi_cfg_bridge_delay =\n\t    (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /\n\t    1000;\n\t/* Clipping */\n\tif ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)\n\t\text_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;\n\t/* SCL bridge delay, same as SDA for now */\n\text_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<\n\t\t\t\t      SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);\n\t/* Wakeup key, setting the read flag (as suggest in the documentation) does\n\t   not always result into a working solution (barebones worked VI2C failed).\n\t   Not setting the bit works in all cases . */\n\text_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;\n\t/* port/bridge/power down ctrl */\n\text_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);\n\t/* transit mode time out delay and watch dog divider */\n\text_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;\n\n\trc = hi_cfg_command(demod);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\n\nrw_error:\n\treturn rc;\n}",
        "static void smb20_oplock_break_ack(struct ksmbd_work *work)\n{\n\tstruct smb2_oplock_break *req = smb2_get_msg(work->request_buf);\n\tstruct smb2_oplock_break *rsp = smb2_get_msg(work->response_buf);\n\tstruct ksmbd_file *fp;": "static void smb20_oplock_break_ack(struct ksmbd_work *work)\n{\n\tstruct smb2_oplock_break *req = smb2_get_msg(work->request_buf);\n\tstruct smb2_oplock_break *rsp = smb2_get_msg(work->response_buf);\n\tstruct ksmbd_file *fp;\n\tstruct oplock_info *opinfo = NULL;\n\t__le32 err = 0;\n\tint ret = 0;\n\tu64 volatile_id, persistent_id;\n\tchar req_oplevel = 0, rsp_oplevel = 0;\n\tunsigned int oplock_change_type;\n\n\tvolatile_id = req->VolatileFid;\n\tpersistent_id = req->PersistentFid;\n\treq_oplevel = req->OplockLevel;\n\tksmbd_debug(OPLOCK, \"v_id %llu, p_id %llu request oplock level %d\\n\",\n\t\t    volatile_id, persistent_id, req_oplevel);\n\n\tfp = ksmbd_lookup_fd_slow(work, volatile_id, persistent_id);\n\tif (!fp) {\n\t\trsp->hdr.Status = STATUS_FILE_CLOSED;\n\t\tsmb2_set_err_rsp(work);\n\t\treturn;\n\t}\n\n\topinfo = opinfo_get(fp);\n\tif (!opinfo) {\n\t\tpr_err(\"unexpected null oplock_info\\n\");\n\t\trsp->hdr.Status = STATUS_INVALID_OPLOCK_PROTOCOL;\n\t\tsmb2_set_err_rsp(work);\n\t\tksmbd_fd_put(work, fp);\n\t\treturn;\n\t}\n\n\tif (opinfo->level == SMB2_OPLOCK_LEVEL_NONE) {\n\t\trsp->hdr.Status = STATUS_INVALID_OPLOCK_PROTOCOL;\n\t\tgoto err_out;\n\t}\n\n\tif (opinfo->op_state == OPLOCK_STATE_NONE) {\n\t\tksmbd_debug(SMB, \"unexpected oplock state 0x%x\\n\", opinfo->op_state);\n\t\trsp->hdr.Status = STATUS_UNSUCCESSFUL;\n\t\tgoto err_out;\n\t}\n\n\tif ((opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE ||\n\t     opinfo->level == SMB2_OPLOCK_LEVEL_BATCH) &&\n\t    (req_oplevel != SMB2_OPLOCK_LEVEL_II &&\n\t     req_oplevel != SMB2_OPLOCK_LEVEL_NONE)) {\n\t\terr = STATUS_INVALID_OPLOCK_PROTOCOL;\n\t\toplock_change_type = OPLOCK_WRITE_TO_NONE;\n\t} else if (opinfo->level == SMB2_OPLOCK_LEVEL_II &&\n\t\t   req_oplevel != SMB2_OPLOCK_LEVEL_NONE) {\n\t\terr = STATUS_INVALID_OPLOCK_PROTOCOL;\n\t\toplock_change_type = OPLOCK_READ_TO_NONE;\n\t} else if (req_oplevel == SMB2_OPLOCK_LEVEL_II ||\n\t\t   req_oplevel == SMB2_OPLOCK_LEVEL_NONE) {\n\t\terr = STATUS_INVALID_DEVICE_STATE;\n\t\tif ((opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE ||\n\t\t     opinfo->level == SMB2_OPLOCK_LEVEL_BATCH) &&\n\t\t    req_oplevel == SMB2_OPLOCK_LEVEL_II) {\n\t\t\toplock_change_type = OPLOCK_WRITE_TO_READ;\n\t\t} else if ((opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE ||\n\t\t\t    opinfo->level == SMB2_OPLOCK_LEVEL_BATCH) &&\n\t\t\t   req_oplevel == SMB2_OPLOCK_LEVEL_NONE) {\n\t\t\toplock_change_type = OPLOCK_WRITE_TO_NONE;\n\t\t} else if (opinfo->level == SMB2_OPLOCK_LEVEL_II &&\n\t\t\t   req_oplevel == SMB2_OPLOCK_LEVEL_NONE) {\n\t\t\toplock_change_type = OPLOCK_READ_TO_NONE;\n\t\t} else {\n\t\t\toplock_change_type = 0;\n\t\t}\n\t} else {\n\t\toplock_change_type = 0;\n\t}\n\n\tswitch (oplock_change_type) {\n\tcase OPLOCK_WRITE_TO_READ:\n\t\tret = opinfo_write_to_read(opinfo);\n\t\trsp_oplevel = SMB2_OPLOCK_LEVEL_II;\n\t\tbreak;\n\tcase OPLOCK_WRITE_TO_NONE:\n\t\tret = opinfo_write_to_none(opinfo);\n\t\trsp_oplevel = SMB2_OPLOCK_LEVEL_NONE;\n\t\tbreak;\n\tcase OPLOCK_READ_TO_NONE:\n\t\tret = opinfo_read_to_none(opinfo);\n\t\trsp_oplevel = SMB2_OPLOCK_LEVEL_NONE;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"unknown oplock change 0x%x -> 0x%x\\n\",\n\t\t       opinfo->level, rsp_oplevel);\n\t}\n\n\tif (ret < 0) {\n\t\trsp->hdr.Status = err;\n\t\tgoto err_out;\n\t}\n\n\topinfo_put(opinfo);\n\tksmbd_fd_put(work, fp);\n\topinfo->op_state = OPLOCK_STATE_NONE;\n\twake_up_interruptible_all(&opinfo->oplock_q);\n\n\trsp->StructureSize = cpu_to_le16(24);\n\trsp->OplockLevel = rsp_oplevel;\n\trsp->Reserved = 0;\n\trsp->Reserved2 = 0;\n\trsp->VolatileFid = volatile_id;\n\trsp->PersistentFid = persistent_id;\n\tinc_rfc1001_len(work->response_buf, 24);\n\treturn;\n\nerr_out:\n\topinfo->op_state = OPLOCK_STATE_NONE;\n\twake_up_interruptible_all(&opinfo->oplock_q);\n\n\topinfo_put(opinfo);\n\tksmbd_fd_put(work, fp);\n\tsmb2_set_err_rsp(work);\n}",
        "static int md_alloc(dev_t dev, char *name)\n{\n\t/*\n\t * If dev is zero, name is the name of a device to allocate with\n\t * an arbitrary minor number.  It will be \"md_???\"": "static int md_alloc(dev_t dev, char *name)\n{\n\t/*\n\t * If dev is zero, name is the name of a device to allocate with\n\t * an arbitrary minor number.  It will be \"md_???\"\n\t * If dev is non-zero it must be a device number with a MAJOR of\n\t * MD_MAJOR or mdp_major.  In this case, if \"name\" is NULL, then\n\t * the device is being created by opening a node in /dev.\n\t * If \"name\" is not NULL, the device is being created by\n\t * writing to /sys/module/md_mod/parameters/new_array.\n\t */\n\tstatic DEFINE_MUTEX(disks_mutex);\n\tstruct mddev *mddev;\n\tstruct gendisk *disk;\n\tint partitioned;\n\tint shift;\n\tint unit;\n\tint error ;\n\n\t/*\n\t * Wait for any previous instance of this device to be completely\n\t * removed (mddev_delayed_delete).\n\t */\n\tflush_workqueue(md_misc_wq);\n\n\tmutex_lock(&disks_mutex);\n\tmddev = mddev_alloc(dev);\n\tif (IS_ERR(mddev)) {\n\t\tmutex_unlock(&disks_mutex);\n\t\treturn PTR_ERR(mddev);\n\t}\n\n\tpartitioned = (MAJOR(mddev->unit) != MD_MAJOR);\n\tshift = partitioned ? MdpMinorShift : 0;\n\tunit = MINOR(mddev->unit) >> shift;\n\n\tif (name && !dev) {\n\t\t/* Need to ensure that 'name' is not a duplicate.\n\t\t */\n\t\tstruct mddev *mddev2;\n\t\tspin_lock(&all_mddevs_lock);\n\n\t\tlist_for_each_entry(mddev2, &all_mddevs, all_mddevs)\n\t\t\tif (mddev2->gendisk &&\n\t\t\t    strcmp(mddev2->gendisk->disk_name, name) == 0) {\n\t\t\t\tspin_unlock(&all_mddevs_lock);\n\t\t\t\terror = -EEXIST;\n\t\t\t\tgoto out_unlock_disks_mutex;\n\t\t\t}\n\t\tspin_unlock(&all_mddevs_lock);\n\t}\n\tif (name && dev)\n\t\t/*\n\t\t * Creating /dev/mdNNN via \"newarray\", so adjust hold_active.\n\t\t */\n\t\tmddev->hold_active = UNTIL_STOP;\n\n\terror = -ENOMEM;\n\tdisk = blk_alloc_disk(NUMA_NO_NODE);\n\tif (!disk)\n\t\tgoto out_unlock_disks_mutex;\n\n\tdisk->major = MAJOR(mddev->unit);\n\tdisk->first_minor = unit << shift;\n\tdisk->minors = 1 << shift;\n\tif (name)\n\t\tstrcpy(disk->disk_name, name);\n\telse if (partitioned)\n\t\tsprintf(disk->disk_name, \"md_d%d\", unit);\n\telse\n\t\tsprintf(disk->disk_name, \"md%d\", unit);\n\tdisk->fops = &md_fops;\n\tdisk->private_data = mddev;\n\n\tmddev->queue = disk->queue;\n\tblk_set_stacking_limits(&mddev->queue->limits);\n\tblk_queue_write_cache(mddev->queue, true, true);\n\tdisk->events |= DISK_EVENT_MEDIA_CHANGE;\n\tmddev->gendisk = disk;\n\terror = add_disk(disk);\n\tif (error)\n\t\tgoto out_cleanup_disk;\n\n\terror = kobject_add(&mddev->kobj, &disk_to_dev(disk)->kobj, \"%s\", \"md\");\n\tif (error)\n\t\tgoto out_del_gendisk;\n\n\tkobject_uevent(&mddev->kobj, KOBJ_ADD);\n\tmddev->sysfs_state = sysfs_get_dirent_safe(mddev->kobj.sd, \"array_state\");\n\tmddev->sysfs_level = sysfs_get_dirent_safe(mddev->kobj.sd, \"level\");\n\tgoto out_unlock_disks_mutex;\n\nout_del_gendisk:\n\tdel_gendisk(disk);\nout_cleanup_disk:\n\tblk_cleanup_disk(disk);\nout_unlock_disks_mutex:\n\tmutex_unlock(&disks_mutex);\n\tmddev_put(mddev);\n\treturn error;\n}",
        "static void soi763a_6810_start(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tstatic const struct cmd bridge_init_2[] = {\n\t\t{TP6800_R7A_BLK_THRLD, 0x00},": "static void soi763a_6810_start(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tstatic const struct cmd bridge_init_2[] = {\n\t\t{TP6800_R7A_BLK_THRLD, 0x00},\n\t\t{TP6800_R79_QUALITY, 0x04},\n\t\t{TP6800_R79_QUALITY, 0x01},\n\t};\n\tstatic const struct cmd bridge_init_3[] = {\n\t\t{TP6800_R31_PIXEL_START, 0x20},\n\t\t{TP6800_R32_PIXEL_END_L, 0x9f},\n\t\t{TP6800_R33_PIXEL_END_H, 0x02},\n\t\t{TP6800_R34_LINE_START, 0x13},\n\t\t{TP6800_R35_LINE_END_L, 0xf8},\n\t\t{TP6800_R36_LINE_END_H, 0x01},\n\t};\n\tstatic const struct cmd bridge_init_6[] = {\n\t\t{0x08, 0xff},\n\t\t{0x09, 0xff},\n\t\t{0x0a, 0x5f},\n\t\t{0x0b, 0x80},\n\t};\n\n\treg_w(gspca_dev, 0x22, gspca_dev->alt);\n\tbulk_w(gspca_dev, 0x03, color_null, sizeof color_null);\n\treg_w(gspca_dev, 0x59, 0x40);\n\tif (sd->sensor == SENSOR_CX0342)\n\t\tsetexposure(gspca_dev, v4l2_ctrl_g_ctrl(gspca_dev->exposure),\n\t\t\tv4l2_ctrl_g_ctrl(gspca_dev->gain),\n\t\t\tv4l2_ctrl_g_ctrl(sd->blue),\n\t\t\tv4l2_ctrl_g_ctrl(sd->red));\n\telse\n\t\tsetexposure(gspca_dev, v4l2_ctrl_g_ctrl(gspca_dev->exposure),\n\t\t\tv4l2_ctrl_g_ctrl(gspca_dev->gain), 0, 0);\n\treg_w_buf(gspca_dev, bridge_init_2, ARRAY_SIZE(bridge_init_2));\n\treg_w_buf(gspca_dev, tp6810_ov_init_common,\n\t\t\tARRAY_SIZE(tp6810_ov_init_common));\n\treg_w_buf(gspca_dev, bridge_init_3, ARRAY_SIZE(bridge_init_3));\n\tif (gspca_dev->curr_mode) {\n\t\treg_w(gspca_dev, 0x4a, 0x7f);\n\t\treg_w(gspca_dev, 0x07, 0x05);\n\t\treg_w(gspca_dev, TP6800_R78_FORMAT, 0x00);\t/* vga */\n\t} else {\n\t\treg_w(gspca_dev, 0x4a, 0xff);\n\t\treg_w(gspca_dev, 0x07, 0x85);\n\t\treg_w(gspca_dev, TP6800_R78_FORMAT, 0x01);\t/* qvga */\n\t}\n\tsetgamma(gspca_dev, v4l2_ctrl_g_ctrl(sd->gamma));\n\treg_w_buf(gspca_dev, tp6810_bridge_start,\n\t\t\tARRAY_SIZE(tp6810_bridge_start));\n\n\tif (gspca_dev->curr_mode) {\n\t\treg_w(gspca_dev, 0x4f, 0x00);\n\t\treg_w(gspca_dev, 0x4e, 0x7c);\n\t}\n\n\treg_w(gspca_dev, 0x00, 0x00);\n\n\tsetsharpness(gspca_dev, v4l2_ctrl_g_ctrl(sd->sharpness));\n\tbulk_w(gspca_dev, 0x03, color_gain[SENSOR_SOI763A],\n\t\t\t\tARRAY_SIZE(color_gain[0]));\n\tset_led(gspca_dev, 1);\n\treg_w(gspca_dev, TP6800_R3F_FRAME_RATE, 0xf0);\n\tif (sd->sensor == SENSOR_CX0342)\n\t\tsetexposure(gspca_dev, v4l2_ctrl_g_ctrl(gspca_dev->exposure),\n\t\t\tv4l2_ctrl_g_ctrl(gspca_dev->gain),\n\t\t\tv4l2_ctrl_g_ctrl(sd->blue),\n\t\t\tv4l2_ctrl_g_ctrl(sd->red));\n\telse\n\t\tsetexposure(gspca_dev, v4l2_ctrl_g_ctrl(gspca_dev->exposure),\n\t\t\tv4l2_ctrl_g_ctrl(gspca_dev->gain), 0, 0);\n\treg_w_buf(gspca_dev, bridge_init_6, ARRAY_SIZE(bridge_init_6));\n}",
        "static int sgp40_measure_resistance_raw(struct sgp40_data *data, u16 *resistance_raw)\n{\n\tint ret;\n\tstruct i2c_client *client = data->client;\n\tu32 ticks;": "static int sgp40_measure_resistance_raw(struct sgp40_data *data, u16 *resistance_raw)\n{\n\tint ret;\n\tstruct i2c_client *client = data->client;\n\tu32 ticks;\n\tu16 ticks16;\n\tu8 crc;\n\tstruct sgp40_tg_measure tg = {.command = {0x26, 0x0F}};\n\tstruct sgp40_tg_result tgres;\n\n\tmutex_lock(&data->lock);\n\n\tticks = (data->rht / 10) * 65535 / 10000;\n\tticks16 = (u16)clamp(ticks, 0u, 65535u); /* clamp between 0 .. 100 %rH */\n\ttg.rht_ticks = cpu_to_be16(ticks16);\n\ttg.rht_crc = crc8(sgp40_crc8_table, (u8 *)&tg.rht_ticks, 2, SGP40_CRC8_INIT);\n\n\tticks = ((data->temp + 45000) / 10 ) * 65535 / 17500;\n\tticks16 = (u16)clamp(ticks, 0u, 65535u); /* clamp between -45 .. +130 \u00b0C */\n\ttg.temp_ticks = cpu_to_be16(ticks16);\n\ttg.temp_crc = crc8(sgp40_crc8_table, (u8 *)&tg.temp_ticks, 2, SGP40_CRC8_INIT);\n\n\tmutex_unlock(&data->lock);\n\n\tret = i2c_master_send(client, (const char *)&tg, sizeof(tg));\n\tif (ret != sizeof(tg)) {\n\t\tdev_warn(data->dev, \"i2c_master_send ret: %d sizeof: %zu\\n\", ret, sizeof(tg));\n\t\treturn -EIO;\n\t}\n\tmsleep(30);\n\n\tret = i2c_master_recv(client, (u8 *)&tgres, sizeof(tgres));\n\tif (ret < 0)\n\t\treturn ret;\n\tif (ret != sizeof(tgres)) {\n\t\tdev_warn(data->dev, \"i2c_master_recv ret: %d sizeof: %zu\\n\", ret, sizeof(tgres));\n\t\treturn -EIO;\n\t}\n\n\tcrc = crc8(sgp40_crc8_table, (u8 *)&tgres.res_ticks, 2, SGP40_CRC8_INIT);\n\tif (crc != tgres.res_crc) {\n\t\tdev_err(data->dev, \"CRC error while measure-raw\\n\");\n\t\treturn -EIO;\n\t}\n\n\t*resistance_raw = be16_to_cpu(tgres.res_ticks);\n\n\treturn 0;\n}",
        "static void raid10_set_cluster_sync_high(struct r10conf *conf)\n{\n\tsector_t window_size;\n\tint extra_chunk, chunks;\n": "static void raid10_set_cluster_sync_high(struct r10conf *conf)\n{\n\tsector_t window_size;\n\tint extra_chunk, chunks;\n\n\t/*\n\t * First, here we define \"stripe\" as a unit which across\n\t * all member devices one time, so we get chunks by use\n\t * raid_disks / near_copies. Otherwise, if near_copies is\n\t * close to raid_disks, then resync window could increases\n\t * linearly with the increase of raid_disks, which means\n\t * we will suspend a really large IO window while it is not\n\t * necessary. If raid_disks is not divisible by near_copies,\n\t * an extra chunk is needed to ensure the whole \"stripe\" is\n\t * covered.\n\t */\n\n\tchunks = conf->geo.raid_disks / conf->geo.near_copies;\n\tif (conf->geo.raid_disks % conf->geo.near_copies == 0)\n\t\textra_chunk = 0;\n\telse\n\t\textra_chunk = 1;\n\twindow_size = (chunks + extra_chunk) * conf->mddev->chunk_sectors;\n\n\t/*\n\t * At least use a 32M window to align with raid1's resync window\n\t */\n\twindow_size = (CLUSTER_RESYNC_WINDOW_SECTORS > window_size) ?\n\t\t\tCLUSTER_RESYNC_WINDOW_SECTORS : window_size;\n\n\tconf->cluster_sync_high = conf->cluster_sync_low + window_size;\n}",
        "static void cal_camerarx_config(struct cal_camerarx *phy, s64 link_freq)\n{\n\tunsigned int reg0, reg1;\n\tunsigned int ths_term, ths_settle;\n": "static void cal_camerarx_config(struct cal_camerarx *phy, s64 link_freq)\n{\n\tunsigned int reg0, reg1;\n\tunsigned int ths_term, ths_settle;\n\n\t/* DPHY timing configuration */\n\n\t/* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */\n\tths_term = div_s64(20 * link_freq, 1000 * 1000 * 1000);\n\tphy_dbg(1, phy, \"ths_term: %d (0x%02x)\\n\", ths_term, ths_term);\n\n\t/* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */\n\tths_settle = div_s64(105 * link_freq, 1000 * 1000 * 1000) + 4;\n\tphy_dbg(1, phy, \"ths_settle: %d (0x%02x)\\n\", ths_settle, ths_settle);\n\n\treg0 = camerarx_read(phy, CAL_CSI2_PHY_REG0);\n\tcal_set_field(&reg0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,\n\t\t      CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);\n\tcal_set_field(&reg0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);\n\tcal_set_field(&reg0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);\n\n\tphy_dbg(1, phy, \"CSI2_%d_REG0 = 0x%08x\\n\", phy->instance, reg0);\n\tcamerarx_write(phy, CAL_CSI2_PHY_REG0, reg0);\n\n\treg1 = camerarx_read(phy, CAL_CSI2_PHY_REG1);\n\tcal_set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);\n\tcal_set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);\n\tcal_set_field(&reg1, TCLK_MISS,\n\t\t      CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);\n\tcal_set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);\n\n\tphy_dbg(1, phy, \"CSI2_%d_REG1 = 0x%08x\\n\", phy->instance, reg1);\n\tcamerarx_write(phy, CAL_CSI2_PHY_REG1, reg1);\n}",
        "static int audit_netlink_ok(struct sk_buff *skb, u16 msg_type)\n{\n\tint err = 0;\n\n\t/* Only support initial user namespace for now. */": "static int audit_netlink_ok(struct sk_buff *skb, u16 msg_type)\n{\n\tint err = 0;\n\n\t/* Only support initial user namespace for now. */\n\t/*\n\t * We return ECONNREFUSED because it tricks userspace into thinking\n\t * that audit was not configured into the kernel.  Lots of users\n\t * configure their PAM stack (because that's what the distro does)\n\t * to reject login if unable to send messages to audit.  If we return\n\t * ECONNREFUSED the PAM stack thinks the kernel does not have audit\n\t * configured in and will let login proceed.  If we return EPERM\n\t * userspace will reject all logins.  This should be removed when we\n\t * support non init namespaces!!\n\t */\n\tif (current_user_ns() != &init_user_ns)\n\t\treturn -ECONNREFUSED;\n\n\tswitch (msg_type) {\n\tcase AUDIT_LIST:\n\tcase AUDIT_ADD:\n\tcase AUDIT_DEL:\n\t\treturn -EOPNOTSUPP;\n\tcase AUDIT_GET:\n\tcase AUDIT_SET:\n\tcase AUDIT_GET_FEATURE:\n\tcase AUDIT_SET_FEATURE:\n\tcase AUDIT_LIST_RULES:\n\tcase AUDIT_ADD_RULE:\n\tcase AUDIT_DEL_RULE:\n\tcase AUDIT_SIGNAL_INFO:\n\tcase AUDIT_TTY_GET:\n\tcase AUDIT_TTY_SET:\n\tcase AUDIT_TRIM:\n\tcase AUDIT_MAKE_EQUIV:\n\t\t/* Only support auditd and auditctl in initial pid namespace\n\t\t * for now. */\n\t\tif (task_active_pid_ns(current) != &init_pid_ns)\n\t\t\treturn -EPERM;\n\n\t\tif (!netlink_capable(skb, CAP_AUDIT_CONTROL))\n\t\t\terr = -EPERM;\n\t\tbreak;\n\tcase AUDIT_USER:\n\tcase AUDIT_FIRST_USER_MSG ... AUDIT_LAST_USER_MSG:\n\tcase AUDIT_FIRST_USER_MSG2 ... AUDIT_LAST_USER_MSG2:\n\t\tif (!netlink_capable(skb, CAP_AUDIT_WRITE))\n\t\t\terr = -EPERM;\n\t\tbreak;\n\tdefault:  /* bad msg */\n\t\terr = -EINVAL;\n\t}\n\n\treturn err;\n}",
        "static void test_getsockopt_override(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_getsockopt *obj;\n\tstruct bpf_link *link_set_eisconn = NULL;\n\tint buf;": "static void test_getsockopt_override(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_getsockopt *obj;\n\tstruct bpf_link *link_set_eisconn = NULL;\n\tint buf;\n\tsocklen_t optlen = sizeof(buf);\n\n\tobj = cgroup_getset_retval_getsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach getsockopt that sets retval to -EISCONN. Assert that this\n\t * overrides the value from kernel.\n\t */\n\tlink_set_eisconn = bpf_program__attach_cgroup(obj->progs.set_eisconn,\n\t\t\t\t\t\t      cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_set_eisconn, \"cg-attach-set_eisconn\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(getsockopt(sock_fd, SOL_CUSTOM, 0,\n\t\t\t\t   &buf, &optlen), \"getsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EISCONN, \"getsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 1, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_set_eisconn);\n\n\tcgroup_getset_retval_getsockopt__destroy(obj);\n}",
        "static void timerlat_top_usage(char *usage)\n{\n\tint i;\n\n\tstatic const char *const msg[] = {": "static void timerlat_top_usage(char *usage)\n{\n\tint i;\n\n\tstatic const char *const msg[] = {\n\t\t\"\",\n\t\t\"  usage: rtla timerlat [top] [-h] [-q] [-a us] [-d s] [-D] [-n] [-p us] [-i us] [-T us] [-s us] \\\\\",\n\t\t\"\t  [[-t[=file]] [-e sys[:event]] [--filter <filter>] [--trigger <trigger>] [-c cpu-list] \\\\\",\n\t\t\"\t  [-P priority] [--dma-latency us]\",\n\t\t\"\",\n\t\t\"\t  -h/--help: print this menu\",\n\t\t\"\t  -a/--auto: set automatic trace mode, stopping the session if argument in us latency is hit\",\n\t\t\"\t  -p/--period us: timerlat period in us\",\n\t\t\"\t  -i/--irq us: stop trace if the irq latency is higher than the argument in us\",\n\t\t\"\t  -T/--thread us: stop trace if the thread latency is higher than the argument in us\",\n\t\t\"\t  -s/--stack us: save the stack trace at the IRQ if a thread latency is higher than the argument in us\",\n\t\t\"\t  -c/--cpus cpus: run the tracer only on the given cpus\",\n\t\t\"\t  -d/--duration time[m|h|d]: duration of the session in seconds\",\n\t\t\"\t  -D/--debug: print debug info\",\n\t\t\"\t  -t/--trace[=file]: save the stopped trace to [file|timerlat_trace.txt]\",\n\t\t\"\t  -e/--event <sys:event>: enable the <sys:event> in the trace instance, multiple -e are allowed\",\n\t\t\"\t     --filter <command>: enable a trace event filter to the previous -e event\",\n\t\t\"\t     --trigger <command>: enable a trace event trigger to the previous -e event\",\n\t\t\"\t  -n/--nano: display data in nanoseconds\",\n\t\t\"\t  -q/--quiet print only a summary at the end\",\n\t\t\"\t     --dma-latency us: set /dev/cpu_dma_latency latency <us> to reduce exit from idle latency\",\n\t\t\"\t  -P/--priority o:prio|r:prio|f:prio|d:runtime:period : set scheduling parameters\",\n\t\t\"\t\to:prio - use SCHED_OTHER with prio\",\n\t\t\"\t\tr:prio - use SCHED_RR with prio\",\n\t\t\"\t\tf:prio - use SCHED_FIFO with prio\",\n\t\t\"\t\td:runtime[us|ms|s]:period[us|ms|s] - use SCHED_DEADLINE with runtime and period\",\n\t\t\"\t\t\t\t\t\t       in nanoseconds\",\n\t\tNULL,\n\t};\n\n\tif (usage)\n\t\tfprintf(stderr, \"%s\\n\", usage);\n\n\tfprintf(stderr, \"rtla timerlat top: a per-cpu summary of the timer latency (version %s)\\n\",\n\t\t\tVERSION);\n\n\tfor (i = 0; msg[i]; i++)\n\t\tfprintf(stderr, \"%s\\n\", msg[i]);\n\texit(1);\n}",
        "static int gate_ctrl(struct dvb_frontend *fe, int enable)\n{\n\tstruct stv *state = fe->demodulator_priv;\n\tu8 i2crpt = state->i2crpt & ~0x86;\n": "static int gate_ctrl(struct dvb_frontend *fe, int enable)\n{\n\tstruct stv *state = fe->demodulator_priv;\n\tu8 i2crpt = state->i2crpt & ~0x86;\n\n\t/*\n\t * mutex_lock note: Concurrent I2C gate bus accesses must be\n\t * prevented (STV0910 = dual demod on a single IC with a single I2C\n\t * gate/bus, and two tuners attached), similar to most (if not all)\n\t * other I2C host interfaces/buses.\n\t *\n\t * enable=1 (open I2C gate) will grab the lock\n\t * enable=0 (close I2C gate) releases the lock\n\t */\n\n\tif (enable) {\n\t\tmutex_lock(&state->base->i2c_lock);\n\t\ti2crpt |= 0x80;\n\t} else {\n\t\ti2crpt |= 0x02;\n\t}\n\n\tif (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :\n\t\t      RSTV0910_P1_I2CRPT, i2crpt) < 0) {\n\t\t/* don't hold the I2C bus lock on failure */\n\t\tif (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))\n\t\t\tmutex_unlock(&state->base->i2c_lock);\n\t\tdev_err(&state->base->i2c->dev,\n\t\t\t\"%s() write_reg failure (enable=%d)\\n\",\n\t\t\t__func__, enable);\n\t\treturn -EIO;\n\t}\n\n\tstate->i2crpt = i2crpt;\n\n\tif (!enable)\n\t\tif (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))\n\t\t\tmutex_unlock(&state->base->i2c_lock);\n\treturn 0;\n}",
        "static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)\n{\n\tstruct xd_info *xd_card = &chip->xd_card;\n\tstruct zone_entry *zone;\n\tint retval;": "static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)\n{\n\tstruct xd_info *xd_card = &chip->xd_card;\n\tstruct zone_entry *zone;\n\tint retval;\n\tu32 start, end, i;\n\tu16 max_logoff, cur_fst_page_logoff;\n\tu16 cur_lst_page_logoff, ent_lst_page_logoff;\n\tu8 redunt[11];\n\n\tdev_dbg(rtsx_dev(chip), \"%s: %d\\n\", __func__, zone_no);\n\n\tif (!xd_card->zone) {\n\t\tretval = xd_init_l2p_tbl(chip);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\treturn retval;\n\t}\n\n\tif (xd_card->zone[zone_no].build_flag) {\n\t\tdev_dbg(rtsx_dev(chip), \"l2p table of zone %d has been built\\n\",\n\t\t\tzone_no);\n\t\treturn STATUS_SUCCESS;\n\t}\n\n\tzone = &xd_card->zone[zone_no];\n\n\tif (!zone->l2p_table) {\n\t\tzone->l2p_table = vmalloc(2000);\n\t\tif (!zone->l2p_table)\n\t\t\tgoto build_fail;\n\t}\n\tmemset((u8 *)(zone->l2p_table), 0xff, 2000);\n\n\tif (!zone->free_table) {\n\t\tzone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);\n\t\tif (!zone->free_table)\n\t\t\tgoto build_fail;\n\t}\n\tmemset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);\n\n\tif (zone_no == 0) {\n\t\tif (xd_card->cis_block == 0xFFFF)\n\t\t\tstart = 0;\n\t\telse\n\t\t\tstart = xd_card->cis_block + 1;\n\t\tif (XD_CHK_4MB(xd_card)) {\n\t\t\tend = 0x200;\n\t\t\tmax_logoff = 499;\n\t\t} else {\n\t\t\tend = 0x400;\n\t\t\tmax_logoff = 999;\n\t\t}\n\t} else {\n\t\tstart = (u32)(zone_no) << 10;\n\t\tend = (u32)(zone_no + 1) << 10;\n\t\tmax_logoff = 999;\n\t}\n\n\tdev_dbg(rtsx_dev(chip), \"start block 0x%x, end block 0x%x\\n\",\n\t\tstart, end);\n\n\tzone->set_index = 0;\n\tzone->get_index = 0;\n\tzone->unused_blk_cnt = 0;\n\n\tfor (i = start; i < end; i++) {\n\t\tu32 page_addr = i << xd_card->block_shift;\n\t\tu32 phy_block;\n\n\t\tretval = xd_read_redundant(chip, page_addr, redunt, 11);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tcontinue;\n\n\t\tif (redunt[BLOCK_STATUS] != 0xFF) {\n\t\t\tdev_dbg(rtsx_dev(chip), \"bad block\\n\");\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (xd_check_data_blank(redunt)) {\n\t\t\tdev_dbg(rtsx_dev(chip), \"blank block\\n\");\n\t\t\txd_set_unused_block(chip, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tcur_fst_page_logoff = xd_load_log_block_addr(redunt);\n\t\tif (cur_fst_page_logoff == 0xFFFF ||\n\t\t    cur_fst_page_logoff > max_logoff) {\n\t\t\tretval = xd_erase_block(chip, i);\n\t\t\tif (retval == STATUS_SUCCESS)\n\t\t\t\txd_set_unused_block(chip, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (zone_no == 0 && cur_fst_page_logoff == 0 &&\n\t\t    redunt[PAGE_STATUS] != XD_GPG)\n\t\t\tXD_SET_MBR_FAIL(xd_card);\n\n\t\tif (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {\n\t\t\tzone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);\n\t\t\tcontinue;\n\t\t}\n\n\t\tphy_block = zone->l2p_table[cur_fst_page_logoff] +\n\t\t\t((u32)((zone_no) << 10));\n\n\t\tpage_addr = ((i + 1) << xd_card->block_shift) - 1;\n\n\t\tretval = xd_read_redundant(chip, page_addr, redunt, 11);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tcontinue;\n\n\t\tcur_lst_page_logoff = xd_load_log_block_addr(redunt);\n\t\tif (cur_lst_page_logoff == cur_fst_page_logoff) {\n\t\t\tint m;\n\n\t\t\tpage_addr = ((phy_block + 1) <<\n\t\t\t\txd_card->block_shift) - 1;\n\n\t\t\tfor (m = 0; m < 3; m++) {\n\t\t\t\tretval = xd_read_redundant(chip, page_addr,\n\t\t\t\t\t\t\t   redunt, 11);\n\t\t\t\tif (retval == STATUS_SUCCESS)\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (m == 3) {\n\t\t\t\tzone->l2p_table[cur_fst_page_logoff] =\n\t\t\t\t\t(u16)(i & 0x3FF);\n\t\t\t\tretval = xd_erase_block(chip, phy_block);\n\t\t\t\tif (retval == STATUS_SUCCESS)\n\t\t\t\t\txd_set_unused_block(chip, phy_block);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tent_lst_page_logoff = xd_load_log_block_addr(redunt);\n\t\t\tif (ent_lst_page_logoff != cur_fst_page_logoff) {\n\t\t\t\tzone->l2p_table[cur_fst_page_logoff] =\n\t\t\t\t\t(u16)(i & 0x3FF);\n\t\t\t\tretval = xd_erase_block(chip, phy_block);\n\t\t\t\tif (retval == STATUS_SUCCESS)\n\t\t\t\t\txd_set_unused_block(chip, phy_block);\n\t\t\t\tcontinue;\n\t\t\t} else {\n\t\t\t\tretval = xd_erase_block(chip, i);\n\t\t\t\tif (retval == STATUS_SUCCESS)\n\t\t\t\t\txd_set_unused_block(chip, i);\n\t\t\t}\n\t\t} else {\n\t\t\tretval = xd_erase_block(chip, i);\n\t\t\tif (retval == STATUS_SUCCESS)\n\t\t\t\txd_set_unused_block(chip, i);\n\t\t}\n\t}\n\n\tif (XD_CHK_4MB(xd_card))\n\t\tend = 500;\n\telse\n\t\tend = 1000;\n\n\ti = 0;\n\tfor (start = 0; start < end; start++) {\n\t\tif (zone->l2p_table[start] == 0xFFFF)\n\t\t\ti++;\n\t}\n\n\tdev_dbg(rtsx_dev(chip), \"Block count %d, invalid L2P entry %d\\n\",\n\t\tend, i);\n\tdev_dbg(rtsx_dev(chip), \"Total unused block: %d\\n\",\n\t\tzone->unused_blk_cnt);\n\n\tif ((zone->unused_blk_cnt - i) < 1)\n\t\tchip->card_wp |= XD_CARD;\n\n\tzone->build_flag = 1;\n\n\treturn STATUS_SUCCESS;\n\nbuild_fail:\n\tvfree(zone->l2p_table);\n\tzone->l2p_table = NULL;\n\tvfree(zone->free_table);\n\tzone->free_table = NULL;\n\n\treturn STATUS_FAIL;\n}",
        "static int ssam_serial_hub_pm_freeze(struct device *dev)\n{\n\tstruct ssam_controller *c = dev_get_drvdata(dev);\n\tint status;\n": "static int ssam_serial_hub_pm_freeze(struct device *dev)\n{\n\tstruct ssam_controller *c = dev_get_drvdata(dev);\n\tint status;\n\n\t/*\n\t * During hibernation image creation, we only have to ensure that the\n\t * EC doesn't send us any events. This is done via the display-off\n\t * and D0-exit notifications. Note that this sets up the wakeup IRQ\n\t * on the EC side, however, we have disabled it by default on our side\n\t * and won't enable it here.\n\t *\n\t * See ssam_serial_hub_poweroff() for more details on the hibernation\n\t * process.\n\t */\n\n\tstatus = ssam_ctrl_notif_d0_exit(c);\n\tif (status) {\n\t\tssam_err(c, \"pm: D0-exit notification failed: %d\\n\", status);\n\t\tssam_ctrl_notif_display_on(c);\n\t\treturn status;\n\t}\n\n\tWARN_ON(ssam_controller_suspend(c));\n\treturn 0;\n}",
        "static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)\n{\n\tstruct device *dev = uc->dev;\n\tconst struct firmware *fw = NULL;\n\tconst char *p, *s;": "static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)\n{\n\tstruct device *dev = uc->dev;\n\tconst struct firmware *fw = NULL;\n\tconst char *p, *s;\n\tconst char *eof;\n\tint err, row, len, line_sz, line_cnt = 0;\n\tunsigned long start_time = jiffies;\n\tstruct fw_config_table  fw_cfg;\n\tu8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];\n\tu8 *wr_buf;\n\n\terr = request_firmware(&fw, ccg_fw_names[mode], dev);\n\tif (err) {\n\t\tdev_err(dev, \"request %s failed err=%d\\n\",\n\t\t\tccg_fw_names[mode], err);\n\t\treturn err;\n\t}\n\n\tif (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>\n\t\t\tCCG_DEVINFO_FWMODE_SHIFT) == FW2) {\n\t\terr = ccg_cmd_port_control(uc, false);\n\t\tif (err < 0)\n\t\t\tgoto release_fw;\n\t\terr = ccg_cmd_jump_boot_mode(uc, 0);\n\t\tif (err < 0)\n\t\t\tgoto release_fw;\n\t}\n\n\teof = fw->data + fw->size;\n\n\t/*\n\t * check if signed fw\n\t * last part of fw image is fw cfg table and signature\n\t */\n\tif (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))\n\t\tgoto not_signed_fw;\n\n\tmemcpy((uint8_t *)&fw_cfg, fw->data + fw->size -\n\t       sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));\n\n\tif (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {\n\t\tdev_info(dev, \"not a signed image\\n\");\n\t\tgoto not_signed_fw;\n\t}\n\teof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);\n\n\tmemcpy((uint8_t *)&fw_cfg_sig,\n\t       fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));\n\n\t/* flash fw config table and signature first */\n\terr = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,\n\t\t\t\t      FLASH_FWCT1_WR_CMD);\n\tif (err)\n\t\tgoto release_fw;\n\n\terr = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,\n\t\t\t\t      FLASH_FWCT2_WR_CMD);\n\tif (err)\n\t\tgoto release_fw;\n\n\terr = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,\n\t\t\t\t      FLASH_FWCT_SIG_WR_CMD);\n\tif (err)\n\t\tgoto release_fw;\n\nnot_signed_fw:\n\twr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);\n\tif (!wr_buf) {\n\t\terr = -ENOMEM;\n\t\tgoto release_fw;\n\t}\n\n\terr = ccg_cmd_enter_flashing(uc);\n\tif (err)\n\t\tgoto release_mem;\n\n\t/*****************************************************************\n\t * CCG firmware image (.cyacd) file line format\n\t *\n\t * :00rrrrllll[dd....]cc/r/n\n\t *\n\t * :00   header\n\t * rrrr is row number to flash\t\t\t\t(4 char)\n\t * llll is data len to flash\t\t\t\t(4 char)\n\t * dd   is a data field represents one byte of data\t(512 char)\n\t * cc   is checksum\t\t\t\t\t(2 char)\n\t * \\r\\n newline\n\t *\n\t * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527\n\t *\n\t *****************************************************************/\n\n\tp = strnchr(fw->data, fw->size, ':');\n\twhile (p < eof) {\n\t\ts = strnchr(p + 1, eof - p - 1, ':');\n\n\t\tif (!s)\n\t\t\ts = eof;\n\n\t\tline_sz = s - p;\n\n\t\tif (line_sz != CYACD_LINE_SIZE) {\n\t\t\tdev_err(dev, \"Bad FW format line_sz=%d\\n\", line_sz);\n\t\t\terr =  -EINVAL;\n\t\t\tgoto release_mem;\n\t\t}\n\n\t\tif (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {\n\t\t\terr =  -EINVAL;\n\t\t\tgoto release_mem;\n\t\t}\n\n\t\trow = get_unaligned_be16(wr_buf);\n\t\tlen = get_unaligned_be16(&wr_buf[2]);\n\n\t\tif (len != CCG4_ROW_SIZE) {\n\t\t\terr =  -EINVAL;\n\t\t\tgoto release_mem;\n\t\t}\n\n\t\terr = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,\n\t\t\t\t\t      FLASH_WR_CMD);\n\t\tif (err)\n\t\t\tgoto release_mem;\n\n\t\tline_cnt++;\n\t\tp = s;\n\t}\n\n\tdev_info(dev, \"total %d row flashed. time: %dms\\n\",\n\t\t line_cnt, jiffies_to_msecs(jiffies - start_time));\n\n\terr = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 :  FW1);\n\tif (err)\n\t\tdev_err(dev, \"%s validation failed err=%d\\n\",\n\t\t\t(mode == PRIMARY) ? \"FW2\" :  \"FW1\", err);\n\telse\n\t\tdev_info(dev, \"%s validated\\n\",\n\t\t\t (mode == PRIMARY) ? \"FW2\" :  \"FW1\");\n\n\terr = ccg_cmd_port_control(uc, false);\n\tif (err < 0)\n\t\tgoto release_mem;\n\n\terr = ccg_cmd_reset(uc);\n\tif (err < 0)\n\t\tgoto release_mem;\n\n\terr = ccg_cmd_port_control(uc, true);\n\tif (err < 0)\n\t\tgoto release_mem;\n\nrelease_mem:\n\tkfree(wr_buf);\n\nrelease_fw:\n\trelease_firmware(fw);\n\treturn err;\n}",
        "static int ad7192_setup(struct ad7192_state *st, struct device_node *np)\n{\n\tstruct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);\n\tbool rej60_en, refin2_en;\n\tbool buf_en, bipolar, burnout_curr_en;": "static int ad7192_setup(struct ad7192_state *st, struct device_node *np)\n{\n\tstruct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);\n\tbool rej60_en, refin2_en;\n\tbool buf_en, bipolar, burnout_curr_en;\n\tunsigned long long scale_uv;\n\tint i, ret, id;\n\n\t/* reset the serial interface */\n\tret = ad_sd_reset(&st->sd, 48);\n\tif (ret < 0)\n\t\treturn ret;\n\tusleep_range(500, 1000); /* Wait for at least 500us */\n\n\t/* write/read test for device presence */\n\tret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);\n\tif (ret)\n\t\treturn ret;\n\n\tid &= AD7192_ID_MASK;\n\n\tif (id != st->chip_info->chip_id)\n\t\tdev_warn(&st->sd.spi->dev, \"device ID query failed (0x%X)\\n\",\n\t\t\t id);\n\n\tst->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |\n\t\tAD7192_MODE_CLKSRC(st->clock_sel) |\n\t\tAD7192_MODE_RATE(480);\n\n\tst->conf = AD7192_CONF_GAIN(0);\n\n\trej60_en = of_property_read_bool(np, \"adi,rejection-60-Hz-enable\");\n\tif (rej60_en)\n\t\tst->mode |= AD7192_MODE_REJ60;\n\n\trefin2_en = of_property_read_bool(np, \"adi,refin2-pins-enable\");\n\tif (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)\n\t\tst->conf |= AD7192_CONF_REFSEL;\n\n\tst->conf &= ~AD7192_CONF_CHOP;\n\tst->f_order = AD7192_NO_SYNC_FILTER;\n\n\tbuf_en = of_property_read_bool(np, \"adi,buffer-enable\");\n\tif (buf_en)\n\t\tst->conf |= AD7192_CONF_BUF;\n\n\tbipolar = of_property_read_bool(np, \"bipolar\");\n\tif (!bipolar)\n\t\tst->conf |= AD7192_CONF_UNIPOLAR;\n\n\tburnout_curr_en = of_property_read_bool(np,\n\t\t\t\t\t\t\"adi,burnout-currents-enable\");\n\tif (burnout_curr_en && buf_en) {\n\t\tst->conf |= AD7192_CONF_BURN;\n\t} else if (burnout_curr_en) {\n\t\tdev_warn(&st->sd.spi->dev,\n\t\t\t \"Can't enable burnout currents: see CHOP or buffer\\n\");\n\t}\n\n\tret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);\n\tif (ret)\n\t\treturn ret;\n\n\tret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);\n\tif (ret)\n\t\treturn ret;\n\n\tret = ad7192_calibrate_all(st);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Populate available ADC input ranges */\n\tfor (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {\n\t\tscale_uv = ((u64)st->int_vref_mv * 100000000)\n\t\t\t>> (indio_dev->channels[0].scan_type.realbits -\n\t\t\t((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));\n\t\tscale_uv >>= i;\n\n\t\tst->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;\n\t\tst->scale_avail[i][0] = scale_uv;\n\t}\n\n\treturn 0;\n}",
        "static void futex_cleanup_begin(struct task_struct *tsk)\n{\n\t/*\n\t * Prevent various race issues against a concurrent incoming waiter\n\t * including live locks by forcing the waiter to block on": "static void futex_cleanup_begin(struct task_struct *tsk)\n{\n\t/*\n\t * Prevent various race issues against a concurrent incoming waiter\n\t * including live locks by forcing the waiter to block on\n\t * tsk->futex_exit_mutex when it observes FUTEX_STATE_EXITING in\n\t * attach_to_pi_owner().\n\t */\n\tmutex_lock(&tsk->futex_exit_mutex);\n\n\t/*\n\t * Switch the state to FUTEX_STATE_EXITING under tsk->pi_lock.\n\t *\n\t * This ensures that all subsequent checks of tsk->futex_state in\n\t * attach_to_pi_owner() must observe FUTEX_STATE_EXITING with\n\t * tsk->pi_lock held.\n\t *\n\t * It guarantees also that a pi_state which was queued right before\n\t * the state change under tsk->pi_lock by a concurrent waiter must\n\t * be observed in exit_pi_state_list().\n\t */\n\traw_spin_lock_irq(&tsk->pi_lock);\n\ttsk->futex_state = FUTEX_STATE_EXITING;\n\traw_spin_unlock_irq(&tsk->pi_lock);\n}",
        "static int pfkey_spddelete(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tint err;\n\tstruct sadb_address *sa;": "static int pfkey_spddelete(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tint err;\n\tstruct sadb_address *sa;\n\tstruct sadb_x_policy *pol;\n\tstruct xfrm_policy *xp;\n\tstruct xfrm_selector sel;\n\tstruct km_event c;\n\tstruct sadb_x_sec_ctx *sec_ctx;\n\tstruct xfrm_sec_ctx *pol_ctx = NULL;\n\n\tif (!present_and_same_family(ext_hdrs[SADB_EXT_ADDRESS_SRC-1],\n\t\t\t\t     ext_hdrs[SADB_EXT_ADDRESS_DST-1]) ||\n\t    !ext_hdrs[SADB_X_EXT_POLICY-1])\n\t\treturn -EINVAL;\n\n\tpol = ext_hdrs[SADB_X_EXT_POLICY-1];\n\tif (!pol->sadb_x_policy_dir || pol->sadb_x_policy_dir >= IPSEC_DIR_MAX)\n\t\treturn -EINVAL;\n\n\tmemset(&sel, 0, sizeof(sel));\n\n\tsa = ext_hdrs[SADB_EXT_ADDRESS_SRC-1];\n\tsel.family = pfkey_sadb_addr2xfrm_addr(sa, &sel.saddr);\n\tsel.prefixlen_s = sa->sadb_address_prefixlen;\n\tsel.proto = pfkey_proto_to_xfrm(sa->sadb_address_proto);\n\tsel.sport = ((struct sockaddr_in *)(sa+1))->sin_port;\n\tif (sel.sport)\n\t\tsel.sport_mask = htons(0xffff);\n\n\tsa = ext_hdrs[SADB_EXT_ADDRESS_DST-1];\n\tpfkey_sadb_addr2xfrm_addr(sa, &sel.daddr);\n\tsel.prefixlen_d = sa->sadb_address_prefixlen;\n\tsel.proto = pfkey_proto_to_xfrm(sa->sadb_address_proto);\n\tsel.dport = ((struct sockaddr_in *)(sa+1))->sin_port;\n\tif (sel.dport)\n\t\tsel.dport_mask = htons(0xffff);\n\n\tsec_ctx = ext_hdrs[SADB_X_EXT_SEC_CTX - 1];\n\tif (sec_ctx != NULL) {\n\t\tstruct xfrm_user_sec_ctx *uctx = pfkey_sadb2xfrm_user_sec_ctx(sec_ctx, GFP_KERNEL);\n\n\t\tif (!uctx)\n\t\t\treturn -ENOMEM;\n\n\t\terr = security_xfrm_policy_alloc(&pol_ctx, uctx, GFP_KERNEL);\n\t\tkfree(uctx);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\txp = xfrm_policy_bysel_ctx(net, &dummy_mark, 0, XFRM_POLICY_TYPE_MAIN,\n\t\t\t\t   pol->sadb_x_policy_dir - 1, &sel, pol_ctx,\n\t\t\t\t   1, &err);\n\tsecurity_xfrm_policy_free(pol_ctx);\n\tif (xp == NULL)\n\t\treturn -ENOENT;\n\n\txfrm_audit_policy_delete(xp, err ? 0 : 1, true);\n\n\tif (err)\n\t\tgoto out;\n\n\tc.seq = hdr->sadb_msg_seq;\n\tc.portid = hdr->sadb_msg_pid;\n\tc.data.byid = 0;\n\tc.event = XFRM_MSG_DELPOLICY;\n\tkm_policy_notify(xp, pol->sadb_x_policy_dir-1, &c);\n\nout:\n\txfrm_pol_put(xp);\n\treturn err;\n}",
        "static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)\n{\n\tu8 gear;\n\n\t/* Workaround for TMDS PLL problem": "static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)\n{\n\tu8 gear;\n\n\t/* Workaround for TMDS PLL problem\n\t * The TMDS PLL in AD9389b change gear when the chip is heated above a\n\t * certain temperature. The output is disabled when the PLL change gear\n\t * so the monitor has to lock on the signal again. A workaround for\n\t * this is to use the manual PLL gears. This is a solution from Analog\n\t * Devices that is not documented in the datasheets.\n\t * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear\n\t *\n\t * The pixel frequency ranges are based on readout of the gear the\n\t * automatic gearing selects for different pixel clocks\n\t * (read from 0x9e [3:1]).\n\t */\n\n\tif (pixelclock > 140000000)\n\t\tgear = 0xc0; /* 4th gear */\n\telse if (pixelclock > 117000000)\n\t\tgear = 0xb0; /* 3rd gear */\n\telse if (pixelclock > 87000000)\n\t\tgear = 0xa0; /* 2nd gear */\n\telse if (pixelclock > 60000000)\n\t\tgear = 0x90; /* 1st gear */\n\telse\n\t\tgear = 0x80; /* 0th gear */\n\n\tad9389b_wr_and_or(sd, 0x98, 0x0f, gear);\n}",
        "static int __init lart_flash_init (void)\n{\n   int result;\n   memset (&mtd,0,sizeof (mtd));\n   printk (\"MTD driver for LART. Written by Abraham vd Merwe <abraham@2d3d.co.za>\\n\");": "static int __init lart_flash_init (void)\n{\n   int result;\n   memset (&mtd,0,sizeof (mtd));\n   printk (\"MTD driver for LART. Written by Abraham vd Merwe <abraham@2d3d.co.za>\\n\");\n   printk (\"%s: Probing for 28F160x3 flash on LART...\\n\",module_name);\n   if (!flash_probe ())\n\t {\n\t\tprintk (KERN_WARNING \"%s: Found no LART compatible flash device\\n\",module_name);\n\t\treturn (-ENXIO);\n\t }\n   printk (\"%s: This looks like a LART board to me.\\n\",module_name);\n   mtd.name = module_name;\n   mtd.type = MTD_NORFLASH;\n   mtd.writesize = 1;\n   mtd.writebufsize = 4;\n   mtd.flags = MTD_CAP_NORFLASH;\n   mtd.size = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM + FLASH_BLOCKSIZE_MAIN * FLASH_NUMBLOCKS_16m_MAIN;\n   mtd.erasesize = FLASH_BLOCKSIZE_MAIN;\n   mtd.numeraseregions = ARRAY_SIZE(erase_regions);\n   mtd.eraseregions = erase_regions;\n   mtd._erase = flash_erase;\n   mtd._read = flash_read;\n   mtd._write = flash_write;\n   mtd.owner = THIS_MODULE;\n\n#ifdef LART_DEBUG\n   printk (KERN_DEBUG\n\t\t   \"mtd.name = %s\\n\"\n\t\t   \"mtd.size = 0x%.8x (%uM)\\n\"\n\t\t   \"mtd.erasesize = 0x%.8x (%uK)\\n\"\n\t\t   \"mtd.numeraseregions = %d\\n\",\n\t\t   mtd.name,\n\t\t   mtd.size,mtd.size / (1024*1024),\n\t\t   mtd.erasesize,mtd.erasesize / 1024,\n\t\t   mtd.numeraseregions);\n\n   if (mtd.numeraseregions)\n\t for (result = 0; result < mtd.numeraseregions; result++)\n\t   printk (KERN_DEBUG\n\t\t\t   \"\\n\\n\"\n\t\t\t   \"mtd.eraseregions[%d].offset = 0x%.8x\\n\"\n\t\t\t   \"mtd.eraseregions[%d].erasesize = 0x%.8x (%uK)\\n\"\n\t\t\t   \"mtd.eraseregions[%d].numblocks = %d\\n\",\n\t\t\t   result,mtd.eraseregions[result].offset,\n\t\t\t   result,mtd.eraseregions[result].erasesize,mtd.eraseregions[result].erasesize / 1024,\n\t\t\t   result,mtd.eraseregions[result].numblocks);\n\n   printk (\"\\npartitions = %d\\n\", ARRAY_SIZE(lart_partitions));\n\n   for (result = 0; result < ARRAY_SIZE(lart_partitions); result++)\n\t printk (KERN_DEBUG\n\t\t\t \"\\n\\n\"\n\t\t\t \"lart_partitions[%d].name = %s\\n\"\n\t\t\t \"lart_partitions[%d].offset = 0x%.8x\\n\"\n\t\t\t \"lart_partitions[%d].size = 0x%.8x (%uK)\\n\",\n\t\t\t result,lart_partitions[result].name,\n\t\t\t result,lart_partitions[result].offset,\n\t\t\t result,lart_partitions[result].size,lart_partitions[result].size / 1024);\n#endif\n\n   result = mtd_device_register(&mtd, lart_partitions,\n                                ARRAY_SIZE(lart_partitions));\n\n   return (result);\n}",
        "static int test6_rw_aligned_9434bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0x5F000) & ~(ADI_BLKSZ - 1);": "static int test6_rw_aligned_9434bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0x5F000) & ~(ADI_BLKSZ - 1);\n\tunsigned char version[TEST6_VERSION_SZ],\n\t\t      expected_version[TEST6_VERSION_SZ];\n\tloff_t offset;\n\toff_t oret;\n\tint ret, i;\n\n\toffset = paddr / ADI_BLKSZ;\n\tfor (i = 0; i < TEST6_VERSION_SZ; i++)\n\t\tversion[i] = expected_version[i] = random_version();\n\n\toret = seek_adi(fd, offset, SEEK_SET);\n\tif (oret != offset) {\n\t\tret = -1;\n\t\tTEST_STEP_FAILURE(ret);\n\t}\n\n\tret = write_adi(fd, version, sizeof(version));\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tmemset(version, 0, TEST6_VERSION_SZ);\n\n\toret = seek_adi(fd, offset, SEEK_SET);\n\tif (oret != offset) {\n\t\tret = -1;\n\t\tTEST_STEP_FAILURE(ret);\n\t}\n\n\tret = read_adi(fd, version, sizeof(version));\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tfor (i = 0; i < TEST6_VERSION_SZ; i++) {\n\t\tif (expected_version[i] != version[i]) {\n\t\t\tDEBUG_PRINT_L2(\n\t\t\t\t\"\\tExpected version %d but read version %d\\n\",\n\t\t\t\texpected_version[i], version[i]);\n\t\t\tTEST_STEP_FAILURE(-expected_version[i]);\n\t\t}\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static int max2175_core_init(struct max2175 *ctx, u32 refout_bits)\n{\n\tint ret;\n\n\t/* MAX2175 uses 36.864MHz clock for EU & 40.154MHz for NA region */": "static int max2175_core_init(struct max2175 *ctx, u32 refout_bits)\n{\n\tint ret;\n\n\t/* MAX2175 uses 36.864MHz clock for EU & 40.154MHz for NA region */\n\tif (ctx->xtal_freq == MAX2175_EU_XTAL_FREQ)\n\t\tmax2175_load_full_fm_eu_1p0(ctx);\n\telse\n\t\tmax2175_load_full_fm_na_1p0(ctx);\n\n\t/* The default settings assume master */\n\tif (!ctx->master)\n\t\tmax2175_write_bit(ctx, 30, 7, 1);\n\n\tmxm_dbg(ctx, \"refout_bits %u\\n\", refout_bits);\n\n\t/* Set REFOUT */\n\tmax2175_write_bits(ctx, 56, 7, 5, refout_bits);\n\n\t/* ADC Reset */\n\tmax2175_write_bit(ctx, 99, 1, 0);\n\tusleep_range(1000, 1500);\n\tmax2175_write_bit(ctx, 99, 1, 1);\n\n\t/* Load ADC preset values */\n\tmax2175_load_adc_presets(ctx);\n\n\t/* Initialize the power management state machine */\n\tret = max2175_init_power_manager(ctx);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Recalibrate ADC */\n\tret = max2175_recalibrate_adc(ctx);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Load ROM values to appropriate registers */\n\tmax2175_load_from_rom(ctx);\n\n\tif (ctx->xtal_freq == MAX2175_EU_XTAL_FREQ) {\n\t\t/* Load FIR coefficients into bank 0 */\n\t\tmax2175_set_filter_coeffs(ctx, MAX2175_CH_MSEL, 0,\n\t\t\t\t\t  ch_coeff_fmeu);\n\t\tmax2175_set_filter_coeffs(ctx, MAX2175_EQ_MSEL, 0,\n\t\t\t\t\t  eq_coeff_fmeu1_ra02_m6db);\n\t} else {\n\t\t/* Load FIR coefficients into bank 0 */\n\t\tmax2175_set_filter_coeffs(ctx, MAX2175_CH_MSEL, 0,\n\t\t\t\t\t  ch_coeff_fmna);\n\t\tmax2175_set_filter_coeffs(ctx, MAX2175_EQ_MSEL, 0,\n\t\t\t\t\t  eq_coeff_fmna1_ra02_m6db);\n\t}\n\tmxm_dbg(ctx, \"core initialized\\n\");\n\n\treturn 0;\n}",
        "static int ipc_flash_full_erase(struct iosm_devlink *ipc_devlink, u8 *mdm_rsp)\n{\n\tu32 erase_address = IOSM_ERASE_START_ADDR;\n\tstruct iosm_flash_msg_control cmd_msg;\n\tu32 erase_length = IOSM_ERASE_LEN;": "static int ipc_flash_full_erase(struct iosm_devlink *ipc_devlink, u8 *mdm_rsp)\n{\n\tu32 erase_address = IOSM_ERASE_START_ADDR;\n\tstruct iosm_flash_msg_control cmd_msg;\n\tu32 erase_length = IOSM_ERASE_LEN;\n\tint ret;\n\n\tdev_dbg(ipc_devlink->dev, \"Erase full nand flash\");\n\tcmd_msg.action = cpu_to_le32(FLASH_OOSC_ACTION_ERASE);\n\tcmd_msg.type = cpu_to_le32(FLASH_OOSC_TYPE_ALL_FLASH);\n\tcmd_msg.length = cpu_to_le32(erase_length);\n\tcmd_msg.arguments = cpu_to_le32(erase_address);\n\n\tret = ipc_flash_send_receive(ipc_devlink, FLASH_OOS_CONTROL,\n\t\t\t\t     (unsigned char *)&cmd_msg,\n\t\t\t\t     IOSM_MDM_SEND_16, mdm_rsp);\n\tif (ret)\n\t\tgoto ipc_flash_erase_err;\n\n\tipc_devlink->param.erase_full_flash_done = IOSM_SET_FLAG;\n\tret = ipc_flash_erase_check(ipc_devlink, mdm_rsp);\n\nipc_flash_erase_err:\n\treturn ret;\n}",
        "static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)\n{\n\tu16 block_extra_bytes_size;\n\tu8 data;\n": "static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)\n{\n\tu16 block_extra_bytes_size;\n\tu8 data;\n\n\t/* added bytes to the packet: */\n\tblock_extra_bytes_size = bus->read_block_use + bus->PEC_use;\n\n\t/*\n\t * Perform master read, distinguishing between last byte and the rest of\n\t * the bytes. The last byte should be read when the clock is stopped\n\t */\n\tif (bus->rd_ind == 0) { /* first byte handling: */\n\t\tif (bus->read_block_use) {\n\t\t\t/* first byte in block protocol is the size: */\n\t\t\tdata = npcm_i2c_rd_byte(bus);\n\t\t\tdata = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);\n\t\t\tbus->rd_size = data + block_extra_bytes_size;\n\t\t\tbus->rd_buf[bus->rd_ind++] = data;\n\n\t\t\t/* clear RX FIFO interrupt status: */\n\t\t\tif (bus->fifo_use) {\n\t\t\t\tdata = ioread8(bus->reg + NPCM_I2CFIF_CTS);\n\t\t\t\tdata = data | NPCM_I2CFIF_CTS_RXF_TXE;\n\t\t\t\tiowrite8(data, bus->reg + NPCM_I2CFIF_CTS);\n\t\t\t}\n\n\t\t\tnpcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);\n\t\t\tnpcm_i2c_stall_after_start(bus, false);\n\t\t} else {\n\t\t\tnpcm_i2c_clear_tx_fifo(bus);\n\t\t\tnpcm_i2c_master_fifo_read(bus);\n\t\t}\n\t} else {\n\t\tif (bus->rd_size == block_extra_bytes_size &&\n\t\t    bus->read_block_use) {\n\t\t\tbus->state = I2C_STOP_PENDING;\n\t\t\tbus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;\n\t\t\tbus->cmd_err = -EIO;\n\t\t\tnpcm_i2c_eob_int(bus, true);\n\t\t\tnpcm_i2c_master_stop(bus);\n\t\t\tnpcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));\n\t\t} else {\n\t\t\tnpcm_i2c_master_fifo_read(bus);\n\t\t}\n\t}\n}",
        "static void mlx5_cleanup_once(struct mlx5_core_dev *dev)\n{\n\tmlx5_rsc_dump_destroy(dev);\n\tmlx5_hv_vhca_destroy(dev->hv_vhca);\n\tmlx5_fw_tracer_destroy(dev->tracer);": "static void mlx5_cleanup_once(struct mlx5_core_dev *dev)\n{\n\tmlx5_rsc_dump_destroy(dev);\n\tmlx5_hv_vhca_destroy(dev->hv_vhca);\n\tmlx5_fw_tracer_destroy(dev->tracer);\n\tmlx5_dm_cleanup(dev);\n\tmlx5_fs_core_free(dev);\n\tmlx5_sf_table_cleanup(dev);\n\tmlx5_sf_hw_table_cleanup(dev);\n\tmlx5_vhca_event_cleanup(dev);\n\tmlx5_fpga_cleanup(dev);\n\tmlx5_eswitch_cleanup(dev->priv.eswitch);\n\tmlx5_sriov_cleanup(dev);\n\tmlx5_mpfs_cleanup(dev);\n\tmlx5_cleanup_rl_table(dev);\n\tmlx5_geneve_destroy(dev->geneve);\n\tmlx5_vxlan_destroy(dev->vxlan);\n\tmlx5_cleanup_clock(dev);\n\tmlx5_cleanup_reserved_gids(dev);\n\tmlx5_cq_debugfs_cleanup(dev);\n\tmlx5_fw_reset_cleanup(dev);\n\tmlx5_events_cleanup(dev);\n\tmlx5_eq_table_cleanup(dev);\n\tmlx5_irq_table_cleanup(dev);\n\tmlx5_devcom_unregister_device(dev->priv.devcom);\n}",
        "static void __tcp_ack_snd_check(struct sock *sk, int ofo_possible)\n{\n\tstruct tcp_sock *tp = tcp_sk(sk);\n\tunsigned long rtt, delay;\n": "static void __tcp_ack_snd_check(struct sock *sk, int ofo_possible)\n{\n\tstruct tcp_sock *tp = tcp_sk(sk);\n\tunsigned long rtt, delay;\n\n\t    /* More than one full frame received... */\n\tif (((tp->rcv_nxt - tp->rcv_wup) > inet_csk(sk)->icsk_ack.rcv_mss &&\n\t     /* ... and right edge of window advances far enough.\n\t      * (tcp_recvmsg() will send ACK otherwise).\n\t      * If application uses SO_RCVLOWAT, we want send ack now if\n\t      * we have not received enough bytes to satisfy the condition.\n\t      */\n\t    (tp->rcv_nxt - tp->copied_seq < sk->sk_rcvlowat ||\n\t     __tcp_select_window(sk) >= tp->rcv_wnd)) ||\n\t    /* We ACK each frame or... */\n\t    tcp_in_quickack_mode(sk) ||\n\t    /* Protocol state mandates a one-time immediate ACK */\n\t    inet_csk(sk)->icsk_ack.pending & ICSK_ACK_NOW) {\nsend_now:\n\t\ttcp_send_ack(sk);\n\t\treturn;\n\t}\n\n\tif (!ofo_possible || RB_EMPTY_ROOT(&tp->out_of_order_queue)) {\n\t\ttcp_send_delayed_ack(sk);\n\t\treturn;\n\t}\n\n\tif (!tcp_is_sack(tp) ||\n\t    tp->compressed_ack >= sock_net(sk)->ipv4.sysctl_tcp_comp_sack_nr)\n\t\tgoto send_now;\n\n\tif (tp->compressed_ack_rcv_nxt != tp->rcv_nxt) {\n\t\ttp->compressed_ack_rcv_nxt = tp->rcv_nxt;\n\t\ttp->dup_ack_counter = 0;\n\t}\n\tif (tp->dup_ack_counter < TCP_FASTRETRANS_THRESH) {\n\t\ttp->dup_ack_counter++;\n\t\tgoto send_now;\n\t}\n\ttp->compressed_ack++;\n\tif (hrtimer_is_queued(&tp->compressed_ack_timer))\n\t\treturn;\n\n\t/* compress ack timer : 5 % of rtt, but no more than tcp_comp_sack_delay_ns */\n\n\trtt = tp->rcv_rtt_est.rtt_us;\n\tif (tp->srtt_us && tp->srtt_us < rtt)\n\t\trtt = tp->srtt_us;\n\n\tdelay = min_t(unsigned long, sock_net(sk)->ipv4.sysctl_tcp_comp_sack_delay_ns,\n\t\t      rtt * (NSEC_PER_USEC >> 3)/20);\n\tsock_hold(sk);\n\thrtimer_start_range_ns(&tp->compressed_ack_timer, ns_to_ktime(delay),\n\t\t\t       sock_net(sk)->ipv4.sysctl_tcp_comp_sack_slack_ns,\n\t\t\t       HRTIMER_MODE_REL_PINNED_SOFT);\n}",
        "static int jit_subprogs(struct bpf_verifier_env *env)\n{\n\tstruct bpf_prog *prog = env->prog, **func, *tmp;\n\tint i, j, subprog_start, subprog_end = 0, len, subprog;\n\tstruct bpf_map *map_ptr;": "static int jit_subprogs(struct bpf_verifier_env *env)\n{\n\tstruct bpf_prog *prog = env->prog, **func, *tmp;\n\tint i, j, subprog_start, subprog_end = 0, len, subprog;\n\tstruct bpf_map *map_ptr;\n\tstruct bpf_insn *insn;\n\tvoid *old_bpf_func;\n\tint err, num_exentries;\n\n\tif (env->subprog_cnt <= 1)\n\t\treturn 0;\n\n\tfor (i = 0, insn = prog->insnsi; i < prog->len; i++, insn++) {\n\t\tif (!bpf_pseudo_func(insn) && !bpf_pseudo_call(insn))\n\t\t\tcontinue;\n\n\t\t/* Upon error here we cannot fall back to interpreter but\n\t\t * need a hard reject of the program. Thus -EFAULT is\n\t\t * propagated in any case.\n\t\t */\n\t\tsubprog = find_subprog(env, i + insn->imm + 1);\n\t\tif (subprog < 0) {\n\t\t\tWARN_ONCE(1, \"verifier bug. No program starts at insn %d\\n\",\n\t\t\t\t  i + insn->imm + 1);\n\t\t\treturn -EFAULT;\n\t\t}\n\t\t/* temporarily remember subprog id inside insn instead of\n\t\t * aux_data, since next loop will split up all insns into funcs\n\t\t */\n\t\tinsn->off = subprog;\n\t\t/* remember original imm in case JIT fails and fallback\n\t\t * to interpreter will be needed\n\t\t */\n\t\tenv->insn_aux_data[i].call_imm = insn->imm;\n\t\t/* point imm to __bpf_call_base+1 from JITs point of view */\n\t\tinsn->imm = 1;\n\t\tif (bpf_pseudo_func(insn))\n\t\t\t/* jit (e.g. x86_64) may emit fewer instructions\n\t\t\t * if it learns a u32 imm is the same as a u64 imm.\n\t\t\t * Force a non zero here.\n\t\t\t */\n\t\t\tinsn[1].imm = 1;\n\t}\n\n\terr = bpf_prog_alloc_jited_linfo(prog);\n\tif (err)\n\t\tgoto out_undo_insn;\n\n\terr = -ENOMEM;\n\tfunc = kcalloc(env->subprog_cnt, sizeof(prog), GFP_KERNEL);\n\tif (!func)\n\t\tgoto out_undo_insn;\n\n\tfor (i = 0; i < env->subprog_cnt; i++) {\n\t\tsubprog_start = subprog_end;\n\t\tsubprog_end = env->subprog_info[i + 1].start;\n\n\t\tlen = subprog_end - subprog_start;\n\t\t/* bpf_prog_run() doesn't call subprogs directly,\n\t\t * hence main prog stats include the runtime of subprogs.\n\t\t * subprogs don't have IDs and not reachable via prog_get_next_id\n\t\t * func[i]->stats will never be accessed and stays NULL\n\t\t */\n\t\tfunc[i] = bpf_prog_alloc_no_stats(bpf_prog_size(len), GFP_USER);\n\t\tif (!func[i])\n\t\t\tgoto out_free;\n\t\tmemcpy(func[i]->insnsi, &prog->insnsi[subprog_start],\n\t\t       len * sizeof(struct bpf_insn));\n\t\tfunc[i]->type = prog->type;\n\t\tfunc[i]->len = len;\n\t\tif (bpf_prog_calc_tag(func[i]))\n\t\t\tgoto out_free;\n\t\tfunc[i]->is_func = 1;\n\t\tfunc[i]->aux->func_idx = i;\n\t\t/* Below members will be freed only at prog->aux */\n\t\tfunc[i]->aux->btf = prog->aux->btf;\n\t\tfunc[i]->aux->func_info = prog->aux->func_info;\n\t\tfunc[i]->aux->poke_tab = prog->aux->poke_tab;\n\t\tfunc[i]->aux->size_poke_tab = prog->aux->size_poke_tab;\n\n\t\tfor (j = 0; j < prog->aux->size_poke_tab; j++) {\n\t\t\tstruct bpf_jit_poke_descriptor *poke;\n\n\t\t\tpoke = &prog->aux->poke_tab[j];\n\t\t\tif (poke->insn_idx < subprog_end &&\n\t\t\t    poke->insn_idx >= subprog_start)\n\t\t\t\tpoke->aux = func[i]->aux;\n\t\t}\n\n\t\t/* Use bpf_prog_F_tag to indicate functions in stack traces.\n\t\t * Long term would need debug info to populate names\n\t\t */\n\t\tfunc[i]->aux->name[0] = 'F';\n\t\tfunc[i]->aux->stack_depth = env->subprog_info[i].stack_depth;\n\t\tfunc[i]->jit_requested = 1;\n\t\tfunc[i]->blinding_requested = prog->blinding_requested;\n\t\tfunc[i]->aux->kfunc_tab = prog->aux->kfunc_tab;\n\t\tfunc[i]->aux->kfunc_btf_tab = prog->aux->kfunc_btf_tab;\n\t\tfunc[i]->aux->linfo = prog->aux->linfo;\n\t\tfunc[i]->aux->nr_linfo = prog->aux->nr_linfo;\n\t\tfunc[i]->aux->jited_linfo = prog->aux->jited_linfo;\n\t\tfunc[i]->aux->linfo_idx = env->subprog_info[i].linfo_idx;\n\t\tnum_exentries = 0;\n\t\tinsn = func[i]->insnsi;\n\t\tfor (j = 0; j < func[i]->len; j++, insn++) {\n\t\t\tif (BPF_CLASS(insn->code) == BPF_LDX &&\n\t\t\t    BPF_MODE(insn->code) == BPF_PROBE_MEM)\n\t\t\t\tnum_exentries++;\n\t\t}\n\t\tfunc[i]->aux->num_exentries = num_exentries;\n\t\tfunc[i]->aux->tail_call_reachable = env->subprog_info[i].tail_call_reachable;\n\t\tfunc[i] = bpf_int_jit_compile(func[i]);\n\t\tif (!func[i]->jited) {\n\t\t\terr = -ENOTSUPP;\n\t\t\tgoto out_free;\n\t\t}\n\t\tcond_resched();\n\t}\n\n\t/* at this point all bpf functions were successfully JITed\n\t * now populate all bpf_calls with correct addresses and\n\t * run last pass of JIT\n\t */\n\tfor (i = 0; i < env->subprog_cnt; i++) {\n\t\tinsn = func[i]->insnsi;\n\t\tfor (j = 0; j < func[i]->len; j++, insn++) {\n\t\t\tif (bpf_pseudo_func(insn)) {\n\t\t\t\tsubprog = insn->off;\n\t\t\t\tinsn[0].imm = (u32)(long)func[subprog]->bpf_func;\n\t\t\t\tinsn[1].imm = ((u64)(long)func[subprog]->bpf_func) >> 32;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (!bpf_pseudo_call(insn))\n\t\t\t\tcontinue;\n\t\t\tsubprog = insn->off;\n\t\t\tinsn->imm = BPF_CALL_IMM(func[subprog]->bpf_func);\n\t\t}\n\n\t\t/* we use the aux data to keep a list of the start addresses\n\t\t * of the JITed images for each function in the program\n\t\t *\n\t\t * for some architectures, such as powerpc64, the imm field\n\t\t * might not be large enough to hold the offset of the start\n\t\t * address of the callee's JITed image from __bpf_call_base\n\t\t *\n\t\t * in such cases, we can lookup the start address of a callee\n\t\t * by using its subprog id, available from the off field of\n\t\t * the call instruction, as an index for this list\n\t\t */\n\t\tfunc[i]->aux->func = func;\n\t\tfunc[i]->aux->func_cnt = env->subprog_cnt;\n\t}\n\tfor (i = 0; i < env->subprog_cnt; i++) {\n\t\told_bpf_func = func[i]->bpf_func;\n\t\ttmp = bpf_int_jit_compile(func[i]);\n\t\tif (tmp != func[i] || func[i]->bpf_func != old_bpf_func) {\n\t\t\tverbose(env, \"JIT doesn't support bpf-to-bpf calls\\n\");\n\t\t\terr = -ENOTSUPP;\n\t\t\tgoto out_free;\n\t\t}\n\t\tcond_resched();\n\t}\n\n\t/* finally lock prog and jit images for all functions and\n\t * populate kallsysm\n\t */\n\tfor (i = 0; i < env->subprog_cnt; i++) {\n\t\tbpf_prog_lock_ro(func[i]);\n\t\tbpf_prog_kallsyms_add(func[i]);\n\t}\n\n\t/* Last step: make now unused interpreter insns from main\n\t * prog consistent for later dump requests, so they can\n\t * later look the same as if they were interpreted only.\n\t */\n\tfor (i = 0, insn = prog->insnsi; i < prog->len; i++, insn++) {\n\t\tif (bpf_pseudo_func(insn)) {\n\t\t\tinsn[0].imm = env->insn_aux_data[i].call_imm;\n\t\t\tinsn[1].imm = insn->off;\n\t\t\tinsn->off = 0;\n\t\t\tcontinue;\n\t\t}\n\t\tif (!bpf_pseudo_call(insn))\n\t\t\tcontinue;\n\t\tinsn->off = env->insn_aux_data[i].call_imm;\n\t\tsubprog = find_subprog(env, i + insn->off + 1);\n\t\tinsn->imm = subprog;\n\t}\n\n\tprog->jited = 1;\n\tprog->bpf_func = func[0]->bpf_func;\n\tprog->jited_len = func[0]->jited_len;\n\tprog->aux->func = func;\n\tprog->aux->func_cnt = env->subprog_cnt;\n\tbpf_prog_jit_attempt_done(prog);\n\treturn 0;\nout_free:\n\t/* We failed JIT'ing, so at this point we need to unregister poke\n\t * descriptors from subprogs, so that kernel is not attempting to\n\t * patch it anymore as we're freeing the subprog JIT memory.\n\t */\n\tfor (i = 0; i < prog->aux->size_poke_tab; i++) {\n\t\tmap_ptr = prog->aux->poke_tab[i].tail_call.map;\n\t\tmap_ptr->ops->map_poke_untrack(map_ptr, prog->aux);\n\t}\n\t/* At this point we're guaranteed that poke descriptors are not\n\t * live anymore. We can just unlink its descriptor table as it's\n\t * released with the main prog.\n\t */\n\tfor (i = 0; i < env->subprog_cnt; i++) {\n\t\tif (!func[i])\n\t\t\tcontinue;\n\t\tfunc[i]->aux->poke_tab = NULL;\n\t\tbpf_jit_free(func[i]);\n\t}\n\tkfree(func);\nout_undo_insn:\n\t/* cleanup main prog to be interpreted */\n\tprog->jit_requested = 0;\n\tprog->blinding_requested = 0;\n\tfor (i = 0, insn = prog->insnsi; i < prog->len; i++, insn++) {\n\t\tif (!bpf_pseudo_call(insn))\n\t\t\tcontinue;\n\t\tinsn->off = 0;\n\t\tinsn->imm = env->insn_aux_data[i].call_imm;\n\t}\n\tbpf_prog_jit_attempt_done(prog);\n\treturn err;\n}",
        "static bool cond_snapshot_update(struct trace_array *tr, void *cond_data)\n{\n\t/* called with tr->max_lock held */\n\tstruct track_data *track_data = tr->cond_snapshot->cond_data;\n\tstruct hist_elt_data *elt_data, *track_elt_data;": "static bool cond_snapshot_update(struct trace_array *tr, void *cond_data)\n{\n\t/* called with tr->max_lock held */\n\tstruct track_data *track_data = tr->cond_snapshot->cond_data;\n\tstruct hist_elt_data *elt_data, *track_elt_data;\n\tstruct snapshot_context *context = cond_data;\n\tstruct action_data *action;\n\tu64 track_val;\n\n\tif (!track_data)\n\t\treturn false;\n\n\taction = track_data->action_data;\n\n\ttrack_val = get_track_val(track_data->hist_data, context->elt,\n\t\t\t\t  track_data->action_data);\n\n\tif (!action->track_data.check_val(track_data->track_val, track_val))\n\t\treturn false;\n\n\ttrack_data->track_val = track_val;\n\tmemcpy(track_data->key, context->key, track_data->key_len);\n\n\telt_data = context->elt->private_data;\n\ttrack_elt_data = track_data->elt.private_data;\n\tif (elt_data->comm)\n\t\tstrncpy(track_elt_data->comm, elt_data->comm, TASK_COMM_LEN);\n\n\ttrack_data->updated = true;\n\n\treturn true;\n}",
        "static void rt711_sdca_vd1_io_init(struct rt711_sdca_priv *rt711)\n{\n\trt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,\n\t\tRT711_HDA_LEGACY_UNSOLICITED_CTL, 0x0300, 0x0000);\n": "static void rt711_sdca_vd1_io_init(struct rt711_sdca_priv *rt711)\n{\n\trt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,\n\t\tRT711_HDA_LEGACY_UNSOLICITED_CTL, 0x0300, 0x0000);\n\n\trt711_sdca_index_write(rt711, RT711_VENDOR_REG,\n\t\tRT711_COMBO_JACK_AUTO_CTL3, 0xa43e);\n\n\tregmap_write(rt711->regmap, 0x2f5a, 0x05);\n\n\trt711_sdca_index_write(rt711, RT711_VENDOR_REG,\n\t\tRT711_JD_CTRL6, 0x0500);\n\n\trt711_sdca_index_write(rt711, RT711_VENDOR_REG,\n\t\tRT711_DMIC_CTL1, 0x6173);\n\n\trt711_sdca_index_write(rt711, RT711_VENDOR_HDA_CTL,\n\t\tRT711_HDA_LEGACY_CONFIG_CTL, 0x0000);\n\n\trt711_sdca_index_write(rt711, RT711_VENDOR_VAD,\n\t\tRT711_VAD_SRAM_CTL1, 0x0050);\n}",
        "static int handle_gso_encap(struct sk_buff *skb, bool ipv4, int encap_len)\n{\n\tint next_hdr_offset;\n\tvoid *next_hdr;\n\t__u8 protocol;": "static int handle_gso_encap(struct sk_buff *skb, bool ipv4, int encap_len)\n{\n\tint next_hdr_offset;\n\tvoid *next_hdr;\n\t__u8 protocol;\n\n\t/* SCTP and UDP_L4 gso need more nuanced handling than what\n\t * handle_gso_type() does above: skb_decrease_gso_size() is not enough.\n\t * So at the moment only TCP GSO packets are let through.\n\t */\n\tif (!(skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)))\n\t\treturn -ENOTSUPP;\n\n\tif (ipv4) {\n\t\tprotocol = ip_hdr(skb)->protocol;\n\t\tnext_hdr_offset = sizeof(struct iphdr);\n\t\tnext_hdr = skb_network_header(skb) + next_hdr_offset;\n\t} else {\n\t\tprotocol = ipv6_hdr(skb)->nexthdr;\n\t\tnext_hdr_offset = sizeof(struct ipv6hdr);\n\t\tnext_hdr = skb_network_header(skb) + next_hdr_offset;\n\t}\n\n\tswitch (protocol) {\n\tcase IPPROTO_GRE:\n\t\tnext_hdr_offset += sizeof(struct gre_base_hdr);\n\t\tif (next_hdr_offset > encap_len)\n\t\t\treturn -EINVAL;\n\n\t\tif (((struct gre_base_hdr *)next_hdr)->flags & GRE_CSUM)\n\t\t\treturn handle_gso_type(skb, SKB_GSO_GRE_CSUM,\n\t\t\t\t\t       encap_len);\n\t\treturn handle_gso_type(skb, SKB_GSO_GRE, encap_len);\n\n\tcase IPPROTO_UDP:\n\t\tnext_hdr_offset += sizeof(struct udphdr);\n\t\tif (next_hdr_offset > encap_len)\n\t\t\treturn -EINVAL;\n\n\t\tif (((struct udphdr *)next_hdr)->check)\n\t\t\treturn handle_gso_type(skb, SKB_GSO_UDP_TUNNEL_CSUM,\n\t\t\t\t\t       encap_len);\n\t\treturn handle_gso_type(skb, SKB_GSO_UDP_TUNNEL, encap_len);\n\n\tcase IPPROTO_IP:\n\tcase IPPROTO_IPV6:\n\t\tif (ipv4)\n\t\t\treturn handle_gso_type(skb, SKB_GSO_IPXIP4, encap_len);\n\t\telse\n\t\t\treturn handle_gso_type(skb, SKB_GSO_IPXIP6, encap_len);\n\n\tdefault:\n\t\treturn -EPROTONOSUPPORT;\n\t}\n}",
        "static void nfdicf_decompose(void)\n{\n\tunsigned int unichar;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */\n\tunsigned int *um;": "static void nfdicf_decompose(void)\n{\n\tunsigned int unichar;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */\n\tunsigned int *um;\n\tunsigned int *dc;\n\tint count;\n\tint i;\n\tint j;\n\tint ret;\n\n\tif (verbose > 0)\n\t\tprintf(\"Decomposing nfdicf\\n\");\n\tcount = 0;\n\tfor (unichar = 0; unichar != 0x110000; unichar++) {\n\t\tif (!unicode_data[unichar].utf32nfdicf)\n\t\t\tcontinue;\n\t\tfor (;;) {\n\t\t\tret = 1;\n\t\t\ti = 0;\n\t\t\tum = unicode_data[unichar].utf32nfdicf;\n\t\t\twhile (*um) {\n\t\t\t\tdc = unicode_data[*um].utf32nfdicf;\n\t\t\t\tif (dc) {\n\t\t\t\t\tfor (j = 0; dc[j]; j++)\n\t\t\t\t\t\tmapping[i++] = dc[j];\n\t\t\t\t\tret = 0;\n\t\t\t\t} else {\n\t\t\t\t\tmapping[i++] = *um;\n\t\t\t\t}\n\t\t\t\tum++;\n\t\t\t}\n\t\t\tmapping[i++] = 0;\n\t\t\tif (ret)\n\t\t\t\tbreak;\n\t\t\tfree(unicode_data[unichar].utf32nfdicf);\n\t\t\tum = malloc(i * sizeof(unsigned int));\n\t\t\tmemcpy(um, mapping, i * sizeof(unsigned int));\n\t\t\tunicode_data[unichar].utf32nfdicf = um;\n\t\t}\n\t\tif (verbose > 1)\n\t\t\tprint_utf32nfdicf(unichar);\n\t\tcount++;\n\t}\n\tif (verbose > 0)\n\t\tprintf(\"Processed %d entries\\n\", count);\n}",
        "static int es581_4_set_bittiming(struct es58x_priv *priv)\n{\n\tstruct es581_4_tx_conf_msg tx_conf_msg = { 0 };\n\tstruct can_bittiming *bt = &priv->can.bittiming;\n": "static int es581_4_set_bittiming(struct es58x_priv *priv)\n{\n\tstruct es581_4_tx_conf_msg tx_conf_msg = { 0 };\n\tstruct can_bittiming *bt = &priv->can.bittiming;\n\n\ttx_conf_msg.bitrate = cpu_to_le32(bt->bitrate);\n\t/* bt->sample_point is in tenth of percent. Convert it to percent. */\n\ttx_conf_msg.sample_point = cpu_to_le32(bt->sample_point / 10U);\n\ttx_conf_msg.samples_per_bit = cpu_to_le32(ES58X_SAMPLES_PER_BIT_ONE);\n\ttx_conf_msg.bit_time = cpu_to_le32(can_bit_time(bt));\n\ttx_conf_msg.sjw = cpu_to_le32(bt->sjw);\n\ttx_conf_msg.sync_edge = cpu_to_le32(ES58X_SYNC_EDGE_SINGLE);\n\ttx_conf_msg.physical_layer =\n\t    cpu_to_le32(ES58X_PHYSICAL_LAYER_HIGH_SPEED);\n\ttx_conf_msg.echo_mode = cpu_to_le32(ES58X_ECHO_ON);\n\ttx_conf_msg.channel_no = priv->channel_idx + ES581_4_CHANNEL_IDX_OFFSET;\n\n\treturn es58x_send_msg(priv->es58x_dev, ES581_4_CAN_COMMAND_TYPE,\n\t\t\t      ES581_4_CMD_ID_SET_BITTIMING, &tx_conf_msg,\n\t\t\t      sizeof(tx_conf_msg), priv->channel_idx);\n}",
        "static void debug_string_to_mask(char *debug_string, void *mask, int type)\n{\n\tchar *unchecked_keyword;\n\tint i;\n\tchar *strsep_fodder = kstrdup(debug_string, GFP_KERNEL);": "static void debug_string_to_mask(char *debug_string, void *mask, int type)\n{\n\tchar *unchecked_keyword;\n\tint i;\n\tchar *strsep_fodder = kstrdup(debug_string, GFP_KERNEL);\n\tchar *original_pointer;\n\tint element_count = 0;\n\tstruct client_debug_mask *c_mask = NULL;\n\t__u64 *k_mask = NULL;\n\n\tgossip_debug(GOSSIP_UTILS_DEBUG, \"%s: start\\n\", __func__);\n\n\tif (type) {\n\t\tc_mask = (struct client_debug_mask *)mask;\n\t\telement_count = cdm_element_count;\n\t} else {\n\t\tk_mask = (__u64 *)mask;\n\t\t*k_mask = 0;\n\t\telement_count = num_kmod_keyword_mask_map;\n\t}\n\n\toriginal_pointer = strsep_fodder;\n\twhile ((unchecked_keyword = strsep(&strsep_fodder, \",\")))\n\t\tif (strlen(unchecked_keyword)) {\n\t\t\tfor (i = 0; i < element_count; i++)\n\t\t\t\tif (type)\n\t\t\t\t\tdo_c_mask(i,\n\t\t\t\t\t\t  unchecked_keyword,\n\t\t\t\t\t\t  &c_mask);\n\t\t\t\telse\n\t\t\t\t\tdo_k_mask(i,\n\t\t\t\t\t\t  unchecked_keyword,\n\t\t\t\t\t\t  &k_mask);\n\t\t}\n\n\tkfree(original_pointer);\n}",
        "static int rx_queue_add_kobject(struct net_device *dev, int index)\n{\n\tstruct netdev_rx_queue *queue = dev->_rx + index;\n\tstruct kobject *kobj = &queue->kobj;\n\tint error = 0;": "static int rx_queue_add_kobject(struct net_device *dev, int index)\n{\n\tstruct netdev_rx_queue *queue = dev->_rx + index;\n\tstruct kobject *kobj = &queue->kobj;\n\tint error = 0;\n\n\t/* Kobject_put later will trigger rx_queue_release call which\n\t * decreases dev refcount: Take that reference here\n\t */\n\tdev_hold_track(queue->dev, &queue->dev_tracker, GFP_KERNEL);\n\n\tkobj->kset = dev->queues_kset;\n\terror = kobject_init_and_add(kobj, &rx_queue_ktype, NULL,\n\t\t\t\t     \"rx-%u\", index);\n\tif (error)\n\t\tgoto err;\n\n\tif (dev->sysfs_rx_queue_group) {\n\t\terror = sysfs_create_group(kobj, dev->sysfs_rx_queue_group);\n\t\tif (error)\n\t\t\tgoto err;\n\t}\n\n\tkobject_uevent(kobj, KOBJ_ADD);\n\n\treturn error;\n\nerr:\n\tkobject_put(kobj);\n\treturn error;\n}",
        "static inline u64 timekeeping_get_delta(const struct tk_read_base *tkr)\n{\n\tstruct timekeeper *tk = &tk_core.timekeeper;\n\tu64 now, last, mask, max, delta;\n\tunsigned int seq;": "static inline u64 timekeeping_get_delta(const struct tk_read_base *tkr)\n{\n\tstruct timekeeper *tk = &tk_core.timekeeper;\n\tu64 now, last, mask, max, delta;\n\tunsigned int seq;\n\n\t/*\n\t * Since we're called holding a seqcount, the data may shift\n\t * under us while we're doing the calculation. This can cause\n\t * false positives, since we'd note a problem but throw the\n\t * results away. So nest another seqcount here to atomically\n\t * grab the points we are checking with.\n\t */\n\tdo {\n\t\tseq = read_seqcount_begin(&tk_core.seq);\n\t\tnow = tk_clock_read(tkr);\n\t\tlast = tkr->cycle_last;\n\t\tmask = tkr->mask;\n\t\tmax = tkr->clock->max_cycles;\n\t} while (read_seqcount_retry(&tk_core.seq, seq));\n\n\tdelta = clocksource_delta(now, last, mask);\n\n\t/*\n\t * Try to catch underflows by checking if we are seeing small\n\t * mask-relative negative values.\n\t */\n\tif (unlikely((~delta & mask) < (mask >> 3))) {\n\t\ttk->underflow_seen = 1;\n\t\tdelta = 0;\n\t}\n\n\t/* Cap delta value to the max_cycles values to avoid mult overflows */\n\tif (unlikely(delta > max)) {\n\t\ttk->overflow_seen = 1;\n\t\tdelta = tkr->clock->max_cycles;\n\t}\n\n\treturn delta;\n}",
        "static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc)\n{\n\tu32 val;\n\n\t/* restore port speed to gen2 */": "static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc)\n{\n\tu32 val;\n\n\t/* restore port speed to gen2 */\n\tval = xudc_readl(xudc, SSPX_CORE_CNT56);\n\tval &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK);\n\tval |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438);\n\txudc_writel(xudc, val, SSPX_CORE_CNT56);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT57);\n\tval &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK);\n\tval |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528);\n\txudc_writel(xudc, val, SSPX_CORE_CNT57);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT65);\n\tval &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK);\n\tval |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10);\n\txudc_writel(xudc, val, SSPX_CORE_CNT66);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT66);\n\tval &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK);\n\tval |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348);\n\txudc_writel(xudc, val, SSPX_CORE_CNT66);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT67);\n\tval &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK);\n\tval |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0);\n\txudc_writel(xudc, val, SSPX_CORE_CNT67);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT72);\n\tval &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK);\n\tval |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21);\n\txudc_writel(xudc, val, SSPX_CORE_CNT72);\n}",
        "static void dtTruncateEntry(dtpage_t * p, int ti, struct dt_lock ** dtlock)\n{\n\tint tsi;\t\t/* truncate entry slot index */\n\ts8 *stbl;\n\tstruct dtslot *t;": "static void dtTruncateEntry(dtpage_t * p, int ti, struct dt_lock ** dtlock)\n{\n\tint tsi;\t\t/* truncate entry slot index */\n\ts8 *stbl;\n\tstruct dtslot *t;\n\tint si, freecnt;\n\tstruct dt_lock *dtlck = *dtlock;\n\tstruct lv *lv;\n\tint fsi, xsi, n;\n\n\t/* get free entry slot index */\n\tstbl = DT_GETSTBL(p);\n\ttsi = stbl[ti];\n\n\t/* open new linelock */\n\tif (dtlck->index >= dtlck->maxcnt)\n\t\tdtlck = (struct dt_lock *) txLinelock(dtlck);\n\tlv = & dtlck->lv[dtlck->index];\n\n\tlv->offset = tsi;\n\n\t/* get the head/only segment */\n\tt = &p->slot[tsi];\n\tASSERT(p->header.flag & BT_INTERNAL);\n\t((struct idtentry *) t)->namlen = 0;\n\tsi = ((struct idtentry *) t)->next;\n\t((struct idtentry *) t)->next = -1;\n\n\tn = 1;\n\tfreecnt = 0;\n\tfsi = si;\n\txsi = tsi;\n\n\t/* find the last/only segment */\n\twhile (si >= 0) {\n\t\t/* is next slot contiguous ? */\n\t\tif (si != xsi + 1) {\n\t\t\t/* close current linelock */\n\t\t\tlv->length = n;\n\t\t\tdtlck->index++;\n\n\t\t\t/* open new linelock */\n\t\t\tif (dtlck->index < dtlck->maxcnt)\n\t\t\t\tlv++;\n\t\t\telse {\n\t\t\t\tdtlck = (struct dt_lock *) txLinelock(dtlck);\n\t\t\t\tlv = & dtlck->lv[0];\n\t\t\t}\n\n\t\t\tlv->offset = si;\n\t\t\tn = 0;\n\t\t}\n\n\t\tn++;\n\t\txsi = si;\n\t\tfreecnt++;\n\n\t\tt = &p->slot[si];\n\t\tt->cnt = 1;\n\t\tsi = t->next;\n\t}\n\n\t/* close current linelock */\n\tlv->length = n;\n\tdtlck->index++;\n\n\t*dtlock = dtlck;\n\n\t/* update freelist */\n\tif (freecnt == 0)\n\t\treturn;\n\tt->next = p->header.freelist;\n\tp->header.freelist = fsi;\n\tp->header.freecnt += freecnt;\n}",
        "static int aqc111_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n{\n\tstruct aqc111_data *aqc111_data = dev->driver_priv;\n\tstruct sk_buff *new_skb = NULL;\n\tu32 pkt_total_offset = 0;": "static int aqc111_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n{\n\tstruct aqc111_data *aqc111_data = dev->driver_priv;\n\tstruct sk_buff *new_skb = NULL;\n\tu32 pkt_total_offset = 0;\n\tu64 *pkt_desc_ptr = NULL;\n\tu32 start_of_descs = 0;\n\tu32 desc_offset = 0; /*RX Header Offset*/\n\tu16 pkt_count = 0;\n\tu64 desc_hdr = 0;\n\tu16 vlan_tag = 0;\n\tu32 skb_len = 0;\n\n\tif (!skb)\n\t\tgoto err;\n\n\tif (skb->len == 0)\n\t\tgoto err;\n\n\tskb_len = skb->len;\n\t/* RX Descriptor Header */\n\tskb_trim(skb, skb->len - sizeof(desc_hdr));\n\tdesc_hdr = le64_to_cpup((u64 *)skb_tail_pointer(skb));\n\n\t/* Check these packets */\n\tdesc_offset = (desc_hdr & AQ_RX_DH_DESC_OFFSET_MASK) >>\n\t\t      AQ_RX_DH_DESC_OFFSET_SHIFT;\n\tpkt_count = desc_hdr & AQ_RX_DH_PKT_CNT_MASK;\n\tstart_of_descs = skb_len - ((pkt_count + 1) *  sizeof(desc_hdr));\n\n\t/* self check descs position */\n\tif (start_of_descs != desc_offset)\n\t\tgoto err;\n\n\t/* self check desc_offset from header and make sure that the\n\t * bounds of the metadata array are inside the SKB\n\t */\n\tif (pkt_count * 2 + desc_offset >= skb_len)\n\t\tgoto err;\n\n\t/* Packets must not overlap the metadata array */\n\tskb_trim(skb, desc_offset);\n\n\tif (pkt_count == 0)\n\t\tgoto err;\n\n\t/* Get the first RX packet descriptor */\n\tpkt_desc_ptr = (u64 *)(skb->data + desc_offset);\n\n\twhile (pkt_count--) {\n\t\tu64 pkt_desc = le64_to_cpup(pkt_desc_ptr);\n\t\tu32 pkt_len_with_padd = 0;\n\t\tu32 pkt_len = 0;\n\n\t\tpkt_len = (u32)((pkt_desc & AQ_RX_PD_LEN_MASK) >>\n\t\t\t  AQ_RX_PD_LEN_SHIFT);\n\t\tpkt_len_with_padd = ((pkt_len + 7) & 0x7FFF8);\n\n\t\tpkt_total_offset += pkt_len_with_padd;\n\t\tif (pkt_total_offset > desc_offset ||\n\t\t    (pkt_count == 0 && pkt_total_offset != desc_offset)) {\n\t\t\tgoto err;\n\t\t}\n\n\t\tif (pkt_desc & AQ_RX_PD_DROP ||\n\t\t    !(pkt_desc & AQ_RX_PD_RX_OK) ||\n\t\t    pkt_len > (dev->hard_mtu + AQ_RX_HW_PAD)) {\n\t\t\tskb_pull(skb, pkt_len_with_padd);\n\t\t\t/* Next RX Packet Descriptor */\n\t\t\tpkt_desc_ptr++;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Clone SKB */\n\t\tnew_skb = skb_clone(skb, GFP_ATOMIC);\n\n\t\tif (!new_skb)\n\t\t\tgoto err;\n\n\t\tnew_skb->len = pkt_len;\n\t\tskb_pull(new_skb, AQ_RX_HW_PAD);\n\t\tskb_set_tail_pointer(new_skb, new_skb->len);\n\n\t\tnew_skb->truesize = SKB_TRUESIZE(new_skb->len);\n\t\tif (aqc111_data->rx_checksum)\n\t\t\taqc111_rx_checksum(new_skb, pkt_desc);\n\n\t\tif (pkt_desc & AQ_RX_PD_VLAN) {\n\t\t\tvlan_tag = pkt_desc >> AQ_RX_PD_VLAN_SHIFT;\n\t\t\t__vlan_hwaccel_put_tag(new_skb, htons(ETH_P_8021Q),\n\t\t\t\t\t       vlan_tag & VLAN_VID_MASK);\n\t\t}\n\n\t\tusbnet_skb_return(dev, new_skb);\n\t\tif (pkt_count == 0)\n\t\t\tbreak;\n\n\t\tskb_pull(skb, pkt_len_with_padd);\n\n\t\t/* Next RX Packet Header */\n\t\tpkt_desc_ptr++;\n\n\t\tnew_skb = NULL;\n\t}\n\n\treturn 1;\n\nerr:\n\treturn 0;\n}",
        "static int test_process_multi_diff_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, diff addr\";": "static int test_process_multi_diff_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, diff addr\";\n\tsize_t res;\n\n\tfd1 = perf_process_event_open(HW_BREAKPOINT_RW, (__u64)&a, (__u64)sizeof(a));\n\tif (fd1 < 0) {\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tfd2 = perf_process_event_open(HW_BREAKPOINT_RW, (__u64)&b, (__u64)sizeof(b));\n\tif (fd2 < 0) {\n\t\tclose(fd1);\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tioctl(fd1, PERF_EVENT_IOC_RESET);\n\tioctl(fd2, PERF_EVENT_IOC_RESET);\n\tioctl(fd1, PERF_EVENT_IOC_ENABLE);\n\tioctl(fd2, PERF_EVENT_IOC_ENABLE);\n\tmulti_dawr_workload();\n\tioctl(fd1, PERF_EVENT_IOC_DISABLE);\n\tioctl(fd2, PERF_EVENT_IOC_DISABLE);\n\n\tres = read(fd1, &breaks1, sizeof(breaks1));\n\tassert(res == sizeof(unsigned long long));\n\tres = read(fd2, &breaks2, sizeof(breaks2));\n\tassert(res == sizeof(unsigned long long));\n\n\tclose(fd1);\n\tclose(fd2);\n\n\tif (breaks1 != 2 || breaks2 != 2) {\n\t\tprintf(\"FAILED: %s: %lld != 2 || %lld != 2\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static int wsa_macro_component_probe(struct snd_soc_component *comp)\n{\n\tstruct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);\n\n\tsnd_soc_component_init_regmap(comp, wsa->regmap);": "static int wsa_macro_component_probe(struct snd_soc_component *comp)\n{\n\tstruct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);\n\n\tsnd_soc_component_init_regmap(comp, wsa->regmap);\n\n\twsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;\n\n\t/* set SPKR rate to FS_2P4_3P072 */\n\tsnd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,\n\t\t\t\tCDC_WSA_RX_PATH_SPKR_RATE_MASK,\n\t\t\t\tCDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);\n\n\tsnd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,\n\t\t\t\tCDC_WSA_RX_PATH_SPKR_RATE_MASK,\n\t\t\t\tCDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);\n\n\twsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);\n\n\treturn 0;\n}",
        "static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)\n{\n\tint ret = 0, limit = QUP_READ_LIMIT;\n\tu32 len = 0, blocks, rem;\n\tu32 i = 0, tlen, tx_len = 0;": "static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)\n{\n\tint ret = 0, limit = QUP_READ_LIMIT;\n\tu32 len = 0, blocks, rem;\n\tu32 i = 0, tlen, tx_len = 0;\n\tu8 *tags;\n\n\tqup->blk_xfer_limit = QUP_READ_LIMIT;\n\tqup_i2c_set_blk_data(qup, msg);\n\n\tblocks = qup->blk.count;\n\trem = msg->len - (blocks - 1) * limit;\n\n\tif (msg->flags & I2C_M_RD) {\n\t\twhile (qup->blk.pos < blocks) {\n\t\t\ttlen = (i == (blocks - 1)) ? rem : limit;\n\t\t\ttags = &qup->start_tag.start[qup->tag_buf_pos + len];\n\t\t\tlen += qup_i2c_set_tags(tags, qup, msg);\n\t\t\tqup->blk.data_len -= tlen;\n\n\t\t\t/* scratch buf to read the start and len tags */\n\t\t\tret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],\n\t\t\t\t\t     &qup->brx.tag.start[0],\n\t\t\t\t\t     2, qup, DMA_FROM_DEVICE);\n\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\tret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],\n\t\t\t\t\t     &msg->buf[limit * i],\n\t\t\t\t\t     tlen, qup,\n\t\t\t\t\t     DMA_FROM_DEVICE);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\ti++;\n\t\t\tqup->blk.pos = i;\n\t\t}\n\t\tret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],\n\t\t\t\t     &qup->start_tag.start[qup->tag_buf_pos],\n\t\t\t\t     len, qup, DMA_TO_DEVICE);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tqup->tag_buf_pos += len;\n\t} else {\n\t\twhile (qup->blk.pos < blocks) {\n\t\t\ttlen = (i == (blocks - 1)) ? rem : limit;\n\t\t\ttags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];\n\t\t\tlen = qup_i2c_set_tags(tags, qup, msg);\n\t\t\tqup->blk.data_len -= tlen;\n\n\t\t\tret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],\n\t\t\t\t\t     tags, len,\n\t\t\t\t\t     qup, DMA_TO_DEVICE);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\ttx_len += len;\n\t\t\tret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],\n\t\t\t\t\t     &msg->buf[limit * i],\n\t\t\t\t\t     tlen, qup, DMA_TO_DEVICE);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\t\t\ti++;\n\t\t\tqup->blk.pos = i;\n\t\t}\n\n\t\tqup->tag_buf_pos += tx_len;\n\t}\n\n\treturn 0;\n}",
        "static int do_for_each_set_bit(unsigned int num_bits)\n{\n\tunsigned long *to_test = bitmap_zalloc(num_bits);\n\tstruct timeval start, end, diff;\n\tu64 runtime_us;": "static int do_for_each_set_bit(unsigned int num_bits)\n{\n\tunsigned long *to_test = bitmap_zalloc(num_bits);\n\tstruct timeval start, end, diff;\n\tu64 runtime_us;\n\tstruct stats fb_time_stats, tb_time_stats;\n\tdouble time_average, time_stddev;\n\tunsigned int bit, i, j;\n\tunsigned int set_bits, skip;\n\tunsigned int old;\n\n\tinit_stats(&fb_time_stats);\n\tinit_stats(&tb_time_stats);\n\n\tfor (set_bits = 1; set_bits <= num_bits; set_bits <<= 1) {\n\t\tbitmap_zero(to_test, num_bits);\n\t\tskip = num_bits / set_bits;\n\t\tfor (i = 0; i < num_bits; i += skip)\n\t\t\tset_bit(i, to_test);\n\n\t\tfor (i = 0; i < outer_iterations; i++) {\n\t\t\told = accumulator;\n\t\t\tgettimeofday(&start, NULL);\n\t\t\tfor (j = 0; j < inner_iterations; j++) {\n\t\t\t\tfor_each_set_bit(bit, to_test, num_bits)\n\t\t\t\t\tworkload(bit);\n\t\t\t}\n\t\t\tgettimeofday(&end, NULL);\n\t\t\tassert(old + (inner_iterations * set_bits) == accumulator);\n\t\t\ttimersub(&end, &start, &diff);\n\t\t\truntime_us = diff.tv_sec * USEC_PER_SEC + diff.tv_usec;\n\t\t\tupdate_stats(&fb_time_stats, runtime_us);\n\n\t\t\told = accumulator;\n\t\t\tgettimeofday(&start, NULL);\n\t\t\tfor (j = 0; j < inner_iterations; j++) {\n\t\t\t\tfor (bit = 0; bit < num_bits; bit++) {\n\t\t\t\t\tif (asm_test_bit(bit, to_test))\n\t\t\t\t\t\tworkload(bit);\n\t\t\t\t}\n\t\t\t}\n\t\t\tgettimeofday(&end, NULL);\n\t\t\tassert(old + (inner_iterations * set_bits) == accumulator);\n\t\t\ttimersub(&end, &start, &diff);\n\t\t\truntime_us = diff.tv_sec * USEC_PER_SEC + diff.tv_usec;\n\t\t\tupdate_stats(&tb_time_stats, runtime_us);\n\t\t}\n\n\t\tprintf(\"%d operations %d bits set of %d bits\\n\",\n\t\t\tinner_iterations, set_bits, num_bits);\n\t\ttime_average = avg_stats(&fb_time_stats);\n\t\ttime_stddev = stddev_stats(&fb_time_stats);\n\t\tprintf(\"  Average for_each_set_bit took: %.3f usec (+- %.3f usec)\\n\",\n\t\t\ttime_average, time_stddev);\n\t\ttime_average = avg_stats(&tb_time_stats);\n\t\ttime_stddev = stddev_stats(&tb_time_stats);\n\t\tprintf(\"  Average test_bit loop took:    %.3f usec (+- %.3f usec)\\n\",\n\t\t\ttime_average, time_stddev);\n\n\t\tif (use_of_val == accumulator)  /* Try to avoid compiler tricks. */\n\t\t\tprintf(\"\\n\");\n\t}\n\tbitmap_free(to_test);\n\treturn 0;\n}",
        "static void setexposure(struct gspca_dev *gspca_dev, s32 val)\n{\n\tint i, expo = 0;\n\n\t/* Register 0x8309 controls exposure for the spca561,": "static void setexposure(struct gspca_dev *gspca_dev, s32 val)\n{\n\tint i, expo = 0;\n\n\t/* Register 0x8309 controls exposure for the spca561,\n\t   the basic exposure setting goes from 1-2047, where 1 is completely\n\t   dark and 2047 is very bright. It not only influences exposure but\n\t   also the framerate (to allow for longer exposure) from 1 - 300 it\n\t   only raises the exposure time then from 300 - 600 it halves the\n\t   framerate to be able to further raise the exposure time and for every\n\t   300 more it halves the framerate again. This allows for a maximum\n\t   exposure time of circa 0.2 - 0.25 seconds (30 / (2000/3000) fps).\n\t   Sometimes this is not enough, the 1-2047 uses bits 0-10, bits 11-12\n\t   configure a divider for the base framerate which us used at the\n\t   exposure setting of 1-300. These bits configure the base framerate\n\t   according to the following formula: fps = 60 / (value + 2) */\n\n\t/* We choose to use the high bits setting the fixed framerate divisor\n\t   asap, as setting high basic exposure setting without the fixed\n\t   divider in combination with high gains makes the cam stop */\n\tstatic const int table[] =  { 0, 450, 550, 625, EXPOSURE_MAX };\n\n\tfor (i = 0; i < ARRAY_SIZE(table) - 1; i++) {\n\t\tif (val <= table[i + 1]) {\n\t\t\texpo  = val - table[i];\n\t\t\tif (i)\n\t\t\t\texpo += 300;\n\t\t\texpo |= i << 11;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tgspca_dev->usb_buf[0] = expo;\n\tgspca_dev->usb_buf[1] = expo >> 8;\n\treg_w_buf(gspca_dev, 0x8309, 2);\n}",
        "static int rvu_dbg_npa_ctx_display(struct seq_file *m, void *unused, int ctype)\n{\n\tvoid (*print_npa_ctx)(struct seq_file *m, struct npa_aq_enq_rsp *rsp);\n\tstruct npa_aq_enq_req aq_req;\n\tstruct npa_aq_enq_rsp rsp;": "static int rvu_dbg_npa_ctx_display(struct seq_file *m, void *unused, int ctype)\n{\n\tvoid (*print_npa_ctx)(struct seq_file *m, struct npa_aq_enq_rsp *rsp);\n\tstruct npa_aq_enq_req aq_req;\n\tstruct npa_aq_enq_rsp rsp;\n\tstruct rvu_pfvf *pfvf;\n\tint aura, rc, max_id;\n\tint npalf, id, all;\n\tstruct rvu *rvu;\n\tu16 pcifunc;\n\n\trvu = m->private;\n\n\tswitch (ctype) {\n\tcase NPA_AQ_CTYPE_AURA:\n\t\tnpalf = rvu->rvu_dbg.npa_aura_ctx.lf;\n\t\tid = rvu->rvu_dbg.npa_aura_ctx.id;\n\t\tall = rvu->rvu_dbg.npa_aura_ctx.all;\n\t\tbreak;\n\n\tcase NPA_AQ_CTYPE_POOL:\n\t\tnpalf = rvu->rvu_dbg.npa_pool_ctx.lf;\n\t\tid = rvu->rvu_dbg.npa_pool_ctx.id;\n\t\tall = rvu->rvu_dbg.npa_pool_ctx.all;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tif (!rvu_dbg_is_valid_lf(rvu, BLKADDR_NPA, npalf, &pcifunc))\n\t\treturn -EINVAL;\n\n\tpfvf = rvu_get_pfvf(rvu, pcifunc);\n\tif (ctype == NPA_AQ_CTYPE_AURA && !pfvf->aura_ctx) {\n\t\tseq_puts(m, \"Aura context is not initialized\\n\");\n\t\treturn -EINVAL;\n\t} else if (ctype == NPA_AQ_CTYPE_POOL && !pfvf->pool_ctx) {\n\t\tseq_puts(m, \"Pool context is not initialized\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(&aq_req, 0, sizeof(struct npa_aq_enq_req));\n\taq_req.hdr.pcifunc = pcifunc;\n\taq_req.ctype = ctype;\n\taq_req.op = NPA_AQ_INSTOP_READ;\n\tif (ctype == NPA_AQ_CTYPE_AURA) {\n\t\tmax_id = pfvf->aura_ctx->qsize;\n\t\tprint_npa_ctx = print_npa_aura_ctx;\n\t} else {\n\t\tmax_id = pfvf->pool_ctx->qsize;\n\t\tprint_npa_ctx = print_npa_pool_ctx;\n\t}\n\n\tif (id < 0 || id >= max_id) {\n\t\tseq_printf(m, \"Invalid %s, valid range is 0-%d\\n\",\n\t\t\t   (ctype == NPA_AQ_CTYPE_AURA) ? \"aura\" : \"pool\",\n\t\t\tmax_id - 1);\n\t\treturn -EINVAL;\n\t}\n\n\tif (all)\n\t\tid = 0;\n\telse\n\t\tmax_id = id + 1;\n\n\tfor (aura = id; aura < max_id; aura++) {\n\t\taq_req.aura_id = aura;\n\t\tseq_printf(m, \"======%s : %d=======\\n\",\n\t\t\t   (ctype == NPA_AQ_CTYPE_AURA) ? \"AURA\" : \"POOL\",\n\t\t\taq_req.aura_id);\n\t\trc = rvu_npa_aq_enq_inst(rvu, &aq_req, &rsp);\n\t\tif (rc) {\n\t\t\tseq_puts(m, \"Failed to read context\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tprint_npa_ctx(m, &rsp);\n\t}\n\treturn 0;\n}",
        "static void ax88796c_proc_tx_hdr(struct tx_pkt_info *info, u8 ip_summed)\n{\n\tu16 pkt_len_bar = (~info->pkt_len & TX_HDR_SOP_PKTLENBAR);\n\n\t/* Prepare SOP header */": "static void ax88796c_proc_tx_hdr(struct tx_pkt_info *info, u8 ip_summed)\n{\n\tu16 pkt_len_bar = (~info->pkt_len & TX_HDR_SOP_PKTLENBAR);\n\n\t/* Prepare SOP header */\n\tinfo->sop.flags_len = info->pkt_len |\n\t\t((ip_summed == CHECKSUM_NONE) ||\n\t\t (ip_summed == CHECKSUM_UNNECESSARY) ? TX_HDR_SOP_DICF : 0);\n\n\tinfo->sop.seq_lenbar = ((info->seq_num << 11) & TX_HDR_SOP_SEQNUM)\n\t\t\t\t| pkt_len_bar;\n\tcpu_to_be16s(&info->sop.flags_len);\n\tcpu_to_be16s(&info->sop.seq_lenbar);\n\n\t/* Prepare Segment header */\n\tinfo->seg.flags_seqnum_seglen = TX_HDR_SEG_FS | TX_HDR_SEG_LS\n\t\t\t\t\t\t| info->pkt_len;\n\n\tinfo->seg.eo_so_seglenbar = pkt_len_bar;\n\n\tcpu_to_be16s(&info->seg.flags_seqnum_seglen);\n\tcpu_to_be16s(&info->seg.eo_so_seglenbar);\n\n\t/* Prepare EOP header */\n\tinfo->eop.seq_len = ((info->seq_num << 11) &\n\t\t\t     TX_HDR_EOP_SEQNUM) | info->pkt_len;\n\tinfo->eop.seqbar_lenbar = ((~info->seq_num << 11) &\n\t\t\t\t   TX_HDR_EOP_SEQNUMBAR) | pkt_len_bar;\n\n\tcpu_to_be16s(&info->eop.seq_len);\n\tcpu_to_be16s(&info->eop.seqbar_lenbar);\n}",
        "static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)\n{\n\t/* zero out state machine indices */\n\t/* rx indices */\n\tindex_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;": "static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)\n{\n\t/* zero out state machine indices */\n\t/* rx indices */\n\tindex_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;\n\n\t/* tx indices */\n\tindex_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;\n\n\t/* map indices */\n\t/* rx indices */\n\tindex_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=\n\t\tSM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;\n\n\t/* tx indices */\n\tindex_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=\n\t\tSM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=\n\t\tSM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=\n\t\tSM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=\n\t\tSM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;\n}",
        "static int test_debug_fs_uprobe(char *binary_path, long offset, bool is_return)\n{\n\tchar buf[256], event_alias[sizeof(\"test_1234567890\")];\n\tconst char *event_type = \"uprobe\";\n\tstruct perf_event_attr attr = {};": "static int test_debug_fs_uprobe(char *binary_path, long offset, bool is_return)\n{\n\tchar buf[256], event_alias[sizeof(\"test_1234567890\")];\n\tconst char *event_type = \"uprobe\";\n\tstruct perf_event_attr attr = {};\n\t__u64 probe_offset, probe_addr;\n\t__u32 len, prog_id, fd_type;\n\tint err = -1, res, kfd, efd;\n\tstruct bpf_link *link;\n\tssize_t bytes;\n\n\tsnprintf(buf, sizeof(buf), \"/sys/kernel/debug/tracing/%s_events\",\n\t\t event_type);\n\tkfd = open(buf, O_WRONLY | O_TRUNC, 0);\n\tCHECK_PERROR_RET(kfd < 0);\n\n\tres = snprintf(event_alias, sizeof(event_alias), \"test_%d\", getpid());\n\tCHECK_PERROR_RET(res < 0 || res >= sizeof(event_alias));\n\n\tres = snprintf(buf, sizeof(buf), \"%c:%ss/%s %s:0x%lx\",\n\t\t       is_return ? 'r' : 'p', event_type, event_alias,\n\t\t       binary_path, offset);\n\tCHECK_PERROR_RET(res < 0 || res >= sizeof(buf));\n\tCHECK_PERROR_RET(write(kfd, buf, strlen(buf)) < 0);\n\n\tclose(kfd);\n\tkfd = -1;\n\n\tsnprintf(buf, sizeof(buf), \"/sys/kernel/debug/tracing/events/%ss/%s/id\",\n\t\t event_type, event_alias);\n\tefd = open(buf, O_RDONLY, 0);\n\tCHECK_PERROR_RET(efd < 0);\n\n\tbytes = read(efd, buf, sizeof(buf));\n\tCHECK_PERROR_RET(bytes <= 0 || bytes >= sizeof(buf));\n\tclose(efd);\n\tbuf[bytes] = '\\0';\n\n\tattr.config = strtol(buf, NULL, 0);\n\tattr.type = PERF_TYPE_TRACEPOINT;\n\tattr.sample_period = 1;\n\tattr.wakeup_events = 1;\n\n\tkfd = sys_perf_event_open(&attr, -1, 0, -1, PERF_FLAG_FD_CLOEXEC);\n\tlink = bpf_program__attach_perf_event(progs[0], kfd);\n\tif (libbpf_get_error(link)) {\n\t\tprintf(\"ERROR: bpf_program__attach_perf_event failed\\n\");\n\t\tlink = NULL;\n\t\tclose(kfd);\n\t\tgoto cleanup;\n\t}\n\n\tlen = sizeof(buf);\n\terr = bpf_task_fd_query(getpid(), kfd, 0, buf, &len,\n\t\t\t\t&prog_id, &fd_type, &probe_offset,\n\t\t\t\t&probe_addr);\n\tif (err < 0) {\n\t\tprintf(\"FAIL: %s, binary_path %s\\n\", __func__, binary_path);\n\t\tperror(\"    :\");\n\t\treturn -1;\n\t}\n\tif ((is_return && fd_type != BPF_FD_TYPE_URETPROBE) ||\n\t    (!is_return && fd_type != BPF_FD_TYPE_UPROBE)) {\n\t\tprintf(\"FAIL: %s, incorrect fd_type %u\\n\", __func__,\n\t\t       fd_type);\n\t\treturn -1;\n\t}\n\tif (strcmp(binary_path, buf) != 0) {\n\t\tprintf(\"FAIL: %s, incorrect buf %s\\n\", __func__, buf);\n\t\treturn -1;\n\t}\n\tif (probe_offset != offset) {\n\t\tprintf(\"FAIL: %s, incorrect probe_offset 0x%llx\\n\", __func__,\n\t\t       probe_offset);\n\t\treturn -1;\n\t}\n\terr = 0;\n\ncleanup:\n\tbpf_link__destroy(link);\n\treturn err;\n}",
        "static int prepare_client_ident(struct ceph_connection *con)\n{\n\tstruct ceph_entity_addr *my_addr = &con->msgr->inst.addr;\n\tstruct ceph_client *client = from_msgr(con->msgr);\n\tu64 global_id = ceph_client_gid(client);": "static int prepare_client_ident(struct ceph_connection *con)\n{\n\tstruct ceph_entity_addr *my_addr = &con->msgr->inst.addr;\n\tstruct ceph_client *client = from_msgr(con->msgr);\n\tu64 global_id = ceph_client_gid(client);\n\tvoid *buf, *p;\n\tint ctrl_len;\n\n\tWARN_ON(con->v2.server_cookie);\n\tWARN_ON(con->v2.connect_seq);\n\tWARN_ON(con->v2.peer_global_seq);\n\n\tif (!con->v2.client_cookie) {\n\t\tdo {\n\t\t\tget_random_bytes(&con->v2.client_cookie,\n\t\t\t\t\t sizeof(con->v2.client_cookie));\n\t\t} while (!con->v2.client_cookie);\n\t\tdout(\"%s con %p generated cookie 0x%llx\\n\", __func__, con,\n\t\t     con->v2.client_cookie);\n\t} else {\n\t\tdout(\"%s con %p cookie already set 0x%llx\\n\", __func__, con,\n\t\t     con->v2.client_cookie);\n\t}\n\n\tdout(\"%s con %p my_addr %s/%u peer_addr %s/%u global_id %llu global_seq %llu features 0x%llx required_features 0x%llx cookie 0x%llx\\n\",\n\t     __func__, con, ceph_pr_addr(my_addr), le32_to_cpu(my_addr->nonce),\n\t     ceph_pr_addr(&con->peer_addr), le32_to_cpu(con->peer_addr.nonce),\n\t     global_id, con->v2.global_seq, client->supported_features,\n\t     client->required_features, con->v2.client_cookie);\n\n\tctrl_len = 1 + 4 + ceph_entity_addr_encoding_len(my_addr) +\n\t\t   ceph_entity_addr_encoding_len(&con->peer_addr) + 6 * 8;\n\tbuf = alloc_conn_buf(con, head_onwire_len(ctrl_len, con_secure(con)));\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tp = CTRL_BODY(buf);\n\tceph_encode_8(&p, 2);  /* addrvec marker */\n\tceph_encode_32(&p, 1);  /* addr_cnt */\n\tceph_encode_entity_addr(&p, my_addr);\n\tceph_encode_entity_addr(&p, &con->peer_addr);\n\tceph_encode_64(&p, global_id);\n\tceph_encode_64(&p, con->v2.global_seq);\n\tceph_encode_64(&p, client->supported_features);\n\tceph_encode_64(&p, client->required_features);\n\tceph_encode_64(&p, 0);  /* flags */\n\tceph_encode_64(&p, con->v2.client_cookie);\n\tWARN_ON(p != CTRL_BODY(buf) + ctrl_len);\n\n\treturn prepare_control(con, FRAME_TAG_CLIENT_IDENT, buf, ctrl_len);\n}",
        "static int receive_flow_control(struct nozomi *dc)\n{\n\tenum port_type port = PORT_MDM;\n\tstruct ctrl_dl ctrl_dl;\n\tstruct ctrl_dl old_ctrl;": "static int receive_flow_control(struct nozomi *dc)\n{\n\tenum port_type port = PORT_MDM;\n\tstruct ctrl_dl ctrl_dl;\n\tstruct ctrl_dl old_ctrl;\n\tu16 enable_ier = 0;\n\n\tread_mem32((u32 *) &ctrl_dl, dc->port[PORT_CTRL].dl_addr[CH_A], 2);\n\n\tswitch (ctrl_dl.port) {\n\tcase CTRL_CMD:\n\t\tDBG1(\"The Base Band sends this value as a response to a \"\n\t\t\t\"request for IMSI detach sent over the control \"\n\t\t\t\"channel uplink (see section 7.6.1).\");\n\t\tbreak;\n\tcase CTRL_MDM:\n\t\tport = PORT_MDM;\n\t\tenable_ier = MDM_DL;\n\t\tbreak;\n\tcase CTRL_DIAG:\n\t\tport = PORT_DIAG;\n\t\tenable_ier = DIAG_DL;\n\t\tbreak;\n\tcase CTRL_APP1:\n\t\tport = PORT_APP1;\n\t\tenable_ier = APP1_DL;\n\t\tbreak;\n\tcase CTRL_APP2:\n\t\tport = PORT_APP2;\n\t\tenable_ier = APP2_DL;\n\t\tif (dc->state == NOZOMI_STATE_ALLOCATED) {\n\t\t\t/*\n\t\t\t * After card initialization the flow control\n\t\t\t * received for APP2 is always the last\n\t\t\t */\n\t\t\tdc->state = NOZOMI_STATE_READY;\n\t\t\tdev_info(&dc->pdev->dev, \"Device READY!\\n\");\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tdev_err(&dc->pdev->dev,\n\t\t\t\"ERROR: flow control received for non-existing port\\n\");\n\t\treturn 0;\n\t}\n\n\tDBG1(\"0x%04X->0x%04X\", *((u16 *)&dc->port[port].ctrl_dl),\n\t   *((u16 *)&ctrl_dl));\n\n\told_ctrl = dc->port[port].ctrl_dl;\n\tdc->port[port].ctrl_dl = ctrl_dl;\n\n\tif (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) {\n\t\tDBG1(\"Disable interrupt (0x%04X) on port: %d\",\n\t\t\tenable_ier, port);\n\t\tdisable_transmit_ul(port, dc);\n\n\t} else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) {\n\n\t\tif (kfifo_len(&dc->port[port].fifo_ul)) {\n\t\t\tDBG1(\"Enable interrupt (0x%04X) on port: %d\",\n\t\t\t\tenable_ier, port);\n\t\t\tDBG1(\"Data in buffer [%d], enable transmit! \",\n\t\t\t\tkfifo_len(&dc->port[port].fifo_ul));\n\t\t\tenable_transmit_ul(port, dc);\n\t\t} else {\n\t\t\tDBG1(\"No data in buffer...\");\n\t\t}\n\t}\n\n\tif (*(u16 *)&old_ctrl == *(u16 *)&ctrl_dl) {\n\t\tDBG1(\" No change in mctrl\");\n\t\treturn 1;\n\t}\n\t/* Update statistics */\n\tif (old_ctrl.CTS != ctrl_dl.CTS)\n\t\tdc->port[port].tty_icount.cts++;\n\tif (old_ctrl.DSR != ctrl_dl.DSR)\n\t\tdc->port[port].tty_icount.dsr++;\n\tif (old_ctrl.RI != ctrl_dl.RI)\n\t\tdc->port[port].tty_icount.rng++;\n\tif (old_ctrl.DCD != ctrl_dl.DCD)\n\t\tdc->port[port].tty_icount.dcd++;\n\n\twake_up_interruptible(&dc->port[port].tty_wait);\n\n\tDBG1(\"port: %d DCD(%d), CTS(%d), RI(%d), DSR(%d)\",\n\t   port,\n\t   dc->port[port].tty_icount.dcd, dc->port[port].tty_icount.cts,\n\t   dc->port[port].tty_icount.rng, dc->port[port].tty_icount.dsr);\n\n\treturn 1;\n}",
        "static void amd_pmc_s2idle_prepare(void)\n{\n\tstruct amd_pmc_dev *pdev = &pmc;\n\tint rc;\n\tu8 msg;": "static void amd_pmc_s2idle_prepare(void)\n{\n\tstruct amd_pmc_dev *pdev = &pmc;\n\tint rc;\n\tu8 msg;\n\tu32 arg = 1;\n\n\t/* Reset and Start SMU logging - to monitor the s0i3 stats */\n\tamd_pmc_setup_smu_logging(pdev);\n\n\t/* Activate CZN specific RTC functionality */\n\tif (pdev->cpu_id == AMD_CPU_ID_CZN) {\n\t\trc = amd_pmc_verify_czn_rtc(pdev, &arg);\n\t\tif (rc) {\n\t\t\tdev_err(pdev->dev, \"failed to set RTC: %d\\n\", rc);\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* Dump the IdleMask before we send hint to SMU */\n\tamd_pmc_idlemask_read(pdev, pdev->dev, NULL);\n\tmsg = amd_pmc_get_os_hint(pdev);\n\trc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);\n\tif (rc) {\n\t\tdev_err(pdev->dev, \"suspend failed: %d\\n\", rc);\n\t\treturn;\n\t}\n\n\tif (enable_stb) {\n\t\trc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);\n\t\tif (rc)\n\t\t\tdev_err(pdev->dev, \"error writing to STB: %d\\n\", rc);\n\t}\n}",
        "static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)\n{\n\tstruct v4l2_pix_format_mplane *pix =\n\t\t&line->video_out.active_fmt.fmt.pix_mp;\n": "static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)\n{\n\tstruct v4l2_pix_format_mplane *pix =\n\t\t&line->video_out.active_fmt.fmt.pix_mp;\n\n\twm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */\n\n\t/* no clock gating at bus input */\n\twritel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);\n\n\twritel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);\n\n\twritel_relaxed(pix->plane_fmt[0].bytesperline * pix->height,\n\t\t       vfe->base + VFE_BUS_WM_FRAME_INCR(wm));\n\twritel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));\n\twritel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH,\n\t\t       vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));\n\twritel_relaxed(pix->plane_fmt[0].bytesperline,\n\t\t       vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));\n\twritel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));\n\n\t/* no dropped frames, one irq per frame */\n\twritel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));\n\twritel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));\n\twritel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));\n\twritel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));\n\n\twritel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE,\n\t\t       vfe->base + VFE_BUS_WM_CFG(wm));\n}",
        "static void netfs_rreq_do_write_to_cache(struct netfs_io_request *rreq)\n{\n\tstruct netfs_cache_resources *cres = &rreq->cache_resources;\n\tstruct netfs_io_subrequest *subreq, *next, *p;\n\tstruct iov_iter iter;": "static void netfs_rreq_do_write_to_cache(struct netfs_io_request *rreq)\n{\n\tstruct netfs_cache_resources *cres = &rreq->cache_resources;\n\tstruct netfs_io_subrequest *subreq, *next, *p;\n\tstruct iov_iter iter;\n\tint ret;\n\n\ttrace_netfs_rreq(rreq, netfs_rreq_trace_copy);\n\n\t/* We don't want terminating writes trying to wake us up whilst we're\n\t * still going through the list.\n\t */\n\tatomic_inc(&rreq->nr_copy_ops);\n\n\tlist_for_each_entry_safe(subreq, p, &rreq->subrequests, rreq_link) {\n\t\tif (!test_bit(NETFS_SREQ_COPY_TO_CACHE, &subreq->flags)) {\n\t\t\tlist_del_init(&subreq->rreq_link);\n\t\t\tnetfs_put_subrequest(subreq, false,\n\t\t\t\t\t     netfs_sreq_trace_put_no_copy);\n\t\t}\n\t}\n\n\tlist_for_each_entry(subreq, &rreq->subrequests, rreq_link) {\n\t\t/* Amalgamate adjacent writes */\n\t\twhile (!list_is_last(&subreq->rreq_link, &rreq->subrequests)) {\n\t\t\tnext = list_next_entry(subreq, rreq_link);\n\t\t\tif (next->start != subreq->start + subreq->len)\n\t\t\t\tbreak;\n\t\t\tsubreq->len += next->len;\n\t\t\tlist_del_init(&next->rreq_link);\n\t\t\tnetfs_put_subrequest(next, false,\n\t\t\t\t\t     netfs_sreq_trace_put_merged);\n\t\t}\n\n\t\tret = cres->ops->prepare_write(cres, &subreq->start, &subreq->len,\n\t\t\t\t\t       rreq->i_size, true);\n\t\tif (ret < 0) {\n\t\t\ttrace_netfs_failure(rreq, subreq, ret, netfs_fail_prepare_write);\n\t\t\ttrace_netfs_sreq(subreq, netfs_sreq_trace_write_skip);\n\t\t\tcontinue;\n\t\t}\n\n\t\tiov_iter_xarray(&iter, WRITE, &rreq->mapping->i_pages,\n\t\t\t\tsubreq->start, subreq->len);\n\n\t\tatomic_inc(&rreq->nr_copy_ops);\n\t\tnetfs_stat(&netfs_n_rh_write);\n\t\tnetfs_get_subrequest(subreq, netfs_sreq_trace_get_copy_to_cache);\n\t\ttrace_netfs_sreq(subreq, netfs_sreq_trace_write);\n\t\tcres->ops->write(cres, subreq->start, &iter,\n\t\t\t\t netfs_rreq_copy_terminated, subreq);\n\t}\n\n\t/* If we decrement nr_copy_ops to 0, the usage ref belongs to us. */\n\tif (atomic_dec_and_test(&rreq->nr_copy_ops))\n\t\tnetfs_rreq_unmark_after_write(rreq, false);\n}",
        "static void __smb2_oplock_break_noti(struct work_struct *wk)\n{\n\tstruct smb2_oplock_break *rsp = NULL;\n\tstruct ksmbd_work *work = container_of(wk, struct ksmbd_work, work);\n\tstruct ksmbd_conn *conn = work->conn;": "static void __smb2_oplock_break_noti(struct work_struct *wk)\n{\n\tstruct smb2_oplock_break *rsp = NULL;\n\tstruct ksmbd_work *work = container_of(wk, struct ksmbd_work, work);\n\tstruct ksmbd_conn *conn = work->conn;\n\tstruct oplock_break_info *br_info = work->request_buf;\n\tstruct smb2_hdr *rsp_hdr;\n\tstruct ksmbd_file *fp;\n\n\tfp = ksmbd_lookup_durable_fd(br_info->fid);\n\tif (!fp) {\n\t\tatomic_dec(&conn->r_count);\n\t\tksmbd_free_work_struct(work);\n\t\treturn;\n\t}\n\n\tif (allocate_oplock_break_buf(work)) {\n\t\tpr_err(\"smb2_allocate_rsp_buf failed! \");\n\t\tatomic_dec(&conn->r_count);\n\t\tksmbd_fd_put(work, fp);\n\t\tksmbd_free_work_struct(work);\n\t\treturn;\n\t}\n\n\trsp_hdr = smb2_get_msg(work->response_buf);\n\tmemset(rsp_hdr, 0, sizeof(struct smb2_hdr) + 2);\n\t*(__be32 *)work->response_buf =\n\t\tcpu_to_be32(conn->vals->header_size);\n\trsp_hdr->ProtocolId = SMB2_PROTO_NUMBER;\n\trsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE;\n\trsp_hdr->CreditRequest = cpu_to_le16(0);\n\trsp_hdr->Command = SMB2_OPLOCK_BREAK;\n\trsp_hdr->Flags = (SMB2_FLAGS_SERVER_TO_REDIR);\n\trsp_hdr->NextCommand = 0;\n\trsp_hdr->MessageId = cpu_to_le64(-1);\n\trsp_hdr->Id.SyncId.ProcessId = 0;\n\trsp_hdr->Id.SyncId.TreeId = 0;\n\trsp_hdr->SessionId = 0;\n\tmemset(rsp_hdr->Signature, 0, 16);\n\n\trsp = smb2_get_msg(work->response_buf);\n\n\trsp->StructureSize = cpu_to_le16(24);\n\tif (!br_info->open_trunc &&\n\t    (br_info->level == SMB2_OPLOCK_LEVEL_BATCH ||\n\t     br_info->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE))\n\t\trsp->OplockLevel = SMB2_OPLOCK_LEVEL_II;\n\telse\n\t\trsp->OplockLevel = SMB2_OPLOCK_LEVEL_NONE;\n\trsp->Reserved = 0;\n\trsp->Reserved2 = 0;\n\trsp->PersistentFid = fp->persistent_id;\n\trsp->VolatileFid = fp->volatile_id;\n\n\tinc_rfc1001_len(work->response_buf, 24);\n\n\tksmbd_debug(OPLOCK,\n\t\t    \"sending oplock break v_id %llu p_id = %llu lock level = %d\\n\",\n\t\t    rsp->VolatileFid, rsp->PersistentFid, rsp->OplockLevel);\n\n\tksmbd_fd_put(work, fp);\n\tksmbd_conn_write(work);\n\tksmbd_free_work_struct(work);\n\tatomic_dec(&conn->r_count);\n}",
        "static void mtip_handle_tfe(struct driver_data *dd)\n{\n\tint group, tag, bit, reissue, rv;\n\tstruct mtip_port *port;\n\tstruct mtip_cmd  *cmd;": "static void mtip_handle_tfe(struct driver_data *dd)\n{\n\tint group, tag, bit, reissue, rv;\n\tstruct mtip_port *port;\n\tstruct mtip_cmd  *cmd;\n\tu32 completed;\n\tstruct host_to_dev_fis *fis;\n\tunsigned long tagaccum[SLOTBITS_IN_LONGS];\n\tunsigned int cmd_cnt = 0;\n\tunsigned char *buf;\n\tchar *fail_reason = NULL;\n\tint fail_all_ncq_write = 0, fail_all_ncq_cmds = 0;\n\n\tdev_warn(&dd->pdev->dev, \"Taskfile error\\n\");\n\n\tport = dd->port;\n\n\tif (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags)) {\n\t\tcmd = mtip_cmd_from_tag(dd, MTIP_TAG_INTERNAL);\n\t\tdbg_printk(MTIP_DRV_NAME \" TFE for the internal command\\n\");\n\t\tmtip_complete_command(cmd, BLK_STS_IOERR);\n\t\treturn;\n\t}\n\n\t/* clear the tag accumulator */\n\tmemset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));\n\n\t/* Loop through all the groups */\n\tfor (group = 0; group < dd->slot_groups; group++) {\n\t\tcompleted = readl(port->completed[group]);\n\n\t\tdev_warn(&dd->pdev->dev, \"g=%u, comp=%x\\n\", group, completed);\n\n\t\t/* clear completed status register in the hardware.*/\n\t\twritel(completed, port->completed[group]);\n\n\t\t/* Process successfully completed commands */\n\t\tfor (bit = 0; bit < 32 && completed; bit++) {\n\t\t\tif (!(completed & (1<<bit)))\n\t\t\t\tcontinue;\n\t\t\ttag = (group << 5) + bit;\n\n\t\t\t/* Skip the internal command slot */\n\t\t\tif (tag == MTIP_TAG_INTERNAL)\n\t\t\t\tcontinue;\n\n\t\t\tcmd = mtip_cmd_from_tag(dd, tag);\n\t\t\tmtip_complete_command(cmd, 0);\n\t\t\tset_bit(tag, tagaccum);\n\t\t\tcmd_cnt++;\n\t\t}\n\t}\n\n\tprint_tags(dd, \"completed (TFE)\", tagaccum, cmd_cnt);\n\n\t/* Restart the port */\n\tmdelay(20);\n\tmtip_restart_port(port);\n\n\t/* Trying to determine the cause of the error */\n\trv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,\n\t\t\t\tdd->port->log_buf,\n\t\t\t\tdd->port->log_buf_dma, 1);\n\tif (rv) {\n\t\tdev_warn(&dd->pdev->dev,\n\t\t\t\"Error in READ LOG EXT (10h) command\\n\");\n\t\t/* non-critical error, don't fail the load */\n\t} else {\n\t\tbuf = (unsigned char *)dd->port->log_buf;\n\t\tif (buf[259] & 0x1) {\n\t\t\tdev_info(&dd->pdev->dev,\n\t\t\t\t\"Write protect bit is set.\\n\");\n\t\t\tset_bit(MTIP_DDF_WRITE_PROTECT_BIT, &dd->dd_flag);\n\t\t\tfail_all_ncq_write = 1;\n\t\t\tfail_reason = \"write protect\";\n\t\t}\n\t\tif (buf[288] == 0xF7) {\n\t\t\tdev_info(&dd->pdev->dev,\n\t\t\t\t\"Exceeded Tmax, drive in thermal shutdown.\\n\");\n\t\t\tset_bit(MTIP_DDF_OVER_TEMP_BIT, &dd->dd_flag);\n\t\t\tfail_all_ncq_cmds = 1;\n\t\t\tfail_reason = \"thermal shutdown\";\n\t\t}\n\t\tif (buf[288] == 0xBF) {\n\t\t\tset_bit(MTIP_DDF_REBUILD_FAILED_BIT, &dd->dd_flag);\n\t\t\tdev_info(&dd->pdev->dev,\n\t\t\t\t\"Drive indicates rebuild has failed. Secure erase required.\\n\");\n\t\t\tfail_all_ncq_cmds = 1;\n\t\t\tfail_reason = \"rebuild failed\";\n\t\t}\n\t}\n\n\t/* clear the tag accumulator */\n\tmemset(tagaccum, 0, SLOTBITS_IN_LONGS * sizeof(long));\n\n\t/* Loop through all the groups */\n\tfor (group = 0; group < dd->slot_groups; group++) {\n\t\tfor (bit = 0; bit < 32; bit++) {\n\t\t\treissue = 1;\n\t\t\ttag = (group << 5) + bit;\n\t\t\tcmd = mtip_cmd_from_tag(dd, tag);\n\n\t\t\tfis = (struct host_to_dev_fis *)cmd->command;\n\n\t\t\t/* Should re-issue? */\n\t\t\tif (tag == MTIP_TAG_INTERNAL ||\n\t\t\t    fis->command == ATA_CMD_SET_FEATURES)\n\t\t\t\treissue = 0;\n\t\t\telse {\n\t\t\t\tif (fail_all_ncq_cmds ||\n\t\t\t\t\t(fail_all_ncq_write &&\n\t\t\t\t\tfis->command == ATA_CMD_FPDMA_WRITE)) {\n\t\t\t\t\tdev_warn(&dd->pdev->dev,\n\t\t\t\t\t\"  Fail: %s w/tag %d [%s].\\n\",\n\t\t\t\t\tfis->command == ATA_CMD_FPDMA_WRITE ?\n\t\t\t\t\t\t\"write\" : \"read\",\n\t\t\t\t\ttag,\n\t\t\t\t\tfail_reason != NULL ?\n\t\t\t\t\t\tfail_reason : \"unknown\");\n\t\t\t\t\tmtip_complete_command(cmd, BLK_STS_MEDIUM);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * First check if this command has\n\t\t\t *  exceeded its retries.\n\t\t\t */\n\t\t\tif (reissue && (cmd->retries-- > 0)) {\n\n\t\t\t\tset_bit(tag, tagaccum);\n\n\t\t\t\t/* Re-issue the command. */\n\t\t\t\tmtip_issue_ncq_command(port, tag);\n\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* Retire a command that will not be reissued */\n\t\t\tdev_warn(&port->dd->pdev->dev,\n\t\t\t\t\"retiring tag %d\\n\", tag);\n\n\t\t\tmtip_complete_command(cmd, BLK_STS_IOERR);\n\t\t}\n\t}\n\tprint_tags(dd, \"reissued (TFE)\", tagaccum, cmd_cnt);\n}",
        "static int acpi_hibernation_begin_old(pm_message_t stage)\n{\n\tint error;\n\t/*\n\t * The _TTS object should always be evaluated before the _PTS object.": "static int acpi_hibernation_begin_old(pm_message_t stage)\n{\n\tint error;\n\t/*\n\t * The _TTS object should always be evaluated before the _PTS object.\n\t * When the old_suspended_ordering is true, the _PTS object is\n\t * evaluated in the acpi_sleep_prepare.\n\t */\n\tacpi_sleep_tts_switch(ACPI_STATE_S4);\n\n\terror = acpi_sleep_prepare(ACPI_STATE_S4);\n\tif (error)\n\t\treturn error;\n\n\tif (!nvs_nosave) {\n\t\terror = suspend_nvs_alloc();\n\t\tif (error)\n\t\t\treturn error;\n\t}\n\n\tif (stage.event == PM_EVENT_HIBERNATE)\n\t\tpm_set_suspend_via_firmware();\n\n\tacpi_target_sleep_state = ACPI_STATE_S4;\n\tacpi_scan_lock_acquire();\n\treturn 0;\n}",
        "static int qspi_set_config_register(struct rspi_data *rspi, int access_size)\n{\n\tunsigned long clksrc;\n\tint brdv = 0, spbr;\n": "static int qspi_set_config_register(struct rspi_data *rspi, int access_size)\n{\n\tunsigned long clksrc;\n\tint brdv = 0, spbr;\n\n\t/* Sets output mode, MOSI signal, and (optionally) loopback */\n\trspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);\n\n\t/* Sets transfer bit rate */\n\tclksrc = clk_get_rate(rspi->clk);\n\tif (rspi->speed_hz >= clksrc) {\n\t\tspbr = 0;\n\t\trspi->speed_hz = clksrc;\n\t} else {\n\t\tspbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);\n\t\twhile (spbr > 255 && brdv < 3) {\n\t\t\tbrdv++;\n\t\t\tspbr = DIV_ROUND_UP(spbr, 2);\n\t\t}\n\t\tspbr = clamp(spbr, 0, 255);\n\t\trspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);\n\t}\n\trspi_write8(rspi, spbr, RSPI_SPBR);\n\trspi->spcmd |= SPCMD_BRDV(brdv);\n\n\t/* Disable dummy transmission, set byte access */\n\trspi_write8(rspi, 0, RSPI_SPDCR);\n\trspi->byte_access = 1;\n\n\t/* Sets RSPCK, SSL, next-access delay value */\n\trspi_write8(rspi, 0x00, RSPI_SPCKD);\n\trspi_write8(rspi, 0x00, RSPI_SSLND);\n\trspi_write8(rspi, 0x00, RSPI_SPND);\n\n\t/* Data Length Setting */\n\tif (access_size == 8)\n\t\trspi->spcmd |= SPCMD_SPB_8BIT;\n\telse if (access_size == 16)\n\t\trspi->spcmd |= SPCMD_SPB_16BIT;\n\telse\n\t\trspi->spcmd |= SPCMD_SPB_32BIT;\n\n\trspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;\n\n\t/* Resets transfer data length */\n\trspi_write32(rspi, 0, QSPI_SPBMUL0);\n\n\t/* Resets transmit and receive buffer */\n\trspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);\n\t/* Sets buffer to allow normal operation */\n\trspi_write8(rspi, 0x00, QSPI_SPBFCR);\n\n\t/* Resets sequencer */\n\trspi_write8(rspi, 0, RSPI_SPSCR);\n\trspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);\n\n\t/* Sets RSPI mode */\n\trspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);\n\n\treturn 0;\n}",
        "static int rt1719_init_attach_state(struct rt1719_data *data)\n{\n\tu32 conn_info, irq_clear;\n\tu16 conn_stat;\n\tint ret;": "static int rt1719_init_attach_state(struct rt1719_data *data)\n{\n\tu32 conn_info, irq_clear;\n\tu16 conn_stat;\n\tint ret;\n\n\tirq_clear = RT1719_INT_DRSW_ACCEPT | RT1719_INT_RX_SRCCAP |\n\t\t    RT1719_INT_VBUS_DCT | RT1719_INT_VBUS_PRESENT |\n\t\t    RT1719_INT_PE_SNK_RDY;\n\n\tret = rt1719_read32(data, RT1719_REG_POLICYINFO, &conn_info);\n\tret |= rt1719_read16(data, RT1719_REG_STATS, &conn_stat);\n\tret |= rt1719_write32(data, RT1719_REG_EVENTS, irq_clear);\n\tif (ret)\n\t\treturn ret;\n\n\tdata->conn_info = conn_info;\n\tdata->conn_stat = conn_stat;\n\n\tif (conn_info & RT1719_ATTACHDEV_MASK)\n\t\trt1719_attach(data);\n\n\tif (conn_info & RT1719_PE_EXP_CONTRACT) {\n\t\trt1719_update_source_pdos(data);\n\t\trt1719_update_pwr_opmode(data);\n\t}\n\n\treturn 0;\n}",
        "static void vm_map_ram_tags(struct kunit *test)\n{\n\tchar *p_ptr, *v_ptr;\n\tstruct page *page;\n": "static void vm_map_ram_tags(struct kunit *test)\n{\n\tchar *p_ptr, *v_ptr;\n\tstruct page *page;\n\n\t/*\n\t * This test is specifically crafted for the software tag-based mode,\n\t * the only tag-based mode that poisons vm_map_ram mappings.\n\t */\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_SW_TAGS);\n\n\tpage = alloc_pages(GFP_KERNEL, 1);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, page);\n\tp_ptr = page_address(page);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, p_ptr);\n\n\tv_ptr = vm_map_ram(&page, 1, -1);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, v_ptr);\n\n\tKUNIT_EXPECT_GE(test, (u8)get_tag(v_ptr), (u8)KASAN_TAG_MIN);\n\tKUNIT_EXPECT_LT(test, (u8)get_tag(v_ptr), (u8)KASAN_TAG_KERNEL);\n\n\t/* Make sure that in-bounds accesses through both pointers work. */\n\t*p_ptr = 0;\n\t*v_ptr = 0;\n\n\tvm_unmap_ram(v_ptr, 1);\n\tfree_pages((unsigned long)p_ptr, 1);\n}",
        "static unsigned long calibrate_delay_converge(void)\n{\n\t/* First stage - slowly accelerate to find initial bounds */\n\tunsigned long lpj, lpj_base, ticks, loopadd, loopadd_base, chop_limit;\n\tint trials = 0, band = 0, trial_in_band = 0;": "static unsigned long calibrate_delay_converge(void)\n{\n\t/* First stage - slowly accelerate to find initial bounds */\n\tunsigned long lpj, lpj_base, ticks, loopadd, loopadd_base, chop_limit;\n\tint trials = 0, band = 0, trial_in_band = 0;\n\n\tlpj = (1<<12);\n\n\t/* wait for \"start of\" clock tick */\n\tticks = jiffies;\n\twhile (ticks == jiffies)\n\t\t; /* nothing */\n\t/* Go .. */\n\tticks = jiffies;\n\tdo {\n\t\tif (++trial_in_band == (1<<band)) {\n\t\t\t++band;\n\t\t\ttrial_in_band = 0;\n\t\t}\n\t\t__delay(lpj * band);\n\t\ttrials += band;\n\t} while (ticks == jiffies);\n\t/*\n\t * We overshot, so retreat to a clear underestimate. Then estimate\n\t * the largest likely undershoot. This defines our chop bounds.\n\t */\n\ttrials -= band;\n\tloopadd_base = lpj * band;\n\tlpj_base = lpj * trials;\n\nrecalibrate:\n\tlpj = lpj_base;\n\tloopadd = loopadd_base;\n\n\t/*\n\t * Do a binary approximation to get lpj set to\n\t * equal one clock (up to LPS_PREC bits)\n\t */\n\tchop_limit = lpj >> LPS_PREC;\n\twhile (loopadd > chop_limit) {\n\t\tlpj += loopadd;\n\t\tticks = jiffies;\n\t\twhile (ticks == jiffies)\n\t\t\t; /* nothing */\n\t\tticks = jiffies;\n\t\t__delay(lpj);\n\t\tif (jiffies != ticks)\t/* longer than 1 tick */\n\t\t\tlpj -= loopadd;\n\t\tloopadd >>= 1;\n\t}\n\t/*\n\t * If we incremented every single time possible, presume we've\n\t * massively underestimated initially, and retry with a higher\n\t * start, and larger range. (Only seen on x86_64, due to SMIs)\n\t */\n\tif (lpj + loopadd * 2 == lpj_base + loopadd_base * 2) {\n\t\tlpj_base = lpj;\n\t\tloopadd_base <<= 2;\n\t\tgoto recalibrate;\n\t}\n\n\treturn lpj;\n}",
        "static void copy_image_block_Y(const int *src, unsigned char *dst, unsigned int bytes_per_line, unsigned int scalebits)\n{\n#if UNROLL_LOOP_FOR_COPY\n\tconst unsigned char *cm = pwc_crop_table+MAX_OUTER_CROP_VALUE;\n\tconst int *c = src;": "static void copy_image_block_Y(const int *src, unsigned char *dst, unsigned int bytes_per_line, unsigned int scalebits)\n{\n#if UNROLL_LOOP_FOR_COPY\n\tconst unsigned char *cm = pwc_crop_table+MAX_OUTER_CROP_VALUE;\n\tconst int *c = src;\n\tunsigned char *d = dst;\n\n\t*d++ = cm[c[0] >> scalebits];\n\t*d++ = cm[c[1] >> scalebits];\n\t*d++ = cm[c[2] >> scalebits];\n\t*d++ = cm[c[3] >> scalebits];\n\n\td = dst + bytes_per_line;\n\t*d++ = cm[c[4] >> scalebits];\n\t*d++ = cm[c[5] >> scalebits];\n\t*d++ = cm[c[6] >> scalebits];\n\t*d++ = cm[c[7] >> scalebits];\n\n\td = dst + bytes_per_line*2;\n\t*d++ = cm[c[8] >> scalebits];\n\t*d++ = cm[c[9] >> scalebits];\n\t*d++ = cm[c[10] >> scalebits];\n\t*d++ = cm[c[11] >> scalebits];\n\n\td = dst + bytes_per_line*3;\n\t*d++ = cm[c[12] >> scalebits];\n\t*d++ = cm[c[13] >> scalebits];\n\t*d++ = cm[c[14] >> scalebits];\n\t*d++ = cm[c[15] >> scalebits];\n#else\n\tint i;\n\tconst int *c = src;\n\tunsigned char *d = dst;\n\tfor (i = 0; i < 4; i++, c++)\n\t\t*d++ = CLAMP((*c) >> scalebits);\n\n\td = dst + bytes_per_line;\n\tfor (i = 0; i < 4; i++, c++)\n\t\t*d++ = CLAMP((*c) >> scalebits);\n\n\td = dst + bytes_per_line*2;\n\tfor (i = 0; i < 4; i++, c++)\n\t\t*d++ = CLAMP((*c) >> scalebits);\n\n\td = dst + bytes_per_line*3;\n\tfor (i = 0; i < 4; i++, c++)\n\t\t*d++ = CLAMP((*c) >> scalebits);\n#endif\n}",
        "static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)\n{\n\t/* This is only required for 8073A1, version 102 only */\n\tu16 val;\n": "static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)\n{\n\t/* This is only required for 8073A1, version 102 only */\n\tu16 val;\n\n\t/* Read 8073 HW revision*/\n\tbnx2x_cl45_read(bp, phy,\n\t\t\tMDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_8073_CHIP_REV, &val);\n\n\tif (val != 1) {\n\t\t/* No need to workaround in 8073 A1 */\n\t\treturn 0;\n\t}\n\n\tbnx2x_cl45_read(bp, phy,\n\t\t\tMDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_ROM_VER2, &val);\n\n\t/* SNR should be applied only for version 0x102 */\n\tif (val != 0x102)\n\t\treturn 0;\n\n\treturn 1;\n}",
        "static bool delay_autosuspend(struct r8152 *tp)\n{\n\tbool sw_linking = !!netif_carrier_ok(tp->netdev);\n\tbool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);\n": "static bool delay_autosuspend(struct r8152 *tp)\n{\n\tbool sw_linking = !!netif_carrier_ok(tp->netdev);\n\tbool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);\n\n\t/* This means a linking change occurs and the driver doesn't detect it,\n\t * yet. If the driver has disabled tx/rx and hw is linking on, the\n\t * device wouldn't wake up by receiving any packet.\n\t */\n\tif (work_busy(&tp->schedule.work) || sw_linking != hw_linking)\n\t\treturn true;\n\n\t/* If the linking down is occurred by nway, the device may miss the\n\t * linking change event. And it wouldn't wake when linking on.\n\t */\n\tif (!sw_linking && tp->rtl_ops.in_nway(tp))\n\t\treturn true;\n\telse if (!skb_queue_empty(&tp->tx_queue))\n\t\treturn true;\n\telse\n\t\treturn false;\n}",
        "static int drbd_do_auth(struct drbd_connection *connection)\n{\n\tstruct drbd_socket *sock;\n\tchar my_challenge[CHALLENGE_LEN];  /* 64 Bytes... */\n\tchar *response = NULL;": "static int drbd_do_auth(struct drbd_connection *connection)\n{\n\tstruct drbd_socket *sock;\n\tchar my_challenge[CHALLENGE_LEN];  /* 64 Bytes... */\n\tchar *response = NULL;\n\tchar *right_response = NULL;\n\tchar *peers_ch = NULL;\n\tunsigned int key_len;\n\tchar secret[SHARED_SECRET_MAX]; /* 64 byte */\n\tunsigned int resp_size;\n\tstruct shash_desc *desc;\n\tstruct packet_info pi;\n\tstruct net_conf *nc;\n\tint err, rv;\n\n\t/* FIXME: Put the challenge/response into the preallocated socket buffer.  */\n\n\trcu_read_lock();\n\tnc = rcu_dereference(connection->net_conf);\n\tkey_len = strlen(nc->shared_secret);\n\tmemcpy(secret, nc->shared_secret, key_len);\n\trcu_read_unlock();\n\n\tdesc = kmalloc(sizeof(struct shash_desc) +\n\t\t       crypto_shash_descsize(connection->cram_hmac_tfm),\n\t\t       GFP_KERNEL);\n\tif (!desc) {\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\tdesc->tfm = connection->cram_hmac_tfm;\n\n\trv = crypto_shash_setkey(connection->cram_hmac_tfm, (u8 *)secret, key_len);\n\tif (rv) {\n\t\tdrbd_err(connection, \"crypto_shash_setkey() failed with %d\\n\", rv);\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\tget_random_bytes(my_challenge, CHALLENGE_LEN);\n\n\tsock = &connection->data;\n\tif (!conn_prepare_command(connection, sock)) {\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\trv = !conn_send_command(connection, sock, P_AUTH_CHALLENGE, 0,\n\t\t\t\tmy_challenge, CHALLENGE_LEN);\n\tif (!rv)\n\t\tgoto fail;\n\n\terr = drbd_recv_header(connection, &pi);\n\tif (err) {\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\n\tif (pi.cmd != P_AUTH_CHALLENGE) {\n\t\tdrbd_err(connection, \"expected AuthChallenge packet, received: %s (0x%04x)\\n\",\n\t\t\t cmdname(pi.cmd), pi.cmd);\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\tif (pi.size > CHALLENGE_LEN * 2) {\n\t\tdrbd_err(connection, \"expected AuthChallenge payload too big.\\n\");\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\tif (pi.size < CHALLENGE_LEN) {\n\t\tdrbd_err(connection, \"AuthChallenge payload too small.\\n\");\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\tpeers_ch = kmalloc(pi.size, GFP_NOIO);\n\tif (!peers_ch) {\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\terr = drbd_recv_all_warn(connection, peers_ch, pi.size);\n\tif (err) {\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\n\tif (!memcmp(my_challenge, peers_ch, CHALLENGE_LEN)) {\n\t\tdrbd_err(connection, \"Peer presented the same challenge!\\n\");\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\tresp_size = crypto_shash_digestsize(connection->cram_hmac_tfm);\n\tresponse = kmalloc(resp_size, GFP_NOIO);\n\tif (!response) {\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\trv = crypto_shash_digest(desc, peers_ch, pi.size, response);\n\tif (rv) {\n\t\tdrbd_err(connection, \"crypto_hash_digest() failed with %d\\n\", rv);\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\tif (!conn_prepare_command(connection, sock)) {\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\trv = !conn_send_command(connection, sock, P_AUTH_RESPONSE, 0,\n\t\t\t\tresponse, resp_size);\n\tif (!rv)\n\t\tgoto fail;\n\n\terr = drbd_recv_header(connection, &pi);\n\tif (err) {\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\n\tif (pi.cmd != P_AUTH_RESPONSE) {\n\t\tdrbd_err(connection, \"expected AuthResponse packet, received: %s (0x%04x)\\n\",\n\t\t\t cmdname(pi.cmd), pi.cmd);\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\n\tif (pi.size != resp_size) {\n\t\tdrbd_err(connection, \"expected AuthResponse payload of wrong size\\n\");\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\n\terr = drbd_recv_all_warn(connection, response , resp_size);\n\tif (err) {\n\t\trv = 0;\n\t\tgoto fail;\n\t}\n\n\tright_response = kmalloc(resp_size, GFP_NOIO);\n\tif (!right_response) {\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\trv = crypto_shash_digest(desc, my_challenge, CHALLENGE_LEN,\n\t\t\t\t right_response);\n\tif (rv) {\n\t\tdrbd_err(connection, \"crypto_hash_digest() failed with %d\\n\", rv);\n\t\trv = -1;\n\t\tgoto fail;\n\t}\n\n\trv = !memcmp(response, right_response, resp_size);\n\n\tif (rv)\n\t\tdrbd_info(connection, \"Peer authenticated using %d bytes HMAC\\n\",\n\t\t     resp_size);\n\telse\n\t\trv = -1;\n\n fail:\n\tkfree(peers_ch);\n\tkfree(response);\n\tkfree(right_response);\n\tif (desc) {\n\t\tshash_desc_zero(desc);\n\t\tkfree(desc);\n\t}\n\n\treturn rv;\n}",
        "static void spi_nor_init_default_params(struct spi_nor *nor)\n{\n\tstruct spi_nor_flash_parameter *params = nor->params;\n\tconst struct flash_info *info = nor->info;\n\tstruct device_node *np = spi_nor_get_flash_node(nor);": "static void spi_nor_init_default_params(struct spi_nor *nor)\n{\n\tstruct spi_nor_flash_parameter *params = nor->params;\n\tconst struct flash_info *info = nor->info;\n\tstruct device_node *np = spi_nor_get_flash_node(nor);\n\n\tparams->quad_enable = spi_nor_sr2_bit1_quad_enable;\n\tparams->set_4byte_addr_mode = spansion_set_4byte_addr_mode;\n\tparams->otp.org = &info->otp_org;\n\n\t/* Default to 16-bit Write Status (01h) Command */\n\tnor->flags |= SNOR_F_HAS_16BIT_SR;\n\n\t/* Set SPI NOR sizes. */\n\tparams->writesize = 1;\n\tparams->size = (u64)info->sector_size * info->n_sectors;\n\tparams->page_size = info->page_size;\n\n\tif (!(info->flags & SPI_NOR_NO_FR)) {\n\t\t/* Default to Fast Read for DT and non-DT platform devices. */\n\t\tparams->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;\n\n\t\t/* Mask out Fast Read if not requested at DT instantiation. */\n\t\tif (np && !of_property_read_bool(np, \"m25p,fast-read\"))\n\t\t\tparams->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;\n\t}\n\n\t/* (Fast) Read settings. */\n\tparams->hwcaps.mask |= SNOR_HWCAPS_READ;\n\tspi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],\n\t\t\t\t  0, 0, SPINOR_OP_READ,\n\t\t\t\t  SNOR_PROTO_1_1_1);\n\n\tif (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)\n\t\tspi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],\n\t\t\t\t\t  0, 8, SPINOR_OP_READ_FAST,\n\t\t\t\t\t  SNOR_PROTO_1_1_1);\n\t/* Page Program settings. */\n\tparams->hwcaps.mask |= SNOR_HWCAPS_PP;\n\tspi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],\n\t\t\t\tSPINOR_OP_PP, SNOR_PROTO_1_1_1);\n}",
        "static int __init crash_notes_memory_init(void)\n{\n\t/* Allocate memory for saving cpu registers. */\n\tsize_t size, align;\n": "static int __init crash_notes_memory_init(void)\n{\n\t/* Allocate memory for saving cpu registers. */\n\tsize_t size, align;\n\n\t/*\n\t * crash_notes could be allocated across 2 vmalloc pages when percpu\n\t * is vmalloc based . vmalloc doesn't guarantee 2 continuous vmalloc\n\t * pages are also on 2 continuous physical pages. In this case the\n\t * 2nd part of crash_notes in 2nd page could be lost since only the\n\t * starting address and size of crash_notes are exported through sysfs.\n\t * Here round up the size of crash_notes to the nearest power of two\n\t * and pass it to __alloc_percpu as align value. This can make sure\n\t * crash_notes is allocated inside one physical page.\n\t */\n\tsize = sizeof(note_buf_t);\n\talign = min(roundup_pow_of_two(sizeof(note_buf_t)), PAGE_SIZE);\n\n\t/*\n\t * Break compile if size is bigger than PAGE_SIZE since crash_notes\n\t * definitely will be in 2 pages with that.\n\t */\n\tBUILD_BUG_ON(size > PAGE_SIZE);\n\n\tcrash_notes = __alloc_percpu(size, align);\n\tif (!crash_notes) {\n\t\tpr_warn(\"Memory allocation for saving cpu register states failed\\n\");\n\t\treturn -ENOMEM;\n\t}\n\treturn 0;\n}",
        "static int cx24110_set_fec(struct cx24110_state *state, enum fe_code_rate fec)\n{\n\tstatic const int rate[FEC_AUTO] = {-1,    1,    2,    3,    5,    7, -1};\n\tstatic const int g1[FEC_AUTO]   = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};\n\tstatic const int g2[FEC_AUTO]   = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};": "static int cx24110_set_fec(struct cx24110_state *state, enum fe_code_rate fec)\n{\n\tstatic const int rate[FEC_AUTO] = {-1,    1,    2,    3,    5,    7, -1};\n\tstatic const int g1[FEC_AUTO]   = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};\n\tstatic const int g2[FEC_AUTO]   = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};\n\n\t/* Well, the AutoAcq engine of the cx24106 and 24110 automatically\n\t   searches all enabled viterbi rates, and can handle non-standard\n\t   rates as well. */\n\n\tif (fec > FEC_AUTO)\n\t\tfec = FEC_AUTO;\n\n\tif (fec == FEC_AUTO) { /* (re-)establish AutoAcq behaviour */\n\t\tcx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);\n\t\t/* clear AcqVitDis bit */\n\t\tcx24110_writereg(state, 0x18, 0xae);\n\t\t/* allow all DVB standard code rates */\n\t\tcx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);\n\t\t/* set nominal Viterbi rate 3/4 */\n\t\tcx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);\n\t\t/* set current Viterbi rate 3/4 */\n\t\tcx24110_writereg(state, 0x1a, 0x05);\n\t\tcx24110_writereg(state, 0x1b, 0x06);\n\t\t/* set the puncture registers for code rate 3/4 */\n\t\treturn 0;\n\t} else {\n\t\tcx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);\n\t\t/* set AcqVitDis bit */\n\t\tif (rate[fec] < 0)\n\t\t\treturn -EINVAL;\n\n\t\tcx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);\n\t\t/* set nominal Viterbi rate */\n\t\tcx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);\n\t\t/* set current Viterbi rate */\n\t\tcx24110_writereg(state, 0x1a, g1[fec]);\n\t\tcx24110_writereg(state, 0x1b, g2[fec]);\n\t\t/* not sure if this is the right way: I always used AutoAcq mode */\n\t}\n\treturn 0;\n}",
        "static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data_size)\n{\n\tstruct prctl_mm_map prctl_map = { .exe_fd = (u32)-1, };\n\tunsigned long user_auxv[AT_VECTOR_SIZE];\n\tstruct mm_struct *mm = current->mm;": "static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data_size)\n{\n\tstruct prctl_mm_map prctl_map = { .exe_fd = (u32)-1, };\n\tunsigned long user_auxv[AT_VECTOR_SIZE];\n\tstruct mm_struct *mm = current->mm;\n\tint error;\n\n\tBUILD_BUG_ON(sizeof(user_auxv) != sizeof(mm->saved_auxv));\n\tBUILD_BUG_ON(sizeof(struct prctl_mm_map) > 256);\n\n\tif (opt == PR_SET_MM_MAP_SIZE)\n\t\treturn put_user((unsigned int)sizeof(prctl_map),\n\t\t\t\t(unsigned int __user *)addr);\n\n\tif (data_size != sizeof(prctl_map))\n\t\treturn -EINVAL;\n\n\tif (copy_from_user(&prctl_map, addr, sizeof(prctl_map)))\n\t\treturn -EFAULT;\n\n\terror = validate_prctl_map_addr(&prctl_map);\n\tif (error)\n\t\treturn error;\n\n\tif (prctl_map.auxv_size) {\n\t\t/*\n\t\t * Someone is trying to cheat the auxv vector.\n\t\t */\n\t\tif (!prctl_map.auxv ||\n\t\t\t\tprctl_map.auxv_size > sizeof(mm->saved_auxv))\n\t\t\treturn -EINVAL;\n\n\t\tmemset(user_auxv, 0, sizeof(user_auxv));\n\t\tif (copy_from_user(user_auxv,\n\t\t\t\t   (const void __user *)prctl_map.auxv,\n\t\t\t\t   prctl_map.auxv_size))\n\t\t\treturn -EFAULT;\n\n\t\t/* Last entry must be AT_NULL as specification requires */\n\t\tuser_auxv[AT_VECTOR_SIZE - 2] = AT_NULL;\n\t\tuser_auxv[AT_VECTOR_SIZE - 1] = AT_NULL;\n\t}\n\n\tif (prctl_map.exe_fd != (u32)-1) {\n\t\t/*\n\t\t * Check if the current user is checkpoint/restore capable.\n\t\t * At the time of this writing, it checks for CAP_SYS_ADMIN\n\t\t * or CAP_CHECKPOINT_RESTORE.\n\t\t * Note that a user with access to ptrace can masquerade an\n\t\t * arbitrary program as any executable, even setuid ones.\n\t\t * This may have implications in the tomoyo subsystem.\n\t\t */\n\t\tif (!checkpoint_restore_ns_capable(current_user_ns()))\n\t\t\treturn -EPERM;\n\n\t\terror = prctl_set_mm_exe_file(mm, prctl_map.exe_fd);\n\t\tif (error)\n\t\t\treturn error;\n\t}\n\n\t/*\n\t * arg_lock protects concurrent updates but we still need mmap_lock for\n\t * read to exclude races with sys_brk.\n\t */\n\tmmap_read_lock(mm);\n\n\t/*\n\t * We don't validate if these members are pointing to\n\t * real present VMAs because application may have correspond\n\t * VMAs already unmapped and kernel uses these members for statistics\n\t * output in procfs mostly, except\n\t *\n\t *  - @start_brk/@brk which are used in do_brk_flags but kernel lookups\n\t *    for VMAs when updating these members so anything wrong written\n\t *    here cause kernel to swear at userspace program but won't lead\n\t *    to any problem in kernel itself\n\t */\n\n\tspin_lock(&mm->arg_lock);\n\tmm->start_code\t= prctl_map.start_code;\n\tmm->end_code\t= prctl_map.end_code;\n\tmm->start_data\t= prctl_map.start_data;\n\tmm->end_data\t= prctl_map.end_data;\n\tmm->start_brk\t= prctl_map.start_brk;\n\tmm->brk\t\t= prctl_map.brk;\n\tmm->start_stack\t= prctl_map.start_stack;\n\tmm->arg_start\t= prctl_map.arg_start;\n\tmm->arg_end\t= prctl_map.arg_end;\n\tmm->env_start\t= prctl_map.env_start;\n\tmm->env_end\t= prctl_map.env_end;\n\tspin_unlock(&mm->arg_lock);\n\n\t/*\n\t * Note this update of @saved_auxv is lockless thus\n\t * if someone reads this member in procfs while we're\n\t * updating -- it may get partly updated results. It's\n\t * known and acceptable trade off: we leave it as is to\n\t * not introduce additional locks here making the kernel\n\t * more complex.\n\t */\n\tif (prctl_map.auxv_size)\n\t\tmemcpy(mm->saved_auxv, user_auxv, sizeof(user_auxv));\n\n\tmmap_read_unlock(mm);\n\treturn 0;\n}",
        "static struct xsk_umem_info *xsk_configure_umem(void *buffer, u64 size)\n{\n\tstruct xsk_umem_info *umem;\n\tstruct xsk_umem_config cfg = {\n\t\t/* We recommend that you set the fill ring size >= HW RX ring size +": "static struct xsk_umem_info *xsk_configure_umem(void *buffer, u64 size)\n{\n\tstruct xsk_umem_info *umem;\n\tstruct xsk_umem_config cfg = {\n\t\t/* We recommend that you set the fill ring size >= HW RX ring size +\n\t\t * AF_XDP RX ring size. Make sure you fill up the fill ring\n\t\t * with buffers at regular intervals, and you will with this setting\n\t\t * avoid allocation failures in the driver. These are usually quite\n\t\t * expensive since drivers have not been written to assume that\n\t\t * allocation failures are common. For regular sockets, kernel\n\t\t * allocated memory is used that only runs out in OOM situations\n\t\t * that should be rare.\n\t\t */\n\t\t.fill_size = XSK_RING_PROD__DEFAULT_NUM_DESCS * 2,\n\t\t.comp_size = XSK_RING_CONS__DEFAULT_NUM_DESCS,\n\t\t.frame_size = opt_xsk_frame_size,\n\t\t.frame_headroom = XSK_UMEM__DEFAULT_FRAME_HEADROOM,\n\t\t.flags = opt_umem_flags\n\t};\n\tint ret;\n\n\tumem = calloc(1, sizeof(*umem));\n\tif (!umem)\n\t\texit_with_error(errno);\n\n\tret = xsk_umem__create(&umem->umem, buffer, size, &umem->fq, &umem->cq,\n\t\t\t       &cfg);\n\tif (ret)\n\t\texit_with_error(-ret);\n\n\tumem->buffer = buffer;\n\treturn umem;\n}",
        "static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)\n{\n\tu32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;\n\tu64 tsc;\n\tstruct hte_ts_data el;": "static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)\n{\n\tu32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;\n\tu64 tsc;\n\tstruct hte_ts_data el;\n\n\twhile ((tegra_hte_readl(gs, HTE_TESTATUS) >>\n\t\tHTE_TESTATUS_OCCUPANCY_SHIFT) &\n\t\tHTE_TESTATUS_OCCUPANCY_MASK) {\n\t\ttsh = tegra_hte_readl(gs, HTE_TETSCH);\n\t\ttsl = tegra_hte_readl(gs, HTE_TETSCL);\n\t\ttsc = (((u64)tsh << 32) | tsl);\n\n\t\tsrc = tegra_hte_readl(gs, HTE_TESRC);\n\t\tslice = (src >> HTE_TESRC_SLICE_SHIFT) &\n\t\t\t    HTE_TESRC_SLICE_DEFAULT_MASK;\n\n\t\tpv = tegra_hte_readl(gs, HTE_TEPCV);\n\t\tcv = tegra_hte_readl(gs, HTE_TECCV);\n\t\tacv = pv ^ cv;\n\t\twhile (acv) {\n\t\t\tbit_index = __builtin_ctz(acv);\n\t\t\tline_id = bit_index + (slice << 5);\n\t\t\tel.tsc = tsc << HTE_TS_NS_SHIFT;\n\t\t\tel.raw_level = tegra_hte_get_level(gs, line_id);\n\t\t\thte_push_ts_ns(gs->chip, line_id, &el);\n\t\t\tacv &= ~BIT(bit_index);\n\t\t}\n\t\ttegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP);\n\t}\n}",
        "static void usage(void)\n{\n\tprintf(\"slabinfo 4/15/2011. (c) 2007 sgi/(c) 2011 Linux Foundation.\\n\\n\"\n\t\t\"slabinfo [-aABDefhilLnoPrsStTUvXz1] [N=K] [-dafzput] [slab-regexp]\\n\"\n\t\t\"-a|--aliases           Show aliases\\n\"": "static void usage(void)\n{\n\tprintf(\"slabinfo 4/15/2011. (c) 2007 sgi/(c) 2011 Linux Foundation.\\n\\n\"\n\t\t\"slabinfo [-aABDefhilLnoPrsStTUvXz1] [N=K] [-dafzput] [slab-regexp]\\n\"\n\t\t\"-a|--aliases           Show aliases\\n\"\n\t\t\"-A|--activity          Most active slabs first\\n\"\n\t\t\"-B|--Bytes             Show size in bytes\\n\"\n\t\t\"-D|--display-active    Switch line format to activity\\n\"\n\t\t\"-e|--empty             Show empty slabs\\n\"\n\t\t\"-f|--first-alias       Show first alias\\n\"\n\t\t\"-h|--help              Show usage information\\n\"\n\t\t\"-i|--inverted          Inverted list\\n\"\n\t\t\"-l|--slabs             Show slabs\\n\"\n\t\t\"-L|--Loss              Sort by loss\\n\"\n\t\t\"-n|--numa              Show NUMA information\\n\"\n\t\t\"-N|--lines=K           Show the first K slabs\\n\"\n\t\t\"-o|--ops               Show kmem_cache_ops\\n\"\n\t\t\"-P|--partial\t\tSort by number of partial slabs\\n\"\n\t\t\"-r|--report            Detailed report on single slabs\\n\"\n\t\t\"-s|--shrink            Shrink slabs\\n\"\n\t\t\"-S|--Size              Sort by size\\n\"\n\t\t\"-t|--tracking          Show alloc/free information\\n\"\n\t\t\"-T|--Totals            Show summary information\\n\"\n\t\t\"-U|--Unreclaim         Show unreclaimable slabs only\\n\"\n\t\t\"-v|--validate          Validate slabs\\n\"\n\t\t\"-X|--Xtotals           Show extended summary information\\n\"\n\t\t\"-z|--zero              Include empty slabs\\n\"\n\t\t\"-1|--1ref              Single reference\\n\"\n\n\t\t\"\\n\"\n\t\t\"-d  | --debug          Switch off all debug options\\n\"\n\t\t\"-da | --debug=a        Switch on all debug options (--debug=FZPU)\\n\"\n\n\t\t\"\\n\"\n\t\t\"-d[afzput] | --debug=[afzput]\\n\"\n\t\t\"    f | F              Sanity Checks (SLAB_CONSISTENCY_CHECKS)\\n\"\n\t\t\"    z | Z              Redzoning\\n\"\n\t\t\"    p | P              Poisoning\\n\"\n\t\t\"    u | U              Tracking\\n\"\n\t\t\"    t | T              Tracing\\n\"\n\n\t\t\"\\nSorting options (--Loss, --Size, --Partial) are mutually exclusive\\n\"\n\t);\n}",
        "static void ww_test_edeadlk_normal_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_normal_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\to2.ctx = &t2;\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\n\to2.ctx = NULL;\n\tmutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);\n\tww_mutex_base_unlock(&o2.base);\n\tWWU(&o);\n\n\tww_mutex_lock_slow(&o2, &t);\n}",
        "static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)\n{\n\tint doublespeed = 0;\n\tint i, j, channels, ofs;\n": "static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)\n{\n\tint doublespeed = 0;\n\tint i, j, channels, ofs;\n\n\tif (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)\n\t\tdoublespeed = 1;\n\tchannels = doublespeed ? 14 : 26;\n\tfor (i = 0, j = 0; i < 26; ++i) {\n\t\tif (doublespeed && (i & 4))\n\t\t\tcontinue;\n\t\tofs = HDSP_9652_peakBase - j * 4;\n\t\tif (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))\n\t\t\treturn -EFAULT;\n\t\tofs -= channels * 4;\n\t\tif (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))\n\t\t\treturn -EFAULT;\n\t\tofs -= channels * 4;\n\t\tif (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))\n\t\t\treturn -EFAULT;\n\t\tofs = HDSP_9652_rmsBase + j * 8;\n\t\tif (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,\n\t\t\t\thdsp->iobase + ofs + 4))\n\t\t\treturn -EFAULT;\n\t\tofs += channels * 8;\n\t\tif (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,\n\t\t\t\thdsp->iobase + ofs + 4))\n\t\t\treturn -EFAULT;\n\t\tofs += channels * 8;\n\t\tif (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,\n\t\t\t\thdsp->iobase + ofs + 4))\n\t\t\treturn -EFAULT;\n\t\tj++;\n\t}\n\treturn 0;\n}",
        "static int sps30_serial_show_info(struct sps30_state *state)\n{\n\t/*\n\t * tell device do return serial number and add extra nul byte just in case\n\t * serial number isn't a valid string": "static int sps30_serial_show_info(struct sps30_state *state)\n{\n\t/*\n\t * tell device do return serial number and add extra nul byte just in case\n\t * serial number isn't a valid string\n\t */\n\tunsigned char buf[32 + 1] = { 0x03 };\n\tstruct device *dev = state->dev;\n\tint ret;\n\n\tret = sps30_serial_command(state, SPS30_SERIAL_DEV_INFO, buf, 1, buf, sizeof(buf) - 1);\n\tif (ret < 0)\n\t\treturn ret;\n\tif (ret != sizeof(buf) - 1)\n\t\treturn -EIO;\n\n\tdev_info(dev, \"serial number: %s\\n\", buf);\n\n\tret = sps30_serial_command(state, SPS30_SERIAL_READ_VERSION, NULL, 0, buf, sizeof(buf) - 1);\n\tif (ret < 0)\n\t\treturn ret;\n\tif (ret < 2)\n\t\treturn -EIO;\n\n\tdev_info(dev, \"fw version: %u.%u\\n\", buf[0], buf[1]);\n\n\treturn 0;\n}",
        "static void l1_guest_code(struct vmx_pages *vmx_pages)\n{\n\tunsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];\n\tuint32_t control;\n": "static void l1_guest_code(struct vmx_pages *vmx_pages)\n{\n\tunsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];\n\tuint32_t control;\n\n\t/* check that L1's frequency looks alright before launching L2 */\n\tcheck_tsc_freq(UCHECK_L1);\n\n\tGUEST_ASSERT(prepare_for_vmx_operation(vmx_pages));\n\tGUEST_ASSERT(load_vmcs(vmx_pages));\n\n\t/* prepare the VMCS for L2 execution */\n\tprepare_vmcs(vmx_pages, l2_guest_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]);\n\n\t/* enable TSC offsetting and TSC scaling for L2 */\n\tcontrol = vmreadz(CPU_BASED_VM_EXEC_CONTROL);\n\tcontrol |= CPU_BASED_USE_MSR_BITMAPS | CPU_BASED_USE_TSC_OFFSETTING;\n\tvmwrite(CPU_BASED_VM_EXEC_CONTROL, control);\n\n\tcontrol = vmreadz(SECONDARY_VM_EXEC_CONTROL);\n\tcontrol |= SECONDARY_EXEC_TSC_SCALING;\n\tvmwrite(SECONDARY_VM_EXEC_CONTROL, control);\n\n\tvmwrite(TSC_OFFSET, TSC_OFFSET_L2);\n\tvmwrite(TSC_MULTIPLIER, TSC_MULTIPLIER_L2);\n\tvmwrite(TSC_MULTIPLIER_HIGH, TSC_MULTIPLIER_L2 >> 32);\n\n\t/* launch L2 */\n\tGUEST_ASSERT(!vmlaunch());\n\tGUEST_ASSERT(vmreadz(VM_EXIT_REASON) == EXIT_REASON_VMCALL);\n\n\t/* check that L1's frequency still looks good */\n\tcheck_tsc_freq(UCHECK_L1);\n\n\tGUEST_DONE();\n}",
        "static int write_partial_message_data(struct ceph_connection *con)\n{\n\tstruct ceph_msg *msg = con->out_msg;\n\tstruct ceph_msg_data_cursor *cursor = &msg->cursor;\n\tbool do_datacrc = !ceph_test_opt(from_msgr(con->msgr), NOCRC);": "static int write_partial_message_data(struct ceph_connection *con)\n{\n\tstruct ceph_msg *msg = con->out_msg;\n\tstruct ceph_msg_data_cursor *cursor = &msg->cursor;\n\tbool do_datacrc = !ceph_test_opt(from_msgr(con->msgr), NOCRC);\n\tint more = MSG_MORE | MSG_SENDPAGE_NOTLAST;\n\tu32 crc;\n\n\tdout(\"%s %p msg %p\\n\", __func__, con, msg);\n\n\tif (!msg->num_data_items)\n\t\treturn -EINVAL;\n\n\t/*\n\t * Iterate through each page that contains data to be\n\t * written, and send as much as possible for each.\n\t *\n\t * If we are calculating the data crc (the default), we will\n\t * need to map the page.  If we have no pages, they have\n\t * been revoked, so use the zero page.\n\t */\n\tcrc = do_datacrc ? le32_to_cpu(msg->footer.data_crc) : 0;\n\twhile (cursor->total_resid) {\n\t\tstruct page *page;\n\t\tsize_t page_offset;\n\t\tsize_t length;\n\t\tint ret;\n\n\t\tif (!cursor->resid) {\n\t\t\tceph_msg_data_advance(cursor, 0);\n\t\t\tcontinue;\n\t\t}\n\n\t\tpage = ceph_msg_data_next(cursor, &page_offset, &length, NULL);\n\t\tif (length == cursor->total_resid)\n\t\t\tmore = MSG_MORE;\n\t\tret = ceph_tcp_sendpage(con->sock, page, page_offset, length,\n\t\t\t\t\tmore);\n\t\tif (ret <= 0) {\n\t\t\tif (do_datacrc)\n\t\t\t\tmsg->footer.data_crc = cpu_to_le32(crc);\n\n\t\t\treturn ret;\n\t\t}\n\t\tif (do_datacrc && cursor->need_crc)\n\t\t\tcrc = ceph_crc32c_page(crc, page, page_offset, length);\n\t\tceph_msg_data_advance(cursor, (size_t)ret);\n\t}\n\n\tdout(\"%s %p msg %p done\\n\", __func__, con, msg);\n\n\t/* prepare and queue up footer, too */\n\tif (do_datacrc)\n\t\tmsg->footer.data_crc = cpu_to_le32(crc);\n\telse\n\t\tmsg->footer.flags |= CEPH_MSG_FOOTER_NOCRC;\n\tcon_out_kvec_reset(con);\n\tprepare_write_message_footer(con);\n\n\treturn 1;\t/* must return > 0 to indicate success */\n}",
        "static int pfkey_spdflush(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tstruct km_event c;\n\tint err, err2;": "static int pfkey_spdflush(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tstruct km_event c;\n\tint err, err2;\n\n\terr = xfrm_policy_flush(net, XFRM_POLICY_TYPE_MAIN, true);\n\terr2 = unicast_flush_resp(sk, hdr);\n\tif (err || err2) {\n\t\tif (err == -ESRCH) /* empty table - old silent behavior */\n\t\t\treturn 0;\n\t\treturn err;\n\t}\n\n\tc.data.type = XFRM_POLICY_TYPE_MAIN;\n\tc.event = XFRM_MSG_FLUSHPOLICY;\n\tc.portid = hdr->sadb_msg_pid;\n\tc.seq = hdr->sadb_msg_seq;\n\tc.net = net;\n\tkm_policy_notify(NULL, 0, &c);\n\n\treturn 0;\n}",
        "static int cypress_nor_octal_dtr_en(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;": "static int cypress_nor_octal_dtr_en(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;\n\n\t/* Use 24 dummy cycles for memory array reads. */\n\t*buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;\n\top = (struct spi_mem_op)\n\t\tCYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf);\n\n\tret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);\n\tif (ret)\n\t\treturn ret;\n\n\tnor->read_dummy = 24;\n\n\t/* Set the octal and DTR enable bits. */\n\tbuf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;\n\top = (struct spi_mem_op)\n\t\tCYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf);\n\n\tret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Read flash ID to make sure the switch was successful. */\n\tret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);\n\tif (ret) {\n\t\tdev_dbg(nor->dev, \"error %d reading JEDEC ID after enabling 8D-8D-8D mode\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tif (memcmp(buf, nor->info->id, nor->info->id_len))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static void monitor_exposure(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tu8 exp_acc, bcomp, cmd[8];\n\tint ret, light_exp, dark_exp, very_dark_exp;": "static void monitor_exposure(struct gspca_dev *gspca_dev)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tu8 exp_acc, bcomp, cmd[8];\n\tint ret, light_exp, dark_exp, very_dark_exp;\n\tint old_exposure, new_exposure, framerate;\n\tint setfps = 0, setexp = 0, setflicker = 0;\n\n\t/* get necessary stats and register settings from camera */\n\t/* do_command can't handle this, so do it ourselves */\n\tcmd[0] = CPIA_COMMAND_ReadVPRegs >> 8;\n\tcmd[1] = CPIA_COMMAND_ReadVPRegs & 0xff;\n\tcmd[2] = 30;\n\tcmd[3] = 4;\n\tcmd[4] = 9;\n\tcmd[5] = 8;\n\tcmd[6] = 8;\n\tcmd[7] = 0;\n\tret = cpia_usb_transferCmd(gspca_dev, cmd);\n\tif (ret) {\n\t\tpr_err(\"ReadVPRegs(30,4,9,8) - failed: %d\\n\", ret);\n\t\treturn;\n\t}\n\texp_acc = gspca_dev->usb_buf[0];\n\tbcomp = gspca_dev->usb_buf[1];\n\n\tlight_exp = sd->params.colourParams.brightness +\n\t\t    TC - 50 + EXP_ACC_LIGHT;\n\tif (light_exp > 255)\n\t\tlight_exp = 255;\n\tdark_exp = sd->params.colourParams.brightness +\n\t\t   TC - 50 - EXP_ACC_DARK;\n\tif (dark_exp < 0)\n\t\tdark_exp = 0;\n\tvery_dark_exp = dark_exp / 2;\n\n\told_exposure = sd->params.exposure.coarseExpHi * 256 +\n\t\t       sd->params.exposure.coarseExpLo;\n\n\tif (!sd->params.flickerControl.disabled) {\n\t\t/* Flicker control on */\n\t\tint max_comp = FIRMWARE_VERSION(1, 2) ? MAX_COMP :\n\t\t\t\t\t\t\tHIGH_COMP_102;\n\t\tbcomp += 128;\t/* decode */\n\t\tif (bcomp >= max_comp && exp_acc < dark_exp) {\n\t\t\t/* dark */\n\t\t\tif (exp_acc < very_dark_exp) {\n\t\t\t\t/* very dark */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_VERY_DARK)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status =\n\t\t\t\t\t\tEXPOSURE_VERY_DARK;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* just dark */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_DARK)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status = EXPOSURE_DARK;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t} else if (old_exposure <= LOW_EXP || exp_acc > light_exp) {\n\t\t\t/* light */\n\t\t\tif (old_exposure <= VERY_LOW_EXP) {\n\t\t\t\t/* very light */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_VERY_LIGHT)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status =\n\t\t\t\t\t\tEXPOSURE_VERY_LIGHT;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* just light */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_LIGHT)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status = EXPOSURE_LIGHT;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\t/* not dark or light */\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t}\n\t} else {\n\t\t/* Flicker control off */\n\t\tif (old_exposure >= MAX_EXP && exp_acc < dark_exp) {\n\t\t\t/* dark */\n\t\t\tif (exp_acc < very_dark_exp) {\n\t\t\t\t/* very dark */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_VERY_DARK)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status =\n\t\t\t\t\t\tEXPOSURE_VERY_DARK;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* just dark */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_DARK)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status = EXPOSURE_DARK;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t} else if (old_exposure <= LOW_EXP || exp_acc > light_exp) {\n\t\t\t/* light */\n\t\t\tif (old_exposure <= VERY_LOW_EXP) {\n\t\t\t\t/* very light */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_VERY_LIGHT)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status =\n\t\t\t\t\t\tEXPOSURE_VERY_LIGHT;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* just light */\n\t\t\t\tif (sd->exposure_status == EXPOSURE_LIGHT)\n\t\t\t\t\t++sd->exposure_count;\n\t\t\t\telse {\n\t\t\t\t\tsd->exposure_status = EXPOSURE_LIGHT;\n\t\t\t\t\tsd->exposure_count = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\t/* not dark or light */\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t}\n\t}\n\n\tframerate = atomic_read(&sd->fps);\n\tif (framerate > 30 || framerate < 1)\n\t\tframerate = 1;\n\n\tif (!sd->params.flickerControl.disabled) {\n\t\t/* Flicker control on */\n\t\tif ((sd->exposure_status == EXPOSURE_VERY_DARK ||\n\t\t     sd->exposure_status == EXPOSURE_DARK) &&\n\t\t    sd->exposure_count >= DARK_TIME * framerate &&\n\t\t    sd->params.sensorFps.divisor < 2) {\n\n\t\t\t/* dark for too long */\n\t\t\t++sd->params.sensorFps.divisor;\n\t\t\tsetfps = 1;\n\n\t\t\tsd->params.flickerControl.coarseJump =\n\t\t\t\tflicker_jumps[sd->mainsFreq]\n\t\t\t\t\t     [sd->params.sensorFps.baserate]\n\t\t\t\t\t     [sd->params.sensorFps.divisor];\n\t\t\tsetflicker = 1;\n\n\t\t\tnew_exposure = sd->params.flickerControl.coarseJump-1;\n\t\t\twhile (new_exposure < old_exposure / 2)\n\t\t\t\tnew_exposure +=\n\t\t\t\t\tsd->params.flickerControl.coarseJump;\n\t\t\tsd->params.exposure.coarseExpLo = new_exposure & 0xff;\n\t\t\tsd->params.exposure.coarseExpHi = new_exposure >> 8;\n\t\t\tsetexp = 1;\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t\tgspca_dbg(gspca_dev, D_CONF, \"Automatically decreasing sensor_fps\\n\");\n\n\t\t} else if ((sd->exposure_status == EXPOSURE_VERY_LIGHT ||\n\t\t\t    sd->exposure_status == EXPOSURE_LIGHT) &&\n\t\t\t   sd->exposure_count >= LIGHT_TIME * framerate &&\n\t\t\t   sd->params.sensorFps.divisor > 0) {\n\n\t\t\t/* light for too long */\n\t\t\tint max_exp = FIRMWARE_VERSION(1, 2) ? MAX_EXP_102 :\n\t\t\t\t\t\t\t       MAX_EXP;\n\t\t\t--sd->params.sensorFps.divisor;\n\t\t\tsetfps = 1;\n\n\t\t\tsd->params.flickerControl.coarseJump =\n\t\t\t\tflicker_jumps[sd->mainsFreq]\n\t\t\t\t\t     [sd->params.sensorFps.baserate]\n\t\t\t\t\t     [sd->params.sensorFps.divisor];\n\t\t\tsetflicker = 1;\n\n\t\t\tnew_exposure = sd->params.flickerControl.coarseJump-1;\n\t\t\twhile (new_exposure < 2 * old_exposure &&\n\t\t\t       new_exposure +\n\t\t\t       sd->params.flickerControl.coarseJump < max_exp)\n\t\t\t\tnew_exposure +=\n\t\t\t\t\tsd->params.flickerControl.coarseJump;\n\t\t\tsd->params.exposure.coarseExpLo = new_exposure & 0xff;\n\t\t\tsd->params.exposure.coarseExpHi = new_exposure >> 8;\n\t\t\tsetexp = 1;\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t\tgspca_dbg(gspca_dev, D_CONF, \"Automatically increasing sensor_fps\\n\");\n\t\t}\n\t} else {\n\t\t/* Flicker control off */\n\t\tif ((sd->exposure_status == EXPOSURE_VERY_DARK ||\n\t\t     sd->exposure_status == EXPOSURE_DARK) &&\n\t\t    sd->exposure_count >= DARK_TIME * framerate &&\n\t\t    sd->params.sensorFps.divisor < 2) {\n\n\t\t\t/* dark for too long */\n\t\t\t++sd->params.sensorFps.divisor;\n\t\t\tsetfps = 1;\n\n\t\t\tif (sd->params.exposure.gain > 0) {\n\t\t\t\t--sd->params.exposure.gain;\n\t\t\t\tsetexp = 1;\n\t\t\t}\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t\tgspca_dbg(gspca_dev, D_CONF, \"Automatically decreasing sensor_fps\\n\");\n\n\t\t} else if ((sd->exposure_status == EXPOSURE_VERY_LIGHT ||\n\t\t\t    sd->exposure_status == EXPOSURE_LIGHT) &&\n\t\t\t   sd->exposure_count >= LIGHT_TIME * framerate &&\n\t\t\t   sd->params.sensorFps.divisor > 0) {\n\n\t\t\t/* light for too long */\n\t\t\t--sd->params.sensorFps.divisor;\n\t\t\tsetfps = 1;\n\n\t\t\tif (sd->params.exposure.gain <\n\t\t\t    sd->params.exposure.gainMode - 1) {\n\t\t\t\t++sd->params.exposure.gain;\n\t\t\t\tsetexp = 1;\n\t\t\t}\n\t\t\tsd->exposure_status = EXPOSURE_NORMAL;\n\t\t\tgspca_dbg(gspca_dev, D_CONF, \"Automatically increasing sensor_fps\\n\");\n\t\t}\n\t}\n\n\tif (setexp)\n\t\tcommand_setexposure(gspca_dev);\n\n\tif (setfps)\n\t\tcommand_setsensorfps(gspca_dev);\n\n\tif (setflicker)\n\t\tcommand_setflickerctrl(gspca_dev);\n}",
        "static int vdec_hevc_stop(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\tstruct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;\n": "static int vdec_hevc_stop(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\tstruct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;\n\n\t/* Disable interrupt */\n\tamvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 0);\n\t/* Disable firmware processor */\n\tamvdec_write_dos(core, HEVC_MPSR, 0);\n\n\tif (sess->priv)\n\t\tcodec_ops->stop(sess);\n\n\t/* Enable VDEC_HEVC Isolation */\n\tif (core->platform->revision == VDEC_REVISION_SM1)\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,\n\t\t\t\t   GEN_PWR_VDEC_HEVC_SM1,\n\t\t\t\t   GEN_PWR_VDEC_HEVC_SM1);\n\telse\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,\n\t\t\t\t   0xc00, 0xc00);\n\n\t/* VDEC_HEVC Memories */\n\tamvdec_write_dos(core, DOS_MEM_PD_HEVC, 0xffffffffUL);\n\n\tif (core->platform->revision == VDEC_REVISION_SM1)\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,\n\t\t\t\t   GEN_PWR_VDEC_HEVC_SM1,\n\t\t\t\t   GEN_PWR_VDEC_HEVC_SM1);\n\telse\n\t\tregmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,\n\t\t\t\t   GEN_PWR_VDEC_HEVC, GEN_PWR_VDEC_HEVC);\n\n\tclk_disable_unprepare(core->vdec_hevc_clk);\n\tif (core->platform->revision == VDEC_REVISION_G12A ||\n\t    core->platform->revision == VDEC_REVISION_SM1)\n\t\tclk_disable_unprepare(core->vdec_hevcf_clk);\n\n\treturn 0;\n}",
        "static int vt_unbind(struct con_driver *con)\n{\n\tconst struct consw *csw = NULL;\n\tint i, more = 1, first = -1, last = -1, deflt = 0;\n\tint ret;": "static int vt_unbind(struct con_driver *con)\n{\n\tconst struct consw *csw = NULL;\n\tint i, more = 1, first = -1, last = -1, deflt = 0;\n\tint ret;\n\n \tif (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE))\n\t\tgoto err;\n\n\tcsw = con->con;\n\n\twhile (more) {\n\t\tmore = 0;\n\n\t\tfor (i = con->first; i <= con->last; i++) {\n\t\t\tif (con_driver_map[i] == csw) {\n\t\t\t\tif (first == -1)\n\t\t\t\t\tfirst = i;\n\t\t\t\tlast = i;\n\t\t\t\tmore = 1;\n\t\t\t} else if (first != -1)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (first == 0 && last == MAX_NR_CONSOLES -1)\n\t\t\tdeflt = 1;\n\n\t\tif (first != -1) {\n\t\t\tret = do_unbind_con_driver(csw, first, last, deflt);\n\t\t\tif (ret != 0)\n\t\t\t\treturn ret;\n\t\t}\n\n\t\tfirst = -1;\n\t\tlast = -1;\n\t\tdeflt = 0;\n\t}\n\nerr:\n\treturn 0;\n}",
        "static int select_idle_sibling(struct task_struct *p, int prev, int target)\n{\n\tbool has_idle_core = false;\n\tstruct sched_domain *sd;\n\tunsigned long task_util;": "static int select_idle_sibling(struct task_struct *p, int prev, int target)\n{\n\tbool has_idle_core = false;\n\tstruct sched_domain *sd;\n\tunsigned long task_util;\n\tint i, recent_used_cpu;\n\n\t/*\n\t * On asymmetric system, update task utilization because we will check\n\t * that the task fits with cpu's capacity.\n\t */\n\tif (static_branch_unlikely(&sched_asym_cpucapacity)) {\n\t\tsync_entity_load_avg(&p->se);\n\t\ttask_util = uclamp_task_util(p);\n\t}\n\n\t/*\n\t * per-cpu select_idle_mask usage\n\t */\n\tlockdep_assert_irqs_disabled();\n\n\tif ((available_idle_cpu(target) || sched_idle_cpu(target)) &&\n\t    asym_fits_capacity(task_util, target))\n\t\treturn target;\n\n\t/*\n\t * If the previous CPU is cache affine and idle, don't be stupid:\n\t */\n\tif (prev != target && cpus_share_cache(prev, target) &&\n\t    (available_idle_cpu(prev) || sched_idle_cpu(prev)) &&\n\t    asym_fits_capacity(task_util, prev))\n\t\treturn prev;\n\n\t/*\n\t * Allow a per-cpu kthread to stack with the wakee if the\n\t * kworker thread and the tasks previous CPUs are the same.\n\t * The assumption is that the wakee queued work for the\n\t * per-cpu kthread that is now complete and the wakeup is\n\t * essentially a sync wakeup. An obvious example of this\n\t * pattern is IO completions.\n\t */\n\tif (is_per_cpu_kthread(current) &&\n\t    in_task() &&\n\t    prev == smp_processor_id() &&\n\t    this_rq()->nr_running <= 1 &&\n\t    asym_fits_capacity(task_util, prev)) {\n\t\treturn prev;\n\t}\n\n\t/* Check a recently used CPU as a potential idle candidate: */\n\trecent_used_cpu = p->recent_used_cpu;\n\tp->recent_used_cpu = prev;\n\tif (recent_used_cpu != prev &&\n\t    recent_used_cpu != target &&\n\t    cpus_share_cache(recent_used_cpu, target) &&\n\t    (available_idle_cpu(recent_used_cpu) || sched_idle_cpu(recent_used_cpu)) &&\n\t    cpumask_test_cpu(p->recent_used_cpu, p->cpus_ptr) &&\n\t    asym_fits_capacity(task_util, recent_used_cpu)) {\n\t\treturn recent_used_cpu;\n\t}\n\n\t/*\n\t * For asymmetric CPU capacity systems, our domain of interest is\n\t * sd_asym_cpucapacity rather than sd_llc.\n\t */\n\tif (static_branch_unlikely(&sched_asym_cpucapacity)) {\n\t\tsd = rcu_dereference(per_cpu(sd_asym_cpucapacity, target));\n\t\t/*\n\t\t * On an asymmetric CPU capacity system where an exclusive\n\t\t * cpuset defines a symmetric island (i.e. one unique\n\t\t * capacity_orig value through the cpuset), the key will be set\n\t\t * but the CPUs within that cpuset will not have a domain with\n\t\t * SD_ASYM_CPUCAPACITY. These should follow the usual symmetric\n\t\t * capacity path.\n\t\t */\n\t\tif (sd) {\n\t\t\ti = select_idle_capacity(p, sd, target);\n\t\t\treturn ((unsigned)i < nr_cpumask_bits) ? i : target;\n\t\t}\n\t}\n\n\tsd = rcu_dereference(per_cpu(sd_llc, target));\n\tif (!sd)\n\t\treturn target;\n\n\tif (sched_smt_active()) {\n\t\thas_idle_core = test_idle_cores(target, false);\n\n\t\tif (!has_idle_core && cpus_share_cache(prev, target)) {\n\t\t\ti = select_idle_smt(p, sd, prev);\n\t\t\tif ((unsigned int)i < nr_cpumask_bits)\n\t\t\t\treturn i;\n\t\t}\n\t}\n\n\ti = select_idle_cpu(p, sd, has_idle_core, target);\n\tif ((unsigned)i < nr_cpumask_bits)\n\t\treturn i;\n\n\treturn target;\n}",
        "static void mon_update_local_domain(struct tipc_monitor *mon)\n{\n\tstruct tipc_peer *self = mon->self;\n\tstruct tipc_mon_domain *cache = &mon->cache;\n\tstruct tipc_mon_domain *dom = self->domain;": "static void mon_update_local_domain(struct tipc_monitor *mon)\n{\n\tstruct tipc_peer *self = mon->self;\n\tstruct tipc_mon_domain *cache = &mon->cache;\n\tstruct tipc_mon_domain *dom = self->domain;\n\tstruct tipc_peer *peer = self;\n\tu64 prev_up_map = dom->up_map;\n\tu16 member_cnt, i;\n\tbool diff;\n\n\t/* Update local domain size based on current size of cluster */\n\tmember_cnt = dom_size(mon->peer_cnt) - 1;\n\tself->applied = member_cnt;\n\n\t/* Update native and cached outgoing local domain records */\n\tdom->len = dom_rec_len(dom, member_cnt);\n\tdiff = dom->member_cnt != member_cnt;\n\tdom->member_cnt = member_cnt;\n\tfor (i = 0; i < member_cnt; i++) {\n\t\tpeer = peer_nxt(peer);\n\t\tdiff |= dom->members[i] != peer->addr;\n\t\tdom->members[i] = peer->addr;\n\t\tmap_set(&dom->up_map, i, peer->is_up);\n\t\tcache->members[i] = mon_cpu_to_le32(peer->addr);\n\t}\n\tdiff |= dom->up_map != prev_up_map;\n\tif (!diff)\n\t\treturn;\n\tdom->gen = ++mon->dom_gen;\n\tcache->len = mon_cpu_to_le16(dom->len);\n\tcache->gen = mon_cpu_to_le16(dom->gen);\n\tcache->member_cnt = mon_cpu_to_le16(member_cnt);\n\tcache->up_map = mon_cpu_to_le64(dom->up_map);\n\tmon_apply_domain(mon, self);\n}",
        "static void amd_mp2_pci_check_rw_event(struct amd_i2c_common *i2c_common)\n{\n\tstruct amd_mp2_dev *privdata = i2c_common->mp2_dev;\n\tstruct pci_dev *pdev = privdata->pci_dev;\n\tint len = i2c_common->eventval.r.length;": "static void amd_mp2_pci_check_rw_event(struct amd_i2c_common *i2c_common)\n{\n\tstruct amd_mp2_dev *privdata = i2c_common->mp2_dev;\n\tstruct pci_dev *pdev = privdata->pci_dev;\n\tint len = i2c_common->eventval.r.length;\n\tu32 slave_addr = i2c_common->eventval.r.slave_addr;\n\tbool err = false;\n\n\tif (unlikely(len != i2c_common->msg->len)) {\n\t\tpci_err(pdev, \"length %d in event doesn't match buffer length %d!\\n\",\n\t\t\tlen, i2c_common->msg->len);\n\t\terr = true;\n\t}\n\n\tif (unlikely(slave_addr != i2c_common->msg->addr)) {\n\t\tpci_err(pdev, \"unexpected slave address %x (expected: %x)!\\n\",\n\t\t\tslave_addr, i2c_common->msg->addr);\n\t\terr = true;\n\t}\n\n\tif (!err)\n\t\ti2c_common->cmd_success = true;\n}",
        "static int mx23_check_transcription_stamp(struct gpmi_nand_data *this)\n{\n\tstruct boot_rom_geometry *rom_geo = &this->rom_geometry;\n\tstruct device *dev = this->dev;\n\tstruct nand_chip *chip = &this->nand;": "static int mx23_check_transcription_stamp(struct gpmi_nand_data *this)\n{\n\tstruct boot_rom_geometry *rom_geo = &this->rom_geometry;\n\tstruct device *dev = this->dev;\n\tstruct nand_chip *chip = &this->nand;\n\tunsigned int search_area_size_in_strides;\n\tunsigned int stride;\n\tunsigned int page;\n\tu8 *buffer = nand_get_data_buf(chip);\n\tint found_an_ncb_fingerprint = false;\n\tint ret;\n\n\t/* Compute the number of strides in a search area. */\n\tsearch_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;\n\n\tnand_select_target(chip, 0);\n\n\t/*\n\t * Loop through the first search area, looking for the NCB fingerprint.\n\t */\n\tdev_dbg(dev, \"Scanning for an NCB fingerprint...\\n\");\n\n\tfor (stride = 0; stride < search_area_size_in_strides; stride++) {\n\t\t/* Compute the page addresses. */\n\t\tpage = stride * rom_geo->stride_size_in_pages;\n\n\t\tdev_dbg(dev, \"Looking for a fingerprint in page 0x%x\\n\", page);\n\n\t\t/*\n\t\t * Read the NCB fingerprint. The fingerprint is four bytes long\n\t\t * and starts in the 12th byte of the page.\n\t\t */\n\t\tret = nand_read_page_op(chip, page, 12, buffer,\n\t\t\t\t\tstrlen(fingerprint));\n\t\tif (ret)\n\t\t\tcontinue;\n\n\t\t/* Look for the fingerprint. */\n\t\tif (!memcmp(buffer, fingerprint, strlen(fingerprint))) {\n\t\t\tfound_an_ncb_fingerprint = true;\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\tnand_deselect_target(chip);\n\n\tif (found_an_ncb_fingerprint)\n\t\tdev_dbg(dev, \"\\tFound a fingerprint\\n\");\n\telse\n\t\tdev_dbg(dev, \"\\tNo fingerprint found\\n\");\n\treturn found_an_ncb_fingerprint;\n}",
        "static bool rcu_torture_one_read(struct torture_random_state *trsp, long myid)\n{\n\tunsigned long cookie;\n\tint i;\n\tunsigned long started;": "static bool rcu_torture_one_read(struct torture_random_state *trsp, long myid)\n{\n\tunsigned long cookie;\n\tint i;\n\tunsigned long started;\n\tunsigned long completed;\n\tint newstate;\n\tstruct rcu_torture *p;\n\tint pipe_count;\n\tint readstate = 0;\n\tstruct rt_read_seg rtseg[RCUTORTURE_RDR_MAX_SEGS] = { { 0 } };\n\tstruct rt_read_seg *rtrsp = &rtseg[0];\n\tstruct rt_read_seg *rtrsp1;\n\tunsigned long long ts;\n\n\tWARN_ON_ONCE(!rcu_is_watching());\n\tnewstate = rcutorture_extend_mask(readstate, trsp);\n\trcutorture_one_extend(&readstate, newstate, trsp, rtrsp++);\n\tif (cur_ops->get_gp_state && cur_ops->poll_gp_state)\n\t\tcookie = cur_ops->get_gp_state();\n\tstarted = cur_ops->get_gp_seq();\n\tts = rcu_trace_clock_local();\n\tp = rcu_dereference_check(rcu_torture_current,\n\t\t\t\t  !cur_ops->readlock_held || cur_ops->readlock_held());\n\tif (p == NULL) {\n\t\t/* Wait for rcu_torture_writer to get underway */\n\t\trcutorture_one_extend(&readstate, 0, trsp, rtrsp);\n\t\treturn false;\n\t}\n\tif (p->rtort_mbtest == 0)\n\t\tatomic_inc(&n_rcu_torture_mberror);\n\trcu_torture_reader_do_mbchk(myid, p, trsp);\n\trtrsp = rcutorture_loop_extend(&readstate, trsp, rtrsp);\n\tpreempt_disable();\n\tpipe_count = READ_ONCE(p->rtort_pipe_count);\n\tif (pipe_count > RCU_TORTURE_PIPE_LEN) {\n\t\t/* Should not happen, but... */\n\t\tpipe_count = RCU_TORTURE_PIPE_LEN;\n\t}\n\tcompleted = cur_ops->get_gp_seq();\n\tif (pipe_count > 1) {\n\t\tdo_trace_rcu_torture_read(cur_ops->name, &p->rtort_rcu,\n\t\t\t\t\t  ts, started, completed);\n\t\trcu_ftrace_dump(DUMP_ALL);\n\t}\n\t__this_cpu_inc(rcu_torture_count[pipe_count]);\n\tcompleted = rcutorture_seq_diff(completed, started);\n\tif (completed > RCU_TORTURE_PIPE_LEN) {\n\t\t/* Should not happen, but... */\n\t\tcompleted = RCU_TORTURE_PIPE_LEN;\n\t}\n\t__this_cpu_inc(rcu_torture_batch[completed]);\n\tpreempt_enable();\n\tif (cur_ops->get_gp_state && cur_ops->poll_gp_state)\n\t\tWARN_ONCE(cur_ops->poll_gp_state(cookie),\n\t\t\t  \"%s: Cookie check 2 failed %s(%d) %lu->%lu\\n\",\n\t\t\t  __func__,\n\t\t\t  rcu_torture_writer_state_getname(),\n\t\t\t  rcu_torture_writer_state,\n\t\t\t  cookie, cur_ops->get_gp_state());\n\trcutorture_one_extend(&readstate, 0, trsp, rtrsp);\n\tWARN_ON_ONCE(readstate);\n\t// This next splat is expected behavior if leakpointer, especially\n\t// for CONFIG_RCU_STRICT_GRACE_PERIOD=y kernels.\n\tWARN_ON_ONCE(leakpointer && READ_ONCE(p->rtort_pipe_count) > 1);\n\n\t/* If error or close call, record the sequence of reader protections. */\n\tif ((pipe_count > 1 || completed > 1) && !xchg(&err_segs_recorded, 1)) {\n\t\ti = 0;\n\t\tfor (rtrsp1 = &rtseg[0]; rtrsp1 < rtrsp; rtrsp1++)\n\t\t\terr_segs[i++] = *rtrsp1;\n\t\trt_read_nsegs = i;\n\t}\n\n\treturn true;\n}",
        "static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)\n{\n\tu32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);\n\tu32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);\n\tu32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);": "static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)\n{\n\tu32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);\n\tu32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);\n\tu32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);\n\tu32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);\n\tu32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);\n\tu32 rx_st, tx_st;\n\n\tif (dma) {\n\t\trx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);\n\t\ttx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);\n\t} else {\n\t\trx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);\n\t\ttx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);\n\t}\n\tdev_dbg(gi2c->se.dev, \"DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\\n\",\n\t\tdma, tx_st, rx_st, m_stat);\n\tdev_dbg(gi2c->se.dev, \"m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\\n\",\n\t\tm_cmd, geni_s, geni_ios);\n}",
        "static int qthread_fn(void *data)\n{\n\tstruct anybuss_host *cd = data;\n\tstruct kfifo *qs = cd->qs;\n\tsize_t nqs = ARRAY_SIZE(cd->qs);": "static int qthread_fn(void *data)\n{\n\tstruct anybuss_host *cd = data;\n\tstruct kfifo *qs = cd->qs;\n\tsize_t nqs = ARRAY_SIZE(cd->qs);\n\tunsigned int ind_ab;\n\n\t/*\n\t * this kernel thread has exclusive access to the anybus's memory.\n\t * only exception: the IND_AB register, which is accessed exclusively\n\t * by the interrupt service routine (ISR). This thread must not touch\n\t * the IND_AB register, but it does require access to its value.\n\t *\n\t * the interrupt service routine stores the register's value in\n\t * cd->ind_ab (an atomic_t), where we may safely access it, with the\n\t * understanding that it can be modified by the ISR at any time.\n\t */\n\n\twhile (!kthread_should_stop()) {\n\t\t/*\n\t\t * make a local copy of IND_AB, so we can go around the loop\n\t\t * again in case it changed while processing queues and softint.\n\t\t */\n\t\tind_ab = atomic_read(&cd->ind_ab);\n\t\tprocess_qs(cd);\n\t\tprocess_softint(cd);\n\t\twait_event_timeout(cd->wq,\n\t\t\t\t   (atomic_read(&cd->ind_ab) != ind_ab) ||\n\t\t\t\tqs_have_work(qs, nqs) ||\n\t\t\t\tkthread_should_stop(),\n\t\t\tHZ);\n\t\t/*\n\t\t * time out so even 'stuck' tasks will run eventually,\n\t\t * and can time out.\n\t\t */\n\t}\n\n\treturn 0;\n}",
        "static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)\n{\n \tunsigned long flags;\n\tint s;\n\tint rc=0;": "static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)\n{\n \tunsigned long flags;\n\tint s;\n\tint rc=0;\n\tstruct mgsl_icount cprev, cnow;\n\tint events;\n\tint mask;\n\tstruct\t_input_signal_events oldsigs, newsigs;\n\tDECLARE_WAITQUEUE(wait, current);\n\n\tif (get_user(mask, mask_ptr))\n\t\treturn -EFAULT;\n\n\tDBGINFO((\"%s wait_mgsl_event(%d)\\n\", info->device_name, mask));\n\n\tspin_lock_irqsave(&info->lock,flags);\n\n\t/* return immediately if state matches requested events */\n\tget_gtsignals(info);\n\ts = info->signals;\n\n\tevents = mask &\n\t\t( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +\n \t\t  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +\n\t\t  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +\n\t\t  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );\n\tif (events) {\n\t\tspin_unlock_irqrestore(&info->lock,flags);\n\t\tgoto exit;\n\t}\n\n\t/* save current irq counts */\n\tcprev = info->icount;\n\toldsigs = info->input_signal_events;\n\n\t/* enable hunt and idle irqs if needed */\n\tif (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {\n\t\tunsigned short val = rd_reg16(info, SCR);\n\t\tif (!(val & IRQ_RXIDLE))\n\t\t\twr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));\n\t}\n\n\tset_current_state(TASK_INTERRUPTIBLE);\n\tadd_wait_queue(&info->event_wait_q, &wait);\n\n\tspin_unlock_irqrestore(&info->lock,flags);\n\n\tfor(;;) {\n\t\tschedule();\n\t\tif (signal_pending(current)) {\n\t\t\trc = -ERESTARTSYS;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* get current irq counts */\n\t\tspin_lock_irqsave(&info->lock,flags);\n\t\tcnow = info->icount;\n\t\tnewsigs = info->input_signal_events;\n\t\tset_current_state(TASK_INTERRUPTIBLE);\n\t\tspin_unlock_irqrestore(&info->lock,flags);\n\n\t\t/* if no change, wait aborted for some reason */\n\t\tif (newsigs.dsr_up   == oldsigs.dsr_up   &&\n\t\t    newsigs.dsr_down == oldsigs.dsr_down &&\n\t\t    newsigs.dcd_up   == oldsigs.dcd_up   &&\n\t\t    newsigs.dcd_down == oldsigs.dcd_down &&\n\t\t    newsigs.cts_up   == oldsigs.cts_up   &&\n\t\t    newsigs.cts_down == oldsigs.cts_down &&\n\t\t    newsigs.ri_up    == oldsigs.ri_up    &&\n\t\t    newsigs.ri_down  == oldsigs.ri_down  &&\n\t\t    cnow.exithunt    == cprev.exithunt   &&\n\t\t    cnow.rxidle      == cprev.rxidle) {\n\t\t\trc = -EIO;\n\t\t\tbreak;\n\t\t}\n\n\t\tevents = mask &\n\t\t\t( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +\n\t\t\t  (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +\n\t\t\t  (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +\n\t\t\t  (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +\n\t\t\t  (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +\n\t\t\t  (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +\n\t\t\t  (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +\n\t\t\t  (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +\n\t\t\t  (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +\n\t\t\t  (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );\n\t\tif (events)\n\t\t\tbreak;\n\n\t\tcprev = cnow;\n\t\toldsigs = newsigs;\n\t}\n\n\tremove_wait_queue(&info->event_wait_q, &wait);\n\tset_current_state(TASK_RUNNING);\n\n\n\tif (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {\n\t\tspin_lock_irqsave(&info->lock,flags);\n\t\tif (!waitqueue_active(&info->event_wait_q)) {\n\t\t\t/* disable enable exit hunt mode/idle rcvd IRQs */\n\t\t\twr_reg16(info, SCR,\n\t\t\t\t(unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));\n\t\t}\n\t\tspin_unlock_irqrestore(&info->lock,flags);\n\t}\nexit:\n\tif (rc == 0)\n\t\trc = put_user(events, mask_ptr);\n\treturn rc;\n}",
        "static int mlx5e_alloc_rx_hd_mpwqe(struct mlx5e_rq *rq)\n{\n\tstruct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;\n\tu16 klm_entries, num_wqe, index, entries_before;\n\tstruct mlx5e_icosq *sq = rq->icosq;": "static int mlx5e_alloc_rx_hd_mpwqe(struct mlx5e_rq *rq)\n{\n\tstruct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;\n\tu16 klm_entries, num_wqe, index, entries_before;\n\tstruct mlx5e_icosq *sq = rq->icosq;\n\tint i, err, max_klm_entries, len;\n\n\tmax_klm_entries = MLX5E_MAX_KLM_PER_WQE(rq->mdev);\n\tklm_entries = bitmap_find_window(shampo->bitmap,\n\t\t\t\t\t shampo->hd_per_wqe,\n\t\t\t\t\t shampo->hd_per_wq, shampo->pi);\n\tif (!klm_entries)\n\t\treturn 0;\n\n\tklm_entries += (shampo->pi & (MLX5_UMR_KLM_ALIGNMENT - 1));\n\tindex = ALIGN_DOWN(shampo->pi, MLX5_UMR_KLM_ALIGNMENT);\n\tentries_before = shampo->hd_per_wq - index;\n\n\tif (unlikely(entries_before < klm_entries))\n\t\tnum_wqe = DIV_ROUND_UP(entries_before, max_klm_entries) +\n\t\t\t  DIV_ROUND_UP(klm_entries - entries_before, max_klm_entries);\n\telse\n\t\tnum_wqe = DIV_ROUND_UP(klm_entries, max_klm_entries);\n\n\tfor (i = 0; i < num_wqe; i++) {\n\t\tlen = (klm_entries > max_klm_entries) ? max_klm_entries :\n\t\t\t\t\t\t\tklm_entries;\n\t\tif (unlikely(index + len > shampo->hd_per_wq))\n\t\t\tlen = shampo->hd_per_wq - index;\n\t\terr = mlx5e_build_shampo_hd_umr(rq, sq, len, index);\n\t\tif (unlikely(err))\n\t\t\treturn err;\n\t\tindex = (index + len) & (rq->mpwqe.shampo->hd_per_wq - 1);\n\t\tklm_entries -= len;\n\t}\n\n\treturn 0;\n}",
        "static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)\n{\n\tu32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;\n\tstruct i2c_msg *msg = &bus->msgs[bus->msgs_index];\n\tu8 slave_addr = i2c_8bit_addr_from_msg(msg);": "static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)\n{\n\tu32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;\n\tstruct i2c_msg *msg = &bus->msgs[bus->msgs_index];\n\tu8 slave_addr = i2c_8bit_addr_from_msg(msg);\n\n#if IS_ENABLED(CONFIG_I2C_SLAVE)\n\t/*\n\t * If it's requested in the middle of a slave session, set the master\n\t * state to 'pending' then H/W will continue handling this master\n\t * command when the bus comes back to the idle state.\n\t */\n\tif (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE) {\n\t\tbus->master_state = ASPEED_I2C_MASTER_PENDING;\n\t\treturn;\n\t}\n#endif /* CONFIG_I2C_SLAVE */\n\n\tbus->master_state = ASPEED_I2C_MASTER_START;\n\tbus->buf_index = 0;\n\n\tif (msg->flags & I2C_M_RD) {\n\t\tcommand |= ASPEED_I2CD_M_RX_CMD;\n\t\t/* Need to let the hardware know to NACK after RX. */\n\t\tif (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))\n\t\t\tcommand |= ASPEED_I2CD_M_S_RX_CMD_LAST;\n\t}\n\n\twritel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);\n\twritel(command, bus->base + ASPEED_I2C_CMD_REG);\n}",
        "static int ns_do_state_action(struct nandsim *ns, uint32_t action)\n{\n\tint num;\n\tint busdiv = ns->busw == 8 ? 1 : 2;\n\tunsigned int erase_block_no, page_no;": "static int ns_do_state_action(struct nandsim *ns, uint32_t action)\n{\n\tint num;\n\tint busdiv = ns->busw == 8 ? 1 : 2;\n\tunsigned int erase_block_no, page_no;\n\n\taction &= ACTION_MASK;\n\n\t/* Check that page address input is correct */\n\tif (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {\n\t\tNS_WARN(\"do_state_action: wrong page number (%#x)\\n\", ns->regs.row);\n\t\treturn -1;\n\t}\n\n\tswitch (action) {\n\n\tcase ACTION_CPY:\n\t\t/*\n\t\t * Copy page data to the internal buffer.\n\t\t */\n\n\t\t/* Column shouldn't be very large */\n\t\tif (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {\n\t\t\tNS_ERR(\"do_state_action: column number is too large\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tnum = ns->geom.pgszoob - NS_PAGE_BYTE_SHIFT(ns);\n\t\tns_read_page(ns, num);\n\n\t\tNS_DBG(\"do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\\n\",\n\t\t\tnum, NS_RAW_OFFSET(ns) + ns->regs.off);\n\n\t\tif (ns->regs.off == 0)\n\t\t\tNS_LOG(\"read page %d\\n\", ns->regs.row);\n\t\telse if (ns->regs.off < ns->geom.pgsz)\n\t\t\tNS_LOG(\"read page %d (second half)\\n\", ns->regs.row);\n\t\telse\n\t\t\tNS_LOG(\"read OOB of page %d\\n\", ns->regs.row);\n\n\t\tNS_UDELAY(access_delay);\n\t\tNS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);\n\n\t\tbreak;\n\n\tcase ACTION_SECERASE:\n\t\t/*\n\t\t * Erase sector.\n\t\t */\n\n\t\tif (ns->lines.wp) {\n\t\t\tNS_ERR(\"do_state_action: device is write-protected, ignore sector erase\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec\n\t\t\t|| (ns->regs.row & ~(ns->geom.secsz - 1))) {\n\t\t\tNS_ERR(\"do_state_action: wrong sector address (%#x)\\n\", ns->regs.row);\n\t\t\treturn -1;\n\t\t}\n\n\t\tns->regs.row = (ns->regs.row <<\n\t\t\t\t8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;\n\t\tns->regs.column = 0;\n\n\t\terase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);\n\n\t\tNS_DBG(\"do_state_action: erase sector at address %#x, off = %d\\n\",\n\t\t\t\tns->regs.row, NS_RAW_OFFSET(ns));\n\t\tNS_LOG(\"erase sector %u\\n\", erase_block_no);\n\n\t\tns_erase_sector(ns);\n\n\t\tNS_MDELAY(erase_delay);\n\n\t\tif (erase_block_wear)\n\t\t\tns_update_wear(erase_block_no);\n\n\t\tif (ns_erase_error(erase_block_no)) {\n\t\t\tNS_WARN(\"simulating erase failure in erase block %u\\n\", erase_block_no);\n\t\t\treturn -1;\n\t\t}\n\n\t\tbreak;\n\n\tcase ACTION_PRGPAGE:\n\t\t/*\n\t\t * Program page - move internal buffer data to the page.\n\t\t */\n\n\t\tif (ns->lines.wp) {\n\t\t\tNS_WARN(\"do_state_action: device is write-protected, programm\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tnum = ns->geom.pgszoob - NS_PAGE_BYTE_SHIFT(ns);\n\t\tif (num != ns->regs.count) {\n\t\t\tNS_ERR(\"do_state_action: too few bytes were input (%d instead of %d)\\n\",\n\t\t\t\t\tns->regs.count, num);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (ns_prog_page(ns, num) == -1)\n\t\t\treturn -1;\n\n\t\tpage_no = ns->regs.row;\n\n\t\tNS_DBG(\"do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\\n\",\n\t\t\tnum, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);\n\t\tNS_LOG(\"programm page %d\\n\", ns->regs.row);\n\n\t\tNS_UDELAY(programm_delay);\n\t\tNS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);\n\n\t\tif (ns_write_error(page_no)) {\n\t\t\tNS_WARN(\"simulating write failure in page %u\\n\", page_no);\n\t\t\treturn -1;\n\t\t}\n\n\t\tbreak;\n\n\tcase ACTION_ZEROOFF:\n\t\tNS_DBG(\"do_state_action: set internal offset to 0\\n\");\n\t\tns->regs.off = 0;\n\t\tbreak;\n\n\tcase ACTION_HALFOFF:\n\t\tif (!(ns->options & OPT_PAGE512_8BIT)) {\n\t\t\tNS_ERR(\"do_state_action: BUG! can't skip half of page for non-512\"\n\t\t\t\t\"byte page size 8x chips\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tNS_DBG(\"do_state_action: set internal offset to %d\\n\", ns->geom.pgsz/2);\n\t\tns->regs.off = ns->geom.pgsz/2;\n\t\tbreak;\n\n\tcase ACTION_OOBOFF:\n\t\tNS_DBG(\"do_state_action: set internal offset to %d\\n\", ns->geom.pgsz);\n\t\tns->regs.off = ns->geom.pgsz;\n\t\tbreak;\n\n\tdefault:\n\t\tNS_DBG(\"do_state_action: BUG! unknown action\\n\");\n\t}\n\n\treturn 0;\n}",
        "static int resize_platform_label_table(struct net *net, size_t limit)\n{\n\tsize_t size = sizeof(struct mpls_route *) * limit;\n\tsize_t old_limit;\n\tsize_t cp_size;": "static int resize_platform_label_table(struct net *net, size_t limit)\n{\n\tsize_t size = sizeof(struct mpls_route *) * limit;\n\tsize_t old_limit;\n\tsize_t cp_size;\n\tstruct mpls_route __rcu **labels = NULL, **old;\n\tstruct mpls_route *rt0 = NULL, *rt2 = NULL;\n\tunsigned index;\n\n\tif (size) {\n\t\tlabels = kvzalloc(size, GFP_KERNEL);\n\t\tif (!labels)\n\t\t\tgoto nolabels;\n\t}\n\n\t/* In case the predefined labels need to be populated */\n\tif (limit > MPLS_LABEL_IPV4NULL) {\n\t\tstruct net_device *lo = net->loopback_dev;\n\t\trt0 = mpls_rt_alloc(1, lo->addr_len, 0);\n\t\tif (IS_ERR(rt0))\n\t\t\tgoto nort0;\n\t\trt0->rt_nh->nh_dev = lo;\n\t\trt0->rt_protocol = RTPROT_KERNEL;\n\t\trt0->rt_payload_type = MPT_IPV4;\n\t\trt0->rt_ttl_propagate = MPLS_TTL_PROP_DEFAULT;\n\t\trt0->rt_nh->nh_via_table = NEIGH_LINK_TABLE;\n\t\trt0->rt_nh->nh_via_alen = lo->addr_len;\n\t\tmemcpy(__mpls_nh_via(rt0, rt0->rt_nh), lo->dev_addr,\n\t\t       lo->addr_len);\n\t}\n\tif (limit > MPLS_LABEL_IPV6NULL) {\n\t\tstruct net_device *lo = net->loopback_dev;\n\t\trt2 = mpls_rt_alloc(1, lo->addr_len, 0);\n\t\tif (IS_ERR(rt2))\n\t\t\tgoto nort2;\n\t\trt2->rt_nh->nh_dev = lo;\n\t\trt2->rt_protocol = RTPROT_KERNEL;\n\t\trt2->rt_payload_type = MPT_IPV6;\n\t\trt2->rt_ttl_propagate = MPLS_TTL_PROP_DEFAULT;\n\t\trt2->rt_nh->nh_via_table = NEIGH_LINK_TABLE;\n\t\trt2->rt_nh->nh_via_alen = lo->addr_len;\n\t\tmemcpy(__mpls_nh_via(rt2, rt2->rt_nh), lo->dev_addr,\n\t\t       lo->addr_len);\n\t}\n\n\trtnl_lock();\n\t/* Remember the original table */\n\told = rtnl_dereference(net->mpls.platform_label);\n\told_limit = net->mpls.platform_labels;\n\n\t/* Free any labels beyond the new table */\n\tfor (index = limit; index < old_limit; index++)\n\t\tmpls_route_update(net, index, NULL, NULL);\n\n\t/* Copy over the old labels */\n\tcp_size = size;\n\tif (old_limit < limit)\n\t\tcp_size = old_limit * sizeof(struct mpls_route *);\n\n\tmemcpy(labels, old, cp_size);\n\n\t/* If needed set the predefined labels */\n\tif ((old_limit <= MPLS_LABEL_IPV6NULL) &&\n\t    (limit > MPLS_LABEL_IPV6NULL)) {\n\t\tRCU_INIT_POINTER(labels[MPLS_LABEL_IPV6NULL], rt2);\n\t\trt2 = NULL;\n\t}\n\n\tif ((old_limit <= MPLS_LABEL_IPV4NULL) &&\n\t    (limit > MPLS_LABEL_IPV4NULL)) {\n\t\tRCU_INIT_POINTER(labels[MPLS_LABEL_IPV4NULL], rt0);\n\t\trt0 = NULL;\n\t}\n\n\t/* Update the global pointers */\n\tnet->mpls.platform_labels = limit;\n\trcu_assign_pointer(net->mpls.platform_label, labels);\n\n\trtnl_unlock();\n\n\tmpls_rt_free(rt2);\n\tmpls_rt_free(rt0);\n\n\tif (old) {\n\t\tsynchronize_rcu();\n\t\tkvfree(old);\n\t}\n\treturn 0;\n\nnort2:\n\tmpls_rt_free(rt0);\nnort0:\n\tkvfree(labels);\nnolabels:\n\treturn -ENOMEM;\n}",
        "static int hci_set_event_mask_sync(struct hci_dev *hdev)\n{\n\t/* The second byte is 0xff instead of 0x9f (two reserved bits\n\t * disabled) since a Broadcom 1.2 dongle doesn't respond to the\n\t * command otherwise.": "static int hci_set_event_mask_sync(struct hci_dev *hdev)\n{\n\t/* The second byte is 0xff instead of 0x9f (two reserved bits\n\t * disabled) since a Broadcom 1.2 dongle doesn't respond to the\n\t * command otherwise.\n\t */\n\tu8 events[8] = { 0xff, 0xff, 0xfb, 0xff, 0x00, 0x00, 0x00, 0x00 };\n\n\t/* CSR 1.1 dongles does not accept any bitfield so don't try to set\n\t * any event mask for pre 1.2 devices.\n\t */\n\tif (hdev->hci_ver < BLUETOOTH_VER_1_2)\n\t\treturn 0;\n\n\tif (lmp_bredr_capable(hdev)) {\n\t\tevents[4] |= 0x01; /* Flow Specification Complete */\n\n\t\t/* Don't set Disconnect Complete when suspended as that\n\t\t * would wakeup the host when disconnecting due to\n\t\t * suspend.\n\t\t */\n\t\tif (hdev->suspended)\n\t\t\tevents[0] &= 0xef;\n\t} else {\n\t\t/* Use a different default for LE-only devices */\n\t\tmemset(events, 0, sizeof(events));\n\t\tevents[1] |= 0x20; /* Command Complete */\n\t\tevents[1] |= 0x40; /* Command Status */\n\t\tevents[1] |= 0x80; /* Hardware Error */\n\n\t\t/* If the controller supports the Disconnect command, enable\n\t\t * the corresponding event. In addition enable packet flow\n\t\t * control related events.\n\t\t */\n\t\tif (hdev->commands[0] & 0x20) {\n\t\t\t/* Don't set Disconnect Complete when suspended as that\n\t\t\t * would wakeup the host when disconnecting due to\n\t\t\t * suspend.\n\t\t\t */\n\t\t\tif (!hdev->suspended)\n\t\t\t\tevents[0] |= 0x10; /* Disconnection Complete */\n\t\t\tevents[2] |= 0x04; /* Number of Completed Packets */\n\t\t\tevents[3] |= 0x02; /* Data Buffer Overflow */\n\t\t}\n\n\t\t/* If the controller supports the Read Remote Version\n\t\t * Information command, enable the corresponding event.\n\t\t */\n\t\tif (hdev->commands[2] & 0x80)\n\t\t\tevents[1] |= 0x08; /* Read Remote Version Information\n\t\t\t\t\t    * Complete\n\t\t\t\t\t    */\n\n\t\tif (hdev->le_features[0] & HCI_LE_ENCRYPTION) {\n\t\t\tevents[0] |= 0x80; /* Encryption Change */\n\t\t\tevents[5] |= 0x80; /* Encryption Key Refresh Complete */\n\t\t}\n\t}\n\n\tif (lmp_inq_rssi_capable(hdev) ||\n\t    test_bit(HCI_QUIRK_FIXUP_INQUIRY_MODE, &hdev->quirks))\n\t\tevents[4] |= 0x02; /* Inquiry Result with RSSI */\n\n\tif (lmp_ext_feat_capable(hdev))\n\t\tevents[4] |= 0x04; /* Read Remote Extended Features Complete */\n\n\tif (lmp_esco_capable(hdev)) {\n\t\tevents[5] |= 0x08; /* Synchronous Connection Complete */\n\t\tevents[5] |= 0x10; /* Synchronous Connection Changed */\n\t}\n\n\tif (lmp_sniffsubr_capable(hdev))\n\t\tevents[5] |= 0x20; /* Sniff Subrating */\n\n\tif (lmp_pause_enc_capable(hdev))\n\t\tevents[5] |= 0x80; /* Encryption Key Refresh Complete */\n\n\tif (lmp_ext_inq_capable(hdev))\n\t\tevents[5] |= 0x40; /* Extended Inquiry Result */\n\n\tif (lmp_no_flush_capable(hdev))\n\t\tevents[7] |= 0x01; /* Enhanced Flush Complete */\n\n\tif (lmp_lsto_capable(hdev))\n\t\tevents[6] |= 0x80; /* Link Supervision Timeout Changed */\n\n\tif (lmp_ssp_capable(hdev)) {\n\t\tevents[6] |= 0x01;\t/* IO Capability Request */\n\t\tevents[6] |= 0x02;\t/* IO Capability Response */\n\t\tevents[6] |= 0x04;\t/* User Confirmation Request */\n\t\tevents[6] |= 0x08;\t/* User Passkey Request */\n\t\tevents[6] |= 0x10;\t/* Remote OOB Data Request */\n\t\tevents[6] |= 0x20;\t/* Simple Pairing Complete */\n\t\tevents[7] |= 0x04;\t/* User Passkey Notification */\n\t\tevents[7] |= 0x08;\t/* Keypress Notification */\n\t\tevents[7] |= 0x10;\t/* Remote Host Supported\n\t\t\t\t\t * Features Notification\n\t\t\t\t\t */\n\t}\n\n\tif (lmp_le_capable(hdev))\n\t\tevents[7] |= 0x20;\t/* LE Meta-Event */\n\n\treturn __hci_cmd_sync_status(hdev, HCI_OP_SET_EVENT_MASK,\n\t\t\t\t     sizeof(events), events, HCI_CMD_TIMEOUT);\n}",
        "static int vdec_1_stbuf_power_up(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0);": "static int vdec_1_stbuf_power_up(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0);\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_WRAP_COUNT, 0);\n\tamvdec_write_dos(core, POWER_CTL_VLD, BIT(4));\n\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_START_PTR, sess->vififo_paddr);\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_CURR_PTR, sess->vififo_paddr);\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_END_PTR,\n\t\t\t sess->vififo_paddr + sess->vififo_size - 8);\n\n\tamvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);\n\tamvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);\n\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL);\n\tamvdec_write_dos(core, VLD_MEM_VIFIFO_WP, sess->vififo_paddr);\n\n\tamvdec_write_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);\n\tamvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);\n\n\tamvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL,\n\t\t\t      (0x11 << MEM_FIFO_CNT_BIT) | MEM_FILL_ON_LEVEL |\n\t\t\t      MEM_CTRL_FILL_EN | MEM_CTRL_EMPTY_EN);\n\n\treturn 0;\n}",
        "static void mana_gd_process_eq_events(void *arg)\n{\n\tu32 owner_bits, new_bits, old_bits;\n\tunion gdma_eqe_info eqe_info;\n\tstruct gdma_eqe *eq_eqe_ptr;": "static void mana_gd_process_eq_events(void *arg)\n{\n\tu32 owner_bits, new_bits, old_bits;\n\tunion gdma_eqe_info eqe_info;\n\tstruct gdma_eqe *eq_eqe_ptr;\n\tstruct gdma_queue *eq = arg;\n\tstruct gdma_context *gc;\n\tstruct gdma_eqe *eqe;\n\tu32 head, num_eqe;\n\tint i;\n\n\tgc = eq->gdma_dev->gdma_context;\n\n\tnum_eqe = eq->queue_size / GDMA_EQE_SIZE;\n\teq_eqe_ptr = eq->queue_mem_ptr;\n\n\t/* Process up to 5 EQEs at a time, and update the HW head. */\n\tfor (i = 0; i < 5; i++) {\n\t\teqe = &eq_eqe_ptr[eq->head % num_eqe];\n\t\teqe_info.as_uint32 = eqe->eqe_info;\n\t\towner_bits = eqe_info.owner_bits;\n\n\t\told_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;\n\t\t/* No more entries */\n\t\tif (owner_bits == old_bits)\n\t\t\tbreak;\n\n\t\tnew_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;\n\t\tif (owner_bits != new_bits) {\n\t\t\tdev_err(gc->dev, \"EQ %d: overflow detected\\n\", eq->id);\n\t\t\tbreak;\n\t\t}\n\n\t\tmana_gd_process_eqe(eq);\n\n\t\teq->head++;\n\t}\n\n\thead = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);\n\n\tmana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id,\n\t\t\t      head, SET_ARM_BIT);\n}",
        "static int qlge_start_rss(struct qlge_adapter *qdev)\n{\n\tstatic const u8 init_hash_seed[] = {\n\t\t0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,\n\t\t0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,": "static int qlge_start_rss(struct qlge_adapter *qdev)\n{\n\tstatic const u8 init_hash_seed[] = {\n\t\t0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,\n\t\t0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,\n\t\t0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,\n\t\t0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,\n\t\t0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa\n\t};\n\tstruct ricb *ricb = &qdev->ricb;\n\tint status = 0;\n\tint i;\n\tu8 *hash_id = (u8 *)ricb->hash_cq_id;\n\n\tmemset((void *)ricb, 0, sizeof(*ricb));\n\n\tricb->base_cq = RSS_L4K;\n\tricb->flags =\n\t\t(RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);\n\tricb->mask = cpu_to_le16((u16)(0x3ff));\n\n\t/*\n\t * Fill out the Indirection Table.\n\t */\n\tfor (i = 0; i < 1024; i++)\n\t\thash_id[i] = (i & (qdev->rss_ring_count - 1));\n\n\tmemcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);\n\tmemcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);\n\n\tstatus = qlge_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);\n\tif (status) {\n\t\tnetif_err(qdev, ifup, qdev->ndev, \"Failed to load RICB.\\n\");\n\t\treturn status;\n\t}\n\treturn status;\n}",
        "static void tda1997x_reset_n1(struct tda1997x_state *state)\n{\n\tstruct v4l2_subdev *sd = &state->sd;\n\tu8 reg;\n": "static void tda1997x_reset_n1(struct tda1997x_state *state)\n{\n\tstruct v4l2_subdev *sd = &state->sd;\n\tu8 reg;\n\n\t/* clear HDMI mode flag in BCAPS */\n\tio_write(sd, REG_CLK_CFG, CLK_CFG_SEL_ACLK_EN | CLK_CFG_SEL_ACLK);\n\tio_write(sd, REG_PON_OVR_EN, PON_EN);\n\tio_write(sd, REG_PON_CBIAS, PON_EN);\n\tio_write(sd, REG_PON_PLL, PON_EN);\n\n\treg = io_read(sd, REG_MODE_REC_CFG1);\n\treg &= ~0x06;\n\treg |= 0x02;\n\tio_write(sd, REG_MODE_REC_CFG1, reg);\n\tio_write(sd, REG_CLK_CFG, CLK_CFG_DIS);\n\tio_write(sd, REG_PON_OVR_EN, PON_DIS);\n\treg = io_read(sd, REG_MODE_REC_CFG1);\n\treg &= ~0x06;\n\tio_write(sd, REG_MODE_REC_CFG1, reg);\n}",
        "static int __init bluetooth_init(struct ibm_init_struct *iibm)\n{\n\tint res;\n\tint status = 0;\n": "static int __init bluetooth_init(struct ibm_init_struct *iibm)\n{\n\tint res;\n\tint status = 0;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\t\"initializing bluetooth subdriver\\n\");\n\n\tTPACPI_ACPIHANDLE_INIT(hkey);\n\n\t/* bluetooth not supported on 570, 600e/x, 770e, 770x, A21e, A2xm/p,\n\t   G4x, R30, R31, R40e, R50e, T20-22, X20-21 */\n\ttp_features.bluetooth = !have_bt_fwbug() && hkey_handle &&\n\t    acpi_evalf(hkey_handle, &status, \"GBDC\", \"qd\");\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\"bluetooth is %s, status 0x%02x\\n\",\n\t\tstr_supported(tp_features.bluetooth),\n\t\tstatus);\n\n#ifdef CONFIG_THINKPAD_ACPI_DEBUGFACILITIES\n\tif (dbg_bluetoothemul) {\n\t\ttp_features.bluetooth = 1;\n\t\tpr_info(\"bluetooth switch emulation enabled\\n\");\n\t} else\n#endif\n\tif (tp_features.bluetooth &&\n\t    !(status & TP_ACPI_BLUETOOTH_HWPRESENT)) {\n\t\t/* no bluetooth hardware present in system */\n\t\ttp_features.bluetooth = 0;\n\t\tdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\t   \"bluetooth hardware not installed\\n\");\n\t}\n\n\tif (!tp_features.bluetooth)\n\t\treturn -ENODEV;\n\n\tres = tpacpi_new_rfkill(TPACPI_RFK_BLUETOOTH_SW_ID,\n\t\t\t\t&bluetooth_tprfk_ops,\n\t\t\t\tRFKILL_TYPE_BLUETOOTH,\n\t\t\t\tTPACPI_RFK_BLUETOOTH_SW_NAME,\n\t\t\t\ttrue);\n\treturn res;\n}",
        "static void __exit comp_exit(void)\n{\n\tstruct most_video_dev *mdev, *tmp;\n\n\t/*": "static void __exit comp_exit(void)\n{\n\tstruct most_video_dev *mdev, *tmp;\n\n\t/*\n\t * As the mostcore currently doesn't call disconnect_channel()\n\t * for linked channels while we call most_deregister_component()\n\t * we simulate this call here.\n\t * This must be fixed in core.\n\t */\n\tspin_lock_irq(&list_lock);\n\tlist_for_each_entry_safe(mdev, tmp, &video_devices, list) {\n\t\tlist_del(&mdev->list);\n\t\tspin_unlock_irq(&list_lock);\n\n\t\tcomp_unregister_videodev(mdev);\n\t\tv4l2_device_disconnect(&mdev->v4l2_dev);\n\t\tv4l2_device_put(&mdev->v4l2_dev);\n\t\tspin_lock_irq(&list_lock);\n\t}\n\tspin_unlock_irq(&list_lock);\n\n\tmost_deregister_configfs_subsys(&comp);\n\tmost_deregister_component(&comp);\n\tBUG_ON(!list_empty(&video_devices));\n}",
        "static int ms_read_attribute_info(struct rtsx_chip *chip)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tint retval, i;\n\tu8 val, *buf, class_code, device_type, sub_class, data[16];": "static int ms_read_attribute_info(struct rtsx_chip *chip)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tint retval, i;\n\tu8 val, *buf, class_code, device_type, sub_class, data[16];\n\tu16 total_blk = 0, blk_size = 0;\n#ifdef SUPPORT_MSXC\n\tu32 xc_total_blk = 0, xc_blk_size = 0;\n#endif\n\tu32 sys_info_addr = 0, sys_info_size;\n#ifdef SUPPORT_PCGL_1P18\n\tu32 model_name_addr = 0, model_name_size;\n\tint found_sys_info = 0, found_model_name = 0;\n#endif\n\n\tretval = ms_set_rw_reg_addr(chip, PRO_INT_REG, 2, PRO_SYSTEM_PARAM, 7);\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\tif (CHK_MS8BIT(ms_card))\n\t\tdata[0] = PARALLEL_8BIT_IF;\n\telse\n\t\tdata[0] = PARALLEL_4BIT_IF;\n\n\tdata[1] = 0;\n\n\tdata[2] = 0x40;\n\tdata[3] = 0;\n\tdata[4] = 0;\n\tdata[5] = 0;\n\tdata[6] = 0;\n\tdata[7] = 0;\n\n\tfor (i = 0; i < MS_MAX_RETRY_COUNT; i++) {\n\t\tretval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,\n\t\t\t\t\tdata, 8);\n\t\tif (retval == STATUS_SUCCESS)\n\t\t\tbreak;\n\t}\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\tbuf = kmalloc(64 * 512, GFP_KERNEL);\n\tif (!buf)\n\t\treturn STATUS_ERROR;\n\n\tfor (i = 0; i < MS_MAX_RETRY_COUNT; i++) {\n\t\tretval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tcontinue;\n\n\t\tretval = rtsx_read_register(chip, MS_TRANS_CFG, &val);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tkfree(buf);\n\t\t\treturn STATUS_FAIL;\n\t\t}\n\t\tif (!(val & MS_INT_BREQ)) {\n\t\t\tkfree(buf);\n\t\t\treturn STATUS_FAIL;\n\t\t}\n\t\tretval = ms_transfer_data(chip, MS_TM_AUTO_READ,\n\t\t\t\t\t  PRO_READ_LONG_DATA, 0x40, WAIT_INT,\n\t\t\t\t\t  0, 0, buf, 64 * 512);\n\t\tif (retval == STATUS_SUCCESS)\n\t\t\tbreak;\n\n\t\trtsx_clear_ms_error(chip);\n\t}\n\tif (retval != STATUS_SUCCESS) {\n\t\tkfree(buf);\n\t\treturn STATUS_FAIL;\n\t}\n\n\ti = 0;\n\tdo {\n\t\tretval = rtsx_read_register(chip, MS_TRANS_CFG, &val);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tkfree(buf);\n\t\t\treturn STATUS_FAIL;\n\t\t}\n\n\t\tif ((val & MS_INT_CED) || !(val & MS_INT_BREQ))\n\t\t\tbreak;\n\n\t\tretval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,\n\t\t\t\t\t PRO_READ_LONG_DATA, 0, WAIT_INT);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tkfree(buf);\n\t\t\treturn STATUS_FAIL;\n\t\t}\n\n\t\ti++;\n\t} while (i < 1024);\n\n\tif (buf[0] != 0xa5 && buf[1] != 0xc3) {\n\t\t/* Signature code is wrong */\n\t\tkfree(buf);\n\t\treturn STATUS_FAIL;\n\t}\n\n\tif (buf[4] < 1 || buf[4] > 12) {\n\t\tkfree(buf);\n\t\treturn STATUS_FAIL;\n\t}\n\n\tfor (i = 0; i < buf[4]; i++) {\n\t\tint cur_addr_off = 16 + i * 12;\n\n#ifdef SUPPORT_MSXC\n\t\tif (buf[cur_addr_off + 8] == 0x10 ||\n\t\t    buf[cur_addr_off + 8] == 0x13) {\n#else\n\t\tif (buf[cur_addr_off + 8] == 0x10) {\n#endif\n\t\t\tsys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |\n\t\t\t\t((u32)buf[cur_addr_off + 1] << 16) |\n\t\t\t\t((u32)buf[cur_addr_off + 2] << 8) |\n\t\t\t\tbuf[cur_addr_off + 3];\n\t\t\tsys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |\n\t\t\t\t((u32)buf[cur_addr_off + 5] << 16) |\n\t\t\t\t((u32)buf[cur_addr_off + 6] << 8) |\n\t\t\t\tbuf[cur_addr_off + 7];\n\t\t\tdev_dbg(rtsx_dev(chip), \"sys_info_addr = 0x%x, sys_info_size = 0x%x\\n\",\n\t\t\t\tsys_info_addr, sys_info_size);\n\t\t\tif (sys_info_size != 96)  {\n\t\t\t\tkfree(buf);\n\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\t\t\tif (sys_info_addr < 0x1A0) {\n\t\t\t\tkfree(buf);\n\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\t\t\tif ((sys_info_size + sys_info_addr) > 0x8000) {\n\t\t\t\tkfree(buf);\n\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\n#ifdef SUPPORT_MSXC\n\t\t\tif (buf[cur_addr_off + 8] == 0x13)\n\t\t\t\tms_card->ms_type |= MS_XC;\n#endif\n#ifdef SUPPORT_PCGL_1P18\n\t\t\tfound_sys_info = 1;\n#else\n\t\t\tbreak;\n#endif\n\t\t}\n#ifdef SUPPORT_PCGL_1P18\n\t\tif (buf[cur_addr_off + 8] == 0x15) {\n\t\t\tmodel_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |\n\t\t\t\t((u32)buf[cur_addr_off + 1] << 16) |\n\t\t\t\t((u32)buf[cur_addr_off + 2] << 8) |\n\t\t\t\tbuf[cur_addr_off + 3];\n\t\t\tmodel_name_size = ((u32)buf[cur_addr_off + 4] << 24) |\n\t\t\t\t((u32)buf[cur_addr_off + 5] << 16) |\n\t\t\t\t((u32)buf[cur_addr_off + 6] << 8) |\n\t\t\t\tbuf[cur_addr_off + 7];\n\t\t\tdev_dbg(rtsx_dev(chip), \"model_name_addr = 0x%x, model_name_size = 0x%x\\n\",\n\t\t\t\tmodel_name_addr, model_name_size);\n\t\t\tif (model_name_size != 48)  {\n\t\t\t\tkfree(buf);\n\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\t\t\tif (model_name_addr < 0x1A0) {\n\t\t\t\tkfree(buf);\n\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\t\t\tif ((model_name_size + model_name_addr) > 0x8000) {\n\t\t\t\tkfree(buf);\n\t\t\t\treturn STATUS_FAIL;\n\t\t\t}\n\n\t\t\tfound_model_name = 1;\n\t\t}\n\n\t\tif (found_sys_info && found_model_name)\n\t\t\tbreak;\n#endif\n\t}\n\n\tif (i == buf[4]) {\n\t\tkfree(buf);\n\t\treturn STATUS_FAIL;\n\t}\n\n\tclass_code =  buf[sys_info_addr + 0];\n\tdevice_type = buf[sys_info_addr + 56];\n\tsub_class = buf[sys_info_addr + 46];\n#ifdef SUPPORT_MSXC\n\tif (CHK_MSXC(ms_card)) {\n\t\txc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |\n\t\t\t\t((u32)buf[sys_info_addr + 7] << 16) |\n\t\t\t\t((u32)buf[sys_info_addr + 8] << 8) |\n\t\t\t\tbuf[sys_info_addr + 9];\n\t\txc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |\n\t\t\t\t((u32)buf[sys_info_addr + 33] << 16) |\n\t\t\t\t((u32)buf[sys_info_addr + 34] << 8) |\n\t\t\t\tbuf[sys_info_addr + 35];\n\t\tdev_dbg(rtsx_dev(chip), \"xc_total_blk = 0x%x, xc_blk_size = 0x%x\\n\",\n\t\t\txc_total_blk, xc_blk_size);\n\t} else {\n\t\ttotal_blk = ((u16)buf[sys_info_addr + 6] << 8) |\n\t\t\tbuf[sys_info_addr + 7];\n\t\tblk_size = ((u16)buf[sys_info_addr + 2] << 8) |\n\t\t\tbuf[sys_info_addr + 3];\n\t\tdev_dbg(rtsx_dev(chip), \"total_blk = 0x%x, blk_size = 0x%x\\n\",\n\t\t\ttotal_blk, blk_size);\n\t}\n#else\n\ttotal_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];\n\tblk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];\n\tdev_dbg(rtsx_dev(chip), \"total_blk = 0x%x, blk_size = 0x%x\\n\",\n\t\ttotal_blk, blk_size);\n#endif\n\n\tdev_dbg(rtsx_dev(chip), \"class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\\n\",\n\t\tclass_code, device_type, sub_class);\n\n\tmemcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);\n#ifdef SUPPORT_PCGL_1P18\n\tmemcpy(ms_card->raw_model_name, buf + model_name_addr, 48);\n#endif\n\n\tkfree(buf);\n\n#ifdef SUPPORT_MSXC\n\tif (CHK_MSXC(ms_card)) {\n\t\tif (class_code != 0x03)\n\t\t\treturn STATUS_FAIL;\n\t} else {\n\t\tif (class_code != 0x02)\n\t\t\treturn STATUS_FAIL;\n\t}\n#else\n\tif (class_code != 0x02)\n\t\treturn STATUS_FAIL;\n#endif\n\n\tif (device_type != 0x00) {\n\t\tif (device_type == 0x01 || device_type == 0x02 ||\n\t\t    device_type == 0x03) {\n\t\t\tchip->card_wp |= MS_CARD;\n\t\t} else {\n\t\t\treturn STATUS_FAIL;\n\t\t}\n\t}\n\n\tif (sub_class & 0xC0)\n\t\treturn STATUS_FAIL;\n\n\tdev_dbg(rtsx_dev(chip), \"class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\\n\",\n\t\tclass_code, device_type, sub_class);\n\n#ifdef SUPPORT_MSXC\n\tif (CHK_MSXC(ms_card)) {\n\t\tchip->capacity[chip->card2lun[MS_CARD]] =\n\t\t\tms_card->capacity = xc_total_blk * xc_blk_size;\n\t} else {\n\t\tchip->capacity[chip->card2lun[MS_CARD]] =\n\t\t\tms_card->capacity = total_blk * blk_size;\n\t}\n#else\n\tms_card->capacity = total_blk * blk_size;\n\tchip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;\n#endif\n\n\treturn STATUS_SUCCESS;\n}",
        "static inline int dentry_cmp(const struct dentry *dentry, const unsigned char *ct, unsigned tcount)\n{\n\t/*\n\t * Be careful about RCU walk racing with rename:\n\t * use 'READ_ONCE' to fetch the name pointer.": "static inline int dentry_cmp(const struct dentry *dentry, const unsigned char *ct, unsigned tcount)\n{\n\t/*\n\t * Be careful about RCU walk racing with rename:\n\t * use 'READ_ONCE' to fetch the name pointer.\n\t *\n\t * NOTE! Even if a rename will mean that the length\n\t * was not loaded atomically, we don't care. The\n\t * RCU walk will check the sequence count eventually,\n\t * and catch it. And we won't overrun the buffer,\n\t * because we're reading the name pointer atomically,\n\t * and a dentry name is guaranteed to be properly\n\t * terminated with a NUL byte.\n\t *\n\t * End result: even if 'len' is wrong, we'll exit\n\t * early because the data cannot match (there can\n\t * be no NUL in the ct/tcount data)\n\t */\n\tconst unsigned char *cs = READ_ONCE(dentry->d_name.name);\n\n\treturn dentry_string_cmp(cs, ct, tcount);\n}",
        "static bool vmci_transport_notify_waiting_write(struct vsock_sock *vsk)\n{\n#if defined(VSOCK_OPTIMIZATION_WAITING_NOTIFY)\n\tbool retval;\n\tu64 notify_limit;": "static bool vmci_transport_notify_waiting_write(struct vsock_sock *vsk)\n{\n#if defined(VSOCK_OPTIMIZATION_WAITING_NOTIFY)\n\tbool retval;\n\tu64 notify_limit;\n\n\tif (!PKT_FIELD(vsk, peer_waiting_write))\n\t\treturn false;\n\n#ifdef VSOCK_OPTIMIZATION_FLOW_CONTROL\n\t/* When the sender blocks, we take that as a sign that the sender is\n\t * faster than the receiver. To reduce the transmit rate of the sender,\n\t * we delay the sending of the read notification by decreasing the\n\t * write_notify_window. The notification is delayed until the number of\n\t * bytes used in the queue drops below the write_notify_window.\n\t */\n\n\tif (!PKT_FIELD(vsk, peer_waiting_write_detected)) {\n\t\tPKT_FIELD(vsk, peer_waiting_write_detected) = true;\n\t\tif (PKT_FIELD(vsk, write_notify_window) < PAGE_SIZE) {\n\t\t\tPKT_FIELD(vsk, write_notify_window) =\n\t\t\t    PKT_FIELD(vsk, write_notify_min_window);\n\t\t} else {\n\t\t\tPKT_FIELD(vsk, write_notify_window) -= PAGE_SIZE;\n\t\t\tif (PKT_FIELD(vsk, write_notify_window) <\n\t\t\t    PKT_FIELD(vsk, write_notify_min_window))\n\t\t\t\tPKT_FIELD(vsk, write_notify_window) =\n\t\t\t\t    PKT_FIELD(vsk, write_notify_min_window);\n\n\t\t}\n\t}\n\tnotify_limit = vmci_trans(vsk)->consume_size -\n\t\tPKT_FIELD(vsk, write_notify_window);\n#else\n\tnotify_limit = 0;\n#endif\n\n\t/* For now we ignore the wait information and just see if the free\n\t * space exceeds the notify limit.  Note that improving this function\n\t * to be more intelligent will not require a protocol change and will\n\t * retain compatibility between endpoints with mixed versions of this\n\t * function.\n\t *\n\t * The notify_limit is used to delay notifications in the case where\n\t * flow control is enabled. Below the test is expressed in terms of\n\t * free space in the queue: if free_space > ConsumeSize -\n\t * write_notify_window then notify An alternate way of expressing this\n\t * is to rewrite the expression to use the data ready in the receive\n\t * queue: if write_notify_window > bufferReady then notify as\n\t * free_space == ConsumeSize - bufferReady.\n\t */\n\tretval = vmci_qpair_consume_free_space(vmci_trans(vsk)->qpair) >\n\t\tnotify_limit;\n#ifdef VSOCK_OPTIMIZATION_FLOW_CONTROL\n\tif (retval) {\n\t\t/*\n\t\t * Once we notify the peer, we reset the detected flag so the\n\t\t * next wait will again cause a decrease in the window size.\n\t\t */\n\n\t\tPKT_FIELD(vsk, peer_waiting_write_detected) = false;\n\t}\n#endif\n\treturn retval;\n#else\n\treturn true;\n#endif\n}",
        "static void mld_add_delrec(struct inet6_dev *idev, struct ifmcaddr6 *im)\n{\n\tstruct ifmcaddr6 *pmc;\n\n\t/* this is an \"ifmcaddr6\" for convenience; only the fields below": "static void mld_add_delrec(struct inet6_dev *idev, struct ifmcaddr6 *im)\n{\n\tstruct ifmcaddr6 *pmc;\n\n\t/* this is an \"ifmcaddr6\" for convenience; only the fields below\n\t * are actually used. In particular, the refcnt and users are not\n\t * used for management of the delete list. Using the same structure\n\t * for deleted items allows change reports to use common code with\n\t * non-deleted or query-response MCA's.\n\t */\n\tpmc = kzalloc(sizeof(*pmc), GFP_KERNEL);\n\tif (!pmc)\n\t\treturn;\n\n\tpmc->idev = im->idev;\n\tin6_dev_hold(idev);\n\tpmc->mca_addr = im->mca_addr;\n\tpmc->mca_crcount = idev->mc_qrv;\n\tpmc->mca_sfmode = im->mca_sfmode;\n\tif (pmc->mca_sfmode == MCAST_INCLUDE) {\n\t\tstruct ip6_sf_list *psf;\n\n\t\trcu_assign_pointer(pmc->mca_tomb,\n\t\t\t\t   mc_dereference(im->mca_tomb, idev));\n\t\trcu_assign_pointer(pmc->mca_sources,\n\t\t\t\t   mc_dereference(im->mca_sources, idev));\n\t\tRCU_INIT_POINTER(im->mca_tomb, NULL);\n\t\tRCU_INIT_POINTER(im->mca_sources, NULL);\n\n\t\tfor_each_psf_mclock(pmc, psf)\n\t\t\tpsf->sf_crcount = pmc->mca_crcount;\n\t}\n\n\trcu_assign_pointer(pmc->next, idev->mc_tomb);\n\trcu_assign_pointer(idev->mc_tomb, pmc);\n}",
        "static int rspi_set_config_register(struct rspi_data *rspi, int access_size)\n{\n\t/* Sets output mode, MOSI signal, and (optionally) loopback */\n\trspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);\n": "static int rspi_set_config_register(struct rspi_data *rspi, int access_size)\n{\n\t/* Sets output mode, MOSI signal, and (optionally) loopback */\n\trspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);\n\n\t/* Sets transfer bit rate */\n\trspi_set_rate(rspi);\n\n\t/* Disable dummy transmission, set 16-bit word access, 1 frame */\n\trspi_write8(rspi, 0, RSPI_SPDCR);\n\trspi->byte_access = 0;\n\n\t/* Sets RSPCK, SSL, next-access delay value */\n\trspi_write8(rspi, 0x00, RSPI_SPCKD);\n\trspi_write8(rspi, 0x00, RSPI_SSLND);\n\trspi_write8(rspi, 0x00, RSPI_SPND);\n\n\t/* Sets parity, interrupt mask */\n\trspi_write8(rspi, 0x00, RSPI_SPCR2);\n\n\t/* Resets sequencer */\n\trspi_write8(rspi, 0, RSPI_SPSCR);\n\trspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);\n\trspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);\n\n\t/* Sets RSPI mode */\n\trspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);\n\n\treturn 0;\n}",
        "static void handle_init_ack_msg(const struct vdec_vpu_ipi_init_ack *msg)\n{\n\tstruct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *)\n\t\t\t\t\t(unsigned long)msg->ap_inst_addr;\n": "static void handle_init_ack_msg(const struct vdec_vpu_ipi_init_ack *msg)\n{\n\tstruct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *)\n\t\t\t\t\t(unsigned long)msg->ap_inst_addr;\n\n\tmtk_vcodec_debug(vpu, \"+ ap_inst_addr = 0x%llx\", msg->ap_inst_addr);\n\n\t/* mapping VPU address to kernel virtual address */\n\t/* the content in vsi is initialized to 0 in VPU */\n\tvpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler,\n\t\t\t\t\t     msg->vpu_inst_addr);\n\tvpu->inst_addr = msg->vpu_inst_addr;\n\n\tmtk_vcodec_debug(vpu, \"- vpu_inst_addr = 0x%x\", vpu->inst_addr);\n\n\t/* Set default ABI version if dealing with unversioned firmware. */\n\tvpu->fw_abi_version = 0;\n\t/*\n\t * Instance ID is only used if ABI version >= 2. Initialize it with\n\t * garbage by default.\n\t */\n\tvpu->inst_id = 0xdeadbeef;\n\n\t/* VPU firmware does not contain a version field. */\n\tif (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU)\n\t\treturn;\n\n\t/* Check firmware version. */\n\tvpu->fw_abi_version = msg->vdec_abi_version;\n\tmtk_vcodec_debug(vpu, \"firmware version 0x%x\\n\", vpu->fw_abi_version);\n\tswitch (vpu->fw_abi_version) {\n\tcase 1:\n\t\tbreak;\n\tcase 2:\n\t\tvpu->inst_id = msg->inst_id;\n\t\tbreak;\n\tdefault:\n\t\tmtk_vcodec_err(vpu, \"unhandled firmware version 0x%x\\n\",\n\t\t\t       vpu->fw_abi_version);\n\t\tvpu->failure = 1;\n\t\tbreak;\n\t}\n}",
        "static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)\n{\n\tstruct qup_i2c_block *blk = &qup->blk;\n\tu32 qup_config = I2C_MINI_CORE | I2C_N_VAL;\n\tu32 io_mode = QUP_REPACK_EN;": "static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)\n{\n\tstruct qup_i2c_block *blk = &qup->blk;\n\tu32 qup_config = I2C_MINI_CORE | I2C_N_VAL;\n\tu32 io_mode = QUP_REPACK_EN;\n\n\tblk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;\n\tblk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;\n\n\tif (blk->is_tx_blk_mode) {\n\t\tio_mode |= QUP_OUTPUT_BLK_MODE;\n\t\twritel(0, qup->base + QUP_MX_WRITE_CNT);\n\t\twritel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);\n\t} else {\n\t\twritel(0, qup->base + QUP_MX_OUTPUT_CNT);\n\t\twritel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);\n\t}\n\n\tif (blk->total_rx_len) {\n\t\tif (blk->is_rx_blk_mode) {\n\t\t\tio_mode |= QUP_INPUT_BLK_MODE;\n\t\t\twritel(0, qup->base + QUP_MX_READ_CNT);\n\t\t\twritel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);\n\t\t} else {\n\t\t\twritel(0, qup->base + QUP_MX_INPUT_CNT);\n\t\t\twritel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);\n\t\t}\n\t} else {\n\t\tqup_config |= QUP_NO_INPUT;\n\t}\n\n\twritel(qup_config, qup->base + QUP_CONFIG);\n\twritel(io_mode, qup->base + QUP_IO_MODE);\n}",
        "static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc)\n{\n\tint blkaddr, layer, prof_idx, err;\n\tstruct nix_ipolicer *ipolicer;\n\tstruct nix_hw *nix_hw;": "static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc)\n{\n\tint blkaddr, layer, prof_idx, err;\n\tstruct nix_ipolicer *ipolicer;\n\tstruct nix_hw *nix_hw;\n\n\tif (!rvu->hw->cap.ipolicer)\n\t\treturn NIX_AF_ERR_IPOLICER_NOTSUPP;\n\n\terr = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);\n\tif (err)\n\t\treturn err;\n\n\tmutex_lock(&rvu->rsrc_lock);\n\t/* Free all the profiles allocated to the PCIFUNC */\n\tfor (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {\n\t\tif (layer == BAND_PROF_INVAL_LAYER)\n\t\t\tcontinue;\n\t\tipolicer = &nix_hw->ipolicer[layer];\n\n\t\tfor (prof_idx = 0; prof_idx < ipolicer->band_prof.max; prof_idx++) {\n\t\t\tif (ipolicer->pfvf_map[prof_idx] != pcifunc)\n\t\t\t\tcontinue;\n\n\t\t\t/* Clear ratelimit aggregation, if any */\n\t\t\tif (layer == BAND_PROF_LEAF_LAYER &&\n\t\t\t    ipolicer->match_id[prof_idx])\n\t\t\t\tnix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx);\n\n\t\t\tipolicer->pfvf_map[prof_idx] = 0x00;\n\t\t\tipolicer->match_id[prof_idx] = 0;\n\t\t\trvu_free_rsrc(&ipolicer->band_prof, prof_idx);\n\t\t}\n\t}\n\tmutex_unlock(&rvu->rsrc_lock);\n\treturn 0;\n}",
        "static void ks7010_init_defaults(struct ks_wlan_private *priv)\n{\n\tpriv->reg.tx_rate = TX_RATE_AUTO;\n\tpriv->reg.preamble = LONG_PREAMBLE;\n\tpriv->reg.power_mgmt = POWER_MGMT_ACTIVE;": "static void ks7010_init_defaults(struct ks_wlan_private *priv)\n{\n\tpriv->reg.tx_rate = TX_RATE_AUTO;\n\tpriv->reg.preamble = LONG_PREAMBLE;\n\tpriv->reg.power_mgmt = POWER_MGMT_ACTIVE;\n\tpriv->reg.scan_type = ACTIVE_SCAN;\n\tpriv->reg.beacon_lost_count = 20;\n\tpriv->reg.rts = 2347UL;\n\tpriv->reg.fragment = 2346UL;\n\tpriv->reg.phy_type = D_11BG_COMPATIBLE_MODE;\n\tpriv->reg.cts_mode = CTS_MODE_FALSE;\n\tpriv->reg.rate_set.body[11] = TX_RATE_54M;\n\tpriv->reg.rate_set.body[10] = TX_RATE_48M;\n\tpriv->reg.rate_set.body[9] = TX_RATE_36M;\n\tpriv->reg.rate_set.body[8] = TX_RATE_18M;\n\tpriv->reg.rate_set.body[7] = TX_RATE_9M;\n\tpriv->reg.rate_set.body[6] = TX_RATE_24M | BASIC_RATE;\n\tpriv->reg.rate_set.body[5] = TX_RATE_12M | BASIC_RATE;\n\tpriv->reg.rate_set.body[4] = TX_RATE_6M | BASIC_RATE;\n\tpriv->reg.rate_set.body[3] = TX_RATE_11M | BASIC_RATE;\n\tpriv->reg.rate_set.body[2] = TX_RATE_5M | BASIC_RATE;\n\tpriv->reg.rate_set.body[1] = TX_RATE_2M | BASIC_RATE;\n\tpriv->reg.rate_set.body[0] = TX_RATE_1M | BASIC_RATE;\n\tpriv->reg.tx_rate = TX_RATE_FULL_AUTO;\n\tpriv->reg.rate_set.size = 12;\n}",
        "static void amd_dump_ibs_op(struct perf_sample *sample)\n{\n\tstruct perf_ibs_data *data = sample->raw_data;\n\tunion ibs_op_ctl *op_ctl = (union ibs_op_ctl *)data->data;\n\t__u64 *rip = (__u64 *)op_ctl + 1;": "static void amd_dump_ibs_op(struct perf_sample *sample)\n{\n\tstruct perf_ibs_data *data = sample->raw_data;\n\tunion ibs_op_ctl *op_ctl = (union ibs_op_ctl *)data->data;\n\t__u64 *rip = (__u64 *)op_ctl + 1;\n\tunion ibs_op_data *op_data = (union ibs_op_data *)(rip + 1);\n\tunion ibs_op_data3 *op_data3 = (union ibs_op_data3 *)(rip + 3);\n\n\tpr_ibs_op_ctl(*op_ctl);\n\tif (!op_data->op_rip_invalid)\n\t\tprintf(\"IbsOpRip:\\t%016llx\\n\", *rip);\n\tpr_ibs_op_data(*op_data);\n\t/*\n\t * Erratum #1293: ignore op_data2 if DcMissNoMabAlloc or SwPf are set\n\t */\n\tif (!(cpu_family == 0x19 && cpu_model < 0x10 &&\n\t      (op_data3->dc_miss_no_mab_alloc || op_data3->sw_pf)))\n\t\tpr_ibs_op_data2(*(union ibs_op_data2 *)(rip + 2));\n\tpr_ibs_op_data3(*op_data3);\n\tif (op_data3->dc_lin_addr_valid)\n\t\tprintf(\"IbsDCLinAd:\\t%016llx\\n\", *(rip + 4));\n\tif (op_data3->dc_phy_addr_valid)\n\t\tprintf(\"IbsDCPhysAd:\\t%016llx\\n\", *(rip + 5));\n\tif (op_data->op_brn_ret && *(rip + 6))\n\t\tprintf(\"IbsBrTarget:\\t%016llx\\n\", *(rip + 6));\n}",
        "static int getmac_tt(u8 * decodedMAC, u8 * encodedMAC)\n{\n\tu8 xor[20] = { 0x72, 0x23, 0x68, 0x19, 0x5c, 0xa8, 0x71, 0x2c,\n\t\t       0x54, 0xd3, 0x7b, 0xf1, 0x9E, 0x23, 0x16, 0xf6,\n\t\t       0x1d, 0x36, 0x64, 0x78};": "static int getmac_tt(u8 * decodedMAC, u8 * encodedMAC)\n{\n\tu8 xor[20] = { 0x72, 0x23, 0x68, 0x19, 0x5c, 0xa8, 0x71, 0x2c,\n\t\t       0x54, 0xd3, 0x7b, 0xf1, 0x9E, 0x23, 0x16, 0xf6,\n\t\t       0x1d, 0x36, 0x64, 0x78};\n\tu8 data[20];\n\tint i;\n\n\t/* In case there is a sig check failure have the orig contents available */\n\tmemcpy(data, encodedMAC, 20);\n\n\tfor (i = 0; i < 20; i++)\n\t\tdata[i] ^= xor[i];\n\tfor (i = 0; i < 10; i++)\n\t\tdata[i] = ((data[2 * i + 1] << 8) | data[2 * i])\n\t\t\t>> ((data[2 * i + 1] >> 6) & 3);\n\n\tif (check_mac_tt(data))\n\t\treturn -ENODEV;\n\n\tdecodedMAC[0] = data[2]; decodedMAC[1] = data[1]; decodedMAC[2] = data[0];\n\tdecodedMAC[3] = data[6]; decodedMAC[4] = data[5]; decodedMAC[5] = data[4];\n\treturn 0;\n}",
        "static int test_tc_bpf_api(struct bpf_tc_hook *hook, int fd)\n{\n\tDECLARE_LIBBPF_OPTS(bpf_tc_opts, attach_opts, .handle = 1, .priority = 1, .prog_fd = fd);\n\tDECLARE_LIBBPF_OPTS(bpf_tc_hook, inv_hook, .attach_point = BPF_TC_INGRESS);\n\tDECLARE_LIBBPF_OPTS(bpf_tc_opts, opts, .handle = 1, .priority = 1);": "static int test_tc_bpf_api(struct bpf_tc_hook *hook, int fd)\n{\n\tDECLARE_LIBBPF_OPTS(bpf_tc_opts, attach_opts, .handle = 1, .priority = 1, .prog_fd = fd);\n\tDECLARE_LIBBPF_OPTS(bpf_tc_hook, inv_hook, .attach_point = BPF_TC_INGRESS);\n\tDECLARE_LIBBPF_OPTS(bpf_tc_opts, opts, .handle = 1, .priority = 1);\n\tint ret;\n\n\tret = bpf_tc_hook_create(NULL);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_create invalid hook = NULL\"))\n\t\treturn -EINVAL;\n\n\t/* hook ifindex = 0 */\n\tret = bpf_tc_hook_create(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_create invalid hook ifindex == 0\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_hook_destroy(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_destroy invalid hook ifindex == 0\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_attach(&inv_hook, &attach_opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid hook ifindex == 0\"))\n\t\treturn -EINVAL;\n\tattach_opts.prog_id = 0;\n\n\tret = bpf_tc_detach(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid hook ifindex == 0\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_query(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid hook ifindex == 0\"))\n\t\treturn -EINVAL;\n\n\t/* hook ifindex < 0 */\n\tinv_hook.ifindex = -1;\n\n\tret = bpf_tc_hook_create(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_create invalid hook ifindex < 0\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_hook_destroy(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_destroy invalid hook ifindex < 0\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_attach(&inv_hook, &attach_opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid hook ifindex < 0\"))\n\t\treturn -EINVAL;\n\tattach_opts.prog_id = 0;\n\n\tret = bpf_tc_detach(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid hook ifindex < 0\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_query(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid hook ifindex < 0\"))\n\t\treturn -EINVAL;\n\n\tinv_hook.ifindex = LO_IFINDEX;\n\n\t/* hook.attach_point invalid */\n\tinv_hook.attach_point = 0xabcd;\n\tret = bpf_tc_hook_create(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_create invalid hook.attach_point\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_hook_destroy(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_destroy invalid hook.attach_point\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_attach(&inv_hook, &attach_opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid hook.attach_point\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_detach(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid hook.attach_point\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_query(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid hook.attach_point\"))\n\t\treturn -EINVAL;\n\n\tinv_hook.attach_point = BPF_TC_INGRESS;\n\n\t/* hook.attach_point valid, but parent invalid */\n\tinv_hook.parent = TC_H_MAKE(1UL << 16, 10);\n\tret = bpf_tc_hook_create(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_create invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_hook_destroy(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_hook_destroy invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_attach(&inv_hook, &attach_opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_detach(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_query(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tinv_hook.attach_point = BPF_TC_CUSTOM;\n\tinv_hook.parent = 0;\n\t/* These return EOPNOTSUPP instead of EINVAL as parent is checked after\n\t * attach_point of the hook.\n\t */\n\tret = bpf_tc_hook_create(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EOPNOTSUPP, \"bpf_tc_hook_create invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_hook_destroy(&inv_hook);\n\tif (!ASSERT_EQ(ret, -EOPNOTSUPP, \"bpf_tc_hook_destroy invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_attach(&inv_hook, &attach_opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_detach(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tret = bpf_tc_query(&inv_hook, &opts);\n\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid hook parent\"))\n\t\treturn -EINVAL;\n\n\tinv_hook.attach_point = BPF_TC_INGRESS;\n\n\t/* detach */\n\t{\n\t\tTEST_DECLARE_OPTS(fd);\n\n\t\tret = bpf_tc_detach(NULL, &opts_hp);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid hook = NULL\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, NULL);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid opts = NULL\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, &opts_hpr);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid flags set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, &opts_hpf);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid prog_fd set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, &opts_hpi);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid prog_id set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, &opts_p);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid handle unset\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, &opts_h);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid priority unset\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_detach(hook, &opts_prio_max);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_detach invalid priority > UINT16_MAX\"))\n\t\t\treturn -EINVAL;\n\t}\n\n\t/* query */\n\t{\n\t\tTEST_DECLARE_OPTS(fd);\n\n\t\tret = bpf_tc_query(NULL, &opts);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid hook = NULL\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, NULL);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid opts = NULL\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, &opts_hpr);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid flags set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, &opts_hpf);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid prog_fd set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, &opts_hpi);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid prog_id set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, &opts_p);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid handle unset\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, &opts_h);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid priority unset\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_query(hook, &opts_prio_max);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query invalid priority > UINT16_MAX\"))\n\t\t\treturn -EINVAL;\n\n\t\t/* when chain is not present, kernel returns -EINVAL */\n\t\tret = bpf_tc_query(hook, &opts_hp);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_query valid handle, priority set\"))\n\t\t\treturn -EINVAL;\n\t}\n\n\t/* attach */\n\t{\n\t\tTEST_DECLARE_OPTS(fd);\n\n\t\tret = bpf_tc_attach(NULL, &opts_hp);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid hook = NULL\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_attach(hook, NULL);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid opts = NULL\"))\n\t\t\treturn -EINVAL;\n\n\t\topts_hp.flags = 42;\n\t\tret = bpf_tc_attach(hook, &opts_hp);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid flags\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_attach(hook, NULL);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid prog_fd unset\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_attach(hook, &opts_hpi);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid prog_id set\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_attach(hook, &opts_pf);\n\t\tif (!ASSERT_OK(ret, \"bpf_tc_attach valid handle unset\"))\n\t\t\treturn -EINVAL;\n\t\topts_pf.prog_fd = opts_pf.prog_id = 0;\n\t\tASSERT_OK(bpf_tc_detach(hook, &opts_pf), \"bpf_tc_detach\");\n\n\t\tret = bpf_tc_attach(hook, &opts_hf);\n\t\tif (!ASSERT_OK(ret, \"bpf_tc_attach valid priority unset\"))\n\t\t\treturn -EINVAL;\n\t\topts_hf.prog_fd = opts_hf.prog_id = 0;\n\t\tASSERT_OK(bpf_tc_detach(hook, &opts_hf), \"bpf_tc_detach\");\n\n\t\tret = bpf_tc_attach(hook, &opts_prio_max);\n\t\tif (!ASSERT_EQ(ret, -EINVAL, \"bpf_tc_attach invalid priority > UINT16_MAX\"))\n\t\t\treturn -EINVAL;\n\n\t\tret = bpf_tc_attach(hook, &opts_f);\n\t\tif (!ASSERT_OK(ret, \"bpf_tc_attach valid both handle and priority unset\"))\n\t\t\treturn -EINVAL;\n\t\topts_f.prog_fd = opts_f.prog_id = 0;\n\t\tASSERT_OK(bpf_tc_detach(hook, &opts_f), \"bpf_tc_detach\");\n\t}\n\n\treturn 0;\n}",
        "static void __enqueue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags)\n{\n\tstruct rt_rq *rt_rq = rt_rq_of_se(rt_se);\n\tstruct rt_prio_array *array = &rt_rq->active;\n\tstruct rt_rq *group_rq = group_rt_rq(rt_se);": "static void __enqueue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags)\n{\n\tstruct rt_rq *rt_rq = rt_rq_of_se(rt_se);\n\tstruct rt_prio_array *array = &rt_rq->active;\n\tstruct rt_rq *group_rq = group_rt_rq(rt_se);\n\tstruct list_head *queue = array->queue + rt_se_prio(rt_se);\n\n\t/*\n\t * Don't enqueue the group if its throttled, or when empty.\n\t * The latter is a consequence of the former when a child group\n\t * get throttled and the current group doesn't have any other\n\t * active members.\n\t */\n\tif (group_rq && (rt_rq_throttled(group_rq) || !group_rq->rt_nr_running)) {\n\t\tif (rt_se->on_list)\n\t\t\t__delist_rt_entity(rt_se, array);\n\t\treturn;\n\t}\n\n\tif (move_entity(flags)) {\n\t\tWARN_ON_ONCE(rt_se->on_list);\n\t\tif (flags & ENQUEUE_HEAD)\n\t\t\tlist_add(&rt_se->run_list, queue);\n\t\telse\n\t\t\tlist_add_tail(&rt_se->run_list, queue);\n\n\t\t__set_bit(rt_se_prio(rt_se), array->bitmap);\n\t\trt_se->on_list = 1;\n\t}\n\trt_se->on_rq = 1;\n\n\tinc_rt_tasks(rt_se, rt_rq);\n}",
        "static int smc_pnet_remove_by_pnetid(struct net *net, char *pnet_name)\n{\n\tstruct smc_pnetentry *pnetelem, *tmp_pe;\n\tstruct smc_pnettable *pnettable;\n\tstruct smc_ib_device *ibdev;": "static int smc_pnet_remove_by_pnetid(struct net *net, char *pnet_name)\n{\n\tstruct smc_pnetentry *pnetelem, *tmp_pe;\n\tstruct smc_pnettable *pnettable;\n\tstruct smc_ib_device *ibdev;\n\tstruct smcd_dev *smcd_dev;\n\tstruct smc_net *sn;\n\tint rc = -ENOENT;\n\tint ibport;\n\n\t/* get pnettable for namespace */\n\tsn = net_generic(net, smc_net_id);\n\tpnettable = &sn->pnettable;\n\n\t/* remove table entry */\n\tmutex_lock(&pnettable->lock);\n\tlist_for_each_entry_safe(pnetelem, tmp_pe, &pnettable->pnetlist,\n\t\t\t\t list) {\n\t\tif (!pnet_name ||\n\t\t    smc_pnet_match(pnetelem->pnet_name, pnet_name)) {\n\t\t\tlist_del(&pnetelem->list);\n\t\t\tif (pnetelem->type == SMC_PNET_ETH && pnetelem->ndev) {\n\t\t\t\tdev_put_track(pnetelem->ndev, &pnetelem->dev_tracker);\n\t\t\t\tpr_warn_ratelimited(\"smc: net device %s \"\n\t\t\t\t\t\t    \"erased user defined \"\n\t\t\t\t\t\t    \"pnetid %.16s\\n\",\n\t\t\t\t\t\t    pnetelem->eth_name,\n\t\t\t\t\t\t    pnetelem->pnet_name);\n\t\t\t}\n\t\t\tkfree(pnetelem);\n\t\t\trc = 0;\n\t\t}\n\t}\n\tmutex_unlock(&pnettable->lock);\n\n\t/* if this is not the initial namespace, stop here */\n\tif (net != &init_net)\n\t\treturn rc;\n\n\t/* remove ib devices */\n\tmutex_lock(&smc_ib_devices.mutex);\n\tlist_for_each_entry(ibdev, &smc_ib_devices.list, list) {\n\t\tfor (ibport = 0; ibport < SMC_MAX_PORTS; ibport++) {\n\t\t\tif (ibdev->pnetid_by_user[ibport] &&\n\t\t\t    (!pnet_name ||\n\t\t\t     smc_pnet_match(pnet_name,\n\t\t\t\t\t    ibdev->pnetid[ibport]))) {\n\t\t\t\tpr_warn_ratelimited(\"smc: ib device %s ibport \"\n\t\t\t\t\t\t    \"%d erased user defined \"\n\t\t\t\t\t\t    \"pnetid %.16s\\n\",\n\t\t\t\t\t\t    ibdev->ibdev->name,\n\t\t\t\t\t\t    ibport + 1,\n\t\t\t\t\t\t    ibdev->pnetid[ibport]);\n\t\t\t\tmemset(ibdev->pnetid[ibport], 0,\n\t\t\t\t       SMC_MAX_PNETID_LEN);\n\t\t\t\tibdev->pnetid_by_user[ibport] = false;\n\t\t\t\trc = 0;\n\t\t\t}\n\t\t}\n\t}\n\tmutex_unlock(&smc_ib_devices.mutex);\n\t/* remove smcd devices */\n\tmutex_lock(&smcd_dev_list.mutex);\n\tlist_for_each_entry(smcd_dev, &smcd_dev_list.list, list) {\n\t\tif (smcd_dev->pnetid_by_user &&\n\t\t    (!pnet_name ||\n\t\t     smc_pnet_match(pnet_name, smcd_dev->pnetid))) {\n\t\t\tpr_warn_ratelimited(\"smc: smcd device %s \"\n\t\t\t\t\t    \"erased user defined pnetid \"\n\t\t\t\t\t    \"%.16s\\n\", dev_name(&smcd_dev->dev),\n\t\t\t\t\t    smcd_dev->pnetid);\n\t\t\tmemset(smcd_dev->pnetid, 0, SMC_MAX_PNETID_LEN);\n\t\t\tsmcd_dev->pnetid_by_user = false;\n\t\t\trc = 0;\n\t\t}\n\t}\n\tmutex_unlock(&smcd_dev_list.mutex);\n\treturn rc;\n}",
        "static void nozomi_setup_memory(struct nozomi *dc)\n{\n\tvoid __iomem *offset = dc->base_addr + dc->config_table.dl_start;\n\t/* The length reported is including the length field of 4 bytes,\n\t * hence subtract with 4.": "static void nozomi_setup_memory(struct nozomi *dc)\n{\n\tvoid __iomem *offset = dc->base_addr + dc->config_table.dl_start;\n\t/* The length reported is including the length field of 4 bytes,\n\t * hence subtract with 4.\n\t */\n\tconst u16 buff_offset = 4;\n\n\t/* Modem port dl configuration */\n\tdc->port[PORT_MDM].dl_addr[CH_A] = offset;\n\tdc->port[PORT_MDM].dl_addr[CH_B] =\n\t\t\t\t(offset += dc->config_table.dl_mdm_len1);\n\tdc->port[PORT_MDM].dl_size[CH_A] =\n\t\t\t\tdc->config_table.dl_mdm_len1 - buff_offset;\n\tdc->port[PORT_MDM].dl_size[CH_B] =\n\t\t\t\tdc->config_table.dl_mdm_len2 - buff_offset;\n\n\t/* Diag port dl configuration */\n\tdc->port[PORT_DIAG].dl_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.dl_mdm_len2);\n\tdc->port[PORT_DIAG].dl_size[CH_A] =\n\t\t\t\tdc->config_table.dl_diag_len1 - buff_offset;\n\tdc->port[PORT_DIAG].dl_addr[CH_B] =\n\t\t\t\t(offset += dc->config_table.dl_diag_len1);\n\tdc->port[PORT_DIAG].dl_size[CH_B] =\n\t\t\t\tdc->config_table.dl_diag_len2 - buff_offset;\n\n\t/* App1 port dl configuration */\n\tdc->port[PORT_APP1].dl_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.dl_diag_len2);\n\tdc->port[PORT_APP1].dl_size[CH_A] =\n\t\t\t\tdc->config_table.dl_app1_len - buff_offset;\n\n\t/* App2 port dl configuration */\n\tdc->port[PORT_APP2].dl_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.dl_app1_len);\n\tdc->port[PORT_APP2].dl_size[CH_A] =\n\t\t\t\tdc->config_table.dl_app2_len - buff_offset;\n\n\t/* Ctrl dl configuration */\n\tdc->port[PORT_CTRL].dl_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.dl_app2_len);\n\tdc->port[PORT_CTRL].dl_size[CH_A] =\n\t\t\t\tdc->config_table.dl_ctrl_len - buff_offset;\n\n\toffset = dc->base_addr + dc->config_table.ul_start;\n\n\t/* Modem Port ul configuration */\n\tdc->port[PORT_MDM].ul_addr[CH_A] = offset;\n\tdc->port[PORT_MDM].ul_size[CH_A] =\n\t\t\t\tdc->config_table.ul_mdm_len1 - buff_offset;\n\tdc->port[PORT_MDM].ul_addr[CH_B] =\n\t\t\t\t(offset += dc->config_table.ul_mdm_len1);\n\tdc->port[PORT_MDM].ul_size[CH_B] =\n\t\t\t\tdc->config_table.ul_mdm_len2 - buff_offset;\n\n\t/* Diag port ul configuration */\n\tdc->port[PORT_DIAG].ul_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.ul_mdm_len2);\n\tdc->port[PORT_DIAG].ul_size[CH_A] =\n\t\t\t\tdc->config_table.ul_diag_len - buff_offset;\n\n\t/* App1 port ul configuration */\n\tdc->port[PORT_APP1].ul_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.ul_diag_len);\n\tdc->port[PORT_APP1].ul_size[CH_A] =\n\t\t\t\tdc->config_table.ul_app1_len - buff_offset;\n\n\t/* App2 port ul configuration */\n\tdc->port[PORT_APP2].ul_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.ul_app1_len);\n\tdc->port[PORT_APP2].ul_size[CH_A] =\n\t\t\t\tdc->config_table.ul_app2_len - buff_offset;\n\n\t/* Ctrl ul configuration */\n\tdc->port[PORT_CTRL].ul_addr[CH_A] =\n\t\t\t\t(offset += dc->config_table.ul_app2_len);\n\tdc->port[PORT_CTRL].ul_size[CH_A] =\n\t\t\t\tdc->config_table.ul_ctrl_len - buff_offset;\n}",
        "static int ila_del_mapping(struct net *net, struct ila_xlat_params *xp)\n{\n\tstruct ila_net *ilan = net_generic(net, ila_net_id);\n\tstruct ila_map *ila, *head, *prev;\n\tspinlock_t *lock = ila_get_lock(ilan, xp->ip.locator_match);": "static int ila_del_mapping(struct net *net, struct ila_xlat_params *xp)\n{\n\tstruct ila_net *ilan = net_generic(net, ila_net_id);\n\tstruct ila_map *ila, *head, *prev;\n\tspinlock_t *lock = ila_get_lock(ilan, xp->ip.locator_match);\n\tint err = -ENOENT;\n\n\tspin_lock(lock);\n\n\thead = rhashtable_lookup_fast(&ilan->xlat.rhash_table,\n\t\t\t\t      &xp->ip.locator_match, rht_params);\n\tila = head;\n\n\tprev = NULL;\n\n\twhile (ila) {\n\t\tif (ila_cmp_params(ila, xp)) {\n\t\t\tprev = ila;\n\t\t\tila = rcu_dereference_protected(ila->next,\n\t\t\t\t\t\t\tlockdep_is_held(lock));\n\t\t\tcontinue;\n\t\t}\n\n\t\terr = 0;\n\n\t\tif (prev) {\n\t\t\t/* Not head, just delete from list */\n\t\t\trcu_assign_pointer(prev->next, ila->next);\n\t\t} else {\n\t\t\t/* It is the head. If there is something in the\n\t\t\t * sublist we need to make a new head.\n\t\t\t */\n\t\t\thead = rcu_dereference_protected(ila->next,\n\t\t\t\t\t\t\t lockdep_is_held(lock));\n\t\t\tif (head) {\n\t\t\t\t/* Put first entry in the sublist into the\n\t\t\t\t * table\n\t\t\t\t */\n\t\t\t\terr = rhashtable_replace_fast(\n\t\t\t\t\t&ilan->xlat.rhash_table, &ila->node,\n\t\t\t\t\t&head->node, rht_params);\n\t\t\t\tif (err)\n\t\t\t\t\tgoto out;\n\t\t\t} else {\n\t\t\t\t/* Entry no longer used */\n\t\t\t\terr = rhashtable_remove_fast(\n\t\t\t\t\t\t&ilan->xlat.rhash_table,\n\t\t\t\t\t\t&ila->node, rht_params);\n\t\t\t}\n\t\t}\n\n\t\tila_release(ila);\n\n\t\tbreak;\n\t}\n\nout:\n\tspin_unlock(lock);\n\n\treturn err;\n}",
        "static void soi763a_6810_init(struct gspca_dev *gspca_dev)\n{\n\tstatic const struct cmd reg_init_1[] = {\n\t\t{TP6800_R2F_TIMING_CFG, 0x2f},\n\t\t{TP6800_R18_GPIO_DATA, 0xe1},": "static void soi763a_6810_init(struct gspca_dev *gspca_dev)\n{\n\tstatic const struct cmd reg_init_1[] = {\n\t\t{TP6800_R2F_TIMING_CFG, 0x2f},\n\t\t{TP6800_R18_GPIO_DATA, 0xe1},\n\t\t{0x25, 0x02},\n\t\t{TP6800_R21_ENDP_1_CTL, 0x00},\n\t\t{TP6800_R3F_FRAME_RATE, 0x80},\n\t\t{TP6800_R2F_TIMING_CFG, 0x2f},\n\t\t{TP6800_R18_GPIO_DATA, 0xc1},\n\t};\n\tstatic const struct cmd reg_init_2[] = {\n\t\t{TP6800_R78_FORMAT, 0x54},\n\t};\n\tstatic const struct cmd sensor_init[] = {\n\t\t{0x00, 0x00},\n\t\t{0x01, 0x80},\n\t\t{0x02, 0x80},\n\t\t{0x03, 0x90},\n\t\t{0x04, 0x20},\n\t\t{0x05, 0x20},\n\t\t{0x06, 0x80},\n\t\t{0x07, 0x00},\n\t\t{0x08, 0xff},\n\t\t{0x09, 0xff},\n\t\t{0x0a, 0x76},\t\t/* 7630 = soi673a */\n\t\t{0x0b, 0x30},\n\t\t{0x0c, 0x20},\n\t\t{0x0d, 0x20},\n\t\t{0x0e, 0xff},\n\t\t{0x0f, 0xff},\n\t\t{0x10, 0x41},\n\t\t{0x15, 0x14},\n\t\t{0x11, 0x40},\n\t\t{0x12, 0x48},\n\t\t{0x13, 0x80},\n\t\t{0x14, 0x80},\n\t\t{0x16, 0x03},\n\t\t{0x28, 0xb0},\n\t\t{0x71, 0x20},\n\t\t{0x75, 0x8e},\n\t\t{0x17, 0x1b},\n\t\t{0x18, 0xbd},\n\t\t{0x19, 0x05},\n\t\t{0x1a, 0xf6},\n\t\t{0x1b, 0x04},\n\t\t{0x1c, 0x7f},\t\t/* omnivision */\n\t\t{0x1d, 0xa2},\n\t\t{0x1e, 0x00},\n\t\t{0x1f, 0x00},\n\t\t{0x20, 0x45},\n\t\t{0x21, 0x80},\n\t\t{0x22, 0x80},\n\t\t{0x23, 0xee},\n\t\t{0x24, 0x50},\n\t\t{0x25, 0x7a},\n\t\t{0x26, 0xa0},\n\t\t{0x27, 0x9a},\n\t\t{0x29, 0x30},\n\t\t{0x2a, 0x80},\n\t\t{0x2b, 0x00},\n\t\t{0x2c, 0xac},\n\t\t{0x2d, 0x05},\n\t\t{0x2e, 0x80},\n\t\t{0x2f, 0x3c},\n\t\t{0x30, 0x22},\n\t\t{0x31, 0x00},\n\t\t{0x32, 0x86},\n\t\t{0x33, 0x08},\n\t\t{0x34, 0xff},\n\t\t{0x35, 0xff},\n\t\t{0x36, 0xff},\n\t\t{0x37, 0xff},\n\t\t{0x38, 0xff},\n\t\t{0x39, 0xff},\n\t\t{0x3a, 0xfe},\n\t\t{0x3b, 0xfe},\n\t\t{0x3c, 0xfe},\n\t\t{0x3d, 0xfe},\n\t\t{0x3e, 0xfe},\n\t\t{0x3f, 0x71},\n\t\t{0x40, 0xff},\n\t\t{0x41, 0xff},\n\t\t{0x42, 0xff},\n\t\t{0x43, 0xff},\n\t\t{0x44, 0xff},\n\t\t{0x45, 0xff},\n\t\t{0x46, 0xff},\n\t\t{0x47, 0xff},\n\t\t{0x48, 0xff},\n\t\t{0x49, 0xff},\n\t\t{0x4a, 0xfe},\n\t\t{0x4b, 0xff},\n\t\t{0x4c, 0x00},\n\t\t{0x4d, 0x00},\n\t\t{0x4e, 0xff},\n\t\t{0x4f, 0xff},\n\t\t{0x50, 0xff},\n\t\t{0x51, 0xff},\n\t\t{0x52, 0xff},\n\t\t{0x53, 0xff},\n\t\t{0x54, 0xff},\n\t\t{0x55, 0xff},\n\t\t{0x56, 0xff},\n\t\t{0x57, 0xff},\n\t\t{0x58, 0xff},\n\t\t{0x59, 0xff},\n\t\t{0x5a, 0xff},\n\t\t{0x5b, 0xfe},\n\t\t{0x5c, 0xff},\n\t\t{0x5d, 0x8f},\n\t\t{0x5e, 0xff},\n\t\t{0x5f, 0x8f},\n\t\t{0x60, 0xa2},\n\t\t{0x61, 0x4a},\n\t\t{0x62, 0xf3},\n\t\t{0x63, 0x75},\n\t\t{0x64, 0xf0},\n\t\t{0x65, 0x00},\n\t\t{0x66, 0x55},\n\t\t{0x67, 0x92},\n\t\t{0x68, 0xa0},\n\t\t{0x69, 0x4a},\n\t\t{0x6a, 0x22},\n\t\t{0x6b, 0x00},\n\t\t{0x6c, 0x33},\n\t\t{0x6d, 0x44},\n\t\t{0x6e, 0x22},\n\t\t{0x6f, 0x84},\n\t\t{0x70, 0x0b},\n\t\t{0x72, 0x10},\n\t\t{0x73, 0x50},\n\t\t{0x74, 0x21},\n\t\t{0x76, 0x00},\n\t\t{0x77, 0xa5},\n\t\t{0x78, 0x80},\n\t\t{0x79, 0x80},\n\t\t{0x7a, 0x80},\n\t\t{0x7b, 0xe2},\n\t\t{0x7c, 0x00},\n\t\t{0x7d, 0xf7},\n\t\t{0x7e, 0x00},\n\t\t{0x7f, 0x00},\n\t};\n\n\treg_w_buf(gspca_dev, reg_init_1, ARRAY_SIZE(reg_init_1));\n\treg_w_buf(gspca_dev, tp6810_ov_init_common,\n\t\t\tARRAY_SIZE(tp6810_ov_init_common));\n\treg_w_buf(gspca_dev, reg_init_2, ARRAY_SIZE(reg_init_2));\n\n\ti2c_w(gspca_dev, 0x12, 0x80);\t\t/* sensor reset */\n\tmsleep(10);\n\ti2c_w_buf(gspca_dev, sensor_init, ARRAY_SIZE(sensor_init));\n}",
        "static int vidtv_mux_pid_ctx_init(struct vidtv_mux *m)\n{\n\tstruct vidtv_psi_table_pat_program *p = m->si.pat->program;\n\tu16 pid;\n": "static int vidtv_mux_pid_ctx_init(struct vidtv_mux *m)\n{\n\tstruct vidtv_psi_table_pat_program *p = m->si.pat->program;\n\tu16 pid;\n\n\thash_init(m->pid_ctx);\n\t/* push the pcr pid ctx */\n\tif (!vidtv_mux_create_pid_ctx_once(m, m->pcr_pid))\n\t\treturn -ENOMEM;\n\t/* push the NULL packet pid ctx */\n\tif (!vidtv_mux_create_pid_ctx_once(m, TS_NULL_PACKET_PID))\n\t\tgoto free;\n\t/* push the PAT pid ctx */\n\tif (!vidtv_mux_create_pid_ctx_once(m, VIDTV_PAT_PID))\n\t\tgoto free;\n\t/* push the SDT pid ctx */\n\tif (!vidtv_mux_create_pid_ctx_once(m, VIDTV_SDT_PID))\n\t\tgoto free;\n\t/* push the NIT pid ctx */\n\tif (!vidtv_mux_create_pid_ctx_once(m, VIDTV_NIT_PID))\n\t\tgoto free;\n\t/* push the EIT pid ctx */\n\tif (!vidtv_mux_create_pid_ctx_once(m, VIDTV_EIT_PID))\n\t\tgoto free;\n\n\t/* add a ctx for all PMT sections */\n\twhile (p) {\n\t\tpid = vidtv_psi_get_pat_program_pid(p);\n\t\tvidtv_mux_create_pid_ctx_once(m, pid);\n\t\tp = p->next;\n\t}\n\n\treturn 0;\n\nfree:\n\tvidtv_mux_pid_ctx_destroy(m);\n\treturn -ENOMEM;\n}",
        "static int nitrox_load_fw(struct nitrox_device *ndev)\n{\n\tconst struct firmware *fw;\n\tconst char *fw_name;\n\tstruct ucode *ucode;": "static int nitrox_load_fw(struct nitrox_device *ndev)\n{\n\tconst struct firmware *fw;\n\tconst char *fw_name;\n\tstruct ucode *ucode;\n\tu64 *ucode_data;\n\tu64 offset;\n\tunion ucd_core_eid_ucode_block_num core_2_eid_val;\n\tunion aqm_grp_execmsk_lo aqm_grp_execmask_lo;\n\tunion aqm_grp_execmsk_hi aqm_grp_execmask_hi;\n\tu32 ucode_size;\n\tint ret, i = 0;\n\n\tfw_name = SE_FW;\n\tdev_info(DEV(ndev), \"Loading firmware \\\"%s\\\"\\n\", fw_name);\n\n\tret = request_firmware(&fw, fw_name, DEV(ndev));\n\tif (ret < 0) {\n\t\tdev_err(DEV(ndev), \"failed to get firmware %s\\n\", fw_name);\n\t\treturn ret;\n\t}\n\n\tucode = (struct ucode *)fw->data;\n\n\tucode_size = be32_to_cpu(ucode->code_size) * 2;\n\tif (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {\n\t\tdev_err(DEV(ndev), \"Invalid ucode size: %u for firmware %s\\n\",\n\t\t\tucode_size, fw_name);\n\t\trelease_firmware(fw);\n\t\treturn -EINVAL;\n\t}\n\tucode_data = ucode->code;\n\n\t/* copy the firmware version */\n\tmemcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2));\n\tndev->hw.fw_name[0][VERSION_LEN - 1] = '\\0';\n\n\t/* Load SE Firmware on UCD Block 0 */\n\twrite_to_ucd_unit(ndev, ucode_size, ucode_data, 0);\n\n\trelease_firmware(fw);\n\n\t/* put all SE cores in DEFAULT_SE_GROUP */\n\toffset = POM_GRP_EXECMASKX(DEFAULT_SE_GROUP);\n\tnitrox_write_csr(ndev, offset, (~0ULL));\n\n\t/* write block number and firmware length\n\t * bit:<2:0> block number\n\t * bit:3 is set SE uses 32KB microcode\n\t * bit:3 is clear SE uses 64KB microcode\n\t */\n\tcore_2_eid_val.value = 0ULL;\n\tcore_2_eid_val.ucode_blk = 0;\n\tif (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)\n\t\tcore_2_eid_val.ucode_len = 1;\n\telse\n\t\tcore_2_eid_val.ucode_len = 0;\n\n\tfor (i = 0; i < ndev->hw.se_cores; i++) {\n\t\toffset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);\n\t\tnitrox_write_csr(ndev, offset, core_2_eid_val.value);\n\t}\n\n\n\tfw_name = AE_FW;\n\tdev_info(DEV(ndev), \"Loading firmware \\\"%s\\\"\\n\", fw_name);\n\n\tret = request_firmware(&fw, fw_name, DEV(ndev));\n\tif (ret < 0) {\n\t\tdev_err(DEV(ndev), \"failed to get firmware %s\\n\", fw_name);\n\t\treturn ret;\n\t}\n\n\tucode = (struct ucode *)fw->data;\n\n\tucode_size = be32_to_cpu(ucode->code_size) * 2;\n\tif (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {\n\t\tdev_err(DEV(ndev), \"Invalid ucode size: %u for firmware %s\\n\",\n\t\t\tucode_size, fw_name);\n\t\trelease_firmware(fw);\n\t\treturn -EINVAL;\n\t}\n\tucode_data = ucode->code;\n\n\t/* copy the firmware version */\n\tmemcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2));\n\tndev->hw.fw_name[1][VERSION_LEN - 1] = '\\0';\n\n\t/* Load AE Firmware on UCD Block 2 */\n\twrite_to_ucd_unit(ndev, ucode_size, ucode_data, 2);\n\n\trelease_firmware(fw);\n\n\t/* put all AE cores in DEFAULT_AE_GROUP */\n\toffset = AQM_GRP_EXECMSK_LOX(DEFAULT_AE_GROUP);\n\taqm_grp_execmask_lo.exec_0_to_39 = 0xFFFFFFFFFFULL;\n\tnitrox_write_csr(ndev, offset, aqm_grp_execmask_lo.value);\n\toffset = AQM_GRP_EXECMSK_HIX(DEFAULT_AE_GROUP);\n\taqm_grp_execmask_hi.exec_40_to_79 = 0xFFFFFFFFFFULL;\n\tnitrox_write_csr(ndev, offset, aqm_grp_execmask_hi.value);\n\n\t/* write block number and firmware length\n\t * bit:<2:0> block number\n\t * bit:3 is set AE uses 32KB microcode\n\t * bit:3 is clear AE uses 64KB microcode\n\t */\n\tcore_2_eid_val.value = 0ULL;\n\tcore_2_eid_val.ucode_blk = 2;\n\tif (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)\n\t\tcore_2_eid_val.ucode_len = 1;\n\telse\n\t\tcore_2_eid_val.ucode_len = 0;\n\n\tfor (i = 0; i < ndev->hw.ae_cores; i++) {\n\t\toffset = UCD_AE_EID_UCODE_BLOCK_NUMX(i);\n\t\tnitrox_write_csr(ndev, offset, core_2_eid_val.value);\n\t}\n\n\treturn 0;\n}",
        "static void run_test(struct vcpu_config *c)\n{\n\tstruct kvm_vcpu_init init = { .target = -1, };\n\tint new_regs = 0, missing_regs = 0, i, n;\n\tint failed_get = 0, failed_set = 0, failed_reject = 0;": "static void run_test(struct vcpu_config *c)\n{\n\tstruct kvm_vcpu_init init = { .target = -1, };\n\tint new_regs = 0, missing_regs = 0, i, n;\n\tint failed_get = 0, failed_set = 0, failed_reject = 0;\n\tstruct kvm_vm *vm;\n\tstruct reg_sublist *s;\n\n\tcheck_supported(c);\n\n\tvm = vm_create(VM_MODE_DEFAULT, DEFAULT_GUEST_PHY_PAGES, O_RDWR);\n\tprepare_vcpu_init(c, &init);\n\taarch64_vcpu_add_default(vm, 0, &init, NULL);\n\tfinalize_vcpu(vm, 0, c);\n\n\treg_list = vcpu_get_reg_list(vm, 0);\n\n\tif (fixup_core_regs)\n\t\tcore_reg_fixup();\n\n\tif (print_list || print_filtered) {\n\t\tputchar('\\n');\n\t\tfor_each_reg(i) {\n\t\t\t__u64 id = reg_list->reg[i];\n\t\t\tif ((print_list && !filter_reg(id)) ||\n\t\t\t    (print_filtered && filter_reg(id)))\n\t\t\t\tprint_reg(c, id);\n\t\t}\n\t\tputchar('\\n');\n\t\treturn;\n\t}\n\n\t/*\n\t * We only test that we can get the register and then write back the\n\t * same value. Some registers may allow other values to be written\n\t * back, but others only allow some bits to be changed, and at least\n\t * for ID registers set will fail if the value does not exactly match\n\t * what was returned by get. If registers that allow other values to\n\t * be written need to have the other values tested, then we should\n\t * create a new set of tests for those in a new independent test\n\t * executable.\n\t */\n\tfor_each_reg(i) {\n\t\tuint8_t addr[2048 / 8];\n\t\tstruct kvm_one_reg reg = {\n\t\t\t.id = reg_list->reg[i],\n\t\t\t.addr = (__u64)&addr,\n\t\t};\n\t\tbool reject_reg = false;\n\t\tint ret;\n\n\t\tret = _vcpu_ioctl(vm, 0, KVM_GET_ONE_REG, &reg);\n\t\tif (ret) {\n\t\t\tprintf(\"%s: Failed to get \", config_name(c));\n\t\t\tprint_reg(c, reg.id);\n\t\t\tputchar('\\n');\n\t\t\t++failed_get;\n\t\t}\n\n\t\t/* rejects_set registers are rejected after KVM_ARM_VCPU_FINALIZE */\n\t\tfor_each_sublist(c, s) {\n\t\t\tif (s->rejects_set && find_reg(s->rejects_set, s->rejects_set_n, reg.id)) {\n\t\t\t\treject_reg = true;\n\t\t\t\tret = _vcpu_ioctl(vm, 0, KVM_SET_ONE_REG, &reg);\n\t\t\t\tif (ret != -1 || errno != EPERM) {\n\t\t\t\t\tprintf(\"%s: Failed to reject (ret=%d, errno=%d) \", config_name(c), ret, errno);\n\t\t\t\t\tprint_reg(c, reg.id);\n\t\t\t\t\tputchar('\\n');\n\t\t\t\t\t++failed_reject;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (!reject_reg) {\n\t\t\tret = _vcpu_ioctl(vm, 0, KVM_SET_ONE_REG, &reg);\n\t\t\tif (ret) {\n\t\t\t\tprintf(\"%s: Failed to set \", config_name(c));\n\t\t\t\tprint_reg(c, reg.id);\n\t\t\t\tputchar('\\n');\n\t\t\t\t++failed_set;\n\t\t\t}\n\t\t}\n\t}\n\n\tfor_each_sublist(c, s)\n\t\tblessed_n += s->regs_n;\n\tblessed_reg = calloc(blessed_n, sizeof(__u64));\n\n\tn = 0;\n\tfor_each_sublist(c, s) {\n\t\tfor (i = 0; i < s->regs_n; ++i)\n\t\t\tblessed_reg[n++] = s->regs[i];\n\t}\n\n\tfor_each_new_reg(i)\n\t\t++new_regs;\n\n\tfor_each_missing_reg(i)\n\t\t++missing_regs;\n\n\tif (new_regs || missing_regs) {\n\t\tn = 0;\n\t\tfor_each_reg_filtered(i)\n\t\t\t++n;\n\n\t\tprintf(\"%s: Number blessed registers: %5lld\\n\", config_name(c), blessed_n);\n\t\tprintf(\"%s: Number registers:         %5lld (includes %lld filtered registers)\\n\",\n\t\t       config_name(c), reg_list->n, reg_list->n - n);\n\t}\n\n\tif (new_regs) {\n\t\tprintf(\"\\n%s: There are %d new registers.\\n\"\n\t\t       \"Consider adding them to the blessed reg \"\n\t\t       \"list with the following lines:\\n\\n\", config_name(c), new_regs);\n\t\tfor_each_new_reg(i)\n\t\t\tprint_reg(c, reg_list->reg[i]);\n\t\tputchar('\\n');\n\t}\n\n\tif (missing_regs) {\n\t\tprintf(\"\\n%s: There are %d missing registers.\\n\"\n\t\t       \"The following lines are missing registers:\\n\\n\", config_name(c), missing_regs);\n\t\tfor_each_missing_reg(i)\n\t\t\tprint_reg(c, blessed_reg[i]);\n\t\tputchar('\\n');\n\t}\n\n\tTEST_ASSERT(!missing_regs && !failed_get && !failed_set && !failed_reject,\n\t\t    \"%s: There are %d missing registers; \"\n\t\t    \"%d registers failed get; %d registers failed set; %d registers failed reject\",\n\t\t    config_name(c), missing_regs, failed_get, failed_set, failed_reject);\n\n\tpr_info(\"%s: PASS\\n\", config_name(c));\n\tblessed_n = 0;\n\tfree(blessed_reg);\n\tfree(reg_list);\n\tkvm_vm_free(vm);\n}",
        "static int cxd2880_set_ber_per_period_t2(struct dvb_frontend *fe)\n{\n\tint ret;\n\tstruct cxd2880_priv *priv;\n\tstruct cxd2880_dvbt2_l1pre l1pre;": "static int cxd2880_set_ber_per_period_t2(struct dvb_frontend *fe)\n{\n\tint ret;\n\tstruct cxd2880_priv *priv;\n\tstruct cxd2880_dvbt2_l1pre l1pre;\n\tstruct cxd2880_dvbt2_l1post l1post;\n\tstruct cxd2880_dvbt2_plp plp;\n\tstruct cxd2880_dvbt2_bbheader bbheader;\n\tenum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;\n\tu32 pre_ber_rate = 0;\n\tu32 post_ber_rate = 0;\n\tu32 ucblock_rate = 0;\n\tu32 mes_exp = 0;\n\tu32 term_a = 0;\n\tu32 term_b = 0;\n\tu32 denominator = 0;\n\tstatic const u32 gi_tbl[7] = {32, 64, 128, 256, 8, 152, 76};\n\tstatic const u8 n_tbl[6] = {8, 2, 4, 16, 1, 1};\n\tstatic const u8 mode_tbl[6] = {2, 8, 4, 1, 16, 32};\n\tstatic const u32 kbch_tbl[2][8] = {\n\t\t{6952, 9472, 10552, 11632, 12352, 13072, 5152, 6232},\n\t\t{32128, 38608, 42960, 48328, 51568, 53760, 0, 0}\n\t};\n\n\tif (!fe) {\n\t\tpr_err(\"invalid arg\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tpriv = fe->demodulator_priv;\n\tbw = priv->dvbt2_tune_param.bandwidth;\n\n\tret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);\n\tif (ret) {\n\t\tpr_info(\"l1 pre error\\n\");\n\t\tgoto error_ber_setting;\n\t}\n\n\tret = cxd2880_tnrdmd_dvbt2_mon_active_plp(&priv->tnrdmd,\n\t\t\t\t\t\t  CXD2880_DVBT2_PLP_DATA, &plp);\n\tif (ret) {\n\t\tpr_info(\"plp info error\\n\");\n\t\tgoto error_ber_setting;\n\t}\n\n\tret = cxd2880_tnrdmd_dvbt2_mon_l1_post(&priv->tnrdmd, &l1post);\n\tif (ret) {\n\t\tpr_info(\"l1 post error\\n\");\n\t\tgoto error_ber_setting;\n\t}\n\n\tterm_a =\n\t\t(mode_tbl[l1pre.fft_mode] * (1024 + gi_tbl[l1pre.gi])) *\n\t\t(l1pre.num_symbols + n_tbl[l1pre.fft_mode]) + 2048;\n\n\tif (l1pre.mixed && l1post.fef_intvl) {\n\t\tterm_b = (l1post.fef_length + (l1post.fef_intvl / 2)) /\n\t\t\t l1post.fef_intvl;\n\t} else {\n\t\tterm_b = 0;\n\t}\n\n\tswitch (bw) {\n\tcase CXD2880_DTV_BW_1_7_MHZ:\n\t\tdenominator = ((term_a + term_b) * 71 + (131 / 2)) / 131;\n\t\tbreak;\n\tcase CXD2880_DTV_BW_5_MHZ:\n\t\tdenominator = ((term_a + term_b) * 7 + 20) / 40;\n\t\tbreak;\n\tcase CXD2880_DTV_BW_6_MHZ:\n\t\tdenominator = ((term_a + term_b) * 7 + 24) / 48;\n\t\tbreak;\n\tcase CXD2880_DTV_BW_7_MHZ:\n\t\tdenominator = ((term_a + term_b) + 4) / 8;\n\t\tbreak;\n\tcase CXD2880_DTV_BW_8_MHZ:\n\tdefault:\n\t\tdenominator = ((term_a + term_b) * 7 + 32) / 64;\n\t\tbreak;\n\t}\n\n\tif (plp.til_type && plp.til_len) {\n\t\tpre_ber_rate =\n\t\t\t(plp.num_blocks_max * 1000000 + (denominator / 2)) /\n\t\t\tdenominator;\n\t\tpre_ber_rate = (pre_ber_rate + (plp.til_len / 2)) /\n\t\t\t       plp.til_len;\n\t} else {\n\t\tpre_ber_rate =\n\t\t\t(plp.num_blocks_max * 1000000 + (denominator / 2)) /\n\t\t\tdenominator;\n\t}\n\n\tpost_ber_rate = pre_ber_rate;\n\n\tmes_exp = intlog2(pre_ber_rate) >> 24;\n\tpriv->pre_ber_interval =\n\t\t((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /\n\t\tpre_ber_rate;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,\n\t\t\t       mes_exp);\n\n\tmes_exp = intlog2(post_ber_rate) >> 24;\n\tpriv->post_ber_interval =\n\t\t((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /\n\t\tpost_ber_rate;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,\n\t\t\t       mes_exp);\n\n\tret = cxd2880_tnrdmd_dvbt2_mon_bbheader(&priv->tnrdmd,\n\t\t\t\t\t\tCXD2880_DVBT2_PLP_DATA,\n\t\t\t\t\t\t&bbheader);\n\tif (ret) {\n\t\tpr_info(\"bb header error\\n\");\n\t\tgoto error_ucblock_setting;\n\t}\n\n\tif (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_NM) {\n\t\tif (!bbheader.issy_indicator) {\n\t\t\tucblock_rate =\n\t\t\t\t(pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +\n\t\t\t\t752) / 1504;\n\t\t} else {\n\t\t\tucblock_rate =\n\t\t\t\t(pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +\n\t\t\t\t764) / 1528;\n\t\t}\n\t} else if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_HEM) {\n\t\tucblock_rate =\n\t\t\t(pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] + 748) /\n\t\t\t1496;\n\t} else {\n\t\tpr_info(\"plp mode is not Normal or HEM\\n\");\n\t\tgoto error_ucblock_setting;\n\t}\n\n\tmes_exp = intlog2(ucblock_rate) >> 24;\n\tpriv->ucblock_interval =\n\t\t((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /\n\t\tucblock_rate;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT2_PER_MES,\n\t\t\t       mes_exp);\n\n\treturn 0;\n\nerror_ber_setting:\n\tpriv->pre_ber_interval = 1000;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t\t     CXD2880_TNRDMD_CFG_DVBT2_LBER_MES, 0);\n\n\tpriv->post_ber_interval = 1000;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT2_BBER_MES, 0);\n\nerror_ucblock_setting:\n\tpriv->ucblock_interval = 1000;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT2_PER_MES, 8);\n\n\treturn 0;\n}",
        "static int fix_curseg_write_pointer(struct f2fs_sb_info *sbi, int type)\n{\n\tstruct curseg_info *cs = CURSEG_I(sbi, type);\n\tstruct f2fs_dev_info *zbd;\n\tstruct blk_zone zone;": "static int fix_curseg_write_pointer(struct f2fs_sb_info *sbi, int type)\n{\n\tstruct curseg_info *cs = CURSEG_I(sbi, type);\n\tstruct f2fs_dev_info *zbd;\n\tstruct blk_zone zone;\n\tunsigned int cs_section, wp_segno, wp_blkoff, wp_sector_off;\n\tblock_t cs_zone_block, wp_block;\n\tunsigned int log_sectors_per_block = sbi->log_blocksize - SECTOR_SHIFT;\n\tsector_t zone_sector;\n\tint err;\n\n\tcs_section = GET_SEC_FROM_SEG(sbi, cs->segno);\n\tcs_zone_block = START_BLOCK(sbi, GET_SEG_FROM_SEC(sbi, cs_section));\n\n\tzbd = get_target_zoned_dev(sbi, cs_zone_block);\n\tif (!zbd)\n\t\treturn 0;\n\n\t/* report zone for the sector the curseg points to */\n\tzone_sector = (sector_t)(cs_zone_block - zbd->start_blk)\n\t\t<< log_sectors_per_block;\n\terr = blkdev_report_zones(zbd->bdev, zone_sector, 1,\n\t\t\t\t  report_one_zone_cb, &zone);\n\tif (err != 1) {\n\t\tf2fs_err(sbi, \"Report zone failed: %s errno=(%d)\",\n\t\t\t zbd->path, err);\n\t\treturn err;\n\t}\n\n\tif (zone.type != BLK_ZONE_TYPE_SEQWRITE_REQ)\n\t\treturn 0;\n\n\twp_block = zbd->start_blk + (zone.wp >> log_sectors_per_block);\n\twp_segno = GET_SEGNO(sbi, wp_block);\n\twp_blkoff = wp_block - START_BLOCK(sbi, wp_segno);\n\twp_sector_off = zone.wp & GENMASK(log_sectors_per_block - 1, 0);\n\n\tif (cs->segno == wp_segno && cs->next_blkoff == wp_blkoff &&\n\t\twp_sector_off == 0)\n\t\treturn 0;\n\n\tf2fs_notice(sbi, \"Unaligned curseg[%d] with write pointer: \"\n\t\t    \"curseg[0x%x,0x%x] wp[0x%x,0x%x]\",\n\t\t    type, cs->segno, cs->next_blkoff, wp_segno, wp_blkoff);\n\n\tf2fs_notice(sbi, \"Assign new section to curseg[%d]: \"\n\t\t    \"curseg[0x%x,0x%x]\", type, cs->segno, cs->next_blkoff);\n\n\tf2fs_allocate_new_section(sbi, type, true);\n\n\t/* check consistency of the zone curseg pointed to */\n\tif (check_zone_write_pointer(sbi, zbd, &zone))\n\t\treturn -EIO;\n\n\t/* check newly assigned zone */\n\tcs_section = GET_SEC_FROM_SEG(sbi, cs->segno);\n\tcs_zone_block = START_BLOCK(sbi, GET_SEG_FROM_SEC(sbi, cs_section));\n\n\tzbd = get_target_zoned_dev(sbi, cs_zone_block);\n\tif (!zbd)\n\t\treturn 0;\n\n\tzone_sector = (sector_t)(cs_zone_block - zbd->start_blk)\n\t\t<< log_sectors_per_block;\n\terr = blkdev_report_zones(zbd->bdev, zone_sector, 1,\n\t\t\t\t  report_one_zone_cb, &zone);\n\tif (err != 1) {\n\t\tf2fs_err(sbi, \"Report zone failed: %s errno=(%d)\",\n\t\t\t zbd->path, err);\n\t\treturn err;\n\t}\n\n\tif (zone.type != BLK_ZONE_TYPE_SEQWRITE_REQ)\n\t\treturn 0;\n\n\tif (zone.wp != zone.start) {\n\t\tf2fs_notice(sbi,\n\t\t\t    \"New zone for curseg[%d] is not yet discarded. \"\n\t\t\t    \"Reset the zone: curseg[0x%x,0x%x]\",\n\t\t\t    type, cs->segno, cs->next_blkoff);\n\t\terr = __f2fs_issue_discard_zone(sbi, zbd->bdev,\n\t\t\t\tzone_sector >> log_sectors_per_block,\n\t\t\t\tzone.len >> log_sectors_per_block);\n\t\tif (err) {\n\t\t\tf2fs_err(sbi, \"Discard zone failed: %s (errno=%d)\",\n\t\t\t\t zbd->path, err);\n\t\t\treturn err;\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static int io_accept(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_accept *accept = &req->accept;\n\tbool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;": "static int io_accept(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_accept *accept = &req->accept;\n\tbool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;\n\tunsigned int file_flags = force_nonblock ? O_NONBLOCK : 0;\n\tbool fixed = !!accept->file_slot;\n\tstruct file *file;\n\tint ret, fd;\n\nretry:\n\tif (!fixed) {\n\t\tfd = __get_unused_fd_flags(accept->flags, accept->nofile);\n\t\tif (unlikely(fd < 0))\n\t\t\treturn fd;\n\t}\n\tfile = do_accept(req->file, file_flags, accept->addr, accept->addr_len,\n\t\t\t accept->flags);\n\tif (IS_ERR(file)) {\n\t\tif (!fixed)\n\t\t\tput_unused_fd(fd);\n\t\tret = PTR_ERR(file);\n\t\tif (ret == -EAGAIN && force_nonblock) {\n\t\t\t/*\n\t\t\t * if it's multishot and polled, we don't need to\n\t\t\t * return EAGAIN to arm the poll infra since it\n\t\t\t * has already been done\n\t\t\t */\n\t\t\tif ((req->flags & IO_APOLL_MULTI_POLLED) ==\n\t\t\t    IO_APOLL_MULTI_POLLED)\n\t\t\t\tret = 0;\n\t\t\treturn ret;\n\t\t}\n\t\tif (ret == -ERESTARTSYS)\n\t\t\tret = -EINTR;\n\t\treq_set_fail(req);\n\t} else if (!fixed) {\n\t\tfd_install(fd, file);\n\t\tret = fd;\n\t} else {\n\t\tret = io_fixed_fd_install(req, issue_flags, file,\n\t\t\t\t\t\taccept->file_slot);\n\t}\n\n\tif (!(req->flags & REQ_F_APOLL_MULTISHOT)) {\n\t\t__io_req_complete(req, issue_flags, ret, 0);\n\t\treturn 0;\n\t}\n\tif (ret >= 0) {\n\t\tbool filled;\n\n\t\tspin_lock(&ctx->completion_lock);\n\t\tfilled = io_fill_cqe_aux(ctx, req->cqe.user_data, ret,\n\t\t\t\t\t IORING_CQE_F_MORE);\n\t\tio_commit_cqring(ctx);\n\t\tspin_unlock(&ctx->completion_lock);\n\t\tif (filled) {\n\t\t\tio_cqring_ev_posted(ctx);\n\t\t\tgoto retry;\n\t\t}\n\t\tret = -ECANCELED;\n\t}\n\n\treturn ret;\n}",
        "static int intel_reg_show(struct seq_file *s_file, void *data)\n{\n\tstruct sdw_intel *sdw = s_file->private;\n\tvoid __iomem *s = sdw->link_res->shim;\n\tvoid __iomem *a = sdw->link_res->alh;": "static int intel_reg_show(struct seq_file *s_file, void *data)\n{\n\tstruct sdw_intel *sdw = s_file->private;\n\tvoid __iomem *s = sdw->link_res->shim;\n\tvoid __iomem *a = sdw->link_res->alh;\n\tchar *buf;\n\tssize_t ret;\n\tint i, j;\n\tunsigned int links, reg;\n\n\tbuf = kzalloc(RD_BUF, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tlinks = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);\n\n\tret = scnprintf(buf, RD_BUF, \"Register  Value\\n\");\n\tret += scnprintf(buf + ret, RD_BUF - ret, \"\\nShim\\n\");\n\n\tfor (i = 0; i < links; i++) {\n\t\treg = SDW_SHIM_LCAP + i * 4;\n\t\tret += intel_sprintf(s, true, buf, ret, reg);\n\t}\n\n\tfor (i = 0; i < links; i++) {\n\t\tret += scnprintf(buf + ret, RD_BUF - ret, \"\\nLink%d\\n\", i);\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));\n\n\t\tret += scnprintf(buf + ret, RD_BUF - ret, \"\\n PCMSyCH registers\\n\");\n\n\t\t/*\n\t\t * the value 10 is the number of PDIs. We will need a\n\t\t * cleanup to remove hard-coded Intel configurations\n\t\t * from cadence_master.c\n\t\t */\n\t\tfor (j = 0; j < 10; j++) {\n\t\t\tret += intel_sprintf(s, false, buf, ret,\n\t\t\t\t\tSDW_SHIM_PCMSYCHM(i, j));\n\t\t\tret += intel_sprintf(s, false, buf, ret,\n\t\t\t\t\tSDW_SHIM_PCMSYCHC(i, j));\n\t\t}\n\t\tret += scnprintf(buf + ret, RD_BUF - ret, \"\\n PDMSCAP, IOCTL, CTMCTL\\n\");\n\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));\n\t\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));\n\t}\n\n\tret += scnprintf(buf + ret, RD_BUF - ret, \"\\nWake registers\\n\");\n\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);\n\tret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);\n\n\tret += scnprintf(buf + ret, RD_BUF - ret, \"\\nALH STRMzCFG\\n\");\n\tfor (i = 0; i < SDW_ALH_NUM_STREAMS; i++)\n\t\tret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));\n\n\tseq_printf(s_file, \"%s\", buf);\n\tkfree(buf);\n\n\treturn 0;\n}",
        "static int init_hash_table(struct pxa168_eth_private *pep)\n{\n\t/*\n\t * Hardware expects CPU to build a hash table based on a predefined\n\t * hash function and populate it based on hardware address. The": "static int init_hash_table(struct pxa168_eth_private *pep)\n{\n\t/*\n\t * Hardware expects CPU to build a hash table based on a predefined\n\t * hash function and populate it based on hardware address. The\n\t * location of the hash table is identified by 32-bit pointer stored\n\t * in HTPR internal register. Two possible sizes exists for the hash\n\t * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB\n\t * (16kB of DRAM required (4 x 4 kB banks)).We currently only support\n\t * 1/2kB.\n\t */\n\t/* TODO: Add support for 8kB hash table and alternative hash\n\t * function.Driver can dynamically switch to them if the 1/2kB hash\n\t * table is full.\n\t */\n\tif (!pep->htpr) {\n\t\tpep->htpr = dma_alloc_coherent(pep->dev->dev.parent,\n\t\t\t\t\t       HASH_ADDR_TABLE_SIZE,\n\t\t\t\t\t       &pep->htpr_dma, GFP_KERNEL);\n\t\tif (!pep->htpr)\n\t\t\treturn -ENOMEM;\n\t} else {\n\t\tmemset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);\n\t}\n\twrl(pep, HTPR, pep->htpr_dma);\n\treturn 0;\n}",
        "static void xdp_test_run_init_page(struct page *page, void *arg)\n{\n\tstruct xdp_page_head *head = phys_to_virt(page_to_phys(page));\n\tstruct xdp_buff *new_ctx, *orig_ctx;\n\tu32 headroom = XDP_PACKET_HEADROOM;": "static void xdp_test_run_init_page(struct page *page, void *arg)\n{\n\tstruct xdp_page_head *head = phys_to_virt(page_to_phys(page));\n\tstruct xdp_buff *new_ctx, *orig_ctx;\n\tu32 headroom = XDP_PACKET_HEADROOM;\n\tstruct xdp_test_data *xdp = arg;\n\tsize_t frm_len, meta_len;\n\tstruct xdp_frame *frm;\n\tvoid *data;\n\n\torig_ctx = xdp->orig_ctx;\n\tfrm_len = orig_ctx->data_end - orig_ctx->data_meta;\n\tmeta_len = orig_ctx->data - orig_ctx->data_meta;\n\theadroom -= meta_len;\n\n\tnew_ctx = &head->ctx;\n\tfrm = &head->frm;\n\tdata = &head->data;\n\tmemcpy(data + headroom, orig_ctx->data_meta, frm_len);\n\n\txdp_init_buff(new_ctx, TEST_XDP_FRAME_SIZE, &xdp->rxq);\n\txdp_prepare_buff(new_ctx, data, headroom, frm_len, true);\n\tnew_ctx->data = new_ctx->data_meta + meta_len;\n\n\txdp_update_frame_from_buff(new_ctx, frm);\n\tfrm->mem = new_ctx->rxq->mem;\n\n\tmemcpy(&head->orig_ctx, new_ctx, sizeof(head->orig_ctx));\n}",
        "static const struct perf_dlfilter_al *dlfilter__resolve_ip(void *ctx)\n{\n\tstruct dlfilter *d = (struct dlfilter *)ctx;\n\tstruct perf_dlfilter_al *d_al = d->d_ip_al;\n\tstruct addr_location *al;": "static const struct perf_dlfilter_al *dlfilter__resolve_ip(void *ctx)\n{\n\tstruct dlfilter *d = (struct dlfilter *)ctx;\n\tstruct perf_dlfilter_al *d_al = d->d_ip_al;\n\tstruct addr_location *al;\n\n\tif (!d->ctx_valid)\n\t\treturn NULL;\n\n\t/* 'size' is also used to indicate already initialized */\n\tif (d_al->size)\n\t\treturn d_al;\n\n\tal = get_al(d);\n\tif (!al)\n\t\treturn NULL;\n\n\tal_to_d_al(al, d_al);\n\n\td_al->is_kernel_ip = machine__kernel_ip(d->machine, d->sample->ip);\n\td_al->comm = al->thread ? thread__comm_str(al->thread) : \":-1\";\n\td_al->filtered = al->filtered;\n\n\treturn d_al;\n}",
        "static int diag_get(struct bpf_local_storage_data *sdata, struct sk_buff *skb)\n{\n\tstruct nlattr *nla_stg, *nla_value;\n\tstruct bpf_local_storage_map *smap;\n": "static int diag_get(struct bpf_local_storage_data *sdata, struct sk_buff *skb)\n{\n\tstruct nlattr *nla_stg, *nla_value;\n\tstruct bpf_local_storage_map *smap;\n\n\t/* It cannot exceed max nlattr's payload */\n\tBUILD_BUG_ON(U16_MAX - NLA_HDRLEN < BPF_LOCAL_STORAGE_MAX_VALUE_SIZE);\n\n\tnla_stg = nla_nest_start(skb, SK_DIAG_BPF_STORAGE);\n\tif (!nla_stg)\n\t\treturn -EMSGSIZE;\n\n\tsmap = rcu_dereference(sdata->smap);\n\tif (nla_put_u32(skb, SK_DIAG_BPF_STORAGE_MAP_ID, smap->map.id))\n\t\tgoto errout;\n\n\tnla_value = nla_reserve_64bit(skb, SK_DIAG_BPF_STORAGE_MAP_VALUE,\n\t\t\t\t      smap->map.value_size,\n\t\t\t\t      SK_DIAG_BPF_STORAGE_PAD);\n\tif (!nla_value)\n\t\tgoto errout;\n\n\tif (map_value_has_spin_lock(&smap->map))\n\t\tcopy_map_value_locked(&smap->map, nla_data(nla_value),\n\t\t\t\t      sdata->data, true);\n\telse\n\t\tcopy_map_value(&smap->map, nla_data(nla_value), sdata->data);\n\n\tnla_nest_end(skb, nla_stg);\n\treturn 0;\n\nerrout:\n\tnla_nest_cancel(skb, nla_stg);\n\treturn -EMSGSIZE;\n}",
        "static bool _wait_barrier(struct r1conf *conf, int idx, bool nowait)\n{\n\tbool ret = true;\n\n\t/*": "static bool _wait_barrier(struct r1conf *conf, int idx, bool nowait)\n{\n\tbool ret = true;\n\n\t/*\n\t * We need to increase conf->nr_pending[idx] very early here,\n\t * then raise_barrier() can be blocked when it waits for\n\t * conf->nr_pending[idx] to be 0. Then we can avoid holding\n\t * conf->resync_lock when there is no barrier raised in same\n\t * barrier unit bucket. Also if the array is frozen, I/O\n\t * should be blocked until array is unfrozen.\n\t */\n\tatomic_inc(&conf->nr_pending[idx]);\n\t/*\n\t * In _wait_barrier() we firstly increase conf->nr_pending[idx], then\n\t * check conf->barrier[idx]. In raise_barrier() we firstly increase\n\t * conf->barrier[idx], then check conf->nr_pending[idx]. A memory\n\t * barrier is necessary here to make sure conf->barrier[idx] won't be\n\t * fetched before conf->nr_pending[idx] is increased. Otherwise there\n\t * will be a race between _wait_barrier() and raise_barrier().\n\t */\n\tsmp_mb__after_atomic();\n\n\t/*\n\t * Don't worry about checking two atomic_t variables at same time\n\t * here. If during we check conf->barrier[idx], the array is\n\t * frozen (conf->array_frozen is 1), and chonf->barrier[idx] is\n\t * 0, it is safe to return and make the I/O continue. Because the\n\t * array is frozen, all I/O returned here will eventually complete\n\t * or be queued, no race will happen. See code comment in\n\t * frozen_array().\n\t */\n\tif (!READ_ONCE(conf->array_frozen) &&\n\t    !atomic_read(&conf->barrier[idx]))\n\t\treturn ret;\n\n\t/*\n\t * After holding conf->resync_lock, conf->nr_pending[idx]\n\t * should be decreased before waiting for barrier to drop.\n\t * Otherwise, we may encounter a race condition because\n\t * raise_barrer() might be waiting for conf->nr_pending[idx]\n\t * to be 0 at same time.\n\t */\n\tspin_lock_irq(&conf->resync_lock);\n\tatomic_inc(&conf->nr_waiting[idx]);\n\tatomic_dec(&conf->nr_pending[idx]);\n\t/*\n\t * In case freeze_array() is waiting for\n\t * get_unqueued_pending() == extra\n\t */\n\twake_up(&conf->wait_barrier);\n\t/* Wait for the barrier in same barrier unit bucket to drop. */\n\n\t/* Return false when nowait flag is set */\n\tif (nowait) {\n\t\tret = false;\n\t} else {\n\t\twait_event_lock_irq(conf->wait_barrier,\n\t\t\t\t!conf->array_frozen &&\n\t\t\t\t!atomic_read(&conf->barrier[idx]),\n\t\t\t\tconf->resync_lock);\n\t\tatomic_inc(&conf->nr_pending[idx]);\n\t}\n\n\tatomic_dec(&conf->nr_waiting[idx]);\n\tspin_unlock_irq(&conf->resync_lock);\n\treturn ret;\n}",
        "static void ww_test_edeadlk_acquire_wrong_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_acquire_wrong_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\to2.ctx = &t2;\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\tif (!ret)\n\t\tWWU(&o2);\n\n\tWWU(&o);\n\n\tww_mutex_lock_slow(&o3, &t);\n}",
        "static int es58x_fd_enable_channel(struct es58x_priv *priv)\n{\n\tstruct es58x_device *es58x_dev = priv->es58x_dev;\n\tstruct net_device *netdev = es58x_dev->netdev[priv->channel_idx];\n\tstruct es58x_fd_tx_conf_msg tx_conf_msg = { 0 };": "static int es58x_fd_enable_channel(struct es58x_priv *priv)\n{\n\tstruct es58x_device *es58x_dev = priv->es58x_dev;\n\tstruct net_device *netdev = es58x_dev->netdev[priv->channel_idx];\n\tstruct es58x_fd_tx_conf_msg tx_conf_msg = { 0 };\n\tu32 ctrlmode;\n\tsize_t conf_len = 0;\n\n\tes58x_fd_convert_bittiming(&tx_conf_msg.nominal_bittiming,\n\t\t\t\t   &priv->can.bittiming);\n\tctrlmode = priv->can.ctrlmode;\n\n\tif (ctrlmode & CAN_CTRLMODE_3_SAMPLES)\n\t\ttx_conf_msg.samples_per_bit = ES58X_SAMPLES_PER_BIT_THREE;\n\telse\n\t\ttx_conf_msg.samples_per_bit = ES58X_SAMPLES_PER_BIT_ONE;\n\ttx_conf_msg.sync_edge = ES58X_SYNC_EDGE_SINGLE;\n\ttx_conf_msg.physical_layer = ES58X_PHYSICAL_LAYER_HIGH_SPEED;\n\ttx_conf_msg.echo_mode = ES58X_ECHO_ON;\n\tif (ctrlmode & CAN_CTRLMODE_LISTENONLY)\n\t\ttx_conf_msg.ctrlmode |= ES58X_FD_CTRLMODE_PASSIVE;\n\telse\n\t\ttx_conf_msg.ctrlmode |=  ES58X_FD_CTRLMODE_ACTIVE;\n\n\tif (ctrlmode & CAN_CTRLMODE_FD_NON_ISO) {\n\t\ttx_conf_msg.ctrlmode |= ES58X_FD_CTRLMODE_FD_NON_ISO;\n\t\ttx_conf_msg.canfd_enabled = 1;\n\t} else if (ctrlmode & CAN_CTRLMODE_FD) {\n\t\ttx_conf_msg.ctrlmode |= ES58X_FD_CTRLMODE_FD;\n\t\ttx_conf_msg.canfd_enabled = 1;\n\t}\n\n\tif (tx_conf_msg.canfd_enabled) {\n\t\tes58x_fd_convert_bittiming(&tx_conf_msg.data_bittiming,\n\t\t\t\t\t   &priv->can.data_bittiming);\n\n\t\tif (can_tdc_is_enabled(&priv->can)) {\n\t\t\ttx_conf_msg.tdc_enabled = 1;\n\t\t\ttx_conf_msg.tdco = cpu_to_le16(priv->can.tdc.tdco);\n\t\t\ttx_conf_msg.tdcf = cpu_to_le16(priv->can.tdc.tdcf);\n\t\t}\n\n\t\tconf_len = ES58X_FD_CANFD_CONF_LEN;\n\t} else {\n\t\tconf_len = ES58X_FD_CAN_CONF_LEN;\n\t}\n\n\treturn es58x_send_msg(es58x_dev, es58x_fd_cmd_type(netdev),\n\t\t\t      ES58X_FD_CAN_CMD_ID_ENABLE_CHANNEL,\n\t\t\t      &tx_conf_msg, conf_len, priv->channel_idx);\n}",
        "static int cfg80211_scan_6ghz(struct cfg80211_registered_device *rdev)\n{\n\tu8 i;\n\tstruct cfg80211_colocated_ap *ap;\n\tint n_channels, count = 0, err;": "static int cfg80211_scan_6ghz(struct cfg80211_registered_device *rdev)\n{\n\tu8 i;\n\tstruct cfg80211_colocated_ap *ap;\n\tint n_channels, count = 0, err;\n\tstruct cfg80211_scan_request *request, *rdev_req = rdev->scan_req;\n\tLIST_HEAD(coloc_ap_list);\n\tbool need_scan_psc = true;\n\tconst struct ieee80211_sband_iftype_data *iftd;\n\n\trdev_req->scan_6ghz = true;\n\n\tif (!rdev->wiphy.bands[NL80211_BAND_6GHZ])\n\t\treturn -EOPNOTSUPP;\n\n\tiftd = ieee80211_get_sband_iftype_data(rdev->wiphy.bands[NL80211_BAND_6GHZ],\n\t\t\t\t\t       rdev_req->wdev->iftype);\n\tif (!iftd || !iftd->he_cap.has_he)\n\t\treturn -EOPNOTSUPP;\n\n\tn_channels = rdev->wiphy.bands[NL80211_BAND_6GHZ]->n_channels;\n\n\tif (rdev_req->flags & NL80211_SCAN_FLAG_COLOCATED_6GHZ) {\n\t\tstruct cfg80211_internal_bss *intbss;\n\n\t\tspin_lock_bh(&rdev->bss_lock);\n\t\tlist_for_each_entry(intbss, &rdev->bss_list, list) {\n\t\t\tstruct cfg80211_bss *res = &intbss->pub;\n\t\t\tconst struct cfg80211_bss_ies *ies;\n\n\t\t\ties = rcu_access_pointer(res->ies);\n\t\t\tcount += cfg80211_parse_colocated_ap(ies,\n\t\t\t\t\t\t\t     &coloc_ap_list);\n\t\t}\n\t\tspin_unlock_bh(&rdev->bss_lock);\n\t}\n\n\trequest = kzalloc(struct_size(request, channels, n_channels) +\n\t\t\t  sizeof(*request->scan_6ghz_params) * count +\n\t\t\t  sizeof(*request->ssids) * rdev_req->n_ssids,\n\t\t\t  GFP_KERNEL);\n\tif (!request) {\n\t\tcfg80211_free_coloc_ap_list(&coloc_ap_list);\n\t\treturn -ENOMEM;\n\t}\n\n\t*request = *rdev_req;\n\trequest->n_channels = 0;\n\trequest->scan_6ghz_params =\n\t\t(void *)&request->channels[n_channels];\n\n\t/*\n\t * PSC channels should not be scanned in case of direct scan with 1 SSID\n\t * and at least one of the reported co-located APs with same SSID\n\t * indicating that all APs in the same ESS are co-located\n\t */\n\tif (count && request->n_ssids == 1 && request->ssids[0].ssid_len) {\n\t\tlist_for_each_entry(ap, &coloc_ap_list, list) {\n\t\t\tif (ap->colocated_ess &&\n\t\t\t    cfg80211_find_ssid_match(ap, request)) {\n\t\t\t\tneed_scan_psc = false;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\n\t * add to the scan request the channels that need to be scanned\n\t * regardless of the collocated APs (PSC channels or all channels\n\t * in case that NL80211_SCAN_FLAG_COLOCATED_6GHZ is not set)\n\t */\n\tfor (i = 0; i < rdev_req->n_channels; i++) {\n\t\tif (rdev_req->channels[i]->band == NL80211_BAND_6GHZ &&\n\t\t    ((need_scan_psc &&\n\t\t      cfg80211_channel_is_psc(rdev_req->channels[i])) ||\n\t\t     !(rdev_req->flags & NL80211_SCAN_FLAG_COLOCATED_6GHZ))) {\n\t\t\tcfg80211_scan_req_add_chan(request,\n\t\t\t\t\t\t   rdev_req->channels[i],\n\t\t\t\t\t\t   false);\n\t\t}\n\t}\n\n\tif (!(rdev_req->flags & NL80211_SCAN_FLAG_COLOCATED_6GHZ))\n\t\tgoto skip;\n\n\tlist_for_each_entry(ap, &coloc_ap_list, list) {\n\t\tbool found = false;\n\t\tstruct cfg80211_scan_6ghz_params *scan_6ghz_params =\n\t\t\t&request->scan_6ghz_params[request->n_6ghz_params];\n\t\tstruct ieee80211_channel *chan =\n\t\t\tieee80211_get_channel(&rdev->wiphy, ap->center_freq);\n\n\t\tif (!chan || chan->flags & IEEE80211_CHAN_DISABLED)\n\t\t\tcontinue;\n\n\t\tfor (i = 0; i < rdev_req->n_channels; i++) {\n\t\t\tif (rdev_req->channels[i] == chan)\n\t\t\t\tfound = true;\n\t\t}\n\n\t\tif (!found)\n\t\t\tcontinue;\n\n\t\tif (request->n_ssids > 0 &&\n\t\t    !cfg80211_find_ssid_match(ap, request))\n\t\t\tcontinue;\n\n\t\tif (!request->n_ssids && ap->multi_bss && !ap->transmitted_bssid)\n\t\t\tcontinue;\n\n\t\tcfg80211_scan_req_add_chan(request, chan, true);\n\t\tmemcpy(scan_6ghz_params->bssid, ap->bssid, ETH_ALEN);\n\t\tscan_6ghz_params->short_ssid = ap->short_ssid;\n\t\tscan_6ghz_params->short_ssid_valid = ap->short_ssid_valid;\n\t\tscan_6ghz_params->unsolicited_probe = ap->unsolicited_probe;\n\n\t\t/*\n\t\t * If a PSC channel is added to the scan and 'need_scan_psc' is\n\t\t * set to false, then all the APs that the scan logic is\n\t\t * interested with on the channel are collocated and thus there\n\t\t * is no need to perform the initial PSC channel listen.\n\t\t */\n\t\tif (cfg80211_channel_is_psc(chan) && !need_scan_psc)\n\t\t\tscan_6ghz_params->psc_no_listen = true;\n\n\t\trequest->n_6ghz_params++;\n\t}\n\nskip:\n\tcfg80211_free_coloc_ap_list(&coloc_ap_list);\n\n\tif (request->n_channels) {\n\t\tstruct cfg80211_scan_request *old = rdev->int_scan_req;\n\t\trdev->int_scan_req = request;\n\n\t\t/*\n\t\t * Add the ssids from the parent scan request to the new scan\n\t\t * request, so the driver would be able to use them in its\n\t\t * probe requests to discover hidden APs on PSC channels.\n\t\t */\n\t\trequest->ssids = (void *)&request->channels[request->n_channels];\n\t\trequest->n_ssids = rdev_req->n_ssids;\n\t\tmemcpy(request->ssids, rdev_req->ssids, sizeof(*request->ssids) *\n\t\t       request->n_ssids);\n\n\t\t/*\n\t\t * If this scan follows a previous scan, save the scan start\n\t\t * info from the first part of the scan\n\t\t */\n\t\tif (old)\n\t\t\trdev->int_scan_req->info = old->info;\n\n\t\terr = rdev_scan(rdev, request);\n\t\tif (err) {\n\t\t\trdev->int_scan_req = old;\n\t\t\tkfree(request);\n\t\t} else {\n\t\t\tkfree(old);\n\t\t}\n\n\t\treturn err;\n\t}\n\n\tkfree(request);\n\treturn -EINVAL;\n}",
        "static void mess_with_syscall(pid_t testpid, enum ptrace_pass pass)\n{\n\tstruct user_regs_struct regs;\n\n\tsh->probing_syscall = false; /* Do this on entry only */": "static void mess_with_syscall(pid_t testpid, enum ptrace_pass pass)\n{\n\tstruct user_regs_struct regs;\n\n\tsh->probing_syscall = false; /* Do this on entry only */\n\n\t/* For these, don't even getregs */\n\tif (pass == PTP_NOTHING || pass == PTP_DONE)\n\t\treturn;\n\n\tptrace(PTRACE_GETREGS, testpid, NULL, &regs);\n\n\tif (regs.orig_rax != regs.rbx) {\n\t\tfail(\"orig_rax %#llx doesn't match syscall number %#llx\\n\",\n\t\t     (unsigned long long)regs.orig_rax,\n\t\t     (unsigned long long)regs.rbx);\n\t}\n\n\tswitch (pass) {\n\tcase PTP_GETREGS:\n\t\t/* Just read, no writeback */\n\t\treturn;\n\tcase PTP_WRITEBACK:\n\t\t/* Write back the same register state verbatim */\n\t\tbreak;\n\tcase PTP_FUZZRET:\n\t\tregs.rax = MODIFIED_BY_PTRACE;\n\t\tbreak;\n\tcase PTP_FUZZHIGH:\n\t\tregs.rax = MODIFIED_BY_PTRACE;\n\t\tregs.orig_rax = regs.orig_rax | 0xffffffff00000000ULL;\n\t\tbreak;\n\tcase PTP_INTNUM:\n\t\tregs.rax = MODIFIED_BY_PTRACE;\n\t\tregs.orig_rax = (int)regs.orig_rax;\n\t\tbreak;\n\tdefault:\n\t\tcrit(\"invalid ptrace_pass\\n\");\n\t\tbreak;\n\t}\n\n\tptrace(PTRACE_SETREGS, testpid, NULL, &regs);\n}",
        "static int parse_var_defs(struct hist_trigger_data *hist_data)\n{\n\tstruct trace_array *tr = hist_data->event_file->tr;\n\tchar *s, *str, *var_name, *field_str;\n\tunsigned int i, j, n_vars = 0;": "static int parse_var_defs(struct hist_trigger_data *hist_data)\n{\n\tstruct trace_array *tr = hist_data->event_file->tr;\n\tchar *s, *str, *var_name, *field_str;\n\tunsigned int i, j, n_vars = 0;\n\tint ret = 0;\n\n\tfor (i = 0; i < hist_data->attrs->n_assignments; i++) {\n\t\tstr = hist_data->attrs->assignment_str[i];\n\t\tfor (j = 0; j < TRACING_MAP_VARS_MAX; j++) {\n\t\t\tfield_str = strsep(&str, \",\");\n\t\t\tif (!field_str)\n\t\t\t\tbreak;\n\n\t\t\tvar_name = strsep(&field_str, \"=\");\n\t\t\tif (!var_name || !field_str) {\n\t\t\t\thist_err(tr, HIST_ERR_MALFORMED_ASSIGNMENT,\n\t\t\t\t\t errpos(var_name));\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto free;\n\t\t\t}\n\n\t\t\tif (n_vars == TRACING_MAP_VARS_MAX) {\n\t\t\t\thist_err(tr, HIST_ERR_TOO_MANY_VARS, errpos(var_name));\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto free;\n\t\t\t}\n\n\t\t\ts = kstrdup(var_name, GFP_KERNEL);\n\t\t\tif (!s) {\n\t\t\t\tret = -ENOMEM;\n\t\t\t\tgoto free;\n\t\t\t}\n\t\t\thist_data->attrs->var_defs.name[n_vars] = s;\n\n\t\t\ts = kstrdup(field_str, GFP_KERNEL);\n\t\t\tif (!s) {\n\t\t\t\tret = -ENOMEM;\n\t\t\t\tgoto free;\n\t\t\t}\n\t\t\thist_data->attrs->var_defs.expr[n_vars++] = s;\n\n\t\t\thist_data->attrs->var_defs.n_vars = n_vars;\n\t\t}\n\t}\n\n\treturn ret;\n free:\n\tfree_var_defs(hist_data);\n\n\treturn ret;\n}",
        "static int rvu_dbg_cpt_engines_info_display(struct seq_file *filp, void *unused)\n{\n\tstruct cpt_ctx *ctx = filp->private;\n\tu16 max_ses, max_ies, max_aes;\n\tstruct rvu *rvu = ctx->rvu;": "static int rvu_dbg_cpt_engines_info_display(struct seq_file *filp, void *unused)\n{\n\tstruct cpt_ctx *ctx = filp->private;\n\tu16 max_ses, max_ies, max_aes;\n\tstruct rvu *rvu = ctx->rvu;\n\tint blkaddr = ctx->blkaddr;\n\tu32 e_max, e;\n\tu64 reg;\n\n\treg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1);\n\tmax_ses = reg & 0xffff;\n\tmax_ies = (reg >> 16) & 0xffff;\n\tmax_aes = (reg >> 32) & 0xffff;\n\n\te_max = max_ses + max_ies + max_aes;\n\n\tseq_puts(filp, \"===========================================\\n\");\n\tfor (e = 0; e < e_max; e++) {\n\t\treg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(e));\n\t\tseq_printf(filp, \"CPT Engine[%u] Group Enable   0x%02llx\\n\", e,\n\t\t\t   reg & 0xff);\n\t\treg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_ACTIVE(e));\n\t\tseq_printf(filp, \"CPT Engine[%u] Active Info    0x%llx\\n\", e,\n\t\t\t   reg);\n\t\treg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL(e));\n\t\tseq_printf(filp, \"CPT Engine[%u] Control        0x%llx\\n\", e,\n\t\t\t   reg);\n\t\tseq_puts(filp, \"===========================================\\n\");\n\t}\n\treturn 0;\n}",
        "static void mtip_detect_product(struct driver_data *dd)\n{\n\tu32 hwdata;\n\tunsigned int rev, slotgroups;\n": "static void mtip_detect_product(struct driver_data *dd)\n{\n\tu32 hwdata;\n\tunsigned int rev, slotgroups;\n\n\t/*\n\t * HBA base + 0xFC [15:0] - vendor-specific hardware interface\n\t * info register:\n\t * [15:8] hardware/software interface rev#\n\t * [   3] asic-style interface\n\t * [ 2:0] number of slot groups, minus 1 (only valid for asic-style).\n\t */\n\thwdata = readl(dd->mmio + HOST_HSORG);\n\n\tdd->product_type = MTIP_PRODUCT_UNKNOWN;\n\tdd->slot_groups = 1;\n\n\tif (hwdata & 0x8) {\n\t\tdd->product_type = MTIP_PRODUCT_ASICFPGA;\n\t\trev = (hwdata & HSORG_HWREV) >> 8;\n\t\tslotgroups = (hwdata & HSORG_SLOTGROUPS) + 1;\n\t\tdev_info(&dd->pdev->dev,\n\t\t\t\"ASIC-FPGA design, HS rev 0x%x, \"\n\t\t\t\"%i slot groups [%i slots]\\n\",\n\t\t\t rev,\n\t\t\t slotgroups,\n\t\t\t slotgroups * 32);\n\n\t\tif (slotgroups > MTIP_MAX_SLOT_GROUPS) {\n\t\t\tdev_warn(&dd->pdev->dev,\n\t\t\t\t\"Warning: driver only supports \"\n\t\t\t\t\"%i slot groups.\\n\", MTIP_MAX_SLOT_GROUPS);\n\t\t\tslotgroups = MTIP_MAX_SLOT_GROUPS;\n\t\t}\n\t\tdd->slot_groups = slotgroups;\n\t\treturn;\n\t}\n\n\tdev_warn(&dd->pdev->dev, \"Unrecognized product id\\n\");\n}",
        "static int mana_gd_detect_devices(struct pci_dev *pdev)\n{\n\tstruct gdma_context *gc = pci_get_drvdata(pdev);\n\tstruct gdma_list_devices_resp resp = {};\n\tstruct gdma_general_req req = {};": "static int mana_gd_detect_devices(struct pci_dev *pdev)\n{\n\tstruct gdma_context *gc = pci_get_drvdata(pdev);\n\tstruct gdma_list_devices_resp resp = {};\n\tstruct gdma_general_req req = {};\n\tstruct gdma_dev_id dev;\n\tu32 i, max_num_devs;\n\tu16 dev_type;\n\tint err;\n\n\tmana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req),\n\t\t\t     sizeof(resp));\n\n\terr = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);\n\tif (err || resp.hdr.status) {\n\t\tdev_err(gc->dev, \"Failed to detect devices: %d, 0x%x\\n\", err,\n\t\t\tresp.hdr.status);\n\t\treturn err ? err : -EPROTO;\n\t}\n\n\tmax_num_devs = min_t(u32, MAX_NUM_GDMA_DEVICES, resp.num_of_devs);\n\n\tfor (i = 0; i < max_num_devs; i++) {\n\t\tdev = resp.devs[i];\n\t\tdev_type = dev.type;\n\n\t\t/* HWC is already detected in mana_hwc_create_channel(). */\n\t\tif (dev_type == GDMA_DEVICE_HWC)\n\t\t\tcontinue;\n\n\t\tif (dev_type == GDMA_DEVICE_MANA) {\n\t\t\tgc->mana.gdma_context = gc;\n\t\t\tgc->mana.dev_id = dev;\n\t\t}\n\t}\n\n\treturn gc->mana.dev_id.type == 0 ? -ENODEV : 0;\n}",
        "static void dytc_profile_refresh(struct ideapad_private *priv)\n{\n\tenum platform_profile_option profile;\n\tunsigned long output;\n\tint err, perfmode;": "static void dytc_profile_refresh(struct ideapad_private *priv)\n{\n\tenum platform_profile_option profile;\n\tunsigned long output;\n\tint err, perfmode;\n\n\tmutex_lock(&priv->dytc->mutex);\n\terr = dytc_cql_command(priv, DYTC_CMD_GET, &output);\n\tmutex_unlock(&priv->dytc->mutex);\n\tif (err)\n\t\treturn;\n\n\tperfmode = (output >> DYTC_GET_MODE_BIT) & 0xF;\n\n\tif (convert_dytc_to_profile(perfmode, &profile))\n\t\treturn;\n\n\tif (profile != priv->dytc->current_profile) {\n\t\tpriv->dytc->current_profile = profile;\n\t\tplatform_profile_notify();\n\t}\n}",
        "static void hub_power_on(struct usb_hub *hub, bool do_delay)\n{\n\tint port1;\n\n\t/* Enable power on each port.  Some hubs have reserved values": "static void hub_power_on(struct usb_hub *hub, bool do_delay)\n{\n\tint port1;\n\n\t/* Enable power on each port.  Some hubs have reserved values\n\t * of LPSM (> 2) in their descriptors, even though they are\n\t * USB 2.0 hubs.  Some hubs do not implement port-power switching\n\t * but only emulate it.  In all cases, the ports won't work\n\t * unless we send these messages to the hub.\n\t */\n\tif (hub_is_port_power_switchable(hub))\n\t\tdev_dbg(hub->intfdev, \"enabling power on all ports\\n\");\n\telse\n\t\tdev_dbg(hub->intfdev, \"trying to enable port power on \"\n\t\t\t\t\"non-switchable hub\\n\");\n\tfor (port1 = 1; port1 <= hub->hdev->maxchild; port1++)\n\t\tif (test_bit(port1, hub->power_bits))\n\t\t\tset_port_feature(hub->hdev, port1, USB_PORT_FEAT_POWER);\n\t\telse\n\t\t\tusb_clear_port_feature(hub->hdev, port1,\n\t\t\t\t\t\tUSB_PORT_FEAT_POWER);\n\tif (do_delay)\n\t\tmsleep(hub_power_on_good_delay(hub));\n}",
        "static void update_tasks_nodemask(struct cpuset *cs)\n{\n\tstatic nodemask_t newmems;\t/* protected by cpuset_rwsem */\n\tstruct css_task_iter it;\n\tstruct task_struct *task;": "static void update_tasks_nodemask(struct cpuset *cs)\n{\n\tstatic nodemask_t newmems;\t/* protected by cpuset_rwsem */\n\tstruct css_task_iter it;\n\tstruct task_struct *task;\n\n\tcpuset_being_rebound = cs;\t\t/* causes mpol_dup() rebind */\n\n\tguarantee_online_mems(cs, &newmems);\n\n\t/*\n\t * The mpol_rebind_mm() call takes mmap_lock, which we couldn't\n\t * take while holding tasklist_lock.  Forks can happen - the\n\t * mpol_dup() cpuset_being_rebound check will catch such forks,\n\t * and rebind their vma mempolicies too.  Because we still hold\n\t * the global cpuset_rwsem, we know that no other rebind effort\n\t * will be contending for the global variable cpuset_being_rebound.\n\t * It's ok if we rebind the same mm twice; mpol_rebind_mm()\n\t * is idempotent.  Also migrate pages in each mm to new nodes.\n\t */\n\tcss_task_iter_start(&cs->css, 0, &it);\n\twhile ((task = css_task_iter_next(&it))) {\n\t\tstruct mm_struct *mm;\n\t\tbool migrate;\n\n\t\tcpuset_change_task_nodemask(task, &newmems);\n\n\t\tmm = get_task_mm(task);\n\t\tif (!mm)\n\t\t\tcontinue;\n\n\t\tmigrate = is_memory_migrate(cs);\n\n\t\tmpol_rebind_mm(mm, &cs->mems_allowed);\n\t\tif (migrate)\n\t\t\tcpuset_migrate_mm(mm, &cs->old_mems_allowed, &newmems);\n\t\telse\n\t\t\tmmput(mm);\n\t}\n\tcss_task_iter_end(&it);\n\n\t/*\n\t * All the tasks' nodemasks have been updated, update\n\t * cs->old_mems_allowed.\n\t */\n\tcs->old_mems_allowed = newmems;\n\n\t/* We're done rebinding vmas to this cpuset's new mems_allowed. */\n\tcpuset_being_rebound = NULL;\n}",
        "static int __create_synth_event(const char *name, const char *raw_fields)\n{\n\tchar **argv, *field_str, *tmp_fields, *saved_fields = NULL;\n\tstruct synth_field *field, *fields[SYNTH_FIELDS_MAX];\n\tint consumed, cmd_version = 1, n_fields_this_loop;": "static int __create_synth_event(const char *name, const char *raw_fields)\n{\n\tchar **argv, *field_str, *tmp_fields, *saved_fields = NULL;\n\tstruct synth_field *field, *fields[SYNTH_FIELDS_MAX];\n\tint consumed, cmd_version = 1, n_fields_this_loop;\n\tint i, argc, n_fields = 0, ret = 0;\n\tstruct synth_event *event = NULL;\n\n\t/*\n\t * Argument syntax:\n\t *  - Add synthetic event: <event_name> field[;field] ...\n\t *  - Remove synthetic event: !<event_name> field[;field] ...\n\t *      where 'field' = type field_name\n\t */\n\n\tif (name[0] == '\\0') {\n\t\tsynth_err(SYNTH_ERR_INVALID_CMD, 0);\n\t\treturn -EINVAL;\n\t}\n\n\tif (!is_good_name(name)) {\n\t\tsynth_err(SYNTH_ERR_BAD_NAME, errpos(name));\n\t\treturn -EINVAL;\n\t}\n\n\tmutex_lock(&event_mutex);\n\n\tevent = find_synth_event(name);\n\tif (event) {\n\t\tsynth_err(SYNTH_ERR_EVENT_EXISTS, errpos(name));\n\t\tret = -EEXIST;\n\t\tgoto err;\n\t}\n\n\ttmp_fields = saved_fields = kstrdup(raw_fields, GFP_KERNEL);\n\tif (!tmp_fields) {\n\t\tret = -ENOMEM;\n\t\tgoto err;\n\t}\n\n\twhile ((field_str = strsep(&tmp_fields, \";\")) != NULL) {\n\t\targv = argv_split(GFP_KERNEL, field_str, &argc);\n\t\tif (!argv) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto err;\n\t\t}\n\n\t\tif (!argc) {\n\t\t\targv_free(argv);\n\t\t\tcontinue;\n\t\t}\n\n\t\tn_fields_this_loop = 0;\n\t\tconsumed = 0;\n\t\twhile (argc > consumed) {\n\t\t\tint field_version;\n\n\t\t\tfield = parse_synth_field(argc - consumed,\n\t\t\t\t\t\t  argv + consumed, &consumed,\n\t\t\t\t\t\t  &field_version);\n\t\t\tif (IS_ERR(field)) {\n\t\t\t\tret = PTR_ERR(field);\n\t\t\t\tgoto err_free_arg;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Track the highest version of any field we\n\t\t\t * found in the command.\n\t\t\t */\n\t\t\tif (field_version > cmd_version)\n\t\t\t\tcmd_version = field_version;\n\n\t\t\t/*\n\t\t\t * Now sort out what is and isn't valid for\n\t\t\t * each supported version.\n\t\t\t *\n\t\t\t * If we see more than 1 field per loop, it\n\t\t\t * means we have multiple fields between\n\t\t\t * semicolons, and that's something we no\n\t\t\t * longer support in a version 2 or greater\n\t\t\t * command.\n\t\t\t */\n\t\t\tif (cmd_version > 1 && n_fields_this_loop >= 1) {\n\t\t\t\tsynth_err(SYNTH_ERR_INVALID_CMD, errpos(field_str));\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto err_free_arg;\n\t\t\t}\n\n\t\t\tfields[n_fields++] = field;\n\t\t\tif (n_fields == SYNTH_FIELDS_MAX) {\n\t\t\t\tsynth_err(SYNTH_ERR_TOO_MANY_FIELDS, 0);\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto err_free_arg;\n\t\t\t}\n\n\t\t\tn_fields_this_loop++;\n\t\t}\n\t\targv_free(argv);\n\n\t\tif (consumed < argc) {\n\t\t\tsynth_err(SYNTH_ERR_INVALID_CMD, 0);\n\t\t\tret = -EINVAL;\n\t\t\tgoto err;\n\t\t}\n\n\t}\n\n\tif (n_fields == 0) {\n\t\tsynth_err(SYNTH_ERR_INVALID_CMD, 0);\n\t\tret = -EINVAL;\n\t\tgoto err;\n\t}\n\n\tevent = alloc_synth_event(name, n_fields, fields);\n\tif (IS_ERR(event)) {\n\t\tret = PTR_ERR(event);\n\t\tevent = NULL;\n\t\tgoto err;\n\t}\n\tret = register_synth_event(event);\n\tif (!ret)\n\t\tdyn_event_add(&event->devent, &event->call);\n\telse\n\t\tfree_synth_event(event);\n out:\n\tmutex_unlock(&event_mutex);\n\n\tkfree(saved_fields);\n\n\treturn ret;\n err_free_arg:\n\targv_free(argv);\n err:\n\tfor (i = 0; i < n_fields; i++)\n\t\tfree_synth_field(fields[i]);\n\n\tgoto out;\n}",
        "static int pfkey_spdadd(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tint err = 0;\n\tstruct sadb_lifetime *lifetime;": "static int pfkey_spdadd(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr, void * const *ext_hdrs)\n{\n\tstruct net *net = sock_net(sk);\n\tint err = 0;\n\tstruct sadb_lifetime *lifetime;\n\tstruct sadb_address *sa;\n\tstruct sadb_x_policy *pol;\n\tstruct xfrm_policy *xp;\n\tstruct km_event c;\n\tstruct sadb_x_sec_ctx *sec_ctx;\n\n\tif (!present_and_same_family(ext_hdrs[SADB_EXT_ADDRESS_SRC-1],\n\t\t\t\t     ext_hdrs[SADB_EXT_ADDRESS_DST-1]) ||\n\t    !ext_hdrs[SADB_X_EXT_POLICY-1])\n\t\treturn -EINVAL;\n\n\tpol = ext_hdrs[SADB_X_EXT_POLICY-1];\n\tif (pol->sadb_x_policy_type > IPSEC_POLICY_IPSEC)\n\t\treturn -EINVAL;\n\tif (!pol->sadb_x_policy_dir || pol->sadb_x_policy_dir >= IPSEC_DIR_MAX)\n\t\treturn -EINVAL;\n\n\txp = xfrm_policy_alloc(net, GFP_KERNEL);\n\tif (xp == NULL)\n\t\treturn -ENOBUFS;\n\n\txp->action = (pol->sadb_x_policy_type == IPSEC_POLICY_DISCARD ?\n\t\t      XFRM_POLICY_BLOCK : XFRM_POLICY_ALLOW);\n\txp->priority = pol->sadb_x_policy_priority;\n\n\tsa = ext_hdrs[SADB_EXT_ADDRESS_SRC-1];\n\txp->family = pfkey_sadb_addr2xfrm_addr(sa, &xp->selector.saddr);\n\txp->selector.family = xp->family;\n\txp->selector.prefixlen_s = sa->sadb_address_prefixlen;\n\txp->selector.proto = pfkey_proto_to_xfrm(sa->sadb_address_proto);\n\txp->selector.sport = ((struct sockaddr_in *)(sa+1))->sin_port;\n\tif (xp->selector.sport)\n\t\txp->selector.sport_mask = htons(0xffff);\n\n\tsa = ext_hdrs[SADB_EXT_ADDRESS_DST-1];\n\tpfkey_sadb_addr2xfrm_addr(sa, &xp->selector.daddr);\n\txp->selector.prefixlen_d = sa->sadb_address_prefixlen;\n\n\t/* Amusing, we set this twice.  KAME apps appear to set same value\n\t * in both addresses.\n\t */\n\txp->selector.proto = pfkey_proto_to_xfrm(sa->sadb_address_proto);\n\n\txp->selector.dport = ((struct sockaddr_in *)(sa+1))->sin_port;\n\tif (xp->selector.dport)\n\t\txp->selector.dport_mask = htons(0xffff);\n\n\tsec_ctx = ext_hdrs[SADB_X_EXT_SEC_CTX - 1];\n\tif (sec_ctx != NULL) {\n\t\tstruct xfrm_user_sec_ctx *uctx = pfkey_sadb2xfrm_user_sec_ctx(sec_ctx, GFP_KERNEL);\n\n\t\tif (!uctx) {\n\t\t\terr = -ENOBUFS;\n\t\t\tgoto out;\n\t\t}\n\n\t\terr = security_xfrm_policy_alloc(&xp->security, uctx, GFP_KERNEL);\n\t\tkfree(uctx);\n\n\t\tif (err)\n\t\t\tgoto out;\n\t}\n\n\txp->lft.soft_byte_limit = XFRM_INF;\n\txp->lft.hard_byte_limit = XFRM_INF;\n\txp->lft.soft_packet_limit = XFRM_INF;\n\txp->lft.hard_packet_limit = XFRM_INF;\n\tif ((lifetime = ext_hdrs[SADB_EXT_LIFETIME_HARD-1]) != NULL) {\n\t\txp->lft.hard_packet_limit = _KEY2X(lifetime->sadb_lifetime_allocations);\n\t\txp->lft.hard_byte_limit = _KEY2X(lifetime->sadb_lifetime_bytes);\n\t\txp->lft.hard_add_expires_seconds = lifetime->sadb_lifetime_addtime;\n\t\txp->lft.hard_use_expires_seconds = lifetime->sadb_lifetime_usetime;\n\t}\n\tif ((lifetime = ext_hdrs[SADB_EXT_LIFETIME_SOFT-1]) != NULL) {\n\t\txp->lft.soft_packet_limit = _KEY2X(lifetime->sadb_lifetime_allocations);\n\t\txp->lft.soft_byte_limit = _KEY2X(lifetime->sadb_lifetime_bytes);\n\t\txp->lft.soft_add_expires_seconds = lifetime->sadb_lifetime_addtime;\n\t\txp->lft.soft_use_expires_seconds = lifetime->sadb_lifetime_usetime;\n\t}\n\txp->xfrm_nr = 0;\n\tif (pol->sadb_x_policy_type == IPSEC_POLICY_IPSEC &&\n\t    (err = parse_ipsecrequests(xp, pol)) < 0)\n\t\tgoto out;\n\n\terr = xfrm_policy_insert(pol->sadb_x_policy_dir-1, xp,\n\t\t\t\t hdr->sadb_msg_type != SADB_X_SPDUPDATE);\n\n\txfrm_audit_policy_add(xp, err ? 0 : 1, true);\n\n\tif (err)\n\t\tgoto out;\n\n\tif (hdr->sadb_msg_type == SADB_X_SPDUPDATE)\n\t\tc.event = XFRM_MSG_UPDPOLICY;\n\telse\n\t\tc.event = XFRM_MSG_NEWPOLICY;\n\n\tc.seq = hdr->sadb_msg_seq;\n\tc.portid = hdr->sadb_msg_pid;\n\n\tkm_policy_notify(xp, pol->sadb_x_policy_dir-1, &c);\n\txfrm_pol_put(xp);\n\treturn 0;\n\nout:\n\txp->walk.dead = 1;\n\txfrm_policy_destroy(xp);\n\treturn err;\n}",
        "static void ipc_imem_handle_irq(struct iosm_imem *ipc_imem, int irq)\n{\n\tenum ipc_mem_device_ipc_state curr_ipc_status;\n\tenum ipc_phase old_phase, phase;\n\tbool retry_allocation = false;": "static void ipc_imem_handle_irq(struct iosm_imem *ipc_imem, int irq)\n{\n\tenum ipc_mem_device_ipc_state curr_ipc_status;\n\tenum ipc_phase old_phase, phase;\n\tbool retry_allocation = false;\n\tbool ul_pending = false;\n\tint i;\n\n\tif (irq != IMEM_IRQ_DONT_CARE)\n\t\tipc_imem->ev_irq_pending[irq] = false;\n\n\t/* Get the internal phase. */\n\told_phase = ipc_imem->phase;\n\n\tif (old_phase == IPC_P_OFF_REQ) {\n\t\tdev_dbg(ipc_imem->dev,\n\t\t\t\"[%s]: Ignoring MSI. Deinit sequence in progress!\",\n\t\t\tipc_imem_phase_get_string(old_phase));\n\t\treturn;\n\t}\n\n\t/* Update the phase controlled by CP. */\n\tphase = ipc_imem_phase_update(ipc_imem);\n\n\tswitch (phase) {\n\tcase IPC_P_RUN:\n\t\tif (!ipc_imem->enter_runtime) {\n\t\t\t/* Excute the transition from flash/boot to runtime. */\n\t\t\tipc_imem->enter_runtime = 1;\n\n\t\t\t/* allow device to sleep, default value is\n\t\t\t * IPC_HOST_SLEEP_ENTER_SLEEP\n\t\t\t */\n\t\t\tipc_imem_msg_send_device_sleep(ipc_imem,\n\t\t\t\t\t\t       ipc_imem->device_sleep);\n\n\t\t\tipc_imem_msg_send_feature_set(ipc_imem,\n\t\t\t\t\t\t      IPC_MEM_INBAND_CRASH_SIG,\n\t\t\t\t\t\t  true);\n\t\t}\n\n\t\tcurr_ipc_status =\n\t\t\tipc_protocol_get_ipc_status(ipc_imem->ipc_protocol);\n\n\t\t/* check ipc_status change */\n\t\tif (ipc_imem->ipc_status != curr_ipc_status) {\n\t\t\tipc_imem->ipc_status = curr_ipc_status;\n\n\t\t\tif (ipc_imem->ipc_status ==\n\t\t\t    IPC_MEM_DEVICE_IPC_RUNNING) {\n\t\t\t\tschedule_work(&ipc_imem->run_state_worker);\n\t\t\t}\n\t\t}\n\n\t\t/* Consider power management in the runtime phase. */\n\t\tipc_imem_slp_control_exec(ipc_imem);\n\t\tbreak; /* Continue with skbuf processing. */\n\n\t\t/* Unexpected phases. */\n\tcase IPC_P_OFF:\n\tcase IPC_P_OFF_REQ:\n\t\tdev_err(ipc_imem->dev, \"confused phase %s\",\n\t\t\tipc_imem_phase_get_string(phase));\n\t\treturn;\n\n\tcase IPC_P_PSI:\n\t\tif (old_phase != IPC_P_ROM)\n\t\t\tbreak;\n\n\t\tfallthrough;\n\t\t/* On CP the PSI phase is already active. */\n\n\tcase IPC_P_ROM:\n\t\t/* Before CP ROM driver starts the PSI image, it sets\n\t\t * the exit_code field on the doorbell scratchpad and\n\t\t * triggers the irq.\n\t\t */\n\t\tipc_imem_rom_irq_exec(ipc_imem);\n\t\treturn;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* process message ring */\n\tipc_protocol_msg_process(ipc_imem, irq);\n\n\t/* process all open pipes */\n\tfor (i = 0; i < IPC_MEM_MAX_CHANNELS; i++) {\n\t\tstruct ipc_pipe *ul_pipe = &ipc_imem->channels[i].ul_pipe;\n\t\tstruct ipc_pipe *dl_pipe = &ipc_imem->channels[i].dl_pipe;\n\n\t\tif (dl_pipe->is_open &&\n\t\t    (irq == IMEM_IRQ_DONT_CARE || irq == dl_pipe->irq)) {\n\t\t\tipc_imem_dl_pipe_process(ipc_imem, dl_pipe);\n\n\t\t\tif (dl_pipe->nr_of_queued_entries == 0)\n\t\t\t\tretry_allocation = true;\n\t\t}\n\n\t\tif (ul_pipe->is_open)\n\t\t\tipc_imem_ul_pipe_process(ipc_imem, ul_pipe);\n\t}\n\n\t/* Try to generate new ADB or ADGH. */\n\tif (ipc_mux_ul_data_encode(ipc_imem->mux)) {\n\t\tipc_imem_td_update_timer_start(ipc_imem);\n\t\tif (ipc_imem->mux->protocol == MUX_AGGREGATION)\n\t\t\tipc_imem_adb_timer_start(ipc_imem);\n\t}\n\n\t/* Continue the send procedure with accumulated SIO or NETIF packets.\n\t * Reset the debounce flags.\n\t */\n\tul_pending |= ipc_imem_ul_write_td(ipc_imem);\n\n\t/* if UL data is pending restart TD update timer */\n\tif (ul_pending) {\n\t\tipc_imem->hrtimer_period =\n\t\tktime_set(0, TD_UPDATE_DEFAULT_TIMEOUT_USEC * 1000ULL);\n\t\tif (!hrtimer_active(&ipc_imem->tdupdate_timer))\n\t\t\thrtimer_start(&ipc_imem->tdupdate_timer,\n\t\t\t\t      ipc_imem->hrtimer_period,\n\t\t\t\t      HRTIMER_MODE_REL);\n\t}\n\n\t/* If CP has executed the transition\n\t * from IPC_INIT to IPC_RUNNING in the PSI\n\t * phase, wake up the flash app to open the pipes.\n\t */\n\tif ((phase == IPC_P_PSI || phase == IPC_P_EBL) &&\n\t    ipc_imem->ipc_requested_state == IPC_MEM_DEVICE_IPC_RUNNING &&\n\t    ipc_mmio_get_ipc_state(ipc_imem->mmio) ==\n\t\t\t\t\t\tIPC_MEM_DEVICE_IPC_RUNNING) {\n\t\tcomplete(&ipc_imem->ipc_devlink->devlink_sio.channel->ul_sem);\n\t}\n\n\t/* Reset the expected CP state. */\n\tipc_imem->ipc_requested_state = IPC_MEM_DEVICE_IPC_DONT_CARE;\n\n\tif (retry_allocation) {\n\t\tipc_imem->hrtimer_period =\n\t\tktime_set(0, IPC_TD_ALLOC_TIMER_PERIOD_MS * 1000 * 1000ULL);\n\t\tif (!hrtimer_active(&ipc_imem->td_alloc_timer))\n\t\t\thrtimer_start(&ipc_imem->td_alloc_timer,\n\t\t\t\t      ipc_imem->hrtimer_period,\n\t\t\t\t      HRTIMER_MODE_REL);\n\t}\n}",
        "static int nand_ecc_sw_bch_init(struct nand_device *nand)\n{\n\tstruct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv;\n\tunsigned int eccsize = nand->ecc.ctx.conf.step_size;\n\tunsigned int eccbytes = engine_conf->code_size;": "static int nand_ecc_sw_bch_init(struct nand_device *nand)\n{\n\tstruct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv;\n\tunsigned int eccsize = nand->ecc.ctx.conf.step_size;\n\tunsigned int eccbytes = engine_conf->code_size;\n\tunsigned int m, t, i;\n\tunsigned char *erased_page;\n\tint ret;\n\n\tm = fls(1 + (8 * eccsize));\n\tt = (eccbytes * 8) / m;\n\n\tengine_conf->bch = bch_init(m, t, 0, false);\n\tif (!engine_conf->bch)\n\t\treturn -EINVAL;\n\n\tengine_conf->eccmask = kzalloc(eccbytes, GFP_KERNEL);\n\tengine_conf->errloc = kmalloc_array(t, sizeof(*engine_conf->errloc),\n\t\t\t\t\t    GFP_KERNEL);\n\tif (!engine_conf->eccmask || !engine_conf->errloc) {\n\t\tret = -ENOMEM;\n\t\tgoto cleanup;\n\t}\n\n\t/* Compute and store the inverted ECC of an erased step */\n\terased_page = kmalloc(eccsize, GFP_KERNEL);\n\tif (!erased_page) {\n\t\tret = -ENOMEM;\n\t\tgoto cleanup;\n\t}\n\n\tmemset(erased_page, 0xff, eccsize);\n\tbch_encode(engine_conf->bch, erased_page, eccsize,\n\t\t   engine_conf->eccmask);\n\tkfree(erased_page);\n\n\tfor (i = 0; i < eccbytes; i++)\n\t\tengine_conf->eccmask[i] ^= 0xff;\n\n\t/* Verify that the number of code bytes has the expected value */\n\tif (engine_conf->bch->ecc_bytes != eccbytes) {\n\t\tpr_err(\"Invalid number of ECC bytes: %u, expected: %u\\n\",\n\t\t       eccbytes, engine_conf->bch->ecc_bytes);\n\t\tret = -EINVAL;\n\t\tgoto cleanup;\n\t}\n\n\t/* Sanity checks */\n\tif (8 * (eccsize + eccbytes) >= (1 << m)) {\n\t\tpr_err(\"ECC step size is too large (%u)\\n\", eccsize);\n\t\tret = -EINVAL;\n\t\tgoto cleanup;\n\t}\n\n\treturn 0;\n\ncleanup:\n\tnand_ecc_sw_bch_cleanup(nand);\n\n\treturn ret;\n}",
        "static void torture_rtmutex_boost(struct torture_random_state *trsp)\n{\n\tconst unsigned int factor = 50000; /* yes, quite arbitrary */\n\n\tif (!rt_task(current)) {": "static void torture_rtmutex_boost(struct torture_random_state *trsp)\n{\n\tconst unsigned int factor = 50000; /* yes, quite arbitrary */\n\n\tif (!rt_task(current)) {\n\t\t/*\n\t\t * Boost priority once every ~50k operations. When the\n\t\t * task tries to take the lock, the rtmutex it will account\n\t\t * for the new priority, and do any corresponding pi-dance.\n\t\t */\n\t\tif (trsp && !(torture_random(trsp) %\n\t\t\t      (cxt.nrealwriters_stress * factor))) {\n\t\t\tsched_set_fifo(current);\n\t\t} else /* common case, do nothing */\n\t\t\treturn;\n\t} else {\n\t\t/*\n\t\t * The task will remain boosted for another ~500k operations,\n\t\t * then restored back to its original prio, and so forth.\n\t\t *\n\t\t * When @trsp is nil, we want to force-reset the task for\n\t\t * stopping the kthread.\n\t\t */\n\t\tif (!trsp || !(torture_random(trsp) %\n\t\t\t       (cxt.nrealwriters_stress * factor * 2))) {\n\t\t\tsched_set_normal(current, 0);\n\t\t} else /* common case, do nothing */\n\t\t\treturn;\n\t}\n}",
        "static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)\n{\n\tunsigned long timeout;\n\n\tif (i2c->variant->hw == I2C_TYPE_EXYNOS5)": "static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)\n{\n\tunsigned long timeout;\n\n\tif (i2c->variant->hw == I2C_TYPE_EXYNOS5)\n\t\treturn;\n\n\t/*\n\t * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants)\n\t * before transaction indicates that bus is stuck (SDA is low).\n\t * In such case bus recovery can be performed.\n\t */\n\ttimeout = jiffies + msecs_to_jiffies(100);\n\tfor (;;) {\n\t\tu32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);\n\n\t\tif ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)\n\t\t\treturn;\n\n\t\tif (time_is_before_jiffies(timeout))\n\t\t\treturn;\n\n\t\texynos5_i2c_bus_recover(i2c);\n\t}\n}",
        "static void ov519_set_fr(struct sd *sd)\n{\n\tint fr;\n\tu8 clock;\n\t/* frame rate table with indices:": "static void ov519_set_fr(struct sd *sd)\n{\n\tint fr;\n\tu8 clock;\n\t/* frame rate table with indices:\n\t *\t- mode = 0: 320x240, 1: 640x480\n\t *\t- fr rate = 0: 30, 1: 25, 2: 20, 3: 15, 4: 10, 5: 5\n\t *\t- reg = 0: bridge a4, 1: bridge 23, 2: sensor 11 (clock)\n\t */\n\tstatic const u8 fr_tb[2][6][3] = {\n\t\t{{0x04, 0xff, 0x00},\n\t\t {0x04, 0x1f, 0x00},\n\t\t {0x04, 0x1b, 0x00},\n\t\t {0x04, 0x15, 0x00},\n\t\t {0x04, 0x09, 0x00},\n\t\t {0x04, 0x01, 0x00}},\n\t\t{{0x0c, 0xff, 0x00},\n\t\t {0x0c, 0x1f, 0x00},\n\t\t {0x0c, 0x1b, 0x00},\n\t\t {0x04, 0xff, 0x01},\n\t\t {0x04, 0x1f, 0x01},\n\t\t {0x04, 0x1b, 0x01}},\n\t};\n\n\tif (frame_rate > 0)\n\t\tsd->frame_rate = frame_rate;\n\tif (sd->frame_rate >= 30)\n\t\tfr = 0;\n\telse if (sd->frame_rate >= 25)\n\t\tfr = 1;\n\telse if (sd->frame_rate >= 20)\n\t\tfr = 2;\n\telse if (sd->frame_rate >= 15)\n\t\tfr = 3;\n\telse if (sd->frame_rate >= 10)\n\t\tfr = 4;\n\telse\n\t\tfr = 5;\n\treg_w(sd, 0xa4, fr_tb[sd->gspca_dev.curr_mode][fr][0]);\n\treg_w(sd, 0x23, fr_tb[sd->gspca_dev.curr_mode][fr][1]);\n\tclock = fr_tb[sd->gspca_dev.curr_mode][fr][2];\n\tif (sd->sensor == SEN_OV7660)\n\t\tclock |= 0x80;\t\t/* enable double clock */\n\tov518_i2c_w(sd, OV7670_R11_CLKRC, clock);\n}",
        "static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)\n{\n\tint ret, adc_ts_pin_ctrl;\n\tu8 buf[2];\n": "static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)\n{\n\tint ret, adc_ts_pin_ctrl;\n\tu8 buf[2];\n\n\t/*\n\t * The current-source used for the battery temp-sensor (TS) is shared\n\t * with the GPADC. For proper fuel-gauge and charger operation the TS\n\t * current-source needs to be permanently on. But to read the GPADC we\n\t * need to temporary switch the TS current-source to ondemand, so that\n\t * the GPADC can use it, otherwise we will always read an all 0 value.\n\t *\n\t * Note that the switching from on to on-ondemand is not necessary\n\t * when the TS current-source is off (this happens on devices which\n\t * do not use the TS-pin).\n\t */\n\tret = regmap_read(regmap, AXP288_ADC_TS_PIN_CTRL, &adc_ts_pin_ctrl);\n\tif (ret)\n\t\treturn ret;\n\n\tif (adc_ts_pin_ctrl & AXP288_ADC_TS_CURRENT_ON_OFF_MASK) {\n\t\t/*\n\t\t * AXP288_ADC_TS_PIN_CTRL reads are cached by the regmap, so\n\t\t * this does to a single I2C-transfer, and thus there is no\n\t\t * need to explicitly call iosf_mbi_block_punit_i2c_access().\n\t\t */\n\t\tret = regmap_update_bits(regmap, AXP288_ADC_TS_PIN_CTRL,\n\t\t\t\t\t AXP288_ADC_TS_CURRENT_ON_OFF_MASK,\n\t\t\t\t\t AXP288_ADC_TS_CURRENT_ON_ONDEMAND);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/* Wait a bit after switching the current-source */\n\t\tusleep_range(6000, 10000);\n\t}\n\n\tret = iosf_mbi_block_punit_i2c_access();\n\tif (ret)\n\t\treturn ret;\n\n\tret = regmap_bulk_read(regmap, AXP288_GP_ADC_H, buf, 2);\n\tif (ret == 0)\n\t\tret = (buf[0] << 4) + ((buf[1] >> 4) & 0x0f);\n\n\tif (adc_ts_pin_ctrl & AXP288_ADC_TS_CURRENT_ON_OFF_MASK) {\n\t\tregmap_update_bits(regmap, AXP288_ADC_TS_PIN_CTRL,\n\t\t\t\t   AXP288_ADC_TS_CURRENT_ON_OFF_MASK,\n\t\t\t\t   AXP288_ADC_TS_CURRENT_ON);\n\t}\n\n\tiosf_mbi_unblock_punit_i2c_access();\n\n\treturn ret;\n}",
        "static int locate_mem_hole_callback(struct resource *res, void *arg)\n{\n\tstruct kexec_buf *kbuf = (struct kexec_buf *)arg;\n\tu64 start = res->start, end = res->end;\n\tunsigned long sz = end - start + 1;": "static int locate_mem_hole_callback(struct resource *res, void *arg)\n{\n\tstruct kexec_buf *kbuf = (struct kexec_buf *)arg;\n\tu64 start = res->start, end = res->end;\n\tunsigned long sz = end - start + 1;\n\n\t/* Returning 0 will take to next memory range */\n\n\t/* Don't use memory that will be detected and handled by a driver. */\n\tif (res->flags & IORESOURCE_SYSRAM_DRIVER_MANAGED)\n\t\treturn 0;\n\n\tif (sz < kbuf->memsz)\n\t\treturn 0;\n\n\tif (end < kbuf->buf_min || start > kbuf->buf_max)\n\t\treturn 0;\n\n\t/*\n\t * Allocate memory top down with-in ram range. Otherwise bottom up\n\t * allocation.\n\t */\n\tif (kbuf->top_down)\n\t\treturn locate_mem_hole_top_down(start, end, kbuf);\n\treturn locate_mem_hole_bottom_up(start, end, kbuf);\n}",
        "static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)\n{\n\tstruct idtcm *idtcm = channel->idtcm;\n\tint err;\n\tu8 i;": "static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)\n{\n\tstruct idtcm *idtcm = channel->idtcm;\n\tint err;\n\tu8 i;\n\tu8 buf[4] = {0};\n\ts32 phase_50ps;\n\ts64 offset_ps;\n\n\tif (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {\n\t\terr = channel->configure_write_phase(channel);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\toffset_ps = (s64)delta_ns * 1000;\n\n\t/*\n\t * Check for 32-bit signed max * 50:\n\t *\n\t * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350\n\t */\n\tif (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)\n\t\toffset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;\n\telse if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)\n\t\toffset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;\n\n\tphase_50ps = div_s64(offset_ps, 50);\n\n\tfor (i = 0; i < 4; i++) {\n\t\tbuf[i] = phase_50ps & 0xff;\n\t\tphase_50ps >>= 8;\n\t}\n\n\terr = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,\n\t\t\t  buf, sizeof(buf));\n\n\treturn err;\n}",
        "static void copy_hashes_authenticate_chunks(struct work_struct *work)\n{\n\tstruct ifs_work *local_work = container_of(work, struct ifs_work, w);\n\tunion ifs_scan_hashes_status hashes_status;\n\tunion ifs_chunks_auth_status chunk_status;": "static void copy_hashes_authenticate_chunks(struct work_struct *work)\n{\n\tstruct ifs_work *local_work = container_of(work, struct ifs_work, w);\n\tunion ifs_scan_hashes_status hashes_status;\n\tunion ifs_chunks_auth_status chunk_status;\n\tstruct device *dev = local_work->dev;\n\tint i, num_chunks, chunk_size;\n\tstruct ifs_data *ifsd;\n\tu64 linear_addr, base;\n\tu32 err_code;\n\n\tifsd = ifs_get_data(dev);\n\t/* run scan hash copy */\n\twrmsrl(MSR_COPY_SCAN_HASHES, ifs_hash_ptr);\n\trdmsrl(MSR_SCAN_HASHES_STATUS, hashes_status.data);\n\n\t/* enumerate the scan image information */\n\tnum_chunks = hashes_status.num_chunks;\n\tchunk_size = hashes_status.chunk_size * 1024;\n\terr_code = hashes_status.error_code;\n\n\tif (!hashes_status.valid) {\n\t\tifsd->loading_error = true;\n\t\tif (err_code >= ARRAY_SIZE(scan_hash_status)) {\n\t\t\tdev_err(dev, \"invalid error code 0x%x for hash copy\\n\", err_code);\n\t\t\tgoto done;\n\t\t}\n\t\tdev_err(dev, \"Hash copy error : %s\", scan_hash_status[err_code]);\n\t\tgoto done;\n\t}\n\n\t/* base linear address to the scan data */\n\tbase = ifs_test_image_ptr;\n\n\t/* scan data authentication and copy chunks to secured memory */\n\tfor (i = 0; i < num_chunks; i++) {\n\t\tlinear_addr = base + i * chunk_size;\n\t\tlinear_addr |= i;\n\n\t\twrmsrl(MSR_AUTHENTICATE_AND_COPY_CHUNK, linear_addr);\n\t\trdmsrl(MSR_CHUNKS_AUTHENTICATION_STATUS, chunk_status.data);\n\n\t\tifsd->valid_chunks = chunk_status.valid_chunks;\n\t\terr_code = chunk_status.error_code;\n\n\t\tif (err_code) {\n\t\t\tifsd->loading_error = true;\n\t\t\tif (err_code >= ARRAY_SIZE(scan_authentication_status)) {\n\t\t\t\tdev_err(dev,\n\t\t\t\t\t\"invalid error code 0x%x for authentication\\n\", err_code);\n\t\t\t\tgoto done;\n\t\t\t}\n\t\t\tdev_err(dev, \"Chunk authentication error %s\\n\",\n\t\t\t\tscan_authentication_status[err_code]);\n\t\t\tgoto done;\n\t\t}\n\t}\ndone:\n\tcomplete(&ifs_done);\n}",
        "static int ina2xx_conversion_ready(struct iio_dev *indio_dev)\n{\n\tstruct ina2xx_chip_info *chip = iio_priv(indio_dev);\n\tint ret;\n\tunsigned int alert;": "static int ina2xx_conversion_ready(struct iio_dev *indio_dev)\n{\n\tstruct ina2xx_chip_info *chip = iio_priv(indio_dev);\n\tint ret;\n\tunsigned int alert;\n\n\t/*\n\t * Because the timer thread and the chip conversion clock\n\t * are asynchronous, the period difference will eventually\n\t * result in reading V[k-1] again, or skip V[k] at time Tk.\n\t * In order to resync the timer with the conversion process\n\t * we check the ConVersionReadyFlag.\n\t * On hardware that supports using the ALERT pin to toggle a\n\t * GPIO a triggered buffer could be used instead.\n\t * For now, we do an extra read of the MASK_ENABLE register (INA226)\n\t * resp. the BUS_VOLTAGE register (INA219).\n\t */\n\tif (chip->config->chip_id == ina226) {\n\t\tret = regmap_read(chip->regmap,\n\t\t\t\t  INA226_MASK_ENABLE, &alert);\n\t\talert &= INA226_CVRF;\n\t} else {\n\t\tret = regmap_read(chip->regmap,\n\t\t\t\t  INA2XX_BUS_VOLTAGE, &alert);\n\t\talert &= INA219_CNVR;\n\t}\n\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn !!alert;\n}",
        "static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)\n{\n\tint i, j;\n\tstruct hdsp_9632_meters __iomem *m;\n\tint doublespeed = 0;": "static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)\n{\n\tint i, j;\n\tstruct hdsp_9632_meters __iomem *m;\n\tint doublespeed = 0;\n\n\tif (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)\n\t\tdoublespeed = 1;\n\tm = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);\n\tfor (i = 0, j = 0; i < 16; ++i, ++j) {\n\t\tif (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))\n\t\t\treturn -EFAULT;\n\t\tif (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))\n\t\t\treturn -EFAULT;\n\t\tif (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))\n\t\t\treturn -EFAULT;\n\t\tif (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],\n\t\t\t\t&m->input_rms_high[j]))\n\t\t\treturn -EFAULT;\n\t\tif (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],\n\t\t\t\t&m->playback_rms_high[j]))\n\t\t\treturn -EFAULT;\n\t\tif (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],\n\t\t\t\t&m->output_rms_high[j]))\n\t\t\treturn -EFAULT;\n\t\tif (doublespeed && i == 3) i += 4;\n\t}\n\treturn 0;\n}",
        "static int mt6360_strobe_set(struct led_classdev_flash *fl_cdev, bool state)\n{\n\tstruct mt6360_led *led =\n\t\tcontainer_of(fl_cdev, struct mt6360_led, flash);\n\tstruct mt6360_priv *priv = led->priv;": "static int mt6360_strobe_set(struct led_classdev_flash *fl_cdev, bool state)\n{\n\tstruct mt6360_led *led =\n\t\tcontainer_of(fl_cdev, struct mt6360_led, flash);\n\tstruct mt6360_priv *priv = led->priv;\n\tstruct led_classdev *lcdev = &fl_cdev->led_cdev;\n\tstruct led_flash_setting *s = &fl_cdev->brightness;\n\tu32 enable_mask = MT6360_STROBEN_MASK | MT6360_FLCSEN_MASK(led->led_no);\n\tu32 val = state ? MT6360_FLCSEN_MASK(led->led_no) : 0;\n\tu32 prev = priv->fled_strobe_used, curr;\n\tint ret;\n\n\tmutex_lock(&priv->lock);\n\n\t/*\n\t * Only one set of flash control logic, use the flag to avoid torch is\n\t * currently used\n\t */\n\tif (priv->fled_torch_used) {\n\t\tdev_warn(lcdev->dev, \"Please disable torch first [0x%x]\\n\",\n\t\t\t priv->fled_torch_used);\n\t\tret = -EBUSY;\n\t\tgoto unlock;\n\t}\n\n\tif (state)\n\t\tcurr = prev | BIT(led->led_no);\n\telse\n\t\tcurr = prev & ~BIT(led->led_no);\n\n\tif (curr)\n\t\tval |= MT6360_STROBEN_MASK;\n\n\tret = regmap_update_bits(priv->regmap, MT6360_REG_FLEDEN, enable_mask,\n\t\t\t\t val);\n\tif (ret) {\n\t\tdev_err(lcdev->dev, \"[%d] control current source %d fail\\n\",\n\t\t\tled->led_no, state);\n\t\tgoto unlock;\n\t}\n\n\t/*\n\t * If the flash need to be on, config the flash current ramping up to\n\t * the setting value.\n\t * Else, always recover back to the minimum one\n\t */\n\tret = _mt6360_flash_brightness_set(fl_cdev, state ? s->val : s->min);\n\tif (ret)\n\t\tgoto unlock;\n\n\t/*\n\t * For the flash turn on/off, HW rampping up/down time is 5ms/500us,\n\t * respectively.\n\t */\n\tif (!prev && curr)\n\t\tusleep_range(5000, 6000);\n\telse if (prev && !curr)\n\t\tudelay(500);\n\n\tpriv->fled_strobe_used = curr;\n\nunlock:\n\tmutex_unlock(&priv->lock);\n\treturn ret;\n}",
        "static void i40e_determine_queue_usage(struct i40e_pf *pf)\n{\n\tint queues_left;\n\tint q_max;\n": "static void i40e_determine_queue_usage(struct i40e_pf *pf)\n{\n\tint queues_left;\n\tint q_max;\n\n\tpf->num_lan_qps = 0;\n\n\t/* Find the max queues to be put into basic use.  We'll always be\n\t * using TC0, whether or not DCB is running, and TC0 will get the\n\t * big RSS set.\n\t */\n\tqueues_left = pf->hw.func_caps.num_tx_qp;\n\n\tif ((queues_left == 1) ||\n\t    !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {\n\t\t/* one qp for PF, no queues for anything else */\n\t\tqueues_left = 0;\n\t\tpf->alloc_rss_size = pf->num_lan_qps = 1;\n\n\t\t/* make sure all the fancies are disabled */\n\t\tpf->flags &= ~(I40E_FLAG_RSS_ENABLED\t|\n\t\t\t       I40E_FLAG_IWARP_ENABLED\t|\n\t\t\t       I40E_FLAG_FD_SB_ENABLED\t|\n\t\t\t       I40E_FLAG_FD_ATR_ENABLED\t|\n\t\t\t       I40E_FLAG_DCB_CAPABLE\t|\n\t\t\t       I40E_FLAG_DCB_ENABLED\t|\n\t\t\t       I40E_FLAG_SRIOV_ENABLED\t|\n\t\t\t       I40E_FLAG_VMDQ_ENABLED);\n\t\tpf->flags |= I40E_FLAG_FD_SB_INACTIVE;\n\t} else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |\n\t\t\t\t  I40E_FLAG_FD_SB_ENABLED |\n\t\t\t\t  I40E_FLAG_FD_ATR_ENABLED |\n\t\t\t\t  I40E_FLAG_DCB_CAPABLE))) {\n\t\t/* one qp for PF */\n\t\tpf->alloc_rss_size = pf->num_lan_qps = 1;\n\t\tqueues_left -= pf->num_lan_qps;\n\n\t\tpf->flags &= ~(I40E_FLAG_RSS_ENABLED\t|\n\t\t\t       I40E_FLAG_IWARP_ENABLED\t|\n\t\t\t       I40E_FLAG_FD_SB_ENABLED\t|\n\t\t\t       I40E_FLAG_FD_ATR_ENABLED\t|\n\t\t\t       I40E_FLAG_DCB_ENABLED\t|\n\t\t\t       I40E_FLAG_VMDQ_ENABLED);\n\t\tpf->flags |= I40E_FLAG_FD_SB_INACTIVE;\n\t} else {\n\t\t/* Not enough queues for all TCs */\n\t\tif ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&\n\t\t    (queues_left < I40E_MAX_TRAFFIC_CLASS)) {\n\t\t\tpf->flags &= ~(I40E_FLAG_DCB_CAPABLE |\n\t\t\t\t\tI40E_FLAG_DCB_ENABLED);\n\t\t\tdev_info(&pf->pdev->dev, \"not enough queues for DCB. DCB is disabled.\\n\");\n\t\t}\n\n\t\t/* limit lan qps to the smaller of qps, cpus or msix */\n\t\tq_max = max_t(int, pf->rss_size_max, num_online_cpus());\n\t\tq_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp);\n\t\tq_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors);\n\t\tpf->num_lan_qps = q_max;\n\n\t\tqueues_left -= pf->num_lan_qps;\n\t}\n\n\tif (pf->flags & I40E_FLAG_FD_SB_ENABLED) {\n\t\tif (queues_left > 1) {\n\t\t\tqueues_left -= 1; /* save 1 queue for FD */\n\t\t} else {\n\t\t\tpf->flags &= ~I40E_FLAG_FD_SB_ENABLED;\n\t\t\tpf->flags |= I40E_FLAG_FD_SB_INACTIVE;\n\t\t\tdev_info(&pf->pdev->dev, \"not enough queues for Flow Director. Flow Director feature is disabled\\n\");\n\t\t}\n\t}\n\n\tif ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&\n\t    pf->num_vf_qps && pf->num_req_vfs && queues_left) {\n\t\tpf->num_req_vfs = min_t(int, pf->num_req_vfs,\n\t\t\t\t\t(queues_left / pf->num_vf_qps));\n\t\tqueues_left -= (pf->num_req_vfs * pf->num_vf_qps);\n\t}\n\n\tif ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&\n\t    pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {\n\t\tpf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,\n\t\t\t\t\t  (queues_left / pf->num_vmdq_qps));\n\t\tqueues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);\n\t}\n\n\tpf->queues_left = queues_left;\n\tdev_dbg(&pf->pdev->dev,\n\t\t\"qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\\n\",\n\t\tpf->hw.func_caps.num_tx_qp,\n\t\t!!(pf->flags & I40E_FLAG_FD_SB_ENABLED),\n\t\tpf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,\n\t\tpf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,\n\t\tqueues_left);\n}",
        "static int dbJoin(dmtree_t * tp, int leafno, int newval)\n{\n\tint budsz, buddy;\n\ts8 *leaf;\n": "static int dbJoin(dmtree_t * tp, int leafno, int newval)\n{\n\tint budsz, buddy;\n\ts8 *leaf;\n\n\t/* can the new leaf value require a join with other leaves ?\n\t */\n\tif (newval >= tp->dmt_budmin) {\n\t\t/* pickup a pointer to the leaves of the tree.\n\t\t */\n\t\tleaf = tp->dmt_stree + le32_to_cpu(tp->dmt_leafidx);\n\n\t\t/* try to join the specified leaf into a large binary\n\t\t * buddy system.  the join proceeds by attempting to join\n\t\t * the specified leafno with its buddy (leaf) at new value.\n\t\t * if the join occurs, we attempt to join the left leaf\n\t\t * of the joined buddies with its buddy at new value + 1.\n\t\t * we continue to join until we find a buddy that cannot be\n\t\t * joined (does not have a value equal to the size of the\n\t\t * last join) or until all leaves have been joined into a\n\t\t * single system.\n\t\t *\n\t\t * get the buddy size (number of words covered) of\n\t\t * the new value.\n\t\t */\n\t\tbudsz = BUDSIZE(newval, tp->dmt_budmin);\n\n\t\t/* try to join.\n\t\t */\n\t\twhile (budsz < le32_to_cpu(tp->dmt_nleafs)) {\n\t\t\t/* get the buddy leaf.\n\t\t\t */\n\t\t\tbuddy = leafno ^ budsz;\n\n\t\t\t/* if the leaf's new value is greater than its\n\t\t\t * buddy's value, we join no more.\n\t\t\t */\n\t\t\tif (newval > leaf[buddy])\n\t\t\t\tbreak;\n\n\t\t\t/* It shouldn't be less */\n\t\t\tif (newval < leaf[buddy])\n\t\t\t\treturn -EIO;\n\n\t\t\t/* check which (leafno or buddy) is the left buddy.\n\t\t\t * the left buddy gets to claim the blocks resulting\n\t\t\t * from the join while the right gets to claim none.\n\t\t\t * the left buddy is also eligible to participate in\n\t\t\t * a join at the next higher level while the right\n\t\t\t * is not.\n\t\t\t *\n\t\t\t */\n\t\t\tif (leafno < buddy) {\n\t\t\t\t/* leafno is the left buddy.\n\t\t\t\t */\n\t\t\t\tdbAdjTree(tp, buddy, NOFREE);\n\t\t\t} else {\n\t\t\t\t/* buddy is the left buddy and becomes\n\t\t\t\t * leafno.\n\t\t\t\t */\n\t\t\t\tdbAdjTree(tp, leafno, NOFREE);\n\t\t\t\tleafno = buddy;\n\t\t\t}\n\n\t\t\t/* on to try the next join.\n\t\t\t */\n\t\t\tnewval += 1;\n\t\t\tbudsz <<= 1;\n\t\t}\n\t}\n\n\t/* update the leaf value.\n\t */\n\tdbAdjTree(tp, leafno, newval);\n\n\treturn 0;\n}",
        "static void fun_handle_cqe_pkt(struct funeth_rxq *q, struct funeth_txq *xdp_q)\n{\n\tconst struct fun_eth_cqe *rxreq = info_to_cqe(q->next_cqe_info);\n\tunsigned int i, tot_len, pkt_len = be32_to_cpu(rxreq->pkt_len);\n\tstruct net_device *ndev = q->netdev;": "static void fun_handle_cqe_pkt(struct funeth_rxq *q, struct funeth_txq *xdp_q)\n{\n\tconst struct fun_eth_cqe *rxreq = info_to_cqe(q->next_cqe_info);\n\tunsigned int i, tot_len, pkt_len = be32_to_cpu(rxreq->pkt_len);\n\tstruct net_device *ndev = q->netdev;\n\tskb_frag_t frags[RX_MAX_FRAGS];\n\tstruct skb_shared_info *si;\n\tunsigned int headroom;\n\tgro_result_t gro_res;\n\tstruct sk_buff *skb;\n\tint ref_ok;\n\tvoid *va;\n\tu16 cv;\n\n\tu64_stats_update_begin(&q->syncp);\n\tq->stats.rx_pkts++;\n\tq->stats.rx_bytes += pkt_len;\n\tu64_stats_update_end(&q->syncp);\n\n\tadvance_cq(q);\n\n\t/* account for head- and tail-room, present only for 1-buffer packets */\n\ttot_len = pkt_len;\n\theadroom = be16_to_cpu(rxreq->headroom);\n\tif (likely(headroom))\n\t\ttot_len += FUN_RX_TAILROOM + headroom;\n\n\tref_ok = fun_gather_pkt(q, tot_len, frags);\n\tva = skb_frag_address(frags);\n\tif (xdp_q && headroom == FUN_XDP_HEADROOM) {\n\t\tva = fun_run_xdp(q, frags, va, ref_ok, xdp_q);\n\t\tif (!va)\n\t\t\treturn;\n\t\theadroom = 0;   /* XDP_PASS trims it */\n\t}\n\tif (unlikely(!ref_ok))\n\t\tgoto no_mem;\n\n\tif (likely(headroom)) {\n\t\t/* headroom is either FUN_RX_HEADROOM or FUN_XDP_HEADROOM */\n\t\tprefetch(va + headroom);\n\t\tskb = napi_build_skb(va, ALIGN(tot_len, FUN_EPRQ_PKT_ALIGN));\n\t\tif (unlikely(!skb))\n\t\t\tgoto no_mem;\n\n\t\tskb_reserve(skb, headroom);\n\t\t__skb_put(skb, pkt_len);\n\t\tskb->protocol = eth_type_trans(skb, ndev);\n\t} else {\n\t\tprefetch(va);\n\t\tskb = napi_get_frags(q->napi);\n\t\tif (unlikely(!skb))\n\t\t\tgoto no_mem;\n\n\t\tif (ref_ok < 0)\n\t\t\tskb->pfmemalloc = 1;\n\n\t\tsi = skb_shinfo(skb);\n\t\tsi->nr_frags = rxreq->nsgl;\n\t\tfor (i = 0; i < si->nr_frags; i++)\n\t\t\tsi->frags[i] = frags[i];\n\n\t\tskb->len = pkt_len;\n\t\tskb->data_len = pkt_len;\n\t\tskb->truesize += round_up(pkt_len, FUN_EPRQ_PKT_ALIGN);\n\t}\n\n\tskb_record_rx_queue(skb, q->qidx);\n\tcv = be16_to_cpu(rxreq->pkt_cv);\n\tif (likely((q->netdev->features & NETIF_F_RXHASH) && rxreq->hash))\n\t\tskb_set_hash(skb, be32_to_cpu(rxreq->hash),\n\t\t\t     cqe_to_pkt_hash_type(cv));\n\tif (likely((q->netdev->features & NETIF_F_RXCSUM) && rxreq->csum)) {\n\t\tFUN_QSTAT_INC(q, rx_cso);\n\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t\tskb->csum_level = be16_to_cpu(rxreq->csum) - 1;\n\t}\n\tif (unlikely(rx_hwtstamp_enabled(q->netdev)))\n\t\tskb_hwtstamps(skb)->hwtstamp = be64_to_cpu(rxreq->timestamp);\n\n\ttrace_funeth_rx(q, rxreq->nsgl, pkt_len, skb->hash, cv);\n\n\tgro_res = skb->data_len ? napi_gro_frags(q->napi) :\n\t\t\t\t  napi_gro_receive(q->napi, skb);\n\tif (gro_res == GRO_MERGED || gro_res == GRO_MERGED_FREE)\n\t\tFUN_QSTAT_INC(q, gro_merged);\n\telse if (gro_res == GRO_HELD)\n\t\tFUN_QSTAT_INC(q, gro_pkts);\n\treturn;\n\nno_mem:\n\tFUN_QSTAT_INC(q, rx_mem_drops);\n\n\t/* Release the references we've been granted for the frag pages.\n\t * We return the ref of the last frag and free the rest.\n\t */\n\tq->cur_buf->pg_refs++;\n\tfor (i = 0; i < rxreq->nsgl - 1; i++)\n\t\t__free_page(skb_frag_page(frags + i));\n}",
        "static int armada38x_rtc_set_offset(struct device *dev, long offset)\n{\n\tstruct armada38x_rtc *rtc = dev_get_drvdata(dev);\n\tunsigned long ccr = 0;\n\tlong ppb_cor, off;": "static int armada38x_rtc_set_offset(struct device *dev, long offset)\n{\n\tstruct armada38x_rtc *rtc = dev_get_drvdata(dev);\n\tunsigned long ccr = 0;\n\tlong ppb_cor, off;\n\n\t/*\n\t * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we\n\t * need to clamp the input.  This equates to -484270 .. 488558.\n\t * Not only is this to stop out of range \"off\" but also to\n\t * avoid the division by zero in armada38x_ppb_convert().\n\t */\n\toffset = clamp(offset, -484270L, 488558L);\n\n\tppb_cor = armada38x_ppb_convert(offset);\n\n\t/*\n\t * Use low update mode where possible, which gives a better\n\t * resolution of correction.\n\t */\n\toff = DIV_ROUND_CLOSEST(ppb_cor, 954);\n\tif (off > 127 || off < -128) {\n\t\tccr = RTC_CCR_MODE;\n\t\toff = DIV_ROUND_CLOSEST(ppb_cor, 3815);\n\t}\n\n\t/*\n\t * Armada 388 requires a bit pattern in bits 14..8 depending on\n\t * the sign bit: { 0, ~S, S, S, S, S, S }\n\t */\n\tccr |= (off & 0x3fff) ^ 0x2000;\n\trtc_delayed_write(ccr, rtc, RTC_CCR);\n\n\treturn 0;\n}",
        "static void imx7_csi_configure(struct imx7_csi *csi)\n{\n\tstruct imx_media_video_dev *vdev = csi->vdev;\n\tstruct v4l2_pix_format *out_pix = &vdev->fmt;\n\tint width = out_pix->width;": "static void imx7_csi_configure(struct imx7_csi *csi)\n{\n\tstruct imx_media_video_dev *vdev = csi->vdev;\n\tstruct v4l2_pix_format *out_pix = &vdev->fmt;\n\tint width = out_pix->width;\n\tu32 stride = 0;\n\tu32 cr3 = BIT_FRMCNT_RST;\n\tu32 cr1, cr18;\n\n\tcr18 = imx7_csi_reg_read(csi, CSI_CSICR18);\n\n\tcr18 &= ~(BIT_CSI_HW_ENABLE | BIT_MIPI_DATA_FORMAT_MASK |\n\t\t  BIT_DATA_FROM_MIPI | BIT_BASEADDR_CHG_ERR_EN |\n\t\t  BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |\n\t\t  BIT_DEINTERLACE_EN);\n\n\tif (out_pix->field == V4L2_FIELD_INTERLACED) {\n\t\tcr18 |= BIT_DEINTERLACE_EN;\n\t\tstride = out_pix->width;\n\t}\n\n\tif (!csi->is_csi2) {\n\t\tcr1 = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL\n\t\t    | BIT_FCC | BIT_MCLKDIV(1) | BIT_MCLKEN;\n\n\t\tcr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |\n\t\t\tBIT_BASEADDR_CHG_ERR_EN;\n\n\t\tif (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||\n\t\t    out_pix->pixelformat == V4L2_PIX_FMT_YUYV)\n\t\t\twidth *= 2;\n\t} else {\n\t\tcr1 = BIT_SOF_POL | BIT_REDGE | BIT_HSYNC_POL | BIT_FCC\n\t\t    | BIT_MCLKDIV(1) | BIT_MCLKEN;\n\n\t\tcr18 |= BIT_DATA_FROM_MIPI;\n\n\t\tswitch (csi->format_mbus[IMX7_CSI_PAD_SINK].code) {\n\t\tcase MEDIA_BUS_FMT_Y8_1X8:\n\t\tcase MEDIA_BUS_FMT_SBGGR8_1X8:\n\t\tcase MEDIA_BUS_FMT_SGBRG8_1X8:\n\t\tcase MEDIA_BUS_FMT_SGRBG8_1X8:\n\t\tcase MEDIA_BUS_FMT_SRGGB8_1X8:\n\t\t\tcr18 |= BIT_MIPI_DATA_FORMAT_RAW8;\n\t\t\tbreak;\n\t\tcase MEDIA_BUS_FMT_Y10_1X10:\n\t\tcase MEDIA_BUS_FMT_SBGGR10_1X10:\n\t\tcase MEDIA_BUS_FMT_SGBRG10_1X10:\n\t\tcase MEDIA_BUS_FMT_SGRBG10_1X10:\n\t\tcase MEDIA_BUS_FMT_SRGGB10_1X10:\n\t\t\tcr3 |= BIT_TWO_8BIT_SENSOR;\n\t\t\tcr18 |= BIT_MIPI_DATA_FORMAT_RAW10;\n\t\t\tbreak;\n\t\tcase MEDIA_BUS_FMT_Y12_1X12:\n\t\tcase MEDIA_BUS_FMT_SBGGR12_1X12:\n\t\tcase MEDIA_BUS_FMT_SGBRG12_1X12:\n\t\tcase MEDIA_BUS_FMT_SGRBG12_1X12:\n\t\tcase MEDIA_BUS_FMT_SRGGB12_1X12:\n\t\t\tcr3 |= BIT_TWO_8BIT_SENSOR;\n\t\t\tcr18 |= BIT_MIPI_DATA_FORMAT_RAW12;\n\t\t\tbreak;\n\t\tcase MEDIA_BUS_FMT_Y14_1X14:\n\t\tcase MEDIA_BUS_FMT_SBGGR14_1X14:\n\t\tcase MEDIA_BUS_FMT_SGBRG14_1X14:\n\t\tcase MEDIA_BUS_FMT_SGRBG14_1X14:\n\t\tcase MEDIA_BUS_FMT_SRGGB14_1X14:\n\t\t\tcr3 |= BIT_TWO_8BIT_SENSOR;\n\t\t\tcr18 |= BIT_MIPI_DATA_FORMAT_RAW14;\n\t\t\tbreak;\n\n\t\t/*\n\t\t * The CSI bridge has a 16-bit input bus. Depending on the\n\t\t * connected source, data may be transmitted with 8 or 10 bits\n\t\t * per clock sample (in bits [9:2] or [9:0] respectively) or\n\t\t * with 16 bits per clock sample (in bits [15:0]). The data is\n\t\t * then packed into a 32-bit FIFO (as shown in figure 13-11 of\n\t\t * the i.MX8MM reference manual rev. 3).\n\t\t *\n\t\t * The data packing in a 32-bit FIFO input word is controlled by\n\t\t * the CR3 TWO_8BIT_SENSOR field (also known as SENSOR_16BITS in\n\t\t * the i.MX8MM reference manual). When set to 0, data packing\n\t\t * groups four 8-bit input samples (bits [9:2]). When set to 1,\n\t\t * data packing groups two 16-bit input samples (bits [15:0]).\n\t\t *\n\t\t * The register field CR18 MIPI_DOUBLE_CMPNT also needs to be\n\t\t * configured according to the input format for YUV 4:2:2 data.\n\t\t * The field controls the gasket between the CSI-2 receiver and\n\t\t * the CSI bridge. On i.MX7 and i.MX8MM, the field must be set\n\t\t * to 1 when the CSIS outputs 16-bit samples. On i.MX8MQ, the\n\t\t * gasket ignores the MIPI_DOUBLE_CMPNT bit and YUV 4:2:2 always\n\t\t * uses 16-bit samples. Setting MIPI_DOUBLE_CMPNT in that case\n\t\t * has no effect, but doesn't cause any issue.\n\t\t */\n\t\tcase MEDIA_BUS_FMT_UYVY8_2X8:\n\t\tcase MEDIA_BUS_FMT_YUYV8_2X8:\n\t\t\tcr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;\n\t\t\tbreak;\n\t\tcase MEDIA_BUS_FMT_UYVY8_1X16:\n\t\tcase MEDIA_BUS_FMT_YUYV8_1X16:\n\t\t\tcr3 |= BIT_TWO_8BIT_SENSOR;\n\t\t\tcr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B |\n\t\t\t\tBIT_MIPI_DOUBLE_CMPNT;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\timx7_csi_reg_write(csi, cr1, CSI_CSICR1);\n\timx7_csi_reg_write(csi, BIT_DMA_BURST_TYPE_RFF_INCR16, CSI_CSICR2);\n\timx7_csi_reg_write(csi, cr3, CSI_CSICR3);\n\timx7_csi_reg_write(csi, cr18, CSI_CSICR18);\n\n\timx7_csi_reg_write(csi, (width * out_pix->height) >> 2, CSI_CSIRXCNT);\n\timx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(width) |\n\t\t\t   BIT_IMAGE_HEIGHT(out_pix->height),\n\t\t\t   CSI_CSIIMAG_PARA);\n\timx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA);\n}",
        "static unsigned int fun_xdpq_clean(struct funeth_txq *q, unsigned int budget)\n{\n\tunsigned int npkts = 0, head, reclaim_idx;\n\n\tfor (head = txq_hw_head(q), reclaim_idx = q->cons_cnt & q->mask;": "static unsigned int fun_xdpq_clean(struct funeth_txq *q, unsigned int budget)\n{\n\tunsigned int npkts = 0, head, reclaim_idx;\n\n\tfor (head = txq_hw_head(q), reclaim_idx = q->cons_cnt & q->mask;\n\t     head != reclaim_idx && npkts < budget; head = txq_hw_head(q)) {\n\t\t/* The HW head is continually updated, ensure we don't read\n\t\t * descriptor state before the head tells us to reclaim it.\n\t\t * On the enqueue side the doorbell is an implicit write\n\t\t * barrier.\n\t\t */\n\t\trmb();\n\n\t\tdo {\n\t\t\tfun_xdp_unmap(q, reclaim_idx);\n\t\t\tpage_frag_free(q->info[reclaim_idx].vaddr);\n\n\t\t\ttrace_funeth_tx_free(q, reclaim_idx, 1, head);\n\n\t\t\treclaim_idx = (reclaim_idx + 1) & q->mask;\n\t\t\tnpkts++;\n\t\t} while (reclaim_idx != head && npkts < budget);\n\t}\n\n\tq->cons_cnt += npkts;\n\treturn npkts;\n}",
        "static void print_help(void)\n{\n\tprintf(\"usage: ksm_tests [-h] <test type> [-a prot] [-p page_count] [-l timeout]\\n\"\n\t       \"[-z use_zero_pages] [-m merge_across_nodes] [-s size]\\n\");\n": "static void print_help(void)\n{\n\tprintf(\"usage: ksm_tests [-h] <test type> [-a prot] [-p page_count] [-l timeout]\\n\"\n\t       \"[-z use_zero_pages] [-m merge_across_nodes] [-s size]\\n\");\n\n\tprintf(\"Supported <test type>:\\n\"\n\t       \" -M (page merging)\\n\"\n\t       \" -Z (zero pages merging)\\n\"\n\t       \" -N (merging of pages in different NUMA nodes)\\n\"\n\t       \" -U (page unmerging)\\n\"\n\t       \" -P evaluate merging time and speed.\\n\"\n\t       \"    For this test, the size of duplicated memory area (in MiB)\\n\"\n\t       \"    must be provided using -s option\\n\"\n\t\t\t\t \" -H evaluate merging time and speed of area allocated mostly with huge pages\\n\"\n\t       \"    For this test, the size of duplicated memory area (in MiB)\\n\"\n\t       \"    must be provided using -s option\\n\"\n\t       \" -C evaluate the time required to break COW of merged pages.\\n\\n\");\n\n\tprintf(\" -a: specify the access protections of pages.\\n\"\n\t       \"     <prot> must be of the form [rwx].\\n\"\n\t       \"     Default: %s\\n\", KSM_PROT_STR_DEFAULT);\n\tprintf(\" -p: specify the number of pages to test.\\n\"\n\t       \"     Default: %ld\\n\", KSM_PAGE_COUNT_DEFAULT);\n\tprintf(\" -l: limit the maximum running time (in seconds) for a test.\\n\"\n\t       \"     Default: %d seconds\\n\", KSM_SCAN_LIMIT_SEC_DEFAULT);\n\tprintf(\" -z: change use_zero_pages tunable\\n\"\n\t       \"     Default: %d\\n\", KSM_USE_ZERO_PAGES_DEFAULT);\n\tprintf(\" -m: change merge_across_nodes tunable\\n\"\n\t       \"     Default: %d\\n\", KSM_MERGE_ACROSS_NODES_DEFAULT);\n\tprintf(\" -s: the size of duplicated memory area (in MiB)\\n\");\n\n\texit(0);\n}",
        "static void init_chained_smb2_rsp(struct ksmbd_work *work)\n{\n\tstruct smb2_hdr *req = ksmbd_req_buf_next(work);\n\tstruct smb2_hdr *rsp = ksmbd_resp_buf_next(work);\n\tstruct smb2_hdr *rsp_hdr;": "static void init_chained_smb2_rsp(struct ksmbd_work *work)\n{\n\tstruct smb2_hdr *req = ksmbd_req_buf_next(work);\n\tstruct smb2_hdr *rsp = ksmbd_resp_buf_next(work);\n\tstruct smb2_hdr *rsp_hdr;\n\tstruct smb2_hdr *rcv_hdr;\n\tint next_hdr_offset = 0;\n\tint len, new_len;\n\n\t/* Len of this response = updated RFC len - offset of previous cmd\n\t * in the compound rsp\n\t */\n\n\t/* Storing the current local FID which may be needed by subsequent\n\t * command in the compound request\n\t */\n\tif (req->Command == SMB2_CREATE && rsp->Status == STATUS_SUCCESS) {\n\t\twork->compound_fid = ((struct smb2_create_rsp *)rsp)->VolatileFileId;\n\t\twork->compound_pfid = ((struct smb2_create_rsp *)rsp)->PersistentFileId;\n\t\twork->compound_sid = le64_to_cpu(rsp->SessionId);\n\t}\n\n\tlen = get_rfc1002_len(work->response_buf) - work->next_smb2_rsp_hdr_off;\n\tnext_hdr_offset = le32_to_cpu(req->NextCommand);\n\n\tnew_len = ALIGN(len, 8);\n\tinc_rfc1001_len(work->response_buf,\n\t\t\tsizeof(struct smb2_hdr) + new_len - len);\n\trsp->NextCommand = cpu_to_le32(new_len);\n\n\twork->next_smb2_rcv_hdr_off += next_hdr_offset;\n\twork->next_smb2_rsp_hdr_off += new_len;\n\tksmbd_debug(SMB,\n\t\t    \"Compound req new_len = %d rcv off = %d rsp off = %d\\n\",\n\t\t    new_len, work->next_smb2_rcv_hdr_off,\n\t\t    work->next_smb2_rsp_hdr_off);\n\n\trsp_hdr = ksmbd_resp_buf_next(work);\n\trcv_hdr = ksmbd_req_buf_next(work);\n\n\tif (!(rcv_hdr->Flags & SMB2_FLAGS_RELATED_OPERATIONS)) {\n\t\tksmbd_debug(SMB, \"related flag should be set\\n\");\n\t\twork->compound_fid = KSMBD_NO_FID;\n\t\twork->compound_pfid = KSMBD_NO_FID;\n\t}\n\tmemset((char *)rsp_hdr, 0, sizeof(struct smb2_hdr) + 2);\n\trsp_hdr->ProtocolId = SMB2_PROTO_NUMBER;\n\trsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE;\n\trsp_hdr->Command = rcv_hdr->Command;\n\n\t/*\n\t * Message is response. We don't grant oplock yet.\n\t */\n\trsp_hdr->Flags = (SMB2_FLAGS_SERVER_TO_REDIR |\n\t\t\t\tSMB2_FLAGS_RELATED_OPERATIONS);\n\trsp_hdr->NextCommand = 0;\n\trsp_hdr->MessageId = rcv_hdr->MessageId;\n\trsp_hdr->Id.SyncId.ProcessId = rcv_hdr->Id.SyncId.ProcessId;\n\trsp_hdr->Id.SyncId.TreeId = rcv_hdr->Id.SyncId.TreeId;\n\trsp_hdr->SessionId = rcv_hdr->SessionId;\n\tmemcpy(rsp_hdr->Signature, rcv_hdr->Signature, 16);\n}",
        "static void mport_cdev_remove(struct mport_dev *md)\n{\n\tstruct rio_mport_mapping *map, *_map;\n\n\trmcd_debug(EXIT, \"Remove %s cdev\", md->mport->name);": "static void mport_cdev_remove(struct mport_dev *md)\n{\n\tstruct rio_mport_mapping *map, *_map;\n\n\trmcd_debug(EXIT, \"Remove %s cdev\", md->mport->name);\n\tatomic_set(&md->active, 0);\n\tmport_cdev_terminate_dma(md);\n\trio_del_mport_pw_handler(md->mport, md, rio_mport_pw_handler);\n\tcdev_device_del(&md->cdev, &md->dev);\n\tmport_cdev_kill_fasync(md);\n\n\t/* TODO: do we need to give clients some time to close file\n\t * descriptors? Simple wait for XX, or kref?\n\t */\n\n\t/*\n\t * Release DMA buffers allocated for the mport device.\n\t * Disable associated inbound Rapidio requests mapping if applicable.\n\t */\n\tmutex_lock(&md->buf_mutex);\n\tlist_for_each_entry_safe(map, _map, &md->mappings, node) {\n\t\tkref_put(&map->ref, mport_release_mapping);\n\t}\n\tmutex_unlock(&md->buf_mutex);\n\n\tif (!list_empty(&md->mappings))\n\t\trmcd_warn(\"WARNING: %s pending mappings on removal\",\n\t\t\t  md->mport->name);\n\n\trio_release_inb_dbell(md->mport, 0, 0x0fff);\n\n\tput_device(&md->dev);\n}",
        "static int tile_buffer_reallocate(struct hantro_ctx *ctx)\n{\n\tstruct hantro_dev *vpu = ctx->dev;\n\tstruct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;": "static int tile_buffer_reallocate(struct hantro_ctx *ctx)\n{\n\tstruct hantro_dev *vpu = ctx->dev;\n\tstruct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;\n\tconst struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;\n\tunsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;\n\tunsigned int height64 = (sps->pic_height_in_luma_samples + 63) & ~63;\n\tunsigned int size;\n\n\tif (num_tile_cols <= 1 ||\n\t    num_tile_cols <= hevc_dec->num_tile_cols_allocated)\n\t\treturn 0;\n\n\t/* Need to reallocate due to tiles passed via PPS */\n\tif (hevc_dec->tile_filter.cpu) {\n\t\tdma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,\n\t\t\t\t  hevc_dec->tile_filter.cpu,\n\t\t\t\t  hevc_dec->tile_filter.dma);\n\t\thevc_dec->tile_filter.cpu = NULL;\n\t}\n\n\tif (hevc_dec->tile_sao.cpu) {\n\t\tdma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,\n\t\t\t\t  hevc_dec->tile_sao.cpu,\n\t\t\t\t  hevc_dec->tile_sao.dma);\n\t\thevc_dec->tile_sao.cpu = NULL;\n\t}\n\n\tif (hevc_dec->tile_bsd.cpu) {\n\t\tdma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,\n\t\t\t\t  hevc_dec->tile_bsd.cpu,\n\t\t\t\t  hevc_dec->tile_bsd.dma);\n\t\thevc_dec->tile_bsd.cpu = NULL;\n\t}\n\n\tsize = VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1);\n\thevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size,\n\t\t\t\t\t\t       &hevc_dec->tile_filter.dma,\n\t\t\t\t\t\t       GFP_KERNEL);\n\tif (!hevc_dec->tile_filter.cpu)\n\t\tgoto err_free_tile_buffers;\n\thevc_dec->tile_filter.size = size;\n\n\tsize = VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1);\n\thevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size,\n\t\t\t\t\t\t    &hevc_dec->tile_sao.dma,\n\t\t\t\t\t\t    GFP_KERNEL);\n\tif (!hevc_dec->tile_sao.cpu)\n\t\tgoto err_free_tile_buffers;\n\thevc_dec->tile_sao.size = size;\n\n\tsize = BSD_CTRL_RAM_SIZE * height64 * (num_tile_cols - 1);\n\thevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size,\n\t\t\t\t\t\t    &hevc_dec->tile_bsd.dma,\n\t\t\t\t\t\t    GFP_KERNEL);\n\tif (!hevc_dec->tile_bsd.cpu)\n\t\tgoto err_free_tile_buffers;\n\thevc_dec->tile_bsd.size = size;\n\n\thevc_dec->num_tile_cols_allocated = num_tile_cols;\n\n\treturn 0;\n\nerr_free_tile_buffers:\n\tif (hevc_dec->tile_filter.cpu)\n\t\tdma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,\n\t\t\t\t  hevc_dec->tile_filter.cpu,\n\t\t\t\t  hevc_dec->tile_filter.dma);\n\thevc_dec->tile_filter.cpu = NULL;\n\n\tif (hevc_dec->tile_sao.cpu)\n\t\tdma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,\n\t\t\t\t  hevc_dec->tile_sao.cpu,\n\t\t\t\t  hevc_dec->tile_sao.dma);\n\thevc_dec->tile_sao.cpu = NULL;\n\n\tif (hevc_dec->tile_bsd.cpu)\n\t\tdma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,\n\t\t\t\t  hevc_dec->tile_bsd.cpu,\n\t\t\t\t  hevc_dec->tile_bsd.dma);\n\thevc_dec->tile_bsd.cpu = NULL;\n\n\treturn -ENOMEM;\n}",
        "static void __three_after_loss(struct tfrc_rx_hist *h)\n{\n\t/*\n\t * At this stage we know already that there is a gap between S0 and S1\n\t * (since S0 was the highest sequence number received before detecting": "static void __three_after_loss(struct tfrc_rx_hist *h)\n{\n\t/*\n\t * At this stage we know already that there is a gap between S0 and S1\n\t * (since S0 was the highest sequence number received before detecting\n\t * the loss). To recycle the loss record, it is\tthus only necessary to\n\t * check for other possible gaps between S1/S2 and between S2/S3.\n\t */\n\tu64 s1 = tfrc_rx_hist_entry(h, 1)->tfrchrx_seqno,\n\t    s2 = tfrc_rx_hist_entry(h, 2)->tfrchrx_seqno,\n\t    s3 = tfrc_rx_hist_entry(h, 3)->tfrchrx_seqno;\n\tu64 n2 = tfrc_rx_hist_entry(h, 2)->tfrchrx_ndp,\n\t    n3 = tfrc_rx_hist_entry(h, 3)->tfrchrx_ndp;\n\n\tif (dccp_loss_free(s1, s2, n2)) {\n\n\t\tif (dccp_loss_free(s2, s3, n3)) {\n\t\t\t/* no gap between S2 and S3: entire hole is filled */\n\t\t\th->loss_start = tfrc_rx_hist_index(h, 3);\n\t\t\th->loss_count = 0;\n\t\t} else {\n\t\t\t/* gap between S2 and S3 */\n\t\t\th->loss_start = tfrc_rx_hist_index(h, 2);\n\t\t\th->loss_count = 1;\n\t\t}\n\n\t} else {\t/* gap between S1 and S2 */\n\t\th->loss_start = tfrc_rx_hist_index(h, 1);\n\t\th->loss_count = 2;\n\t}\n}",
        "static void print_trailer(struct kmem_cache *s, struct slab *slab, u8 *p)\n{\n\tunsigned int off;\t/* Offset of last byte */\n\tu8 *addr = slab_address(slab);\n": "static void print_trailer(struct kmem_cache *s, struct slab *slab, u8 *p)\n{\n\tunsigned int off;\t/* Offset of last byte */\n\tu8 *addr = slab_address(slab);\n\n\tprint_tracking(s, p);\n\n\tprint_slab_info(slab);\n\n\tpr_err(\"Object 0x%p @offset=%tu fp=0x%p\\n\\n\",\n\t       p, p - addr, get_freepointer(s, p));\n\n\tif (s->flags & SLAB_RED_ZONE)\n\t\tprint_section(KERN_ERR, \"Redzone  \", p - s->red_left_pad,\n\t\t\t      s->red_left_pad);\n\telse if (p > addr + 16)\n\t\tprint_section(KERN_ERR, \"Bytes b4 \", p - 16, 16);\n\n\tprint_section(KERN_ERR,         \"Object   \", p,\n\t\t      min_t(unsigned int, s->object_size, PAGE_SIZE));\n\tif (s->flags & SLAB_RED_ZONE)\n\t\tprint_section(KERN_ERR, \"Redzone  \", p + s->object_size,\n\t\t\ts->inuse - s->object_size);\n\n\toff = get_info_end(s);\n\n\tif (s->flags & SLAB_STORE_USER)\n\t\toff += 2 * sizeof(struct track);\n\n\toff += kasan_metadata_size(s);\n\n\tif (off != size_from_object(s))\n\t\t/* Beginning of the filler is the free pointer */\n\t\tprint_section(KERN_ERR, \"Padding  \", p + off,\n\t\t\t      size_from_object(s) - off);\n\n\tdump_stack();\n}",
        "static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)\n{\n\tstruct bnx2x *bp = params->bp;\n\tu32 is_port4mode = bnx2x_is_4_port_mode(bp);\n": "static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)\n{\n\tstruct bnx2x *bp = params->bp;\n\tu32 is_port4mode = bnx2x_is_4_port_mode(bp);\n\n\t/* In 4-port mode, need to set the mode only once, so if XMAC is\n\t * already out of reset, it means the mode has already been set,\n\t * and it must not* reset the XMAC again, since it controls both\n\t * ports of the path\n\t */\n\n\tif (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||\n\t     (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||\n\t     (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&\n\t    is_port4mode &&\n\t    (REG_RD(bp, MISC_REG_RESET_REG_2) &\n\t     MISC_REGISTERS_RESET_REG_2_XMAC)) {\n\t\tDP(NETIF_MSG_LINK,\n\t\t   \"XMAC already out of reset in 4-port mode\\n\");\n\t\treturn;\n\t}\n\n\t/* Hard reset */\n\tREG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t       MISC_REGISTERS_RESET_REG_2_XMAC);\n\tusleep_range(1000, 2000);\n\n\tREG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t       MISC_REGISTERS_RESET_REG_2_XMAC);\n\tif (is_port4mode) {\n\t\tDP(NETIF_MSG_LINK, \"Init XMAC to 2 ports x 10G per path\\n\");\n\n\t\t/* Set the number of ports on the system side to up to 2 */\n\t\tREG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);\n\n\t\t/* Set the number of ports on the Warp Core to 10G */\n\t\tREG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);\n\t} else {\n\t\t/* Set the number of ports on the system side to 1 */\n\t\tREG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);\n\t\tif (max_speed == SPEED_10000) {\n\t\t\tDP(NETIF_MSG_LINK,\n\t\t\t   \"Init XMAC to 10G x 1 port per path\\n\");\n\t\t\t/* Set the number of ports on the Warp Core to 10G */\n\t\t\tREG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);\n\t\t} else {\n\t\t\tDP(NETIF_MSG_LINK,\n\t\t\t   \"Init XMAC to 20G x 2 ports per path\\n\");\n\t\t\t/* Set the number of ports on the Warp Core to 20G */\n\t\t\tREG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);\n\t\t}\n\t}\n\t/* Soft reset */\n\tREG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t       MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);\n\tusleep_range(1000, 2000);\n\n\tREG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t       MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);\n\n}",
        "static void handle_backoff_block(struct ceph_osd *osd, struct MOSDBackoff *m)\n{\n\tstruct ceph_spg_mapping *spg;\n\tstruct ceph_osd_backoff *backoff;\n\tstruct ceph_msg *msg;": "static void handle_backoff_block(struct ceph_osd *osd, struct MOSDBackoff *m)\n{\n\tstruct ceph_spg_mapping *spg;\n\tstruct ceph_osd_backoff *backoff;\n\tstruct ceph_msg *msg;\n\n\tdout(\"%s osd%d spgid %llu.%xs%d id %llu\\n\", __func__, osd->o_osd,\n\t     m->spgid.pgid.pool, m->spgid.pgid.seed, m->spgid.shard, m->id);\n\n\tspg = lookup_spg_mapping(&osd->o_backoff_mappings, &m->spgid);\n\tif (!spg) {\n\t\tspg = alloc_spg_mapping();\n\t\tif (!spg) {\n\t\t\tpr_err(\"%s failed to allocate spg\\n\", __func__);\n\t\t\treturn;\n\t\t}\n\t\tspg->spgid = m->spgid; /* struct */\n\t\tinsert_spg_mapping(&osd->o_backoff_mappings, spg);\n\t}\n\n\tbackoff = alloc_backoff();\n\tif (!backoff) {\n\t\tpr_err(\"%s failed to allocate backoff\\n\", __func__);\n\t\treturn;\n\t}\n\tbackoff->spgid = m->spgid; /* struct */\n\tbackoff->id = m->id;\n\tbackoff->begin = m->begin;\n\tm->begin = NULL; /* backoff now owns this */\n\tbackoff->end = m->end;\n\tm->end = NULL;   /* ditto */\n\n\tinsert_backoff(&spg->backoffs, backoff);\n\tinsert_backoff_by_id(&osd->o_backoffs_by_id, backoff);\n\n\t/*\n\t * Ack with original backoff's epoch so that the OSD can\n\t * discard this if there was a PG split.\n\t */\n\tmsg = create_backoff_message(backoff, m->map_epoch);\n\tif (!msg) {\n\t\tpr_err(\"%s failed to allocate msg\\n\", __func__);\n\t\treturn;\n\t}\n\tceph_con_send(&osd->o_con, msg);\n}",
        "static int patch_sigmatel_stac9708(struct snd_ac97 * ac97)\n{\n\tunsigned int codec72, codec6c;\n\n\tac97->build_ops = &patch_sigmatel_stac9708_ops;": "static int patch_sigmatel_stac9708(struct snd_ac97 * ac97)\n{\n\tunsigned int codec72, codec6c;\n\n\tac97->build_ops = &patch_sigmatel_stac9708_ops;\n\tac97->caps |= 0x10;\t/* HP (sigmatel surround) support */\n\n\tcodec72 = snd_ac97_read(ac97, AC97_SIGMATEL_BIAS2) & 0x8000;\n\tcodec6c = snd_ac97_read(ac97, AC97_SIGMATEL_ANALOG);\n\n\tif ((codec72==0) && (codec6c==0)) {\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba);\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x1000);\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS1, 0xabba);\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_BIAS2, 0x0007);\n\t} else if ((codec72==0x8000) && (codec6c==0)) {\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC1, 0xabba);\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_CIC2, 0x1001);\n\t\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_DAC2INVERT, 0x0008);\n\t} else if ((codec72==0x8000) && (codec6c==0x0080)) {\n\t\t/* nothing */\n\t}\n\tsnd_ac97_write_cache(ac97, AC97_SIGMATEL_MULTICHN, 0x0000);\n\treturn 0;\n}",
        "static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)\n{\n\tstruct otx2_cptlfs_info *lfs = &cptvf->lfs;\n\tstruct device *dev = &cptvf->pdev->dev;\n\tint ret, lfs_num;": "static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)\n{\n\tstruct otx2_cptlfs_info *lfs = &cptvf->lfs;\n\tstruct device *dev = &cptvf->pdev->dev;\n\tint ret, lfs_num;\n\tu8 eng_grp_msk;\n\n\t/* Get engine group number for symmetric crypto */\n\tcptvf->lfs.kcrypto_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;\n\tret = otx2_cptvf_send_eng_grp_num_msg(cptvf, OTX2_CPT_SE_TYPES);\n\tif (ret)\n\t\treturn ret;\n\n\tif (cptvf->lfs.kcrypto_eng_grp_num == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {\n\t\tdev_err(dev, \"Engine group for kernel crypto not available\\n\");\n\t\tret = -ENOENT;\n\t\treturn ret;\n\t}\n\teng_grp_msk = 1 << cptvf->lfs.kcrypto_eng_grp_num;\n\n\tret = otx2_cptvf_send_kvf_limits_msg(cptvf);\n\tif (ret)\n\t\treturn ret;\n\n\tlfs->reg_base = cptvf->reg_base;\n\tlfs->pdev = cptvf->pdev;\n\tlfs->mbox = &cptvf->pfvf_mbox;\n\n\tlfs_num = cptvf->lfs.kvf_limits ? cptvf->lfs.kvf_limits :\n\t\t  num_online_cpus();\n\tret = otx2_cptlf_init(lfs, eng_grp_msk, OTX2_CPT_QUEUE_HI_PRIO,\n\t\t\t      lfs_num);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Get msix offsets for attached LFs */\n\tret = otx2_cpt_msix_offset_msg(lfs);\n\tif (ret)\n\t\tgoto cleanup_lf;\n\n\t/* Initialize LFs software side */\n\tret = lf_sw_init(lfs);\n\tif (ret)\n\t\tgoto cleanup_lf;\n\n\t/* Register LFs interrupts */\n\tret = otx2_cptlf_register_interrupts(lfs);\n\tif (ret)\n\t\tgoto cleanup_lf_sw;\n\n\t/* Set interrupts affinity */\n\tret = otx2_cptlf_set_irqs_affinity(lfs);\n\tif (ret)\n\t\tgoto unregister_intr;\n\n\tatomic_set(&lfs->state, OTX2_CPTLF_STARTED);\n\t/* Register crypto algorithms */\n\tret = otx2_cpt_crypto_init(lfs->pdev, THIS_MODULE, lfs_num, 1);\n\tif (ret) {\n\t\tdev_err(&lfs->pdev->dev, \"algorithms registration failed\\n\");\n\t\tgoto disable_irqs;\n\t}\n\treturn 0;\n\ndisable_irqs:\n\totx2_cptlf_free_irqs_affinity(lfs);\nunregister_intr:\n\totx2_cptlf_unregister_interrupts(lfs);\ncleanup_lf_sw:\n\tlf_sw_cleanup(lfs);\ncleanup_lf:\n\totx2_cptlf_shutdown(lfs);\n\n\treturn ret;\n}",
        "static int madera_enable_fll(struct madera_fll *fll)\n{\n\tstruct madera *madera = fll->madera;\n\tbool have_sync = false;\n\tint already_enabled = madera_is_enabled_fll(fll, fll->base);": "static int madera_enable_fll(struct madera_fll *fll)\n{\n\tstruct madera *madera = fll->madera;\n\tbool have_sync = false;\n\tint already_enabled = madera_is_enabled_fll(fll, fll->base);\n\tint sync_enabled;\n\tstruct madera_fll_cfg cfg;\n\tunsigned int sync_base;\n\tint gain, ret;\n\tbool fll_change = false;\n\n\tif (already_enabled < 0)\n\t\treturn already_enabled;\t/* error getting current state */\n\n\tif (fll->ref_src < 0 || fll->ref_freq == 0) {\n\t\tmadera_fll_err(fll, \"No REFCLK\\n\");\n\t\tret = -EINVAL;\n\t\tgoto err;\n\t}\n\n\tmadera_fll_dbg(fll, \"Enabling FLL, initially %s\\n\",\n\t\t       already_enabled ? \"enabled\" : \"disabled\");\n\n\tif (fll->fout < MADERA_FLL_MIN_FOUT ||\n\t    fll->fout > MADERA_FLL_MAX_FOUT) {\n\t\tmadera_fll_err(fll, \"invalid fout %uHz\\n\", fll->fout);\n\t\tret = -EINVAL;\n\t\tgoto err;\n\t}\n\n\tswitch (madera->type) {\n\tcase CS47L35:\n\t\tsync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS;\n\t\tbreak;\n\tdefault:\n\t\tsync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS;\n\t\tbreak;\n\t}\n\n\tsync_enabled = madera_is_enabled_fll(fll, sync_base);\n\tif (sync_enabled < 0)\n\t\treturn sync_enabled;\n\n\tif (already_enabled) {\n\t\t/* Facilitate smooth refclk across the transition */\n\t\tregmap_update_bits(fll->madera->regmap,\n\t\t\t\t   fll->base + MADERA_FLL_CONTROL_1_OFFS,\n\t\t\t\t   MADERA_FLL1_FREERUN,\n\t\t\t\t   MADERA_FLL1_FREERUN);\n\t\tudelay(32);\n\t\tregmap_update_bits(fll->madera->regmap,\n\t\t\t\t   fll->base + MADERA_FLL_CONTROL_7_OFFS,\n\t\t\t\t   MADERA_FLL1_GAIN_MASK, 0);\n\n\t\tif (sync_enabled > 0)\n\t\t\tmadera_set_fll_clks(fll, sync_base, false);\n\t\tmadera_set_fll_clks(fll, fll->base, false);\n\t}\n\n\t/* Apply SYNCCLK setting */\n\tif (fll->sync_src >= 0) {\n\t\tret = madera_calc_fll(fll, &cfg, fll->sync_freq, true);\n\t\tif (ret < 0)\n\t\t\tgoto err;\n\n\t\tfll_change |= madera_write_fll(madera, sync_base,\n\t\t\t\t\t       &cfg, fll->sync_src,\n\t\t\t\t\t       true, cfg.gain);\n\t\thave_sync = true;\n\t}\n\n\tif (already_enabled && !!sync_enabled != have_sync)\n\t\tmadera_fll_warn(fll, \"Synchroniser changed on active FLL\\n\");\n\n\t/* Apply REFCLK setting */\n\tret = madera_calc_fll(fll, &cfg, fll->ref_freq, false);\n\tif (ret < 0)\n\t\tgoto err;\n\n\t/* Ref path hardcodes lambda to 65536 when sync is on */\n\tif (have_sync && cfg.lambda)\n\t\tcfg.theta = (cfg.theta * (1 << 16)) / cfg.lambda;\n\n\tswitch (fll->madera->type) {\n\tcase CS47L35:\n\t\tswitch (fll->madera->rev) {\n\t\tcase 0:\n\t\t\tgain = cfg.gain;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tfll_change |=\n\t\t\t\tmadera_set_fll_phase_integrator(fll, &cfg,\n\t\t\t\t\t\t\t\thave_sync);\n\t\t\tif (!have_sync && cfg.theta == 0)\n\t\t\t\tgain = cfg.alt_gain;\n\t\t\telse\n\t\t\t\tgain = cfg.gain;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase CS47L85:\n\tcase WM1840:\n\t\tgain = cfg.gain;\n\t\tbreak;\n\tdefault:\n\t\tfll_change |= madera_set_fll_phase_integrator(fll, &cfg,\n\t\t\t\t\t\t\t      have_sync);\n\t\tif (!have_sync && cfg.theta == 0)\n\t\t\tgain = cfg.alt_gain;\n\t\telse\n\t\t\tgain = cfg.gain;\n\t\tbreak;\n\t}\n\n\tfll_change |= madera_write_fll(madera, fll->base,\n\t\t\t\t       &cfg, fll->ref_src,\n\t\t\t\t       false, gain);\n\n\t/*\n\t * Increase the bandwidth if we're not using a low frequency\n\t * sync source.\n\t */\n\tif (have_sync && fll->sync_freq > 100000)\n\t\tregmap_update_bits(madera->regmap,\n\t\t\t\t   sync_base + MADERA_FLL_SYNCHRONISER_7_OFFS,\n\t\t\t\t   MADERA_FLL1_SYNC_DFSAT_MASK, 0);\n\telse\n\t\tregmap_update_bits(madera->regmap,\n\t\t\t\t   sync_base + MADERA_FLL_SYNCHRONISER_7_OFFS,\n\t\t\t\t   MADERA_FLL1_SYNC_DFSAT_MASK,\n\t\t\t\t   MADERA_FLL1_SYNC_DFSAT);\n\n\tif (!already_enabled)\n\t\tpm_runtime_get_sync(madera->dev);\n\n\tif (have_sync) {\n\t\tmadera_set_fll_clks(fll, sync_base, true);\n\t\tregmap_update_bits(madera->regmap,\n\t\t\t\t   sync_base + MADERA_FLL_SYNCHRONISER_1_OFFS,\n\t\t\t\t   MADERA_FLL1_SYNC_ENA,\n\t\t\t\t   MADERA_FLL1_SYNC_ENA);\n\t}\n\n\tmadera_set_fll_clks(fll, fll->base, true);\n\tregmap_update_bits(madera->regmap,\n\t\t\t   fll->base + MADERA_FLL_CONTROL_1_OFFS,\n\t\t\t   MADERA_FLL1_ENA, MADERA_FLL1_ENA);\n\n\tif (already_enabled)\n\t\tregmap_update_bits(madera->regmap,\n\t\t\t\t   fll->base + MADERA_FLL_CONTROL_1_OFFS,\n\t\t\t\t   MADERA_FLL1_FREERUN, 0);\n\n\tif (fll_change || !already_enabled)\n\t\tmadera_wait_for_fll(fll, true);\n\n\treturn 0;\n\nerr:\n\t /* In case of error don't leave the FLL running with an old config */\n\tmadera_disable_fll(fll);\n\n\treturn ret;\n}",
        "static int child_f(unsigned int nr, int test_desc_fd, int cmd_fd, void *buf)\n{\n\tstruct xfrm_desc desc;\n\tstruct test_desc msg;\n\tint xfrm_sock = -1;": "static int child_f(unsigned int nr, int test_desc_fd, int cmd_fd, void *buf)\n{\n\tstruct xfrm_desc desc;\n\tstruct test_desc msg;\n\tint xfrm_sock = -1;\n\tuint32_t seq;\n\n\tif (switch_ns(nsfd_childa))\n\t\texit(KSFT_FAIL);\n\n\tif (netlink_sock(&xfrm_sock, &seq, NETLINK_XFRM)) {\n\t\tprintk(\"Failed to open xfrm netlink socket\");\n\t\texit(KSFT_FAIL);\n\t}\n\n\t/* Check that seq sock is ready, just for sure. */\n\tmemset(&msg, 0, sizeof(msg));\n\tmsg.type = MSG_ACK;\n\twrite_msg(cmd_fd, &msg, 1);\n\tread_msg(cmd_fd, &msg, 1);\n\tif (msg.type != MSG_ACK) {\n\t\tprintk(\"Ack failed\");\n\t\texit(KSFT_FAIL);\n\t}\n\n\tfor (;;) {\n\t\tssize_t received = read(test_desc_fd, &desc, sizeof(desc));\n\t\tint ret;\n\n\t\tif (received == 0) /* EOF */\n\t\t\tbreak;\n\n\t\tif (received != sizeof(desc)) {\n\t\t\tpr_err(\"read() returned %zd\", received);\n\t\t\texit(KSFT_FAIL);\n\t\t}\n\n\t\tswitch (desc.type) {\n\t\tcase CREATE_TUNNEL:\n\t\t\tret = child_serv(xfrm_sock, &seq, nr,\n\t\t\t\t\t cmd_fd, buf, &desc);\n\t\t\tbreak;\n\t\tcase ALLOCATE_SPI:\n\t\t\tret = xfrm_state_allocspi(xfrm_sock, &seq,\n\t\t\t\t\t\t  -1, desc.proto);\n\t\t\tbreak;\n\t\tcase MONITOR_ACQUIRE:\n\t\t\tret = xfrm_monitor_acquire(xfrm_sock, &seq, nr);\n\t\t\tbreak;\n\t\tcase EXPIRE_STATE:\n\t\t\tret = xfrm_expire_state(xfrm_sock, &seq, nr, &desc);\n\t\t\tbreak;\n\t\tcase EXPIRE_POLICY:\n\t\t\tret = xfrm_expire_policy(xfrm_sock, &seq, nr, &desc);\n\t\t\tbreak;\n\t\tcase SPDINFO_ATTRS:\n\t\t\tret = xfrm_spdinfo_attrs(xfrm_sock, &seq);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintk(\"Unknown desc type %d\", desc.type);\n\t\t\texit(KSFT_FAIL);\n\t\t}\n\t\twrite_test_result(ret, &desc);\n\t}\n\n\tclose(xfrm_sock);\n\n\tmsg.type = MSG_EXIT;\n\twrite_msg(cmd_fd, &msg, 1);\n\texit(KSFT_PASS);\n}",
        "static int inv_icm42600_buffer_postdisable(struct iio_dev *indio_dev)\n{\n\tstruct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);\n\tstruct device *dev = regmap_get_device(st->map);\n\tunsigned int sensor;": "static int inv_icm42600_buffer_postdisable(struct iio_dev *indio_dev)\n{\n\tstruct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);\n\tstruct device *dev = regmap_get_device(st->map);\n\tunsigned int sensor;\n\tunsigned int *watermark;\n\tstruct inv_icm42600_timestamp *ts;\n\tstruct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;\n\tunsigned int sleep_temp = 0;\n\tunsigned int sleep_sensor = 0;\n\tunsigned int sleep;\n\tint ret;\n\n\tif (indio_dev == st->indio_gyro) {\n\t\tsensor = INV_ICM42600_SENSOR_GYRO;\n\t\twatermark = &st->fifo.watermark.gyro;\n\t\tts = iio_priv(st->indio_gyro);\n\t} else if (indio_dev == st->indio_accel) {\n\t\tsensor = INV_ICM42600_SENSOR_ACCEL;\n\t\twatermark = &st->fifo.watermark.accel;\n\t\tts = iio_priv(st->indio_accel);\n\t} else {\n\t\treturn -EINVAL;\n\t}\n\n\tmutex_lock(&st->lock);\n\n\tret = inv_icm42600_buffer_set_fifo_en(st, st->fifo.en & ~sensor);\n\tif (ret)\n\t\tgoto out_unlock;\n\n\t*watermark = 0;\n\tret = inv_icm42600_buffer_update_watermark(st);\n\tif (ret)\n\t\tgoto out_unlock;\n\n\tconf.mode = INV_ICM42600_SENSOR_MODE_OFF;\n\tif (sensor == INV_ICM42600_SENSOR_GYRO)\n\t\tret = inv_icm42600_set_gyro_conf(st, &conf, &sleep_sensor);\n\telse\n\t\tret = inv_icm42600_set_accel_conf(st, &conf, &sleep_sensor);\n\tif (ret)\n\t\tgoto out_unlock;\n\n\t/* if FIFO is off, turn temperature off */\n\tif (!st->fifo.on)\n\t\tret = inv_icm42600_set_temp_conf(st, false, &sleep_temp);\n\n\tinv_icm42600_timestamp_reset(ts);\n\nout_unlock:\n\tmutex_unlock(&st->lock);\n\n\t/* sleep maximum required time */\n\tif (sleep_sensor > sleep_temp)\n\t\tsleep = sleep_sensor;\n\telse\n\t\tsleep = sleep_temp;\n\tif (sleep)\n\t\tmsleep(sleep);\n\n\tpm_runtime_mark_last_busy(dev);\n\tpm_runtime_put_autosuspend(dev);\n\n\treturn ret;\n}",
        "static void alc850_update_jacks(struct snd_ac97 *ac97)\n{\n\tint shared;\n\tint aux_is_back_surround;\n\t": "static void alc850_update_jacks(struct snd_ac97 *ac97)\n{\n\tint shared;\n\tint aux_is_back_surround;\n\t\n\t/* shared Line-In / Surround Out */\n\tshared = is_shared_surrout(ac97);\n\t/* SURR 1kOhm (bit4), Amp (bit5) */\n\tsnd_ac97_update_bits(ac97, AC97_ALC850_MISC1, (1<<4)|(1<<5),\n\t\t\t     shared ? (1<<5) : (1<<4));\n\t/* LINE-IN = 0, SURROUND = 2 */\n\tsnd_ac97_update_bits(ac97, AC97_ALC850_JACK_SELECT, 7 << 12,\n\t\t\t     shared ? (2<<12) : (0<<12));\n\t/* update shared Mic In / Center/LFE Out */\n\tshared = is_shared_clfeout(ac97);\n\t/* Vref disable (bit12), 1kOhm (bit13) */\n\tsnd_ac97_update_bits(ac97, AC97_ALC850_MISC1, (1<<12)|(1<<13),\n\t\t\t     shared ? (1<<12) : (1<<13));\n\t/* MIC-IN = 1, CENTER-LFE = 5 */\n\tsnd_ac97_update_bits(ac97, AC97_ALC850_JACK_SELECT, 7 << 4,\n\t\t\t     shared ? (5<<4) : (1<<4));\n\n\taux_is_back_surround = alc850_is_aux_back_surround(ac97);\n\t/* Aux is Back Surround */\n\tsnd_ac97_update_bits(ac97, AC97_ALC850_MULTICH, 1 << 10,\n\t\t\t\t aux_is_back_surround ? (1<<10) : (0<<10));\n}",
        "static void ssh_ptl_timeout_reap(struct work_struct *work)\n{\n\tstruct ssh_ptl *ptl = to_ssh_ptl(work, rtx_timeout.reaper.work);\n\tstruct ssh_packet *p, *n;\n\tLIST_HEAD(claimed);": "static void ssh_ptl_timeout_reap(struct work_struct *work)\n{\n\tstruct ssh_ptl *ptl = to_ssh_ptl(work, rtx_timeout.reaper.work);\n\tstruct ssh_packet *p, *n;\n\tLIST_HEAD(claimed);\n\tktime_t now = ktime_get_coarse_boottime();\n\tktime_t timeout = ptl->rtx_timeout.timeout;\n\tktime_t next = KTIME_MAX;\n\tbool resub = false;\n\tint status;\n\n\ttrace_ssam_ptl_timeout_reap(atomic_read(&ptl->pending.count));\n\n\t/*\n\t * Mark reaper as \"not pending\". This is done before checking any\n\t * packets to avoid lost-update type problems.\n\t */\n\tspin_lock(&ptl->rtx_timeout.lock);\n\tptl->rtx_timeout.expires = KTIME_MAX;\n\tspin_unlock(&ptl->rtx_timeout.lock);\n\n\tspin_lock(&ptl->pending.lock);\n\n\tlist_for_each_entry_safe(p, n, &ptl->pending.head, pending_node) {\n\t\tktime_t expires = ssh_packet_get_expiration(p, timeout);\n\n\t\t/*\n\t\t * Check if the timeout hasn't expired yet. Find out next\n\t\t * expiration date to be handled after this run.\n\t\t */\n\t\tif (ktime_after(expires, now)) {\n\t\t\tnext = ktime_before(expires, next) ? expires : next;\n\t\t\tcontinue;\n\t\t}\n\n\t\ttrace_ssam_packet_timeout(p);\n\n\t\tstatus = __ssh_ptl_resubmit(p);\n\n\t\t/*\n\t\t * Re-submission fails if the packet is out of tries, has been\n\t\t * locked, is already queued, or the layer is being shut down.\n\t\t * No need to re-schedule tx-thread in those cases.\n\t\t */\n\t\tif (!status)\n\t\t\tresub = true;\n\n\t\t/* Go to next packet if this packet is not out of tries. */\n\t\tif (status != -ECANCELED)\n\t\t\tcontinue;\n\n\t\t/* No more tries left: Cancel the packet. */\n\n\t\t/*\n\t\t * If someone else has locked the packet already, don't use it\n\t\t * and let the other party complete it.\n\t\t */\n\t\tif (test_and_set_bit(SSH_PACKET_SF_LOCKED_BIT, &p->state))\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * We have now marked the packet as locked. Thus it cannot be\n\t\t * added to the pending list again after we've removed it here.\n\t\t * We can therefore re-use the pending_node of this packet\n\t\t * temporarily.\n\t\t */\n\n\t\tclear_bit(SSH_PACKET_SF_PENDING_BIT, &p->state);\n\n\t\tatomic_dec(&ptl->pending.count);\n\t\tlist_move_tail(&p->pending_node, &claimed);\n\t}\n\n\tspin_unlock(&ptl->pending.lock);\n\n\t/* Cancel and complete the packet. */\n\tlist_for_each_entry_safe(p, n, &claimed, pending_node) {\n\t\tif (!test_and_set_bit(SSH_PACKET_SF_COMPLETED_BIT, &p->state)) {\n\t\t\tssh_ptl_queue_remove(p);\n\t\t\t__ssh_ptl_complete(p, -ETIMEDOUT);\n\t\t}\n\n\t\t/*\n\t\t * Drop the reference we've obtained by removing it from\n\t\t * the pending set.\n\t\t */\n\t\tlist_del(&p->pending_node);\n\t\tssh_packet_put(p);\n\t}\n\n\t/* Ensure that reaper doesn't run again immediately. */\n\tnext = max(next, ktime_add(now, SSH_PTL_PACKET_TIMEOUT_RESOLUTION));\n\tif (next != KTIME_MAX)\n\t\tssh_ptl_timeout_reaper_mod(ptl, now, next);\n\n\tif (resub)\n\t\tssh_ptl_tx_wakeup_packet(ptl);\n}",
        "static void vmap_tags(struct kunit *test)\n{\n\tchar *p_ptr, *v_ptr;\n\tstruct page *p_page, *v_page;\n": "static void vmap_tags(struct kunit *test)\n{\n\tchar *p_ptr, *v_ptr;\n\tstruct page *p_page, *v_page;\n\n\t/*\n\t * This test is specifically crafted for the software tag-based mode,\n\t * the only tag-based mode that poisons vmap mappings.\n\t */\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_SW_TAGS);\n\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_VMALLOC);\n\n\tp_page = alloc_pages(GFP_KERNEL, 1);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, p_page);\n\tp_ptr = page_address(p_page);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, p_ptr);\n\n\tv_ptr = vmap(&p_page, 1, VM_MAP, PAGE_KERNEL);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, v_ptr);\n\n\t/*\n\t * We can't check for out-of-bounds bugs in this nor in the following\n\t * vmalloc tests, as allocations have page granularity and accessing\n\t * the guard page will crash the kernel.\n\t */\n\n\tKUNIT_EXPECT_GE(test, (u8)get_tag(v_ptr), (u8)KASAN_TAG_MIN);\n\tKUNIT_EXPECT_LT(test, (u8)get_tag(v_ptr), (u8)KASAN_TAG_KERNEL);\n\n\t/* Make sure that in-bounds accesses through both pointers work. */\n\t*p_ptr = 0;\n\t*v_ptr = 0;\n\n\t/* Make sure vmalloc_to_page() correctly recovers the page pointer. */\n\tv_page = vmalloc_to_page(v_ptr);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, v_page);\n\tKUNIT_EXPECT_PTR_EQ(test, p_page, v_page);\n\n\tvunmap(v_ptr);\n\tfree_pages((unsigned long)p_ptr, 1);\n}",
        "static void ivc120_muxsel(struct bttv *btv, unsigned int input)\n{\n\t/* Simple maths */\n\tint key = input % 4;\n\tint matrix = input / 4;": "static void ivc120_muxsel(struct bttv *btv, unsigned int input)\n{\n\t/* Simple maths */\n\tint key = input % 4;\n\tint matrix = input / 4;\n\n\tdprintk(\"%d: ivc120_muxsel: Input - %02d | TDA - %02d | In - %02d\\n\",\n\t\tbtv->c.nr, input, matrix, key);\n\n\t/* Handles the input selection on the TDA8540's */\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT3, 0x00,\n\t\t      ((matrix == 3) ? (key | key << 2) : 0x00), 1);\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT4, 0x00,\n\t\t      ((matrix == 0) ? (key | key << 2) : 0x00), 1);\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT5, 0x00,\n\t\t      ((matrix == 1) ? (key | key << 2) : 0x00), 1);\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT6, 0x00,\n\t\t      ((matrix == 2) ? (key | key << 2) : 0x00), 1);\n\n\t/* Handles the output enables on the TDA8540's */\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT3, 0x02,\n\t\t      ((matrix == 3) ? 0x03 : 0x00), 1);  /* 13 - 16 */\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT4, 0x02,\n\t\t      ((matrix == 0) ? 0x03 : 0x00), 1);  /* 1-4 */\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT5, 0x02,\n\t\t      ((matrix == 1) ? 0x03 : 0x00), 1);  /* 5-8 */\n\tbttv_I2CWrite(btv, I2C_TDA8540_ALT6, 0x02,\n\t\t      ((matrix == 2) ? 0x03 : 0x00), 1);  /* 9-12 */\n\n\t/* 878's MUX0 is already selected for input via muxsel values */\n}",
        "static int add_named_array(const char *val, const struct kernel_param *kp)\n{\n\t/*\n\t * val must be \"md_*\" or \"mdNNN\".\n\t * For \"md_*\" we allocate an array with a large free minor number, and": "static int add_named_array(const char *val, const struct kernel_param *kp)\n{\n\t/*\n\t * val must be \"md_*\" or \"mdNNN\".\n\t * For \"md_*\" we allocate an array with a large free minor number, and\n\t * set the name to val.  val must not already be an active name.\n\t * For \"mdNNN\" we allocate an array with the minor number NNN\n\t * which must not already be in use.\n\t */\n\tint len = strlen(val);\n\tchar buf[DISK_NAME_LEN];\n\tunsigned long devnum;\n\n\twhile (len && val[len-1] == '\\n')\n\t\tlen--;\n\tif (len >= DISK_NAME_LEN)\n\t\treturn -E2BIG;\n\tstrscpy(buf, val, len+1);\n\tif (strncmp(buf, \"md_\", 3) == 0)\n\t\treturn md_alloc(0, buf);\n\tif (strncmp(buf, \"md\", 2) == 0 &&\n\t    isdigit(buf[2]) &&\n\t    kstrtoul(buf+2, 10, &devnum) == 0 &&\n\t    devnum <= MINORMASK)\n\t\treturn md_alloc(MKDEV(MD_MAJOR, devnum), NULL);\n\n\treturn -EINVAL;\n}",
        "static void help(char *name, struct test_args *targs)\n{\n\tint ctr;\n\n\tpr_info(\"usage: %s [-h] [-v] [-d] [-s slots] [-f first_test] [-e last_test] [-l test_length] [-r run_count]\\n\",": "static void help(char *name, struct test_args *targs)\n{\n\tint ctr;\n\n\tpr_info(\"usage: %s [-h] [-v] [-d] [-s slots] [-f first_test] [-e last_test] [-l test_length] [-r run_count]\\n\",\n\t\tname);\n\tpr_info(\" -h: print this help screen.\\n\");\n\tpr_info(\" -v: enable verbose mode (not for benchmarking).\\n\");\n\tpr_info(\" -d: enable extra debug checks.\\n\");\n\tpr_info(\" -s: specify memslot count cap (-1 means no cap; currently: %i)\\n\",\n\t\ttargs->nslots);\n\tpr_info(\" -f: specify the first test to run (currently: %i; max %zu)\\n\",\n\t\ttargs->tfirst, NTESTS - 1);\n\tpr_info(\" -e: specify the last test to run (currently: %i; max %zu)\\n\",\n\t\ttargs->tlast, NTESTS - 1);\n\tpr_info(\" -l: specify the test length in seconds (currently: %i)\\n\",\n\t\ttargs->seconds);\n\tpr_info(\" -r: specify the number of runs per test (currently: %i)\\n\",\n\t\ttargs->runs);\n\n\tpr_info(\"\\nAvailable tests:\\n\");\n\tfor (ctr = 0; ctr < NTESTS; ctr++)\n\t\tpr_info(\"%d: %s\\n\", ctr, tests[ctr].name);\n}",
        "static int otx2_init_hw_resources(struct otx2_nic *pf)\n{\n\tstruct nix_lf_free_req *free_req;\n\tstruct mbox *mbox = &pf->mbox;\n\tstruct otx2_hw *hw = &pf->hw;": "static int otx2_init_hw_resources(struct otx2_nic *pf)\n{\n\tstruct nix_lf_free_req *free_req;\n\tstruct mbox *mbox = &pf->mbox;\n\tstruct otx2_hw *hw = &pf->hw;\n\tstruct msg_req *req;\n\tint err = 0, lvl;\n\n\t/* Set required NPA LF's pool counts\n\t * Auras and Pools are used in a 1:1 mapping,\n\t * so, aura count = pool count.\n\t */\n\thw->rqpool_cnt = hw->rx_queues;\n\thw->sqpool_cnt = hw->tot_tx_queues;\n\thw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;\n\n\t/* Maximum hardware supported transmit length */\n\tpf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN;\n\n\tpf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu);\n\n\tmutex_lock(&mbox->lock);\n\t/* NPA init */\n\terr = otx2_config_npa(pf);\n\tif (err)\n\t\tgoto exit;\n\n\t/* NIX init */\n\terr = otx2_config_nix(pf);\n\tif (err)\n\t\tgoto err_free_npa_lf;\n\n\t/* Enable backpressure */\n\totx2_nix_config_bp(pf, true);\n\n\t/* Init Auras and pools used by NIX RQ, for free buffer ptrs */\n\terr = otx2_rq_aura_pool_init(pf);\n\tif (err) {\n\t\tmutex_unlock(&mbox->lock);\n\t\tgoto err_free_nix_lf;\n\t}\n\t/* Init Auras and pools used by NIX SQ, for queueing SQEs */\n\terr = otx2_sq_aura_pool_init(pf);\n\tif (err) {\n\t\tmutex_unlock(&mbox->lock);\n\t\tgoto err_free_rq_ptrs;\n\t}\n\n\terr = otx2_txsch_alloc(pf);\n\tif (err) {\n\t\tmutex_unlock(&mbox->lock);\n\t\tgoto err_free_sq_ptrs;\n\t}\n\n\terr = otx2_config_nix_queues(pf);\n\tif (err) {\n\t\tmutex_unlock(&mbox->lock);\n\t\tgoto err_free_txsch;\n\t}\n\tfor (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {\n\t\terr = otx2_txschq_config(pf, lvl);\n\t\tif (err) {\n\t\t\tmutex_unlock(&mbox->lock);\n\t\t\tgoto err_free_nix_queues;\n\t\t}\n\t}\n\tmutex_unlock(&mbox->lock);\n\treturn err;\n\nerr_free_nix_queues:\n\totx2_free_sq_res(pf);\n\totx2_free_cq_res(pf);\n\totx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);\nerr_free_txsch:\n\tif (otx2_txschq_stop(pf))\n\t\tdev_err(pf->dev, \"%s failed to stop TX schedulers\\n\", __func__);\nerr_free_sq_ptrs:\n\totx2_sq_free_sqbs(pf);\nerr_free_rq_ptrs:\n\totx2_free_aura_ptr(pf, AURA_NIX_RQ);\n\totx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);\n\totx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);\n\totx2_aura_pool_free(pf);\nerr_free_nix_lf:\n\tmutex_lock(&mbox->lock);\n\tfree_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);\n\tif (free_req) {\n\t\tfree_req->flags = NIX_LF_DISABLE_FLOWS;\n\t\tif (otx2_sync_mbox_msg(mbox))\n\t\t\tdev_err(pf->dev, \"%s failed to free nixlf\\n\", __func__);\n\t}\nerr_free_npa_lf:\n\t/* Reset NPA LF */\n\treq = otx2_mbox_alloc_msg_npa_lf_free(mbox);\n\tif (req) {\n\t\tif (otx2_sync_mbox_msg(mbox))\n\t\t\tdev_err(pf->dev, \"%s failed to free npalf\\n\", __func__);\n\t}\nexit:\n\tmutex_unlock(&mbox->lock);\n\treturn err;\n}",
        "static void snd_hdsp_initialize_channels(struct hdsp *hdsp)\n{\n\tint status, aebi_channels, aebo_channels, i;\n\n\tswitch (hdsp->io_type) {": "static void snd_hdsp_initialize_channels(struct hdsp *hdsp)\n{\n\tint status, aebi_channels, aebo_channels, i;\n\n\tswitch (hdsp->io_type) {\n\tcase Digiface:\n\t\thdsp->card_name = \"RME Hammerfall DSP + Digiface\";\n\t\thdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;\n\t\thdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;\n\t\tbreak;\n\n\tcase H9652:\n\t\thdsp->card_name = \"RME Hammerfall HDSP 9652\";\n\t\thdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;\n\t\thdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;\n\t\tbreak;\n\n\tcase H9632:\n\t\tstatus = hdsp_read(hdsp, HDSP_statusRegister);\n\t\t/* HDSP_AEBx bits are low when AEB are connected */\n\t\taebi_channels = (status & HDSP_AEBI) ? 0 : 4;\n\t\taebo_channels = (status & HDSP_AEBO) ? 0 : 4;\n\t\thdsp->card_name = \"RME Hammerfall HDSP 9632\";\n\t\thdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;\n\t\thdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;\n\t\thdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;\n\t\thdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;\n\t\thdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;\n\t\thdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;\n\t\t/* Disable loopback of output channels, as the set function\n\t\t * only sets on a change we fake all bits (channels) as enabled.\n\t\t */\n\t\thdsp->io_loopback = 0xffffffff;\n\t\tfor (i = 0; i < hdsp->max_channels; ++i)\n\t\t\thdsp_loopback_set(hdsp, i, false);\n\t\tbreak;\n\n\tcase Multiface:\n\t\thdsp->card_name = \"RME Hammerfall DSP + Multiface\";\n\t\thdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;\n\t\thdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;\n\t\tbreak;\n\n\tcase RPM:\n\t\thdsp->card_name = \"RME Hammerfall DSP + RPM\";\n\t\thdsp->ss_in_channels = RPM_CHANNELS-1;\n\t\thdsp->ss_out_channels = RPM_CHANNELS;\n\t\thdsp->ds_in_channels = RPM_CHANNELS-1;\n\t\thdsp->ds_out_channels = RPM_CHANNELS;\n\t\tbreak;\n\n\tdefault:\n \t\t/* should never get here */\n\t\tbreak;\n\t}\n}",
        "static void rxrpc_input_data(struct rxrpc_call *call, struct sk_buff *skb)\n{\n\tstruct rxrpc_skb_priv *sp = rxrpc_skb(skb);\n\tenum rxrpc_call_state state;\n\tunsigned int j, nr_subpackets, nr_unacked = 0;": "static void rxrpc_input_data(struct rxrpc_call *call, struct sk_buff *skb)\n{\n\tstruct rxrpc_skb_priv *sp = rxrpc_skb(skb);\n\tenum rxrpc_call_state state;\n\tunsigned int j, nr_subpackets, nr_unacked = 0;\n\trxrpc_serial_t serial = sp->hdr.serial, ack_serial = serial;\n\trxrpc_seq_t seq0 = sp->hdr.seq, hard_ack;\n\tbool immediate_ack = false, jumbo_bad = false;\n\tu8 ack = 0;\n\n\t_enter(\"{%u,%u},{%u,%u}\",\n\t       call->rx_hard_ack, call->rx_top, skb->len, seq0);\n\n\t_proto(\"Rx DATA %%%u { #%u f=%02x n=%u }\",\n\t       sp->hdr.serial, seq0, sp->hdr.flags, sp->nr_subpackets);\n\n\tstate = READ_ONCE(call->state);\n\tif (state >= RXRPC_CALL_COMPLETE) {\n\t\trxrpc_free_skb(skb, rxrpc_skb_freed);\n\t\treturn;\n\t}\n\n\tif (state == RXRPC_CALL_SERVER_RECV_REQUEST) {\n\t\tunsigned long timo = READ_ONCE(call->next_req_timo);\n\t\tunsigned long now, expect_req_by;\n\n\t\tif (timo) {\n\t\t\tnow = jiffies;\n\t\t\texpect_req_by = now + timo;\n\t\t\tWRITE_ONCE(call->expect_req_by, expect_req_by);\n\t\t\trxrpc_reduce_call_timer(call, expect_req_by, now,\n\t\t\t\t\t\trxrpc_timer_set_for_idle);\n\t\t}\n\t}\n\n\tspin_lock(&call->input_lock);\n\n\t/* Received data implicitly ACKs all of the request packets we sent\n\t * when we're acting as a client.\n\t */\n\tif ((state == RXRPC_CALL_CLIENT_SEND_REQUEST ||\n\t     state == RXRPC_CALL_CLIENT_AWAIT_REPLY) &&\n\t    !rxrpc_receiving_reply(call))\n\t\tgoto unlock;\n\n\thard_ack = READ_ONCE(call->rx_hard_ack);\n\n\tnr_subpackets = sp->nr_subpackets;\n\tif (nr_subpackets > 1) {\n\t\tif (call->nr_jumbo_bad > 3) {\n\t\t\tack = RXRPC_ACK_NOSPACE;\n\t\t\tack_serial = serial;\n\t\t\tgoto ack;\n\t\t}\n\t}\n\n\tfor (j = 0; j < nr_subpackets; j++) {\n\t\trxrpc_serial_t serial = sp->hdr.serial + j;\n\t\trxrpc_seq_t seq = seq0 + j;\n\t\tunsigned int ix = seq & RXRPC_RXTX_BUFF_MASK;\n\t\tbool terminal = (j == nr_subpackets - 1);\n\t\tbool last = terminal && (sp->rx_flags & RXRPC_SKB_INCL_LAST);\n\t\tu8 flags, annotation = j;\n\n\t\t_proto(\"Rx DATA+%u %%%u { #%x t=%u l=%u }\",\n\t\t     j, serial, seq, terminal, last);\n\n\t\tif (last) {\n\t\t\tif (test_bit(RXRPC_CALL_RX_LAST, &call->flags) &&\n\t\t\t    seq != call->rx_top) {\n\t\t\t\trxrpc_proto_abort(\"LSN\", call, seq);\n\t\t\t\tgoto unlock;\n\t\t\t}\n\t\t} else {\n\t\t\tif (test_bit(RXRPC_CALL_RX_LAST, &call->flags) &&\n\t\t\t    after_eq(seq, call->rx_top)) {\n\t\t\t\trxrpc_proto_abort(\"LSA\", call, seq);\n\t\t\t\tgoto unlock;\n\t\t\t}\n\t\t}\n\n\t\tflags = 0;\n\t\tif (last)\n\t\t\tflags |= RXRPC_LAST_PACKET;\n\t\tif (!terminal)\n\t\t\tflags |= RXRPC_JUMBO_PACKET;\n\t\tif (test_bit(j, sp->rx_req_ack))\n\t\t\tflags |= RXRPC_REQUEST_ACK;\n\t\ttrace_rxrpc_rx_data(call->debug_id, seq, serial, flags, annotation);\n\n\t\tif (before_eq(seq, hard_ack)) {\n\t\t\tack = RXRPC_ACK_DUPLICATE;\n\t\t\tack_serial = serial;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (call->rxtx_buffer[ix]) {\n\t\t\trxrpc_input_dup_data(call, seq, nr_subpackets > 1,\n\t\t\t\t\t     &jumbo_bad);\n\t\t\tif (ack != RXRPC_ACK_DUPLICATE) {\n\t\t\t\tack = RXRPC_ACK_DUPLICATE;\n\t\t\t\tack_serial = serial;\n\t\t\t}\n\t\t\timmediate_ack = true;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (after(seq, hard_ack + call->rx_winsize)) {\n\t\t\tack = RXRPC_ACK_EXCEEDS_WINDOW;\n\t\t\tack_serial = serial;\n\t\t\tif (flags & RXRPC_JUMBO_PACKET) {\n\t\t\t\tif (!jumbo_bad) {\n\t\t\t\t\tcall->nr_jumbo_bad++;\n\t\t\t\t\tjumbo_bad = true;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tgoto ack;\n\t\t}\n\n\t\tif (flags & RXRPC_REQUEST_ACK && !ack) {\n\t\t\tack = RXRPC_ACK_REQUESTED;\n\t\t\tack_serial = serial;\n\t\t}\n\n\t\tif (after(seq0, call->ackr_highest_seq))\n\t\t\tcall->ackr_highest_seq = seq0;\n\n\t\t/* Queue the packet.  We use a couple of memory barriers here as need\n\t\t * to make sure that rx_top is perceived to be set after the buffer\n\t\t * pointer and that the buffer pointer is set after the annotation and\n\t\t * the skb data.\n\t\t *\n\t\t * Barriers against rxrpc_recvmsg_data() and rxrpc_rotate_rx_window()\n\t\t * and also rxrpc_fill_out_ack().\n\t\t */\n\t\tif (!terminal)\n\t\t\trxrpc_get_skb(skb, rxrpc_skb_got);\n\t\tcall->rxtx_annotations[ix] = annotation;\n\t\tsmp_wmb();\n\t\tcall->rxtx_buffer[ix] = skb;\n\t\tif (after(seq, call->rx_top)) {\n\t\t\tsmp_store_release(&call->rx_top, seq);\n\t\t} else if (before(seq, call->rx_top)) {\n\t\t\t/* Send an immediate ACK if we fill in a hole */\n\t\t\tif (!ack) {\n\t\t\t\tack = RXRPC_ACK_DELAY;\n\t\t\t\tack_serial = serial;\n\t\t\t}\n\t\t\timmediate_ack = true;\n\t\t}\n\n\t\tif (terminal) {\n\t\t\t/* From this point on, we're not allowed to touch the\n\t\t\t * packet any longer as its ref now belongs to the Rx\n\t\t\t * ring.\n\t\t\t */\n\t\t\tskb = NULL;\n\t\t\tsp = NULL;\n\t\t}\n\n\t\tnr_unacked++;\n\n\t\tif (last) {\n\t\t\tset_bit(RXRPC_CALL_RX_LAST, &call->flags);\n\t\t\tif (!ack) {\n\t\t\t\tack = RXRPC_ACK_DELAY;\n\t\t\t\tack_serial = serial;\n\t\t\t}\n\t\t\ttrace_rxrpc_receive(call, rxrpc_receive_queue_last, serial, seq);\n\t\t} else {\n\t\t\ttrace_rxrpc_receive(call, rxrpc_receive_queue, serial, seq);\n\t\t}\n\n\t\tif (after_eq(seq, call->rx_expect_next)) {\n\t\t\tif (after(seq, call->rx_expect_next)) {\n\t\t\t\t_net(\"OOS %u > %u\", seq, call->rx_expect_next);\n\t\t\t\tack = RXRPC_ACK_OUT_OF_SEQUENCE;\n\t\t\t\tack_serial = serial;\n\t\t\t}\n\t\t\tcall->rx_expect_next = seq + 1;\n\t\t}\n\t\tif (!ack)\n\t\t\tack_serial = serial;\n\t}\n\nack:\n\tif (atomic_add_return(nr_unacked, &call->ackr_nr_unacked) > 2 && !ack)\n\t\tack = RXRPC_ACK_IDLE;\n\n\tif (ack)\n\t\trxrpc_propose_ACK(call, ack, ack_serial,\n\t\t\t\t  immediate_ack, true,\n\t\t\t\t  rxrpc_propose_ack_input_data);\n\telse\n\t\trxrpc_propose_ACK(call, RXRPC_ACK_DELAY, serial,\n\t\t\t\t  false, true,\n\t\t\t\t  rxrpc_propose_ack_input_data);\n\n\ttrace_rxrpc_notify_socket(call->debug_id, serial);\n\trxrpc_notify_socket(call);\n\nunlock:\n\tspin_unlock(&call->input_lock);\n\trxrpc_free_skb(skb, rxrpc_skb_freed);\n\t_leave(\" [queued]\");\n}",
        "static void isc_wb_update(struct isc_ctrls *ctrls)\n{\n\tstruct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);\n\tu32 *hist_count = &ctrls->hist_count[0];\n\tu32 c, offset[4];": "static void isc_wb_update(struct isc_ctrls *ctrls)\n{\n\tstruct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);\n\tu32 *hist_count = &ctrls->hist_count[0];\n\tu32 c, offset[4];\n\tu64 avg = 0;\n\t/* We compute two gains, stretch gain and grey world gain */\n\tu32 s_gain[4], gw_gain[4];\n\n\t/*\n\t * According to Grey World, we need to set gains for R/B to normalize\n\t * them towards the green channel.\n\t * Thus we want to keep Green as fixed and adjust only Red/Blue\n\t * Compute the average of the both green channels first\n\t */\n\tavg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +\n\t\t(u64)hist_count[ISC_HIS_CFG_MODE_GB];\n\tavg >>= 1;\n\n\tv4l2_dbg(1, debug, &isc->v4l2_dev,\n\t\t \"isc wb: green components average %llu\\n\", avg);\n\n\t/* Green histogram is null, nothing to do */\n\tif (!avg)\n\t\treturn;\n\n\tfor (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {\n\t\t/*\n\t\t * the color offset is the minimum value of the histogram.\n\t\t * we stretch this color to the full range by substracting\n\t\t * this value from the color component.\n\t\t */\n\t\toffset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];\n\t\t/*\n\t\t * The offset is always at least 1. If the offset is 1, we do\n\t\t * not need to adjust it, so our result must be zero.\n\t\t * the offset is computed in a histogram on 9 bits (0..512)\n\t\t * but the offset in register is based on\n\t\t * 12 bits pipeline (0..4096).\n\t\t * we need to shift with the 3 bits that the histogram is\n\t\t * ignoring\n\t\t */\n\t\tctrls->offset[c] = (offset[c] - 1) << 3;\n\n\t\t/*\n\t\t * the offset is then taken and converted to 2's complements,\n\t\t * and must be negative, as we subtract this value from the\n\t\t * color components\n\t\t */\n\t\tctrls->offset[c] = -ctrls->offset[c];\n\n\t\t/*\n\t\t * the stretch gain is the total number of histogram bins\n\t\t * divided by the actual range of color component (Max - Min)\n\t\t * If we compute gain like this, the actual color component\n\t\t * will be stretched to the full histogram.\n\t\t * We need to shift 9 bits for precision, we have 9 bits for\n\t\t * decimals\n\t\t */\n\t\ts_gain[c] = (HIST_ENTRIES << 9) /\n\t\t\t(ctrls->hist_minmax[c][HIST_MAX_INDEX] -\n\t\t\tctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);\n\n\t\t/*\n\t\t * Now we have to compute the gain w.r.t. the average.\n\t\t * Add/lose gain to the component towards the average.\n\t\t * If it happens that the component is zero, use the\n\t\t * fixed point value : 1.0 gain.\n\t\t */\n\t\tif (hist_count[c])\n\t\t\tgw_gain[c] = div_u64(avg << 9, hist_count[c]);\n\t\telse\n\t\t\tgw_gain[c] = 1 << 9;\n\n\t\tv4l2_dbg(1, debug, &isc->v4l2_dev,\n\t\t\t \"isc wb: component %d, s_gain %u, gw_gain %u\\n\",\n\t\t\t c, s_gain[c], gw_gain[c]);\n\t\t/* multiply both gains and adjust for decimals */\n\t\tctrls->gain[c] = s_gain[c] * gw_gain[c];\n\t\tctrls->gain[c] >>= 9;\n\n\t\t/* make sure we are not out of range */\n\t\tctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));\n\n\t\tv4l2_dbg(1, debug, &isc->v4l2_dev,\n\t\t\t \"isc wb: component %d, final gain %u\\n\",\n\t\t\t c, ctrls->gain[c]);\n\t}\n}",
        "static int fw_cfg_sysfs_probe(struct platform_device *pdev)\n{\n\tint err;\n\t__le32 rev;\n": "static int fw_cfg_sysfs_probe(struct platform_device *pdev)\n{\n\tint err;\n\t__le32 rev;\n\n\t/* NOTE: If we supported multiple fw_cfg devices, we'd first create\n\t * a subdirectory named after e.g. pdev->id, then hang per-device\n\t * by_key (and by_name) subdirectories underneath it. However, only\n\t * one fw_cfg device exist system-wide, so if one was already found\n\t * earlier, we might as well stop here.\n\t */\n\tif (fw_cfg_sel_ko)\n\t\treturn -EBUSY;\n\n\t/* create by_key and by_name subdirs of /sys/firmware/qemu_fw_cfg/ */\n\terr = -ENOMEM;\n\tfw_cfg_sel_ko = kobject_create_and_add(\"by_key\", fw_cfg_top_ko);\n\tif (!fw_cfg_sel_ko)\n\t\tgoto err_sel;\n\tfw_cfg_fname_kset = kset_create_and_add(\"by_name\", NULL, fw_cfg_top_ko);\n\tif (!fw_cfg_fname_kset)\n\t\tgoto err_name;\n\n\t/* initialize fw_cfg device i/o from platform data */\n\terr = fw_cfg_do_platform_probe(pdev);\n\tif (err)\n\t\tgoto err_probe;\n\n\t/* get revision number, add matching top-level attribute */\n\terr = fw_cfg_read_blob(FW_CFG_ID, &rev, 0, sizeof(rev));\n\tif (err < 0)\n\t\tgoto err_probe;\n\n\tfw_cfg_rev = le32_to_cpu(rev);\n\terr = sysfs_create_file(fw_cfg_top_ko, &fw_cfg_rev_attr.attr);\n\tif (err)\n\t\tgoto err_rev;\n\n\t/* process fw_cfg file directory entry, registering each file */\n\terr = fw_cfg_register_dir_entries();\n\tif (err)\n\t\tgoto err_dir;\n\n\t/* success */\n\tpr_debug(\"fw_cfg: loaded.\\n\");\n\treturn 0;\n\nerr_dir:\n\tfw_cfg_sysfs_cache_cleanup();\n\tsysfs_remove_file(fw_cfg_top_ko, &fw_cfg_rev_attr.attr);\nerr_rev:\n\tfw_cfg_io_cleanup();\nerr_probe:\n\tfw_cfg_kset_unregister_recursive(fw_cfg_fname_kset);\nerr_name:\n\tfw_cfg_kobj_cleanup(fw_cfg_sel_ko);\nerr_sel:\n\treturn err;\n}",
        "static int parse_output_paths(struct hda_codec *codec)\n{\n\tstruct hda_gen_spec *spec = codec->spec;\n\tstruct auto_pin_cfg *cfg = &spec->autocfg;\n\tstruct auto_pin_cfg *best_cfg;": "static int parse_output_paths(struct hda_codec *codec)\n{\n\tstruct hda_gen_spec *spec = codec->spec;\n\tstruct auto_pin_cfg *cfg = &spec->autocfg;\n\tstruct auto_pin_cfg *best_cfg;\n\tunsigned int val;\n\tint best_badness = INT_MAX;\n\tint badness;\n\tbool fill_hardwired = true, fill_mio_first = true;\n\tbool best_wired = true, best_mio = true;\n\tbool hp_spk_swapped = false;\n\n\tbest_cfg = kmalloc(sizeof(*best_cfg), GFP_KERNEL);\n\tif (!best_cfg)\n\t\treturn -ENOMEM;\n\t*best_cfg = *cfg;\n\n\tfor (;;) {\n\t\tbadness = fill_and_eval_dacs(codec, fill_hardwired,\n\t\t\t\t\t     fill_mio_first);\n\t\tif (badness < 0) {\n\t\t\tkfree(best_cfg);\n\t\t\treturn badness;\n\t\t}\n\t\tdebug_badness(\"==> lo_type=%d, wired=%d, mio=%d, badness=0x%x\\n\",\n\t\t\t      cfg->line_out_type, fill_hardwired, fill_mio_first,\n\t\t\t      badness);\n\t\tdebug_show_configs(codec, cfg);\n\t\tif (badness < best_badness) {\n\t\t\tbest_badness = badness;\n\t\t\t*best_cfg = *cfg;\n\t\t\tbest_wired = fill_hardwired;\n\t\t\tbest_mio = fill_mio_first;\n\t\t}\n\t\tif (!badness)\n\t\t\tbreak;\n\t\tfill_mio_first = !fill_mio_first;\n\t\tif (!fill_mio_first)\n\t\t\tcontinue;\n\t\tfill_hardwired = !fill_hardwired;\n\t\tif (!fill_hardwired)\n\t\t\tcontinue;\n\t\tif (hp_spk_swapped)\n\t\t\tbreak;\n\t\thp_spk_swapped = true;\n\t\tif (cfg->speaker_outs > 0 &&\n\t\t    cfg->line_out_type == AUTO_PIN_HP_OUT) {\n\t\t\tcfg->hp_outs = cfg->line_outs;\n\t\t\tmemcpy(cfg->hp_pins, cfg->line_out_pins,\n\t\t\t       sizeof(cfg->hp_pins));\n\t\t\tcfg->line_outs = cfg->speaker_outs;\n\t\t\tmemcpy(cfg->line_out_pins, cfg->speaker_pins,\n\t\t\t       sizeof(cfg->speaker_pins));\n\t\t\tcfg->speaker_outs = 0;\n\t\t\tmemset(cfg->speaker_pins, 0, sizeof(cfg->speaker_pins));\n\t\t\tcfg->line_out_type = AUTO_PIN_SPEAKER_OUT;\n\t\t\tfill_hardwired = true;\n\t\t\tcontinue;\n\t\t}\n\t\tif (cfg->hp_outs > 0 &&\n\t\t    cfg->line_out_type == AUTO_PIN_SPEAKER_OUT) {\n\t\t\tcfg->speaker_outs = cfg->line_outs;\n\t\t\tmemcpy(cfg->speaker_pins, cfg->line_out_pins,\n\t\t\t       sizeof(cfg->speaker_pins));\n\t\t\tcfg->line_outs = cfg->hp_outs;\n\t\t\tmemcpy(cfg->line_out_pins, cfg->hp_pins,\n\t\t\t       sizeof(cfg->hp_pins));\n\t\t\tcfg->hp_outs = 0;\n\t\t\tmemset(cfg->hp_pins, 0, sizeof(cfg->hp_pins));\n\t\t\tcfg->line_out_type = AUTO_PIN_HP_OUT;\n\t\t\tfill_hardwired = true;\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (badness) {\n\t\tdebug_badness(\"==> restoring best_cfg\\n\");\n\t\t*cfg = *best_cfg;\n\t\tfill_and_eval_dacs(codec, best_wired, best_mio);\n\t}\n\tdebug_badness(\"==> Best config: lo_type=%d, wired=%d, mio=%d\\n\",\n\t\t      cfg->line_out_type, best_wired, best_mio);\n\tdebug_show_configs(codec, cfg);\n\n\tif (cfg->line_out_pins[0]) {\n\t\tstruct nid_path *path;\n\t\tpath = snd_hda_get_path_from_idx(codec, spec->out_paths[0]);\n\t\tif (path)\n\t\t\tspec->vmaster_nid = look_for_out_vol_nid(codec, path);\n\t\tif (spec->vmaster_nid) {\n\t\t\tsnd_hda_set_vmaster_tlv(codec, spec->vmaster_nid,\n\t\t\t\t\t\tHDA_OUTPUT, spec->vmaster_tlv);\n\t\t\tif (spec->dac_min_mute)\n\t\t\t\tspec->vmaster_tlv[SNDRV_CTL_TLVO_DB_SCALE_MUTE_AND_STEP] |= TLV_DB_SCALE_MUTE;\n\t\t}\n\t}\n\n\t/* set initial pinctl targets */\n\tif (spec->prefer_hp_amp || cfg->line_out_type == AUTO_PIN_HP_OUT)\n\t\tval = PIN_HP;\n\telse\n\t\tval = PIN_OUT;\n\tset_pin_targets(codec, cfg->line_outs, cfg->line_out_pins, val);\n\tif (cfg->line_out_type != AUTO_PIN_HP_OUT)\n\t\tset_pin_targets(codec, cfg->hp_outs, cfg->hp_pins, PIN_HP);\n\tif (cfg->line_out_type != AUTO_PIN_SPEAKER_OUT) {\n\t\tval = spec->prefer_hp_amp ? PIN_HP : PIN_OUT;\n\t\tset_pin_targets(codec, cfg->speaker_outs,\n\t\t\t\tcfg->speaker_pins, val);\n\t}\n\n\t/* clear indep_hp flag if not available */\n\tif (spec->indep_hp && !indep_hp_possible(codec))\n\t\tspec->indep_hp = 0;\n\n\tkfree(best_cfg);\n\treturn 0;\n}",
        "static void nv_tx_timeout(struct net_device *dev, unsigned int txqueue)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 status;": "static void nv_tx_timeout(struct net_device *dev, unsigned int txqueue)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 status;\n\tunion ring_type put_tx;\n\tint saved_tx_limit;\n\n\tif (np->msi_flags & NV_MSI_X_ENABLED)\n\t\tstatus = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;\n\telse\n\t\tstatus = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;\n\n\tnetdev_warn(dev, \"Got tx_timeout. irq status: %08x\\n\", status);\n\n\tif (unlikely(debug_tx_timeout)) {\n\t\tint i;\n\n\t\tnetdev_info(dev, \"Ring at %lx\\n\", (unsigned long)np->ring_addr);\n\t\tnetdev_info(dev, \"Dumping tx registers\\n\");\n\t\tfor (i = 0; i <= np->register_size; i += 32) {\n\t\t\tnetdev_info(dev,\n\t\t\t\t    \"%3x: %08x %08x %08x %08x \"\n\t\t\t\t    \"%08x %08x %08x %08x\\n\",\n\t\t\t\t    i,\n\t\t\t\t    readl(base + i + 0), readl(base + i + 4),\n\t\t\t\t    readl(base + i + 8), readl(base + i + 12),\n\t\t\t\t    readl(base + i + 16), readl(base + i + 20),\n\t\t\t\t    readl(base + i + 24), readl(base + i + 28));\n\t\t}\n\t\tnetdev_info(dev, \"Dumping tx ring\\n\");\n\t\tfor (i = 0; i < np->tx_ring_size; i += 4) {\n\t\t\tif (!nv_optimized(np)) {\n\t\t\t\tnetdev_info(dev,\n\t\t\t\t\t    \"%03x: %08x %08x // %08x %08x \"\n\t\t\t\t\t    \"// %08x %08x // %08x %08x\\n\",\n\t\t\t\t\t    i,\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i].buf),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i].flaglen),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i+1].buf),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i+1].flaglen),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i+2].buf),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i+2].flaglen),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i+3].buf),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.orig[i+3].flaglen));\n\t\t\t} else {\n\t\t\t\tnetdev_info(dev,\n\t\t\t\t\t    \"%03x: %08x %08x %08x \"\n\t\t\t\t\t    \"// %08x %08x %08x \"\n\t\t\t\t\t    \"// %08x %08x %08x \"\n\t\t\t\t\t    \"// %08x %08x %08x\\n\",\n\t\t\t\t\t    i,\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i].bufhigh),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i].buflow),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i].flaglen),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+1].buflow),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+1].flaglen),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+2].buflow),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+2].flaglen),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+3].buflow),\n\t\t\t\t\t    le32_to_cpu(np->tx_ring.ex[i+3].flaglen));\n\t\t\t}\n\t\t}\n\t}\n\n\tspin_lock_irq(&np->lock);\n\n\t/* 1) stop tx engine */\n\tnv_stop_tx(dev);\n\n\t/* 2) complete any outstanding tx and do not give HW any limited tx pkts */\n\tsaved_tx_limit = np->tx_limit;\n\tnp->tx_limit = 0; /* prevent giving HW any limited pkts */\n\tnp->tx_stop = 0;  /* prevent waking tx queue */\n\tif (!nv_optimized(np))\n\t\tnv_tx_done(dev, np->tx_ring_size);\n\telse\n\t\tnv_tx_done_optimized(dev, np->tx_ring_size);\n\n\t/* save current HW position */\n\tif (np->tx_change_owner)\n\t\tput_tx.ex = np->tx_change_owner->first_tx_desc;\n\telse\n\t\tput_tx = np->put_tx;\n\n\t/* 3) clear all tx state */\n\tnv_drain_tx(dev);\n\tnv_init_tx(dev);\n\n\t/* 4) restore state to current HW position */\n\tnp->get_tx = np->put_tx = put_tx;\n\tnp->tx_limit = saved_tx_limit;\n\n\t/* 5) restart tx engine */\n\tnv_start_tx(dev);\n\tnetif_wake_queue(dev);\n\tspin_unlock_irq(&np->lock);\n}",
        "static unsigned int bm_find(struct ts_config *conf, struct ts_state *state)\n{\n\tstruct ts_bm *bm = ts_config_priv(conf);\n\tunsigned int i, text_len, consumed = state->offset;\n\tconst u8 *text;": "static unsigned int bm_find(struct ts_config *conf, struct ts_state *state)\n{\n\tstruct ts_bm *bm = ts_config_priv(conf);\n\tunsigned int i, text_len, consumed = state->offset;\n\tconst u8 *text;\n\tint shift = bm->patlen - 1, bs;\n\tconst u8 icase = conf->flags & TS_IGNORECASE;\n\n\tfor (;;) {\n\t\ttext_len = conf->get_next_block(consumed, &text, conf, state);\n\n\t\tif (unlikely(text_len == 0))\n\t\t\tbreak;\n\n\t\twhile (shift < text_len) {\n\t\t\tDEBUGP(\"Searching in position %d (%c)\\n\", \n\t\t\t\tshift, text[shift]);\n\t\t\tfor (i = 0; i < bm->patlen; i++) \n\t\t\t\tif ((icase ? toupper(text[shift-i])\n\t\t\t\t    : text[shift-i])\n\t\t\t\t\t!= bm->pattern[bm->patlen-1-i])\n\t\t\t\t     goto next;\n\n\t\t\t/* London calling... */\n\t\t\tDEBUGP(\"found!\\n\");\n\t\t\treturn consumed += (shift-(bm->patlen-1));\n\nnext:\t\t\tbs = bm->bad_shift[text[shift-i]];\n\n\t\t\t/* Now jumping to... */\n\t\t\tshift = max_t(int, shift-i+bs, shift+bm->good_shift[i]);\n\t\t}\n\t\tconsumed += text_len;\n\t}\n\n\treturn UINT_MAX;\n}",
        "static int send_hole(struct send_ctx *sctx, u64 end)\n{\n\tstruct fs_path *p = NULL;\n\tu64 read_size = max_send_read_size(sctx);\n\tu64 offset = sctx->cur_inode_last_extent;": "static int send_hole(struct send_ctx *sctx, u64 end)\n{\n\tstruct fs_path *p = NULL;\n\tu64 read_size = max_send_read_size(sctx);\n\tu64 offset = sctx->cur_inode_last_extent;\n\tint ret = 0;\n\n\t/*\n\t * A hole that starts at EOF or beyond it. Since we do not yet support\n\t * fallocate (for extent preallocation and hole punching), sending a\n\t * write of zeroes starting at EOF or beyond would later require issuing\n\t * a truncate operation which would undo the write and achieve nothing.\n\t */\n\tif (offset >= sctx->cur_inode_size)\n\t\treturn 0;\n\n\t/*\n\t * Don't go beyond the inode's i_size due to prealloc extents that start\n\t * after the i_size.\n\t */\n\tend = min_t(u64, end, sctx->cur_inode_size);\n\n\tif (sctx->flags & BTRFS_SEND_FLAG_NO_FILE_DATA)\n\t\treturn send_update_extent(sctx, offset, end - offset);\n\n\tp = fs_path_alloc();\n\tif (!p)\n\t\treturn -ENOMEM;\n\tret = get_cur_path(sctx, sctx->cur_ino, sctx->cur_inode_gen, p);\n\tif (ret < 0)\n\t\tgoto tlv_put_failure;\n\twhile (offset < end) {\n\t\tu64 len = min(end - offset, read_size);\n\n\t\tret = begin_cmd(sctx, BTRFS_SEND_C_WRITE);\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t\tTLV_PUT_PATH(sctx, BTRFS_SEND_A_PATH, p);\n\t\tTLV_PUT_U64(sctx, BTRFS_SEND_A_FILE_OFFSET, offset);\n\t\tret = put_data_header(sctx, len);\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t\tmemset(sctx->send_buf + sctx->send_size, 0, len);\n\t\tsctx->send_size += len;\n\t\tret = send_cmd(sctx);\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t\toffset += len;\n\t}\n\tsctx->cur_inode_next_write_offset = offset;\ntlv_put_failure:\n\tfs_path_free(p);\n\treturn ret;\n}",
        "static int alloc_try_nid_bottom_up_reserved_no_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[2];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn3 = &memblock.reserved.regions[0];": "static int alloc_try_nid_bottom_up_reserved_no_space_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[2];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[1];\n\tstruct memblock_region *rgn3 = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\tstruct region r1, r2;\n\n\tphys_addr_t r3_size = SZ_256;\n\tphys_addr_t gap_size = SMP_CACHE_BYTES;\n\tphys_addr_t total_size;\n\tphys_addr_t max_addr;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2;\n\tr1.size = SMP_CACHE_BYTES;\n\n\tr2.size = SZ_128;\n\tr2.base = r1.base - (r2.size + gap_size);\n\n\ttotal_size = r1.size + r2.size + r3_size;\n\tmin_addr = r2.base + r2.size;\n\tmax_addr = r1.base;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr,\n\t\t\t\t\t       NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn3->size == r3_size);\n\tassert(rgn3->base == memblock_start_of_DRAM());\n\n\tassert(rgn2->size == r2.size);\n\tassert(rgn2->base == r2.base);\n\n\tassert(rgn1->size == r1.size);\n\tassert(rgn1->base == r1.base);\n\n\tassert(memblock.reserved.cnt == 3);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static bool bfq_better_to_idle(struct bfq_queue *bfqq)\n{\n\tstruct bfq_data *bfqd = bfqq->bfqd;\n\tbool idling_boosts_thr_with_no_issue, idling_needed_for_service_guar;\n": "static bool bfq_better_to_idle(struct bfq_queue *bfqq)\n{\n\tstruct bfq_data *bfqd = bfqq->bfqd;\n\tbool idling_boosts_thr_with_no_issue, idling_needed_for_service_guar;\n\n\t/* No point in idling for bfqq if it won't get requests any longer */\n\tif (unlikely(!bfqq_process_refs(bfqq)))\n\t\treturn false;\n\n\tif (unlikely(bfqd->strict_guarantees))\n\t\treturn true;\n\n\t/*\n\t * Idling is performed only if slice_idle > 0. In addition, we\n\t * do not idle if\n\t * (a) bfqq is async\n\t * (b) bfqq is in the idle io prio class: in this case we do\n\t * not idle because we want to minimize the bandwidth that\n\t * queues in this class can steal to higher-priority queues\n\t */\n\tif (bfqd->bfq_slice_idle == 0 || !bfq_bfqq_sync(bfqq) ||\n\t   bfq_class_idle(bfqq))\n\t\treturn false;\n\n\tidling_boosts_thr_with_no_issue =\n\t\tidling_boosts_thr_without_issues(bfqd, bfqq);\n\n\tidling_needed_for_service_guar =\n\t\tidling_needed_for_service_guarantees(bfqd, bfqq);\n\n\t/*\n\t * We have now the two components we need to compute the\n\t * return value of the function, which is true only if idling\n\t * either boosts the throughput (without issues), or is\n\t * necessary to preserve service guarantees.\n\t */\n\treturn idling_boosts_thr_with_no_issue ||\n\t\tidling_needed_for_service_guar;\n}",
        "static int ef100_alloc_vis(struct efx_nic *efx, unsigned int *allocated_vis)\n{\n\t/* EF100 uses a single TXQ per channel, as all checksum offloading\n\t * is configured in the TX descriptor, and there is no TX Pacer for\n\t * HIGHPRI queues.": "static int ef100_alloc_vis(struct efx_nic *efx, unsigned int *allocated_vis)\n{\n\t/* EF100 uses a single TXQ per channel, as all checksum offloading\n\t * is configured in the TX descriptor, and there is no TX Pacer for\n\t * HIGHPRI queues.\n\t */\n\tunsigned int tx_vis = efx->n_tx_channels + efx->n_extra_tx_channels;\n\tunsigned int rx_vis = efx->n_rx_channels;\n\tunsigned int min_vis, max_vis;\n\n\tEFX_WARN_ON_PARANOID(efx->tx_queues_per_channel != 1);\n\n\ttx_vis += efx->n_xdp_channels * efx->xdp_tx_per_channel;\n\n\tmax_vis = max(rx_vis, tx_vis);\n\t/* Currently don't handle resource starvation and only accept\n\t * our maximum needs and no less.\n\t */\n\tmin_vis = max_vis;\n\n\treturn efx_mcdi_alloc_vis(efx, min_vis, max_vis,\n\t\t\t\t  NULL, allocated_vis);\n}",
        "static int cache_obj_to_cnode(struct uv_bios_hub_info *obj)\n{\n\tint cnode;\n\tunion geoid_u geoid;\n\tint obj_rack, obj_slot, obj_blade;": "static int cache_obj_to_cnode(struct uv_bios_hub_info *obj)\n{\n\tint cnode;\n\tunion geoid_u geoid;\n\tint obj_rack, obj_slot, obj_blade;\n\tint rack, slot, blade;\n\n\tif (!obj->f.fields.this_part && !obj->f.fields.is_shared)\n\t\treturn 0;\n\n\tif (location_to_bpos(obj->location, &obj_rack, &obj_slot, &obj_blade))\n\t\treturn -1;\n\n\tfor (cnode = 0; cnode < num_cnodes; cnode++) {\n\t\tgeoid = cnode_to_geoid(cnode);\n\t\track = geo_rack(geoid);\n\t\tslot = geo_slot(geoid);\n\t\tblade = geo_blade(geoid);\n\t\tif (obj_rack == rack && obj_slot == slot && obj_blade == blade)\n\t\t\tprev_obj_to_cnode[obj->id] = cnode;\n\t}\n\n\treturn 0;\n}",
        "static int bind_control_target(struct pool *pool, struct dm_target *ti)\n{\n\tstruct pool_c *pt = ti->private;\n\n\t/*": "static int bind_control_target(struct pool *pool, struct dm_target *ti)\n{\n\tstruct pool_c *pt = ti->private;\n\n\t/*\n\t * We want to make sure that a pool in PM_FAIL mode is never upgraded.\n\t */\n\tenum pool_mode old_mode = get_pool_mode(pool);\n\tenum pool_mode new_mode = pt->adjusted_pf.mode;\n\n\t/*\n\t * Don't change the pool's mode until set_pool_mode() below.\n\t * Otherwise the pool's process_* function pointers may\n\t * not match the desired pool mode.\n\t */\n\tpt->adjusted_pf.mode = old_mode;\n\n\tpool->ti = ti;\n\tpool->pf = pt->adjusted_pf;\n\tpool->low_water_blocks = pt->low_water_blocks;\n\n\tset_pool_mode(pool, new_mode);\n\n\treturn 0;\n}",
        "static void __smb2_lease_break_noti(struct work_struct *wk)\n{\n\tstruct smb2_lease_break *rsp = NULL;\n\tstruct ksmbd_work *work = container_of(wk, struct ksmbd_work, work);\n\tstruct lease_break_info *br_info = work->request_buf;": "static void __smb2_lease_break_noti(struct work_struct *wk)\n{\n\tstruct smb2_lease_break *rsp = NULL;\n\tstruct ksmbd_work *work = container_of(wk, struct ksmbd_work, work);\n\tstruct lease_break_info *br_info = work->request_buf;\n\tstruct ksmbd_conn *conn = work->conn;\n\tstruct smb2_hdr *rsp_hdr;\n\n\tif (allocate_oplock_break_buf(work)) {\n\t\tksmbd_debug(OPLOCK, \"smb2_allocate_rsp_buf failed! \");\n\t\tksmbd_free_work_struct(work);\n\t\tatomic_dec(&conn->r_count);\n\t\treturn;\n\t}\n\n\trsp_hdr = smb2_get_msg(work->response_buf);\n\tmemset(rsp_hdr, 0, sizeof(struct smb2_hdr) + 2);\n\t*(__be32 *)work->response_buf =\n\t\tcpu_to_be32(conn->vals->header_size);\n\trsp_hdr->ProtocolId = SMB2_PROTO_NUMBER;\n\trsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE;\n\trsp_hdr->CreditRequest = cpu_to_le16(0);\n\trsp_hdr->Command = SMB2_OPLOCK_BREAK;\n\trsp_hdr->Flags = (SMB2_FLAGS_SERVER_TO_REDIR);\n\trsp_hdr->NextCommand = 0;\n\trsp_hdr->MessageId = cpu_to_le64(-1);\n\trsp_hdr->Id.SyncId.ProcessId = 0;\n\trsp_hdr->Id.SyncId.TreeId = 0;\n\trsp_hdr->SessionId = 0;\n\tmemset(rsp_hdr->Signature, 0, 16);\n\n\trsp = smb2_get_msg(work->response_buf);\n\trsp->StructureSize = cpu_to_le16(44);\n\trsp->Epoch = br_info->epoch;\n\trsp->Flags = 0;\n\n\tif (br_info->curr_state & (SMB2_LEASE_WRITE_CACHING_LE |\n\t\t\tSMB2_LEASE_HANDLE_CACHING_LE))\n\t\trsp->Flags = SMB2_NOTIFY_BREAK_LEASE_FLAG_ACK_REQUIRED;\n\n\tmemcpy(rsp->LeaseKey, br_info->lease_key, SMB2_LEASE_KEY_SIZE);\n\trsp->CurrentLeaseState = br_info->curr_state;\n\trsp->NewLeaseState = br_info->new_state;\n\trsp->BreakReason = 0;\n\trsp->AccessMaskHint = 0;\n\trsp->ShareMaskHint = 0;\n\n\tinc_rfc1001_len(work->response_buf, 44);\n\n\tksmbd_conn_write(work);\n\tksmbd_free_work_struct(work);\n\tatomic_dec(&conn->r_count);\n}",
        "static int vmu_connect(struct maple_device *mdev)\n{\n\tunsigned long test_flash_data, basic_flash_data;\n\tint c, error;\n\tstruct memcard *card;": "static int vmu_connect(struct maple_device *mdev)\n{\n\tunsigned long test_flash_data, basic_flash_data;\n\tint c, error;\n\tstruct memcard *card;\n\tu32 partnum = 0;\n\n\ttest_flash_data = be32_to_cpu(mdev->devinfo.function);\n\t/* Need to count how many bits are set - to find out which\n\t * function_data element has details of the memory card\n\t */\n\tc = hweight_long(test_flash_data);\n\n\tbasic_flash_data = be32_to_cpu(mdev->devinfo.function_data[c - 1]);\n\n\tcard = kmalloc(sizeof(struct memcard), GFP_KERNEL);\n\tif (!card) {\n\t\terror = -ENOMEM;\n\t\tgoto fail_nomem;\n\t}\n\n\tcard->partitions = (basic_flash_data >> 24 & 0xFF) + 1;\n\tcard->blocklen = ((basic_flash_data >> 16 & 0xFF) + 1) << 5;\n\tcard->writecnt = basic_flash_data >> 12 & 0xF;\n\tcard->readcnt = basic_flash_data >> 8 & 0xF;\n\tcard->removable = basic_flash_data >> 7 & 1;\n\n\tcard->partition = 0;\n\n\t/*\n\t* Not sure there are actually any multi-partition devices in the\n\t* real world, but the hardware supports them, so, so will we\n\t*/\n\tcard->parts = kmalloc_array(card->partitions, sizeof(struct vmupart),\n\t\t\t\t    GFP_KERNEL);\n\tif (!card->parts) {\n\t\terror = -ENOMEM;\n\t\tgoto fail_partitions;\n\t}\n\n\tcard->mtd = kmalloc_array(card->partitions, sizeof(struct mtd_info),\n\t\t\t\t  GFP_KERNEL);\n\tif (!card->mtd) {\n\t\terror = -ENOMEM;\n\t\tgoto fail_mtd_info;\n\t}\n\n\tmaple_set_drvdata(mdev, card);\n\n\t/*\n\t* We want to trap meminfo not get cond\n\t* so set interval to zero, but rely on maple bus\n\t* driver to pass back the results of the meminfo\n\t*/\n\tmaple_getcond_callback(mdev, vmu_queryblocks, 0,\n\t\tMAPLE_FUNC_MEMCARD);\n\n\t/* Make sure we are clear to go */\n\tif (atomic_read(&mdev->busy) == 1) {\n\t\twait_event_interruptible_timeout(mdev->maple_wait,\n\t\t\tatomic_read(&mdev->busy) == 0, HZ);\n\t\tif (atomic_read(&mdev->busy) == 1) {\n\t\t\tdev_notice(&mdev->dev, \"VMU at (%d, %d) is busy\\n\",\n\t\t\t\tmdev->port, mdev->unit);\n\t\t\terror = -EAGAIN;\n\t\t\tgoto fail_device_busy;\n\t\t}\n\t}\n\n\tatomic_set(&mdev->busy, 1);\n\n\t/*\n\t* Set up the minfo call: vmu_queryblocks will handle\n\t* the information passed back\n\t*/\n\terror = maple_add_packet(mdev, MAPLE_FUNC_MEMCARD,\n\t\tMAPLE_COMMAND_GETMINFO, 2, &partnum);\n\tif (error) {\n\t\tdev_err(&mdev->dev, \"Could not lock VMU at (%d, %d)\"\n\t\t\t\" error is 0x%X\\n\", mdev->port, mdev->unit, error);\n\t\tgoto fail_mtd_info;\n\t}\n\treturn 0;\n\nfail_device_busy:\n\tkfree(card->mtd);\nfail_mtd_info:\n\tkfree(card->parts);\nfail_partitions:\n\tkfree(card);\nfail_nomem:\n\treturn error;\n}",
        "static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 rar_low, rar_high;\n\tu8 *addr = adapter->mac_table[index].addr;": "static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 rar_low, rar_high;\n\tu8 *addr = adapter->mac_table[index].addr;\n\n\t/* HW expects these to be in network order when they are plugged\n\t * into the registers which are little endian.  In order to guarantee\n\t * that ordering we need to do an leXX_to_cpup here in order to be\n\t * ready for the byteswap that occurs with writel\n\t */\n\trar_low = le32_to_cpup((__le32 *)(addr));\n\trar_high = le16_to_cpup((__le16 *)(addr + 4));\n\n\t/* Indicate to hardware the Address is Valid. */\n\tif (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {\n\t\tif (is_valid_ether_addr(addr))\n\t\t\trar_high |= E1000_RAH_AV;\n\n\t\tif (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)\n\t\t\trar_high |= E1000_RAH_ASEL_SRC_ADDR;\n\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_82575:\n\t\tcase e1000_i210:\n\t\t\tif (adapter->mac_table[index].state &\n\t\t\t    IGB_MAC_STATE_QUEUE_STEERING)\n\t\t\t\trar_high |= E1000_RAH_QSEL_ENABLE;\n\n\t\t\trar_high |= E1000_RAH_POOL_1 *\n\t\t\t\t    adapter->mac_table[index].queue;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\trar_high |= E1000_RAH_POOL_1 <<\n\t\t\t\t    adapter->mac_table[index].queue;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\twr32(E1000_RAL(index), rar_low);\n\twrfl();\n\twr32(E1000_RAH(index), rar_high);\n\twrfl();\n}",
        "static void test_array_map(void)\n{\n\t__u32 key, num_cpus, max_entries;\n\tint i, err;\n\tstruct for_each_array_map_elem *skel;": "static void test_array_map(void)\n{\n\t__u32 key, num_cpus, max_entries;\n\tint i, err;\n\tstruct for_each_array_map_elem *skel;\n\t__u64 *percpu_valbuf = NULL;\n\tsize_t percpu_val_sz;\n\t__u64 val, expected_total;\n\tLIBBPF_OPTS(bpf_test_run_opts, topts,\n\t\t.data_in = &pkt_v4,\n\t\t.data_size_in = sizeof(pkt_v4),\n\t\t.repeat = 1,\n\t);\n\n\tskel = for_each_array_map_elem__open_and_load();\n\tif (!ASSERT_OK_PTR(skel, \"for_each_array_map_elem__open_and_load\"))\n\t\treturn;\n\n\texpected_total = 0;\n\tmax_entries = bpf_map__max_entries(skel->maps.arraymap);\n\tfor (i = 0; i < max_entries; i++) {\n\t\tkey = i;\n\t\tval = i + 1;\n\t\t/* skip the last iteration for expected total */\n\t\tif (i != max_entries - 1)\n\t\t\texpected_total += val;\n\t\terr = bpf_map__update_elem(skel->maps.arraymap, &key, sizeof(key),\n\t\t\t\t\t   &val, sizeof(val), BPF_ANY);\n\t\tif (!ASSERT_OK(err, \"map_update\"))\n\t\t\tgoto out;\n\t}\n\n\tnum_cpus = bpf_num_possible_cpus();\n\tpercpu_val_sz = sizeof(__u64) * num_cpus;\n\tpercpu_valbuf = malloc(percpu_val_sz);\n\tif (!ASSERT_OK_PTR(percpu_valbuf, \"percpu_valbuf\"))\n\t\tgoto out;\n\n\tkey = 0;\n\tfor (i = 0; i < num_cpus; i++)\n\t\tpercpu_valbuf[i] = i + 1;\n\terr = bpf_map__update_elem(skel->maps.percpu_map, &key, sizeof(key),\n\t\t\t\t   percpu_valbuf, percpu_val_sz, BPF_ANY);\n\tif (!ASSERT_OK(err, \"percpu_map_update\"))\n\t\tgoto out;\n\n\terr = bpf_prog_test_run_opts(bpf_program__fd(skel->progs.test_pkt_access), &topts);\n\tduration = topts.duration;\n\tif (CHECK(err || topts.retval, \"ipv4\", \"err %d errno %d retval %d\\n\",\n\t\t  err, errno, topts.retval))\n\t\tgoto out;\n\n\tASSERT_EQ(skel->bss->arraymap_output, expected_total, \"array_output\");\n\tASSERT_EQ(skel->bss->cpu + 1, skel->bss->percpu_val, \"percpu_val\");\n\nout:\n\tfree(percpu_valbuf);\n\tfor_each_array_map_elem__destroy(skel);\n}",
        "static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)\n{\n\tstruct rvu *rvu = mwork->rvu;\n\tstruct otx2_mbox_dev *mdev;\n\tstruct mbox_hdr *rsp_hdr;": "static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)\n{\n\tstruct rvu *rvu = mwork->rvu;\n\tstruct otx2_mbox_dev *mdev;\n\tstruct mbox_hdr *rsp_hdr;\n\tstruct mbox_msghdr *msg;\n\tstruct mbox_wq_info *mw;\n\tstruct otx2_mbox *mbox;\n\tint offset, id, devid;\n\n\tswitch (type) {\n\tcase TYPE_AFPF:\n\t\tmw = &rvu->afpf_wq_info;\n\t\tbreak;\n\tcase TYPE_AFVF:\n\t\tmw = &rvu->afvf_wq_info;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tdevid = mwork - mw->mbox_wrk_up;\n\tmbox = &mw->mbox_up;\n\tmdev = &mbox->dev[devid];\n\n\trsp_hdr = mdev->mbase + mbox->rx_start;\n\tif (mw->mbox_wrk_up[devid].up_num_msgs == 0) {\n\t\tdev_warn(rvu->dev, \"mbox up handler: num_msgs = 0\\n\");\n\t\treturn;\n\t}\n\n\toffset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);\n\n\tfor (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {\n\t\tmsg = mdev->mbase + offset;\n\n\t\tif (msg->id >= MBOX_MSG_MAX) {\n\t\t\tdev_err(rvu->dev,\n\t\t\t\t\"Mbox msg with unknown ID 0x%x\\n\", msg->id);\n\t\t\tgoto end;\n\t\t}\n\n\t\tif (msg->sig != OTX2_MBOX_RSP_SIG) {\n\t\t\tdev_err(rvu->dev,\n\t\t\t\t\"Mbox msg with wrong signature %x, ID 0x%x\\n\",\n\t\t\t\tmsg->sig, msg->id);\n\t\t\tgoto end;\n\t\t}\n\n\t\tswitch (msg->id) {\n\t\tcase MBOX_MSG_CGX_LINK_EVENT:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (msg->rc)\n\t\t\t\tdev_err(rvu->dev,\n\t\t\t\t\t\"Mbox msg response has err %d, ID 0x%x\\n\",\n\t\t\t\t\tmsg->rc, msg->id);\n\t\t\tbreak;\n\t\t}\nend:\n\t\toffset = mbox->rx_start + msg->next_msgoff;\n\t\tmdev->msgs_acked++;\n\t}\n\tmw->mbox_wrk_up[devid].up_num_msgs = 0;\n\n\totx2_mbox_reset(mbox, devid);\n}",
        "static void vidtv_psi_nit_table_update_sec_len(struct vidtv_psi_table_nit *nit)\n{\n\tu16 length = 0;\n\tstruct vidtv_psi_table_transport *t = nit->transport;\n\tu16 desc_loop_len;": "static void vidtv_psi_nit_table_update_sec_len(struct vidtv_psi_table_nit *nit)\n{\n\tu16 length = 0;\n\tstruct vidtv_psi_table_transport *t = nit->transport;\n\tu16 desc_loop_len;\n\tu16 transport_loop_len = 0;\n\n\t/*\n\t * from immediately after 'section_length' until\n\t * 'network_descriptor_length'\n\t */\n\tlength += NIT_LEN_UNTIL_NETWORK_DESCRIPTOR_LEN;\n\n\tdesc_loop_len = vidtv_psi_desc_comp_loop_len(nit->descriptor);\n\tvidtv_psi_set_desc_loop_len(&nit->bitfield, desc_loop_len, 12);\n\n\tlength += desc_loop_len;\n\n\tlength += sizeof_field(struct vidtv_psi_table_nit, bitfield2);\n\n\twhile (t) {\n\t\t/* skip both pointers at the end */\n\t\ttransport_loop_len += sizeof(struct vidtv_psi_table_transport) -\n\t\t\t\t      sizeof(struct vidtv_psi_desc *) -\n\t\t\t\t      sizeof(struct vidtv_psi_table_transport *);\n\n\t\tlength += transport_loop_len;\n\n\t\tdesc_loop_len = vidtv_psi_desc_comp_loop_len(t->descriptor);\n\t\tvidtv_psi_set_desc_loop_len(&t->bitfield, desc_loop_len, 12);\n\n\t\tlength += desc_loop_len;\n\n\t\tt = t->next;\n\t}\n\n\t// Actually sets the transport stream loop len, maybe rename this function later\n\tvidtv_psi_set_desc_loop_len(&nit->bitfield2, transport_loop_len, 12);\n\tlength += CRC_SIZE_IN_BYTES;\n\n\tvidtv_psi_set_sec_len(&nit->header, length);\n}",
        "static int alloc_try_nid_top_down_cap_max_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_top_down_cap_max_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_256;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_end_of_DRAM() - SZ_1K;\n\tmax_addr = memblock_end_of_DRAM() + SZ_256;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == memblock_end_of_DRAM() - size);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static inline void lx_message_dump(struct lx_rmh *rmh)\n{}\n#endif\n\n": "static inline void lx_message_dump(struct lx_rmh *rmh)\n{}\n#endif\n\n\n\n/* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */\n#define XILINX_TIMEOUT_MS       40\n#define XILINX_POLL_NO_SLEEP    100\n#define XILINX_POLL_ITERATIONS  150\n\n\nstatic int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)\n{\n\tu32 reg = ED_DSP_TIMED_OUT;\n\tint dwloop;\n\n\tif (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {\n\t\tdev_err(chip->card->dev, \"PIOSendMessage eReg_CSM %x\\n\", reg);\n\t\treturn -EBUSY;\n\t}\n\n\t/* write command */\n\tlx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);\n\n\t/* MicoBlaze gogogo */\n\tlx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);\n\n\t/* wait for device to answer */\n\tfor (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {\n\t\tif (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {\n\t\t\tif (rmh->dsp_stat == 0)\n\t\t\t\treg = lx_dsp_reg_read(chip, eReg_CRM1);\n\t\t\telse\n\t\t\t\treg = 0;\n\t\t\tgoto polling_successful;\n\t\t} else\n\t\t\tudelay(1);\n\t}\n\tdev_warn(chip->card->dev, \"TIMEOUT lx_message_send_atomic! \"\n\t\t   \"polling failed\\n\");\n\npolling_successful:\n\tif ((reg & ERROR_VALUE) == 0) {\n\t\t/* read response */\n\t\tif (rmh->stat_len) {\n\t\t\tsnd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));\n\t\t\tlx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,\n\t\t\t\t\t   rmh->stat_len);\n\t\t}\n\t} else\n\t\tdev_err(chip->card->dev, \"rmh error: %08x\\n\", reg);\n\n\t/* clear Reg_CSM_MR */\n\tlx_dsp_reg_write(chip, eReg_CSM, 0);\n\n\tswitch (reg) {\n\tcase ED_DSP_TIMED_OUT:\n\t\tdev_warn(chip->card->dev, \"lx_message_send: dsp timeout\\n\");\n\t\treturn -ETIMEDOUT;\n\n\tcase ED_DSP_CRASHED:\n\t\tdev_warn(chip->card->dev, \"lx_message_send: dsp crashed\\n\");\n\t\treturn -EAGAIN;\n\t}\n\n\tlx_message_dump(rmh);\n\n\treturn reg;\n}",
        "static int max_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)\n{\n\tstruct ddb_input *input = fe->sec_priv;\n\tstruct ddb_port *port = input->port;\n\tstruct ddb *dev = port->dev;": "static int max_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)\n{\n\tstruct ddb_input *input = fe->sec_priv;\n\tstruct ddb_port *port = input->port;\n\tstruct ddb *dev = port->dev;\n\tstruct ddb_dvb *dvb = &port->dvb[input->nr & 1];\n\tint tuner = 0;\n\tu32 nv, ov = dev->link[port->lnr].lnb.voltages;\n\tint res = 0;\n\tu32 fmode = dev->link[port->lnr].lnb.fmode;\n\n\tmutex_lock(&dev->link[port->lnr].lnb.lock);\n\tdvb->voltage = voltage;\n\n\tswitch (fmode) {\n\tcase 3:\n\tdefault:\n\tcase 0:\n\t\tif (fmode == 3)\n\t\t\tmax_set_input_unlocked(fe, 0);\n\t\tif (voltage == SEC_VOLTAGE_OFF)\n\t\t\tdev->link[port->lnr].lnb.voltage[dvb->input] &=\n\t\t\t\t~(1ULL << input->nr);\n\t\telse\n\t\t\tdev->link[port->lnr].lnb.voltage[dvb->input] |=\n\t\t\t\t(1ULL << input->nr);\n\n\t\tres = lnb_set_voltage(dev, port->lnr, dvb->input, voltage);\n\t\tbreak;\n\tcase 1:\n\tcase 2:\n\t\tif (voltage == SEC_VOLTAGE_OFF)\n\t\t\tdev->link[port->lnr].lnb.voltages &=\n\t\t\t\t~(1ULL << input->nr);\n\t\telse\n\t\t\tdev->link[port->lnr].lnb.voltages |=\n\t\t\t\t(1ULL << input->nr);\n\n\t\tnv = dev->link[port->lnr].lnb.voltages;\n\n\t\tif (old_quattro) {\n\t\t\tif (dvb->tone == SEC_TONE_ON)\n\t\t\t\ttuner |= 2;\n\t\t\tif (dvb->voltage == SEC_VOLTAGE_18)\n\t\t\t\ttuner |= 1;\n\t\t} else {\n\t\t\tif (dvb->tone == SEC_TONE_ON)\n\t\t\t\ttuner |= 1;\n\t\t\tif (dvb->voltage == SEC_VOLTAGE_18)\n\t\t\t\ttuner |= 2;\n\t\t}\n\t\tres = max_set_input_unlocked(fe, tuner);\n\n\t\tif (nv != ov) {\n\t\t\tif (nv) {\n\t\t\t\tlnb_set_voltage(\n\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t0, SEC_VOLTAGE_13);\n\t\t\t\tif (fmode == 1) {\n\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t0, SEC_VOLTAGE_13);\n\t\t\t\t\tif (old_quattro) {\n\t\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t\t1, SEC_VOLTAGE_18);\n\t\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t\t2, SEC_VOLTAGE_13);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t\t1, SEC_VOLTAGE_13);\n\t\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t\t2, SEC_VOLTAGE_18);\n\t\t\t\t\t}\n\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t3, SEC_VOLTAGE_18);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tlnb_set_voltage(\n\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t0, SEC_VOLTAGE_OFF);\n\t\t\t\tif (fmode == 1) {\n\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t1, SEC_VOLTAGE_OFF);\n\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t2, SEC_VOLTAGE_OFF);\n\t\t\t\t\tlnb_set_voltage(\n\t\t\t\t\t\tdev, port->lnr,\n\t\t\t\t\t\t3, SEC_VOLTAGE_OFF);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tbreak;\n\t}\n\tmutex_unlock(&dev->link[port->lnr].lnb.lock);\n\treturn res;\n}",
        "static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val)\n{\n\t__be16 adc_enable;\n\tu8 rpt[3];\n\tktime_t predict_end_t, timeout;": "static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val)\n{\n\t__be16 adc_enable;\n\tu8 rpt[3];\n\tktime_t predict_end_t, timeout;\n\tunsigned int pre_wait_time;\n\tint ret;\n\n\tmutex_lock(&mad->adc_lock);\n\n\t/* Select the preferred ADC channel */\n\tret = regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,\n\t\t\t\t channel << MT6360_PREFERCH_SHFT);\n\tif (ret)\n\t\tgoto out_adc_lock;\n\n\tadc_enable = cpu_to_be16(MT6360_ADCEN_MASK | BIT(channel));\n\tret = regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));\n\tif (ret)\n\t\tgoto out_adc_lock;\n\n\tpredict_end_t = ktime_add_ms(mad->last_off_timestamps[channel], 2 * ADC_WAIT_TIME_MS);\n\n\tif (ktime_after(ktime_get(), predict_end_t))\n\t\tpre_wait_time = ADC_WAIT_TIME_MS;\n\telse\n\t\tpre_wait_time = 3 * ADC_WAIT_TIME_MS;\n\n\tif (msleep_interruptible(pre_wait_time)) {\n\t\tret = -ERESTARTSYS;\n\t\tgoto out_adc_conv;\n\t}\n\n\ttimeout = ktime_add_ms(ktime_get(), ADC_CONV_TIMEOUT_MS);\n\twhile (true) {\n\t\tret = regmap_raw_read(mad->regmap, MT6360_REG_PMUADCRPT1, rpt, sizeof(rpt));\n\t\tif (ret)\n\t\t\tgoto out_adc_conv;\n\n\t\t/*\n\t\t * There are two functions, ZCV and TypeC OTP, running ADC VBAT and TS in\n\t\t * background, and ADC samples are taken on a fixed frequency no matter read the\n\t\t * previous one or not.\n\t\t * To avoid conflict, We set minimum time threshold after enable ADC and\n\t\t * check report channel is the same.\n\t\t * The worst case is run the same ADC twice and background function is also running,\n\t\t * ADC conversion sequence is desire channel before start ADC, background ADC,\n\t\t * desire channel after start ADC.\n\t\t * So the minimum correct data is three times of typical conversion time.\n\t\t */\n\t\tif ((rpt[0] & MT6360_RPTCH_MASK) == channel)\n\t\t\tbreak;\n\n\t\tif (ktime_compare(ktime_get(), timeout) > 0) {\n\t\t\tret = -ETIMEDOUT;\n\t\t\tgoto out_adc_conv;\n\t\t}\n\n\t\tusleep_range(ADC_LOOP_TIME_US / 2, ADC_LOOP_TIME_US);\n\t}\n\n\t*val = rpt[1] << 8 | rpt[2];\n\tret = IIO_VAL_INT;\n\nout_adc_conv:\n\t/* Only keep ADC enable */\n\tadc_enable = cpu_to_be16(MT6360_ADCEN_MASK);\n\tregmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));\n\tmad->last_off_timestamps[channel] = ktime_get();\n\t/* Config prefer channel to NO_PREFER */\n\tregmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,\n\t\t\t   MT6360_NO_PREFER << MT6360_PREFERCH_SHFT);\nout_adc_lock:\n\tmutex_unlock(&mad->adc_lock);\n\n\treturn ret;\n}",
        "static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)\n{\n\tstruct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);\n\tint err;\n": "static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)\n{\n\tstruct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);\n\tint err;\n\n\tpfvf->maxlen = 0;\n\tpfvf->minlen = 0;\n\n\t/* Remove this PF_FUNC from bcast pkt replication list */\n\terr = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, false);\n\tif (err) {\n\t\tdev_err(rvu->dev,\n\t\t\t\"Bcast list, failed to disable PF_FUNC 0x%x\\n\",\n\t\t\tpcifunc);\n\t}\n\n\t/* Free and disable any MCAM entries used by this NIX LF */\n\trvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);\n\n\t/* Disable DMAC filters used */\n\trvu_cgx_disable_dmac_entries(rvu, pcifunc);\n}",
        "static int audioreach_gain_set(struct q6apm_graph *graph, struct audioreach_module *module)\n{\n\tstruct apm_module_param_data *param_data;\n\tstruct apm_gain_module_cfg *cfg;\n\tint rc, payload_size;": "static int audioreach_gain_set(struct q6apm_graph *graph, struct audioreach_module *module)\n{\n\tstruct apm_module_param_data *param_data;\n\tstruct apm_gain_module_cfg *cfg;\n\tint rc, payload_size;\n\tstruct gpr_pkt *pkt;\n\n\tpayload_size = APM_GAIN_CFG_PSIZE;\n\tpkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);\n\tif (IS_ERR(pkt))\n\t\treturn PTR_ERR(pkt);\n\n\tcfg = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;\n\n\tparam_data = &cfg->param_data;\n\tparam_data->module_instance_id = module->instance_id;\n\tparam_data->error_code = 0;\n\tparam_data->param_id = APM_PARAM_ID_GAIN;\n\tparam_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;\n\n\tcfg->gain_cfg.gain = module->gain;\n\n\trc = q6apm_send_cmd_sync(graph->apm, pkt, 0);\n\n\tkfree(pkt);\n\n\treturn rc;\n}",
        "static void test_isolated(int parent_cgroup_fd, int child_cgroup_fd)\n{\n\tstruct cg_storage_multi_isolated *obj;\n\tstruct cgroup_value expected_cgroup_value;\n\tstruct bpf_cgroup_storage_key key;": "static void test_isolated(int parent_cgroup_fd, int child_cgroup_fd)\n{\n\tstruct cg_storage_multi_isolated *obj;\n\tstruct cgroup_value expected_cgroup_value;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct bpf_link *parent_egress1_link = NULL, *parent_egress2_link = NULL;\n\tstruct bpf_link *child_egress1_link = NULL, *child_egress2_link = NULL;\n\tstruct bpf_link *parent_ingress_link = NULL, *child_ingress_link = NULL;\n\tbool err;\n\n\tobj = cg_storage_multi_isolated__open_and_load();\n\tif (CHECK(!obj, \"skel-load\", \"errno %d\", errno))\n\t\treturn;\n\n\t/* Attach to parent cgroup, trigger packet from child.\n\t * Assert that there is three runs, two with parent cgroup egress and\n\t * one with parent cgroup ingress, stored in separate parent storages.\n\t * Also assert that child cgroup's storages does not exist\n\t */\n\tparent_egress1_link = bpf_program__attach_cgroup(obj->progs.egress1,\n\t\t\t\t\t\t\t parent_cgroup_fd);\n\tif (!ASSERT_OK_PTR(parent_egress1_link, \"parent-egress1-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tparent_egress2_link = bpf_program__attach_cgroup(obj->progs.egress2,\n\t\t\t\t\t\t\t parent_cgroup_fd);\n\tif (!ASSERT_OK_PTR(parent_egress2_link, \"parent-egress2-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tparent_ingress_link = bpf_program__attach_cgroup(obj->progs.ingress,\n\t\t\t\t\t\t\t parent_cgroup_fd);\n\tif (!ASSERT_OK_PTR(parent_ingress_link, \"parent-ingress-cg-attach\"))\n\t\tgoto close_bpf_object;\n\terr = connect_send(CHILD_CGROUP);\n\tif (CHECK(err, \"first-connect-send\", \"errno %d\", errno))\n\t\tgoto close_bpf_object;\n\tif (CHECK(obj->bss->invocations != 3,\n\t\t  \"first-invoke\", \"invocations=%d\", obj->bss->invocations))\n\t\tgoto close_bpf_object;\n\tkey.cgroup_inode_id = get_cgroup_id(PARENT_CGROUP);\n\tkey.attach_type = BPF_CGROUP_INET_EGRESS;\n\texpected_cgroup_value = (struct cgroup_value) { .egress_pkts = 2 };\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey.attach_type = BPF_CGROUP_INET_INGRESS;\n\texpected_cgroup_value = (struct cgroup_value) { .ingress_pkts = 1 };\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey.cgroup_inode_id = get_cgroup_id(CHILD_CGROUP);\n\tkey.attach_type = BPF_CGROUP_INET_EGRESS;\n\tif (assert_storage_noexist(obj->maps.cgroup_storage, &key))\n\t\tgoto close_bpf_object;\n\tkey.attach_type = BPF_CGROUP_INET_INGRESS;\n\tif (assert_storage_noexist(obj->maps.cgroup_storage, &key))\n\t\tgoto close_bpf_object;\n\n\t/* Attach to parent and child cgroup, trigger packet from child.\n\t * Assert that there is six additional runs, parent cgroup egresses and\n\t * ingress, child cgroup egresses and ingress.\n\t * Assert that egree and ingress storages are separate.\n\t */\n\tchild_egress1_link = bpf_program__attach_cgroup(obj->progs.egress1,\n\t\t\t\t\t\t\tchild_cgroup_fd);\n\tif (!ASSERT_OK_PTR(child_egress1_link, \"child-egress1-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tchild_egress2_link = bpf_program__attach_cgroup(obj->progs.egress2,\n\t\t\t\t\t\t\tchild_cgroup_fd);\n\tif (!ASSERT_OK_PTR(child_egress2_link, \"child-egress2-cg-attach\"))\n\t\tgoto close_bpf_object;\n\tchild_ingress_link = bpf_program__attach_cgroup(obj->progs.ingress,\n\t\t\t\t\t\t\tchild_cgroup_fd);\n\tif (!ASSERT_OK_PTR(child_ingress_link, \"child-ingress-cg-attach\"))\n\t\tgoto close_bpf_object;\n\terr = connect_send(CHILD_CGROUP);\n\tif (CHECK(err, \"second-connect-send\", \"errno %d\", errno))\n\t\tgoto close_bpf_object;\n\tif (CHECK(obj->bss->invocations != 9,\n\t\t  \"second-invoke\", \"invocations=%d\", obj->bss->invocations))\n\t\tgoto close_bpf_object;\n\tkey.cgroup_inode_id = get_cgroup_id(PARENT_CGROUP);\n\tkey.attach_type = BPF_CGROUP_INET_EGRESS;\n\texpected_cgroup_value = (struct cgroup_value) { .egress_pkts = 4 };\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey.attach_type = BPF_CGROUP_INET_INGRESS;\n\texpected_cgroup_value = (struct cgroup_value) { .ingress_pkts = 2 };\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey.cgroup_inode_id = get_cgroup_id(CHILD_CGROUP);\n\tkey.attach_type = BPF_CGROUP_INET_EGRESS;\n\texpected_cgroup_value = (struct cgroup_value) { .egress_pkts = 2 };\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\tkey.attach_type = BPF_CGROUP_INET_INGRESS;\n\texpected_cgroup_value = (struct cgroup_value) { .ingress_pkts = 1 };\n\tif (assert_storage(obj->maps.cgroup_storage,\n\t\t\t   &key, &expected_cgroup_value))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(parent_egress1_link);\n\tbpf_link__destroy(parent_egress2_link);\n\tbpf_link__destroy(parent_ingress_link);\n\tbpf_link__destroy(child_egress1_link);\n\tbpf_link__destroy(child_egress2_link);\n\tbpf_link__destroy(child_ingress_link);\n\n\tcg_storage_multi_isolated__destroy(obj);\n}",
        "static int ax25_info_show(struct seq_file *seq, void *v)\n{\n\tax25_cb *ax25 = hlist_entry(v, struct ax25_cb, ax25_node);\n\tchar buf[11];\n\tint k;": "static int ax25_info_show(struct seq_file *seq, void *v)\n{\n\tax25_cb *ax25 = hlist_entry(v, struct ax25_cb, ax25_node);\n\tchar buf[11];\n\tint k;\n\n\n\t/*\n\t * New format:\n\t * magic dev src_addr dest_addr,digi1,digi2,.. st vs vr va t1 t1 t2 t2 t3 t3 idle idle n2 n2 rtt window paclen Snd-Q Rcv-Q inode\n\t */\n\n\tseq_printf(seq, \"%p %s %s%s \",\n\t\t   ax25,\n\t\t   ax25->ax25_dev == NULL? \"???\" : ax25->ax25_dev->dev->name,\n\t\t   ax2asc(buf, &ax25->source_addr),\n\t\t   ax25->iamdigi? \"*\":\"\");\n\tseq_printf(seq, \"%s\", ax2asc(buf, &ax25->dest_addr));\n\n\tfor (k=0; (ax25->digipeat != NULL) && (k < ax25->digipeat->ndigi); k++) {\n\t\tseq_printf(seq, \",%s%s\",\n\t\t\t   ax2asc(buf, &ax25->digipeat->calls[k]),\n\t\t\t   ax25->digipeat->repeated[k]? \"*\":\"\");\n\t}\n\n\tseq_printf(seq, \" %d %d %d %d %lu %lu %lu %lu %lu %lu %lu %lu %d %d %lu %d %d\",\n\t\t   ax25->state,\n\t\t   ax25->vs, ax25->vr, ax25->va,\n\t\t   ax25_display_timer(&ax25->t1timer) / HZ, ax25->t1 / HZ,\n\t\t   ax25_display_timer(&ax25->t2timer) / HZ, ax25->t2 / HZ,\n\t\t   ax25_display_timer(&ax25->t3timer) / HZ, ax25->t3 / HZ,\n\t\t   ax25_display_timer(&ax25->idletimer) / (60 * HZ),\n\t\t   ax25->idle / (60 * HZ),\n\t\t   ax25->n2count, ax25->n2,\n\t\t   ax25->rtt / HZ,\n\t\t   ax25->window,\n\t\t   ax25->paclen);\n\n\tif (ax25->sk != NULL) {\n\t\tseq_printf(seq, \" %d %d %lu\\n\",\n\t\t\t   sk_wmem_alloc_get(ax25->sk),\n\t\t\t   sk_rmem_alloc_get(ax25->sk),\n\t\t\t   sock_i_ino(ax25->sk));\n\t} else {\n\t\tseq_puts(seq, \" * * *\\n\");\n\t}\n\treturn 0;\n}",
        "static int mipid02_configure_from_rx(struct mipid02_dev *bridge)\n{\n\tstruct v4l2_fwnode_endpoint *ep = &bridge->rx;\n\tbool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;\n\tbool *polarities = ep->bus.mipi_csi2.lane_polarities;": "static int mipid02_configure_from_rx(struct mipid02_dev *bridge)\n{\n\tstruct v4l2_fwnode_endpoint *ep = &bridge->rx;\n\tbool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;\n\tbool *polarities = ep->bus.mipi_csi2.lane_polarities;\n\tint nb = ep->bus.mipi_csi2.num_data_lanes;\n\tint ret;\n\n\tret = mipid02_configure_clk_lane(bridge);\n\tif (ret)\n\t\treturn ret;\n\n\tret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,\n\t\t\t\t\t   polarities);\n\tif (ret)\n\t\treturn ret;\n\n\tret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,\n\t\t\t\t\t   polarities);\n\tif (ret)\n\t\treturn ret;\n\n\tbridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;\n\tbridge->r.mode_reg1 |= (nb - 1) << 1;\n\n\treturn mipid02_configure_from_rx_speed(bridge);\n}",
        "static bool ca0132_download_dsp_images(struct hda_codec *codec)\n{\n\tbool dsp_loaded = false;\n\tstruct ca0132_spec *spec = codec->spec;\n\tconst struct dsp_image_seg *dsp_os_image;": "static bool ca0132_download_dsp_images(struct hda_codec *codec)\n{\n\tbool dsp_loaded = false;\n\tstruct ca0132_spec *spec = codec->spec;\n\tconst struct dsp_image_seg *dsp_os_image;\n\tconst struct firmware *fw_entry = NULL;\n\t/*\n\t * Alternate firmwares for different variants. The Recon3Di apparently\n\t * can use the default firmware, but I'll leave the option in case\n\t * it needs it again.\n\t */\n\tswitch (ca0132_quirk(spec)) {\n\tcase QUIRK_SBZ:\n\tcase QUIRK_R3D:\n\tcase QUIRK_AE5:\n\t\tif (request_firmware(&fw_entry, DESKTOP_EFX_FILE,\n\t\t\t\t\tcodec->card->dev) != 0)\n\t\t\tcodec_dbg(codec, \"Desktop firmware not found.\");\n\t\telse\n\t\t\tcodec_dbg(codec, \"Desktop firmware selected.\");\n\t\tbreak;\n\tcase QUIRK_R3DI:\n\t\tif (request_firmware(&fw_entry, R3DI_EFX_FILE,\n\t\t\t\t\tcodec->card->dev) != 0)\n\t\t\tcodec_dbg(codec, \"Recon3Di alt firmware not detected.\");\n\t\telse\n\t\t\tcodec_dbg(codec, \"Recon3Di firmware selected.\");\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\t/*\n\t * Use default ctefx.bin if no alt firmware is detected, or if none\n\t * exists for your particular codec.\n\t */\n\tif (!fw_entry) {\n\t\tcodec_dbg(codec, \"Default firmware selected.\");\n\t\tif (request_firmware(&fw_entry, EFX_FILE,\n\t\t\t\t\tcodec->card->dev) != 0)\n\t\t\treturn false;\n\t}\n\n\tdsp_os_image = (struct dsp_image_seg *)(fw_entry->data);\n\tif (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {\n\t\tcodec_err(codec, \"ca0132 DSP load image failed\\n\");\n\t\tgoto exit_download;\n\t}\n\n\tdsp_loaded = dspload_wait_loaded(codec);\n\nexit_download:\n\trelease_firmware(fw_entry);\n\n\treturn dsp_loaded;\n}",
        "static int alloc_bottom_up_disjoint_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[0];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[1];\n\tstruct region r1;": "static int alloc_bottom_up_disjoint_check(void)\n{\n\tstruct memblock_region *rgn1 = &memblock.reserved.regions[0];\n\tstruct memblock_region *rgn2 = &memblock.reserved.regions[1];\n\tstruct region r1;\n\tvoid *allocated_ptr = NULL;\n\n\tphys_addr_t r2_size = SZ_16;\n\t/* Use custom alignment */\n\tphys_addr_t alignment = SMP_CACHE_BYTES * 2;\n\tphys_addr_t total_size;\n\tphys_addr_t expected_start;\n\n\tsetup_memblock();\n\n\tr1.base = memblock_start_of_DRAM() + SZ_2;\n\tr1.size = SZ_2;\n\n\ttotal_size = r1.size + r2_size;\n\texpected_start = memblock_start_of_DRAM() + alignment;\n\n\tmemblock_reserve(r1.base, r1.size);\n\n\tallocated_ptr = memblock_alloc(r2_size, alignment);\n\n\tassert(allocated_ptr);\n\n\tassert(rgn1->size == r1.size);\n\tassert(rgn1->base == r1.base);\n\n\tassert(rgn2->size == r2_size);\n\tassert(rgn2->base == expected_start);\n\n\tassert(memblock.reserved.cnt == 2);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static int task_fn_area_2(struct anybuss_host *cd, struct ab_task *t)\n{\n\tstruct area_priv *pd = &t->area_pd;\n\tunsigned int ind_ap;\n\tint ret;": "static int task_fn_area_2(struct anybuss_host *cd, struct ab_task *t)\n{\n\tstruct area_priv *pd = &t->area_pd;\n\tunsigned int ind_ap;\n\tint ret;\n\n\tif (!cd->power_on)\n\t\treturn -EIO;\n\tregmap_read(cd->regmap, REG_IND_AP, &ind_ap);\n\tif (!(atomic_read(&cd->ind_ab) & pd->flags)) {\n\t\t/* we don't own the area yet */\n\t\tif (time_after(jiffies, t->start_jiffies + TIMEOUT)) {\n\t\t\tdev_warn(cd->dev, \"timeout waiting for area\");\n\t\t\tdump_stack();\n\t\t\treturn -ETIMEDOUT;\n\t\t}\n\t\treturn -EINPROGRESS;\n\t}\n\t/* we own the area, do what we're here to do */\n\tif (pd->is_write)\n\t\tregmap_bulk_write(cd->regmap, pd->addr, pd->buf,\n\t\t\t\t  pd->count);\n\telse\n\t\tregmap_bulk_read(cd->regmap, pd->addr, pd->buf,\n\t\t\t\t pd->count);\n\t/* ask to release the area, must use unlocked release */\n\tind_ap &= ~IND_AP_ABITS;\n\tind_ap |= pd->flags;\n\tret = write_ind_ap(cd->regmap, ind_ap);\n\tif (ret)\n\t\treturn ret;\n\tt->task_fn = task_fn_area_3;\n\treturn -EINPROGRESS;\n}",
        "static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)\n{\n\tint\tnret;\n\tu32\treg_dt;\n": "static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)\n{\n\tint\tnret;\n\tu32\treg_dt;\n\n\t/* chattering */\n\tmdelay(VBUS_CHATTERING_MDELAY);\t\t/* wait (ms) */\n\n\t/* VBUS ON Check*/\n\treg_dt = gpiod_get_value(vbus_gpio);\n\tif (reg_dt == 0) {\n\t\tudc->linux_suspended = 0;\n\n\t\t_nbu2ss_reset_controller(udc);\n\t\tdev_info(udc->dev, \" ----- VBUS OFF\\n\");\n\n\t\tif (udc->vbus_active == 1) {\n\t\t\t/* VBUS OFF */\n\t\t\tudc->vbus_active = 0;\n\t\t\tif (udc->usb_suspended) {\n\t\t\t\tudc->usb_suspended = 0;\n\t\t\t\t/* _nbu2ss_reset_controller(udc); */\n\t\t\t}\n\t\t\tudc->devstate = USB_STATE_NOTATTACHED;\n\n\t\t\t_nbu2ss_quiesce(udc);\n\t\t\tif (udc->driver) {\n\t\t\t\tspin_unlock(&udc->lock);\n\t\t\t\tudc->driver->disconnect(&udc->gadget);\n\t\t\t\tspin_lock(&udc->lock);\n\t\t\t}\n\n\t\t\t_nbu2ss_disable_controller(udc);\n\t\t}\n\t} else {\n\t\tmdelay(5);\t\t/* wait (5ms) */\n\t\treg_dt = gpiod_get_value(vbus_gpio);\n\t\tif (reg_dt == 0)\n\t\t\treturn;\n\n\t\tdev_info(udc->dev, \" ----- VBUS ON\\n\");\n\n\t\tif (udc->linux_suspended)\n\t\t\treturn;\n\n\t\tif (udc->vbus_active == 0) {\n\t\t\t/* VBUS ON */\n\t\t\tudc->vbus_active = 1;\n\t\t\tudc->devstate = USB_STATE_POWERED;\n\n\t\t\tnret = _nbu2ss_enable_controller(udc);\n\t\t\tif (nret < 0) {\n\t\t\t\t_nbu2ss_disable_controller(udc);\n\t\t\t\tudc->vbus_active = 0;\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\t_nbu2ss_pullup(udc, 1);\n\n#ifdef UDC_DEBUG_DUMP\n\t\t\t_nbu2ss_dump_register(udc);\n#endif /* UDC_DEBUG_DUMP */\n\n\t\t} else {\n\t\t\tif (udc->devstate == USB_STATE_POWERED)\n\t\t\t\t_nbu2ss_pullup(udc, 1);\n\t\t}\n\t}\n}",
        "static int hdspm_autosync_ref(struct hdspm *hdspm)\n{\n\t/* This looks at the autosync selected sync reference */\n\tif (AES32 == hdspm->io_type) {\n": "static int hdspm_autosync_ref(struct hdspm *hdspm)\n{\n\t/* This looks at the autosync selected sync reference */\n\tif (AES32 == hdspm->io_type) {\n\n\t\tunsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);\n\t\tunsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;\n\t\t/* syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD is always true */\n\t\tif (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN) {\n\t\t\treturn syncref;\n\t\t}\n\t\treturn HDSPM_AES32_AUTOSYNC_FROM_NONE;\n\n\t} else if (MADI == hdspm->io_type) {\n\n\t\tunsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);\n\t\tswitch (status2 & HDSPM_SelSyncRefMask) {\n\t\tcase HDSPM_SelSyncRef_WORD:\n\t\t\treturn HDSPM_AUTOSYNC_FROM_WORD;\n\t\tcase HDSPM_SelSyncRef_MADI:\n\t\t\treturn HDSPM_AUTOSYNC_FROM_MADI;\n\t\tcase HDSPM_SelSyncRef_TCO:\n\t\t\treturn HDSPM_AUTOSYNC_FROM_TCO;\n\t\tcase HDSPM_SelSyncRef_SyncIn:\n\t\t\treturn HDSPM_AUTOSYNC_FROM_SYNC_IN;\n\t\tcase HDSPM_SelSyncRef_NVALID:\n\t\t\treturn HDSPM_AUTOSYNC_FROM_NONE;\n\t\tdefault:\n\t\t\treturn HDSPM_AUTOSYNC_FROM_NONE;\n\t\t}\n\n\t}\n\treturn 0;\n}",
        "static bool erased_chunk_check_and_fixup(u8 *data_buf, int data_len)\n{\n\tu8 empty1, empty2;\n\n\t/*": "static bool erased_chunk_check_and_fixup(u8 *data_buf, int data_len)\n{\n\tu8 empty1, empty2;\n\n\t/*\n\t * an erased page flags an error in NAND_FLASH_STATUS, check if the page\n\t * is erased by looking for 0x54s at offsets 3 and 175 from the\n\t * beginning of each codeword\n\t */\n\n\tempty1 = data_buf[3];\n\tempty2 = data_buf[175];\n\n\t/*\n\t * if the erased codework markers, if they exist override them with\n\t * 0xffs\n\t */\n\tif ((empty1 == 0x54 && empty2 == 0xff) ||\n\t    (empty1 == 0xff && empty2 == 0x54)) {\n\t\tdata_buf[3] = 0xff;\n\t\tdata_buf[175] = 0xff;\n\t}\n\n\t/*\n\t * check if the entire chunk contains 0xffs or not. if it doesn't, then\n\t * restore the original values at the special offsets\n\t */\n\tif (memchr_inv(data_buf, 0xff, data_len)) {\n\t\tdata_buf[3] = empty1;\n\t\tdata_buf[175] = empty2;\n\n\t\treturn false;\n\t}\n\n\treturn true;\n}",
        "static int status_resync(struct seq_file *seq, struct mddev *mddev)\n{\n\tsector_t max_sectors, resync, res;\n\tunsigned long dt, db = 0;\n\tsector_t rt, curr_mark_cnt, resync_mark_cnt;": "static int status_resync(struct seq_file *seq, struct mddev *mddev)\n{\n\tsector_t max_sectors, resync, res;\n\tunsigned long dt, db = 0;\n\tsector_t rt, curr_mark_cnt, resync_mark_cnt;\n\tint scale, recovery_active;\n\tunsigned int per_milli;\n\n\tif (test_bit(MD_RECOVERY_SYNC, &mddev->recovery) ||\n\t    test_bit(MD_RECOVERY_RESHAPE, &mddev->recovery))\n\t\tmax_sectors = mddev->resync_max_sectors;\n\telse\n\t\tmax_sectors = mddev->dev_sectors;\n\n\tresync = mddev->curr_resync;\n\tif (resync <= 3) {\n\t\tif (test_bit(MD_RECOVERY_DONE, &mddev->recovery))\n\t\t\t/* Still cleaning up */\n\t\t\tresync = max_sectors;\n\t} else if (resync > max_sectors)\n\t\tresync = max_sectors;\n\telse\n\t\tresync -= atomic_read(&mddev->recovery_active);\n\n\tif (resync == 0) {\n\t\tif (test_bit(MD_RESYNCING_REMOTE, &mddev->recovery)) {\n\t\t\tstruct md_rdev *rdev;\n\n\t\t\trdev_for_each(rdev, mddev)\n\t\t\t\tif (rdev->raid_disk >= 0 &&\n\t\t\t\t    !test_bit(Faulty, &rdev->flags) &&\n\t\t\t\t    rdev->recovery_offset != MaxSector &&\n\t\t\t\t    rdev->recovery_offset) {\n\t\t\t\t\tseq_printf(seq, \"\\trecover=REMOTE\");\n\t\t\t\t\treturn 1;\n\t\t\t\t}\n\t\t\tif (mddev->reshape_position != MaxSector)\n\t\t\t\tseq_printf(seq, \"\\treshape=REMOTE\");\n\t\t\telse\n\t\t\t\tseq_printf(seq, \"\\tresync=REMOTE\");\n\t\t\treturn 1;\n\t\t}\n\t\tif (mddev->recovery_cp < MaxSector) {\n\t\t\tseq_printf(seq, \"\\tresync=PENDING\");\n\t\t\treturn 1;\n\t\t}\n\t\treturn 0;\n\t}\n\tif (resync < 3) {\n\t\tseq_printf(seq, \"\\tresync=DELAYED\");\n\t\treturn 1;\n\t}\n\n\tWARN_ON(max_sectors == 0);\n\t/* Pick 'scale' such that (resync>>scale)*1000 will fit\n\t * in a sector_t, and (max_sectors>>scale) will fit in a\n\t * u32, as those are the requirements for sector_div.\n\t * Thus 'scale' must be at least 10\n\t */\n\tscale = 10;\n\tif (sizeof(sector_t) > sizeof(unsigned long)) {\n\t\twhile ( max_sectors/2 > (1ULL<<(scale+32)))\n\t\t\tscale++;\n\t}\n\tres = (resync>>scale)*1000;\n\tsector_div(res, (u32)((max_sectors>>scale)+1));\n\n\tper_milli = res;\n\t{\n\t\tint i, x = per_milli/50, y = 20-x;\n\t\tseq_printf(seq, \"[\");\n\t\tfor (i = 0; i < x; i++)\n\t\t\tseq_printf(seq, \"=\");\n\t\tseq_printf(seq, \">\");\n\t\tfor (i = 0; i < y; i++)\n\t\t\tseq_printf(seq, \".\");\n\t\tseq_printf(seq, \"] \");\n\t}\n\tseq_printf(seq, \" %s =%3u.%u%% (%llu/%llu)\",\n\t\t   (test_bit(MD_RECOVERY_RESHAPE, &mddev->recovery)?\n\t\t    \"reshape\" :\n\t\t    (test_bit(MD_RECOVERY_CHECK, &mddev->recovery)?\n\t\t     \"check\" :\n\t\t     (test_bit(MD_RECOVERY_SYNC, &mddev->recovery) ?\n\t\t      \"resync\" : \"recovery\"))),\n\t\t   per_milli/10, per_milli % 10,\n\t\t   (unsigned long long) resync/2,\n\t\t   (unsigned long long) max_sectors/2);\n\n\t/*\n\t * dt: time from mark until now\n\t * db: blocks written from mark until now\n\t * rt: remaining time\n\t *\n\t * rt is a sector_t, which is always 64bit now. We are keeping\n\t * the original algorithm, but it is not really necessary.\n\t *\n\t * Original algorithm:\n\t *   So we divide before multiply in case it is 32bit and close\n\t *   to the limit.\n\t *   We scale the divisor (db) by 32 to avoid losing precision\n\t *   near the end of resync when the number of remaining sectors\n\t *   is close to 'db'.\n\t *   We then divide rt by 32 after multiplying by db to compensate.\n\t *   The '+1' avoids division by zero if db is very small.\n\t */\n\tdt = ((jiffies - mddev->resync_mark) / HZ);\n\tif (!dt) dt++;\n\n\tcurr_mark_cnt = mddev->curr_mark_cnt;\n\trecovery_active = atomic_read(&mddev->recovery_active);\n\tresync_mark_cnt = mddev->resync_mark_cnt;\n\n\tif (curr_mark_cnt >= (recovery_active + resync_mark_cnt))\n\t\tdb = curr_mark_cnt - (recovery_active + resync_mark_cnt);\n\n\trt = max_sectors - resync;    /* number of remaining sectors */\n\trt = div64_u64(rt, db/32+1);\n\trt *= dt;\n\trt >>= 5;\n\n\tseq_printf(seq, \" finish=%lu.%lumin\", (unsigned long)rt / 60,\n\t\t   ((unsigned long)rt % 60)/6);\n\n\tseq_printf(seq, \" speed=%ldK/sec\", db/2/dt);\n\treturn 1;\n}",
        "static void wwan_remove_dev(struct wwan_device *wwandev)\n{\n\tint ret;\n\n\t/* Prevent concurrent picking from wwan_create_dev */": "static void wwan_remove_dev(struct wwan_device *wwandev)\n{\n\tint ret;\n\n\t/* Prevent concurrent picking from wwan_create_dev */\n\tmutex_lock(&wwan_register_lock);\n\n\t/* WWAN device is created and registered (get+add) along with its first\n\t * child port, and subsequent port registrations only grab a reference\n\t * (get). The WWAN device must then be unregistered (del+put) along with\n\t * its last port, and reference simply dropped (put) otherwise. In the\n\t * same fashion, we must not unregister it when the ops are still there.\n\t */\n\tif (wwandev->ops)\n\t\tret = 1;\n\telse\n\t\tret = device_for_each_child(&wwandev->dev, NULL, is_wwan_child);\n\n\tif (!ret) {\n#ifdef CONFIG_WWAN_DEBUGFS\n\t\tdebugfs_remove_recursive(wwandev->debugfs_dir);\n#endif\n\t\tdevice_unregister(&wwandev->dev);\n\t} else {\n\t\tput_device(&wwandev->dev);\n\t}\n\n\tmutex_unlock(&wwan_register_lock);\n}",
        "static int __init wan_init(struct ibm_init_struct *iibm)\n{\n\tint res;\n\tint status = 0;\n": "static int __init wan_init(struct ibm_init_struct *iibm)\n{\n\tint res;\n\tint status = 0;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\t\"initializing wan subdriver\\n\");\n\n\tTPACPI_ACPIHANDLE_INIT(hkey);\n\n\ttp_features.wan = hkey_handle &&\n\t    acpi_evalf(hkey_handle, &status, \"GWAN\", \"qd\");\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\"wan is %s, status 0x%02x\\n\",\n\t\tstr_supported(tp_features.wan),\n\t\tstatus);\n\n#ifdef CONFIG_THINKPAD_ACPI_DEBUGFACILITIES\n\tif (dbg_wwanemul) {\n\t\ttp_features.wan = 1;\n\t\tpr_info(\"wwan switch emulation enabled\\n\");\n\t} else\n#endif\n\tif (tp_features.wan &&\n\t    !(status & TP_ACPI_WANCARD_HWPRESENT)) {\n\t\t/* no wan hardware present in system */\n\t\ttp_features.wan = 0;\n\t\tdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_RFKILL,\n\t\t\t   \"wan hardware not installed\\n\");\n\t}\n\n\tif (!tp_features.wan)\n\t\treturn -ENODEV;\n\n\tres = tpacpi_new_rfkill(TPACPI_RFK_WWAN_SW_ID,\n\t\t\t\t&wan_tprfk_ops,\n\t\t\t\tRFKILL_TYPE_WWAN,\n\t\t\t\tTPACPI_RFK_WWAN_SW_NAME,\n\t\t\t\ttrue);\n\treturn res;\n}",
        "static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)\n{\n\tconst struct pinmux_drive_reg *drive_regs = info->drive_regs;\n#define drive_nfields\tARRAY_SIZE(drive_regs->fields)\n#define drive_ofs(i)\tdrive_regs[(i) / drive_nfields]": "static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)\n{\n\tconst struct pinmux_drive_reg *drive_regs = info->drive_regs;\n#define drive_nfields\tARRAY_SIZE(drive_regs->fields)\n#define drive_ofs(i)\tdrive_regs[(i) / drive_nfields]\n#define drive_reg(i)\tdrive_ofs(i).reg\n#define drive_bit(i)\t((i) % drive_nfields)\n#define drive_field(i)\tdrive_ofs(i).fields[drive_bit(i)]\n\tconst struct pinmux_bias_reg *bias_regs = info->bias_regs;\n#define bias_npins\tARRAY_SIZE(bias_regs->pins)\n#define bias_ofs(i)\tbias_regs[(i) / bias_npins]\n#define bias_puen(i)\tbias_ofs(i).puen\n#define bias_pud(i)\tbias_ofs(i).pud\n#define bias_bit(i)\t((i) % bias_npins)\n#define bias_pin(i)\tbias_ofs(i).pins[bias_bit(i)]\n\tconst char *drvname = info->name;\n\tunsigned int *refcnts;\n\tunsigned int i, j, k;\n\n\tpr_info(\"sh_pfc: Checking %s\\n\", drvname);\n\tsh_pfc_num_regs = 0;\n\tsh_pfc_num_enums = 0;\n\tsh_pfc_bias_done = false;\n\tsh_pfc_drive_done = false;\n\tsh_pfc_power_done = false;\n\n\t/* Check pins */\n\tfor (i = 0; i < info->nr_pins; i++) {\n\t\tconst struct sh_pfc_pin *pin = &info->pins[i];\n\t\tunsigned int x;\n\n\t\tif (!pin->name) {\n\t\t\tsh_pfc_err(\"empty pin %u\\n\", i);\n\t\t\tcontinue;\n\t\t}\n\t\tfor (j = 0; j < i; j++) {\n\t\t\tconst struct sh_pfc_pin *pin2 = &info->pins[j];\n\n\t\t\tif (same_name(pin->name, pin2->name))\n\t\t\t\tsh_pfc_err(\"pin %s: name conflict\\n\",\n\t\t\t\t\t   pin->name);\n\n\t\t\tif (pin->pin != (u16)-1 && pin->pin == pin2->pin)\n\t\t\t\tsh_pfc_err(\"pin %s/%s: pin %u conflict\\n\",\n\t\t\t\t\t   pin->name, pin2->name, pin->pin);\n\n\t\t\tif (pin->enum_id && pin->enum_id == pin2->enum_id)\n\t\t\t\tsh_pfc_err(\"pin %s/%s: enum_id %u conflict\\n\",\n\t\t\t\t\t   pin->name, pin2->name,\n\t\t\t\t\t   pin->enum_id);\n\t\t}\n\n\t\tif (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {\n\t\t\tif (!info->ops || !info->ops->get_bias ||\n\t\t\t    !info->ops->set_bias)\n\t\t\t\tsh_pfc_err_once(bias, \"SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\\n\");\n\n\t\t\tif (!bias_regs &&\n\t\t\t     (!info->ops || !info->ops->pin_to_portcr))\n\t\t\t\tsh_pfc_err_once(bias, \"SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\\n\");\n\t\t}\n\n\t\tif ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {\n\t\t\tconst struct pinmux_bias_reg *bias_reg =\n\t\t\t\trcar_pin_to_bias_reg(info, pin->pin, &x);\n\n\t\t\tif (!bias_reg ||\n\t\t\t    ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&\n\t\t\t     !bias_reg->puen))\n\t\t\t\tsh_pfc_err(\"pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\\n\",\n\t\t\t\t\t   pin->name);\n\n\t\t\tif (!bias_reg ||\n\t\t\t    ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&\n\t\t\t     !bias_reg->pud))\n\t\t\t\tsh_pfc_err(\"pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\\n\",\n\t\t\t\t\t   pin->name);\n\t\t}\n\n\t\tif (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {\n\t\t\tif (!drive_regs) {\n\t\t\t\tsh_pfc_err_once(drive, \"SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\\n\");\n\t\t\t} else {\n\t\t\t\tfor (j = 0; drive_reg(j); j++) {\n\t\t\t\t\tif (!drive_field(j).pin &&\n\t\t\t\t\t    !drive_field(j).offset &&\n\t\t\t\t\t    !drive_field(j).size)\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\tif (drive_field(j).pin == pin->pin)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tif (!drive_reg(j))\n\t\t\t\t\tsh_pfc_err(\"pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\\n\",\n\t\t\t\t\t\t   pin->name);\n\t\t\t}\n\t\t}\n\n\t\tif (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {\n\t\t\tif (!info->ops || !info->ops->pin_to_pocctrl)\n\t\t\t\tsh_pfc_err_once(power, \"SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\\n\");\n\t\t\telse if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)\n\t\t\t\tsh_pfc_err(\"pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\\n\",\n\t\t\t\t\t   pin->name);\n\t\t} else if (info->ops && info->ops->pin_to_pocctrl &&\n\t\t\t   info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {\n\t\t\tsh_pfc_warn(\"pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\\n\",\n\t\t\t\t    pin->name);\n\t\t}\n\t}\n\n\t/* Check groups and functions */\n\trefcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);\n\tif (!refcnts)\n\t\treturn;\n\n\tfor (i = 0; i < info->nr_functions; i++) {\n\t\tconst struct sh_pfc_function *func = &info->functions[i];\n\n\t\tif (!func->name) {\n\t\t\tsh_pfc_err(\"empty function %u\\n\", i);\n\t\t\tcontinue;\n\t\t}\n\t\tfor (j = 0; j < i; j++) {\n\t\t\tif (same_name(func->name, info->functions[j].name))\n\t\t\t\tsh_pfc_err(\"function %s: name conflict\\n\",\n\t\t\t\t\t   func->name);\n\t\t}\n\t\tfor (j = 0; j < func->nr_groups; j++) {\n\t\t\tfor (k = 0; k < info->nr_groups; k++) {\n\t\t\t\tif (same_name(func->groups[j],\n\t\t\t\t\t      info->groups[k].name)) {\n\t\t\t\t\trefcnts[k]++;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (k == info->nr_groups)\n\t\t\t\tsh_pfc_err(\"function %s: group %s not found\\n\",\n\t\t\t\t\t   func->name, func->groups[j]);\n\t\t}\n\t}\n\n\tfor (i = 0; i < info->nr_groups; i++) {\n\t\tconst struct sh_pfc_pin_group *group = &info->groups[i];\n\n\t\tif (!group->name) {\n\t\t\tsh_pfc_err(\"empty group %u\\n\", i);\n\t\t\tcontinue;\n\t\t}\n\t\tfor (j = 0; j < i; j++)\n\t\t\tsh_pfc_compare_groups(drvname, group, &info->groups[j]);\n\n\t\tif (!refcnts[i])\n\t\t\tsh_pfc_err(\"orphan group %s\\n\", group->name);\n\t\telse if (refcnts[i] > 1)\n\t\t\tsh_pfc_warn(\"group %s referenced by %u functions\\n\",\n\t\t\t\t    group->name, refcnts[i]);\n\t}\n\n\tkfree(refcnts);\n\n\t/* Check config register descriptions */\n\tfor (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)\n\t\tsh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);\n\n\t/* Check drive strength registers */\n\tfor (i = 0; drive_regs && drive_regs[i].reg; i++)\n\t\tsh_pfc_check_drive_reg(info, &drive_regs[i]);\n\n\tfor (i = 0; drive_regs && drive_reg(i); i++) {\n\t\tif (!drive_field(i).pin && !drive_field(i).offset &&\n\t\t    !drive_field(i).size)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < i; j++) {\n\t\t\tif (drive_field(i).pin == drive_field(j).pin &&\n\t\t\t    drive_field(j).offset && drive_field(j).size) {\n\t\t\t\tsh_pfc_err(\"drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\\n\",\n\t\t\t\t\t   drive_reg(i), drive_bit(i),\n\t\t\t\t\t   drive_reg(j), drive_bit(j));\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Check bias registers */\n\tfor (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)\n\t\tsh_pfc_check_bias_reg(info, &bias_regs[i]);\n\n\tfor (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {\n\t\tif (bias_pin(i) == SH_PFC_PIN_NONE)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < i; j++) {\n\t\t\tif (bias_pin(i) != bias_pin(j))\n\t\t\t\tcontinue;\n\n\t\t\tif (bias_puen(i) && bias_puen(j))\n\t\t\t\tsh_pfc_err(\"bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\\n\",\n\t\t\t\t\t   bias_puen(i), bias_bit(i),\n\t\t\t\t\t   bias_puen(j), bias_bit(j));\n\t\t\tif (bias_pud(i) && bias_pud(j))\n\t\t\t\tsh_pfc_err(\"bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\\n\",\n\t\t\t\t\t   bias_pud(i), bias_bit(i),\n\t\t\t\t\t   bias_pud(j), bias_bit(j));\n\t\t}\n\t}\n\n\t/* Check ioctrl registers */\n\tfor (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)\n\t\tsh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);\n\n\t/* Check data registers */\n\tfor (i = 0; info->data_regs && info->data_regs[i].reg; i++) {\n\t\tsh_pfc_check_reg(drvname, info->data_regs[i].reg,\n\t\t\t\t GENMASK(info->data_regs[i].reg_width - 1, 0));\n\t\tsh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,\n\t\t\t\t       info->data_regs[i].enum_ids,\n\t\t\t\t       info->data_regs[i].reg_width);\n\t}\n\n#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO\n\t/* Check function GPIOs */\n\tfor (i = 0; i < info->nr_func_gpios; i++) {\n\t\tconst struct pinmux_func *func = &info->func_gpios[i];\n\n\t\tif (!func->name) {\n\t\t\tsh_pfc_err(\"empty function gpio %u\\n\", i);\n\t\t\tcontinue;\n\t\t}\n\t\tfor (j = 0; j < i; j++) {\n\t\t\tif (same_name(func->name, info->func_gpios[j].name))\n\t\t\t\tsh_pfc_err(\"func_gpio %s: name conflict\\n\",\n\t\t\t\t\t   func->name);\n\t\t}\n\t\tif (sh_pfc_check_enum(drvname, func->enum_id))\n\t\t\tsh_pfc_err(\"%s enum_id %u conflict\\n\", func->name,\n\t\t\t\t   func->enum_id);\n\t}\n#endif\n}",
        "static void bnx2x_set_gmii_tx_driver(struct link_params *params)\n{\n\tstruct bnx2x *bp = params->bp;\n\tstruct bnx2x_phy *phy = &params->phy[INT_PHY];\n\tu16 lp_up2;": "static void bnx2x_set_gmii_tx_driver(struct link_params *params)\n{\n\tstruct bnx2x *bp = params->bp;\n\tstruct bnx2x_phy *phy = &params->phy[INT_PHY];\n\tu16 lp_up2;\n\tu16 tx_driver;\n\tu16 bank;\n\n\t/* Read precomp */\n\tCL22_RD_OVER_CL45(bp, phy,\n\t\t\t  MDIO_REG_BANK_OVER_1G,\n\t\t\t  MDIO_OVER_1G_LP_UP2, &lp_up2);\n\n\t/* Bits [10:7] at lp_up2, positioned at [15:12] */\n\tlp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>\n\t\t   MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<\n\t\t  MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);\n\n\tif (lp_up2 == 0)\n\t\treturn;\n\n\tfor (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;\n\t      bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {\n\t\tCL22_RD_OVER_CL45(bp, phy,\n\t\t\t\t  bank,\n\t\t\t\t  MDIO_TX0_TX_DRIVER, &tx_driver);\n\n\t\t/* Replace tx_driver bits [15:12] */\n\t\tif (lp_up2 !=\n\t\t    (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {\n\t\t\ttx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;\n\t\t\ttx_driver |= lp_up2;\n\t\t\tCL22_WR_OVER_CL45(bp, phy,\n\t\t\t\t\t  bank,\n\t\t\t\t\t  MDIO_TX0_TX_DRIVER, tx_driver);\n\t\t}\n\t}\n}",
        "static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)\n{\n\tstruct idtcm *idtcm = channel->idtcm;\n\tu8 i;\n\tint err;": "static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)\n{\n\tstruct idtcm *idtcm = channel->idtcm;\n\tu8 i;\n\tint err;\n\tu8 buf[6] = {0};\n\ts64 fcw;\n\n\tif (channel->mode  != PTP_PLL_MODE_WRITE_FREQUENCY) {\n\t\terr = channel->configure_write_frequency(channel);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/*\n\t * Frequency Control Word unit is: 1.11 * 10^-10 ppm\n\t *\n\t * adjfreq:\n\t *       ppb * 10^9\n\t * FCW = ----------\n\t *          111\n\t *\n\t * adjfine:\n\t *       ppm_16 * 5^12\n\t * FCW = -------------\n\t *         111 * 2^4\n\t */\n\n\t/* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */\n\tfcw = scaled_ppm * 244140625ULL;\n\n\tfcw = div_s64(fcw, 1776);\n\n\tfor (i = 0; i < 6; i++) {\n\t\tbuf[i] = fcw & 0xff;\n\t\tfcw >>= 8;\n\t}\n\n\terr = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,\n\t\t\t  buf, sizeof(buf));\n\n\treturn err;\n}",
        "static void lpg_apply_lut_control(struct lpg_channel *chan)\n{\n\tstruct lpg *lpg = chan->lpg;\n\tunsigned int hi_pause;\n\tunsigned int lo_pause;": "static void lpg_apply_lut_control(struct lpg_channel *chan)\n{\n\tstruct lpg *lpg = chan->lpg;\n\tunsigned int hi_pause;\n\tunsigned int lo_pause;\n\tunsigned int conf = 0;\n\tunsigned int lo_idx = chan->pattern_lo_idx;\n\tunsigned int hi_idx = chan->pattern_hi_idx;\n\tu16 step = chan->ramp_tick_ms;\n\n\tif (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx)\n\t\treturn;\n\n\thi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step);\n\tlo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step);\n\n\tif (!chan->ramp_reverse)\n\t\tconf |= LPG_PATTERN_CONFIG_LO_TO_HI;\n\tif (!chan->ramp_oneshot)\n\t\tconf |= LPG_PATTERN_CONFIG_REPEAT;\n\tif (chan->ramp_ping_pong)\n\t\tconf |= LPG_PATTERN_CONFIG_TOGGLE;\n\tif (chan->ramp_hi_pause_ms)\n\t\tconf |= LPG_PATTERN_CONFIG_PAUSE_HI;\n\tif (chan->ramp_lo_pause_ms)\n\t\tconf |= LPG_PATTERN_CONFIG_PAUSE_LO;\n\n\tregmap_write(lpg->map, chan->base + LPG_PATTERN_CONFIG_REG, conf);\n\tregmap_write(lpg->map, chan->base + LPG_HI_IDX_REG, hi_idx);\n\tregmap_write(lpg->map, chan->base + LPG_LO_IDX_REG, lo_idx);\n\n\tregmap_bulk_write(lpg->map, chan->base + LPG_RAMP_DURATION_REG, &step, sizeof(step));\n\tregmap_write(lpg->map, chan->base + LPG_HI_PAUSE_REG, hi_pause);\n\tregmap_write(lpg->map, chan->base + LPG_LO_PAUSE_REG, lo_pause);\n}",
        "static void tcp_lp_rtt_sample(struct sock *sk, u32 rtt)\n{\n\tstruct lp *lp = inet_csk_ca(sk);\n\ts64 mowd = tcp_lp_owd_calculator(sk);\n": "static void tcp_lp_rtt_sample(struct sock *sk, u32 rtt)\n{\n\tstruct lp *lp = inet_csk_ca(sk);\n\ts64 mowd = tcp_lp_owd_calculator(sk);\n\n\t/* sorry that we don't have valid data */\n\tif (!(lp->flag & LP_VALID_RHZ) || !(lp->flag & LP_VALID_OWD))\n\t\treturn;\n\n\t/* record the next min owd */\n\tif (mowd < lp->owd_min)\n\t\tlp->owd_min = mowd;\n\n\t/* always forget the max of the max\n\t * we just set owd_max as one below it */\n\tif (mowd > lp->owd_max) {\n\t\tif (mowd > lp->owd_max_rsv) {\n\t\t\tif (lp->owd_max_rsv == 0)\n\t\t\t\tlp->owd_max = mowd;\n\t\t\telse\n\t\t\t\tlp->owd_max = lp->owd_max_rsv;\n\t\t\tlp->owd_max_rsv = mowd;\n\t\t} else\n\t\t\tlp->owd_max = mowd;\n\t}\n\n\t/* calc for smoothed owd */\n\tif (lp->sowd != 0) {\n\t\tmowd -= lp->sowd >> 3;\t/* m is now error in owd est */\n\t\tlp->sowd += mowd;\t/* owd = 7/8 owd + 1/8 new */\n\t} else\n\t\tlp->sowd = mowd << 3;\t/* take the measured time be owd */\n}",
        "static int mptcp_nl_cmd_set_flags(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct mptcp_pm_addr_entry addr = { .addr = { .family = AF_UNSPEC }, }, *entry;\n\tstruct nlattr *attr = info->attrs[MPTCP_PM_ATTR_ADDR];\n\tstruct pm_nl_pernet *pernet = genl_info_pm_nl(info);": "static int mptcp_nl_cmd_set_flags(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct mptcp_pm_addr_entry addr = { .addr = { .family = AF_UNSPEC }, }, *entry;\n\tstruct nlattr *attr = info->attrs[MPTCP_PM_ATTR_ADDR];\n\tstruct pm_nl_pernet *pernet = genl_info_pm_nl(info);\n\tu8 changed, mask = MPTCP_PM_ADDR_FLAG_BACKUP |\n\t\t\t   MPTCP_PM_ADDR_FLAG_FULLMESH;\n\tstruct net *net = sock_net(skb->sk);\n\tu8 bkup = 0, lookup_by_id = 0;\n\tint ret;\n\n\tret = mptcp_pm_parse_entry(attr, info, false, &addr);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tif (addr.flags & MPTCP_PM_ADDR_FLAG_BACKUP)\n\t\tbkup = 1;\n\tif (addr.addr.family == AF_UNSPEC) {\n\t\tlookup_by_id = 1;\n\t\tif (!addr.addr.id)\n\t\t\treturn -EOPNOTSUPP;\n\t}\n\n\tspin_lock_bh(&pernet->lock);\n\tentry = __lookup_addr(pernet, &addr.addr, lookup_by_id);\n\tif (!entry) {\n\t\tspin_unlock_bh(&pernet->lock);\n\t\treturn -EINVAL;\n\t}\n\tif ((addr.flags & MPTCP_PM_ADDR_FLAG_FULLMESH) &&\n\t    (entry->flags & MPTCP_PM_ADDR_FLAG_SIGNAL)) {\n\t\tspin_unlock_bh(&pernet->lock);\n\t\treturn -EINVAL;\n\t}\n\n\tchanged = (addr.flags ^ entry->flags) & mask;\n\tentry->flags = (entry->flags & ~mask) | (addr.flags & mask);\n\taddr = *entry;\n\tspin_unlock_bh(&pernet->lock);\n\n\tmptcp_nl_set_flags(net, &addr.addr, bkup, changed);\n\treturn 0;\n}",
        "static int power_down_aud(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxj_data *ext_attr = NULL;\n\tint rc;": "static int power_down_aud(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tstruct drxj_data *ext_attr = NULL;\n\tint rc;\n\n\tdev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;\n\text_attr = (struct drxj_data *) demod->my_ext_attr;\n\n\trc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\text_attr->aud_data.audio_is_active = false;\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void gv800s_init(struct bttv *btv)\n{\n\tint ix;\n\n\tgpio_inout(0xf107f, 0xf107f);": "static void gv800s_init(struct bttv *btv)\n{\n\tint ix;\n\n\tgpio_inout(0xf107f, 0xf107f);\n\tgpio_write(1<<19); /* reset the analog MUX */\n\tgpio_write(0);\n\n\t/* Preset camera 0 to the 4 controllers */\n\tfor (ix = 0; ix < 4; ix++) {\n\t\tbtv->sw_status[ix] = ix;\n\t\tgv800s_write(btv, ix, ix, 1);\n\t}\n\n\t/* Inputs on the \"master\" controller need this brightness fix */\n\tbttv_I2CWrite(btv, 0x18, 0x5, 0x90, 1);\n\n\tif (btv->c.nr > BTTV_MAX-4)\n\t\treturn;\n\t/*\n\t * Store the \"master\" controller pointer in the master\n\t * array for later use in the muxsel function.\n\t */\n\tmaster[btv->c.nr]   = btv;\n\tmaster[btv->c.nr+1] = btv;\n\tmaster[btv->c.nr+2] = btv;\n\tmaster[btv->c.nr+3] = btv;\n}",
        "static void kodicom4400r_init(struct bttv *btv)\n{\n\tint ix;\n\n\tgpio_inout(0x0003ff, 0x0003ff);": "static void kodicom4400r_init(struct bttv *btv)\n{\n\tint ix;\n\n\tgpio_inout(0x0003ff, 0x0003ff);\n\tgpio_write(1 << 9);\t/* reset MUX */\n\tgpio_write(0);\n\t/* Preset camera 0 to the 4 controllers */\n\tfor (ix = 0; ix < 4; ix++) {\n\t\tbtv->sw_status[ix] = ix;\n\t\tkodicom4400r_write(btv, ix, ix, 1);\n\t}\n\t/*\n\t * Since this is the \"master\", we need to set up the\n\t * other three controller chips' pointers to this structure\n\t * for later use in the muxsel routine.\n\t */\n\tif ((btv->c.nr<1) || (btv->c.nr>BTTV_MAX-3))\n\t    return;\n\tmaster[btv->c.nr-1] = btv;\n\tmaster[btv->c.nr]   = btv;\n\tmaster[btv->c.nr+1] = btv;\n\tmaster[btv->c.nr+2] = btv;\n}",
        "static void rbd_obj_copyup_write_object(struct rbd_obj_request *obj_req)\n{\n\tu32 bytes = rbd_obj_img_extents_bytes(obj_req);\n\tint ret;\n": "static void rbd_obj_copyup_write_object(struct rbd_obj_request *obj_req)\n{\n\tu32 bytes = rbd_obj_img_extents_bytes(obj_req);\n\tint ret;\n\n\trbd_assert(!obj_req->pending.result && !obj_req->pending.num_pending);\n\n\t/*\n\t * Only send non-zero copyup data to save some I/O and network\n\t * bandwidth -- zero copyup data is equivalent to the object not\n\t * existing.\n\t */\n\tif (obj_req->flags & RBD_OBJ_FLAG_COPYUP_ZEROS)\n\t\tbytes = 0;\n\n\tif (obj_req->img_request->snapc->num_snaps && bytes > 0) {\n\t\t/*\n\t\t * Send a copyup request with an empty snapshot context to\n\t\t * deep-copyup the object through all existing snapshots.\n\t\t * A second request with the current snapshot context will be\n\t\t * sent for the actual modification.\n\t\t */\n\t\tret = rbd_obj_copyup_empty_snapc(obj_req, bytes);\n\t\tif (ret) {\n\t\t\tobj_req->pending.result = ret;\n\t\t\treturn;\n\t\t}\n\n\t\tobj_req->pending.num_pending++;\n\t\tbytes = MODS_ONLY;\n\t}\n\n\tret = rbd_obj_copyup_current_snapc(obj_req, bytes);\n\tif (ret) {\n\t\tobj_req->pending.result = ret;\n\t\treturn;\n\t}\n\n\tobj_req->pending.num_pending++;\n}",
        "static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n\tu16 data = 0;": "static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n\tu16 data = 0;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\n\t/* Start measurement */\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\t/* Wait at least 3*128*(1/sysclk) <<< 1 millisec */\n\tmsleep(1);\n\n\t*count = 0;\n\trc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (data == 127)\n\t\t*count = *count + 1;\n\trc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (data == 127)\n\t\t*count = *count + 1;\n\trc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (data == 127)\n\t\t*count = *count + 1;\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void rcu_gp_fqs(bool first_time)\n{\n\tstruct rcu_node *rnp = rcu_get_root();\n\n\tWRITE_ONCE(rcu_state.gp_activity, jiffies);": "static void rcu_gp_fqs(bool first_time)\n{\n\tstruct rcu_node *rnp = rcu_get_root();\n\n\tWRITE_ONCE(rcu_state.gp_activity, jiffies);\n\tWRITE_ONCE(rcu_state.n_force_qs, rcu_state.n_force_qs + 1);\n\tif (first_time) {\n\t\t/* Collect dyntick-idle snapshots. */\n\t\tforce_qs_rnp(dyntick_save_progress_counter);\n\t} else {\n\t\t/* Handle dyntick-idle and offline CPUs. */\n\t\tforce_qs_rnp(rcu_implicit_dynticks_qs);\n\t}\n\t/* Clear flag to prevent immediate re-entry. */\n\tif (READ_ONCE(rcu_state.gp_flags) & RCU_GP_FLAG_FQS) {\n\t\traw_spin_lock_irq_rcu_node(rnp);\n\t\tWRITE_ONCE(rcu_state.gp_flags,\n\t\t\t   READ_ONCE(rcu_state.gp_flags) & ~RCU_GP_FLAG_FQS);\n\t\traw_spin_unlock_irq_rcu_node(rnp);\n\t}\n}",
        "static void test_bench_attach(void)\n{\n\tLIBBPF_OPTS(bpf_kprobe_multi_opts, opts);\n\tstruct kprobe_multi_empty *skel = NULL;\n\tlong attach_start_ns, attach_end_ns;": "static void test_bench_attach(void)\n{\n\tLIBBPF_OPTS(bpf_kprobe_multi_opts, opts);\n\tstruct kprobe_multi_empty *skel = NULL;\n\tlong attach_start_ns, attach_end_ns;\n\tlong detach_start_ns, detach_end_ns;\n\tdouble attach_delta, detach_delta;\n\tstruct bpf_link *link = NULL;\n\tchar **syms = NULL;\n\tsize_t cnt, i;\n\n\tif (!ASSERT_OK(get_syms(&syms, &cnt), \"get_syms\"))\n\t\treturn;\n\n\tskel = kprobe_multi_empty__open_and_load();\n\tif (!ASSERT_OK_PTR(skel, \"kprobe_multi_empty__open_and_load\"))\n\t\tgoto cleanup;\n\n\topts.syms = (const char **) syms;\n\topts.cnt = cnt;\n\n\tattach_start_ns = get_time_ns();\n\tlink = bpf_program__attach_kprobe_multi_opts(skel->progs.test_kprobe_empty,\n\t\t\t\t\t\t     NULL, &opts);\n\tattach_end_ns = get_time_ns();\n\n\tif (!ASSERT_OK_PTR(link, \"bpf_program__attach_kprobe_multi_opts\"))\n\t\tgoto cleanup;\n\n\tdetach_start_ns = get_time_ns();\n\tbpf_link__destroy(link);\n\tdetach_end_ns = get_time_ns();\n\n\tattach_delta = (attach_end_ns - attach_start_ns) / 1000000000.0;\n\tdetach_delta = (detach_end_ns - detach_start_ns) / 1000000000.0;\n\n\tprintf(\"%s: found %lu functions\\n\", __func__, cnt);\n\tprintf(\"%s: attached in %7.3lfs\\n\", __func__, attach_delta);\n\tprintf(\"%s: detached in %7.3lfs\\n\", __func__, detach_delta);\n\ncleanup:\n\tkprobe_multi_empty__destroy(skel);\n\tif (syms) {\n\t\tfor (i = 0; i < cnt; i++)\n\t\t\tfree(syms[i]);\n\t\tfree(syms);\n\t}\n}",
        "static int gdm_lte_receive_pkt(struct phy_dev *phy_dev, char *buf, int len)\n{\n\tstruct hci_packet *hci = (struct hci_packet *)buf;\n\tstruct hci_pdn_table_ind *pdn_table = (struct hci_pdn_table_ind *)buf;\n\tstruct sdu *sdu;": "static int gdm_lte_receive_pkt(struct phy_dev *phy_dev, char *buf, int len)\n{\n\tstruct hci_packet *hci = (struct hci_packet *)buf;\n\tstruct hci_pdn_table_ind *pdn_table = (struct hci_pdn_table_ind *)buf;\n\tstruct sdu *sdu;\n\tstruct net_device *dev;\n\tu8 endian = phy_dev->get_endian(phy_dev->priv_dev);\n\tint ret = 0;\n\tu16 cmd_evt;\n\tu32 nic_type;\n\tint index;\n\n\tif (!len)\n\t\treturn ret;\n\n\tcmd_evt = gdm_dev16_to_cpu(endian, hci->cmd_evt);\n\n\tdev = phy_dev->dev[0];\n\tif (!dev)\n\t\treturn 0;\n\n\tswitch (cmd_evt) {\n\tcase LTE_RX_SDU:\n\t\tsdu = (struct sdu *)hci->data;\n\t\tnic_type = gdm_dev32_to_cpu(endian, sdu->nic_type);\n\t\tindex = find_dev_index(nic_type);\n\t\tif (index < 0)\n\t\t\treturn index;\n\t\tdev = phy_dev->dev[index];\n\t\tgdm_lte_netif_rx(dev, hci->data, len, nic_type);\n\t\tbreak;\n\tcase LTE_RX_MULTI_SDU:\n\t\tgdm_lte_multi_sdu_pkt(phy_dev, buf, len);\n\t\tbreak;\n\tcase LTE_LINK_ON_OFF_INDICATION:\n\t\tnetdev_info(dev, \"link %s\\n\",\n\t\t\t    ((struct hci_connect_ind *)buf)->connect\n\t\t\t    ? \"on\" : \"off\");\n\t\tbreak;\n\tcase LTE_PDN_TABLE_IND:\n\t\tpdn_table = (struct hci_pdn_table_ind *)buf;\n\t\tnic_type = gdm_dev32_to_cpu(endian, pdn_table->nic_type);\n\t\tindex = find_dev_index(nic_type);\n\t\tif (index < 0)\n\t\t\treturn index;\n\t\tdev = phy_dev->dev[index];\n\t\tgdm_lte_pdn_table(dev, buf, len);\n\t\tfallthrough;\n\tdefault:\n\t\tret = gdm_lte_event_send(dev, buf, len);\n\t\tbreak;\n\t}\n\n\treturn ret;\n}",
        "static void do_test_lru_dist(int task, void *data)\n{\n\tunsigned int nr_misses = 0;\n\tstruct pfect_lru pfect_lru;\n\tunsigned long long key, value = 1234;": "static void do_test_lru_dist(int task, void *data)\n{\n\tunsigned int nr_misses = 0;\n\tstruct pfect_lru pfect_lru;\n\tunsigned long long key, value = 1234;\n\tunsigned int i;\n\n\tunsigned int lru_map_fd = ((unsigned int *)data)[0];\n\tunsigned int lru_size = ((unsigned int *)data)[1];\n\tunsigned long long key_offset = task * dist_key_counts;\n\n\tpfect_lru_init(&pfect_lru, lru_size, dist_key_counts);\n\n\tfor (i = 0; i < dist_key_counts; i++) {\n\t\tkey = dist_keys[i] + key_offset;\n\n\t\tpfect_lru_lookup_or_insert(&pfect_lru, key);\n\n\t\tif (!bpf_map_lookup_elem(lru_map_fd, &key, &value))\n\t\t\tcontinue;\n\n\t\tif (bpf_map_update_elem(lru_map_fd, &key, &value, BPF_NOEXIST)) {\n\t\t\tprintf(\"bpf_map_update_elem(lru_map_fd, %llu): errno:%d\\n\",\n\t\t\t       key, errno);\n\t\t\tassert(0);\n\t\t}\n\n\t\tnr_misses++;\n\t}\n\n\tprintf(\"    task:%d BPF LRU: nr_unique:%u(/%u) nr_misses:%u(/%u)\\n\",\n\t       task, pfect_lru.nr_unique, dist_key_counts, nr_misses,\n\t       dist_key_counts);\n\tprintf(\"    task:%d Perfect LRU: nr_unique:%u(/%u) nr_misses:%u(/%u)\\n\",\n\t       task, pfect_lru.nr_unique, pfect_lru.total,\n\t       pfect_lru.nr_misses, pfect_lru.total);\n\n\tpfect_lru_destroy(&pfect_lru);\n\tclose(lru_map_fd);\n}",
        "static void _test_errors_common(struct test_vcpu vcpu, enum mop_target target, int size)\n{\n\tint rv;\n\n\t/* Bad size: */": "static void _test_errors_common(struct test_vcpu vcpu, enum mop_target target, int size)\n{\n\tint rv;\n\n\t/* Bad size: */\n\trv = ERR_MOP(vcpu, target, WRITE, mem1, -1, GADDR_V(mem1));\n\tTEST_ASSERT(rv == -1 && errno == E2BIG, \"ioctl allows insane sizes\");\n\n\t/* Zero size: */\n\trv = ERR_MOP(vcpu, target, WRITE, mem1, 0, GADDR_V(mem1));\n\tTEST_ASSERT(rv == -1 && (errno == EINVAL || errno == ENOMEM),\n\t\t    \"ioctl allows 0 as size\");\n\n\t/* Bad flags: */\n\trv = ERR_MOP(vcpu, target, WRITE, mem1, size, GADDR_V(mem1), SET_FLAGS(-1));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL, \"ioctl allows all flags\");\n\n\t/* Bad guest address: */\n\trv = ERR_MOP(vcpu, target, WRITE, mem1, size, GADDR((void *)~0xfffUL), CHECK_ONLY);\n\tTEST_ASSERT(rv > 0, \"ioctl does not report bad guest memory access\");\n\n\t/* Bad host address: */\n\trv = ERR_MOP(vcpu, target, WRITE, 0, size, GADDR_V(mem1));\n\tTEST_ASSERT(rv == -1 && errno == EFAULT,\n\t\t    \"ioctl does not report bad host memory address\");\n\n\t/* Bad key: */\n\trv = ERR_MOP(vcpu, target, WRITE, mem1, size, GADDR_V(mem1), KEY(17));\n\tTEST_ASSERT(rv == -1 && errno == EINVAL, \"ioctl allows invalid key\");\n}",
        "static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tu16 data = 0;": "static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tu16 data = 0;\n\n\t/* Configure NSU_AOX */\n\trc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (!active)\n\t\tdata &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));\n\telse\n\t\tdata |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);\n\trc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void ov519_mode_init_regs(struct sd *sd)\n{\n\tstatic const struct ov_regvals mode_init_519_ov7670[] = {\n\t\t{ 0x5d,\t0x03 }, /* Turn off suspend mode */\n\t\t{ 0x53,\t0x9f }, /* was 9b in 1.65-1.08 */": "static void ov519_mode_init_regs(struct sd *sd)\n{\n\tstatic const struct ov_regvals mode_init_519_ov7670[] = {\n\t\t{ 0x5d,\t0x03 }, /* Turn off suspend mode */\n\t\t{ 0x53,\t0x9f }, /* was 9b in 1.65-1.08 */\n\t\t{ OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */\n\t\t{ 0xa2,\t0x20 }, /* a2-a5 are undocumented */\n\t\t{ 0xa3,\t0x18 },\n\t\t{ 0xa4,\t0x04 },\n\t\t{ 0xa5,\t0x28 },\n\t\t{ 0x37,\t0x00 },\t/* SetUsbInit */\n\t\t{ 0x55,\t0x02 }, /* 4.096 Mhz audio clock */\n\t\t/* Enable both fields, YUV Input, disable defect comp (why?) */\n\t\t{ 0x20,\t0x0c },\n\t\t{ 0x21,\t0x38 },\n\t\t{ 0x22,\t0x1d },\n\t\t{ 0x17,\t0x50 }, /* undocumented */\n\t\t{ 0x37,\t0x00 }, /* undocumented */\n\t\t{ 0x40,\t0xff }, /* I2C timeout counter */\n\t\t{ 0x46,\t0x00 }, /* I2C clock prescaler */\n\t\t{ 0x59,\t0x04 },\t/* new from windrv 090403 */\n\t\t{ 0xff,\t0x00 }, /* undocumented */\n\t\t/* windows reads 0x55 at this point, why? */\n\t};\n\n\tstatic const struct ov_regvals mode_init_519[] = {\n\t\t{ 0x5d,\t0x03 }, /* Turn off suspend mode */\n\t\t{ 0x53,\t0x9f }, /* was 9b in 1.65-1.08 */\n\t\t{ OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */\n\t\t{ 0xa2,\t0x20 }, /* a2-a5 are undocumented */\n\t\t{ 0xa3,\t0x18 },\n\t\t{ 0xa4,\t0x04 },\n\t\t{ 0xa5,\t0x28 },\n\t\t{ 0x37,\t0x00 },\t/* SetUsbInit */\n\t\t{ 0x55,\t0x02 }, /* 4.096 Mhz audio clock */\n\t\t/* Enable both fields, YUV Input, disable defect comp (why?) */\n\t\t{ 0x22,\t0x1d },\n\t\t{ 0x17,\t0x50 }, /* undocumented */\n\t\t{ 0x37,\t0x00 }, /* undocumented */\n\t\t{ 0x40,\t0xff }, /* I2C timeout counter */\n\t\t{ 0x46,\t0x00 }, /* I2C clock prescaler */\n\t\t{ 0x59,\t0x04 },\t/* new from windrv 090403 */\n\t\t{ 0xff,\t0x00 }, /* undocumented */\n\t\t/* windows reads 0x55 at this point, why? */\n\t};\n\n\tstruct gspca_dev *gspca_dev = (struct gspca_dev *)sd;\n\n\t/******** Set the mode ********/\n\tswitch (sd->sensor) {\n\tdefault:\n\t\twrite_regvals(sd, mode_init_519, ARRAY_SIZE(mode_init_519));\n\t\tif (sd->sensor == SEN_OV7640 ||\n\t\t    sd->sensor == SEN_OV7648) {\n\t\t\t/* Select 8-bit input mode */\n\t\t\treg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);\n\t\t}\n\t\tbreak;\n\tcase SEN_OV7660:\n\t\treturn;\t\t/* done by ov519_set_mode/fr() */\n\tcase SEN_OV7670:\n\t\twrite_regvals(sd, mode_init_519_ov7670,\n\t\t\t\tARRAY_SIZE(mode_init_519_ov7670));\n\t\tbreak;\n\t}\n\n\treg_w(sd, OV519_R10_H_SIZE,\tsd->gspca_dev.pixfmt.width >> 4);\n\treg_w(sd, OV519_R11_V_SIZE,\tsd->gspca_dev.pixfmt.height >> 3);\n\tif (sd->sensor == SEN_OV7670 &&\n\t    sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)\n\t\treg_w(sd, OV519_R12_X_OFFSETL, 0x04);\n\telse if (sd->sensor == SEN_OV7648 &&\n\t    sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)\n\t\treg_w(sd, OV519_R12_X_OFFSETL, 0x01);\n\telse\n\t\treg_w(sd, OV519_R12_X_OFFSETL, 0x00);\n\treg_w(sd, OV519_R13_X_OFFSETH,\t0x00);\n\treg_w(sd, OV519_R14_Y_OFFSETL,\t0x00);\n\treg_w(sd, OV519_R15_Y_OFFSETH,\t0x00);\n\treg_w(sd, OV519_R16_DIVIDER,\t0x00);\n\treg_w(sd, OV519_R25_FORMAT,\t0x03); /* YUV422 */\n\treg_w(sd, 0x26,\t\t\t0x00); /* Undocumented */\n\n\t/******** Set the framerate ********/\n\tif (frame_rate > 0)\n\t\tsd->frame_rate = frame_rate;\n\n/* FIXME: These are only valid at the max resolution. */\n\tsd->clockdiv = 0;\n\tswitch (sd->sensor) {\n\tcase SEN_OV7640:\n\tcase SEN_OV7648:\n\t\tswitch (sd->frame_rate) {\n\t\tdefault:\n/*\t\tcase 30: */\n\t\t\treg_w(sd, 0xa4, 0x0c);\n\t\t\treg_w(sd, 0x23, 0xff);\n\t\t\tbreak;\n\t\tcase 25:\n\t\t\treg_w(sd, 0xa4, 0x0c);\n\t\t\treg_w(sd, 0x23, 0x1f);\n\t\t\tbreak;\n\t\tcase 20:\n\t\t\treg_w(sd, 0xa4, 0x0c);\n\t\t\treg_w(sd, 0x23, 0x1b);\n\t\t\tbreak;\n\t\tcase 15:\n\t\t\treg_w(sd, 0xa4, 0x04);\n\t\t\treg_w(sd, 0x23, 0xff);\n\t\t\tsd->clockdiv = 1;\n\t\t\tbreak;\n\t\tcase 10:\n\t\t\treg_w(sd, 0xa4, 0x04);\n\t\t\treg_w(sd, 0x23, 0x1f);\n\t\t\tsd->clockdiv = 1;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\treg_w(sd, 0xa4, 0x04);\n\t\t\treg_w(sd, 0x23, 0x1b);\n\t\t\tsd->clockdiv = 1;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase SEN_OV8610:\n\t\tswitch (sd->frame_rate) {\n\t\tdefault:\t/* 15 fps */\n/*\t\tcase 15: */\n\t\t\treg_w(sd, 0xa4, 0x06);\n\t\t\treg_w(sd, 0x23, 0xff);\n\t\t\tbreak;\n\t\tcase 10:\n\t\t\treg_w(sd, 0xa4, 0x06);\n\t\t\treg_w(sd, 0x23, 0x1f);\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\treg_w(sd, 0xa4, 0x06);\n\t\t\treg_w(sd, 0x23, 0x1b);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase SEN_OV7670:\t\t/* guesses, based on 7640 */\n\t\tgspca_dbg(gspca_dev, D_STREAM, \"Setting framerate to %d fps\\n\",\n\t\t\t  (sd->frame_rate == 0) ? 15 : sd->frame_rate);\n\t\treg_w(sd, 0xa4, 0x10);\n\t\tswitch (sd->frame_rate) {\n\t\tcase 30:\n\t\t\treg_w(sd, 0x23, 0xff);\n\t\t\tbreak;\n\t\tcase 20:\n\t\t\treg_w(sd, 0x23, 0x1b);\n\t\t\tbreak;\n\t\tdefault:\n/*\t\tcase 15: */\n\t\t\treg_w(sd, 0x23, 0xff);\n\t\t\tsd->clockdiv = 1;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n}",
        "static void fan_resume(void)\n{\n\tu8 current_level = 7;\n\tbool do_set = false;\n\tint rc;": "static void fan_resume(void)\n{\n\tu8 current_level = 7;\n\tbool do_set = false;\n\tint rc;\n\n\t/* DSDT *always* updates status on resume */\n\ttp_features.fan_ctrl_status_undef = 0;\n\n\tif (!fan_control_allowed ||\n\t    !fan_control_resume_level ||\n\t    fan_get_status_safe(&current_level))\n\t\treturn;\n\n\tswitch (fan_control_access_mode) {\n\tcase TPACPI_FAN_WR_ACPI_SFAN:\n\t\t/* never decrease fan level */\n\t\tdo_set = (fan_control_resume_level > current_level);\n\t\tbreak;\n\tcase TPACPI_FAN_WR_ACPI_FANS:\n\tcase TPACPI_FAN_WR_TPEC:\n\t\t/* never decrease fan level, scale is:\n\t\t * TP_EC_FAN_FULLSPEED > 7 >= TP_EC_FAN_AUTO\n\t\t *\n\t\t * We expect the firmware to set either 7 or AUTO, but we\n\t\t * handle FULLSPEED out of paranoia.\n\t\t *\n\t\t * So, we can safely only restore FULLSPEED or 7, anything\n\t\t * else could slow the fan.  Restoring AUTO is useless, at\n\t\t * best that's exactly what the DSDT already set (it is the\n\t\t * slower it uses).\n\t\t *\n\t\t * Always keep in mind that the DSDT *will* have set the\n\t\t * fans to what the vendor supposes is the best level.  We\n\t\t * muck with it only to speed the fan up.\n\t\t */\n\t\tif (fan_control_resume_level != 7 &&\n\t\t    !(fan_control_resume_level & TP_EC_FAN_FULLSPEED))\n\t\t\treturn;\n\t\telse\n\t\t\tdo_set = !(current_level & TP_EC_FAN_FULLSPEED) &&\n\t\t\t\t (current_level != fan_control_resume_level);\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\tif (do_set) {\n\t\tpr_notice(\"restoring fan level to 0x%02x\\n\",\n\t\t\t  fan_control_resume_level);\n\t\trc = fan_set_level_safe(fan_control_resume_level);\n\t\tif (rc < 0)\n\t\t\tpr_notice(\"failed to restore fan level: %d\\n\", rc);\n\t}\n}",
        "static int __init scf_torture_init(void)\n{\n\tlong i;\n\tint firsterr = 0;\n\tunsigned long weight_resched1 = weight_resched;": "static int __init scf_torture_init(void)\n{\n\tlong i;\n\tint firsterr = 0;\n\tunsigned long weight_resched1 = weight_resched;\n\tunsigned long weight_single1 = weight_single;\n\tunsigned long weight_single_rpc1 = weight_single_rpc;\n\tunsigned long weight_single_wait1 = weight_single_wait;\n\tunsigned long weight_many1 = weight_many;\n\tunsigned long weight_many_wait1 = weight_many_wait;\n\tunsigned long weight_all1 = weight_all;\n\tunsigned long weight_all_wait1 = weight_all_wait;\n\n\tif (!torture_init_begin(SCFTORT_STRING, verbose))\n\t\treturn -EBUSY;\n\n\tscftorture_print_module_parms(\"Start of test\");\n\n\tif (weight_resched <= 0 &&\n\t    weight_single <= 0 && weight_single_rpc <= 0 && weight_single_wait <= 0 &&\n\t    weight_many <= 0 && weight_many_wait <= 0 &&\n\t    weight_all <= 0 && weight_all_wait <= 0) {\n\t\tweight_resched1 = weight_resched == 0 ? 0 : 2 * nr_cpu_ids;\n\t\tweight_single1 = weight_single == 0 ? 0 : 2 * nr_cpu_ids;\n\t\tweight_single_rpc1 = weight_single_rpc == 0 ? 0 : 2 * nr_cpu_ids;\n\t\tweight_single_wait1 = weight_single_wait == 0 ? 0 : 2 * nr_cpu_ids;\n\t\tweight_many1 = weight_many == 0 ? 0 : 2;\n\t\tweight_many_wait1 = weight_many_wait == 0 ? 0 : 2;\n\t\tweight_all1 = weight_all == 0 ? 0 : 1;\n\t\tweight_all_wait1 = weight_all_wait == 0 ? 0 : 1;\n\t} else {\n\t\tif (weight_resched == -1)\n\t\t\tweight_resched1 = 0;\n\t\tif (weight_single == -1)\n\t\t\tweight_single1 = 0;\n\t\tif (weight_single_rpc == -1)\n\t\t\tweight_single_rpc1 = 0;\n\t\tif (weight_single_wait == -1)\n\t\t\tweight_single_wait1 = 0;\n\t\tif (weight_many == -1)\n\t\t\tweight_many1 = 0;\n\t\tif (weight_many_wait == -1)\n\t\t\tweight_many_wait1 = 0;\n\t\tif (weight_all == -1)\n\t\t\tweight_all1 = 0;\n\t\tif (weight_all_wait == -1)\n\t\t\tweight_all_wait1 = 0;\n\t}\n\tif (weight_resched1 == 0 && weight_single1 == 0 && weight_single_rpc1 == 0 &&\n\t    weight_single_wait1 == 0 && weight_many1 == 0 && weight_many_wait1 == 0 &&\n\t    weight_all1 == 0 && weight_all_wait1 == 0) {\n\t\tSCFTORTOUT_ERRSTRING(\"all zero weights makes no sense\");\n\t\tfirsterr = -EINVAL;\n\t\tgoto unwind;\n\t}\n\tif (IS_BUILTIN(CONFIG_SCF_TORTURE_TEST))\n\t\tscf_sel_add(weight_resched1, SCF_PRIM_RESCHED, false);\n\telse if (weight_resched1)\n\t\tSCFTORTOUT_ERRSTRING(\"built as module, weight_resched ignored\");\n\tscf_sel_add(weight_single1, SCF_PRIM_SINGLE, false);\n\tscf_sel_add(weight_single_rpc1, SCF_PRIM_SINGLE_RPC, true);\n\tscf_sel_add(weight_single_wait1, SCF_PRIM_SINGLE, true);\n\tscf_sel_add(weight_many1, SCF_PRIM_MANY, false);\n\tscf_sel_add(weight_many_wait1, SCF_PRIM_MANY, true);\n\tscf_sel_add(weight_all1, SCF_PRIM_ALL, false);\n\tscf_sel_add(weight_all_wait1, SCF_PRIM_ALL, true);\n\tscf_sel_dump();\n\n\tif (onoff_interval > 0) {\n\t\tfirsterr = torture_onoff_init(onoff_holdoff * HZ, onoff_interval, NULL);\n\t\tif (torture_init_error(firsterr))\n\t\t\tgoto unwind;\n\t}\n\tif (shutdown_secs > 0) {\n\t\tfirsterr = torture_shutdown_init(shutdown_secs, scf_torture_cleanup);\n\t\tif (torture_init_error(firsterr))\n\t\t\tgoto unwind;\n\t}\n\tif (stutter > 0) {\n\t\tfirsterr = torture_stutter_init(stutter, stutter);\n\t\tif (torture_init_error(firsterr))\n\t\t\tgoto unwind;\n\t}\n\n\t// Worker tasks invoking smp_call_function().\n\tif (nthreads < 0)\n\t\tnthreads = num_online_cpus();\n\tscf_stats_p = kcalloc(nthreads, sizeof(scf_stats_p[0]), GFP_KERNEL);\n\tif (!scf_stats_p) {\n\t\tSCFTORTOUT_ERRSTRING(\"out of memory\");\n\t\tfirsterr = -ENOMEM;\n\t\tgoto unwind;\n\t}\n\n\tVERBOSE_SCFTORTOUT(\"Starting %d smp_call_function() threads\", nthreads);\n\n\tatomic_set(&n_started, nthreads);\n\tfor (i = 0; i < nthreads; i++) {\n\t\tscf_stats_p[i].cpu = i;\n\t\tfirsterr = torture_create_kthread(scftorture_invoker, (void *)&scf_stats_p[i],\n\t\t\t\t\t\t  scf_stats_p[i].task);\n\t\tif (torture_init_error(firsterr))\n\t\t\tgoto unwind;\n\t}\n\tif (stat_interval > 0) {\n\t\tfirsterr = torture_create_kthread(scf_torture_stats, NULL, scf_torture_stats_task);\n\t\tif (torture_init_error(firsterr))\n\t\t\tgoto unwind;\n\t}\n\n\ttorture_init_end();\n\treturn 0;\n\nunwind:\n\ttorture_init_end();\n\tscf_torture_cleanup();\n\tif (shutdown_secs) {\n\t\tWARN_ON(!IS_MODULE(CONFIG_SCF_TORTURE_TEST));\n\t\tkernel_power_off();\n\t}\n\treturn firsterr;\n}",
        "static void test_tc_redirect_neigh_fib(struct netns_setup_result *setup_result)\n{\n\tstruct nstoken *nstoken = NULL;\n\tstruct test_tc_neigh_fib *skel = NULL;\n\tint err;": "static void test_tc_redirect_neigh_fib(struct netns_setup_result *setup_result)\n{\n\tstruct nstoken *nstoken = NULL;\n\tstruct test_tc_neigh_fib *skel = NULL;\n\tint err;\n\n\tnstoken = open_netns(NS_FWD);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns fwd\"))\n\t\treturn;\n\n\tskel = test_tc_neigh_fib__open();\n\tif (!ASSERT_OK_PTR(skel, \"test_tc_neigh_fib__open\"))\n\t\tgoto done;\n\n\tif (!ASSERT_OK(test_tc_neigh_fib__load(skel), \"test_tc_neigh_fib__load\"))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_src, SRC_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" SRC_PROG_PIN_FILE))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_chk, CHK_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" CHK_PROG_PIN_FILE))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_dst, DST_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" DST_PROG_PIN_FILE))\n\t\tgoto done;\n\n\tif (netns_load_bpf())\n\t\tgoto done;\n\n\t/* bpf_fib_lookup() checks if forwarding is enabled */\n\tif (!ASSERT_OK(set_forwarding(true), \"enable forwarding\"))\n\t\tgoto done;\n\n\ttest_connectivity();\n\ndone:\n\tif (skel)\n\t\ttest_tc_neigh_fib__destroy(skel);\n\tclose_netns(nstoken);\n}",
        "static int execute_one_variant(bool legacy)\n{\n\tstruct test_legacy_printk *skel;\n\tint err, zero = 0, my_pid = getpid(), res, map_fd;\n": "static int execute_one_variant(bool legacy)\n{\n\tstruct test_legacy_printk *skel;\n\tint err, zero = 0, my_pid = getpid(), res, map_fd;\n\n\tskel = test_legacy_printk__open();\n\tif (!ASSERT_OK_PTR(skel, \"skel_open\"))\n\t\treturn -errno;\n\n\tbpf_program__set_autoload(skel->progs.handle_legacy, legacy);\n\tbpf_program__set_autoload(skel->progs.handle_modern, !legacy);\n\n\terr = test_legacy_printk__load(skel);\n\t/* no ASSERT_OK, we expect one of two variants can fail here */\n\tif (err)\n\t\tgoto err_out;\n\n\tif (legacy) {\n\t\tmap_fd = bpf_map__fd(skel->maps.my_pid_map);\n\t\terr = bpf_map_update_elem(map_fd, &zero, &my_pid, BPF_ANY);\n\t\tif (!ASSERT_OK(err, \"my_pid_map_update\"))\n\t\t\tgoto err_out;\n\t\terr = bpf_map_lookup_elem(map_fd, &zero, &res);\n\t} else {\n\t\tskel->bss->my_pid_var = my_pid;\n\t}\n\n\terr = test_legacy_printk__attach(skel);\n\tif (!ASSERT_OK(err, \"skel_attach\"))\n\t\tgoto err_out;\n\n\tusleep(1); /* trigger */\n\n\tif (legacy) {\n\t\tmap_fd = bpf_map__fd(skel->maps.res_map);\n\t\terr = bpf_map_lookup_elem(map_fd, &zero, &res);\n\t\tif (!ASSERT_OK(err, \"res_map_lookup\"))\n\t\t\tgoto err_out;\n\t} else {\n\t\tres = skel->bss->res_var;\n\t}\n\n\tif (!ASSERT_GT(res, 0, \"res\")) {\n\t\terr = -EINVAL;\n\t\tgoto err_out;\n\t}\n\nerr_out:\n\ttest_legacy_printk__destroy(skel);\n\treturn err;\n}",
        "static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)\n{\n\tint no_signal, lock = 0;\n\ts32 cpt_step = 0, offst_freq, car_max;\n\tu32 reg;": "static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)\n{\n\tint no_signal, lock = 0;\n\ts32 cpt_step = 0, offst_freq, car_max;\n\tu32 reg;\n\n\tcar_max  = state->search_range / 1000;\n\tcar_max += (car_max / 10);\n\tcar_max  = (65536 * car_max / 2);\n\tcar_max /= (state->internal->mclk / 1000);\n\tif (car_max > 0x4000)\n\t\tcar_max = 0x4000;\n\n\tif (zigzag)\n\t\toffst_freq = 0;\n\telse\n\t\toffst_freq = -car_max + inc;\n\n\tdo {\n\t\tif (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)\n\t\t\tgoto err;\n\t\tif (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)\n\t\t\tgoto err;\n\t\tif (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)\n\t\t\tgoto err;\n\t\tif (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)\n\t\t\tgoto err;\n\n\t\treg = STV090x_READ_DEMOD(state, PDELCTRL1);\n\t\tSTV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */\n\t\tif (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)\n\t\t\tgoto err;\n\n\t\tif (zigzag) {\n\t\t\tif (offst_freq >= 0)\n\t\t\t\toffst_freq = -offst_freq - 2 * inc;\n\t\t\telse\n\t\t\t\toffst_freq = -offst_freq;\n\t\t} else {\n\t\t\toffst_freq += 2 * inc;\n\t\t}\n\n\t\tcpt_step++;\n\n\t\tlock = stv090x_get_dmdlock(state, timeout);\n\t\tno_signal = stv090x_chk_signal(state);\n\n\t} while ((!lock) &&\n\t\t (!no_signal) &&\n\t\t  ((offst_freq - inc) < car_max) &&\n\t\t  ((offst_freq + inc) > -car_max) &&\n\t\t  (cpt_step < steps_max));\n\n\treg = STV090x_READ_DEMOD(state, PDELCTRL1);\n\tSTV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);\n\tif (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)\n\t\t\tgoto err;\n\n\treturn lock;\nerr:\n\tdprintk(FE_ERROR, 1, \"I/O error\");\n\treturn -1;\n}",
        "static int admv4420_calc_parameters(struct admv4420_state *st)\n{\n\tu64 pfd_ref, pfd_vco;\n\tbool sol_found = false;\n": "static int admv4420_calc_parameters(struct admv4420_state *st)\n{\n\tu64 pfd_ref, pfd_vco;\n\tbool sol_found = false;\n\n\tst->ref_block.doubler_en = false;\n\tst->ref_block.divide_by_2_en = false;\n\tst->vco_freq_hz = div_u64(st->lo_freq_hz, 2);\n\n\tfor (st->ref_block.divider = 1; st->ref_block.divider < MAX_R_DIVIDER;\n\t    st->ref_block.divider++) {\n\t\tpfd_ref = admv4420_calc_pfd_ref(st);\n\t\tfor (st->n_counter.n_counter = 1; st->n_counter.n_counter < MAX_N_COUNTER;\n\t\t    st->n_counter.n_counter++) {\n\t\t\tpfd_vco = admv4420_calc_pfd_vco(st);\n\t\t\tif (pfd_ref == pfd_vco) {\n\t\t\t\tsol_found = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (sol_found)\n\t\t\tbreak;\n\n\t\tst->n_counter.n_counter = 1;\n\t}\n\tif (!sol_found)\n\t\treturn -1;\n\n\tst->n_counter.int_val = div_u64_rem(st->n_counter.n_counter, 10, &st->n_counter.frac_val);\n\tst->n_counter.mod_val = 10;\n\n\treturn 0;\n}",
        "static int ad7292_vin_range_multiplier(struct ad7292_state *st, int channel)\n{\n\tint samp_mode, range0, range1, factor = 1;\n\n\t/*": "static int ad7292_vin_range_multiplier(struct ad7292_state *st, int channel)\n{\n\tint samp_mode, range0, range1, factor = 1;\n\n\t/*\n\t * Every AD7292 ADC channel may have its input range adjusted according\n\t * to the settings at the ADC sampling mode and VIN range subregisters.\n\t * For a given channel, the minimum input range is equal to Vref, and it\n\t * may be increased by a multiplier factor of 2 or 4 according to the\n\t * following rule:\n\t * If channel is being sampled with respect to AGND:\n\t *\tfactor = 4 if VIN range0 and VIN range1 equal 0\n\t *\tfactor = 2 if only one of VIN ranges equal 1\n\t *\tfactor = 1 if both VIN range0 and VIN range1 equal 1\n\t * If channel is being sampled with respect to AVDD:\n\t *\tfactor = 4 if VIN range0 and VIN range1 equal 0\n\t *\tBehavior is undefined if any of VIN range doesn't equal 0\n\t */\n\n\tsamp_mode = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,\n\t\t\t\t\t   AD7292_BANK_REG_SAMP_MODE, 2);\n\n\tif (samp_mode < 0)\n\t\treturn samp_mode;\n\n\trange0 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,\n\t\t\t\t\tAD7292_BANK_REG_VIN_RNG0, 2);\n\n\tif (range0 < 0)\n\t\treturn range0;\n\n\trange1 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,\n\t\t\t\t\tAD7292_BANK_REG_VIN_RNG1, 2);\n\n\tif (range1 < 0)\n\t\treturn range1;\n\n\tif (AD7292_CH_SAMP_MODE(samp_mode, channel)) {\n\t\t/* Sampling with respect to AGND */\n\t\tif (!AD7292_CH_VIN_RANGE(range0, channel))\n\t\t\tfactor *= 2;\n\n\t\tif (!AD7292_CH_VIN_RANGE(range1, channel))\n\t\t\tfactor *= 2;\n\n\t} else {\n\t\t/* Sampling with respect to AVDD */\n\t\tif (AD7292_CH_VIN_RANGE(range0, channel) ||\n\t\t    AD7292_CH_VIN_RANGE(range1, channel))\n\t\t\treturn -EPERM;\n\n\t\tfactor = 4;\n\t}\n\n\treturn factor;\n}",
        "static int test_process_multi_same_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, same addr\";": "static int test_process_multi_same_addr(void)\n{\n\tunsigned long long breaks1 = 0, breaks2 = 0;\n\tint fd1, fd2;\n\tchar *desc = \"Process specific, Two events, same addr\";\n\tsize_t res;\n\n\tfd1 = perf_process_event_open(HW_BREAKPOINT_RW, (__u64)&a, (__u64)sizeof(a));\n\tif (fd1 < 0) {\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tfd2 = perf_process_event_open(HW_BREAKPOINT_RW, (__u64)&a, (__u64)sizeof(a));\n\tif (fd2 < 0) {\n\t\tclose(fd1);\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tioctl(fd1, PERF_EVENT_IOC_RESET);\n\tioctl(fd2, PERF_EVENT_IOC_RESET);\n\tioctl(fd1, PERF_EVENT_IOC_ENABLE);\n\tioctl(fd2, PERF_EVENT_IOC_ENABLE);\n\tmulti_dawr_workload();\n\tioctl(fd1, PERF_EVENT_IOC_DISABLE);\n\tioctl(fd2, PERF_EVENT_IOC_DISABLE);\n\n\tres = read(fd1, &breaks1, sizeof(breaks1));\n\tassert(res == sizeof(unsigned long long));\n\tres = read(fd2, &breaks2, sizeof(breaks2));\n\tassert(res == sizeof(unsigned long long));\n\n\tclose(fd1);\n\tclose(fd2);\n\n\tif (breaks1 != 2 || breaks2 != 2) {\n\t\tprintf(\"FAILED: %s: %lld != 2 || %lld != 2\\n\", desc, breaks1, breaks2);\n\t\treturn 1;\n\t}\n\n\tprintf(\"TESTED: %s\\n\", desc);\n\treturn 0;\n}",
        "static inline bool page_copy_sane(struct page *page, size_t offset, size_t n)\n{\n\tstruct page *head;\n\tsize_t v = n + offset;\n": "static inline bool page_copy_sane(struct page *page, size_t offset, size_t n)\n{\n\tstruct page *head;\n\tsize_t v = n + offset;\n\n\t/*\n\t * The general case needs to access the page order in order\n\t * to compute the page size.\n\t * However, we mostly deal with order-0 pages and thus can\n\t * avoid a possible cache line miss for requests that fit all\n\t * page orders.\n\t */\n\tif (n <= v && v <= PAGE_SIZE)\n\t\treturn true;\n\n\thead = compound_head(page);\n\tv += (page - head) << PAGE_SHIFT;\n\n\tif (likely(n <= v && v <= (page_size(head))))\n\t\treturn true;\n\tWARN_ON(1);\n\treturn false;\n}",
        "static bool wcd_mbhc_check_for_spl_headset(struct wcd_mbhc *mbhc)\n{\n\tbool is_spl_hs = false;\n\tint output_mv, hs_threshold, hph_threshold;\n": "static bool wcd_mbhc_check_for_spl_headset(struct wcd_mbhc *mbhc)\n{\n\tbool is_spl_hs = false;\n\tint output_mv, hs_threshold, hph_threshold;\n\n\tif (!mbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic)\n\t\treturn false;\n\n\t/* Bump up MIC_BIAS2 to 2.7V */\n\tmbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic(mbhc->component, MIC_BIAS_2, true);\n\tusleep_range(10000, 10100);\n\n\toutput_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);\n\ths_threshold = wcd_mbhc_get_spl_hs_thres(mbhc);\n\thph_threshold = wcd_mbhc_adc_get_hph_thres(mbhc);\n\n\tif (!(output_mv > hs_threshold || output_mv < hph_threshold))\n\t\tis_spl_hs = true;\n\n\t/* Back MIC_BIAS2 to 1.8v if the type is not special headset */\n\tif (!is_spl_hs) {\n\t\tmbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic(mbhc->component, MIC_BIAS_2, false);\n\t\t/* Add 10ms delay for micbias to settle */\n\t\tusleep_range(10000, 10100);\n\t}\n\n\treturn is_spl_hs;\n}",
        "static int virtio_mem_init_hotplug(struct virtio_mem *vm)\n{\n\tconst struct range pluggable_range = mhp_get_pluggable_range(true);\n\tuint64_t unit_pages, sb_size, addr;\n\tint rc;": "static int virtio_mem_init_hotplug(struct virtio_mem *vm)\n{\n\tconst struct range pluggable_range = mhp_get_pluggable_range(true);\n\tuint64_t unit_pages, sb_size, addr;\n\tint rc;\n\n\t/* bad device setup - warn only */\n\tif (!IS_ALIGNED(vm->addr, memory_block_size_bytes()))\n\t\tdev_warn(&vm->vdev->dev,\n\t\t\t \"The alignment of the physical start address can make some memory unusable.\\n\");\n\tif (!IS_ALIGNED(vm->addr + vm->region_size, memory_block_size_bytes()))\n\t\tdev_warn(&vm->vdev->dev,\n\t\t\t \"The alignment of the physical end address can make some memory unusable.\\n\");\n\tif (vm->addr < pluggable_range.start ||\n\t    vm->addr + vm->region_size - 1 > pluggable_range.end)\n\t\tdev_warn(&vm->vdev->dev,\n\t\t\t \"Some device memory is not addressable/pluggable. This can make some memory unusable.\\n\");\n\n\t/* Prepare the offline threshold - make sure we can add two blocks. */\n\tvm->offline_threshold = max_t(uint64_t, 2 * memory_block_size_bytes(),\n\t\t\t\t      VIRTIO_MEM_DEFAULT_OFFLINE_THRESHOLD);\n\n\t/*\n\t * alloc_contig_range() works reliably with pageblock\n\t * granularity on ZONE_NORMAL, use pageblock_nr_pages.\n\t */\n\tsb_size = PAGE_SIZE * pageblock_nr_pages;\n\tsb_size = max_t(uint64_t, vm->device_block_size, sb_size);\n\n\tif (sb_size < memory_block_size_bytes() && !force_bbm) {\n\t\t/* SBM: At least two subblocks per Linux memory block. */\n\t\tvm->in_sbm = true;\n\t\tvm->sbm.sb_size = sb_size;\n\t\tvm->sbm.sbs_per_mb = memory_block_size_bytes() /\n\t\t\t\t     vm->sbm.sb_size;\n\n\t\t/* Round up to the next full memory block */\n\t\taddr = max_t(uint64_t, vm->addr, pluggable_range.start) +\n\t\t       memory_block_size_bytes() - 1;\n\t\tvm->sbm.first_mb_id = virtio_mem_phys_to_mb_id(addr);\n\t\tvm->sbm.next_mb_id = vm->sbm.first_mb_id;\n\t} else {\n\t\t/* BBM: At least one Linux memory block. */\n\t\tvm->bbm.bb_size = max_t(uint64_t, vm->device_block_size,\n\t\t\t\t\tmemory_block_size_bytes());\n\n\t\tif (bbm_block_size) {\n\t\t\tif (!is_power_of_2(bbm_block_size)) {\n\t\t\t\tdev_warn(&vm->vdev->dev,\n\t\t\t\t\t \"bbm_block_size is not a power of 2\");\n\t\t\t} else if (bbm_block_size < vm->bbm.bb_size) {\n\t\t\t\tdev_warn(&vm->vdev->dev,\n\t\t\t\t\t \"bbm_block_size is too small\");\n\t\t\t} else {\n\t\t\t\tvm->bbm.bb_size = bbm_block_size;\n\t\t\t}\n\t\t}\n\n\t\t/* Round up to the next aligned big block */\n\t\taddr = max_t(uint64_t, vm->addr, pluggable_range.start) +\n\t\t       vm->bbm.bb_size - 1;\n\t\tvm->bbm.first_bb_id = virtio_mem_phys_to_bb_id(vm, addr);\n\t\tvm->bbm.next_bb_id = vm->bbm.first_bb_id;\n\n\t\t/* Make sure we can add two big blocks. */\n\t\tvm->offline_threshold = max_t(uint64_t, 2 * vm->bbm.bb_size,\n\t\t\t\t\t      vm->offline_threshold);\n\t}\n\n\tdev_info(&vm->vdev->dev, \"memory block size: 0x%lx\",\n\t\t memory_block_size_bytes());\n\tif (vm->in_sbm)\n\t\tdev_info(&vm->vdev->dev, \"subblock size: 0x%llx\",\n\t\t\t (unsigned long long)vm->sbm.sb_size);\n\telse\n\t\tdev_info(&vm->vdev->dev, \"big block size: 0x%llx\",\n\t\t\t (unsigned long long)vm->bbm.bb_size);\n\n\t/* create the parent resource for all memory */\n\trc = virtio_mem_create_resource(vm);\n\tif (rc)\n\t\treturn rc;\n\n\t/* use a single dynamic memory group to cover the whole memory device */\n\tif (vm->in_sbm)\n\t\tunit_pages = PHYS_PFN(memory_block_size_bytes());\n\telse\n\t\tunit_pages = PHYS_PFN(vm->bbm.bb_size);\n\trc = memory_group_register_dynamic(vm->nid, unit_pages);\n\tif (rc < 0)\n\t\tgoto out_del_resource;\n\tvm->mgid = rc;\n\n\t/*\n\t * If we still have memory plugged, we have to unplug all memory first.\n\t * Registering our parent resource makes sure that this memory isn't\n\t * actually in use (e.g., trying to reload the driver).\n\t */\n\tif (vm->plugged_size) {\n\t\tvm->unplug_all_required = true;\n\t\tdev_info(&vm->vdev->dev, \"unplugging all memory is required\\n\");\n\t}\n\n\t/* register callbacks */\n\tvm->memory_notifier.notifier_call = virtio_mem_memory_notifier_cb;\n\trc = register_memory_notifier(&vm->memory_notifier);\n\tif (rc)\n\t\tgoto out_unreg_group;\n\trc = register_virtio_mem_device(vm);\n\tif (rc)\n\t\tgoto out_unreg_mem;\n\n\treturn 0;\nout_unreg_mem:\n\tunregister_memory_notifier(&vm->memory_notifier);\nout_unreg_group:\n\tmemory_group_unregister(vm->mgid);\nout_del_resource:\n\tvirtio_mem_delete_resource(vm);\n\treturn rc;\n}",
        "static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)\n{\n\tu32 arm_gpio_lock_val;\n\n\tmutex_lock(yu_arm_gpio_lock_param.lock);": "static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)\n{\n\tu32 arm_gpio_lock_val;\n\n\tmutex_lock(yu_arm_gpio_lock_param.lock);\n\traw_spin_lock(&gs->gc.bgpio_lock);\n\n\tarm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);\n\n\t/*\n\t * When lock active bit[31] is set, ModeX is write enabled\n\t */\n\tif (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {\n\t\traw_spin_unlock(&gs->gc.bgpio_lock);\n\t\tmutex_unlock(yu_arm_gpio_lock_param.lock);\n\t\treturn -EINVAL;\n\t}\n\n\twritel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);\n\n\treturn 0;\n}",
        "static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)\n{\n\tunsigned int ad;\n\n\tif (addr >= HDSP_MATRIX_MIXER_SIZE)": "static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)\n{\n\tunsigned int ad;\n\n\tif (addr >= HDSP_MATRIX_MIXER_SIZE)\n\t\treturn -1;\n\n\tif (hdsp->io_type == H9652 || hdsp->io_type == H9632) {\n\n\t\t/* from martin bjornsen:\n\n\t\t   \"You can only write dwords to the\n\t\t   mixer memory which contain two\n\t\t   mixer values in the low and high\n\t\t   word. So if you want to change\n\t\t   value 0 you have to read value 1\n\t\t   from the cache and write both to\n\t\t   the first dword in the mixer\n\t\t   memory.\"\n\t\t*/\n\n\t\tif (hdsp->io_type == H9632 && addr >= 512)\n\t\t\treturn 0;\n\n\t\tif (hdsp->io_type == H9652 && addr >= 1352)\n\t\t\treturn 0;\n\n\t\thdsp->mixer_matrix[addr] = data;\n\n\n\t\t/* `addr' addresses a 16-bit wide address, but\n\t\t   the address space accessed via hdsp_write\n\t\t   uses byte offsets. put another way, addr\n\t\t   varies from 0 to 1351, but to access the\n\t\t   corresponding memory location, we need\n\t\t   to access 0 to 2703 ...\n\t\t*/\n\t\tad = addr/2;\n\n\t\thdsp_write (hdsp, 4096 + (ad*4),\n\t\t\t    (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +\n\t\t\t    hdsp->mixer_matrix[addr&0x7fe]);\n\n\t\treturn 0;\n\n\t} else {\n\n\t\tad = (addr << 16) + data;\n\n\t\tif (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))\n\t\t\treturn -1;\n\n\t\thdsp_write (hdsp, HDSP_fifoData, ad);\n\t\thdsp->mixer_matrix[addr] = data;\n\n\t}\n\n\treturn 0;\n}",
        "static int spinand_ondie_ecc_init_ctx(struct nand_device *nand)\n{\n\tstruct spinand_device *spinand = nand_to_spinand(nand);\n\tstruct mtd_info *mtd = nanddev_to_mtd(nand);\n\tstruct spinand_ondie_ecc_conf *engine_conf;": "static int spinand_ondie_ecc_init_ctx(struct nand_device *nand)\n{\n\tstruct spinand_device *spinand = nand_to_spinand(nand);\n\tstruct mtd_info *mtd = nanddev_to_mtd(nand);\n\tstruct spinand_ondie_ecc_conf *engine_conf;\n\n\tnand->ecc.ctx.conf.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE;\n\tnand->ecc.ctx.conf.step_size = nand->ecc.requirements.step_size;\n\tnand->ecc.ctx.conf.strength = nand->ecc.requirements.strength;\n\n\tengine_conf = kzalloc(sizeof(*engine_conf), GFP_KERNEL);\n\tif (!engine_conf)\n\t\treturn -ENOMEM;\n\n\tnand->ecc.ctx.priv = engine_conf;\n\n\tif (spinand->eccinfo.ooblayout)\n\t\tmtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);\n\telse\n\t\tmtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);\n\n\treturn 0;\n}",
        "static void check_preempt_wakeup(struct rq *rq, struct task_struct *p, int wake_flags)\n{\n\tstruct task_struct *curr = rq->curr;\n\tstruct sched_entity *se = &curr->se, *pse = &p->se;\n\tstruct cfs_rq *cfs_rq = task_cfs_rq(curr);": "static void check_preempt_wakeup(struct rq *rq, struct task_struct *p, int wake_flags)\n{\n\tstruct task_struct *curr = rq->curr;\n\tstruct sched_entity *se = &curr->se, *pse = &p->se;\n\tstruct cfs_rq *cfs_rq = task_cfs_rq(curr);\n\tint scale = cfs_rq->nr_running >= sched_nr_latency;\n\tint next_buddy_marked = 0;\n\tint cse_is_idle, pse_is_idle;\n\n\tif (unlikely(se == pse))\n\t\treturn;\n\n\t/*\n\t * This is possible from callers such as attach_tasks(), in which we\n\t * unconditionally check_preempt_curr() after an enqueue (which may have\n\t * lead to a throttle).  This both saves work and prevents false\n\t * next-buddy nomination below.\n\t */\n\tif (unlikely(throttled_hierarchy(cfs_rq_of(pse))))\n\t\treturn;\n\n\tif (sched_feat(NEXT_BUDDY) && scale && !(wake_flags & WF_FORK)) {\n\t\tset_next_buddy(pse);\n\t\tnext_buddy_marked = 1;\n\t}\n\n\t/*\n\t * We can come here with TIF_NEED_RESCHED already set from new task\n\t * wake up path.\n\t *\n\t * Note: this also catches the edge-case of curr being in a throttled\n\t * group (e.g. via set_curr_task), since update_curr() (in the\n\t * enqueue of curr) will have resulted in resched being set.  This\n\t * prevents us from potentially nominating it as a false LAST_BUDDY\n\t * below.\n\t */\n\tif (test_tsk_need_resched(curr))\n\t\treturn;\n\n\t/* Idle tasks are by definition preempted by non-idle tasks. */\n\tif (unlikely(task_has_idle_policy(curr)) &&\n\t    likely(!task_has_idle_policy(p)))\n\t\tgoto preempt;\n\n\t/*\n\t * Batch and idle tasks do not preempt non-idle tasks (their preemption\n\t * is driven by the tick):\n\t */\n\tif (unlikely(p->policy != SCHED_NORMAL) || !sched_feat(WAKEUP_PREEMPTION))\n\t\treturn;\n\n\tfind_matching_se(&se, &pse);\n\tBUG_ON(!pse);\n\n\tcse_is_idle = se_is_idle(se);\n\tpse_is_idle = se_is_idle(pse);\n\n\t/*\n\t * Preempt an idle group in favor of a non-idle group (and don't preempt\n\t * in the inverse case).\n\t */\n\tif (cse_is_idle && !pse_is_idle)\n\t\tgoto preempt;\n\tif (cse_is_idle != pse_is_idle)\n\t\treturn;\n\n\tupdate_curr(cfs_rq_of(se));\n\tif (wakeup_preempt_entity(se, pse) == 1) {\n\t\t/*\n\t\t * Bias pick_next to pick the sched entity that is\n\t\t * triggering this preemption.\n\t\t */\n\t\tif (!next_buddy_marked)\n\t\t\tset_next_buddy(pse);\n\t\tgoto preempt;\n\t}\n\n\treturn;\n\npreempt:\n\tresched_curr(rq);\n\t/*\n\t * Only set the backward buddy when the current task is still\n\t * on the rq. This can happen when a wakeup gets interleaved\n\t * with schedule on the ->pre_schedule() or idle_balance()\n\t * point, either of which can * drop the rq lock.\n\t *\n\t * Also, during early boot the idle thread is in the fair class,\n\t * for obvious reasons its a bad idea to schedule back to it.\n\t */\n\tif (unlikely(!se->on_rq || curr == rq->idle))\n\t\treturn;\n\n\tif (sched_feat(LAST_BUDDY) && scale && entity_is_task(se))\n\t\tset_last_buddy(se);\n}",
        "static int rvu_switch_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry)\n{\n\tstruct npc_install_flow_req req = { 0 };\n\tstruct npc_install_flow_rsp rsp = { 0 };\n\tstruct rvu_pfvf *pfvf;": "static int rvu_switch_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry)\n{\n\tstruct npc_install_flow_req req = { 0 };\n\tstruct npc_install_flow_rsp rsp = { 0 };\n\tstruct rvu_pfvf *pfvf;\n\tu8 lbkid;\n\n\tpfvf = rvu_get_pfvf(rvu, pcifunc);\n\t/* If the pcifunc is not initialized then nothing to do.\n\t * This same function will be called again via rvu_switch_update_rules\n\t * after pcifunc is initialized.\n\t */\n\tif (!test_bit(NIXLF_INITIALIZED, &pfvf->flags))\n\t\treturn 0;\n\n\tlbkid = pfvf->nix_blkaddr == BLKADDR_NIX0 ? 0 : 1;\n\tether_addr_copy(req.packet.dmac, pfvf->mac_addr);\n\teth_broadcast_addr((u8 *)&req.mask.dmac);\n\treq.hdr.pcifunc = 0; /* AF is requester */\n\treq.vf = pcifunc;\n\treq.entry = entry;\n\treq.features = BIT_ULL(NPC_DMAC);\n\treq.intf = pfvf->nix_tx_intf;\n\treq.op = NIX_TX_ACTIONOP_UCAST_CHAN;\n\treq.index = (lbkid << 8) | RVU_SWITCH_LBK_CHAN;\n\treq.set_cntr = 1;\n\n\treturn rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);\n}",
        "static void cache_seq(struct amdtp_stream *s, const struct pkt_desc *descs, unsigned int desc_count)\n{\n\tconst unsigned int transfer_delay = s->transfer_delay;\n\tconst unsigned int cache_size = s->ctx_data.tx.cache.size;\n\tstruct seq_desc *cache = s->ctx_data.tx.cache.descs;": "static void cache_seq(struct amdtp_stream *s, const struct pkt_desc *descs, unsigned int desc_count)\n{\n\tconst unsigned int transfer_delay = s->transfer_delay;\n\tconst unsigned int cache_size = s->ctx_data.tx.cache.size;\n\tstruct seq_desc *cache = s->ctx_data.tx.cache.descs;\n\tunsigned int cache_tail = s->ctx_data.tx.cache.tail;\n\tbool aware_syt = !(s->flags & CIP_UNAWARE_SYT);\n\tint i;\n\n\tfor (i = 0; i < desc_count; ++i) {\n\t\tstruct seq_desc *dst = cache + cache_tail;\n\t\tconst struct pkt_desc *src = descs + i;\n\n\t\tif (aware_syt && src->syt != CIP_SYT_NO_INFO)\n\t\t\tdst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay);\n\t\telse\n\t\t\tdst->syt_offset = CIP_SYT_NO_INFO;\n\t\tdst->data_blocks = src->data_blocks;\n\n\t\tcache_tail = (cache_tail + 1) % cache_size;\n\t}\n\n\ts->ctx_data.tx.cache.tail = cache_tail;\n}",
        "static void test_pcpu_lru_map_init(void)\n{\n\tpcpu_map_value_t value[nr_cpus];\n\tstruct test_map_init *skel;\n\tint map_fd, err;": "static void test_pcpu_lru_map_init(void)\n{\n\tpcpu_map_value_t value[nr_cpus];\n\tstruct test_map_init *skel;\n\tint map_fd, err;\n\tmap_key_t key;\n\n\t/* Set up LRU map with 2 elements, values filled for all CPUs.\n\t * With these 2 elements, the LRU map is full\n\t */\n\tskel = setup(BPF_MAP_TYPE_LRU_PERCPU_HASH, 2, &map_fd, 2);\n\tif (!ASSERT_OK_PTR(skel, \"prog_setup\"))\n\t\treturn;\n\n\t/* run bpf prog that inserts new key=3 element, re-using LRU slot */\n\tkey = 3;\n\terr = prog_run_insert_elem(skel, key, TEST_VALUE);\n\tif (!ASSERT_OK(err, \"prog_run_insert_elem\"))\n\t\tgoto cleanup;\n\n\t/* check that key=3 replaced one of earlier elements */\n\terr = bpf_map_lookup_elem(map_fd, &key, value);\n\tif (!ASSERT_OK(err, \"bpf_map_lookup_elem\"))\n\t\tgoto cleanup;\n\n\t/* and has expected values */\n\tcheck_values_one_cpu(value, TEST_VALUE);\n\ncleanup:\n\ttest_map_init__destroy(skel);\n}",
        "static void ktd2692_expresswire_set_bit(struct ktd2692_context *led, bool bit)\n{\n\t/*\n\t * The Low Bit(0) and High Bit(1) is based on a time detection\n\t * algorithm between time low and time high": "static void ktd2692_expresswire_set_bit(struct ktd2692_context *led, bool bit)\n{\n\t/*\n\t * The Low Bit(0) and High Bit(1) is based on a time detection\n\t * algorithm between time low and time high\n\t * Time_(L_LB) : Low time of the Low Bit(0)\n\t * Time_(H_LB) : High time of the LOW Bit(0)\n\t * Time_(L_HB) : Low time of the High Bit(1)\n\t * Time_(H_HB) : High time of the High Bit(1)\n\t *\n\t * It can be simplified to:\n\t * Low Bit(0) : 2 * Time_(H_LB) < Time_(L_LB)\n\t * High Bit(1) : 2 * Time_(L_HB) < Time_(H_HB)\n\t * HIGH  ___           ____    _..     _________    ___\n\t *          |_________|    |_..  |____|         |__|\n\t * LOW        <L_LB>  <H_LB>     <L_HB>  <H_HB>\n\t *          [  Low Bit (0) ]     [  High Bit(1) ]\n\t */\n\tif (bit) {\n\t\tgpiod_direction_output(led->ctrl_gpio, KTD2692_LOW);\n\t\tudelay(KTD2692_TIME_SHORT_BITSET_US);\n\t\tgpiod_direction_output(led->ctrl_gpio, KTD2692_HIGH);\n\t\tudelay(KTD2692_TIME_LONG_BITSET_US);\n\t} else {\n\t\tgpiod_direction_output(led->ctrl_gpio, KTD2692_LOW);\n\t\tudelay(KTD2692_TIME_LONG_BITSET_US);\n\t\tgpiod_direction_output(led->ctrl_gpio, KTD2692_HIGH);\n\t\tudelay(KTD2692_TIME_SHORT_BITSET_US);\n\t}\n}",
        "static int grand_child_f(unsigned int nr, int cmd_fd, void *buf)\n{\n\tstruct test_desc msg;\n\tint xfrm_sock = -1;\n\tuint32_t seq;": "static int grand_child_f(unsigned int nr, int cmd_fd, void *buf)\n{\n\tstruct test_desc msg;\n\tint xfrm_sock = -1;\n\tuint32_t seq;\n\n\tif (switch_ns(nsfd_childb))\n\t\texit(KSFT_FAIL);\n\n\tif (netlink_sock(&xfrm_sock, &seq, NETLINK_XFRM)) {\n\t\tprintk(\"Failed to open xfrm netlink socket\");\n\t\texit(KSFT_FAIL);\n\t}\n\n\tdo {\n\t\tread_msg(cmd_fd, &msg, 1);\n\t\tgrand_child_serv(nr, cmd_fd, buf, &msg, xfrm_sock, &seq);\n\t} while (1);\n\n\tclose(xfrm_sock);\n\texit(KSFT_FAIL);\n}",
        "static int check_file_memory_mapping(int mem_type, int mode, int mapping, int tag_check)\n{\n\tchar *ptr, *map_ptr;\n\tint run, fd, map_size;\n\tint total = sizeof(sizes)/sizeof(int);": "static int check_file_memory_mapping(int mem_type, int mode, int mapping, int tag_check)\n{\n\tchar *ptr, *map_ptr;\n\tint run, fd, map_size;\n\tint total = sizeof(sizes)/sizeof(int);\n\tint result = KSFT_PASS;\n\n\tmte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG);\n\tfor (run = 0; run < total; run++) {\n\t\tfd = create_temp_file();\n\t\tif (fd == -1)\n\t\t\treturn KSFT_FAIL;\n\n\t\tmap_size = sizes[run] + UNDERFLOW + OVERFLOW;\n\t\tmap_ptr = (char *)mte_allocate_file_memory(map_size, mem_type, mapping, false, fd);\n\t\tif (check_allocated_memory(map_ptr, map_size, mem_type, false) != KSFT_PASS) {\n\t\t\tclose(fd);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tptr = map_ptr + UNDERFLOW;\n\t\tmte_initialize_current_context(mode, (uintptr_t)ptr, sizes[run]);\n\t\t/* Only mte enabled memory will allow tag insertion */\n\t\tptr = mte_insert_tags((void *)ptr, sizes[run]);\n\t\tif (!ptr || cur_mte_cxt.fault_valid == true) {\n\t\t\tksft_print_msg(\"FAIL: Insert tags on file based memory\\n\");\n\t\t\tmunmap((void *)map_ptr, map_size);\n\t\t\tclose(fd);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tresult = check_mte_memory(ptr, sizes[run], mode, tag_check);\n\t\tmte_clear_tags((void *)ptr, sizes[run]);\n\t\tmunmap((void *)map_ptr, map_size);\n\t\tclose(fd);\n\t\tif (result == KSFT_FAIL)\n\t\t\tbreak;\n\t}\n\treturn result;\n}",
        "static int smp_cmd_dhkey_check(struct l2cap_conn *conn, struct sk_buff *skb)\n{\n\tstruct smp_cmd_dhkey_check *check = (void *) skb->data;\n\tstruct l2cap_chan *chan = conn->smp;\n\tstruct hci_conn *hcon = conn->hcon;": "static int smp_cmd_dhkey_check(struct l2cap_conn *conn, struct sk_buff *skb)\n{\n\tstruct smp_cmd_dhkey_check *check = (void *) skb->data;\n\tstruct l2cap_chan *chan = conn->smp;\n\tstruct hci_conn *hcon = conn->hcon;\n\tstruct smp_chan *smp = chan->data;\n\tu8 a[7], b[7], *local_addr, *remote_addr;\n\tu8 io_cap[3], r[16], e[16];\n\tint err;\n\n\tbt_dev_dbg(hcon->hdev, \"conn %p\", conn);\n\n\tif (skb->len < sizeof(*check))\n\t\treturn SMP_INVALID_PARAMS;\n\n\tmemcpy(a, &hcon->init_addr, 6);\n\tmemcpy(b, &hcon->resp_addr, 6);\n\ta[6] = hcon->init_addr_type;\n\tb[6] = hcon->resp_addr_type;\n\n\tif (hcon->out) {\n\t\tlocal_addr = a;\n\t\tremote_addr = b;\n\t\tmemcpy(io_cap, &smp->prsp[1], 3);\n\t} else {\n\t\tlocal_addr = b;\n\t\tremote_addr = a;\n\t\tmemcpy(io_cap, &smp->preq[1], 3);\n\t}\n\n\tmemset(r, 0, sizeof(r));\n\n\tif (smp->method == REQ_PASSKEY || smp->method == DSP_PASSKEY)\n\t\tput_unaligned_le32(hcon->passkey_notify, r);\n\telse if (smp->method == REQ_OOB)\n\t\tmemcpy(r, smp->lr, 16);\n\n\terr = smp_f6(smp->tfm_cmac, smp->mackey, smp->rrnd, smp->prnd, r,\n\t\t     io_cap, remote_addr, local_addr, e);\n\tif (err)\n\t\treturn SMP_UNSPECIFIED;\n\n\tif (crypto_memneq(check->e, e, 16))\n\t\treturn SMP_DHKEY_CHECK_FAILED;\n\n\tif (!hcon->out) {\n\t\tif (test_bit(SMP_FLAG_WAIT_USER, &smp->flags)) {\n\t\t\tset_bit(SMP_FLAG_DHKEY_PENDING, &smp->flags);\n\t\t\treturn 0;\n\t\t}\n\n\t\t/* Responder sends DHKey check as response to initiator */\n\t\tsc_dhkey_check(smp);\n\t}\n\n\tsc_add_ltk(smp);\n\n\tif (hcon->out) {\n\t\thci_le_start_enc(hcon, 0, 0, smp->tk, smp->enc_key_size);\n\t\thcon->enc_key_size = smp->enc_key_size;\n\t}\n\n\treturn 0;\n}",
        "static int __init led_init(struct ibm_init_struct *iibm)\n{\n\tunsigned int i;\n\tint rc;\n\tunsigned long useful_leds;": "static int __init led_init(struct ibm_init_struct *iibm)\n{\n\tunsigned int i;\n\tint rc;\n\tunsigned long useful_leds;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing LED subdriver\\n\");\n\n\tled_supported = led_init_detect_mode();\n\n\tif (led_supported != TPACPI_LED_NONE) {\n\t\tuseful_leds = tpacpi_check_quirks(led_useful_qtable,\n\t\t\t\tARRAY_SIZE(led_useful_qtable));\n\n\t\tif (!useful_leds) {\n\t\t\tled_handle = NULL;\n\t\t\tled_supported = TPACPI_LED_NONE;\n\t\t}\n\t}\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"LED commands are %s, mode %d\\n\",\n\t\tstr_supported(led_supported), led_supported);\n\n\tif (led_supported == TPACPI_LED_NONE)\n\t\treturn -ENODEV;\n\n\ttpacpi_leds = kcalloc(TPACPI_LED_NUMLEDS, sizeof(*tpacpi_leds),\n\t\t\t      GFP_KERNEL);\n\tif (!tpacpi_leds) {\n\t\tpr_err(\"Out of memory for LED data\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tfor (i = 0; i < TPACPI_LED_NUMLEDS; i++) {\n\t\ttpacpi_leds[i].led = -1;\n\n\t\tif (!tpacpi_is_led_restricted(i) && test_bit(i, &useful_leds)) {\n\t\t\trc = tpacpi_init_led(i);\n\t\t\tif (rc < 0) {\n\t\t\t\tled_exit();\n\t\t\t\treturn rc;\n\t\t\t}\n\t\t}\n\t}\n\n#ifdef CONFIG_THINKPAD_ACPI_UNSAFE_LEDS\n\tpr_notice(\"warning: userspace override of important firmware LEDs is enabled\\n\");\n#endif\n\treturn 0;\n}",
        "static void rx_async(struct slgt_info *info)\n{\n \tstruct mgsl_icount *icount = &info->icount;\n\tunsigned int start, end;\n\tunsigned char *p;": "static void rx_async(struct slgt_info *info)\n{\n \tstruct mgsl_icount *icount = &info->icount;\n\tunsigned int start, end;\n\tunsigned char *p;\n\tunsigned char status;\n\tstruct slgt_desc *bufs = info->rbufs;\n\tint i, count;\n\tint chars = 0;\n\tint stat;\n\tunsigned char ch;\n\n\tstart = end = info->rbuf_current;\n\n\twhile(desc_complete(bufs[end])) {\n\t\tcount = desc_count(bufs[end]) - info->rbuf_index;\n\t\tp     = bufs[end].buf + info->rbuf_index;\n\n\t\tDBGISR((\"%s rx_async count=%d\\n\", info->device_name, count));\n\t\tDBGDATA(info, p, count, \"rx\");\n\n\t\tfor(i=0 ; i < count; i+=2, p+=2) {\n\t\t\tch = *p;\n\t\t\ticount->rx++;\n\n\t\t\tstat = 0;\n\n\t\t\tstatus = *(p + 1) & (BIT1 + BIT0);\n\t\t\tif (status) {\n\t\t\t\tif (status & BIT1)\n\t\t\t\t\ticount->parity++;\n\t\t\t\telse if (status & BIT0)\n\t\t\t\t\ticount->frame++;\n\t\t\t\t/* discard char if tty control flags say so */\n\t\t\t\tif (status & info->ignore_status_mask)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (status & BIT1)\n\t\t\t\t\tstat = TTY_PARITY;\n\t\t\t\telse if (status & BIT0)\n\t\t\t\t\tstat = TTY_FRAME;\n\t\t\t}\n\t\t\ttty_insert_flip_char(&info->port, ch, stat);\n\t\t\tchars++;\n\t\t}\n\n\t\tif (i < count) {\n\t\t\t/* receive buffer not completed */\n\t\t\tinfo->rbuf_index += i;\n\t\t\tmod_timer(&info->rx_timer, jiffies + 1);\n\t\t\tbreak;\n\t\t}\n\n\t\tinfo->rbuf_index = 0;\n\t\tfree_rbufs(info, end, end);\n\n\t\tif (++end == info->rbuf_count)\n\t\t\tend = 0;\n\n\t\t/* if entire list searched then no frame available */\n\t\tif (end == start)\n\t\t\tbreak;\n\t}\n\n\tif (chars)\n\t\ttty_flip_buffer_push(&info->port);\n}",
        "static void Et_init1(struct gspca_dev *gspca_dev)\n{\n\t__u8 value;\n/*\t__u8 I2c0 [] = {0x0a, 0x12, 0x05, 0x22, 0xac, 0x00, 0x01, 0x00}; */\n\t__u8 I2c0[] = { 0x0a, 0x12, 0x05, 0x6d, 0xcd, 0x00, 0x01, 0x00 };": "static void Et_init1(struct gspca_dev *gspca_dev)\n{\n\t__u8 value;\n/*\t__u8 I2c0 [] = {0x0a, 0x12, 0x05, 0x22, 0xac, 0x00, 0x01, 0x00}; */\n\t__u8 I2c0[] = { 0x0a, 0x12, 0x05, 0x6d, 0xcd, 0x00, 0x01, 0x00 };\n\t\t\t\t\t\t/* try 1/120 0x6d 0xcd 0x40 */\n/*\t__u8 I2c0 [] = {0x0a, 0x12, 0x05, 0xfe, 0xfe, 0xc0, 0x01, 0x00};\n\t\t\t\t\t\t * 1/60000 hmm ?? */\n\n\tgspca_dbg(gspca_dev, D_STREAM, \"Open Init1 ET\\n\\n\");\n\treg_w_val(gspca_dev, ET_GPIO_DIR_CTRL, 7);\n\treg_r(gspca_dev, ET_GPIO_IN, 1);\n\treg_w_val(gspca_dev, ET_RESET_ALL, 1);\n\treg_w_val(gspca_dev, ET_RESET_ALL, 0);\n\treg_w_val(gspca_dev, ET_ClCK, 0x10);\n\treg_w_val(gspca_dev, ET_CTRL, 0x19);\n\t/*   compression et subsampling */\n\tif (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv)\n\t\tvalue = ET_COMP_VAL1;\n\telse\n\t\tvalue = ET_COMP_VAL0;\n\tgspca_dbg(gspca_dev, D_STREAM, \"Open mode %d Compression %d\\n\",\n\t\t  gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv,\n\t\t  value);\n\treg_w_val(gspca_dev, ET_COMP, value);\n\treg_w_val(gspca_dev, ET_MAXQt, 0x1d);\n\treg_w_val(gspca_dev, ET_MINQt, 0x02);\n\t/* undocumented registers */\n\treg_w_val(gspca_dev, ET_REG1d, 0xff);\n\treg_w_val(gspca_dev, ET_REG1e, 0xff);\n\treg_w_val(gspca_dev, ET_REG1f, 0xff);\n\treg_w_val(gspca_dev, ET_REG20, 0x35);\n\treg_w_val(gspca_dev, ET_REG21, 0x01);\n\treg_w_val(gspca_dev, ET_REG22, 0x00);\n\treg_w_val(gspca_dev, ET_REG23, 0xf7);\n\treg_w_val(gspca_dev, ET_REG24, 0xff);\n\treg_w_val(gspca_dev, ET_REG25, 0x07);\n\t/* colors setting */\n\treg_w_val(gspca_dev, ET_G_RED, 0x80);\n\treg_w_val(gspca_dev, ET_G_GREEN1, 0x80);\n\treg_w_val(gspca_dev, ET_G_BLUE, 0x80);\n\treg_w_val(gspca_dev, ET_G_GREEN2, 0x80);\n\treg_w_val(gspca_dev, ET_G_GR_H, 0x00);\n\treg_w_val(gspca_dev, ET_G_GB_H, 0x00);\n\t/* Window control registers */\n\treg_w_val(gspca_dev, ET_SYNCHRO, 0xf0);\n\treg_w_val(gspca_dev, ET_STARTX, 0x56);\t\t/* 0x56 */\n\treg_w_val(gspca_dev, ET_STARTY, 0x05);\t\t/* 0x04 */\n\treg_w_val(gspca_dev, ET_WIDTH_LOW, 0x60);\n\treg_w_val(gspca_dev, ET_HEIGTH_LOW, 0x20);\n\treg_w_val(gspca_dev, ET_W_H_HEIGTH, 0x50);\n\treg_w_val(gspca_dev, ET_REG6e, 0x86);\n\treg_w_val(gspca_dev, ET_REG6f, 0x01);\n\treg_w_val(gspca_dev, ET_REG70, 0x86);\n\treg_w_val(gspca_dev, ET_REG71, 0x14);\n\treg_w_val(gspca_dev, ET_REG72, 0x00);\n\t/* Clock Pattern registers */\n\treg_w_val(gspca_dev, ET_REG73, 0x00);\n\treg_w_val(gspca_dev, ET_REG74, 0x00);\n\treg_w_val(gspca_dev, ET_REG75, 0x0a);\n\treg_w_val(gspca_dev, ET_I2C_CLK, 0x04);\n\treg_w_val(gspca_dev, ET_PXL_CLK, 0x01);\n\t/* set the sensor */\n\tif (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv) {\n\t\tI2c0[0] = 0x06;\n\t\ti2c_w(gspca_dev, PAS106_REG2, I2c0, sizeof I2c0, 1);\n\t\ti2c_w(gspca_dev, PAS106_REG9, I2c2, sizeof I2c2, 1);\n\t\tvalue = 0x06;\n\t\ti2c_w(gspca_dev, PAS106_REG2, &value, 1, 1);\n\t\ti2c_w(gspca_dev, PAS106_REG3, I2c3, sizeof I2c3, 1);\n\t\t/* value = 0x1f; */\n\t\tvalue = 0x04;\n\t\ti2c_w(gspca_dev, PAS106_REG0e, &value, 1, 1);\n\t} else {\n\t\tI2c0[0] = 0x0a;\n\n\t\ti2c_w(gspca_dev, PAS106_REG2, I2c0, sizeof I2c0, 1);\n\t\ti2c_w(gspca_dev, PAS106_REG9, I2c2, sizeof I2c2, 1);\n\t\tvalue = 0x0a;\n\t\ti2c_w(gspca_dev, PAS106_REG2, &value, 1, 1);\n\t\ti2c_w(gspca_dev, PAS106_REG3, I2c3, sizeof I2c3, 1);\n\t\tvalue = 0x04;\n\t\t/* value = 0x10; */\n\t\ti2c_w(gspca_dev, PAS106_REG0e, &value, 1, 1);\n\t\t/* bit 2 enable bit 1:2 select 0 1 2 3\n\t\t   value = 0x07;                                * curve 0 *\n\t\t   i2c_w(gspca_dev, PAS106_REG0f, &value, 1, 1);\n\t\t */\n\t}\n\n/*\tvalue = 0x01; */\n/*\tvalue = 0x22; */\n/*\ti2c_w(gspca_dev, PAS106_REG5, &value, 1, 1); */\n\t/* magnetude and sign bit for DAC */\n\ti2c_w(gspca_dev, PAS106_REG7, I2c4, sizeof I2c4, 1);\n\t/* now set by fifo the whole colors setting */\n\treg_w(gspca_dev, ET_G_RED, GainRGBG, 6);\n\tsetcolors(gspca_dev, getcolors(gspca_dev));\n}",
        "static void __init sklh_idle_state_table_update(void)\n{\n\tunsigned long long msr;\n\tunsigned int eax, ebx, ecx, edx;\n": "static void __init sklh_idle_state_table_update(void)\n{\n\tunsigned long long msr;\n\tunsigned int eax, ebx, ecx, edx;\n\n\n\t/* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */\n\tif (max_cstate <= 7)\n\t\treturn;\n\n\t/* if PC10 not present in CPUID.MWAIT.EDX */\n\tif ((mwait_substates & (0xF << 28)) == 0)\n\t\treturn;\n\n\trdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);\n\n\t/* PC10 is not enabled in PKG C-state limit */\n\tif ((msr & 0xF) != 8)\n\t\treturn;\n\n\tecx = 0;\n\tcpuid(7, &eax, &ebx, &ecx, &edx);\n\n\t/* if SGX is present */\n\tif (ebx & (1 << 2)) {\n\n\t\trdmsrl(MSR_IA32_FEAT_CTL, msr);\n\n\t\t/* if SGX is enabled */\n\t\tif (msr & (1 << 18))\n\t\t\treturn;\n\t}\n\n\tskl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE;\t/* C8-SKL */\n\tskl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE;\t/* C9-SKL */\n}",
        "static void ww_test_edeadlk_no_unlock_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_no_unlock_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\to2.ctx = &t2;\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\n\to2.ctx = NULL;\n\tmutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);\n\tww_mutex_base_unlock(&o2.base);\n\n\tww_mutex_lock_slow(&o2, &t);\n}",
        "static int __optee_enumerate_devices(u32 func)\n{\n\tconst uuid_t pta_uuid =\n\t\tUUID_INIT(0x7011a688, 0xddde, 0x4053,\n\t\t\t  0xa5, 0xa9, 0x7b, 0x3c, 0x4d, 0xdf, 0x13, 0xb8);": "static int __optee_enumerate_devices(u32 func)\n{\n\tconst uuid_t pta_uuid =\n\t\tUUID_INIT(0x7011a688, 0xddde, 0x4053,\n\t\t\t  0xa5, 0xa9, 0x7b, 0x3c, 0x4d, 0xdf, 0x13, 0xb8);\n\tstruct tee_ioctl_open_session_arg sess_arg;\n\tstruct tee_shm *device_shm = NULL;\n\tconst uuid_t *device_uuid = NULL;\n\tstruct tee_context *ctx = NULL;\n\tu32 shm_size = 0, idx, num_devices = 0;\n\tint rc;\n\n\tmemset(&sess_arg, 0, sizeof(sess_arg));\n\n\t/* Open context with OP-TEE driver */\n\tctx = tee_client_open_context(NULL, optee_ctx_match, NULL, NULL);\n\tif (IS_ERR(ctx))\n\t\treturn -ENODEV;\n\n\t/* Open session with device enumeration pseudo TA */\n\texport_uuid(sess_arg.uuid, &pta_uuid);\n\tsess_arg.clnt_login = TEE_IOCTL_LOGIN_PUBLIC;\n\tsess_arg.num_params = 0;\n\n\trc = tee_client_open_session(ctx, &sess_arg, NULL);\n\tif ((rc < 0) || (sess_arg.ret != TEEC_SUCCESS)) {\n\t\t/* Device enumeration pseudo TA not found */\n\t\trc = 0;\n\t\tgoto out_ctx;\n\t}\n\n\trc = get_devices(ctx, sess_arg.session, NULL, &shm_size, func);\n\tif (rc < 0 || !shm_size)\n\t\tgoto out_sess;\n\n\tdevice_shm = tee_shm_alloc_kernel_buf(ctx, shm_size);\n\tif (IS_ERR(device_shm)) {\n\t\tpr_err(\"tee_shm_alloc_kernel_buf failed\\n\");\n\t\trc = PTR_ERR(device_shm);\n\t\tgoto out_sess;\n\t}\n\n\trc = get_devices(ctx, sess_arg.session, device_shm, &shm_size, func);\n\tif (rc < 0)\n\t\tgoto out_shm;\n\n\tdevice_uuid = tee_shm_get_va(device_shm, 0);\n\tif (IS_ERR(device_uuid)) {\n\t\tpr_err(\"tee_shm_get_va failed\\n\");\n\t\trc = PTR_ERR(device_uuid);\n\t\tgoto out_shm;\n\t}\n\n\tnum_devices = shm_size / sizeof(uuid_t);\n\n\tfor (idx = 0; idx < num_devices; idx++) {\n\t\trc = optee_register_device(&device_uuid[idx]);\n\t\tif (rc)\n\t\t\tgoto out_shm;\n\t}\n\nout_shm:\n\ttee_shm_free(device_shm);\nout_sess:\n\ttee_client_close_session(ctx, sess_arg.session);\nout_ctx:\n\ttee_client_close_context(ctx);\n\n\treturn rc;\n}",
        "static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)\n{\n\tint status = 0;\n\tunsigned int size = sizeof(dma_chan);\n": "static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)\n{\n\tint status = 0;\n\tunsigned int size = sizeof(dma_chan);\n\n\tcodec_dbg(codec, \"     dspio_alloc_dma_chan() -- begin\\n\");\n\tstatus = dspio_scp(codec, MASTERCONTROL, 0x20,\n\t\t\tMASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,\n\t\t\tdma_chan, &size);\n\n\tif (status < 0) {\n\t\tcodec_dbg(codec, \"dspio_alloc_dma_chan: SCP Failed\\n\");\n\t\treturn status;\n\t}\n\n\tif ((*dma_chan + 1) == 0) {\n\t\tcodec_dbg(codec, \"no free dma channels to allocate\\n\");\n\t\treturn -EBUSY;\n\t}\n\n\tcodec_dbg(codec, \"dspio_alloc_dma_chan: chan=%d\\n\", *dma_chan);\n\tcodec_dbg(codec, \"     dspio_alloc_dma_chan() -- complete\\n\");\n\n\treturn status;\n}",
        "static void gsi_irq_enable(struct gsi *gsi)\n{\n\tu32 val;\n\n\t/* Global interrupts include hardware error reports.  Enable": "static void gsi_irq_enable(struct gsi *gsi)\n{\n\tu32 val;\n\n\t/* Global interrupts include hardware error reports.  Enable\n\t * that so we can at least report the error should it occur.\n\t */\n\tiowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);\n\tgsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE));\n\n\t/* General GSI interrupts are reported to all EEs; if they occur\n\t * they are unrecoverable (without reset).  A breakpoint interrupt\n\t * also exists, but we don't support that.  We want to be notified\n\t * of errors so we can report them, even if they can't be handled.\n\t */\n\tval = BIT(BUS_ERROR);\n\tval |= BIT(CMD_FIFO_OVRFLOW);\n\tval |= BIT(MCS_STACK_OVRFLOW);\n\tiowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);\n\tgsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL));\n}",
        "static int trace_ctxwake_hex(struct trace_iterator *iter, char S)\n{\n\tstruct ctx_switch_entry *field;\n\tstruct trace_seq *s = &iter->seq;\n\tint T;": "static int trace_ctxwake_hex(struct trace_iterator *iter, char S)\n{\n\tstruct ctx_switch_entry *field;\n\tstruct trace_seq *s = &iter->seq;\n\tint T;\n\n\ttrace_assign_type(field, iter->ent);\n\n\tif (!S)\n\t\tS = task_index_to_char(field->prev_state);\n\tT = task_index_to_char(field->next_state);\n\n\tSEQ_PUT_HEX_FIELD(s, field->prev_pid);\n\tSEQ_PUT_HEX_FIELD(s, field->prev_prio);\n\tSEQ_PUT_HEX_FIELD(s, S);\n\tSEQ_PUT_HEX_FIELD(s, field->next_cpu);\n\tSEQ_PUT_HEX_FIELD(s, field->next_pid);\n\tSEQ_PUT_HEX_FIELD(s, field->next_prio);\n\tSEQ_PUT_HEX_FIELD(s, T);\n\n\treturn trace_handle_return(s);\n}",
        "static int yas5xx_meaure_offsets(struct yas5xx *yas5xx)\n{\n\tint ret;\n\tu16 center;\n\tu16 t, x, y1, y2;": "static int yas5xx_meaure_offsets(struct yas5xx *yas5xx)\n{\n\tint ret;\n\tu16 center;\n\tu16 t, x, y1, y2;\n\ts8 ox, oy1, oy2;\n\tint i;\n\n\t/* Actuate the init coil and measure offsets */\n\tret = regmap_write(yas5xx->map, YAS5XX_ACTUATE_INIT_COIL, 0);\n\tif (ret)\n\t\treturn ret;\n\n\t/* When the initcoil is active this should be around the center */\n\tswitch (yas5xx->devid) {\n\tcase YAS530_DEVICE_ID:\n\t\tcenter = YAS530_DATA_CENTER;\n\t\tbreak;\n\tcase YAS532_DEVICE_ID:\n\t\tcenter = YAS532_DATA_CENTER;\n\t\tbreak;\n\tdefault:\n\t\tdev_err(yas5xx->dev, \"unknown device type\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * We set offsets in the interval +-31 by iterating\n\t * +-16, +-8, +-4, +-2, +-1 adjusting the offsets each\n\t * time, then writing the final offsets into the\n\t * registers.\n\t *\n\t * NOTE: these offsets are NOT in the same unit or magnitude\n\t * as the values for [x, y1, y2]. The value is +/-31\n\t * but the effect on the raw values is much larger.\n\t * The effect of the offset is to bring the measure\n\t * rougly to the center.\n\t */\n\tox = 0;\n\toy1 = 0;\n\toy2 = 0;\n\n\tfor (i = 4; i >= 0; i--) {\n\t\tret = yas5xx_set_offsets(yas5xx, ox, oy1, oy2);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = yas5xx_measure(yas5xx, &t, &x, &y1, &y2);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tdev_dbg(yas5xx->dev, \"measurement %d: x=%d, y1=%d, y2=%d\\n\",\n\t\t\t5-i, x, y1, y2);\n\n\t\tox = yas5xx_adjust_offset(ox, i, center, x);\n\t\toy1 = yas5xx_adjust_offset(oy1, i, center, y1);\n\t\toy2 = yas5xx_adjust_offset(oy2, i, center, y2);\n\t}\n\n\t/* Needed for calibration algorithm */\n\tyas5xx->hard_offsets[0] = ox;\n\tyas5xx->hard_offsets[1] = oy1;\n\tyas5xx->hard_offsets[2] = oy2;\n\tret = yas5xx_set_offsets(yas5xx, ox, oy1, oy2);\n\tif (ret)\n\t\treturn ret;\n\n\tdev_info(yas5xx->dev, \"discovered hard offsets: x=%d, y1=%d, y2=%d\\n\",\n\t\t ox, oy1, oy2);\n\treturn 0;\n}",
        "static int ov08d10_init_controls(struct ov08d10 *ov08d10)\n{\n\tstruct v4l2_ctrl_handler *ctrl_hdlr;\n\tu8 link_freq_size;\n\ts64 exposure_max;": "static int ov08d10_init_controls(struct ov08d10 *ov08d10)\n{\n\tstruct v4l2_ctrl_handler *ctrl_hdlr;\n\tu8 link_freq_size;\n\ts64 exposure_max;\n\ts64 vblank_def;\n\ts64 vblank_min;\n\ts64 h_blank;\n\ts64 pixel_rate_max;\n\tconst struct ov08d10_mode *mode;\n\tint ret;\n\n\tctrl_hdlr = &ov08d10->ctrl_handler;\n\tret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);\n\tif (ret)\n\t\treturn ret;\n\n\tctrl_hdlr->lock = &ov08d10->mutex;\n\tlink_freq_size = ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu);\n\tov08d10->link_freq =\n\t\tv4l2_ctrl_new_int_menu(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t       V4L2_CID_LINK_FREQ,\n\t\t\t\t       link_freq_size - 1,\n\t\t\t\t       0,\n\t\t\t\t       ov08d10->priv_lane->link_freq_menu);\n\tif (ov08d10->link_freq)\n\t\tov08d10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n\n\tpixel_rate_max = to_rate(ov08d10->priv_lane->link_freq_menu, 0,\n\t\t\t\t ov08d10->cur_mode->data_lanes);\n\tov08d10->pixel_rate =\n\t\tv4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t  V4L2_CID_PIXEL_RATE, 0, pixel_rate_max, 1,\n\t\t\t\t  pixel_rate_max);\n\n\tmode = ov08d10->cur_mode;\n\tvblank_def = mode->vts_def - mode->height;\n\tvblank_min = mode->vts_min - mode->height;\n\tov08d10->vblank =\n\t\tv4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t  V4L2_CID_VBLANK, vblank_min,\n\t\t\t\t  OV08D10_VTS_MAX - mode->height, 1,\n\t\t\t\t  vblank_def);\n\n\th_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu,\n\t\t\t\t     mode->hts, mode->link_freq_index,\n\t\t\t\t     mode->data_lanes) -\n\t\t\t\t     mode->width;\n\tov08d10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t\t    V4L2_CID_HBLANK, h_blank, h_blank,\n\t\t\t\t\t    1, h_blank);\n\tif (ov08d10->hblank)\n\t\tov08d10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n\n\tv4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,\n\t\t\t  OV08D10_ANAL_GAIN_MIN, OV08D10_ANAL_GAIN_MAX,\n\t\t\t  OV08D10_ANAL_GAIN_STEP, OV08D10_ANAL_GAIN_MIN);\n\n\tv4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,\n\t\t\t  OV08D10_DGTL_GAIN_MIN, OV08D10_DGTL_GAIN_MAX,\n\t\t\t  OV08D10_DGTL_GAIN_STEP, OV08D10_DGTL_GAIN_DEFAULT);\n\n\texposure_max = mode->vts_def - OV08D10_EXPOSURE_MAX_MARGIN;\n\tov08d10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t\t      V4L2_CID_EXPOSURE,\n\t\t\t\t\t      OV08D10_EXPOSURE_MIN,\n\t\t\t\t\t      exposure_max,\n\t\t\t\t\t      OV08D10_EXPOSURE_STEP,\n\t\t\t\t\t      exposure_max);\n\n\tv4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t     V4L2_CID_TEST_PATTERN,\n\t\t\t\t     ARRAY_SIZE(ov08d10_test_pattern_menu) - 1,\n\t\t\t\t     0, 0, ov08d10_test_pattern_menu);\n\n\tov08d10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t\t   V4L2_CID_HFLIP, 0, 1, 1, 0);\n\tov08d10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,\n\t\t\t\t\t   V4L2_CID_VFLIP, 0, 1, 1, 0);\n\tif (ctrl_hdlr->error)\n\t\treturn ctrl_hdlr->error;\n\n\tov08d10->sd.ctrl_handler = ctrl_hdlr;\n\n\treturn 0;\n}",
        "static void tracee_zap_segment(void)\n{\n\t/*\n\t * The tracer will redirect execution here.  This is meant to\n\t * work like gdb's 'p func()' feature.  The tricky bit is that": "static void tracee_zap_segment(void)\n{\n\t/*\n\t * The tracer will redirect execution here.  This is meant to\n\t * work like gdb's 'p func()' feature.  The tricky bit is that\n\t * we modify a segment register in order to make sure that ptrace\n\t * can correctly restore segment registers.\n\t */\n\tprintf(\"\\tTracee: in tracee_zap_segment()\\n\");\n\n\t/*\n\t * Write a nonzero selector with base zero to the segment register.\n\t * Using a null selector would defeat the test on AMD pre-Zen2\n\t * CPUs, as such CPUs don't clear the base when loading a null\n\t * selector.\n\t */\n\tunsigned short sel;\n\tasm volatile (\"mov %%ss, %0\\n\\t\"\n\t\t      \"mov %0, %\" SEG\n\t\t      : \"=rm\" (sel));\n\n\tpid_t pid = getpid(), tid = syscall(SYS_gettid);\n\n\tprintf(\"\\tTracee is going back to sleep\\n\");\n\tsyscall(SYS_tgkill, pid, tid, SIGSTOP);\n\n\t/* Should not get here. */\n\twhile (true) {\n\t\tprintf(\"[FAIL]\\tTracee hit unreachable code\\n\");\n\t\tpause();\n\t}\n}",
        "static int img_i2c_init(struct img_i2c *i2c)\n{\n\tunsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh;\n\tunsigned int i, data, prescale, inc, int_bitrate, filt;\n\tstruct img_i2c_timings timing;": "static int img_i2c_init(struct img_i2c *i2c)\n{\n\tunsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh;\n\tunsigned int i, data, prescale, inc, int_bitrate, filt;\n\tstruct img_i2c_timings timing;\n\tu32 rev;\n\tint ret;\n\n\tret = pm_runtime_resume_and_get(i2c->adap.dev.parent);\n\tif (ret < 0)\n\t\treturn ret;\n\n\trev = img_i2c_readl(i2c, SCB_CORE_REV_REG);\n\tif ((rev & 0x00ffffff) < 0x00020200) {\n\t\tdev_info(i2c->adap.dev.parent,\n\t\t\t \"Unknown hardware revision (%d.%d.%d.%d)\\n\",\n\t\t\t (rev >> 24) & 0xff, (rev >> 16) & 0xff,\n\t\t\t (rev >> 8) & 0xff, rev & 0xff);\n\t\tpm_runtime_mark_last_busy(i2c->adap.dev.parent);\n\t\tpm_runtime_put_autosuspend(i2c->adap.dev.parent);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Fencing enabled by default. */\n\ti2c->need_wr_rd_fence = true;\n\n\t/* Determine what mode we're in from the bitrate */\n\ttiming = timings[0];\n\tfor (i = 0; i < ARRAY_SIZE(timings); i++) {\n\t\tif (i2c->bitrate <= timings[i].max_bitrate) {\n\t\t\ttiming = timings[i];\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i2c->bitrate > timings[ARRAY_SIZE(timings) - 1].max_bitrate) {\n\t\tdev_warn(i2c->adap.dev.parent,\n\t\t\t \"requested bitrate (%u) is higher than the max bitrate supported (%u)\\n\",\n\t\t\t i2c->bitrate,\n\t\t\t timings[ARRAY_SIZE(timings) - 1].max_bitrate);\n\t\ttiming = timings[ARRAY_SIZE(timings) - 1];\n\t\ti2c->bitrate = timing.max_bitrate;\n\t}\n\n\tbitrate_khz = i2c->bitrate / 1000;\n\tclk_khz = clk_get_rate(i2c->scb_clk) / 1000;\n\n\t/* Find the prescale that would give us that inc (approx delay = 0) */\n\tprescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz);\n\tprescale = clamp_t(unsigned int, prescale, 1, 8);\n\tclk_khz /= prescale;\n\n\t/* Setup the clock increment value */\n\tinc = (256 * 16 * bitrate_khz) / clk_khz;\n\n\t/*\n\t * The clock generation logic allows to filter glitches on the bus.\n\t * This filter is able to remove bus glitches shorter than 50ns.\n\t * If the clock enable rate is greater than 20 MHz, no filtering\n\t * is required, so we need to disable it.\n\t * If it's between the 20-40 MHz range, there's no need to divide\n\t * the clock to get a filter.\n\t */\n\tif (clk_khz < 20000) {\n\t\tfilt = SCB_FILT_DISABLE;\n\t} else if (clk_khz < 40000) {\n\t\tfilt = SCB_FILT_BYPASS;\n\t} else {\n\t\t/* Calculate filter clock */\n\t\tfilt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH));\n\n\t\t/* Scale up if needed */\n\t\tif (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH))\n\t\t\tinc++;\n\n\t\tif (filt > SCB_FILT_INC_MASK)\n\t\t\tfilt = SCB_FILT_INC_MASK;\n\n\t\tfilt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT;\n\t}\n\tdata = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1);\n\timg_i2c_writel(i2c, SCB_CLK_SET_REG, data);\n\n\t/* Obtain the clock period of the fx16 clock in ns */\n\tclk_period = (256 * 1000000) / (clk_khz * inc);\n\n\t/* Calculate the bitrate in terms of internal clock pulses */\n\tint_bitrate = 1000000 / (bitrate_khz * clk_period);\n\tif ((1000000 % (bitrate_khz * clk_period)) >=\n\t    ((bitrate_khz * clk_period) / 2))\n\t\tint_bitrate++;\n\n\t/*\n\t * Setup clock duty cycle, start with 50% and adjust TCKH and TCKL\n\t * values from there if they don't meet minimum timing requirements\n\t */\n\ttckh = int_bitrate / 2;\n\ttckl = int_bitrate - tckh;\n\n\t/* Adjust TCKH and TCKL values */\n\tdata = DIV_ROUND_UP(timing.tckl, clk_period);\n\n\tif (tckl < data) {\n\t\ttckl = data;\n\t\ttckh = int_bitrate - tckl;\n\t}\n\n\tif (tckh > 0)\n\t\t--tckh;\n\n\tif (tckl > 0)\n\t\t--tckl;\n\n\timg_i2c_writel(i2c, SCB_TIME_TCKH_REG, tckh);\n\timg_i2c_writel(i2c, SCB_TIME_TCKL_REG, tckl);\n\n\t/* Setup TSDH value */\n\ttsdh = DIV_ROUND_UP(timing.tsdh, clk_period);\n\n\tif (tsdh > 1)\n\t\tdata = tsdh - 1;\n\telse\n\t\tdata = 0x01;\n\timg_i2c_writel(i2c, SCB_TIME_TSDH_REG, data);\n\n\t/* This value is used later */\n\ttsdh = data;\n\n\t/* Setup TPL value */\n\tdata = timing.tpl / clk_period;\n\tif (data > 0)\n\t\t--data;\n\timg_i2c_writel(i2c, SCB_TIME_TPL_REG, data);\n\n\t/* Setup TPH value */\n\tdata = timing.tph / clk_period;\n\tif (data > 0)\n\t\t--data;\n\timg_i2c_writel(i2c, SCB_TIME_TPH_REG, data);\n\n\t/* Setup TSDL value to TPL + TSDH + 2 */\n\timg_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2);\n\n\t/* Setup TP2S value */\n\tdata = timing.tp2s / clk_period;\n\tif (data > 0)\n\t\t--data;\n\timg_i2c_writel(i2c, SCB_TIME_TP2S_REG, data);\n\n\timg_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI);\n\timg_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL);\n\timg_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL);\n\n\t/* Take module out of soft reset and enable clocks */\n\timg_i2c_soft_reset(i2c);\n\n\t/* Disable all interrupts */\n\timg_i2c_writel(i2c, SCB_INT_MASK_REG, 0);\n\n\t/* Clear all interrupts */\n\timg_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0);\n\n\t/* Clear the scb_line_status events */\n\timg_i2c_writel(i2c, SCB_CLEAR_REG, ~0);\n\n\t/* Enable interrupts */\n\timg_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);\n\n\t/* Perform a synchronous sequence to reset the bus */\n\tret = img_i2c_reset_bus(i2c);\n\n\tpm_runtime_mark_last_busy(i2c->adap.dev.parent);\n\tpm_runtime_put_autosuspend(i2c->adap.dev.parent);\n\n\treturn ret;\n}",
        "static void message_fail(struct device *dev, int cpu, union ifs_status status)\n{\n\t/*\n\t * control_error is set when the microcode runs into a problem\n\t * loading the image from the reserved BIOS memory, or it has": "static void message_fail(struct device *dev, int cpu, union ifs_status status)\n{\n\t/*\n\t * control_error is set when the microcode runs into a problem\n\t * loading the image from the reserved BIOS memory, or it has\n\t * been corrupted. Reloading the image may fix this issue.\n\t */\n\tif (status.control_error) {\n\t\tdev_err(dev, \"CPU(s) %*pbl: could not execute from loaded scan image\\n\",\n\t\t\tcpumask_pr_args(cpu_smt_mask(cpu)));\n\t}\n\n\t/*\n\t * signature_error is set when the output from the scan chains does not\n\t * match the expected signature. This might be a transient problem (e.g.\n\t * due to a bit flip from an alpha particle or neutron). If the problem\n\t * repeats on a subsequent test, then it indicates an actual problem in\n\t * the core being tested.\n\t */\n\tif (status.signature_error) {\n\t\tdev_err(dev, \"CPU(s) %*pbl: test signature incorrect.\\n\",\n\t\t\tcpumask_pr_args(cpu_smt_mask(cpu)));\n\t}\n}",
        "static void codec_h264_src_change(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\tstruct codec_h264 *h264 = sess->priv;\n\tu32 parsed_info, mb_total;": "static void codec_h264_src_change(struct amvdec_session *sess)\n{\n\tstruct amvdec_core *core = sess->core;\n\tstruct codec_h264 *h264 = sess->priv;\n\tu32 parsed_info, mb_total;\n\tu32 crop_infor, crop_bottom, crop_right;\n\tu32 frame_width, frame_height;\n\n\tsess->keyframe_found = 1;\n\n\tparsed_info = amvdec_read_dos(core, AV_SCRATCH_1);\n\n\t/* Total number of 16x16 macroblocks */\n\tmb_total = (parsed_info >> MB_TOTAL_BIT) & MB_TOTAL_MASK;\n\t/* Number of macroblocks per line */\n\th264->mb_width = parsed_info & MB_WIDTH_MASK;\n\t/* Number of macroblock lines */\n\th264->mb_height = mb_total / h264->mb_width;\n\n\th264->max_refs = ((parsed_info >> MAX_REF_BIT) & MAX_REF_MASK) + 1;\n\n\tcrop_infor = amvdec_read_dos(core, AV_SCRATCH_6);\n\tcrop_bottom = (crop_infor & 0xff);\n\tcrop_right = (crop_infor >> 16) & 0xff;\n\n\tframe_width = h264->mb_width * 16 - crop_right;\n\tframe_height = h264->mb_height * 16 - crop_bottom;\n\n\tdev_dbg(core->dev, \"frame: %ux%u; crop: %u %u\\n\",\n\t\tframe_width, frame_height, crop_right, crop_bottom);\n\n\tcodec_h264_set_par(sess);\n\tamvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);\n}",
        "static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)\n{\n\tu32 hcfg, hfir, otgctl, usbcfg;\n\n\tdev_dbg(hsotg->dev, \"%s(%p)\\n\", __func__, hsotg);": "static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)\n{\n\tu32 hcfg, hfir, otgctl, usbcfg;\n\n\tdev_dbg(hsotg->dev, \"%s(%p)\\n\", __func__, hsotg);\n\n\t/* Set HS/FS Timeout Calibration to 7 (max available value).\n\t * The number of PHY clocks that the application programs in\n\t * this field is added to the high/full speed interpacket timeout\n\t * duration in the core to account for any additional delays\n\t * introduced by the PHY. This can be required, because the delay\n\t * introduced by the PHY in generating the linestate condition\n\t * can vary from one PHY to another.\n\t */\n\tusbcfg = dwc2_readl(hsotg, GUSBCFG);\n\tusbcfg |= GUSBCFG_TOUTCAL(7);\n\tdwc2_writel(hsotg, usbcfg, GUSBCFG);\n\n\t/* Restart the Phy Clock */\n\tdwc2_writel(hsotg, 0, PCGCTL);\n\n\t/* Initialize Host Configuration Register */\n\tdwc2_init_fs_ls_pclk_sel(hsotg);\n\tif (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||\n\t    hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {\n\t\thcfg = dwc2_readl(hsotg, HCFG);\n\t\thcfg |= HCFG_FSLSSUPP;\n\t\tdwc2_writel(hsotg, hcfg, HCFG);\n\t}\n\n\t/*\n\t * This bit allows dynamic reloading of the HFIR register during\n\t * runtime. This bit needs to be programmed during initial configuration\n\t * and its value must not be changed during runtime.\n\t */\n\tif (hsotg->params.reload_ctl) {\n\t\thfir = dwc2_readl(hsotg, HFIR);\n\t\thfir |= HFIR_RLDCTRL;\n\t\tdwc2_writel(hsotg, hfir, HFIR);\n\t}\n\n\tif (hsotg->params.dma_desc_enable) {\n\t\tu32 op_mode = hsotg->hw_params.op_mode;\n\n\t\tif (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||\n\t\t    !hsotg->hw_params.dma_desc_enable ||\n\t\t    op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||\n\t\t    op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||\n\t\t    op_mode == GHWCFG2_OP_MODE_UNDEFINED) {\n\t\t\tdev_err(hsotg->dev,\n\t\t\t\t\"Hardware does not support descriptor DMA mode -\\n\");\n\t\t\tdev_err(hsotg->dev,\n\t\t\t\t\"falling back to buffer DMA mode.\\n\");\n\t\t\thsotg->params.dma_desc_enable = false;\n\t\t} else {\n\t\t\thcfg = dwc2_readl(hsotg, HCFG);\n\t\t\thcfg |= HCFG_DESCDMA;\n\t\t\tdwc2_writel(hsotg, hcfg, HCFG);\n\t\t}\n\t}\n\n\t/* Configure data FIFO sizes */\n\tdwc2_config_fifos(hsotg);\n\n\t/* TODO - check this */\n\t/* Clear Host Set HNP Enable in the OTG Control Register */\n\totgctl = dwc2_readl(hsotg, GOTGCTL);\n\totgctl &= ~GOTGCTL_HSTSETHNPEN;\n\tdwc2_writel(hsotg, otgctl, GOTGCTL);\n\n\t/* Make sure the FIFOs are flushed */\n\tdwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);\n\tdwc2_flush_rx_fifo(hsotg);\n\n\t/* Clear Host Set HNP Enable in the OTG Control Register */\n\totgctl = dwc2_readl(hsotg, GOTGCTL);\n\totgctl &= ~GOTGCTL_HSTSETHNPEN;\n\tdwc2_writel(hsotg, otgctl, GOTGCTL);\n\n\tif (!hsotg->params.dma_desc_enable) {\n\t\tint num_channels, i;\n\t\tu32 hcchar;\n\n\t\t/* Flush out any leftover queued requests */\n\t\tnum_channels = hsotg->params.host_channels;\n\t\tfor (i = 0; i < num_channels; i++) {\n\t\t\thcchar = dwc2_readl(hsotg, HCCHAR(i));\n\t\t\tif (hcchar & HCCHAR_CHENA) {\n\t\t\t\thcchar &= ~HCCHAR_CHENA;\n\t\t\t\thcchar |= HCCHAR_CHDIS;\n\t\t\t\thcchar &= ~HCCHAR_EPDIR;\n\t\t\t\tdwc2_writel(hsotg, hcchar, HCCHAR(i));\n\t\t\t}\n\t\t}\n\n\t\t/* Halt all channels to put them into a known state */\n\t\tfor (i = 0; i < num_channels; i++) {\n\t\t\thcchar = dwc2_readl(hsotg, HCCHAR(i));\n\t\t\tif (hcchar & HCCHAR_CHENA) {\n\t\t\t\thcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;\n\t\t\t\thcchar &= ~HCCHAR_EPDIR;\n\t\t\t\tdwc2_writel(hsotg, hcchar, HCCHAR(i));\n\t\t\t\tdev_dbg(hsotg->dev, \"%s: Halt channel %d\\n\",\n\t\t\t\t\t__func__, i);\n\n\t\t\t\tif (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),\n\t\t\t\t\t\t\t      HCCHAR_CHENA,\n\t\t\t\t\t\t\t      1000)) {\n\t\t\t\t\tdev_warn(hsotg->dev,\n\t\t\t\t\t\t \"Unable to clear enable on channel %d\\n\",\n\t\t\t\t\t\t i);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Enable ACG feature in host mode, if supported */\n\tdwc2_enable_acg(hsotg);\n\n\t/* Turn on the vbus power */\n\tdev_dbg(hsotg->dev, \"Init: Port Power? op_state=%d\\n\", hsotg->op_state);\n\tif (hsotg->op_state == OTG_STATE_A_HOST) {\n\t\tu32 hprt0 = dwc2_read_hprt0(hsotg);\n\n\t\tdev_dbg(hsotg->dev, \"Init: Power Port (%d)\\n\",\n\t\t\t!!(hprt0 & HPRT0_PWR));\n\t\tif (!(hprt0 & HPRT0_PWR)) {\n\t\t\thprt0 |= HPRT0_PWR;\n\t\t\tdwc2_writel(hsotg, hprt0, HPRT0);\n\t\t}\n\t}\n\n\tdwc2_enable_host_interrupts(hsotg);\n}",
        "static void sender_guest_code(struct test_data_page *data)\n{\n\tuint64_t last_wake_count;\n\tuint64_t last_hlt_count;\n\tuint64_t last_ipis_rcvd_count;": "static void sender_guest_code(struct test_data_page *data)\n{\n\tuint64_t last_wake_count;\n\tuint64_t last_hlt_count;\n\tuint64_t last_ipis_rcvd_count;\n\tuint32_t icr_val;\n\tuint32_t icr2_val;\n\tuint64_t tsc_start;\n\n\tverify_apic_base_addr();\n\txapic_enable();\n\n\t/*\n\t * Init interrupt command register for sending IPIs\n\t *\n\t * Delivery mode=fixed, per SDM:\n\t *   \"Delivers the interrupt specified in the vector field to the target\n\t *    processor.\"\n\t *\n\t * Destination mode=physical i.e. specify target by its local APIC\n\t * ID. This vCPU assumes that the halter vCPU has already started and\n\t * set data->halter_apic_id.\n\t */\n\ticr_val = (APIC_DEST_PHYSICAL | APIC_DM_FIXED | IPI_VECTOR);\n\ticr2_val = SET_APIC_DEST_FIELD(data->halter_apic_id);\n\tdata->icr = icr_val;\n\tdata->icr2 = icr2_val;\n\n\tlast_wake_count = data->wake_count;\n\tlast_hlt_count = data->hlt_count;\n\tlast_ipis_rcvd_count = ipis_rcvd;\n\tfor (;;) {\n\t\t/*\n\t\t * Send IPI to halter vCPU.\n\t\t * First IPI can be sent unconditionally because halter vCPU\n\t\t * starts earlier.\n\t\t */\n\t\txapic_write_reg(APIC_ICR2, icr2_val);\n\t\txapic_write_reg(APIC_ICR, icr_val);\n\t\tdata->ipis_sent++;\n\n\t\t/*\n\t\t * Wait up to ~1 sec for halter to indicate that it has:\n\t\t * 1. Received the IPI\n\t\t * 2. Woken up from the halt\n\t\t * 3. Gone back into halt\n\t\t * Current CPUs typically run at 2.x Ghz which is ~2\n\t\t * billion ticks per second.\n\t\t */\n\t\ttsc_start = rdtsc();\n\t\twhile (rdtsc() - tsc_start < 2000000000) {\n\t\t\tif ((ipis_rcvd != last_ipis_rcvd_count) &&\n\t\t\t    (data->wake_count != last_wake_count) &&\n\t\t\t    (data->hlt_count != last_hlt_count))\n\t\t\t\tbreak;\n\t\t}\n\n\t\tGUEST_ASSERT((ipis_rcvd != last_ipis_rcvd_count) &&\n\t\t\t     (data->wake_count != last_wake_count) &&\n\t\t\t     (data->hlt_count != last_hlt_count));\n\n\t\tlast_wake_count = data->wake_count;\n\t\tlast_hlt_count = data->hlt_count;\n\t\tlast_ipis_rcvd_count = ipis_rcvd;\n\t}\n}",
        "static void alc269_fill_coef(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\tint val;\n": "static void alc269_fill_coef(struct hda_codec *codec)\n{\n\tstruct alc_spec *spec = codec->spec;\n\tint val;\n\n\tif (spec->codec_variant != ALC269_TYPE_ALC269VB)\n\t\treturn;\n\n\tif ((alc_get_coef0(codec) & 0x00ff) < 0x015) {\n\t\talc_write_coef_idx(codec, 0xf, 0x960b);\n\t\talc_write_coef_idx(codec, 0xe, 0x8817);\n\t}\n\n\tif ((alc_get_coef0(codec) & 0x00ff) == 0x016) {\n\t\talc_write_coef_idx(codec, 0xf, 0x960b);\n\t\talc_write_coef_idx(codec, 0xe, 0x8814);\n\t}\n\n\tif ((alc_get_coef0(codec) & 0x00ff) == 0x017) {\n\t\t/* Power up output pin */\n\t\talc_update_coef_idx(codec, 0x04, 0, 1<<11);\n\t}\n\n\tif ((alc_get_coef0(codec) & 0x00ff) == 0x018) {\n\t\tval = alc_read_coef_idx(codec, 0xd);\n\t\tif (val != -1 && (val & 0x0c00) >> 10 != 0x1) {\n\t\t\t/* Capless ramp up clock control */\n\t\t\talc_write_coef_idx(codec, 0xd, val | (1<<10));\n\t\t}\n\t\tval = alc_read_coef_idx(codec, 0x17);\n\t\tif (val != -1 && (val & 0x01c0) >> 6 != 0x4) {\n\t\t\t/* Class D power on reset */\n\t\t\talc_write_coef_idx(codec, 0x17, val | (1<<7));\n\t\t}\n\t}\n\n\t/* HP */\n\talc_update_coef_idx(codec, 0x4, 0, 1<<11);\n}",
        "static void issue_p2p_GO_response(struct adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)\n{\n\tunsigned char category = WLAN_CATEGORY_PUBLIC;\n\tu8 action = P2P_PUB_ACTION_ACTION;\n\t__be32\t\t\tp2poui = cpu_to_be32(P2POUI);": "static void issue_p2p_GO_response(struct adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)\n{\n\tunsigned char category = WLAN_CATEGORY_PUBLIC;\n\tu8 action = P2P_PUB_ACTION_ACTION;\n\t__be32\t\t\tp2poui = cpu_to_be32(P2POUI);\n\tu8 oui_subtype = P2P_GO_NEGO_RESP;\n\tu8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };\n\tu8 p2pielen = 0;\n\tuint\t\t\twpsielen = 0;\n\tu16 wps_devicepassword_id = 0x0000;\n\t__be16\t\t\tbe_tmp;\n\tuint\t\t\twps_devicepassword_id_len = 0;\n\tu16 len_channellist_attr = 0;\n\n\tstruct xmit_frame\t\t\t*pmgntframe;\n\tstruct pkt_attrib\t\t\t*pattrib;\n\tunsigned char\t\t\t\t\t*pframe;\n\tstruct ieee80211_hdr *pwlanhdr;\n\t__le16 *fctrl;\n\tstruct xmit_priv\t\t\t*pxmitpriv = &padapter->xmitpriv;\n\tstruct mlme_ext_priv\t*pmlmeext = &padapter->mlmeextpriv;\n\tstruct wifidirect_info\t*pwdinfo = &padapter->wdinfo;\n\n\tpmgntframe = alloc_mgtxmitframe(pxmitpriv);\n\tif (!pmgntframe)\n\t\treturn;\n\n\t/* update attribute */\n\tpattrib = &pmgntframe->attrib;\n\tupdate_mgntframe_attrib(padapter, pattrib);\n\n\tmemset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);\n\n\tpframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;\n\tpwlanhdr = (struct ieee80211_hdr *)pframe;\n\n\tfctrl = &pwlanhdr->frame_control;\n\t*(fctrl) = 0;\n\n\tmemcpy(pwlanhdr->addr1, raddr, ETH_ALEN);\n\tmemcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN);\n\tmemcpy(pwlanhdr->addr3, myid(&padapter->eeprompriv), ETH_ALEN);\n\n\tSetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);\n\tpmlmeext->mgnt_seq++;\n\tSetFrameSubType(pframe, WIFI_ACTION);\n\n\tpframe += sizeof(struct ieee80211_hdr_3addr);\n\tpattrib->pktlen = sizeof(struct ieee80211_hdr_3addr);\n\n\tpframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen);\n\tpframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&p2poui, &pattrib->pktlen);\n\tpframe = rtw_set_fixed_ie(pframe, 1, &oui_subtype, &pattrib->pktlen);\n\tpwdinfo->negotiation_dialog_token = frame_body[7];\t/*\tThe Dialog Token of provisioning discovery request frame. */\n\tpframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &pattrib->pktlen);\n\n\t/*\tCommented by Albert 20110328 */\n\t/*\tTry to get the device password ID from the WPS IE of group negotiation request frame */\n\t/*\tWiFi Direct test plan 5.1.15 */\n\trtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);\n\trtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *)&be_tmp, &wps_devicepassword_id_len);\n\twps_devicepassword_id = be16_to_cpu(be_tmp);\n\n\tmemset(wpsie, 0x00, 255);\n\twpsielen = 0;\n\n\t/*\tWPS Section */\n\twpsielen = 0;\n\t/*\tWPS OUI */\n\t*(__be32 *)(wpsie) = cpu_to_be32(WPSOUI);\n\twpsielen += 4;\n\n\t/*\tWPS version */\n\t/*\tType: */\n\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\twpsie[wpsielen++] = WPS_VERSION_1;\t/*\tVersion 1.0 */\n\n\t/*\tDevice Password ID */\n\t/*\tType: */\n\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);\n\twpsielen += 2;\n\n\t/*\tLength: */\n\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);\n\twpsielen += 2;\n\n\t/*\tValue: */\n\tif (wps_devicepassword_id == WPS_DPID_USER_SPEC)\n\t\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);\n\telse if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)\n\t\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);\n\telse\n\t\t*(__be16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);\n\twpsielen += 2;\n\n\t/*\tCommented by Kurt 20120113 */\n\t/*\tIf some device wants to do p2p handshake without sending prov_disc_req */\n\t/*\tWe have to get peer_req_cm from here. */\n\tif (!memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"000\", 3)) {\n\t\tif (wps_devicepassword_id == WPS_DPID_USER_SPEC)\n\t\t\tmemcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"dis\", 3);\n\t\telse if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)\n\t\t\tmemcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pad\", 3);\n\t\telse\n\t\t\tmemcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, \"pbc\", 3);\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *)wpsie, &pattrib->pktlen);\n\n\t/*\tP2P IE Section. */\n\n\t/*\tP2P OUI */\n\tp2pielen = 0;\n\tp2pie[p2pielen++] = 0x50;\n\tp2pie[p2pielen++] = 0x6F;\n\tp2pie[p2pielen++] = 0x9A;\n\tp2pie[p2pielen++] = 0x09;\t/*\tWFA P2P v1.0 */\n\n\t/*\tCommented by Albert 20100908 */\n\t/*\tAccording to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */\n\t/*\t1. Status */\n\t/*\t2. P2P Capability */\n\t/*\t3. Group Owner Intent */\n\t/*\t4. Configuration Timeout */\n\t/*\t5. Operating Channel */\n\t/*\t6. Intended P2P Interface Address */\n\t/*\t7. Channel List */\n\t/*\t8. Device Info */\n\t/*\t9. Group ID\t(Only GO) */\n\n\t/*\tToDo: */\n\n\t/*\tP2P Status */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_STATUS;\n\n\t/*\tLength: */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = result;\n\n\t/*\tP2P Capability */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CAPABILITY;\n\n\t/*\tLength: */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tDevice Capability Bitmap, 1 byte */\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {\n\t\t/*\tCommented by Albert 2011/03/08 */\n\t\t/*\tAccording to the P2P specification */\n\t\t/*\tif the sending device will be client, the P2P Capability should be reserved of group negotiation response frame */\n\t\tp2pie[p2pielen++] = 0;\n\t} else {\n\t\t/*\tBe group owner or meet the error case */\n\t\tp2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;\n\t}\n\n\t/*\tGroup Capability Bitmap, 1 byte */\n\tif (pwdinfo->persistent_supported) {\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;\n\t} else {\n\t\tp2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;\n\t}\n\n\t/*\tGroup Owner Intent */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_GO_INTENT;\n\n\t/*\tLength: */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tif (pwdinfo->peer_intent & 0x01) {\n\t\t/*\tPeer's tie breaker bit is 1, our tie breaker bit should be 0 */\n\t\tp2pie[p2pielen++] = (pwdinfo->intent << 1);\n\t} else {\n\t\t/*\tPeer's tie breaker bit is 0, our tie breaker bit should be 1 */\n\t\tp2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));\n\t}\n\n\t/*\tConfiguration Timeout */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;\n\n\t/*\tLength: */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P GO */\n\tp2pie[p2pielen++] = 200;\t/*\t2 seconds needed to be the P2P Client */\n\n\t/*\tOperating Channel */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;\n\n\t/*\tLength: */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tOperating Class */\n\tp2pie[p2pielen++] = 0x51;\n\n\t/*\tChannel Number */\n\tp2pie[p2pielen++] = pwdinfo->operating_channel;\t/*\toperating channel number */\n\n\t/*\tIntended P2P Interface Address */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR;\n\n\t/*\tLength: */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tmemcpy(p2pie + p2pielen, myid(&padapter->eeprompriv), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tChannel List */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_CH_LIST;\n\n\t/*  Country String(3) */\n\t/*  + (Operating Class (1) + Number of Channels(1)) * Operation Classes (?) */\n\t/*  + number of channels in all classes */\n\tlen_channellist_attr = 3\n\t   + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes\n\t   + get_reg_classes_full_count(&pmlmeext->channel_list);\n\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);\n\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tCountry String */\n\tp2pie[p2pielen++] = 'X';\n\tp2pie[p2pielen++] = 'X';\n\n\t/*\tThe third byte should be set to 0x04. */\n\t/*\tDescribed in the \"Operating Channel Attribute\" section. */\n\tp2pie[p2pielen++] = 0x04;\n\n\t/*\tChannel Entry List */\n\n\t{\n\t\tint i, j;\n\t\tfor (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {\n\t\t\t/*\tOperating Class */\n\t\t\tp2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;\n\n\t\t\t/*\tNumber of Channels */\n\t\t\tp2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;\n\n\t\t\t/*\tChannel List */\n\t\t\tfor (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) {\n\t\t\t\tp2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\tDevice Info */\n\t/*\tType: */\n\tp2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;\n\n\t/*\tLength: */\n\t/*\t21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */\n\t/*\t+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */\n\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\t/*\tP2P Device Address */\n\tmemcpy(p2pie + p2pielen, myid(&padapter->eeprompriv), ETH_ALEN);\n\tp2pielen += ETH_ALEN;\n\n\t/*\tConfig Method */\n\t/*\tThis field should be big endian. Noted by P2P specification. */\n\n\t*(__be16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);\n\n\tp2pielen += 2;\n\n\t/*\tPrimary Device Type */\n\t/*\tCategory ID */\n\t*(__be16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);\n\tp2pielen += 2;\n\n\t/*\tOUI */\n\t*(__be32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);\n\tp2pielen += 4;\n\n\t/*\tSub Category ID */\n\t*(__be16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);\n\tp2pielen += 2;\n\n\t/*\tNumber of Secondary Device Types */\n\tp2pie[p2pielen++] = 0x00;\t/*\tNo Secondary Device Type List */\n\n\t/*\tDevice Name */\n\t/*\tType: */\n\t*(__be16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);\n\tp2pielen += 2;\n\n\t/*\tLength: */\n\t*(__be16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);\n\tp2pielen += 2;\n\n\t/*\tValue: */\n\tmemcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);\n\tp2pielen += pwdinfo->device_name_len;\n\n\tif (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {\n\t\t/*\tGroup ID Attribute */\n\t\t/*\tType: */\n\t\tp2pie[p2pielen++] = P2P_ATTR_GROUP_ID;\n\n\t\t/*\tLength: */\n\t\t*(__le16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);\n\t\tp2pielen += 2;\n\n\t\t/*\tValue: */\n\t\t/*\tp2P Device Address */\n\t\tmemcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);\n\t\tp2pielen += ETH_ALEN;\n\n\t\t/*\tSSID */\n\t\tmemcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);\n\t\tp2pielen += pwdinfo->nego_ssidlen;\n\t}\n\n\tpframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *)p2pie, &pattrib->pktlen);\n\n\tpattrib->last_txcmdsz = pattrib->pktlen;\n\n\tdump_mgntframe(padapter, pmgntframe);\n}",
        "static void sev_write_init_ex_file_if_required(int cmd_id)\n{\n\tlockdep_assert_held(&sev_cmd_mutex);\n\n\tif (!sev_init_ex_buffer)": "static void sev_write_init_ex_file_if_required(int cmd_id)\n{\n\tlockdep_assert_held(&sev_cmd_mutex);\n\n\tif (!sev_init_ex_buffer)\n\t\treturn;\n\n\t/*\n\t * Only a few platform commands modify the SPI/NV area, but none of the\n\t * non-platform commands do. Only INIT(_EX), PLATFORM_RESET, PEK_GEN,\n\t * PEK_CERT_IMPORT, and PDH_GEN do.\n\t */\n\tswitch (cmd_id) {\n\tcase SEV_CMD_FACTORY_RESET:\n\tcase SEV_CMD_INIT_EX:\n\tcase SEV_CMD_PDH_GEN:\n\tcase SEV_CMD_PEK_CERT_IMPORT:\n\tcase SEV_CMD_PEK_GEN:\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tsev_write_init_ex_file();\n}",
        "static void aq_check_txsa_expiration(struct aq_nic_s *nic)\n{\n\tu32 egress_sa_expired, egress_sa_threshold_expired;\n\tstruct aq_macsec_cfg *cfg = nic->macsec_cfg;\n\tstruct aq_hw_s *hw = nic->aq_hw;": "static void aq_check_txsa_expiration(struct aq_nic_s *nic)\n{\n\tu32 egress_sa_expired, egress_sa_threshold_expired;\n\tstruct aq_macsec_cfg *cfg = nic->macsec_cfg;\n\tstruct aq_hw_s *hw = nic->aq_hw;\n\tstruct aq_macsec_txsc *aq_txsc;\n\tconst struct macsec_secy *secy;\n\tint sc_idx = 0, txsc_idx = 0;\n\tenum aq_macsec_sc_sa sc_sa;\n\tstruct macsec_tx_sa *tx_sa;\n\tunsigned char an = 0;\n\tint ret;\n\tint i;\n\n\tsc_sa = cfg->sc_sa;\n\n\tret = aq_mss_get_egress_sa_expired(hw, &egress_sa_expired);\n\tif (unlikely(ret))\n\t\treturn;\n\n\tret = aq_mss_get_egress_sa_threshold_expired(hw,\n\t\t&egress_sa_threshold_expired);\n\n\tfor (i = 0; i < AQ_MACSEC_MAX_SA; i++) {\n\t\tif (egress_sa_expired & BIT(i)) {\n\t\t\tan = aq_sa_from_sa_idx(sc_sa, i);\n\t\t\tsc_idx = aq_sc_idx_from_sa_idx(sc_sa, i);\n\t\t\ttxsc_idx = aq_get_txsc_idx_from_sc_idx(sc_sa, sc_idx);\n\t\t\tif (txsc_idx < 0)\n\t\t\t\tcontinue;\n\n\t\t\taq_txsc = &cfg->aq_txsc[txsc_idx];\n\t\t\tif (!(cfg->txsc_idx_busy & BIT(txsc_idx))) {\n\t\t\t\tnetdev_warn(nic->ndev,\n\t\t\t\t\t\"PN threshold expired on invalid TX SC\");\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tsecy = aq_txsc->sw_secy;\n\t\t\tif (!netif_running(secy->netdev)) {\n\t\t\t\tnetdev_warn(nic->ndev,\n\t\t\t\t\t\"PN threshold expired on down TX SC\");\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (unlikely(!(aq_txsc->tx_sa_idx_busy & BIT(an)))) {\n\t\t\t\tnetdev_warn(nic->ndev,\n\t\t\t\t\t\"PN threshold expired on invalid TX SA\");\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\ttx_sa = rcu_dereference_bh(secy->tx_sc.sa[an]);\n\t\t\tmacsec_pn_wrapped((struct macsec_secy *)secy, tx_sa);\n\t\t}\n\t}\n\n\taq_mss_set_egress_sa_expired(hw, egress_sa_expired);\n\tif (likely(!ret))\n\t\taq_mss_set_egress_sa_threshold_expired(hw,\n\t\t\tegress_sa_threshold_expired);\n}",
        "static struct bpf_prog *bpf_migrate_filter(struct bpf_prog *fp)\n{\n\tstruct sock_filter *old_prog;\n\tstruct bpf_prog *old_fp;\n\tint err, new_len, old_len = fp->len;": "static struct bpf_prog *bpf_migrate_filter(struct bpf_prog *fp)\n{\n\tstruct sock_filter *old_prog;\n\tstruct bpf_prog *old_fp;\n\tint err, new_len, old_len = fp->len;\n\tbool seen_ld_abs = false;\n\n\t/* We are free to overwrite insns et al right here as it won't be used at\n\t * this point in time anymore internally after the migration to the eBPF\n\t * instruction representation.\n\t */\n\tBUILD_BUG_ON(sizeof(struct sock_filter) !=\n\t\t     sizeof(struct bpf_insn));\n\n\t/* Conversion cannot happen on overlapping memory areas,\n\t * so we need to keep the user BPF around until the 2nd\n\t * pass. At this time, the user BPF is stored in fp->insns.\n\t */\n\told_prog = kmemdup(fp->insns, old_len * sizeof(struct sock_filter),\n\t\t\t   GFP_KERNEL | __GFP_NOWARN);\n\tif (!old_prog) {\n\t\terr = -ENOMEM;\n\t\tgoto out_err;\n\t}\n\n\t/* 1st pass: calculate the new program length. */\n\terr = bpf_convert_filter(old_prog, old_len, NULL, &new_len,\n\t\t\t\t &seen_ld_abs);\n\tif (err)\n\t\tgoto out_err_free;\n\n\t/* Expand fp for appending the new filter representation. */\n\told_fp = fp;\n\tfp = bpf_prog_realloc(old_fp, bpf_prog_size(new_len), 0);\n\tif (!fp) {\n\t\t/* The old_fp is still around in case we couldn't\n\t\t * allocate new memory, so uncharge on that one.\n\t\t */\n\t\tfp = old_fp;\n\t\terr = -ENOMEM;\n\t\tgoto out_err_free;\n\t}\n\n\tfp->len = new_len;\n\n\t/* 2nd pass: remap sock_filter insns into bpf_insn insns. */\n\terr = bpf_convert_filter(old_prog, old_len, fp, &new_len,\n\t\t\t\t &seen_ld_abs);\n\tif (err)\n\t\t/* 2nd bpf_convert_filter() can fail only if it fails\n\t\t * to allocate memory, remapping must succeed. Note,\n\t\t * that at this time old_fp has already been released\n\t\t * by krealloc().\n\t\t */\n\t\tgoto out_err_free;\n\n\tfp = bpf_prog_select_runtime(fp, &err);\n\tif (err)\n\t\tgoto out_err_free;\n\n\tkfree(old_prog);\n\treturn fp;\n\nout_err_free:\n\tkfree(old_prog);\nout_err:\n\t__bpf_prog_release(fp);\n\treturn ERR_PTR(err);\n}",
        "static int imx274_apply_trimming(struct stimx274 *imx274)\n{\n\tu32 h_start;\n\tu32 h_end;\n\tu32 hmax;": "static int imx274_apply_trimming(struct stimx274 *imx274)\n{\n\tu32 h_start;\n\tu32 h_end;\n\tu32 hmax;\n\tu32 v_cut;\n\ts32 v_pos;\n\tu32 write_v_size;\n\tu32 y_out_size;\n\tint err;\n\n\th_start = imx274->crop.left + 12;\n\th_end = h_start + imx274->crop.width;\n\n\t/* Use the minimum allowed value of HMAX */\n\t/* Note: except in mode 1, (width / 16 + 23) is always < hmax_min */\n\t/* Note: 260 is the minimum HMAX in all implemented modes */\n\thmax = max_t(u32, 260, (imx274->crop.width) / 16 + 23);\n\n\t/* invert v_pos if VFLIP */\n\tv_pos = imx274->ctrls.vflip->cur.val ?\n\t\t(-imx274->crop.top / 2) : (imx274->crop.top / 2);\n\tv_cut = (IMX274_MAX_HEIGHT - imx274->crop.height) / 2;\n\twrite_v_size = imx274->crop.height + 22;\n\ty_out_size   = imx274->crop.height;\n\n\terr = imx274_write_mbreg(imx274, IMX274_HMAX_REG_LSB, hmax, 2);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_HTRIM_EN_REG, 1, 1);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_HTRIM_START_REG_LSB,\n\t\t\t\t\t h_start, 2);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_HTRIM_END_REG_LSB,\n\t\t\t\t\t h_end, 2);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_VWIDCUTEN_REG, 1, 1);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_VWIDCUT_REG_LSB,\n\t\t\t\t\t v_cut, 2);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_VWINPOS_REG_LSB,\n\t\t\t\t\t v_pos, 2);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_WRITE_VSIZE_REG_LSB,\n\t\t\t\t\t write_v_size, 2);\n\tif (!err)\n\t\terr = imx274_write_mbreg(imx274, IMX274_Y_OUT_SIZE_REG_LSB,\n\t\t\t\t\t y_out_size, 2);\n\n\treturn err;\n}",
        "static int __init dm_init(void)\n{\n\tconst int count = ARRAY_SIZE(_inits);\n\tint r, i;\n": "static int __init dm_init(void)\n{\n\tconst int count = ARRAY_SIZE(_inits);\n\tint r, i;\n\n#if (IS_ENABLED(CONFIG_IMA) && !IS_ENABLED(CONFIG_IMA_DISABLE_HTABLE))\n\tDMWARN(\"CONFIG_IMA_DISABLE_HTABLE is disabled.\"\n\t       \" Duplicate IMA measurements will not be recorded in the IMA log.\");\n#endif\n\n\tfor (i = 0; i < count; i++) {\n\t\tr = _inits[i]();\n\t\tif (r)\n\t\t\tgoto bad;\n\t}\n\n\treturn 0;\nbad:\n\twhile (i--)\n\t\t_exits[i]();\n\n\treturn r;\n}",
        "static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)\n{\n\tconst struct ca0132_alt_out_set_quirk_data *quirk_data;\n\tconst struct ca0132_alt_out_set_info *out_info;\n\tstruct ca0132_spec *spec = codec->spec;": "static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)\n{\n\tconst struct ca0132_alt_out_set_quirk_data *quirk_data;\n\tconst struct ca0132_alt_out_set_info *out_info;\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int i, gpio_data;\n\tint err;\n\n\tca0132_alt_select_out_get_quirk_data(codec, &quirk_data);\n\tif (!quirk_data)\n\t\treturn 0;\n\n\tout_info = &quirk_data->out_set_info[spec->cur_out_type];\n\tif (quirk_data->is_ae_series)\n\t\tae5_mmio_select_out(codec);\n\n\tif (out_info->has_hda_gpio) {\n\t\tgpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,\n\t\t\t\tAC_VERB_GET_GPIO_DATA, 0);\n\n\t\tif (out_info->hda_gpio_set)\n\t\t\tgpio_data |= (1 << out_info->hda_gpio_pin);\n\t\telse\n\t\t\tgpio_data &= ~(1 << out_info->hda_gpio_pin);\n\n\t\tsnd_hda_codec_write(codec, codec->core.afg, 0,\n\t\t\t\t    AC_VERB_SET_GPIO_DATA, gpio_data);\n\t}\n\n\tif (out_info->mmio_gpio_count) {\n\t\tfor (i = 0; i < out_info->mmio_gpio_count; i++) {\n\t\t\tca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],\n\t\t\t\t\tout_info->mmio_gpio_set[i]);\n\t\t}\n\t}\n\n\tif (out_info->scp_cmds_count) {\n\t\tfor (i = 0; i < out_info->scp_cmds_count; i++) {\n\t\t\terr = dspio_set_uint_param(codec,\n\t\t\t\t\tout_info->scp_cmd_mid[i],\n\t\t\t\t\tout_info->scp_cmd_req[i],\n\t\t\t\t\tout_info->scp_cmd_val[i]);\n\t\t\tif (err < 0)\n\t\t\t\treturn err;\n\t\t}\n\t}\n\n\tchipio_set_control_param(codec, 0x0d, out_info->dac2port);\n\n\tif (out_info->has_chipio_write) {\n\t\tchipio_write(codec, out_info->chipio_write_addr,\n\t\t\t\tout_info->chipio_write_data);\n\t}\n\n\tif (quirk_data->has_headphone_gain) {\n\t\tif (spec->cur_out_type != HEADPHONE_OUT) {\n\t\t\tif (quirk_data->is_ae_series)\n\t\t\t\tae5_headphone_gain_set(codec, 2);\n\t\t\telse\n\t\t\t\tzxr_headphone_gain_set(codec, 0);\n\t\t} else {\n\t\t\tif (quirk_data->is_ae_series)\n\t\t\t\tae5_headphone_gain_set(codec,\n\t\t\t\t\t\tspec->ae5_headphone_gain_val);\n\t\t\telse\n\t\t\t\tzxr_headphone_gain_set(codec,\n\t\t\t\t\t\tspec->zxr_gain_set);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static void imgu_css_pipe_cleanup(struct imgu_css *css, unsigned int pipe)\n{\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tunsigned int p, q, i, abi_buf_num;": "static void imgu_css_pipe_cleanup(struct imgu_css *css, unsigned int pipe)\n{\n\tstruct imgu_device *imgu = dev_get_drvdata(css->dev);\n\tstruct imgu_css_pipe *css_pipe = &css->pipes[pipe];\n\tunsigned int p, q, i, abi_buf_num;\n\n\timgu_css_binary_cleanup(css, pipe);\n\n\tfor (q = 0; q < IPU3_CSS_QUEUES; q++) {\n\t\tabi_buf_num = ARRAY_SIZE(css_pipe->abi_buffers[q]);\n\t\tfor (i = 0; i < abi_buf_num; i++)\n\t\t\timgu_dmamap_free(imgu, &css_pipe->abi_buffers[q][i]);\n\t}\n\n\tfor (p = 0; p < IPU3_CSS_PIPE_ID_NUM; p++)\n\t\tfor (i = 0; i < IMGU_ABI_MAX_STAGES; i++) {\n\t\t\timgu_dmamap_free(imgu,\n\t\t\t\t\t &css_pipe->xmem_sp_stage_ptrs[p][i]);\n\t\t\timgu_dmamap_free(imgu,\n\t\t\t\t\t &css_pipe->xmem_isp_stage_ptrs[p][i]);\n\t\t}\n\n\timgu_dmamap_free(imgu, &css_pipe->sp_ddr_ptrs);\n}",
        "static void release_attributes_data(void)\n{\n\tmutex_lock(&wmi_priv.mutex);\n\texit_enum_attributes();\n\texit_int_attributes();": "static void release_attributes_data(void)\n{\n\tmutex_lock(&wmi_priv.mutex);\n\texit_enum_attributes();\n\texit_int_attributes();\n\texit_str_attributes();\n\texit_po_attributes();\n\tif (wmi_priv.authentication_dir_kset) {\n\t\tdestroy_attribute_objs(wmi_priv.authentication_dir_kset);\n\t\tkset_unregister(wmi_priv.authentication_dir_kset);\n\t\twmi_priv.authentication_dir_kset = NULL;\n\t}\n\tif (wmi_priv.main_dir_kset) {\n\t\tsysfs_remove_file(&wmi_priv.main_dir_kset->kobj, &reset_bios.attr);\n\t\tsysfs_remove_file(&wmi_priv.main_dir_kset->kobj, &pending_reboot.attr);\n\t\tdestroy_attribute_objs(wmi_priv.main_dir_kset);\n\t\tkset_unregister(wmi_priv.main_dir_kset);\n\t\twmi_priv.main_dir_kset = NULL;\n\t}\n\tmutex_unlock(&wmi_priv.mutex);\n}",
        "static void kdamond_apply_schemes(struct damon_ctx *c)\n{\n\tstruct damon_target *t;\n\tstruct damon_region *r, *next_r;\n\tstruct damos *s;": "static void kdamond_apply_schemes(struct damon_ctx *c)\n{\n\tstruct damon_target *t;\n\tstruct damon_region *r, *next_r;\n\tstruct damos *s;\n\n\tdamon_for_each_scheme(s, c) {\n\t\tstruct damos_quota *quota = &s->quota;\n\t\tunsigned long cumulated_sz;\n\t\tunsigned int score, max_score = 0;\n\n\t\tif (!s->wmarks.activated)\n\t\t\tcontinue;\n\n\t\tif (!quota->ms && !quota->sz)\n\t\t\tcontinue;\n\n\t\t/* New charge window starts */\n\t\tif (time_after_eq(jiffies, quota->charged_from +\n\t\t\t\t\tmsecs_to_jiffies(\n\t\t\t\t\t\tquota->reset_interval))) {\n\t\t\tif (quota->esz && quota->charged_sz >= quota->esz)\n\t\t\t\ts->stat.qt_exceeds++;\n\t\t\tquota->total_charged_sz += quota->charged_sz;\n\t\t\tquota->charged_from = jiffies;\n\t\t\tquota->charged_sz = 0;\n\t\t\tdamos_set_effective_quota(quota);\n\t\t}\n\n\t\tif (!c->ops.get_scheme_score)\n\t\t\tcontinue;\n\n\t\t/* Fill up the score histogram */\n\t\tmemset(quota->histogram, 0, sizeof(quota->histogram));\n\t\tdamon_for_each_target(t, c) {\n\t\t\tdamon_for_each_region(r, t) {\n\t\t\t\tif (!__damos_valid_target(r, s))\n\t\t\t\t\tcontinue;\n\t\t\t\tscore = c->ops.get_scheme_score(\n\t\t\t\t\t\tc, t, r, s);\n\t\t\t\tquota->histogram[score] +=\n\t\t\t\t\tr->ar.end - r->ar.start;\n\t\t\t\tif (score > max_score)\n\t\t\t\t\tmax_score = score;\n\t\t\t}\n\t\t}\n\n\t\t/* Set the min score limit */\n\t\tfor (cumulated_sz = 0, score = max_score; ; score--) {\n\t\t\tcumulated_sz += quota->histogram[score];\n\t\t\tif (cumulated_sz >= quota->esz || !score)\n\t\t\t\tbreak;\n\t\t}\n\t\tquota->min_score = score;\n\t}\n\n\tdamon_for_each_target(t, c) {\n\t\tdamon_for_each_region_safe(r, next_r, t)\n\t\t\tdamon_do_apply_schemes(c, t, r);\n\t}\n}",
        "static inline u32 iavf_buildreg_itr(const int type, u16 itr)\n{\n\tu32 val;\n\n\t/* We don't bother with setting the CLEARPBA bit as the data sheet": "static inline u32 iavf_buildreg_itr(const int type, u16 itr)\n{\n\tu32 val;\n\n\t/* We don't bother with setting the CLEARPBA bit as the data sheet\n\t * points out doing so is \"meaningless since it was already\n\t * auto-cleared\". The auto-clearing happens when the interrupt is\n\t * asserted.\n\t *\n\t * Hardware errata 28 for also indicates that writing to a\n\t * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear\n\t * an event in the PBA anyway so we need to rely on the automask\n\t * to hold pending events for us until the interrupt is re-enabled\n\t *\n\t * The itr value is reported in microseconds, and the register\n\t * value is recorded in 2 microsecond units. For this reason we\n\t * only need to shift by the interval shift - 1 instead of the\n\t * full value.\n\t */\n\titr &= IAVF_ITR_MASK;\n\n\tval = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |\n\t      (type << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n\t      (itr << (IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));\n\n\treturn val;\n}",
        "static int mock_get_log(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd)\n{\n\tstruct cxl_mbox_get_log *gl = cmd->payload_in;\n\tu32 offset = le32_to_cpu(gl->offset);\n\tu32 length = le32_to_cpu(gl->length);": "static int mock_get_log(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd)\n{\n\tstruct cxl_mbox_get_log *gl = cmd->payload_in;\n\tu32 offset = le32_to_cpu(gl->offset);\n\tu32 length = le32_to_cpu(gl->length);\n\tuuid_t uuid = DEFINE_CXL_CEL_UUID;\n\tvoid *data = &mock_cel;\n\n\tif (cmd->size_in < sizeof(*gl))\n\t\treturn -EINVAL;\n\tif (length > cxlds->payload_size)\n\t\treturn -EINVAL;\n\tif (offset + length > sizeof(mock_cel))\n\t\treturn -EINVAL;\n\tif (!uuid_equal(&gl->uuid, &uuid))\n\t\treturn -EINVAL;\n\tif (length > cmd->size_out)\n\t\treturn -EINVAL;\n\n\tmemcpy(cmd->payload_out, data + offset, length);\n\n\treturn 0;\n}",
        "static int runtest_dar_outside(void)\n{\n\tvoid *target;\n\tvolatile __u16 temp16;\n\tvolatile __u64 temp64;": "static int runtest_dar_outside(void)\n{\n\tvoid *target;\n\tvolatile __u16 temp16;\n\tvolatile __u64 temp64;\n\tint break_fd;\n\tunsigned long long breaks;\n\tint fail = 0;\n\tsize_t res;\n\n\ttarget = malloc(8);\n\tif (!target) {\n\t\tperror(\"malloc failed\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\t/* watch middle half of target array */\n\tbreak_fd = perf_process_event_open(HW_BREAKPOINT_RW, (__u64)(target + 2), 4);\n\tif (break_fd < 0) {\n\t\tfree(target);\n\t\tperror(\"perf_process_event_open\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\t/* Shouldn't hit. */\n\tioctl(break_fd, PERF_EVENT_IOC_RESET);\n\tioctl(break_fd, PERF_EVENT_IOC_ENABLE);\n\ttemp16 = *((__u16 *)target);\n\t*((__u16 *)target) = temp16;\n\tioctl(break_fd, PERF_EVENT_IOC_DISABLE);\n\tres = read(break_fd, &breaks, sizeof(unsigned long long));\n\tassert(res == sizeof(unsigned long long));\n\tif (breaks == 0) {\n\t\tprintf(\"TESTED: No overlap\\n\");\n\t} else {\n\t\tprintf(\"FAILED: No overlap: %lld != 0\\n\", breaks);\n\t\tfail = 1;\n\t}\n\n\t/* Hit */\n\tioctl(break_fd, PERF_EVENT_IOC_RESET);\n\tioctl(break_fd, PERF_EVENT_IOC_ENABLE);\n\ttemp16 = *((__u16 *)(target + 1));\n\t*((__u16 *)(target + 1)) = temp16;\n\tioctl(break_fd, PERF_EVENT_IOC_DISABLE);\n\tres = read(break_fd, &breaks, sizeof(unsigned long long));\n\tassert(res == sizeof(unsigned long long));\n\tif (breaks == 2) {\n\t\tprintf(\"TESTED: Partial overlap\\n\");\n\t} else {\n\t\tprintf(\"FAILED: Partial overlap: %lld != 2\\n\", breaks);\n\t\tfail = 1;\n\t}\n\n\t/* Hit */\n\tioctl(break_fd, PERF_EVENT_IOC_RESET);\n\tioctl(break_fd, PERF_EVENT_IOC_ENABLE);\n\ttemp16 = *((__u16 *)(target + 5));\n\t*((__u16 *)(target + 5)) = temp16;\n\tioctl(break_fd, PERF_EVENT_IOC_DISABLE);\n\tres = read(break_fd, &breaks, sizeof(unsigned long long));\n\tassert(res == sizeof(unsigned long long));\n\tif (breaks == 2) {\n\t\tprintf(\"TESTED: Partial overlap\\n\");\n\t} else {\n\t\tprintf(\"FAILED: Partial overlap: %lld != 2\\n\", breaks);\n\t\tfail = 1;\n\t}\n\n\t/* Shouldn't Hit */\n\tioctl(break_fd, PERF_EVENT_IOC_RESET);\n\tioctl(break_fd, PERF_EVENT_IOC_ENABLE);\n\ttemp16 = *((__u16 *)(target + 6));\n\t*((__u16 *)(target + 6)) = temp16;\n\tioctl(break_fd, PERF_EVENT_IOC_DISABLE);\n\tres = read(break_fd, &breaks, sizeof(unsigned long long));\n\tassert(res == sizeof(unsigned long long));\n\tif (breaks == 0) {\n\t\tprintf(\"TESTED: No overlap\\n\");\n\t} else {\n\t\tprintf(\"FAILED: No overlap: %lld != 0\\n\", breaks);\n\t\tfail = 1;\n\t}\n\n\t/* Hit */\n\tioctl(break_fd, PERF_EVENT_IOC_RESET);\n\tioctl(break_fd, PERF_EVENT_IOC_ENABLE);\n\ttemp64 = *((__u64 *)target);\n\t*((__u64 *)target) = temp64;\n\tioctl(break_fd, PERF_EVENT_IOC_DISABLE);\n\tres = read(break_fd, &breaks, sizeof(unsigned long long));\n\tassert(res == sizeof(unsigned long long));\n\tif (breaks == 2) {\n\t\tprintf(\"TESTED: Full overlap\\n\");\n\t} else {\n\t\tprintf(\"FAILED: Full overlap: %lld != 2\\n\", breaks);\n\t\tfail = 1;\n\t}\n\n\tfree(target);\n\tclose(break_fd);\n\treturn fail;\n}",
        "static void dcon_wiggle_xo_1_5(void)\n{\n\tint x;\n\n\t/*": "static void dcon_wiggle_xo_1_5(void)\n{\n\tint x;\n\n\t/*\n\t * According to HiMax, when powering the DCON up we should hold\n\t * SMB_DATA high for 8 SMB_CLK cycles.  This will force the DCON\n\t * state machine to reset to a (sane) initial state.  Mitch Bradley\n\t * did some testing and discovered that holding for 16 SMB_CLK cycles\n\t * worked a lot more reliably, so that's what we do here.\n\t */\n\tset_i2c_line(1, 1);\n\n\tfor (x = 0; x < 16; x++) {\n\t\tudelay(5);\n\t\tset_i2c_line(1, 0);\n\t\tudelay(5);\n\t\tset_i2c_line(1, 1);\n\t}\n\tudelay(5);\n\n\t/* set   PMIO_Rx52[6] to enable SCI/SMI on gpio12 */\n\toutb(inb(VX855_GPI_SCI_SMI) | BIT_GPIO12, VX855_GPI_SCI_SMI);\n}",
        "static void update_capture_data_from_header(struct vicodec_ctx *ctx)\n{\n\tstruct vicodec_q_data *q_dst = get_q_data(ctx,\n\t\t\t\t\t\t  V4L2_BUF_TYPE_VIDEO_CAPTURE);\n\tconst struct fwht_cframe_hdr *p_hdr = &ctx->state.header;": "static void update_capture_data_from_header(struct vicodec_ctx *ctx)\n{\n\tstruct vicodec_q_data *q_dst = get_q_data(ctx,\n\t\t\t\t\t\t  V4L2_BUF_TYPE_VIDEO_CAPTURE);\n\tconst struct fwht_cframe_hdr *p_hdr = &ctx->state.header;\n\tconst struct v4l2_fwht_pixfmt_info *info = info_from_header(p_hdr);\n\tunsigned int flags = ntohl(p_hdr->flags);\n\tunsigned int hdr_width_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;\n\tunsigned int hdr_height_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;\n\n\t/*\n\t * This function should not be used by a stateless codec since\n\t * it changes values in q_data that are not request specific\n\t */\n\tWARN_ON(ctx->is_stateless);\n\n\tq_dst->info = info;\n\tq_dst->visible_width = ntohl(p_hdr->width);\n\tq_dst->visible_height = ntohl(p_hdr->height);\n\tq_dst->coded_width = vic_round_dim(q_dst->visible_width, hdr_width_div);\n\tq_dst->coded_height = vic_round_dim(q_dst->visible_height,\n\t\t\t\t\t    hdr_height_div);\n\n\tq_dst->sizeimage = q_dst->coded_width * q_dst->coded_height *\n\t\tq_dst->info->sizeimage_mult / q_dst->info->sizeimage_div;\n\tctx->state.colorspace = ntohl(p_hdr->colorspace);\n\n\tctx->state.xfer_func = ntohl(p_hdr->xfer_func);\n\tctx->state.ycbcr_enc = ntohl(p_hdr->ycbcr_enc);\n\tctx->state.quantization = ntohl(p_hdr->quantization);\n}",
        "static void __gsi_trans_commit(struct gsi_trans *trans, bool ring_db)\n{\n\tstruct gsi_channel *channel = &trans->gsi->channel[trans->channel_id];\n\tstruct gsi_ring *ring = &channel->tre_ring;\n\tenum ipa_cmd_opcode opcode = IPA_CMD_NONE;": "static void __gsi_trans_commit(struct gsi_trans *trans, bool ring_db)\n{\n\tstruct gsi_channel *channel = &trans->gsi->channel[trans->channel_id];\n\tstruct gsi_ring *ring = &channel->tre_ring;\n\tenum ipa_cmd_opcode opcode = IPA_CMD_NONE;\n\tbool bei = channel->toward_ipa;\n\tstruct gsi_tre *dest_tre;\n\tstruct scatterlist *sg;\n\tu32 byte_count = 0;\n\tu8 *cmd_opcode;\n\tu32 avail;\n\tu32 i;\n\n\tWARN_ON(!trans->used);\n\n\t/* Consume the entries.  If we cross the end of the ring while\n\t * filling them we'll switch to the beginning to finish.\n\t * If there is no info array we're doing a simple data\n\t * transfer request, whose opcode is IPA_CMD_NONE.\n\t */\n\tcmd_opcode = channel->command ? &trans->cmd_opcode[0] : NULL;\n\tavail = ring->count - ring->index % ring->count;\n\tdest_tre = gsi_ring_virt(ring, ring->index);\n\tfor_each_sg(trans->sgl, sg, trans->used, i) {\n\t\tbool last_tre = i == trans->used - 1;\n\t\tdma_addr_t addr = sg_dma_address(sg);\n\t\tu32 len = sg_dma_len(sg);\n\n\t\tbyte_count += len;\n\t\tif (!avail--)\n\t\t\tdest_tre = gsi_ring_virt(ring, 0);\n\t\tif (cmd_opcode)\n\t\t\topcode = *cmd_opcode++;\n\n\t\tgsi_trans_tre_fill(dest_tre, addr, len, last_tre, bei, opcode);\n\t\tdest_tre++;\n\t}\n\tring->index += trans->used;\n\n\tif (channel->toward_ipa) {\n\t\t/* We record TX bytes when they are sent */\n\t\ttrans->len = byte_count;\n\t\ttrans->trans_count = channel->trans_count;\n\t\ttrans->byte_count = channel->byte_count;\n\t\tchannel->trans_count++;\n\t\tchannel->byte_count += byte_count;\n\t}\n\n\t/* Associate the last TRE with the transaction */\n\tgsi_channel_trans_map(channel, ring->index - 1, trans);\n\n\tgsi_trans_move_pending(trans);\n\n\t/* Ring doorbell if requested, or if all TREs are allocated */\n\tif (ring_db || !atomic_read(&channel->trans_info.tre_avail)) {\n\t\t/* Report what we're handing off to hardware for TX channels */\n\t\tif (channel->toward_ipa)\n\t\t\tgsi_channel_tx_queued(channel);\n\t\tgsi_channel_doorbell(channel);\n\t}\n}",
        "static void tw5864_handle_frame(struct tw5864_h264_frame *frame)\n{\n#define SKIP_VLCBUF_BYTES 3\n\tstruct tw5864_input *input = frame->input;\n\tstruct tw5864_dev *dev = input->root;": "static void tw5864_handle_frame(struct tw5864_h264_frame *frame)\n{\n#define SKIP_VLCBUF_BYTES 3\n\tstruct tw5864_input *input = frame->input;\n\tstruct tw5864_dev *dev = input->root;\n\tstruct tw5864_buf *vb;\n\tstruct vb2_v4l2_buffer *v4l2_buf;\n\tint frame_len = frame->vlc_len - SKIP_VLCBUF_BYTES;\n\tu8 *dst = input->buf_cur_ptr;\n\tu8 tail_mask, vlc_mask = 0;\n\tint i;\n\tu8 vlc_first_byte = ((u8 *)(frame->vlc.addr + SKIP_VLCBUF_BYTES))[0];\n\tunsigned long flags;\n\tint zero_run;\n\tu8 *src;\n\tu8 *src_end;\n\n#ifdef DEBUG\n\tif (frame->checksum !=\n\t    tw5864_vlc_checksum((u32 *)frame->vlc.addr, frame_len))\n\t\tdev_err(&dev->pci->dev,\n\t\t\t\"Checksum of encoded frame doesn't match!\\n\");\n#endif\n\n\tspin_lock_irqsave(&input->slock, flags);\n\tvb = input->vb;\n\tinput->vb = NULL;\n\tspin_unlock_irqrestore(&input->slock, flags);\n\n\tif (!vb) { /* Gone because of disabling */\n\t\tdev_dbg(&dev->pci->dev, \"vb is empty, dropping frame\\n\");\n\t\treturn;\n\t}\n\n\tv4l2_buf = to_vb2_v4l2_buffer(&vb->vb.vb2_buf);\n\n\t/*\n\t * Check for space.\n\t * Mind the overhead of startcode emulation prevention.\n\t */\n\tif (input->buf_cur_space_left < frame_len * 5 / 4) {\n\t\tdev_err_once(&dev->pci->dev,\n\t\t\t     \"Left space in vb2 buffer, %d bytes, is less than considered safely enough to put frame of length %d. Dropping this frame.\\n\",\n\t\t\t     input->buf_cur_space_left, frame_len);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < 8 - input->tail_nb_bits; i++)\n\t\tvlc_mask |= 1 << i;\n\ttail_mask = (~vlc_mask) & 0xff;\n\n\tdst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask);\n\tframe_len--;\n\tdst++;\n\n\t/* H.264 startcode emulation prevention */\n\tsrc = frame->vlc.addr + SKIP_VLCBUF_BYTES + 1;\n\tsrc_end = src + frame_len;\n\tzero_run = 0;\n\tfor (; src < src_end; src++) {\n\t\tif (zero_run < 2) {\n\t\t\tif (*src == 0)\n\t\t\t\t++zero_run;\n\t\t\telse\n\t\t\t\tzero_run = 0;\n\t\t} else {\n\t\t\tif ((*src & ~0x03) == 0)\n\t\t\t\t*dst++ = 0x03;\n\t\t\tzero_run = *src == 0;\n\t\t}\n\t\t*dst++ = *src;\n\t}\n\n\tvb2_set_plane_payload(&vb->vb.vb2_buf, 0,\n\t\t\t      dst - (u8 *)vb2_plane_vaddr(&vb->vb.vb2_buf, 0));\n\n\tvb->vb.vb2_buf.timestamp = frame->timestamp;\n\tv4l2_buf->field = V4L2_FIELD_INTERLACED;\n\tv4l2_buf->sequence = frame->seqno;\n\n\t/* Check for motion flags */\n\tif (frame->gop_seqno /* P-frame */ &&\n\t    tw5864_is_motion_triggered(frame)) {\n\t\tstruct v4l2_event ev = {\n\t\t\t.type = V4L2_EVENT_MOTION_DET,\n\t\t\t.u.motion_det = {\n\t\t\t\t.flags = V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ,\n\t\t\t\t.frame_sequence = v4l2_buf->sequence,\n\t\t\t},\n\t\t};\n\n\t\tv4l2_event_queue(&input->vdev, &ev);\n\t}\n\n\tvb2_buffer_done(&vb->vb.vb2_buf, VB2_BUF_STATE_DONE);\n}",
        "static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)\n{\n\tu32 frames = MALONE_VC1_RCV_NUM_FRAMES;\n\tu32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;\n": "static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)\n{\n\tu32 frames = MALONE_VC1_RCV_NUM_FRAMES;\n\tu32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;\n\n\t/* 0-2 Number of frames, used default value 0xFF */\n\tdst[0] = frames;\n\tdst[1] = frames >> 8;\n\tdst[2] = frames >> 16;\n\n\t/* 3 RCV version, used V1 */\n\tdst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;\n\n\t/* 4-7 extension data size */\n\tdst[4] = ext_data_size;\n\tdst[5] = ext_data_size >> 8;\n\tdst[6] = ext_data_size >> 16;\n\tdst[7] = ext_data_size >> 24;\n\t/* 8-11 extension data */\n\tdst[8] = src[0];\n\tdst[9] = src[1];\n\tdst[10] = src[2];\n\tdst[11] = src[3];\n\n\t/* height */\n\tdst[12] = height;\n\tdst[13] = (height >> 8) & 0xff;\n\tdst[14] = (height >> 16) & 0xff;\n\tdst[15] = (height >> 24) & 0xff;\n\t/* width */\n\tdst[16] = width;\n\tdst[17] = (width >> 8) & 0xff;\n\tdst[18] = (width >> 16) & 0xff;\n\tdst[19] = (width >> 24) & 0xff;\n}",
        "static void ieee802154_if_setup(struct net_device *dev)\n{\n\tdev->addr_len\t\t= IEEE802154_EXTENDED_ADDR_LEN;\n\tmemset(dev->broadcast, 0xff, IEEE802154_EXTENDED_ADDR_LEN);\n": "static void ieee802154_if_setup(struct net_device *dev)\n{\n\tdev->addr_len\t\t= IEEE802154_EXTENDED_ADDR_LEN;\n\tmemset(dev->broadcast, 0xff, IEEE802154_EXTENDED_ADDR_LEN);\n\n\t/* Let hard_header_len set to IEEE802154_MIN_HEADER_LEN. AF_PACKET\n\t * will not send frames without any payload, but ack frames\n\t * has no payload, so substract one that we can send a 3 bytes\n\t * frame. The xmit callback assumes at least a hard header where two\n\t * bytes fc and sequence field are set.\n\t */\n\tdev->hard_header_len\t= IEEE802154_MIN_HEADER_LEN - 1;\n\t/* The auth_tag header is for security and places in private payload\n\t * room of mac frame which stucks between payload and FCS field.\n\t */\n\tdev->needed_tailroom\t= IEEE802154_MAX_AUTH_TAG_LEN +\n\t\t\t\t  IEEE802154_FCS_LEN;\n\t/* The mtu size is the payload without mac header in this case.\n\t * We have a dynamic length header with a minimum header length\n\t * which is hard_header_len. In this case we let mtu to the size\n\t * of maximum payload which is IEEE802154_MTU - IEEE802154_FCS_LEN -\n\t * hard_header_len. The FCS which is set by hardware or ndo_start_xmit\n\t * and the minimum mac header which can be evaluated inside driver\n\t * layer. The rest of mac header will be part of payload if greater\n\t * than hard_header_len.\n\t */\n\tdev->mtu\t\t= IEEE802154_MTU - IEEE802154_FCS_LEN -\n\t\t\t\t  dev->hard_header_len;\n\tdev->tx_queue_len\t= 300;\n\tdev->flags\t\t= IFF_NOARP | IFF_BROADCAST;\n}",
        "static void ops_run_check_p(struct stripe_head *sh, struct raid5_percpu *percpu)\n{\n\tint disks = sh->disks;\n\tint pd_idx = sh->pd_idx;\n\tint qd_idx = sh->qd_idx;": "static void ops_run_check_p(struct stripe_head *sh, struct raid5_percpu *percpu)\n{\n\tint disks = sh->disks;\n\tint pd_idx = sh->pd_idx;\n\tint qd_idx = sh->qd_idx;\n\tstruct page *xor_dest;\n\tunsigned int off_dest;\n\tstruct page **xor_srcs = to_addr_page(percpu, 0);\n\tunsigned int *off_srcs = to_addr_offs(sh, percpu);\n\tstruct dma_async_tx_descriptor *tx;\n\tstruct async_submit_ctl submit;\n\tint count;\n\tint i;\n\n\tpr_debug(\"%s: stripe %llu\\n\", __func__,\n\t\t(unsigned long long)sh->sector);\n\n\tBUG_ON(sh->batch_head);\n\tcount = 0;\n\txor_dest = sh->dev[pd_idx].page;\n\toff_dest = sh->dev[pd_idx].offset;\n\toff_srcs[count] = off_dest;\n\txor_srcs[count++] = xor_dest;\n\tfor (i = disks; i--; ) {\n\t\tif (i == pd_idx || i == qd_idx)\n\t\t\tcontinue;\n\t\toff_srcs[count] = sh->dev[i].offset;\n\t\txor_srcs[count++] = sh->dev[i].page;\n\t}\n\n\tinit_async_submit(&submit, 0, NULL, NULL, NULL,\n\t\t\t  to_addr_conv(sh, percpu, 0));\n\ttx = async_xor_val_offs(xor_dest, off_dest, xor_srcs, off_srcs, count,\n\t\t\t   RAID5_STRIPE_SIZE(sh->raid_conf),\n\t\t\t   &sh->ops.zero_sum_result, &submit);\n\n\tatomic_inc(&sh->count);\n\tinit_async_submit(&submit, ASYNC_TX_ACK, tx, ops_complete_check, sh, NULL);\n\ttx = async_trigger_callback(&submit);\n}",
        "static enum hrtimer_restart timerlat_irq(struct hrtimer *timer)\n{\n\tstruct osnoise_variables *osn_var = this_cpu_osn_var();\n\tstruct timerlat_variables *tlat;\n\tstruct timerlat_sample s;": "static enum hrtimer_restart timerlat_irq(struct hrtimer *timer)\n{\n\tstruct osnoise_variables *osn_var = this_cpu_osn_var();\n\tstruct timerlat_variables *tlat;\n\tstruct timerlat_sample s;\n\tu64 now;\n\tu64 diff;\n\n\t/*\n\t * I am not sure if the timer was armed for this CPU. So, get\n\t * the timerlat struct from the timer itself, not from this\n\t * CPU.\n\t */\n\ttlat = container_of(timer, struct timerlat_variables, timer);\n\n\tnow = ktime_to_ns(hrtimer_cb_get_time(&tlat->timer));\n\n\t/*\n\t * Enable the osnoise: events for thread an softirq.\n\t */\n\ttlat->tracing_thread = true;\n\n\tosn_var->thread.arrival_time = time_get();\n\n\t/*\n\t * A hardirq is running: the timer IRQ. It is for sure preempting\n\t * a thread, and potentially preempting a softirq.\n\t *\n\t * At this point, it is not interesting to know the duration of the\n\t * preempted thread (and maybe softirq), but how much time they will\n\t * delay the beginning of the execution of the timer thread.\n\t *\n\t * To get the correct (net) delay added by the softirq, its delta_start\n\t * is set as the IRQ one. In this way, at the return of the IRQ, the delta\n\t * start of the sofitrq will be zeroed, accounting then only the time\n\t * after that.\n\t *\n\t * The thread follows the same principle. However, if a softirq is\n\t * running, the thread needs to receive the softirq delta_start. The\n\t * reason being is that the softirq will be the last to be unfolded,\n\t * resseting the thread delay to zero.\n\t *\n\t * The PREEMPT_RT is a special case, though. As softirqs run as threads\n\t * on RT, moving the thread is enough.\n\t */\n\tif (!IS_ENABLED(CONFIG_PREEMPT_RT) && osn_var->softirq.delta_start) {\n\t\tcopy_int_safe_time(osn_var, &osn_var->thread.delta_start,\n\t\t\t\t   &osn_var->softirq.delta_start);\n\n\t\tcopy_int_safe_time(osn_var, &osn_var->softirq.delta_start,\n\t\t\t\t    &osn_var->irq.delta_start);\n\t} else {\n\t\tcopy_int_safe_time(osn_var, &osn_var->thread.delta_start,\n\t\t\t\t    &osn_var->irq.delta_start);\n\t}\n\n\t/*\n\t * Compute the current time with the expected time.\n\t */\n\tdiff = now - tlat->abs_period;\n\n\ttlat->count++;\n\ts.seqnum = tlat->count;\n\ts.timer_latency = diff;\n\ts.context = IRQ_CONTEXT;\n\n\ttrace_timerlat_sample(&s);\n\n\tif (osnoise_data.stop_tracing) {\n\t\tif (time_to_us(diff) >= osnoise_data.stop_tracing) {\n\n\t\t\t/*\n\t\t\t * At this point, if stop_tracing is set and <= print_stack,\n\t\t\t * print_stack is set and would be printed in the thread handler.\n\t\t\t *\n\t\t\t * Thus, print the stack trace as it is helpful to define the\n\t\t\t * root cause of an IRQ latency.\n\t\t\t */\n\t\t\tif (osnoise_data.stop_tracing <= osnoise_data.print_stack) {\n\t\t\t\ttimerlat_save_stack(0);\n\t\t\t\ttimerlat_dump_stack(time_to_us(diff));\n\t\t\t}\n\n\t\t\tosnoise_stop_tracing();\n\t\t\tnotify_new_max_latency(diff);\n\n\t\t\treturn HRTIMER_NORESTART;\n\t\t}\n\t}\n\n\twake_up_process(tlat->kthread);\n\n\tif (osnoise_data.print_stack)\n\t\ttimerlat_save_stack(0);\n\n\treturn HRTIMER_NORESTART;\n}",
        "static void *raid0_takeover(struct mddev *mddev)\n{\n\t/* raid0 can take over:\n\t *  raid4 - if all data disks are active.\n\t *  raid5 - providing it is Raid4 layout and one disk is faulty": "static void *raid0_takeover(struct mddev *mddev)\n{\n\t/* raid0 can take over:\n\t *  raid4 - if all data disks are active.\n\t *  raid5 - providing it is Raid4 layout and one disk is faulty\n\t *  raid10 - assuming we have all necessary active disks\n\t *  raid1 - with (N -1) mirror drives faulty\n\t */\n\n\tif (mddev->bitmap) {\n\t\tpr_warn(\"md/raid0: %s: cannot takeover array with bitmap\\n\",\n\t\t\tmdname(mddev));\n\t\treturn ERR_PTR(-EBUSY);\n\t}\n\tif (mddev->level == 4)\n\t\treturn raid0_takeover_raid45(mddev);\n\n\tif (mddev->level == 5) {\n\t\tif (mddev->layout == ALGORITHM_PARITY_N)\n\t\t\treturn raid0_takeover_raid45(mddev);\n\n\t\tpr_warn(\"md/raid0:%s: Raid can only takeover Raid5 with layout: %d\\n\",\n\t\t\tmdname(mddev), ALGORITHM_PARITY_N);\n\t}\n\n\tif (mddev->level == 10)\n\t\treturn raid0_takeover_raid10(mddev);\n\n\tif (mddev->level == 1)\n\t\treturn raid0_takeover_raid1(mddev);\n\n\tpr_warn(\"Takeover from raid%i to raid0 not supported\\n\",\n\t\tmddev->level);\n\n\treturn ERR_PTR(-EINVAL);\n}",
        "static void unhash_nsid(struct net *net, struct net *last)\n{\n\tstruct net *tmp;\n\t/* This function is only called from cleanup_net() work,\n\t * and this work is the only process, that may delete": "static void unhash_nsid(struct net *net, struct net *last)\n{\n\tstruct net *tmp;\n\t/* This function is only called from cleanup_net() work,\n\t * and this work is the only process, that may delete\n\t * a net from net_namespace_list. So, when the below\n\t * is executing, the list may only grow. Thus, we do not\n\t * use for_each_net_rcu() or net_rwsem.\n\t */\n\tfor_each_net(tmp) {\n\t\tint id;\n\n\t\tspin_lock_bh(&tmp->nsid_lock);\n\t\tid = __peernet2id(tmp, net);\n\t\tif (id >= 0)\n\t\t\tidr_remove(&tmp->netns_ids, id);\n\t\tspin_unlock_bh(&tmp->nsid_lock);\n\t\tif (id >= 0)\n\t\t\trtnl_net_notifyid(tmp, RTM_DELNSID, id, 0, NULL,\n\t\t\t\t\t  GFP_KERNEL);\n\t\tif (tmp == last)\n\t\t\tbreak;\n\t}\n\tspin_lock_bh(&net->nsid_lock);\n\tidr_destroy(&net->netns_ids);\n\tspin_unlock_bh(&net->nsid_lock);\n}",
        "static int rt1711h_init(struct tcpci *tcpci, struct tcpci_data *tdata)\n{\n\tint ret;\n\tstruct rt1711h_chip *chip = tdata_to_rt1711h(tdata);\n": "static int rt1711h_init(struct tcpci *tcpci, struct tcpci_data *tdata)\n{\n\tint ret;\n\tstruct rt1711h_chip *chip = tdata_to_rt1711h(tdata);\n\n\t/* CK 300K from 320K, shipping off, auto_idle enable, tout = 32ms */\n\tret = rt1711h_write8(chip, RT1711H_RTCTRL8,\n\t\t\t     RT1711H_RTCTRL8_SET(0, 1, 1, 2));\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/* I2C reset : (val + 1) * 12.5ms */\n\tret = rt1711h_write8(chip, RT1711H_RTCTRL11,\n\t\t\t     RT1711H_RTCTRL11_SET(1, 0x0F));\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/* tTCPCfilter : (26.7 * val) us */\n\tret = rt1711h_write8(chip, RT1711H_RTCTRL14, 0x0F);\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/*  tDRP : (51.2 + 6.4 * val) ms */\n\tret = rt1711h_write8(chip, RT1711H_RTCTRL15, 0x04);\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/* dcSRC.DRP : 33% */\n\treturn rt1711h_write16(chip, RT1711H_RTCTRL16, 330);\n}",
        "static void check_buffer_tree_ref(struct extent_buffer *eb)\n{\n\tint refs;\n\t/*\n\t * The TREE_REF bit is first set when the extent_buffer is added": "static void check_buffer_tree_ref(struct extent_buffer *eb)\n{\n\tint refs;\n\t/*\n\t * The TREE_REF bit is first set when the extent_buffer is added\n\t * to the radix tree. It is also reset, if unset, when a new reference\n\t * is created by find_extent_buffer.\n\t *\n\t * It is only cleared in two cases: freeing the last non-tree\n\t * reference to the extent_buffer when its STALE bit is set or\n\t * calling release_folio when the tree reference is the only reference.\n\t *\n\t * In both cases, care is taken to ensure that the extent_buffer's\n\t * pages are not under io. However, release_folio can be concurrently\n\t * called with creating new references, which is prone to race\n\t * conditions between the calls to check_buffer_tree_ref in those\n\t * codepaths and clearing TREE_REF in try_release_extent_buffer.\n\t *\n\t * The actual lifetime of the extent_buffer in the radix tree is\n\t * adequately protected by the refcount, but the TREE_REF bit and\n\t * its corresponding reference are not. To protect against this\n\t * class of races, we call check_buffer_tree_ref from the codepaths\n\t * which trigger io after they set eb->io_pages. Note that once io is\n\t * initiated, TREE_REF can no longer be cleared, so that is the\n\t * moment at which any such race is best fixed.\n\t */\n\trefs = atomic_read(&eb->refs);\n\tif (refs >= 2 && test_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags))\n\t\treturn;\n\n\tspin_lock(&eb->refs_lock);\n\tif (!test_and_set_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags))\n\t\tatomic_inc(&eb->refs);\n\tspin_unlock(&eb->refs_lock);\n}",
        "static void bpf_object__sanitize_btf(struct bpf_object *obj, struct btf *btf)\n{\n\tbool has_func_global = kernel_supports(obj, FEAT_BTF_GLOBAL_FUNC);\n\tbool has_datasec = kernel_supports(obj, FEAT_BTF_DATASEC);\n\tbool has_float = kernel_supports(obj, FEAT_BTF_FLOAT);": "static void bpf_object__sanitize_btf(struct bpf_object *obj, struct btf *btf)\n{\n\tbool has_func_global = kernel_supports(obj, FEAT_BTF_GLOBAL_FUNC);\n\tbool has_datasec = kernel_supports(obj, FEAT_BTF_DATASEC);\n\tbool has_float = kernel_supports(obj, FEAT_BTF_FLOAT);\n\tbool has_func = kernel_supports(obj, FEAT_BTF_FUNC);\n\tbool has_decl_tag = kernel_supports(obj, FEAT_BTF_DECL_TAG);\n\tbool has_type_tag = kernel_supports(obj, FEAT_BTF_TYPE_TAG);\n\tstruct btf_type *t;\n\tint i, j, vlen;\n\n\tfor (i = 1; i < btf__type_cnt(btf); i++) {\n\t\tt = (struct btf_type *)btf__type_by_id(btf, i);\n\n\t\tif ((!has_datasec && btf_is_var(t)) || (!has_decl_tag && btf_is_decl_tag(t))) {\n\t\t\t/* replace VAR/DECL_TAG with INT */\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_INT, 0, 0);\n\t\t\t/*\n\t\t\t * using size = 1 is the safest choice, 4 will be too\n\t\t\t * big and cause kernel BTF validation failure if\n\t\t\t * original variable took less than 4 bytes\n\t\t\t */\n\t\t\tt->size = 1;\n\t\t\t*(int *)(t + 1) = BTF_INT_ENC(0, 0, 8);\n\t\t} else if (!has_datasec && btf_is_datasec(t)) {\n\t\t\t/* replace DATASEC with STRUCT */\n\t\t\tconst struct btf_var_secinfo *v = btf_var_secinfos(t);\n\t\t\tstruct btf_member *m = btf_members(t);\n\t\t\tstruct btf_type *vt;\n\t\t\tchar *name;\n\n\t\t\tname = (char *)btf__name_by_offset(btf, t->name_off);\n\t\t\twhile (*name) {\n\t\t\t\tif (*name == '.')\n\t\t\t\t\t*name = '_';\n\t\t\t\tname++;\n\t\t\t}\n\n\t\t\tvlen = btf_vlen(t);\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_STRUCT, 0, vlen);\n\t\t\tfor (j = 0; j < vlen; j++, v++, m++) {\n\t\t\t\t/* order of field assignments is important */\n\t\t\t\tm->offset = v->offset * 8;\n\t\t\t\tm->type = v->type;\n\t\t\t\t/* preserve variable name as member name */\n\t\t\t\tvt = (void *)btf__type_by_id(btf, v->type);\n\t\t\t\tm->name_off = vt->name_off;\n\t\t\t}\n\t\t} else if (!has_func && btf_is_func_proto(t)) {\n\t\t\t/* replace FUNC_PROTO with ENUM */\n\t\t\tvlen = btf_vlen(t);\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_ENUM, 0, vlen);\n\t\t\tt->size = sizeof(__u32); /* kernel enforced */\n\t\t} else if (!has_func && btf_is_func(t)) {\n\t\t\t/* replace FUNC with TYPEDEF */\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_TYPEDEF, 0, 0);\n\t\t} else if (!has_func_global && btf_is_func(t)) {\n\t\t\t/* replace BTF_FUNC_GLOBAL with BTF_FUNC_STATIC */\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_FUNC, 0, 0);\n\t\t} else if (!has_float && btf_is_float(t)) {\n\t\t\t/* replace FLOAT with an equally-sized empty STRUCT;\n\t\t\t * since C compilers do not accept e.g. \"float\" as a\n\t\t\t * valid struct name, make it anonymous\n\t\t\t */\n\t\t\tt->name_off = 0;\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_STRUCT, 0, 0);\n\t\t} else if (!has_type_tag && btf_is_type_tag(t)) {\n\t\t\t/* replace TYPE_TAG with a CONST */\n\t\t\tt->name_off = 0;\n\t\t\tt->info = BTF_INFO_ENC(BTF_KIND_CONST, 0, 0);\n\t\t}\n\t}\n}",
        "static bool btf_type_is_modifier(const struct btf_type *t)\n{\n\t/* Some of them is not strictly a C modifier\n\t * but they are grouped into the same bucket\n\t * for BTF concern:": "static bool btf_type_is_modifier(const struct btf_type *t)\n{\n\t/* Some of them is not strictly a C modifier\n\t * but they are grouped into the same bucket\n\t * for BTF concern:\n\t *   A type (t) that refers to another\n\t *   type through t->type AND its size cannot\n\t *   be determined without following the t->type.\n\t *\n\t * ptr does not fall into this bucket\n\t * because its size is always sizeof(void *).\n\t */\n\tswitch (BTF_INFO_KIND(t->info)) {\n\tcase BTF_KIND_TYPEDEF:\n\tcase BTF_KIND_VOLATILE:\n\tcase BTF_KIND_CONST:\n\tcase BTF_KIND_RESTRICT:\n\tcase BTF_KIND_TYPE_TAG:\n\t\treturn true;\n\t}\n\n\treturn false;\n}",
        "static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)\n{\n\tstruct stb0899_internal *internal\t= &state->internal;\n\tstruct stb0899_config *config\t\t= state->config;\n": "static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)\n{\n\tstruct stb0899_internal *internal\t= &state->internal;\n\tstruct stb0899_config *config\t\t= state->config;\n\n\tu32 sym_peak = 23, zeta = 707, loopbw_percent = 60;\n\ts32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;\n\ts32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;\n\tu32 decim, K, wn, k_direct, k_indirect;\n\tu32 reg;\n\n\tdec_ratio = (internal->master_clk * 2) / (5 * internal->srate);\n\tdec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;\n\tdec_rate = Log2Int(dec_ratio);\n\tdecim = (1 << dec_rate);\n\n\tsym_peak *= 576000;\n\tK = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);\n\tK *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/\n\n\tif (K != 0) {\n\t\tK = sym_peak / K;\n\t\twn = (4 * zeta * zeta) + 1000000;\n\t\twn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn;  /*wn =wn 10^-8*/\n\n\t\tk_indirect = (wn * wn) / K;\t/*kindirect = kindirect 10^-6*/\n\t\tk_direct   = (2 * wn * zeta) / K;\t/*kDirect = kDirect 10^-2*/\n\t\tk_direct  *= 100;\n\n\t\tk_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;\n\t\tk_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;\n\t\tk_btr1 = k_direct / (1 << k_direct_shift);\n\t\tk_btr1 /= 10000;\n\n\t\tk_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;\n\t\tk_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;\n\t\tk_btr0 = k_indirect * (1 << (-k_indirect_shift));\n\t\tk_btr0 /= 1000000;\n\n\t\tk_btr2_rshft = 0;\n\t\tif (k_btr0_rshft > 15) {\n\t\t\tk_btr2_rshft = k_btr0_rshft - 15;\n\t\t\tk_btr0_rshft = 15;\n\t\t}\n\t\treg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);\n\t\tSTB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);\n\t\tSTB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);\n\t\tSTB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);\n\t\tSTB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);\n\t\tSTB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);\n\t} else\n\t\tstb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);\n}",
        "static int patch_ad1985(struct snd_ac97 * ac97)\n{\n\tunsigned short misc;\n\t\n\tpatch_ad1881(ac97);": "static int patch_ad1985(struct snd_ac97 * ac97)\n{\n\tunsigned short misc;\n\t\n\tpatch_ad1881(ac97);\n\tac97->build_ops = &patch_ad1985_build_ops;\n\tmisc = snd_ac97_read(ac97, AC97_AD_MISC);\n\t/* switch front/surround line-out/hp-out */\n\t/* AD-compatible mode */\n\t/* Stereo mutes enabled */\n\tsnd_ac97_write_cache(ac97, AC97_AD_MISC, misc |\n\t\t\t     AC97_AD198X_LOSEL |\n\t\t\t     AC97_AD198X_HPSEL |\n\t\t\t     AC97_AD198X_MSPLT |\n\t\t\t     AC97_AD198X_AC97NC);\n\tac97->flags |= AC97_STEREO_MUTES;\n\n\t/* update current jack configuration */\n\tad1985_update_jacks(ac97);\n\n\t/* on AD1985 rev. 3, AC'97 revision bits are zero */\n\tac97->ext_id = (ac97->ext_id & ~AC97_EI_REV_MASK) | AC97_EI_REV_23;\n\treturn 0;\n}",
        "static int test3_prpw_unaligned_12541bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t((start_addr[0] + 0xC000) & ~(ADI_BLKSZ - 1)) + 17;": "static int test3_prpw_unaligned_12541bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t((start_addr[0] + 0xC000) & ~(ADI_BLKSZ - 1)) + 17;\n\tunsigned char version[TEST3_VERSION_SZ],\n\t\texpected_version[TEST3_VERSION_SZ];\n\tloff_t offset;\n\tint ret, i;\n\n\tfor (i = 0; i < TEST3_VERSION_SZ; i++) {\n\t\tversion[i] = random_version();\n\t\texpected_version[i] = version[i];\n\t}\n\n\toffset = paddr / ADI_BLKSZ;\n\n\tret = pwrite_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tret = pread_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tfor (i = 0; i < TEST3_VERSION_SZ; i++) {\n\t\tif (expected_version[i] != version[i]) {\n\t\t\tDEBUG_PRINT_L2(\n\t\t\t\t\"\\tExpected version %d but read version %d\\n\",\n\t\t\t\texpected_version, version[0]);\n\t\t\tTEST_STEP_FAILURE(-expected_version[i]);\n\t\t}\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static int gmin_subdev_add(struct gmin_subdev *gs)\n{\n\tstruct i2c_client *client = v4l2_get_subdevdata(gs->subdev);\n\tstruct device *dev = &client->dev;\n\tstruct acpi_device *adev = ACPI_COMPANION(dev);": "static int gmin_subdev_add(struct gmin_subdev *gs)\n{\n\tstruct i2c_client *client = v4l2_get_subdevdata(gs->subdev);\n\tstruct device *dev = &client->dev;\n\tstruct acpi_device *adev = ACPI_COMPANION(dev);\n\tint ret, default_val, clock_num = -1;\n\n\tdev_info(dev, \"%s: ACPI path is %pfw\\n\", __func__, dev_fwnode(dev));\n\n\t/*WA:CHT requires XTAL clock as PLL is not stable.*/\n\tgs->clock_src = gmin_get_var_int(dev, false, \"ClkSrc\",\n\t\t\t\t         VLV2_CLK_PLL_19P2MHZ);\n\n\t/*\n\t * Get ACPI _PR0 derived clock here already because it is used\n\t * to determine the csi_port default.\n\t */\n\tif (acpi_device_power_manageable(adev))\n\t\tclock_num = atomisp_get_acpi_power(dev);\n\n\t/* Compare clock to CsiPort 1 pmc-clock used in the CHT/BYT reference designs */\n\tif (IS_ISP2401)\n\t\tdefault_val = clock_num == 4 ? 1 : 0;\n\telse\n\t\tdefault_val = clock_num == 0 ? 1 : 0;\n\n\tgs->csi_port = gmin_get_var_int(dev, false, \"CsiPort\", default_val);\n\tgs->csi_lanes = gmin_get_var_int(dev, false, \"CsiLanes\", 1);\n\n\tgs->gpio0 = gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW);\n\tif (IS_ERR(gs->gpio0))\n\t\tgs->gpio0 = NULL;\n\telse\n\t\tdev_info(dev, \"will handle gpio0 via ACPI\\n\");\n\n\tgs->gpio1 = gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW);\n\tif (IS_ERR(gs->gpio1))\n\t\tgs->gpio1 = NULL;\n\telse\n\t\tdev_info(dev, \"will handle gpio1 via ACPI\\n\");\n\n\t/*\n\t * Those are used only when there is an external regulator apart\n\t * from the PMIC that would be providing power supply, like on the\n\t * two cases below:\n\t *\n\t * The ECS E7 board drives camera 2.8v from an external regulator\n\t * instead of the PMIC.  There's a gmin_CamV2P8 config variable\n\t * that specifies the GPIO to handle this particular case,\n\t * but this needs a broader architecture for handling camera power.\n\t *\n\t * The CHT RVP board drives camera 1.8v from an* external regulator\n\t * instead of the PMIC just like ECS E7 board.\n\t */\n\n\tgs->v1p8_gpio = gmin_get_var_int(dev, true, \"V1P8GPIO\", -1);\n\tgs->v2p8_gpio = gmin_get_var_int(dev, true, \"V2P8GPIO\", -1);\n\n\t/*\n\t * FIXME:\n\t *\n\t * The ACPI handling code checks for the _PR? tables in order to\n\t * know what is required to switch the device from power state\n\t * D0 (_PR0) up to D3COLD (_PR3).\n\t *\n\t * The adev->flags.power_manageable is set to true if the device\n\t * has a _PR0 table, which can be checked by calling\n\t * acpi_device_power_manageable(adev).\n\t *\n\t * However, this only says that the device can be set to power off\n\t * mode.\n\t *\n\t * At least on the DSDT tables we've seen so far, there's no _PR3,\n\t * nor _PS3 (which would have a somewhat similar effect).\n\t * So, using ACPI for power management won't work, except if adding\n\t * an ACPI override logic somewhere.\n\t *\n\t * So, at least for the existing devices we know, the check below\n\t * will always be false.\n\t */\n\tif (acpi_device_can_wakeup(adev) &&\n\t    acpi_device_can_poweroff(adev)) {\n\t\tdev_info(dev,\n\t\t\t \"gmin: power management provided via device PM\\n\");\n\t\treturn 0;\n\t}\n\n\t/*\n\t * The code below is here due to backward compatibility with devices\n\t * whose ACPI BIOS may not contain everything that would be needed\n\t * in order to set clocks and do power management.\n\t */\n\n\t/*\n\t * According with :\n\t *   https://github.com/projectceladon/hardware-intel-kernelflinger/blob/master/doc/fastboot.md\n\t *\n\t * The \"CamClk\" EFI var is set via fastboot on some Android devices,\n\t * and seems to contain the number of the clock used to feed the\n\t * sensor.\n\t *\n\t * On systems with a proper ACPI table, this is given via the _PR0\n\t * power resource table. The logic below should first check if there\n\t * is a power resource already, falling back to the EFI vars detection\n\t * otherwise.\n\t */\n\n\t/* If getting the clock from _PR0 above failed, fall-back to EFI and/or DMI match */\n\tif (clock_num < 0)\n\t\tclock_num = gmin_get_var_int(dev, false, \"CamClk\", 0);\n\n\tif (clock_num < 0 || clock_num > MAX_CLK_COUNT) {\n\t\tdev_err(dev, \"Invalid clock number\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tsnprintf(gmin_pmc_clk_name, sizeof(gmin_pmc_clk_name),\n\t\t \"%s_%d\", \"pmc_plt_clk\", clock_num);\n\n\tgs->pmc_clk = devm_clk_get(dev, gmin_pmc_clk_name);\n\tif (IS_ERR(gs->pmc_clk)) {\n\t\tret = PTR_ERR(gs->pmc_clk);\n\t\tdev_err(dev, \"Failed to get clk from %s: %d\\n\", gmin_pmc_clk_name, ret);\n\t\treturn ret;\n\t}\n\tdev_info(dev, \"Will use CLK%d (%s)\\n\", clock_num, gmin_pmc_clk_name);\n\n\t/*\n\t * The firmware might enable the clock at\n\t * boot (this information may or may not\n\t * be reflected in the enable clock register).\n\t * To change the rate we must disable the clock\n\t * first to cover these cases. Due to common\n\t * clock framework restrictions that do not allow\n\t * to disable a clock that has not been enabled,\n\t * we need to enable the clock first.\n\t */\n\tret = clk_prepare_enable(gs->pmc_clk);\n\tif (!ret)\n\t\tclk_disable_unprepare(gs->pmc_clk);\n\n\tswitch (pmic_id) {\n\tcase PMIC_REGULATOR:\n\t\tgs->v1p8_reg = regulator_get(dev, \"V1P8SX\");\n\t\tgs->v2p8_reg = regulator_get(dev, \"V2P8SX\");\n\n\t\tgs->v1p2_reg = regulator_get(dev, \"V1P2A\");\n\t\tgs->v2p8_vcm_reg = regulator_get(dev, \"VPROG4B\");\n\n\t\t/* Note: ideally we would initialize v[12]p8_on to the\n\t\t * output of regulator_is_enabled(), but sadly that\n\t\t * API is broken with the current drivers, returning\n\t\t * \"1\" for a regulator that will then emit a\n\t\t * \"unbalanced disable\" WARNing if we try to disable\n\t\t * it.\n\t\t */\n\t\tbreak;\n\n\tcase PMIC_AXP:\n\t\tgs->eldo1_1p6v = gmin_get_var_int(dev, false,\n\t\t\t\t\t\t  \"eldo1_1p8v\",\n\t\t\t\t\t\t  ELDO1_1P6V);\n\t\tgs->eldo1_sel_reg = gmin_get_var_int(dev, false,\n\t\t\t\t\t\t     \"eldo1_sel_reg\",\n\t\t\t\t\t\t     ELDO1_SEL_REG);\n\t\tgs->eldo1_ctrl_shift = gmin_get_var_int(dev, false,\n\t\t\t\t\t\t\t\"eldo1_ctrl_shift\",\n\t\t\t\t\t\t\tELDO1_CTRL_SHIFT);\n\t\tgs->eldo2_1p8v = gmin_get_var_int(dev, false,\n\t\t\t\t\t\t  \"eldo2_1p8v\",\n\t\t\t\t\t\t  ELDO2_1P8V);\n\t\tgs->eldo2_sel_reg = gmin_get_var_int(dev, false,\n\t\t\t\t\t\t     \"eldo2_sel_reg\",\n\t\t\t\t\t\t     ELDO2_SEL_REG);\n\t\tgs->eldo2_ctrl_shift = gmin_get_var_int(dev, false,\n\t\t\t\t\t\t\t\"eldo2_ctrl_shift\",\n\t\t\t\t\t\t\tELDO2_CTRL_SHIFT);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn 0;\n}",
        "static int hdsp_spdif_sample_rate(struct hdsp *hdsp)\n{\n\tunsigned int status = hdsp_read(hdsp, HDSP_statusRegister);\n\tunsigned int rate_bits = (status & HDSP_spdifFrequencyMask);\n": "static int hdsp_spdif_sample_rate(struct hdsp *hdsp)\n{\n\tunsigned int status = hdsp_read(hdsp, HDSP_statusRegister);\n\tunsigned int rate_bits = (status & HDSP_spdifFrequencyMask);\n\n\t/* For the 9632, the mask is different */\n\tif (hdsp->io_type == H9632)\n\t\t rate_bits = (status & HDSP_spdifFrequencyMask_9632);\n\n\tif (status & HDSP_SPDIFErrorFlag)\n\t\treturn 0;\n\n\tswitch (rate_bits) {\n\tcase HDSP_spdifFrequency32KHz: return 32000;\n\tcase HDSP_spdifFrequency44_1KHz: return 44100;\n\tcase HDSP_spdifFrequency48KHz: return 48000;\n\tcase HDSP_spdifFrequency64KHz: return 64000;\n\tcase HDSP_spdifFrequency88_2KHz: return 88200;\n\tcase HDSP_spdifFrequency96KHz: return 96000;\n\tcase HDSP_spdifFrequency128KHz:\n\t\tif (hdsp->io_type == H9632) return 128000;\n\t\tbreak;\n\tcase HDSP_spdifFrequency176_4KHz:\n\t\tif (hdsp->io_type == H9632) return 176400;\n\t\tbreak;\n\tcase HDSP_spdifFrequency192KHz:\n\t\tif (hdsp->io_type == H9632) return 192000;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tdev_warn(hdsp->card->dev,\n\t\t \"unknown spdif frequency status; bits = 0x%x, status = 0x%x\\n\",\n\t\t rate_bits, status);\n\treturn 0;\n}",
        "static void kasan_memchr(struct kunit *test)\n{\n\tchar *ptr;\n\tsize_t size = 24;\n": "static void kasan_memchr(struct kunit *test)\n{\n\tchar *ptr;\n\tsize_t size = 24;\n\n\t/*\n\t * str* functions are not instrumented with CONFIG_AMD_MEM_ENCRYPT.\n\t * See https://bugzilla.kernel.org/show_bug.cgi?id=206337 for details.\n\t */\n\tKASAN_TEST_NEEDS_CONFIG_OFF(test, CONFIG_AMD_MEM_ENCRYPT);\n\n\tif (OOB_TAG_OFF)\n\t\tsize = round_up(size, OOB_TAG_OFF);\n\n\tptr = kmalloc(size, GFP_KERNEL | __GFP_ZERO);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);\n\n\tOPTIMIZER_HIDE_VAR(ptr);\n\tOPTIMIZER_HIDE_VAR(size);\n\tKUNIT_EXPECT_KASAN_FAIL(test,\n\t\tkasan_ptr_result = memchr(ptr, '1', size + 1));\n\n\tkfree(ptr);\n}",
        "static int micron_st_nor_octal_dtr_en(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;": "static int micron_st_nor_octal_dtr_en(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;\n\n\t/* Use 20 dummy cycles for memory array reads. */\n\t*buf = 20;\n\top = (struct spi_mem_op)\n\t\tMICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);\n\tret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);\n\tif (ret)\n\t\treturn ret;\n\n\tbuf[0] = SPINOR_MT_OCT_DTR;\n\top = (struct spi_mem_op)\n\t\tMICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf);\n\tret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Read flash ID to make sure the switch was successful. */\n\tret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);\n\tif (ret) {\n\t\tdev_dbg(nor->dev, \"error %d reading JEDEC ID after enabling 8D-8D-8D mode\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tif (memcmp(buf, nor->info->id, nor->info->id_len))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static inline int tegra_ivc_check_read(struct tegra_ivc *ivc)\n{\n\tunsigned int offset = offsetof(struct tegra_ivc_header, tx.count);\n\n\t/*": "static inline int tegra_ivc_check_read(struct tegra_ivc *ivc)\n{\n\tunsigned int offset = offsetof(struct tegra_ivc_header, tx.count);\n\n\t/*\n\t * tx.channel->state is set locally, so it is not synchronized with\n\t * state from the remote peer. The remote peer cannot reset its\n\t * transmit counters until we've acknowledged its synchronization\n\t * request, so no additional synchronization is required because an\n\t * asynchronous transition of rx.channel->state to\n\t * TEGRA_IVC_STATE_ACK is not allowed.\n\t */\n\tif (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)\n\t\treturn -ECONNRESET;\n\n\t/*\n\t * Avoid unnecessary invalidations when performing repeated accesses\n\t * to an IVC channel by checking the old queue pointers first.\n\t *\n\t * Synchronization is only necessary when these pointers indicate\n\t * empty or full.\n\t */\n\tif (!tegra_ivc_empty(ivc, ivc->rx.channel))\n\t\treturn 0;\n\n\ttegra_ivc_invalidate(ivc, ivc->rx.phys + offset);\n\n\tif (tegra_ivc_empty(ivc, ivc->rx.channel))\n\t\treturn -ENOSPC;\n\n\treturn 0;\n}",
        "static int is_state_visited(struct bpf_verifier_env *env, int insn_idx)\n{\n\tstruct bpf_verifier_state_list *new_sl;\n\tstruct bpf_verifier_state_list *sl, **pprev;\n\tstruct bpf_verifier_state *cur = env->cur_state, *new;": "static int is_state_visited(struct bpf_verifier_env *env, int insn_idx)\n{\n\tstruct bpf_verifier_state_list *new_sl;\n\tstruct bpf_verifier_state_list *sl, **pprev;\n\tstruct bpf_verifier_state *cur = env->cur_state, *new;\n\tint i, j, err, states_cnt = 0;\n\tbool add_new_state = env->test_state_freq ? true : false;\n\n\tcur->last_insn_idx = env->prev_insn_idx;\n\tif (!env->insn_aux_data[insn_idx].prune_point)\n\t\t/* this 'insn_idx' instruction wasn't marked, so we will not\n\t\t * be doing state search here\n\t\t */\n\t\treturn 0;\n\n\t/* bpf progs typically have pruning point every 4 instructions\n\t * http://vger.kernel.org/bpfconf2019.html#session-1\n\t * Do not add new state for future pruning if the verifier hasn't seen\n\t * at least 2 jumps and at least 8 instructions.\n\t * This heuristics helps decrease 'total_states' and 'peak_states' metric.\n\t * In tests that amounts to up to 50% reduction into total verifier\n\t * memory consumption and 20% verifier time speedup.\n\t */\n\tif (env->jmps_processed - env->prev_jmps_processed >= 2 &&\n\t    env->insn_processed - env->prev_insn_processed >= 8)\n\t\tadd_new_state = true;\n\n\tpprev = explored_state(env, insn_idx);\n\tsl = *pprev;\n\n\tclean_live_states(env, insn_idx, cur);\n\n\twhile (sl) {\n\t\tstates_cnt++;\n\t\tif (sl->state.insn_idx != insn_idx)\n\t\t\tgoto next;\n\n\t\tif (sl->state.branches) {\n\t\t\tstruct bpf_func_state *frame = sl->state.frame[sl->state.curframe];\n\n\t\t\tif (frame->in_async_callback_fn &&\n\t\t\t    frame->async_entry_cnt != cur->frame[cur->curframe]->async_entry_cnt) {\n\t\t\t\t/* Different async_entry_cnt means that the verifier is\n\t\t\t\t * processing another entry into async callback.\n\t\t\t\t * Seeing the same state is not an indication of infinite\n\t\t\t\t * loop or infinite recursion.\n\t\t\t\t * But finding the same state doesn't mean that it's safe\n\t\t\t\t * to stop processing the current state. The previous state\n\t\t\t\t * hasn't yet reached bpf_exit, since state.branches > 0.\n\t\t\t\t * Checking in_async_callback_fn alone is not enough either.\n\t\t\t\t * Since the verifier still needs to catch infinite loops\n\t\t\t\t * inside async callbacks.\n\t\t\t\t */\n\t\t\t} else if (states_maybe_looping(&sl->state, cur) &&\n\t\t\t\t   states_equal(env, &sl->state, cur)) {\n\t\t\t\tverbose_linfo(env, insn_idx, \"; \");\n\t\t\t\tverbose(env, \"infinite loop detected at insn %d\\n\", insn_idx);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\t/* if the verifier is processing a loop, avoid adding new state\n\t\t\t * too often, since different loop iterations have distinct\n\t\t\t * states and may not help future pruning.\n\t\t\t * This threshold shouldn't be too low to make sure that\n\t\t\t * a loop with large bound will be rejected quickly.\n\t\t\t * The most abusive loop will be:\n\t\t\t * r1 += 1\n\t\t\t * if r1 < 1000000 goto pc-2\n\t\t\t * 1M insn_procssed limit / 100 == 10k peak states.\n\t\t\t * This threshold shouldn't be too high either, since states\n\t\t\t * at the end of the loop are likely to be useful in pruning.\n\t\t\t */\n\t\t\tif (env->jmps_processed - env->prev_jmps_processed < 20 &&\n\t\t\t    env->insn_processed - env->prev_insn_processed < 100)\n\t\t\t\tadd_new_state = false;\n\t\t\tgoto miss;\n\t\t}\n\t\tif (states_equal(env, &sl->state, cur)) {\n\t\t\tsl->hit_cnt++;\n\t\t\t/* reached equivalent register/stack state,\n\t\t\t * prune the search.\n\t\t\t * Registers read by the continuation are read by us.\n\t\t\t * If we have any write marks in env->cur_state, they\n\t\t\t * will prevent corresponding reads in the continuation\n\t\t\t * from reaching our parent (an explored_state).  Our\n\t\t\t * own state will get the read marks recorded, but\n\t\t\t * they'll be immediately forgotten as we're pruning\n\t\t\t * this state and will pop a new one.\n\t\t\t */\n\t\t\terr = propagate_liveness(env, &sl->state, cur);\n\n\t\t\t/* if previous state reached the exit with precision and\n\t\t\t * current state is equivalent to it (except precsion marks)\n\t\t\t * the precision needs to be propagated back in\n\t\t\t * the current state.\n\t\t\t */\n\t\t\terr = err ? : push_jmp_history(env, cur);\n\t\t\terr = err ? : propagate_precision(env, &sl->state);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\treturn 1;\n\t\t}\nmiss:\n\t\t/* when new state is not going to be added do not increase miss count.\n\t\t * Otherwise several loop iterations will remove the state\n\t\t * recorded earlier. The goal of these heuristics is to have\n\t\t * states from some iterations of the loop (some in the beginning\n\t\t * and some at the end) to help pruning.\n\t\t */\n\t\tif (add_new_state)\n\t\t\tsl->miss_cnt++;\n\t\t/* heuristic to determine whether this state is beneficial\n\t\t * to keep checking from state equivalence point of view.\n\t\t * Higher numbers increase max_states_per_insn and verification time,\n\t\t * but do not meaningfully decrease insn_processed.\n\t\t */\n\t\tif (sl->miss_cnt > sl->hit_cnt * 3 + 3) {\n\t\t\t/* the state is unlikely to be useful. Remove it to\n\t\t\t * speed up verification\n\t\t\t */\n\t\t\t*pprev = sl->next;\n\t\t\tif (sl->state.frame[0]->regs[0].live & REG_LIVE_DONE) {\n\t\t\t\tu32 br = sl->state.branches;\n\n\t\t\t\tWARN_ONCE(br,\n\t\t\t\t\t  \"BUG live_done but branches_to_explore %d\\n\",\n\t\t\t\t\t  br);\n\t\t\t\tfree_verifier_state(&sl->state, false);\n\t\t\t\tkfree(sl);\n\t\t\t\tenv->peak_states--;\n\t\t\t} else {\n\t\t\t\t/* cannot free this state, since parentage chain may\n\t\t\t\t * walk it later. Add it for free_list instead to\n\t\t\t\t * be freed at the end of verification\n\t\t\t\t */\n\t\t\t\tsl->next = env->free_list;\n\t\t\t\tenv->free_list = sl;\n\t\t\t}\n\t\t\tsl = *pprev;\n\t\t\tcontinue;\n\t\t}\nnext:\n\t\tpprev = &sl->next;\n\t\tsl = *pprev;\n\t}\n\n\tif (env->max_states_per_insn < states_cnt)\n\t\tenv->max_states_per_insn = states_cnt;\n\n\tif (!env->bpf_capable && states_cnt > BPF_COMPLEXITY_LIMIT_STATES)\n\t\treturn push_jmp_history(env, cur);\n\n\tif (!add_new_state)\n\t\treturn push_jmp_history(env, cur);\n\n\t/* There were no equivalent states, remember the current one.\n\t * Technically the current state is not proven to be safe yet,\n\t * but it will either reach outer most bpf_exit (which means it's safe)\n\t * or it will be rejected. When there are no loops the verifier won't be\n\t * seeing this tuple (frame[0].callsite, frame[1].callsite, .. insn_idx)\n\t * again on the way to bpf_exit.\n\t * When looping the sl->state.branches will be > 0 and this state\n\t * will not be considered for equivalence until branches == 0.\n\t */\n\tnew_sl = kzalloc(sizeof(struct bpf_verifier_state_list), GFP_KERNEL);\n\tif (!new_sl)\n\t\treturn -ENOMEM;\n\tenv->total_states++;\n\tenv->peak_states++;\n\tenv->prev_jmps_processed = env->jmps_processed;\n\tenv->prev_insn_processed = env->insn_processed;\n\n\t/* add new state to the head of linked list */\n\tnew = &new_sl->state;\n\terr = copy_verifier_state(new, cur);\n\tif (err) {\n\t\tfree_verifier_state(new, false);\n\t\tkfree(new_sl);\n\t\treturn err;\n\t}\n\tnew->insn_idx = insn_idx;\n\tWARN_ONCE(new->branches != 1,\n\t\t  \"BUG is_state_visited:branches_to_explore=%d insn %d\\n\", new->branches, insn_idx);\n\n\tcur->parent = new;\n\tcur->first_insn_idx = insn_idx;\n\tclear_jmp_history(cur);\n\tnew_sl->next = *explored_state(env, insn_idx);\n\t*explored_state(env, insn_idx) = new_sl;\n\t/* connect new state to parentage chain. Current frame needs all\n\t * registers connected. Only r6 - r9 of the callers are alive (pushed\n\t * to the stack implicitly by JITs) so in callers' frames connect just\n\t * r6 - r9 as an optimization. Callers will have r1 - r5 connected to\n\t * the state of the call instruction (with WRITTEN set), and r0 comes\n\t * from callee with its full parentage chain, anyway.\n\t */\n\t/* clear write marks in current state: the writes we did are not writes\n\t * our child did, so they don't screen off its reads from us.\n\t * (There are no read marks in current state, because reads always mark\n\t * their parent and current state never has children yet.  Only\n\t * explored_states can get read marks.)\n\t */\n\tfor (j = 0; j <= cur->curframe; j++) {\n\t\tfor (i = j < cur->curframe ? BPF_REG_6 : 0; i < BPF_REG_FP; i++)\n\t\t\tcur->frame[j]->regs[i].parent = &new->frame[j]->regs[i];\n\t\tfor (i = 0; i < BPF_REG_FP; i++)\n\t\t\tcur->frame[j]->regs[i].live = REG_LIVE_NONE;\n\t}\n\n\t/* all stack frames are accessible from callee, clear them all */\n\tfor (j = 0; j <= cur->curframe; j++) {\n\t\tstruct bpf_func_state *frame = cur->frame[j];\n\t\tstruct bpf_func_state *newframe = new->frame[j];\n\n\t\tfor (i = 0; i < frame->allocated_stack / BPF_REG_SIZE; i++) {\n\t\t\tframe->stack[i].spilled_ptr.live = REG_LIVE_NONE;\n\t\t\tframe->stack[i].spilled_ptr.parent =\n\t\t\t\t\t\t&newframe->stack[i].spilled_ptr;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int alloc_try_nid_top_down_end_misaligned_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_top_down_end_misaligned_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_128;\n\tphys_addr_t misalign = SZ_2;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\tphys_addr_t rgn_end;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM() + SMP_CACHE_BYTES * 2;\n\tmax_addr = min_addr + SZ_512 + misalign;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\trgn_end = rgn->base + rgn->size;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == max_addr - size - misalign);\n\tassert(rgn_end < max_addr);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static unsigned int tw5864_md_metric_from_mvd(u32 mvd)\n{\n\t/*\n\t * Format of motion vector data exposed by tw5864, according to\n\t * manufacturer:": "static unsigned int tw5864_md_metric_from_mvd(u32 mvd)\n{\n\t/*\n\t * Format of motion vector data exposed by tw5864, according to\n\t * manufacturer:\n\t * mv_x 10 bits\n\t * mv_y 10 bits\n\t * non_zero_members 8 bits\n\t * mb_type 3 bits\n\t * reserved 1 bit\n\t *\n\t * non_zero_members: number of non-zero residuals in each macro block\n\t * after quantization\n\t *\n\t * unsigned int reserved = mvd >> 31;\n\t * unsigned int mb_type = (mvd >> 28) & 0x7;\n\t * unsigned int non_zero_members = (mvd >> 20) & 0xff;\n\t */\n\tunsigned int mv_y = (mvd >> 10) & 0x3ff;\n\tunsigned int mv_x = mvd & 0x3ff;\n\n\t/* heuristic: */\n\tmv_x &= 0x0f;\n\tmv_y &= 0x0f;\n\n\treturn mv_y + mv_x;\n}",
        "static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)\n{\n\t/* Update volatile list for rx/tx macros */\n\tswitch (reg) {\n\tcase CDC_WSA_INTR_CTRL_PIN1_STATUS0:": "static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)\n{\n\t/* Update volatile list for rx/tx macros */\n\tswitch (reg) {\n\tcase CDC_WSA_INTR_CTRL_PIN1_STATUS0:\n\tcase CDC_WSA_INTR_CTRL_PIN2_STATUS0:\n\tcase CDC_WSA_COMPANDER0_CTL6:\n\tcase CDC_WSA_COMPANDER1_CTL6:\n\tcase CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:\n\tcase CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:\n\tcase CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:\n\tcase CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:\n\tcase CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:\n\tcase CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:\n\tcase CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:\n\tcase CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:\n\tcase CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:\n\tcase CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:\n\t\treturn true;\n\t}\n\treturn false;\n}",
        "static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)\n{\n\tstruct nix_mcast *mcast = &nix_hw->mcast;\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tint err, size;": "static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)\n{\n\tstruct nix_mcast *mcast = &nix_hw->mcast;\n\tstruct rvu_hwinfo *hw = rvu->hw;\n\tint err, size;\n\n\tsize = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F;\n\tsize = (1ULL << size);\n\n\t/* Alloc memory for multicast/mirror replication entries */\n\terr = qmem_alloc(rvu->dev, &mcast->mce_ctx,\n\t\t\t (256UL << MC_TBL_SIZE), size);\n\tif (err)\n\t\treturn -ENOMEM;\n\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE,\n\t\t    (u64)mcast->mce_ctx->iova);\n\n\t/* Set max list length equal to max no of VFs per PF  + PF itself */\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG,\n\t\t    BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE);\n\n\t/* Alloc memory for multicast replication buffers */\n\tsize = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF;\n\terr = qmem_alloc(rvu->dev, &mcast->mcast_buf,\n\t\t\t (8UL << MC_BUF_CNT), size);\n\tif (err)\n\t\treturn -ENOMEM;\n\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE,\n\t\t    (u64)mcast->mcast_buf->iova);\n\n\t/* Alloc pkind for NIX internal RX multicast/mirror replay */\n\tmcast->replay_pkind = rvu_alloc_rsrc(&hw->pkind.rsrc);\n\n\trvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG,\n\t\t    BIT_ULL(63) | (mcast->replay_pkind << 24) |\n\t\t    BIT_ULL(20) | MC_BUF_CNT);\n\n\tmutex_init(&mcast->mce_lock);\n\n\treturn nix_setup_mce_tables(rvu, nix_hw);\n}",
        "static bool vc_is_control(struct vc_data *vc, int tc, int c)\n{\n\t/*\n\t * A bitmap for codes <32. A bit of 1 indicates that the code\n\t * corresponding to that bit number invokes some special action (such": "static bool vc_is_control(struct vc_data *vc, int tc, int c)\n{\n\t/*\n\t * A bitmap for codes <32. A bit of 1 indicates that the code\n\t * corresponding to that bit number invokes some special action (such\n\t * as cursor movement) and should not be displayed as a glyph unless\n\t * the disp_ctrl mode is explicitly enabled.\n\t */\n\tstatic const u32 CTRL_ACTION = 0x0d00ff81;\n\t/* Cannot be overridden by disp_ctrl */\n\tstatic const u32 CTRL_ALWAYS = 0x0800f501;\n\n\tif (vc->vc_state != ESnormal)\n\t\treturn true;\n\n\tif (!tc)\n\t\treturn true;\n\n\t/*\n\t * If the original code was a control character we only allow a glyph\n\t * to be displayed if the code is not normally used (such as for cursor\n\t * movement) or if the disp_ctrl mode has been explicitly enabled.\n\t * Certain characters (as given by the CTRL_ALWAYS bitmap) are always\n\t * displayed as control characters, as the console would be pretty\n\t * useless without them; to display an arbitrary font position use the\n\t * direct-to-font zone in UTF-8 mode.\n\t */\n\tif (c < 32) {\n\t\tif (vc->vc_disp_ctrl)\n\t\t\treturn CTRL_ALWAYS & BIT(c);\n\t\telse\n\t\t\treturn vc->vc_utf || (CTRL_ACTION & BIT(c));\n\t}\n\n\tif (c == 127 && !vc->vc_disp_ctrl)\n\t\treturn true;\n\n\tif (c == 128 + 27)\n\t\treturn true;\n\n\treturn false;\n}",
        "static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)\n{\n\tconst struct nand_manufacturer_desc *manufacturer_desc;\n\tstruct mtd_info *mtd = nand_to_mtd(chip);\n\tstruct nand_memory_organization *memorg;": "static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)\n{\n\tconst struct nand_manufacturer_desc *manufacturer_desc;\n\tstruct mtd_info *mtd = nand_to_mtd(chip);\n\tstruct nand_memory_organization *memorg;\n\tint busw, ret;\n\tu8 *id_data = chip->id.data;\n\tu8 maf_id, dev_id;\n\tu64 targetsize;\n\n\t/*\n\t * Let's start by initializing memorg fields that might be left\n\t * unassigned by the ID-based detection logic.\n\t */\n\tmemorg = nanddev_get_memorg(&chip->base);\n\tmemorg->planes_per_lun = 1;\n\tmemorg->luns_per_target = 1;\n\n\t/*\n\t * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)\n\t * after power-up.\n\t */\n\tret = nand_reset(chip, 0);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Select the device */\n\tnand_select_target(chip, 0);\n\n\t/* Send the command for reading device ID */\n\tret = nand_readid_op(chip, 0, id_data, 2);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Read manufacturer and device IDs */\n\tmaf_id = id_data[0];\n\tdev_id = id_data[1];\n\n\t/*\n\t * Try again to make sure, as some systems the bus-hold or other\n\t * interface concerns can cause random data which looks like a\n\t * possibly credible NAND flash to appear. If the two results do\n\t * not match, ignore the device completely.\n\t */\n\n\t/* Read entire ID string */\n\tret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));\n\tif (ret)\n\t\treturn ret;\n\n\tif (id_data[0] != maf_id || id_data[1] != dev_id) {\n\t\tpr_info(\"second ID read did not match %02x,%02x against %02x,%02x\\n\",\n\t\t\tmaf_id, dev_id, id_data[0], id_data[1]);\n\t\treturn -ENODEV;\n\t}\n\n\tchip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));\n\n\t/* Try to identify manufacturer */\n\tmanufacturer_desc = nand_get_manufacturer_desc(maf_id);\n\tchip->manufacturer.desc = manufacturer_desc;\n\n\tif (!type)\n\t\ttype = nand_flash_ids;\n\n\t/*\n\t * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic\n\t * override it.\n\t * This is required to make sure initial NAND bus width set by the\n\t * NAND controller driver is coherent with the real NAND bus width\n\t * (extracted by auto-detection code).\n\t */\n\tbusw = chip->options & NAND_BUSWIDTH_16;\n\n\t/*\n\t * The flag is only set (never cleared), reset it to its default value\n\t * before starting auto-detection.\n\t */\n\tchip->options &= ~NAND_BUSWIDTH_16;\n\n\tfor (; type->name != NULL; type++) {\n\t\tif (is_full_id_nand(type)) {\n\t\t\tif (find_full_id_nand(chip, type))\n\t\t\t\tgoto ident_done;\n\t\t} else if (dev_id == type->dev_id) {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!type->name || !type->pagesize) {\n\t\t/* Check if the chip is ONFI compliant */\n\t\tret = nand_onfi_detect(chip);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\telse if (ret)\n\t\t\tgoto ident_done;\n\n\t\t/* Check if the chip is JEDEC compliant */\n\t\tret = nand_jedec_detect(chip);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\telse if (ret)\n\t\t\tgoto ident_done;\n\t}\n\n\tif (!type->name)\n\t\treturn -ENODEV;\n\n\tchip->parameters.model = kstrdup(type->name, GFP_KERNEL);\n\tif (!chip->parameters.model)\n\t\treturn -ENOMEM;\n\n\tif (!type->pagesize)\n\t\tnand_manufacturer_detect(chip);\n\telse\n\t\tnand_decode_id(chip, type);\n\n\t/* Get chip options */\n\tchip->options |= type->options;\n\n\tmemorg->eraseblocks_per_lun =\n\t\t\tDIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,\n\t\t\t\t\t   memorg->pagesize *\n\t\t\t\t\t   memorg->pages_per_eraseblock);\n\nident_done:\n\tif (!mtd->name)\n\t\tmtd->name = chip->parameters.model;\n\n\tif (chip->options & NAND_BUSWIDTH_AUTO) {\n\t\tWARN_ON(busw & NAND_BUSWIDTH_16);\n\t\tnand_set_defaults(chip);\n\t} else if (busw != (chip->options & NAND_BUSWIDTH_16)) {\n\t\t/*\n\t\t * Check, if buswidth is correct. Hardware drivers should set\n\t\t * chip correct!\n\t\t */\n\t\tpr_info(\"device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\\n\",\n\t\t\tmaf_id, dev_id);\n\t\tpr_info(\"%s %s\\n\", nand_manufacturer_name(manufacturer_desc),\n\t\t\tmtd->name);\n\t\tpr_warn(\"bus width %d instead of %d bits\\n\", busw ? 16 : 8,\n\t\t\t(chip->options & NAND_BUSWIDTH_16) ? 16 : 8);\n\t\tret = -EINVAL;\n\n\t\tgoto free_detect_allocation;\n\t}\n\n\tnand_decode_bbm_options(chip);\n\n\t/* Calculate the address shift from the page size */\n\tchip->page_shift = ffs(mtd->writesize) - 1;\n\t/* Convert chipsize to number of pages per chip -1 */\n\ttargetsize = nanddev_target_size(&chip->base);\n\tchip->pagemask = (targetsize >> chip->page_shift) - 1;\n\n\tchip->bbt_erase_shift = chip->phys_erase_shift =\n\t\tffs(mtd->erasesize) - 1;\n\tif (targetsize & 0xffffffff)\n\t\tchip->chip_shift = ffs((unsigned)targetsize) - 1;\n\telse {\n\t\tchip->chip_shift = ffs((unsigned)(targetsize >> 32));\n\t\tchip->chip_shift += 32 - 1;\n\t}\n\n\tif (chip->chip_shift - chip->page_shift > 16)\n\t\tchip->options |= NAND_ROW_ADDR_3;\n\n\tchip->badblockbits = 8;\n\n\tnand_legacy_adjust_cmdfunc(chip);\n\n\tpr_info(\"device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\\n\",\n\t\tmaf_id, dev_id);\n\tpr_info(\"%s %s\\n\", nand_manufacturer_name(manufacturer_desc),\n\t\tchip->parameters.model);\n\tpr_info(\"%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\\n\",\n\t\t(int)(targetsize >> 20), nand_is_slc(chip) ? \"SLC\" : \"MLC\",\n\t\tmtd->erasesize >> 10, mtd->writesize, mtd->oobsize);\n\treturn 0;\n\nfree_detect_allocation:\n\tkfree(chip->parameters.model);\n\n\treturn ret;\n}",
        "static int t7xx_txq_burst_send_skb(struct dpmaif_tx_queue *txq)\n{\n\tunsigned int drb_remain_cnt, i;\n\tunsigned int send_drb_cnt;\n\tint drb_cnt = 0;": "static int t7xx_txq_burst_send_skb(struct dpmaif_tx_queue *txq)\n{\n\tunsigned int drb_remain_cnt, i;\n\tunsigned int send_drb_cnt;\n\tint drb_cnt = 0;\n\tint ret = 0;\n\n\tdrb_remain_cnt = t7xx_txq_drb_wr_available(txq);\n\n\tfor (i = 0; i < DPMAIF_SKB_TX_BURST_CNT; i++) {\n\t\tstruct sk_buff *skb;\n\n\t\tskb = skb_peek(&txq->tx_skb_head);\n\t\tif (!skb)\n\t\t\tbreak;\n\n\t\tsend_drb_cnt = t7xx_skb_drb_cnt(skb);\n\t\tif (drb_remain_cnt < send_drb_cnt) {\n\t\t\tdrb_remain_cnt = t7xx_txq_drb_wr_available(txq);\n\t\t\tcontinue;\n\t\t}\n\n\t\tdrb_remain_cnt -= send_drb_cnt;\n\n\t\tret = t7xx_dpmaif_add_skb_to_ring(txq->dpmaif_ctrl, skb);\n\t\tif (ret < 0) {\n\t\t\tdev_err(txq->dpmaif_ctrl->dev,\n\t\t\t\t\"Failed to add skb to device's ring: %d\\n\", ret);\n\t\t\tbreak;\n\t\t}\n\n\t\tdrb_cnt += send_drb_cnt;\n\t\tskb_unlink(skb, &txq->tx_skb_head);\n\t}\n\n\tif (drb_cnt > 0)\n\t\treturn drb_cnt;\n\n\treturn ret;\n}",
        "static void setexposure(struct gspca_dev *gspca_dev, s32 val, s32 freq)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint integration = val << 6;\n\tu8 expose_h, expose_m, expose_l;": "static void setexposure(struct gspca_dev *gspca_dev, s32 val, s32 freq)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tint integration = val << 6;\n\tu8 expose_h, expose_m, expose_l;\n\n\t/* Do this before the set_feature calls, for proper timing wrt\n\t   the interrupt driven pkt_scan. Note we may still race but that\n\t   is not a big issue, the expo change state machine is merely for\n\t   avoiding underexposed frames getting send out, if one sneaks\n\t   through so be it */\n\tsd->expo_change_state = EXPO_CHANGED;\n\n\tif (freq == V4L2_CID_POWER_LINE_FREQUENCY_50HZ)\n\t\tintegration = integration - integration % 106667;\n\tif (freq == V4L2_CID_POWER_LINE_FREQUENCY_60HZ)\n\t\tintegration = integration - integration % 88889;\n\n\texpose_h = (integration >> 16);\n\texpose_m = (integration >> 8);\n\texpose_l = integration;\n\n\t/* integration time low */\n\tse401_set_feature(gspca_dev, HV7131_REG_TITL, expose_l);\n\t/* integration time mid */\n\tse401_set_feature(gspca_dev, HV7131_REG_TITM, expose_m);\n\t/* integration time high */\n\tse401_set_feature(gspca_dev, HV7131_REG_TITU, expose_h);\n}",
        "static int sme_vl(struct tdescr *td, siginfo_t *si, ucontext_t *uc)\n{\n\tsize_t resv_sz, offset;\n\tstruct _aarch64_ctx *head = GET_SF_RESV_HEAD(sf);\n\tstruct za_context *za;": "static int sme_vl(struct tdescr *td, siginfo_t *si, ucontext_t *uc)\n{\n\tsize_t resv_sz, offset;\n\tstruct _aarch64_ctx *head = GET_SF_RESV_HEAD(sf);\n\tstruct za_context *za;\n\n\t/* Get a signal context which should have a ZA frame in it */\n\tif (!get_current_context(td, &sf.uc))\n\t\treturn 1;\n\n\tresv_sz = GET_SF_RESV_SIZE(sf);\n\thead = get_header(head, ZA_MAGIC, resv_sz, &offset);\n\tif (!head) {\n\t\tfprintf(stderr, \"No ZA context\\n\");\n\t\treturn 1;\n\t}\n\tza = (struct za_context *)head;\n\n\tif (za->vl != vl) {\n\t\tfprintf(stderr, \"ZA sigframe VL %u, expected %u\\n\",\n\t\t\tza->vl, vl);\n\t\treturn 1;\n\t} else {\n\t\tfprintf(stderr, \"got expected VL %u\\n\", vl);\n\t}\n\n\ttd->pass = 1;\n\n\treturn 0;\n}",
        "static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)\n{\n\tu64 mpidr = read_cpuid_mpidr();\n\tint aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);\n\tint aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);": "static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)\n{\n\tu64 mpidr = read_cpuid_mpidr();\n\tint aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);\n\tint aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);\n\tint aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);\n\tbool mt = mpidr & MPIDR_MT_BITMASK;\n\tint sccl, ccl;\n\n\tif (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {\n\t\tsccl = aff2 >> 3;\n\t\tccl = aff2 & 0x7;\n\t} else if (mt) {\n\t\tsccl = aff3;\n\t\tccl = aff2;\n\t} else {\n\t\tsccl = aff2;\n\t\tccl = aff1;\n\t}\n\n\tif (scclp)\n\t\t*scclp = sccl;\n\tif (cclp)\n\t\t*cclp = ccl;\n}",
        "static void test_basic(void)\n{\n\t__u64 runqueues_addr, bpf_prog_active_addr;\n\t__u32 this_rq_cpu;\n\tint this_bpf_prog_active;": "static void test_basic(void)\n{\n\t__u64 runqueues_addr, bpf_prog_active_addr;\n\t__u32 this_rq_cpu;\n\tint this_bpf_prog_active;\n\tstruct test_ksyms_btf *skel = NULL;\n\tstruct test_ksyms_btf__data *data;\n\tint err;\n\n\terr = kallsyms_find(\"runqueues\", &runqueues_addr);\n\tif (CHECK(err == -EINVAL, \"kallsyms_fopen\", \"failed to open: %d\\n\", errno))\n\t\treturn;\n\tif (CHECK(err == -ENOENT, \"ksym_find\", \"symbol 'runqueues' not found\\n\"))\n\t\treturn;\n\n\terr = kallsyms_find(\"bpf_prog_active\", &bpf_prog_active_addr);\n\tif (CHECK(err == -EINVAL, \"kallsyms_fopen\", \"failed to open: %d\\n\", errno))\n\t\treturn;\n\tif (CHECK(err == -ENOENT, \"ksym_find\", \"symbol 'bpf_prog_active' not found\\n\"))\n\t\treturn;\n\n\tskel = test_ksyms_btf__open_and_load();\n\tif (CHECK(!skel, \"skel_open\", \"failed to open and load skeleton\\n\"))\n\t\tgoto cleanup;\n\n\terr = test_ksyms_btf__attach(skel);\n\tif (CHECK(err, \"skel_attach\", \"skeleton attach failed: %d\\n\", err))\n\t\tgoto cleanup;\n\n\t/* trigger tracepoint */\n\tusleep(1);\n\n\tdata = skel->data;\n\tCHECK(data->out__runqueues_addr != runqueues_addr, \"runqueues_addr\",\n\t      \"got %llu, exp %llu\\n\",\n\t      (unsigned long long)data->out__runqueues_addr,\n\t      (unsigned long long)runqueues_addr);\n\tCHECK(data->out__bpf_prog_active_addr != bpf_prog_active_addr, \"bpf_prog_active_addr\",\n\t      \"got %llu, exp %llu\\n\",\n\t      (unsigned long long)data->out__bpf_prog_active_addr,\n\t      (unsigned long long)bpf_prog_active_addr);\n\n\tCHECK(data->out__rq_cpu == -1, \"rq_cpu\",\n\t      \"got %u, exp != -1\\n\", data->out__rq_cpu);\n\tCHECK(data->out__bpf_prog_active < 0, \"bpf_prog_active\",\n\t      \"got %d, exp >= 0\\n\", data->out__bpf_prog_active);\n\tCHECK(data->out__cpu_0_rq_cpu != 0, \"cpu_rq(0)->cpu\",\n\t      \"got %u, exp 0\\n\", data->out__cpu_0_rq_cpu);\n\n\tthis_rq_cpu = data->out__this_rq_cpu;\n\tCHECK(this_rq_cpu != data->out__rq_cpu, \"this_rq_cpu\",\n\t      \"got %u, exp %u\\n\", this_rq_cpu, data->out__rq_cpu);\n\n\tthis_bpf_prog_active = data->out__this_bpf_prog_active;\n\tCHECK(this_bpf_prog_active != data->out__bpf_prog_active, \"this_bpf_prog_active\",\n\t      \"got %d, exp %d\\n\", this_bpf_prog_active,\n\t      data->out__bpf_prog_active);\n\ncleanup:\n\ttest_ksyms_btf__destroy(skel);\n}",
        "static void batadv_tt_tvlv_container_update(struct batadv_priv *bat_priv)\n{\n\tstruct batadv_tt_change_node *entry, *safe;\n\tstruct batadv_tvlv_tt_data *tt_data;\n\tstruct batadv_tvlv_tt_change *tt_change;": "static void batadv_tt_tvlv_container_update(struct batadv_priv *bat_priv)\n{\n\tstruct batadv_tt_change_node *entry, *safe;\n\tstruct batadv_tvlv_tt_data *tt_data;\n\tstruct batadv_tvlv_tt_change *tt_change;\n\tint tt_diff_len, tt_change_len = 0;\n\tint tt_diff_entries_num = 0;\n\tint tt_diff_entries_count = 0;\n\tu16 tvlv_len;\n\n\ttt_diff_entries_num = atomic_read(&bat_priv->tt.local_changes);\n\ttt_diff_len = batadv_tt_len(tt_diff_entries_num);\n\n\t/* if we have too many changes for one packet don't send any\n\t * and wait for the tt table request which will be fragmented\n\t */\n\tif (tt_diff_len > bat_priv->soft_iface->mtu)\n\t\ttt_diff_len = 0;\n\n\ttvlv_len = batadv_tt_prepare_tvlv_local_data(bat_priv, &tt_data,\n\t\t\t\t\t\t     &tt_change, &tt_diff_len);\n\tif (!tvlv_len)\n\t\treturn;\n\n\ttt_data->flags = BATADV_TT_OGM_DIFF;\n\n\tif (tt_diff_len == 0)\n\t\tgoto container_register;\n\n\tspin_lock_bh(&bat_priv->tt.changes_list_lock);\n\tatomic_set(&bat_priv->tt.local_changes, 0);\n\n\tlist_for_each_entry_safe(entry, safe, &bat_priv->tt.changes_list,\n\t\t\t\t list) {\n\t\tif (tt_diff_entries_count < tt_diff_entries_num) {\n\t\t\tmemcpy(tt_change + tt_diff_entries_count,\n\t\t\t       &entry->change,\n\t\t\t       sizeof(struct batadv_tvlv_tt_change));\n\t\t\ttt_diff_entries_count++;\n\t\t}\n\t\tlist_del(&entry->list);\n\t\tkmem_cache_free(batadv_tt_change_cache, entry);\n\t}\n\tspin_unlock_bh(&bat_priv->tt.changes_list_lock);\n\n\t/* Keep the buffer for possible tt_request */\n\tspin_lock_bh(&bat_priv->tt.last_changeset_lock);\n\tkfree(bat_priv->tt.last_changeset);\n\tbat_priv->tt.last_changeset_len = 0;\n\tbat_priv->tt.last_changeset = NULL;\n\ttt_change_len = batadv_tt_len(tt_diff_entries_count);\n\t/* check whether this new OGM has no changes due to size problems */\n\tif (tt_diff_entries_count > 0) {\n\t\t/* if kmalloc() fails we will reply with the full table\n\t\t * instead of providing the diff\n\t\t */\n\t\tbat_priv->tt.last_changeset = kzalloc(tt_diff_len, GFP_ATOMIC);\n\t\tif (bat_priv->tt.last_changeset) {\n\t\t\tmemcpy(bat_priv->tt.last_changeset,\n\t\t\t       tt_change, tt_change_len);\n\t\t\tbat_priv->tt.last_changeset_len = tt_diff_len;\n\t\t}\n\t}\n\tspin_unlock_bh(&bat_priv->tt.last_changeset_lock);\n\ncontainer_register:\n\tbatadv_tvlv_container_register(bat_priv, BATADV_TVLV_TT, 1, tt_data,\n\t\t\t\t       tvlv_len);\n\tkfree(tt_data);\n}",
        "static void __reg32_deduce_bounds(struct bpf_reg_state *reg)\n{\n\t/* Learn sign from signed bounds.\n\t * If we cannot cross the sign boundary, then signed and unsigned bounds\n\t * are the same, so combine.  This works even in the negative case, e.g.": "static void __reg32_deduce_bounds(struct bpf_reg_state *reg)\n{\n\t/* Learn sign from signed bounds.\n\t * If we cannot cross the sign boundary, then signed and unsigned bounds\n\t * are the same, so combine.  This works even in the negative case, e.g.\n\t * -3 s<= x s<= -1 implies 0xf...fd u<= x u<= 0xf...ff.\n\t */\n\tif (reg->s32_min_value >= 0 || reg->s32_max_value < 0) {\n\t\treg->s32_min_value = reg->u32_min_value =\n\t\t\tmax_t(u32, reg->s32_min_value, reg->u32_min_value);\n\t\treg->s32_max_value = reg->u32_max_value =\n\t\t\tmin_t(u32, reg->s32_max_value, reg->u32_max_value);\n\t\treturn;\n\t}\n\t/* Learn sign from unsigned bounds.  Signed bounds cross the sign\n\t * boundary, so we must be careful.\n\t */\n\tif ((s32)reg->u32_max_value >= 0) {\n\t\t/* Positive.  We can't learn anything from the smin, but smax\n\t\t * is positive, hence safe.\n\t\t */\n\t\treg->s32_min_value = reg->u32_min_value;\n\t\treg->s32_max_value = reg->u32_max_value =\n\t\t\tmin_t(u32, reg->s32_max_value, reg->u32_max_value);\n\t} else if ((s32)reg->u32_min_value < 0) {\n\t\t/* Negative.  We can't learn anything from the smax, but smin\n\t\t * is negative, hence safe.\n\t\t */\n\t\treg->s32_min_value = reg->u32_min_value =\n\t\t\tmax_t(u32, reg->s32_min_value, reg->u32_min_value);\n\t\treg->s32_max_value = reg->u32_max_value;\n\t}\n}",
        "static int mana_smc_poll_register(void __iomem *base, bool reset)\n{\n\tvoid __iomem *ptr = base + SMC_LAST_DWORD * SMC_BASIC_UNIT;\n\tu32 last_dword;\n\tint i;": "static int mana_smc_poll_register(void __iomem *base, bool reset)\n{\n\tvoid __iomem *ptr = base + SMC_LAST_DWORD * SMC_BASIC_UNIT;\n\tu32 last_dword;\n\tint i;\n\n\t/* Poll the hardware for the ownership bit. This should be pretty fast,\n\t * but let's do it in a loop just in case the hardware or the PF\n\t * driver are temporarily busy.\n\t */\n\tfor (i = 0; i < 20 * 1000; i++)  {\n\t\tlast_dword = readl(ptr);\n\n\t\t/* shmem reads as 0xFFFFFFFF in the reset case */\n\t\tif (reset && last_dword == SHMEM_VF_RESET_STATE)\n\t\t\treturn 0;\n\n\t\t/* If bit_31 is set, the PF currently owns the SMC. */\n\t\tif (!(last_dword & BIT(31)))\n\t\t\treturn 0;\n\n\t\tusleep_range(1000, 2000);\n\t}\n\n\treturn -ETIMEDOUT;\n}",
        "static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)\n{\n\tint i;\n\tu32 mask;\n\tu32 dataBit;": "static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)\n{\n\tint i;\n\tu32 mask;\n\tu32 dataBit;\n\tu32 previousBit;\n\tstruct ql3xxx_port_registers __iomem *port_regs =\n\t\t\tqdev->mem_map_registers;\n\t__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;\n\n\t/* Clock in a zero, then do the start bit */\n\tql_write_nvram_reg(qdev, spir,\n\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t    AUBURN_EEPROM_DO_1));\n\tql_write_nvram_reg(qdev, spir,\n\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t    AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));\n\tql_write_nvram_reg(qdev, spir,\n\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t    AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));\n\n\tmask = 1 << (FM93C56A_CMD_BITS - 1);\n\t/* Force the previous data bit to be different */\n\tpreviousBit = 0xffff;\n\tfor (i = 0; i < FM93C56A_CMD_BITS; i++) {\n\t\tdataBit = (cmd & mask)\n\t\t\t? AUBURN_EEPROM_DO_1\n\t\t\t: AUBURN_EEPROM_DO_0;\n\t\tif (previousBit != dataBit) {\n\t\t\t/* If the bit changed, change the DO state to match */\n\t\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t\t   (ISP_NVRAM_MASK |\n\t\t\t\t\t    qdev->eeprom_cmd_data | dataBit));\n\t\t\tpreviousBit = dataBit;\n\t\t}\n\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t\t    dataBit | AUBURN_EEPROM_CLK_RISE));\n\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t\t    dataBit | AUBURN_EEPROM_CLK_FALL));\n\t\tcmd = cmd << 1;\n\t}\n\n\tmask = 1 << (addrBits - 1);\n\t/* Force the previous data bit to be different */\n\tpreviousBit = 0xffff;\n\tfor (i = 0; i < addrBits; i++) {\n\t\tdataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1\n\t\t\t: AUBURN_EEPROM_DO_0;\n\t\tif (previousBit != dataBit) {\n\t\t\t/*\n\t\t\t * If the bit changed, then change the DO state to\n\t\t\t * match\n\t\t\t */\n\t\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t\t   (ISP_NVRAM_MASK |\n\t\t\t\t\t    qdev->eeprom_cmd_data | dataBit));\n\t\t\tpreviousBit = dataBit;\n\t\t}\n\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t\t    dataBit | AUBURN_EEPROM_CLK_RISE));\n\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t   (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t\t    dataBit | AUBURN_EEPROM_CLK_FALL));\n\t\teepromAddr = eepromAddr << 1;\n\t}\n}",
        "static void hpre_ecdh_cb(struct hpre_ctx *ctx, void *resp)\n{\n\tunsigned int curve_sz = hpre_ecdh_get_curvesz(ctx->curve_id);\n\tstruct hpre_dfx *dfx = ctx->hpre->debug.dfx;\n\tstruct hpre_asym_request *req = NULL;": "static void hpre_ecdh_cb(struct hpre_ctx *ctx, void *resp)\n{\n\tunsigned int curve_sz = hpre_ecdh_get_curvesz(ctx->curve_id);\n\tstruct hpre_dfx *dfx = ctx->hpre->debug.dfx;\n\tstruct hpre_asym_request *req = NULL;\n\tstruct kpp_request *areq;\n\tu64 overtime_thrhld;\n\tchar *p;\n\tint ret;\n\n\tret = hpre_alg_res_post_hf(ctx, resp, (void **)&req);\n\tareq = req->areq.ecdh;\n\tareq->dst_len = ctx->key_sz << 1;\n\n\tovertime_thrhld = atomic64_read(&dfx[HPRE_OVERTIME_THRHLD].value);\n\tif (overtime_thrhld && hpre_is_bd_timeout(req, overtime_thrhld))\n\t\tatomic64_inc(&dfx[HPRE_OVER_THRHLD_CNT].value);\n\n\tp = sg_virt(areq->dst);\n\tmemmove(p, p + ctx->key_sz - curve_sz, curve_sz);\n\tmemmove(p + curve_sz, p + areq->dst_len - curve_sz, curve_sz);\n\n\thpre_ecdh_hw_data_clr_all(ctx, req, areq->dst, areq->src);\n\tkpp_request_complete(areq, ret);\n\n\tatomic64_inc(&dfx[HPRE_RECV_CNT].value);\n}",
        "static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags)\n{\n\tu32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst;\n\tu32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest;\n": "static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags)\n{\n\tu32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst;\n\tu32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest;\n\n\t/* dump debug registers */\n\tdbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);\n\tdbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);\n\tdbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0);\n\tdbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1);\n\tdbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);\n\tdbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);\n\tdbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT);\n\tfaultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS);\n\tfaultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);\n\tswrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW);\n\n\tdev_info(sdev->dev, \"adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x\",\n\t\t dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest);\n\tdev_info(sdev->dev, \"dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x\",\n\t\t dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo);\n\n\tmtk_adsp_dump(sdev, flags);\n}",
        "static void coda_approximate_timeperframe(struct v4l2_fract *timeperframe)\n{\n\tstruct v4l2_fract s = *timeperframe;\n\tstruct v4l2_fract f0;\n\tstruct v4l2_fract f1 = { 1, 0 };": "static void coda_approximate_timeperframe(struct v4l2_fract *timeperframe)\n{\n\tstruct v4l2_fract s = *timeperframe;\n\tstruct v4l2_fract f0;\n\tstruct v4l2_fract f1 = { 1, 0 };\n\tstruct v4l2_fract f2 = { 0, 1 };\n\tunsigned int i, div, s_denominator;\n\n\t/* Lower bound is 1/65535 */\n\tif (s.numerator == 0 || s.denominator / s.numerator > 65535) {\n\t\ttimeperframe->numerator = 1;\n\t\ttimeperframe->denominator = 65535;\n\t\treturn;\n\t}\n\n\t/* Upper bound is 65536/1 */\n\tif (s.denominator == 0 || s.numerator / s.denominator > 65536) {\n\t\ttimeperframe->numerator = 65536;\n\t\ttimeperframe->denominator = 1;\n\t\treturn;\n\t}\n\n\t/* Reduce fraction to lowest terms */\n\tdiv = gcd(s.numerator, s.denominator);\n\tif (div > 1) {\n\t\ts.numerator /= div;\n\t\ts.denominator /= div;\n\t}\n\n\tif (s.numerator <= 65536 && s.denominator < 65536) {\n\t\t*timeperframe = s;\n\t\treturn;\n\t}\n\n\t/* Find successive convergents from continued fraction expansion */\n\twhile (f2.numerator <= 65536 && f2.denominator < 65536) {\n\t\tf0 = f1;\n\t\tf1 = f2;\n\n\t\t/* Stop when f2 exactly equals timeperframe */\n\t\tif (s.numerator == 0)\n\t\t\tbreak;\n\n\t\ti = s.denominator / s.numerator;\n\n\t\tf2.numerator = f0.numerator + i * f1.numerator;\n\t\tf2.denominator = f0.denominator + i * f2.denominator;\n\n\t\ts_denominator = s.numerator;\n\t\ts.numerator = s.denominator % s.numerator;\n\t\ts.denominator = s_denominator;\n\t}\n\n\t*timeperframe = f1;\n}",
        "static int avs_updown_mix_create(struct avs_dev *adev, struct avs_path_module *mod)\n{\n\tstruct avs_tplg_module *t = mod->template;\n\tstruct avs_updown_mixer_cfg cfg;\n\tint i;": "static int avs_updown_mix_create(struct avs_dev *adev, struct avs_path_module *mod)\n{\n\tstruct avs_tplg_module *t = mod->template;\n\tstruct avs_updown_mixer_cfg cfg;\n\tint i;\n\n\tcfg.base.cpc = t->cfg_base->cpc;\n\tcfg.base.ibs = t->cfg_base->ibs;\n\tcfg.base.obs = t->cfg_base->obs;\n\tcfg.base.is_pages = t->cfg_base->is_pages;\n\tcfg.base.audio_fmt = *t->in_fmt;\n\tcfg.out_channel_config = t->cfg_ext->updown_mix.out_channel_config;\n\tcfg.coefficients_select = t->cfg_ext->updown_mix.coefficients_select;\n\tfor (i = 0; i < AVS_CHANNELS_MAX; i++)\n\t\tcfg.coefficients[i] = t->cfg_ext->updown_mix.coefficients[i];\n\tcfg.channel_map = t->cfg_ext->updown_mix.channel_map;\n\n\treturn avs_dsp_init_module(adev, mod->module_id, mod->owner->instance_id,\n\t\t\t\t   t->core_id, t->domain, &cfg, sizeof(cfg),\n\t\t\t\t   &mod->instance_id);\n}",
        "static int start_nic(struct s2io_nic *nic)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tstruct net_device *dev = nic->dev;\n\tregister u64 val64 = 0;": "static int start_nic(struct s2io_nic *nic)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tstruct net_device *dev = nic->dev;\n\tregister u64 val64 = 0;\n\tu16 subid, i;\n\tstruct config_param *config = &nic->config;\n\tstruct mac_info *mac_control = &nic->mac_control;\n\n\t/*  PRC Initialization and configuration */\n\tfor (i = 0; i < config->rx_ring_num; i++) {\n\t\tstruct ring_info *ring = &mac_control->rings[i];\n\n\t\twriteq((u64)ring->rx_blocks[0].block_dma_addr,\n\t\t       &bar0->prc_rxd0_n[i]);\n\n\t\tval64 = readq(&bar0->prc_ctrl_n[i]);\n\t\tif (nic->rxd_mode == RXD_MODE_1)\n\t\t\tval64 |= PRC_CTRL_RC_ENABLED;\n\t\telse\n\t\t\tval64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;\n\t\tif (nic->device_type == XFRAME_II_DEVICE)\n\t\t\tval64 |= PRC_CTRL_GROUP_READS;\n\t\tval64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);\n\t\tval64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);\n\t\twriteq(val64, &bar0->prc_ctrl_n[i]);\n\t}\n\n\tif (nic->rxd_mode == RXD_MODE_3B) {\n\t\t/* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */\n\t\tval64 = readq(&bar0->rx_pa_cfg);\n\t\tval64 |= RX_PA_CFG_IGNORE_L2_ERR;\n\t\twriteq(val64, &bar0->rx_pa_cfg);\n\t}\n\n\tif (vlan_tag_strip == 0) {\n\t\tval64 = readq(&bar0->rx_pa_cfg);\n\t\tval64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;\n\t\twriteq(val64, &bar0->rx_pa_cfg);\n\t\tnic->vlan_strip_flag = 0;\n\t}\n\n\t/*\n\t * Enabling MC-RLDRAM. After enabling the device, we timeout\n\t * for around 100ms, which is approximately the time required\n\t * for the device to be ready for operation.\n\t */\n\tval64 = readq(&bar0->mc_rldram_mrs);\n\tval64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;\n\tSPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);\n\tval64 = readq(&bar0->mc_rldram_mrs);\n\n\tmsleep(100);\t/* Delay by around 100 ms. */\n\n\t/* Enabling ECC Protection. */\n\tval64 = readq(&bar0->adapter_control);\n\tval64 &= ~ADAPTER_ECC_EN;\n\twriteq(val64, &bar0->adapter_control);\n\n\t/*\n\t * Verify if the device is ready to be enabled, if so enable\n\t * it.\n\t */\n\tval64 = readq(&bar0->adapter_status);\n\tif (!verify_xena_quiescence(nic)) {\n\t\tDBG_PRINT(ERR_DBG, \"%s: device is not ready, \"\n\t\t\t  \"Adapter status reads: 0x%llx\\n\",\n\t\t\t  dev->name, (unsigned long long)val64);\n\t\treturn FAILURE;\n\t}\n\n\t/*\n\t * With some switches, link might be already up at this point.\n\t * Because of this weird behavior, when we enable laser,\n\t * we may not get link. We need to handle this. We cannot\n\t * figure out which switch is misbehaving. So we are forced to\n\t * make a global change.\n\t */\n\n\t/* Enabling Laser. */\n\tval64 = readq(&bar0->adapter_control);\n\tval64 |= ADAPTER_EOI_TX_ON;\n\twriteq(val64, &bar0->adapter_control);\n\n\tif (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {\n\t\t/*\n\t\t * Dont see link state interrupts initially on some switches,\n\t\t * so directly scheduling the link state task here.\n\t\t */\n\t\tschedule_work(&nic->set_link_task);\n\t}\n\t/* SXE-002: Initialize link and activity LED */\n\tsubid = nic->pdev->subsystem_device;\n\tif (((subid & 0xFF) >= 0x07) &&\n\t    (nic->device_type == XFRAME_I_DEVICE)) {\n\t\tval64 = readq(&bar0->gpio_control);\n\t\tval64 |= 0x0000800000000000ULL;\n\t\twriteq(val64, &bar0->gpio_control);\n\t\tval64 = 0x0411040400000000ULL;\n\t\twriteq(val64, (void __iomem *)bar0 + 0x2700);\n\t}\n\n\treturn SUCCESS;\n}",
        "static int t7xx_cldma_gpd_tx_collect(struct cldma_queue *queue)\n{\n\tstruct cldma_ctrl *md_ctrl = queue->md_ctrl;\n\tunsigned int dma_len, count = 0;\n\tstruct cldma_request *req;": "static int t7xx_cldma_gpd_tx_collect(struct cldma_queue *queue)\n{\n\tstruct cldma_ctrl *md_ctrl = queue->md_ctrl;\n\tunsigned int dma_len, count = 0;\n\tstruct cldma_request *req;\n\tstruct cldma_gpd *gpd;\n\tunsigned long flags;\n\tdma_addr_t dma_free;\n\tstruct sk_buff *skb;\n\n\twhile (!kthread_should_stop()) {\n\t\tspin_lock_irqsave(&queue->ring_lock, flags);\n\t\treq = queue->tr_done;\n\t\tif (!req) {\n\t\t\tspin_unlock_irqrestore(&queue->ring_lock, flags);\n\t\t\tbreak;\n\t\t}\n\t\tgpd = req->gpd;\n\t\tif ((gpd->flags & GPD_FLAGS_HWO) || !req->skb) {\n\t\t\tspin_unlock_irqrestore(&queue->ring_lock, flags);\n\t\t\tbreak;\n\t\t}\n\t\tqueue->budget++;\n\t\tdma_free = req->mapped_buff;\n\t\tdma_len = le16_to_cpu(gpd->data_buff_len);\n\t\tskb = req->skb;\n\t\treq->skb = NULL;\n\t\tqueue->tr_done = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry);\n\t\tspin_unlock_irqrestore(&queue->ring_lock, flags);\n\n\t\tcount++;\n\t\tdma_unmap_single(md_ctrl->dev, dma_free, dma_len, DMA_TO_DEVICE);\n\t\tdev_kfree_skb_any(skb);\n\t}\n\n\tif (count)\n\t\twake_up_nr(&queue->req_wq, count);\n\n\treturn count;\n}",
        "static void mptcp_pm_nl_add_addr_received(struct mptcp_sock *msk)\n{\n\tstruct mptcp_addr_info addrs[MPTCP_PM_ADDR_MAX];\n\tstruct sock *sk = (struct sock *)msk;\n\tunsigned int add_addr_accept_max;": "static void mptcp_pm_nl_add_addr_received(struct mptcp_sock *msk)\n{\n\tstruct mptcp_addr_info addrs[MPTCP_PM_ADDR_MAX];\n\tstruct sock *sk = (struct sock *)msk;\n\tunsigned int add_addr_accept_max;\n\tstruct mptcp_addr_info remote;\n\tunsigned int subflows_max;\n\tint i, nr;\n\n\tadd_addr_accept_max = mptcp_pm_get_add_addr_accept_max(msk);\n\tsubflows_max = mptcp_pm_get_subflows_max(msk);\n\n\tpr_debug(\"accepted %d:%d remote family %d\",\n\t\t msk->pm.add_addr_accepted, add_addr_accept_max,\n\t\t msk->pm.remote.family);\n\n\tremote = msk->pm.remote;\n\tmptcp_pm_announce_addr(msk, &remote, true);\n\tmptcp_pm_nl_addr_send_ack(msk);\n\n\tif (lookup_subflow_by_daddr(&msk->conn_list, &remote))\n\t\treturn;\n\n\t/* pick id 0 port, if none is provided the remote address */\n\tif (!remote.port)\n\t\tremote.port = sk->sk_dport;\n\n\t/* connect to the specified remote address, using whatever\n\t * local address the routing configuration will pick.\n\t */\n\tnr = fill_local_addresses_vec(msk, addrs);\n\n\tmsk->pm.add_addr_accepted++;\n\tif (msk->pm.add_addr_accepted >= add_addr_accept_max ||\n\t    msk->pm.subflows >= subflows_max)\n\t\tWRITE_ONCE(msk->pm.accept_addr, false);\n\n\tspin_unlock_bh(&msk->pm.lock);\n\tfor (i = 0; i < nr; i++)\n\t\t__mptcp_subflow_connect(sk, &addrs[i], &remote);\n\tspin_lock_bh(&msk->pm.lock);\n}",
        "static int mmcr0_pmcjce(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n": "static int mmcr0_pmcjce(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\n\t/* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\n\t/* Init the event for the sampling test */\n\tevent_init_sampling(&event, 0x500fa);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop(10000);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/* Verify that pmcjce field is set in MMCR0 */\n\tFAIL_IF(!get_mmcr0_pmcjce(get_reg_value(intr_regs, \"MMCR0\"), 5));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static void ideapad_check_features(struct ideapad_private *priv)\n{\n\tacpi_handle handle = priv->adev->handle;\n\tunsigned long val;\n": "static void ideapad_check_features(struct ideapad_private *priv)\n{\n\tacpi_handle handle = priv->adev->handle;\n\tunsigned long val;\n\n\tpriv->features.hw_rfkill_switch = dmi_check_system(hw_rfkill_list);\n\n\t/* Most ideapads with ELAN0634 touchpad don't use EC touchpad switch */\n\tpriv->features.touchpad_ctrl_via_ec = !acpi_dev_present(\"ELAN0634\", NULL, -1);\n\n\tif (!read_ec_data(handle, VPCCMD_R_FAN, &val))\n\t\tpriv->features.fan_mode = true;\n\n\tif (acpi_has_method(handle, \"GBMD\") && acpi_has_method(handle, \"SBMC\"))\n\t\tpriv->features.conservation_mode = true;\n\n\tif (acpi_has_method(handle, \"DYTC\"))\n\t\tpriv->features.dytc = true;\n\n\tif (acpi_has_method(handle, \"HALS\") && acpi_has_method(handle, \"SALS\")) {\n\t\tif (!eval_hals(handle, &val)) {\n\t\t\tif (test_bit(HALS_FNLOCK_SUPPORT_BIT, &val))\n\t\t\t\tpriv->features.fn_lock = true;\n\n\t\t\tif (test_bit(HALS_KBD_BL_SUPPORT_BIT, &val))\n\t\t\t\tpriv->features.kbd_bl = true;\n\n\t\t\tif (test_bit(HALS_USB_CHARGING_SUPPORT_BIT, &val))\n\t\t\t\tpriv->features.usb_charging = true;\n\t\t}\n\t}\n}",
        "static void scftorture_invoke_one(struct scf_statistics *scfp, struct torture_random_state *trsp)\n{\n\tuintptr_t cpu;\n\tint ret = 0;\n\tstruct scf_check *scfcp = NULL;": "static void scftorture_invoke_one(struct scf_statistics *scfp, struct torture_random_state *trsp)\n{\n\tuintptr_t cpu;\n\tint ret = 0;\n\tstruct scf_check *scfcp = NULL;\n\tstruct scf_selector *scfsp = scf_sel_rand(trsp);\n\n\tif (use_cpus_read_lock)\n\t\tcpus_read_lock();\n\telse\n\t\tpreempt_disable();\n\tif (scfsp->scfs_prim == SCF_PRIM_SINGLE || scfsp->scfs_wait) {\n\t\tscfcp = kmalloc(sizeof(*scfcp), GFP_ATOMIC);\n\t\tif (WARN_ON_ONCE(!scfcp)) {\n\t\t\tatomic_inc(&n_alloc_errs);\n\t\t} else {\n\t\t\tscfcp->scfc_cpu = -1;\n\t\t\tscfcp->scfc_wait = scfsp->scfs_wait;\n\t\t\tscfcp->scfc_out = false;\n\t\t\tscfcp->scfc_rpc = false;\n\t\t}\n\t}\n\tswitch (scfsp->scfs_prim) {\n\tcase SCF_PRIM_RESCHED:\n\t\tif (IS_BUILTIN(CONFIG_SCF_TORTURE_TEST)) {\n\t\t\tcpu = torture_random(trsp) % nr_cpu_ids;\n\t\t\tscfp->n_resched++;\n\t\t\tresched_cpu(cpu);\n\t\t\tthis_cpu_inc(scf_invoked_count);\n\t\t}\n\t\tbreak;\n\tcase SCF_PRIM_SINGLE:\n\t\tcpu = torture_random(trsp) % nr_cpu_ids;\n\t\tif (scfsp->scfs_wait)\n\t\t\tscfp->n_single_wait++;\n\t\telse\n\t\t\tscfp->n_single++;\n\t\tif (scfcp) {\n\t\t\tscfcp->scfc_cpu = cpu;\n\t\t\tbarrier(); // Prevent race-reduction compiler optimizations.\n\t\t\tscfcp->scfc_in = true;\n\t\t}\n\t\tret = smp_call_function_single(cpu, scf_handler_1, (void *)scfcp, scfsp->scfs_wait);\n\t\tif (ret) {\n\t\t\tif (scfsp->scfs_wait)\n\t\t\t\tscfp->n_single_wait_ofl++;\n\t\t\telse\n\t\t\t\tscfp->n_single_ofl++;\n\t\t\tkfree(scfcp);\n\t\t\tscfcp = NULL;\n\t\t}\n\t\tbreak;\n\tcase SCF_PRIM_SINGLE_RPC:\n\t\tif (!scfcp)\n\t\t\tbreak;\n\t\tcpu = torture_random(trsp) % nr_cpu_ids;\n\t\tscfp->n_single_rpc++;\n\t\tscfcp->scfc_cpu = cpu;\n\t\tscfcp->scfc_wait = true;\n\t\tinit_completion(&scfcp->scfc_completion);\n\t\tscfcp->scfc_rpc = true;\n\t\tbarrier(); // Prevent race-reduction compiler optimizations.\n\t\tscfcp->scfc_in = true;\n\t\tret = smp_call_function_single(cpu, scf_handler_1, (void *)scfcp, 0);\n\t\tif (!ret) {\n\t\t\tif (use_cpus_read_lock)\n\t\t\t\tcpus_read_unlock();\n\t\t\telse\n\t\t\t\tpreempt_enable();\n\t\t\twait_for_completion(&scfcp->scfc_completion);\n\t\t\tif (use_cpus_read_lock)\n\t\t\t\tcpus_read_lock();\n\t\t\telse\n\t\t\t\tpreempt_disable();\n\t\t} else {\n\t\t\tscfp->n_single_rpc_ofl++;\n\t\t\tkfree(scfcp);\n\t\t\tscfcp = NULL;\n\t\t}\n\t\tbreak;\n\tcase SCF_PRIM_MANY:\n\t\tif (scfsp->scfs_wait)\n\t\t\tscfp->n_many_wait++;\n\t\telse\n\t\t\tscfp->n_many++;\n\t\tif (scfcp) {\n\t\t\tbarrier(); // Prevent race-reduction compiler optimizations.\n\t\t\tscfcp->scfc_in = true;\n\t\t}\n\t\tsmp_call_function_many(cpu_online_mask, scf_handler, scfcp, scfsp->scfs_wait);\n\t\tbreak;\n\tcase SCF_PRIM_ALL:\n\t\tif (scfsp->scfs_wait)\n\t\t\tscfp->n_all_wait++;\n\t\telse\n\t\t\tscfp->n_all++;\n\t\tif (scfcp) {\n\t\t\tbarrier(); // Prevent race-reduction compiler optimizations.\n\t\t\tscfcp->scfc_in = true;\n\t\t}\n\t\tsmp_call_function(scf_handler, scfcp, scfsp->scfs_wait);\n\t\tbreak;\n\tdefault:\n\t\tWARN_ON_ONCE(1);\n\t\tif (scfcp)\n\t\t\tscfcp->scfc_out = true;\n\t}\n\tif (scfcp && scfsp->scfs_wait) {\n\t\tif (WARN_ON_ONCE((num_online_cpus() > 1 || scfsp->scfs_prim == SCF_PRIM_SINGLE) &&\n\t\t\t\t !scfcp->scfc_out)) {\n\t\t\tpr_warn(\"%s: Memory-ordering failure, scfs_prim: %d.\\n\", __func__, scfsp->scfs_prim);\n\t\t\tatomic_inc(&n_mb_out_errs); // Leak rather than trash!\n\t\t} else {\n\t\t\tkfree(scfcp);\n\t\t}\n\t\tbarrier(); // Prevent race-reduction compiler optimizations.\n\t}\n\tif (use_cpus_read_lock)\n\t\tcpus_read_unlock();\n\telse\n\t\tpreempt_enable();\n\tif (!(torture_random(trsp) & 0xfff))\n\t\tschedule_timeout_uninterruptible(1);\n}",
        "static int comp_vdev_close(struct file *filp)\n{\n\tstruct comp_fh *fh = filp->private_data;\n\tstruct most_video_dev *mdev = fh->mdev;\n\tstruct mbo *mbo, *tmp;": "static int comp_vdev_close(struct file *filp)\n{\n\tstruct comp_fh *fh = filp->private_data;\n\tstruct most_video_dev *mdev = fh->mdev;\n\tstruct mbo *mbo, *tmp;\n\n\t/*\n\t * We need to put MBOs back before we call most_stop_channel()\n\t * to deallocate MBOs.\n\t * From the other hand mostcore still calling rx_completion()\n\t * to deliver MBOs until most_stop_channel() is called.\n\t * Use mute to work around this issue.\n\t * This must be implemented in core.\n\t */\n\n\tspin_lock_irq(&mdev->list_lock);\n\tmdev->mute = true;\n\tlist_for_each_entry_safe(mbo, tmp, &mdev->pending_mbos, list) {\n\t\tlist_del(&mbo->list);\n\t\tspin_unlock_irq(&mdev->list_lock);\n\t\tmost_put_mbo(mbo);\n\t\tspin_lock_irq(&mdev->list_lock);\n\t}\n\tspin_unlock_irq(&mdev->list_lock);\n\tmost_stop_channel(mdev->iface, mdev->ch_idx, &comp);\n\tmdev->mute = false;\n\n\tv4l2_fh_del(&fh->fh);\n\tv4l2_fh_exit(&fh->fh);\n\n\tatomic_dec(&mdev->access_ref);\n\tkfree(fh);\n\treturn 0;\n}",
        "static void cpu_util_update_eff(struct cgroup_subsys_state *css)\n{\n\tstruct cgroup_subsys_state *top_css = css;\n\tstruct uclamp_se *uc_parent = NULL;\n\tstruct uclamp_se *uc_se = NULL;": "static void cpu_util_update_eff(struct cgroup_subsys_state *css)\n{\n\tstruct cgroup_subsys_state *top_css = css;\n\tstruct uclamp_se *uc_parent = NULL;\n\tstruct uclamp_se *uc_se = NULL;\n\tunsigned int eff[UCLAMP_CNT];\n\tenum uclamp_id clamp_id;\n\tunsigned int clamps;\n\n\tlockdep_assert_held(&uclamp_mutex);\n\tSCHED_WARN_ON(!rcu_read_lock_held());\n\n\tcss_for_each_descendant_pre(css, top_css) {\n\t\tuc_parent = css_tg(css)->parent\n\t\t\t? css_tg(css)->parent->uclamp : NULL;\n\n\t\tfor_each_clamp_id(clamp_id) {\n\t\t\t/* Assume effective clamps matches requested clamps */\n\t\t\teff[clamp_id] = css_tg(css)->uclamp_req[clamp_id].value;\n\t\t\t/* Cap effective clamps with parent's effective clamps */\n\t\t\tif (uc_parent &&\n\t\t\t    eff[clamp_id] > uc_parent[clamp_id].value) {\n\t\t\t\teff[clamp_id] = uc_parent[clamp_id].value;\n\t\t\t}\n\t\t}\n\t\t/* Ensure protection is always capped by limit */\n\t\teff[UCLAMP_MIN] = min(eff[UCLAMP_MIN], eff[UCLAMP_MAX]);\n\n\t\t/* Propagate most restrictive effective clamps */\n\t\tclamps = 0x0;\n\t\tuc_se = css_tg(css)->uclamp;\n\t\tfor_each_clamp_id(clamp_id) {\n\t\t\tif (eff[clamp_id] == uc_se[clamp_id].value)\n\t\t\t\tcontinue;\n\t\t\tuc_se[clamp_id].value = eff[clamp_id];\n\t\t\tuc_se[clamp_id].bucket_id = uclamp_bucket_id(eff[clamp_id]);\n\t\t\tclamps |= (0x1 << clamp_id);\n\t\t}\n\t\tif (!clamps) {\n\t\t\tcss = css_rightmost_descendant(css);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Immediately update descendants RUNNABLE tasks */\n\t\tuclamp_update_active_tasks(css);\n\t}\n}",
        "static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)\n{\n\tint status;\n\tu8 adr = state->demod_address, mm1[4], mm2[2], len;\n": "static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)\n{\n\tint status;\n\tu8 adr = state->demod_address, mm1[4], mm2[2], len;\n\n\tif (state->single_master)\n\t\tflags |= 0xC0;\n\n\tif (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {\n\t\tmm1[0] = (((reg << 1) & 0xFF) | 0x01);\n\t\tmm1[1] = ((reg >> 16) & 0xFF);\n\t\tmm1[2] = ((reg >> 24) & 0xFF) | flags;\n\t\tmm1[3] = ((reg >> 7) & 0xFF);\n\t\tlen = 4;\n\t} else {\n\t\tmm1[0] = ((reg << 1) & 0xFF);\n\t\tmm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));\n\t\tlen = 2;\n\t}\n\tdprintk(2, \"(0x%08x, 0x%02x)\\n\", reg, flags);\n\tstatus = i2c_read(state, adr, mm1, len, mm2, 2);\n\tif (status < 0)\n\t\treturn status;\n\tif (data)\n\t\t*data = mm2[0] | (mm2[1] << 8);\n\n\treturn 0;\n}",
        "static void sock_copy(struct sock *nsk, const struct sock *osk)\n{\n\tconst struct proto *prot = READ_ONCE(osk->sk_prot);\n#ifdef CONFIG_SECURITY_NETWORK\n\tvoid *sptr = nsk->sk_security;": "static void sock_copy(struct sock *nsk, const struct sock *osk)\n{\n\tconst struct proto *prot = READ_ONCE(osk->sk_prot);\n#ifdef CONFIG_SECURITY_NETWORK\n\tvoid *sptr = nsk->sk_security;\n#endif\n\n\t/* If we move sk_tx_queue_mapping out of the private section,\n\t * we must check if sk_tx_queue_clear() is called after\n\t * sock_copy() in sk_clone_lock().\n\t */\n\tBUILD_BUG_ON(offsetof(struct sock, sk_tx_queue_mapping) <\n\t\t     offsetof(struct sock, sk_dontcopy_begin) ||\n\t\t     offsetof(struct sock, sk_tx_queue_mapping) >=\n\t\t     offsetof(struct sock, sk_dontcopy_end));\n\n\tmemcpy(nsk, osk, offsetof(struct sock, sk_dontcopy_begin));\n\n\tmemcpy(&nsk->sk_dontcopy_end, &osk->sk_dontcopy_end,\n\t       prot->obj_size - offsetof(struct sock, sk_dontcopy_end));\n\n#ifdef CONFIG_SECURITY_NETWORK\n\tnsk->sk_security = sptr;\n\tsecurity_sk_clone(osk, nsk);\n#endif\n}",
        "static void tcp_rcv_rtt_update(struct tcp_sock *tp, u32 sample, int win_dep)\n{\n\tu32 new_sample = tp->rcv_rtt_est.rtt_us;\n\tlong m = sample;\n": "static void tcp_rcv_rtt_update(struct tcp_sock *tp, u32 sample, int win_dep)\n{\n\tu32 new_sample = tp->rcv_rtt_est.rtt_us;\n\tlong m = sample;\n\n\tif (new_sample != 0) {\n\t\t/* If we sample in larger samples in the non-timestamp\n\t\t * case, we could grossly overestimate the RTT especially\n\t\t * with chatty applications or bulk transfer apps which\n\t\t * are stalled on filesystem I/O.\n\t\t *\n\t\t * Also, since we are only going for a minimum in the\n\t\t * non-timestamp case, we do not smooth things out\n\t\t * else with timestamps disabled convergence takes too\n\t\t * long.\n\t\t */\n\t\tif (!win_dep) {\n\t\t\tm -= (new_sample >> 3);\n\t\t\tnew_sample += m;\n\t\t} else {\n\t\t\tm <<= 3;\n\t\t\tif (m < new_sample)\n\t\t\t\tnew_sample = m;\n\t\t}\n\t} else {\n\t\t/* No previous measure. */\n\t\tnew_sample = m << 3;\n\t}\n\n\ttp->rcv_rtt_est.rtt_us = new_sample;\n}",
        "static void config_digital_init_by_mode(struct mt6359_accdet *priv)\n{\n\t/* enable eint cmpmem pwm */\n\tregmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR,\n\t\t     (priv->data->pwm_deb->eint_pwm_width << 4 |": "static void config_digital_init_by_mode(struct mt6359_accdet *priv)\n{\n\t/* enable eint cmpmem pwm */\n\tregmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR,\n\t\t     (priv->data->pwm_deb->eint_pwm_width << 4 |\n\t\t     priv->data->pwm_deb->eint_pwm_thresh));\n\t/* DA signal stable */\n\tif (priv->caps & ACCDET_PMIC_EINT0) {\n\t\tregmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,\n\t\t\t     ACCDET_EINT0_STABLE_VAL);\n\t} else if (priv->caps & ACCDET_PMIC_EINT1) {\n\t\tregmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,\n\t\t\t     ACCDET_EINT1_STABLE_VAL);\n\t}\n\t/* after receive n+1 number, interrupt issued. */\n\tregmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR,\n\t\t\t   ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT,\n\t\t\t   BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT));\n\t/* setting HW mode, enable digital fast discharge\n\t * if use EINT0 & EINT1 detection, please modify\n\t * ACCDET_HWMODE_EN_ADDR[2:1]\n\t */\n\tregmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100);\n\n\tregmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR,\n\t\t\t   ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0);\n\n\t/* enable PWM */\n\tregmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67);\n\t/* enable inverter detection */\n\tif (priv->data->eint_detect_mode == 0x1) {\n\t\t/* disable inverter detection */\n\t\tif (priv->caps & ACCDET_PMIC_EINT0) {\n\t\t\tregmap_update_bits(priv->regmap,\n\t\t\t\t\t   ACCDET_EINT0_INVERTER_SW_EN_ADDR,\n\t\t\t\t\t   ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,\n\t\t\t\t\t   0);\n\t\t} else if (priv->caps & ACCDET_PMIC_EINT1) {\n\t\t\tregmap_update_bits(priv->regmap,\n\t\t\t\t\t   ACCDET_EINT1_INVERTER_SW_EN_ADDR,\n\t\t\t\t\t   ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,\n\t\t\t\t\t   0);\n\t\t}\n\t} else {\n\t\tif (priv->caps & ACCDET_PMIC_EINT0) {\n\t\t\tregmap_update_bits(priv->regmap,\n\t\t\t\t\t   ACCDET_EINT0_INVERTER_SW_EN_ADDR,\n\t\t\t\t\t   ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,\n\t\t\t\t\t   BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));\n\t\t} else if (priv->caps & ACCDET_PMIC_EINT1) {\n\t\t\tregmap_update_bits(priv->regmap,\n\t\t\t\t\t   ACCDET_EINT1_INVERTER_SW_EN_ADDR,\n\t\t\t\t\t   ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,\n\t\t\t\t\t   BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));\n\t\t}\n\t}\n}",
        "static bool khugepaged_prealloc_page(struct page **hpage, bool *wait)\n{\n\t/*\n\t * If the hpage allocated earlier was briefly exposed in page cache\n\t * before collapse_file() failed, it is possible that racing lookups": "static bool khugepaged_prealloc_page(struct page **hpage, bool *wait)\n{\n\t/*\n\t * If the hpage allocated earlier was briefly exposed in page cache\n\t * before collapse_file() failed, it is possible that racing lookups\n\t * have not yet completed, and would then be unpleasantly surprised by\n\t * finding the hpage reused for the same mapping at a different offset.\n\t * Just release the previous allocation if there is any danger of that.\n\t */\n\tif (*hpage && page_count(*hpage) > 1) {\n\t\tput_page(*hpage);\n\t\t*hpage = NULL;\n\t}\n\n\tif (!*hpage)\n\t\t*hpage = khugepaged_alloc_hugepage(wait);\n\n\tif (unlikely(!*hpage))\n\t\treturn false;\n\n\treturn true;\n}",
        "static unsigned long fast_find_migrateblock(struct compact_control *cc)\n{\n\tunsigned int limit = freelist_scan_limit(cc);\n\tunsigned int nr_scanned = 0;\n\tunsigned long distance;": "static unsigned long fast_find_migrateblock(struct compact_control *cc)\n{\n\tunsigned int limit = freelist_scan_limit(cc);\n\tunsigned int nr_scanned = 0;\n\tunsigned long distance;\n\tunsigned long pfn = cc->migrate_pfn;\n\tunsigned long high_pfn;\n\tint order;\n\tbool found_block = false;\n\n\t/* Skip hints are relied on to avoid repeats on the fast search */\n\tif (cc->ignore_skip_hint)\n\t\treturn pfn;\n\n\t/*\n\t * If the migrate_pfn is not at the start of a zone or the start\n\t * of a pageblock then assume this is a continuation of a previous\n\t * scan restarted due to COMPACT_CLUSTER_MAX.\n\t */\n\tif (pfn != cc->zone->zone_start_pfn && pfn != pageblock_start_pfn(pfn))\n\t\treturn pfn;\n\n\t/*\n\t * For smaller orders, just linearly scan as the number of pages\n\t * to migrate should be relatively small and does not necessarily\n\t * justify freeing up a large block for a small allocation.\n\t */\n\tif (cc->order <= PAGE_ALLOC_COSTLY_ORDER)\n\t\treturn pfn;\n\n\t/*\n\t * Only allow kcompactd and direct requests for movable pages to\n\t * quickly clear out a MOVABLE pageblock for allocation. This\n\t * reduces the risk that a large movable pageblock is freed for\n\t * an unmovable/reclaimable small allocation.\n\t */\n\tif (cc->direct_compaction && cc->migratetype != MIGRATE_MOVABLE)\n\t\treturn pfn;\n\n\t/*\n\t * When starting the migration scanner, pick any pageblock within the\n\t * first half of the search space. Otherwise try and pick a pageblock\n\t * within the first eighth to reduce the chances that a migration\n\t * target later becomes a source.\n\t */\n\tdistance = (cc->free_pfn - cc->migrate_pfn) >> 1;\n\tif (cc->migrate_pfn != cc->zone->zone_start_pfn)\n\t\tdistance >>= 2;\n\thigh_pfn = pageblock_start_pfn(cc->migrate_pfn + distance);\n\n\tfor (order = cc->order - 1;\n\t     order >= PAGE_ALLOC_COSTLY_ORDER && !found_block && nr_scanned < limit;\n\t     order--) {\n\t\tstruct free_area *area = &cc->zone->free_area[order];\n\t\tstruct list_head *freelist;\n\t\tunsigned long flags;\n\t\tstruct page *freepage;\n\n\t\tif (!area->nr_free)\n\t\t\tcontinue;\n\n\t\tspin_lock_irqsave(&cc->zone->lock, flags);\n\t\tfreelist = &area->free_list[MIGRATE_MOVABLE];\n\t\tlist_for_each_entry(freepage, freelist, lru) {\n\t\t\tunsigned long free_pfn;\n\n\t\t\tif (nr_scanned++ >= limit) {\n\t\t\t\tmove_freelist_tail(freelist, freepage);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tfree_pfn = page_to_pfn(freepage);\n\t\t\tif (free_pfn < high_pfn) {\n\t\t\t\t/*\n\t\t\t\t * Avoid if skipped recently. Ideally it would\n\t\t\t\t * move to the tail but even safe iteration of\n\t\t\t\t * the list assumes an entry is deleted, not\n\t\t\t\t * reordered.\n\t\t\t\t */\n\t\t\t\tif (get_pageblock_skip(freepage))\n\t\t\t\t\tcontinue;\n\n\t\t\t\t/* Reorder to so a future search skips recent pages */\n\t\t\t\tmove_freelist_tail(freelist, freepage);\n\n\t\t\t\tupdate_fast_start_pfn(cc, free_pfn);\n\t\t\t\tpfn = pageblock_start_pfn(free_pfn);\n\t\t\t\tif (pfn < cc->zone->zone_start_pfn)\n\t\t\t\t\tpfn = cc->zone->zone_start_pfn;\n\t\t\t\tcc->fast_search_fail = 0;\n\t\t\t\tfound_block = true;\n\t\t\t\tset_pageblock_skip(freepage);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tspin_unlock_irqrestore(&cc->zone->lock, flags);\n\t}\n\n\tcc->total_migrate_scanned += nr_scanned;\n\n\t/*\n\t * If fast scanning failed then use a cached entry for a page block\n\t * that had free pages as the basis for starting a linear scan.\n\t */\n\tif (!found_block) {\n\t\tcc->fast_search_fail++;\n\t\tpfn = reinit_migrate_pfn(cc);\n\t}\n\treturn pfn;\n}",
        "static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)\n{\n\tconst struct net_device *ndev = priv->ndev;\n\tconst struct mcp251xfd_devtype_data *devtype_data;\n\tu32 osc;": "static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)\n{\n\tconst struct net_device *ndev = priv->ndev;\n\tconst struct mcp251xfd_devtype_data *devtype_data;\n\tu32 osc;\n\tint err;\n\n\t/* The OSC_LPMEN is only supported on MCP2518FD, so use it to\n\t * autodetect the model.\n\t */\n\terr = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,\n\t\t\t\t MCP251XFD_REG_OSC_LPMEN,\n\t\t\t\t MCP251XFD_REG_OSC_LPMEN);\n\tif (err)\n\t\treturn err;\n\n\terr = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);\n\tif (err)\n\t\treturn err;\n\n\tif (osc & MCP251XFD_REG_OSC_LPMEN)\n\t\tdevtype_data = &mcp251xfd_devtype_data_mcp2518fd;\n\telse\n\t\tdevtype_data = &mcp251xfd_devtype_data_mcp2517fd;\n\n\tif (!mcp251xfd_is_251XFD(priv) &&\n\t    priv->devtype_data.model != devtype_data->model) {\n\t\tnetdev_info(ndev,\n\t\t\t    \"Detected %s, but firmware specifies a %s. Fixing up.\\n\",\n\t\t\t    __mcp251xfd_get_model_str(devtype_data->model),\n\t\t\t    mcp251xfd_get_model_str(priv));\n\t}\n\tpriv->devtype_data = *devtype_data;\n\n\t/* We need to preserve the Half Duplex Quirk. */\n\tmcp251xfd_register_quirks(priv);\n\n\t/* Re-init regmap with quirks of detected model. */\n\treturn mcp251xfd_regmap_init(priv);\n}",
        "static void kfence_guarded_free(void *addr, struct kfence_metadata *meta, bool zombie)\n{\n\tstruct kcsan_scoped_access assert_page_exclusive;\n\tunsigned long flags;\n\tbool init;": "static void kfence_guarded_free(void *addr, struct kfence_metadata *meta, bool zombie)\n{\n\tstruct kcsan_scoped_access assert_page_exclusive;\n\tunsigned long flags;\n\tbool init;\n\n\traw_spin_lock_irqsave(&meta->lock, flags);\n\n\tif (meta->state != KFENCE_OBJECT_ALLOCATED || meta->addr != (unsigned long)addr) {\n\t\t/* Invalid or double-free, bail out. */\n\t\tatomic_long_inc(&counters[KFENCE_COUNTER_BUGS]);\n\t\tkfence_report_error((unsigned long)addr, false, NULL, meta,\n\t\t\t\t    KFENCE_ERROR_INVALID_FREE);\n\t\traw_spin_unlock_irqrestore(&meta->lock, flags);\n\t\treturn;\n\t}\n\n\t/* Detect racy use-after-free, or incorrect reallocation of this page by KFENCE. */\n\tkcsan_begin_scoped_access((void *)ALIGN_DOWN((unsigned long)addr, PAGE_SIZE), PAGE_SIZE,\n\t\t\t\t  KCSAN_ACCESS_SCOPED | KCSAN_ACCESS_WRITE | KCSAN_ACCESS_ASSERT,\n\t\t\t\t  &assert_page_exclusive);\n\n\tif (CONFIG_KFENCE_STRESS_TEST_FAULTS)\n\t\tkfence_unprotect((unsigned long)addr); /* To check canary bytes. */\n\n\t/* Restore page protection if there was an OOB access. */\n\tif (meta->unprotected_page) {\n\t\tmemzero_explicit((void *)ALIGN_DOWN(meta->unprotected_page, PAGE_SIZE), PAGE_SIZE);\n\t\tkfence_protect(meta->unprotected_page);\n\t\tmeta->unprotected_page = 0;\n\t}\n\n\t/* Mark the object as freed. */\n\tmetadata_update_state(meta, KFENCE_OBJECT_FREED, NULL, 0);\n\tinit = slab_want_init_on_free(meta->cache);\n\traw_spin_unlock_irqrestore(&meta->lock, flags);\n\n\talloc_covered_add(meta->alloc_stack_hash, -1);\n\n\t/* Check canary bytes for memory corruption. */\n\tfor_each_canary(meta, check_canary_byte);\n\n\t/*\n\t * Clear memory if init-on-free is set. While we protect the page, the\n\t * data is still there, and after a use-after-free is detected, we\n\t * unprotect the page, so the data is still accessible.\n\t */\n\tif (!zombie && unlikely(init))\n\t\tmemzero_explicit(addr, meta->size);\n\n\t/* Protect to detect use-after-frees. */\n\tkfence_protect((unsigned long)addr);\n\n\tkcsan_end_scoped_access(&assert_page_exclusive);\n\tif (!zombie) {\n\t\t/* Add it to the tail of the freelist for reuse. */\n\t\traw_spin_lock_irqsave(&kfence_freelist_lock, flags);\n\t\tKFENCE_WARN_ON(!list_empty(&meta->list));\n\t\tlist_add_tail(&meta->list, &kfence_freelist);\n\t\traw_spin_unlock_irqrestore(&kfence_freelist_lock, flags);\n\n\t\tatomic_long_dec(&counters[KFENCE_COUNTER_ALLOCATED]);\n\t\tatomic_long_inc(&counters[KFENCE_COUNTER_FREES]);\n\t} else {\n\t\t/* See kfence_shutdown_cache(). */\n\t\tatomic_long_inc(&counters[KFENCE_COUNTER_ZOMBIES]);\n\t}\n}",
        "static void rebalance_domains(struct rq *rq, enum cpu_idle_type idle)\n{\n\tint continue_balancing = 1;\n\tint cpu = rq->cpu;\n\tint busy = idle != CPU_IDLE && !sched_idle_cpu(cpu);": "static void rebalance_domains(struct rq *rq, enum cpu_idle_type idle)\n{\n\tint continue_balancing = 1;\n\tint cpu = rq->cpu;\n\tint busy = idle != CPU_IDLE && !sched_idle_cpu(cpu);\n\tunsigned long interval;\n\tstruct sched_domain *sd;\n\t/* Earliest time when we have to do rebalance again */\n\tunsigned long next_balance = jiffies + 60*HZ;\n\tint update_next_balance = 0;\n\tint need_serialize, need_decay = 0;\n\tu64 max_cost = 0;\n\n\trcu_read_lock();\n\tfor_each_domain(cpu, sd) {\n\t\t/*\n\t\t * Decay the newidle max times here because this is a regular\n\t\t * visit to all the domains.\n\t\t */\n\t\tneed_decay = update_newidle_cost(sd, 0);\n\t\tmax_cost += sd->max_newidle_lb_cost;\n\n\t\t/*\n\t\t * Stop the load balance at this level. There is another\n\t\t * CPU in our sched group which is doing load balancing more\n\t\t * actively.\n\t\t */\n\t\tif (!continue_balancing) {\n\t\t\tif (need_decay)\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\t\t}\n\n\t\tinterval = get_sd_balance_interval(sd, busy);\n\n\t\tneed_serialize = sd->flags & SD_SERIALIZE;\n\t\tif (need_serialize) {\n\t\t\tif (!spin_trylock(&balancing))\n\t\t\t\tgoto out;\n\t\t}\n\n\t\tif (time_after_eq(jiffies, sd->last_balance + interval)) {\n\t\t\tif (load_balance(cpu, rq, sd, idle, &continue_balancing)) {\n\t\t\t\t/*\n\t\t\t\t * The LBF_DST_PINNED logic could have changed\n\t\t\t\t * env->dst_cpu, so we can't know our idle\n\t\t\t\t * state even if we migrated tasks. Update it.\n\t\t\t\t */\n\t\t\t\tidle = idle_cpu(cpu) ? CPU_IDLE : CPU_NOT_IDLE;\n\t\t\t\tbusy = idle != CPU_IDLE && !sched_idle_cpu(cpu);\n\t\t\t}\n\t\t\tsd->last_balance = jiffies;\n\t\t\tinterval = get_sd_balance_interval(sd, busy);\n\t\t}\n\t\tif (need_serialize)\n\t\t\tspin_unlock(&balancing);\nout:\n\t\tif (time_after(next_balance, sd->last_balance + interval)) {\n\t\t\tnext_balance = sd->last_balance + interval;\n\t\t\tupdate_next_balance = 1;\n\t\t}\n\t}\n\tif (need_decay) {\n\t\t/*\n\t\t * Ensure the rq-wide value also decays but keep it at a\n\t\t * reasonable floor to avoid funnies with rq->avg_idle.\n\t\t */\n\t\trq->max_idle_balance_cost =\n\t\t\tmax((u64)sysctl_sched_migration_cost, max_cost);\n\t}\n\trcu_read_unlock();\n\n\t/*\n\t * next_balance will be updated only when there is a need.\n\t * When the cpu is attached to null domain for ex, it will not be\n\t * updated.\n\t */\n\tif (likely(update_next_balance))\n\t\trq->next_balance = next_balance;\n\n}",
        "static void test_lru_sanity2(int map_type, int map_flags, unsigned int tgt_free)\n{\n\tunsigned long long key, value[nr_cpus];\n\tunsigned long long end_key;\n\tint lru_map_fd, expected_map_fd;": "static void test_lru_sanity2(int map_type, int map_flags, unsigned int tgt_free)\n{\n\tunsigned long long key, value[nr_cpus];\n\tunsigned long long end_key;\n\tint lru_map_fd, expected_map_fd;\n\tunsigned int batch_size;\n\tunsigned int map_size;\n\tint next_cpu = 0;\n\n\tif (map_flags & BPF_F_NO_COMMON_LRU)\n\t\t/* This test is only applicable to common LRU list */\n\t\treturn;\n\n\tprintf(\"%s (map_type:%d map_flags:0x%X): \", __func__, map_type,\n\t       map_flags);\n\n\tassert(sched_next_online(0, &next_cpu) != -1);\n\n\tbatch_size = tgt_free / 2;\n\tassert(batch_size * 2 == tgt_free);\n\n\tmap_size = tgt_free + batch_size;\n\tlru_map_fd = create_map(map_type, map_flags, map_size);\n\tassert(lru_map_fd != -1);\n\n\texpected_map_fd = create_map(BPF_MAP_TYPE_HASH, 0, map_size);\n\tassert(expected_map_fd != -1);\n\n\tvalue[0] = 1234;\n\n\t/* Insert 1 to tgt_free (+tgt_free keys) */\n\tend_key = 1 + tgt_free;\n\tfor (key = 1; key < end_key; key++)\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\n\t/* Any bpf_map_update_elem will require to acquire a new node\n\t * from LRU first.\n\t *\n\t * The local list is running out of free nodes.\n\t * It gets from the global LRU list which tries to\n\t * shrink the inactive list to get tgt_free\n\t * number of free nodes.\n\t *\n\t * Hence, the oldest key 1 to tgt_free/2\n\t * are removed from the LRU list.\n\t */\n\tkey = 1;\n\tif (map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH) {\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t\tassert(!bpf_map_delete_elem(lru_map_fd, &key));\n\t} else {\n\t\tassert(bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t   BPF_EXIST));\n\t}\n\n\t/* Re-insert 1 to tgt_free/2 again and do a lookup\n\t * immeidately.\n\t */\n\tend_key = 1 + batch_size;\n\tvalue[0] = 4321;\n\tfor (key = 1; key < end_key; key++) {\n\t\tassert(bpf_map_lookup_elem(lru_map_fd, &key, value) == -ENOENT);\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t\tassert(!bpf_map_lookup_elem_with_ref_bit(lru_map_fd, key, value));\n\t\tassert(value[0] == 4321);\n\t\tassert(!bpf_map_update_elem(expected_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t}\n\n\tvalue[0] = 1234;\n\n\t/* Insert 1+tgt_free to tgt_free*3/2 */\n\tend_key = 1 + tgt_free + batch_size;\n\tfor (key = 1 + tgt_free; key < end_key; key++)\n\t\t/* These newly added but not referenced keys will be\n\t\t * gone during the next LRU shrink.\n\t\t */\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\n\t/* Insert 1+tgt_free*3/2 to  tgt_free*5/2 */\n\tend_key = key + tgt_free;\n\tfor (; key < end_key; key++) {\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t\tassert(!bpf_map_update_elem(expected_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t}\n\n\tassert(map_equal(lru_map_fd, expected_map_fd));\n\n\tclose(expected_map_fd);\n\tclose(lru_map_fd);\n\n\tprintf(\"Pass\\n\");\n}",
        "static int max9286_setup(struct max9286_priv *priv)\n{\n\t/*\n\t * Link ordering values for all enabled links combinations. Orders must\n\t * be assigned sequentially from 0 to the number of enabled links": "static int max9286_setup(struct max9286_priv *priv)\n{\n\t/*\n\t * Link ordering values for all enabled links combinations. Orders must\n\t * be assigned sequentially from 0 to the number of enabled links\n\t * without leaving any hole for disabled links. We thus assign orders to\n\t * enabled links first, and use the remaining order values for disabled\n\t * links are all links must have a different order value;\n\t */\n\tstatic const u8 link_order[] = {\n\t\t(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */\n\t\t(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */\n\t\t(3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */\n\t\t(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */\n\t\t(3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */\n\t\t(3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */\n\t\t(3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */\n\t\t(3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */\n\t\t(0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */\n\t\t(1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */\n\t\t(1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */\n\t\t(2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */\n\t\t(1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */\n\t\t(2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */\n\t\t(2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */\n\t\t(3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */\n\t};\n\n\t/*\n\t * Set the I2C bus speed.\n\t *\n\t * Enable I2C Local Acknowledge during the probe sequences of the camera\n\t * only. This should be disabled after the mux is initialised.\n\t */\n\tmax9286_configure_i2c(priv, true);\n\tmax9286_reverse_channel_setup(priv, priv->init_rev_chan_mv);\n\n\t/*\n\t * Enable GMSL links, mask unused ones and autodetect link\n\t * used as CSI clock source.\n\t */\n\tmax9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);\n\tmax9286_write(priv, 0x0b, link_order[priv->route_mask]);\n\tmax9286_write(priv, 0x69, (0xf & ~priv->route_mask));\n\n\t/*\n\t * Video format setup:\n\t * Disable CSI output, VC is set according to Link number.\n\t */\n\tmax9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);\n\n\t/* Enable CSI-2 Lane D0-D3 only, DBL mode, YUV422 8-bit. */\n\tmax9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |\n\t\t      MAX9286_CSILANECNT(priv->csi2_data_lanes) |\n\t\t      MAX9286_DATATYPE_YUV422_8BIT);\n\n\t/* Automatic: FRAMESYNC taken from the slowest Link. */\n\tmax9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |\n\t\t      MAX9286_FSYNCMETH_AUTO);\n\n\t/* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */\n\tmax9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS |\n\t\t      MAX9286_HVSRC_D14);\n\n\t/*\n\t * The overlap window seems to provide additional validation by tracking\n\t * the delay between vsync and frame sync, generating an error if the\n\t * delay is bigger than the programmed window, though it's not yet clear\n\t * what value should be set.\n\t *\n\t * As it's an optional value and can be disabled, we do so by setting\n\t * a 0 overlap value.\n\t */\n\tmax9286_write(priv, 0x63, 0);\n\tmax9286_write(priv, 0x64, 0);\n\n\t/*\n\t * Wait for 2ms to allow the link to resynchronize after the\n\t * configuration change.\n\t */\n\tusleep_range(2000, 5000);\n\n\treturn 0;\n}",
        "static int max_tcpci_set_vbus(struct tcpci *tcpci, struct tcpci_data *tdata, bool source, bool sink)\n{\n\tstruct max_tcpci_chip *chip = tdata_to_max_tcpci(tdata);\n\tu8 buffer_source[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_SOURCE};\n\tu8 buffer_sink[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_SINK};": "static int max_tcpci_set_vbus(struct tcpci *tcpci, struct tcpci_data *tdata, bool source, bool sink)\n{\n\tstruct max_tcpci_chip *chip = tdata_to_max_tcpci(tdata);\n\tu8 buffer_source[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_SOURCE};\n\tu8 buffer_sink[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_SINK};\n\tu8 buffer_none[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_OFF};\n\tstruct i2c_client *i2c = chip->client;\n\tint ret;\n\n\tstruct i2c_msg msgs[] = {\n\t\t{\n\t\t\t.addr = MAX_BUCK_BOOST_SID,\n\t\t\t.flags = i2c->flags & I2C_M_TEN,\n\t\t\t.len = 2,\n\t\t\t.buf = source ? buffer_source : sink ? buffer_sink : buffer_none,\n\t\t},\n\t};\n\n\tif (source && sink) {\n\t\tdev_err(chip->dev, \"Both source and sink set\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tret = i2c_transfer(i2c->adapter, msgs, 1);\n\n\treturn  ret < 0 ? ret : 1;\n}",
        "static void rtl_hw_start_8117(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8117[] = {\n\t\t{ 0x19, 0x0040,\t0x1100 },\n\t\t{ 0x59, 0x0040,\t0x1100 },": "static void rtl_hw_start_8117(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8117[] = {\n\t\t{ 0x19, 0x0040,\t0x1100 },\n\t\t{ 0x59, 0x0040,\t0x1100 },\n\t};\n\tint rg_saw_cnt;\n\n\trtl8168ep_stop_cmac(tp);\n\n\t/* disable aspm and clock request before access ephy */\n\trtl_hw_aspm_clkreq_enable(tp, false);\n\trtl_ephy_init(tp, e_info_8117);\n\n\trtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);\n\trtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);\n\n\trtl_set_def_aspm_entry_latency(tp);\n\n\trtl_reset_packet_filter(tp);\n\n\trtl_eri_set_bits(tp, 0xd4, 0x0010);\n\n\trtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);\n\n\tRTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);\n\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);\n\trtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);\n\n\trtl8168_config_eee_mac(tp);\n\n\tRTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);\n\tRTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);\n\n\tRTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);\n\n\trtl_eri_clear_bits(tp, 0x1b0, BIT(12));\n\n\trtl_pcie_state_l2l3_disable(tp);\n\n\trg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;\n\tif (rg_saw_cnt > 0) {\n\t\tu16 sw_cnt_1ms_ini;\n\n\t\tsw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;\n\t\tr8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);\n\t}\n\n\tr8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);\n\tr8168_mac_ocp_write(tp, 0xea80, 0x0003);\n\tr8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);\n\tr8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);\n\n\tr8168_mac_ocp_write(tp, 0xe63e, 0x0001);\n\tr8168_mac_ocp_write(tp, 0xe63e, 0x0000);\n\tr8168_mac_ocp_write(tp, 0xc094, 0x0000);\n\tr8168_mac_ocp_write(tp, 0xc09e, 0x0000);\n\n\t/* firmware is for MAC only */\n\tr8169_apply_firmware(tp);\n\n\trtl_hw_aspm_clkreq_enable(tp, true);\n}",
        "static void s2io_set_multicast(struct net_device *dev, bool may_sleep)\n{\n\tint i, j, prev_cnt;\n\tstruct netdev_hw_addr *ha;\n\tstruct s2io_nic *sp = netdev_priv(dev);": "static void s2io_set_multicast(struct net_device *dev, bool may_sleep)\n{\n\tint i, j, prev_cnt;\n\tstruct netdev_hw_addr *ha;\n\tstruct s2io_nic *sp = netdev_priv(dev);\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;\n\tu64 val64 = 0, multi_mac = 0x010203040506ULL, mask =\n\t\t0xfeffffffffffULL;\n\tu64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;\n\tvoid __iomem *add;\n\tstruct config_param *config = &sp->config;\n\n\tif ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {\n\t\t/*  Enable all Multicast addresses */\n\t\twriteq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),\n\t\t       &bar0->rmac_addr_data0_mem);\n\t\twriteq(RMAC_ADDR_DATA1_MEM_MASK(mask),\n\t\t       &bar0->rmac_addr_data1_mem);\n\t\tval64 = RMAC_ADDR_CMD_MEM_WE |\n\t\t\tRMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |\n\t\t\tRMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);\n\t\twriteq(val64, &bar0->rmac_addr_cmd_mem);\n\t\t/* Wait till command completes */\n\t\twait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,\n\t\t\t\t      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,\n\t\t\t\t      S2IO_BIT_RESET, may_sleep);\n\n\t\tsp->m_cast_flg = 1;\n\t\tsp->all_multi_pos = config->max_mc_addr - 1;\n\t} else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {\n\t\t/*  Disable all Multicast addresses */\n\t\twriteq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),\n\t\t       &bar0->rmac_addr_data0_mem);\n\t\twriteq(RMAC_ADDR_DATA1_MEM_MASK(0x0),\n\t\t       &bar0->rmac_addr_data1_mem);\n\t\tval64 = RMAC_ADDR_CMD_MEM_WE |\n\t\t\tRMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |\n\t\t\tRMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);\n\t\twriteq(val64, &bar0->rmac_addr_cmd_mem);\n\t\t/* Wait till command completes */\n\t\twait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,\n\t\t\t\t      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,\n\t\t\t\t      S2IO_BIT_RESET, may_sleep);\n\n\t\tsp->m_cast_flg = 0;\n\t\tsp->all_multi_pos = 0;\n\t}\n\n\tif ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {\n\t\t/*  Put the NIC into promiscuous mode */\n\t\tadd = &bar0->mac_cfg;\n\t\tval64 = readq(&bar0->mac_cfg);\n\t\tval64 |= MAC_CFG_RMAC_PROM_ENABLE;\n\n\t\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\t\twritel((u32)val64, add);\n\t\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\t\twritel((u32) (val64 >> 32), (add + 4));\n\n\t\tif (vlan_tag_strip != 1) {\n\t\t\tval64 = readq(&bar0->rx_pa_cfg);\n\t\t\tval64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;\n\t\t\twriteq(val64, &bar0->rx_pa_cfg);\n\t\t\tsp->vlan_strip_flag = 0;\n\t\t}\n\n\t\tval64 = readq(&bar0->mac_cfg);\n\t\tsp->promisc_flg = 1;\n\t\tDBG_PRINT(INFO_DBG, \"%s: entered promiscuous mode\\n\",\n\t\t\t  dev->name);\n\t} else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {\n\t\t/*  Remove the NIC from promiscuous mode */\n\t\tadd = &bar0->mac_cfg;\n\t\tval64 = readq(&bar0->mac_cfg);\n\t\tval64 &= ~MAC_CFG_RMAC_PROM_ENABLE;\n\n\t\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\t\twritel((u32)val64, add);\n\t\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\t\twritel((u32) (val64 >> 32), (add + 4));\n\n\t\tif (vlan_tag_strip != 0) {\n\t\t\tval64 = readq(&bar0->rx_pa_cfg);\n\t\t\tval64 |= RX_PA_CFG_STRIP_VLAN_TAG;\n\t\t\twriteq(val64, &bar0->rx_pa_cfg);\n\t\t\tsp->vlan_strip_flag = 1;\n\t\t}\n\n\t\tval64 = readq(&bar0->mac_cfg);\n\t\tsp->promisc_flg = 0;\n\t\tDBG_PRINT(INFO_DBG, \"%s: left promiscuous mode\\n\", dev->name);\n\t}\n\n\t/*  Update individual M_CAST address list */\n\tif ((!sp->m_cast_flg) && netdev_mc_count(dev)) {\n\t\tif (netdev_mc_count(dev) >\n\t\t    (config->max_mc_addr - config->max_mac_addr)) {\n\t\t\tDBG_PRINT(ERR_DBG,\n\t\t\t\t  \"%s: No more Rx filters can be added - \"\n\t\t\t\t  \"please enable ALL_MULTI instead\\n\",\n\t\t\t\t  dev->name);\n\t\t\treturn;\n\t\t}\n\n\t\tprev_cnt = sp->mc_addr_count;\n\t\tsp->mc_addr_count = netdev_mc_count(dev);\n\n\t\t/* Clear out the previous list of Mc in the H/W. */\n\t\tfor (i = 0; i < prev_cnt; i++) {\n\t\t\twriteq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),\n\t\t\t       &bar0->rmac_addr_data0_mem);\n\t\t\twriteq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),\n\t\t\t       &bar0->rmac_addr_data1_mem);\n\t\t\tval64 = RMAC_ADDR_CMD_MEM_WE |\n\t\t\t\tRMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |\n\t\t\t\tRMAC_ADDR_CMD_MEM_OFFSET\n\t\t\t\t(config->mc_start_offset + i);\n\t\t\twriteq(val64, &bar0->rmac_addr_cmd_mem);\n\n\t\t\t/* Wait for command completes */\n\t\t\tif (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,\n\t\t\t\t\t\t  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,\n\t\t\t\t\t\t  S2IO_BIT_RESET, may_sleep)) {\n\t\t\t\tDBG_PRINT(ERR_DBG,\n\t\t\t\t\t  \"%s: Adding Multicasts failed\\n\",\n\t\t\t\t\t  dev->name);\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\t/* Create the new Rx filter list and update the same in H/W. */\n\t\ti = 0;\n\t\tnetdev_for_each_mc_addr(ha, dev) {\n\t\t\tmac_addr = 0;\n\t\t\tfor (j = 0; j < ETH_ALEN; j++) {\n\t\t\t\tmac_addr |= ha->addr[j];\n\t\t\t\tmac_addr <<= 8;\n\t\t\t}\n\t\t\tmac_addr >>= 8;\n\t\t\twriteq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),\n\t\t\t       &bar0->rmac_addr_data0_mem);\n\t\t\twriteq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),\n\t\t\t       &bar0->rmac_addr_data1_mem);\n\t\t\tval64 = RMAC_ADDR_CMD_MEM_WE |\n\t\t\t\tRMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |\n\t\t\t\tRMAC_ADDR_CMD_MEM_OFFSET\n\t\t\t\t(i + config->mc_start_offset);\n\t\t\twriteq(val64, &bar0->rmac_addr_cmd_mem);\n\n\t\t\t/* Wait for command completes */\n\t\t\tif (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,\n\t\t\t\t\t\t  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,\n\t\t\t\t\t\t  S2IO_BIT_RESET, may_sleep)) {\n\t\t\t\tDBG_PRINT(ERR_DBG,\n\t\t\t\t\t  \"%s: Adding Multicasts failed\\n\",\n\t\t\t\t\t  dev->name);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n}",
        "static void smc_wr_init_sge(struct smc_link *lnk)\n{\n\tint sges_per_buf = (lnk->lgr->smc_version == SMC_V2) ? 2 : 1;\n\tbool send_inline = (lnk->qp_attr.cap.max_inline_data > SMC_WR_TX_SIZE);\n\tu32 i;": "static void smc_wr_init_sge(struct smc_link *lnk)\n{\n\tint sges_per_buf = (lnk->lgr->smc_version == SMC_V2) ? 2 : 1;\n\tbool send_inline = (lnk->qp_attr.cap.max_inline_data > SMC_WR_TX_SIZE);\n\tu32 i;\n\n\tfor (i = 0; i < lnk->wr_tx_cnt; i++) {\n\t\tlnk->wr_tx_sges[i].addr = send_inline ? (uintptr_t)(&lnk->wr_tx_bufs[i]) :\n\t\t\tlnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;\n\t\tlnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;\n\t\tlnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;\n\t\tlnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge[0].lkey =\n\t\t\tlnk->roce_pd->local_dma_lkey;\n\t\tlnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge[1].lkey =\n\t\t\tlnk->roce_pd->local_dma_lkey;\n\t\tlnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge[0].lkey =\n\t\t\tlnk->roce_pd->local_dma_lkey;\n\t\tlnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge[1].lkey =\n\t\t\tlnk->roce_pd->local_dma_lkey;\n\t\tlnk->wr_tx_ibs[i].next = NULL;\n\t\tlnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];\n\t\tlnk->wr_tx_ibs[i].num_sge = 1;\n\t\tlnk->wr_tx_ibs[i].opcode = IB_WR_SEND;\n\t\tlnk->wr_tx_ibs[i].send_flags =\n\t\t\tIB_SEND_SIGNALED | IB_SEND_SOLICITED;\n\t\tif (send_inline)\n\t\t\tlnk->wr_tx_ibs[i].send_flags |= IB_SEND_INLINE;\n\t\tlnk->wr_tx_rdmas[i].wr_tx_rdma[0].wr.opcode = IB_WR_RDMA_WRITE;\n\t\tlnk->wr_tx_rdmas[i].wr_tx_rdma[1].wr.opcode = IB_WR_RDMA_WRITE;\n\t\tlnk->wr_tx_rdmas[i].wr_tx_rdma[0].wr.sg_list =\n\t\t\tlnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge;\n\t\tlnk->wr_tx_rdmas[i].wr_tx_rdma[1].wr.sg_list =\n\t\t\tlnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge;\n\t}\n\n\tif (lnk->lgr->smc_version == SMC_V2) {\n\t\tlnk->wr_tx_v2_sge->addr = lnk->wr_tx_v2_dma_addr;\n\t\tlnk->wr_tx_v2_sge->length = SMC_WR_BUF_V2_SIZE;\n\t\tlnk->wr_tx_v2_sge->lkey = lnk->roce_pd->local_dma_lkey;\n\n\t\tlnk->wr_tx_v2_ib->next = NULL;\n\t\tlnk->wr_tx_v2_ib->sg_list = lnk->wr_tx_v2_sge;\n\t\tlnk->wr_tx_v2_ib->num_sge = 1;\n\t\tlnk->wr_tx_v2_ib->opcode = IB_WR_SEND;\n\t\tlnk->wr_tx_v2_ib->send_flags =\n\t\t\tIB_SEND_SIGNALED | IB_SEND_SOLICITED;\n\t}\n\n\t/* With SMC-Rv2 there can be messages larger than SMC_WR_TX_SIZE.\n\t * Each ib_recv_wr gets 2 sges, the second one is a spillover buffer\n\t * and the same buffer for all sges. When a larger message arrived then\n\t * the content of the first small sge is copied to the beginning of\n\t * the larger spillover buffer, allowing easy data mapping.\n\t */\n\tfor (i = 0; i < lnk->wr_rx_cnt; i++) {\n\t\tint x = i * sges_per_buf;\n\n\t\tlnk->wr_rx_sges[x].addr =\n\t\t\tlnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;\n\t\tlnk->wr_rx_sges[x].length = SMC_WR_TX_SIZE;\n\t\tlnk->wr_rx_sges[x].lkey = lnk->roce_pd->local_dma_lkey;\n\t\tif (lnk->lgr->smc_version == SMC_V2) {\n\t\t\tlnk->wr_rx_sges[x + 1].addr =\n\t\t\t\t\tlnk->wr_rx_v2_dma_addr + SMC_WR_TX_SIZE;\n\t\t\tlnk->wr_rx_sges[x + 1].length =\n\t\t\t\t\tSMC_WR_BUF_V2_SIZE - SMC_WR_TX_SIZE;\n\t\t\tlnk->wr_rx_sges[x + 1].lkey =\n\t\t\t\t\tlnk->roce_pd->local_dma_lkey;\n\t\t}\n\t\tlnk->wr_rx_ibs[i].next = NULL;\n\t\tlnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[x];\n\t\tlnk->wr_rx_ibs[i].num_sge = sges_per_buf;\n\t}\n\tlnk->wr_reg.wr.next = NULL;\n\tlnk->wr_reg.wr.num_sge = 0;\n\tlnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;\n\tlnk->wr_reg.wr.opcode = IB_WR_REG_MR;\n\tlnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;\n}",
        "static inline bool check_index_header(const struct INDEX_HDR *hdr, size_t bytes)\n{\n\t__le16 mask;\n\tu32 min_de, de_off, used, total;\n\tconst struct NTFS_DE *e;": "static inline bool check_index_header(const struct INDEX_HDR *hdr, size_t bytes)\n{\n\t__le16 mask;\n\tu32 min_de, de_off, used, total;\n\tconst struct NTFS_DE *e;\n\n\tif (hdr_has_subnode(hdr)) {\n\t\tmin_de = sizeof(struct NTFS_DE) + sizeof(u64);\n\t\tmask = NTFS_IE_HAS_SUBNODES;\n\t} else {\n\t\tmin_de = sizeof(struct NTFS_DE);\n\t\tmask = 0;\n\t}\n\n\tde_off = le32_to_cpu(hdr->de_off);\n\tused = le32_to_cpu(hdr->used);\n\ttotal = le32_to_cpu(hdr->total);\n\n\tif (de_off > bytes - min_de || used > bytes || total > bytes ||\n\t    de_off + min_de > used || used > total) {\n\t\treturn false;\n\t}\n\n\te = Add2Ptr(hdr, de_off);\n\tfor (;;) {\n\t\tu16 esize = le16_to_cpu(e->size);\n\t\tstruct NTFS_DE *next = Add2Ptr(e, esize);\n\n\t\tif (esize < min_de || PtrOffset(hdr, next) > used ||\n\t\t    (e->flags & NTFS_IE_HAS_SUBNODES) != mask) {\n\t\t\treturn false;\n\t\t}\n\n\t\tif (de_is_last(e))\n\t\t\tbreak;\n\n\t\te = next;\n\t}\n\n\treturn true;\n}",
        "static void hmat_register_target_initiators(struct memory_target *target)\n{\n\tstatic DECLARE_BITMAP(p_nodes, MAX_NUMNODES);\n\tstruct memory_initiator *initiator;\n\tunsigned int mem_nid, cpu_nid;": "static void hmat_register_target_initiators(struct memory_target *target)\n{\n\tstatic DECLARE_BITMAP(p_nodes, MAX_NUMNODES);\n\tstruct memory_initiator *initiator;\n\tunsigned int mem_nid, cpu_nid;\n\tstruct memory_locality *loc = NULL;\n\tu32 best = 0;\n\tbool access0done = false;\n\tint i;\n\n\tmem_nid = pxm_to_node(target->memory_pxm);\n\t/*\n\t * If the Address Range Structure provides a local processor pxm, link\n\t * only that one. Otherwise, find the best performance attributes and\n\t * register all initiators that match.\n\t */\n\tif (target->processor_pxm != PXM_INVAL) {\n\t\tcpu_nid = pxm_to_node(target->processor_pxm);\n\t\tregister_memory_node_under_compute_node(mem_nid, cpu_nid, 0);\n\t\taccess0done = true;\n\t\tif (node_state(cpu_nid, N_CPU)) {\n\t\t\tregister_memory_node_under_compute_node(mem_nid, cpu_nid, 1);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (list_empty(&localities))\n\t\treturn;\n\n\t/*\n\t * We need the initiator list sorted so we can use bitmap_clear for\n\t * previously set initiators when we find a better memory accessor.\n\t * We'll also use the sorting to prime the candidate nodes with known\n\t * initiators.\n\t */\n\tbitmap_zero(p_nodes, MAX_NUMNODES);\n\tlist_sort(p_nodes, &initiators, initiator_cmp);\n\tif (!access0done) {\n\t\tfor (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {\n\t\t\tloc = localities_types[i];\n\t\t\tif (!loc)\n\t\t\t\tcontinue;\n\n\t\t\tbest = 0;\n\t\t\tlist_for_each_entry(initiator, &initiators, node) {\n\t\t\t\tu32 value;\n\n\t\t\t\tif (!test_bit(initiator->processor_pxm, p_nodes))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tvalue = hmat_initiator_perf(target, initiator,\n\t\t\t\t\t\t\t    loc->hmat_loc);\n\t\t\t\tif (hmat_update_best(loc->hmat_loc->data_type, value, &best))\n\t\t\t\t\tbitmap_clear(p_nodes, 0, initiator->processor_pxm);\n\t\t\t\tif (value != best)\n\t\t\t\t\tclear_bit(initiator->processor_pxm, p_nodes);\n\t\t\t}\n\t\t\tif (best)\n\t\t\t\thmat_update_target_access(target, loc->hmat_loc->data_type,\n\t\t\t\t\t\t\t  best, 0);\n\t\t}\n\n\t\tfor_each_set_bit(i, p_nodes, MAX_NUMNODES) {\n\t\t\tcpu_nid = pxm_to_node(i);\n\t\t\tregister_memory_node_under_compute_node(mem_nid, cpu_nid, 0);\n\t\t}\n\t}\n\n\t/* Access 1 ignores Generic Initiators */\n\tbitmap_zero(p_nodes, MAX_NUMNODES);\n\tlist_sort(p_nodes, &initiators, initiator_cmp);\n\tbest = 0;\n\tfor (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {\n\t\tloc = localities_types[i];\n\t\tif (!loc)\n\t\t\tcontinue;\n\n\t\tbest = 0;\n\t\tlist_for_each_entry(initiator, &initiators, node) {\n\t\t\tu32 value;\n\n\t\t\tif (!initiator->has_cpu) {\n\t\t\t\tclear_bit(initiator->processor_pxm, p_nodes);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (!test_bit(initiator->processor_pxm, p_nodes))\n\t\t\t\tcontinue;\n\n\t\t\tvalue = hmat_initiator_perf(target, initiator, loc->hmat_loc);\n\t\t\tif (hmat_update_best(loc->hmat_loc->data_type, value, &best))\n\t\t\t\tbitmap_clear(p_nodes, 0, initiator->processor_pxm);\n\t\t\tif (value != best)\n\t\t\t\tclear_bit(initiator->processor_pxm, p_nodes);\n\t\t}\n\t\tif (best)\n\t\t\thmat_update_target_access(target, loc->hmat_loc->data_type, best, 1);\n\t}\n\tfor_each_set_bit(i, p_nodes, MAX_NUMNODES) {\n\t\tcpu_nid = pxm_to_node(i);\n\t\tregister_memory_node_under_compute_node(mem_nid, cpu_nid, 1);\n\t}\n}",
        "static int rvu_update_lmtaddr(struct rvu *rvu, u16 pcifunc, u64 lmt_addr)\n{\n\tstruct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);\n\tu32 tbl_idx;\n\tint err = 0;": "static int rvu_update_lmtaddr(struct rvu *rvu, u16 pcifunc, u64 lmt_addr)\n{\n\tstruct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);\n\tu32 tbl_idx;\n\tint err = 0;\n\tu64 val;\n\n\t/* Read the current lmt addr of pcifunc */\n\ttbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc);\n\terr = lmtst_map_table_ops(rvu, tbl_idx, &val, LMT_TBL_OP_READ);\n\tif (err) {\n\t\tdev_err(rvu->dev,\n\t\t\t\"Failed to read LMT map table: index 0x%x err %d\\n\",\n\t\t\ttbl_idx, err);\n\t\treturn err;\n\t}\n\n\t/* Storing the seondary's lmt base address as this needs to be\n\t * reverted in FLR. Also making sure this default value doesn't\n\t * get overwritten on multiple calls to this mailbox.\n\t */\n\tif (!pfvf->lmt_base_addr)\n\t\tpfvf->lmt_base_addr = val;\n\n\t/* Update the LMT table with new addr */\n\terr = lmtst_map_table_ops(rvu, tbl_idx, &lmt_addr, LMT_TBL_OP_WRITE);\n\tif (err) {\n\t\tdev_err(rvu->dev,\n\t\t\t\"Failed to update LMT map table: index 0x%x err %d\\n\",\n\t\t\ttbl_idx, err);\n\t\treturn err;\n\t}\n\treturn 0;\n}",
        "static void igc_update_ring_itr(struct igc_q_vector *q_vector)\n{\n\tstruct igc_adapter *adapter = q_vector->adapter;\n\tint new_val = q_vector->itr_val;\n\tint avg_wire_size = 0;": "static void igc_update_ring_itr(struct igc_q_vector *q_vector)\n{\n\tstruct igc_adapter *adapter = q_vector->adapter;\n\tint new_val = q_vector->itr_val;\n\tint avg_wire_size = 0;\n\tunsigned int packets;\n\n\t/* For non-gigabit speeds, just fix the interrupt rate at 4000\n\t * ints/sec - ITR timer value of 120 ticks.\n\t */\n\tswitch (adapter->link_speed) {\n\tcase SPEED_10:\n\tcase SPEED_100:\n\t\tnew_val = IGC_4K_ITR;\n\t\tgoto set_itr_val;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tpackets = q_vector->rx.total_packets;\n\tif (packets)\n\t\tavg_wire_size = q_vector->rx.total_bytes / packets;\n\n\tpackets = q_vector->tx.total_packets;\n\tif (packets)\n\t\tavg_wire_size = max_t(u32, avg_wire_size,\n\t\t\t\t      q_vector->tx.total_bytes / packets);\n\n\t/* if avg_wire_size isn't set no work was done */\n\tif (!avg_wire_size)\n\t\tgoto clear_counts;\n\n\t/* Add 24 bytes to size to account for CRC, preamble, and gap */\n\tavg_wire_size += 24;\n\n\t/* Don't starve jumbo frames */\n\tavg_wire_size = min(avg_wire_size, 3000);\n\n\t/* Give a little boost to mid-size frames */\n\tif (avg_wire_size > 300 && avg_wire_size < 1200)\n\t\tnew_val = avg_wire_size / 3;\n\telse\n\t\tnew_val = avg_wire_size / 2;\n\n\t/* conservative mode (itr 3) eliminates the lowest_latency setting */\n\tif (new_val < IGC_20K_ITR &&\n\t    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||\n\t    (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))\n\t\tnew_val = IGC_20K_ITR;\n\nset_itr_val:\n\tif (new_val != q_vector->itr_val) {\n\t\tq_vector->itr_val = new_val;\n\t\tq_vector->set_itr = 1;\n\t}\nclear_counts:\n\tq_vector->rx.total_bytes = 0;\n\tq_vector->rx.total_packets = 0;\n\tq_vector->tx.total_bytes = 0;\n\tq_vector->tx.total_packets = 0;\n}",
        "static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;": "static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;\n\n\t/*\n\t * The register is 1-byte wide, but 1-byte transactions are not allowed\n\t * in 8D-8D-8D mode. The next register is the dummy cycle configuration\n\t * register. Since the transaction needs to be at least 2 bytes wide,\n\t * set the next register to its default value. This also makes sense\n\t * because the value was changed when enabling 8D-8D-8D mode, it should\n\t * be reset when disabling.\n\t */\n\tbuf[0] = SPINOR_MT_EXSPI;\n\tbuf[1] = SPINOR_REG_MT_CFR1V_DEF;\n\top = (struct spi_mem_op)\n\t\tMICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);\n\tret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Read flash ID to make sure the switch was successful. */\n\tret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);\n\tif (ret) {\n\t\tdev_dbg(nor->dev, \"error %d reading JEDEC ID after disabling 8D-8D-8D mode\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tif (memcmp(buf, nor->info->id, nor->info->id_len))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static void ww_test_normal(void)\n{\n\tint ret;\n\n\tWWAI(&t);": "static void ww_test_normal(void)\n{\n\tint ret;\n\n\tWWAI(&t);\n\n\t/*\n\t * None of the ww_mutex codepaths should be taken in the 'normal'\n\t * mutex calls. The easiest way to verify this is by using the\n\t * normal mutex calls, and making sure o.ctx is unmodified.\n\t */\n\n\t/* mutex_lock (and indirectly, mutex_lock_nested) */\n\to.ctx = (void *)~0UL;\n\tww_mutex_base_lock(&o.base);\n\tww_mutex_base_unlock(&o.base);\n\tWARN_ON(o.ctx != (void *)~0UL);\n\n\t/* mutex_lock_interruptible (and *_nested) */\n\to.ctx = (void *)~0UL;\n\tret = ww_mutex_base_lock_interruptible(&o.base);\n\tif (!ret)\n\t\tww_mutex_base_unlock(&o.base);\n\telse\n\t\tWARN_ON(1);\n\tWARN_ON(o.ctx != (void *)~0UL);\n\n\t/* mutex_lock_killable (and *_nested) */\n\to.ctx = (void *)~0UL;\n\tret = ww_mutex_base_lock_killable(&o.base);\n\tif (!ret)\n\t\tww_mutex_base_unlock(&o.base);\n\telse\n\t\tWARN_ON(1);\n\tWARN_ON(o.ctx != (void *)~0UL);\n\n\t/* trylock, succeeding */\n\to.ctx = (void *)~0UL;\n\tret = ww_mutex_base_trylock(&o.base);\n\tWARN_ON(!ret);\n\tif (ret)\n\t\tww_mutex_base_unlock(&o.base);\n\telse\n\t\tWARN_ON(1);\n\tWARN_ON(o.ctx != (void *)~0UL);\n\n\t/* trylock, failing */\n\to.ctx = (void *)~0UL;\n\tww_mutex_base_lock(&o.base);\n\tret = ww_mutex_base_trylock(&o.base);\n\tWARN_ON(ret);\n\tww_mutex_base_unlock(&o.base);\n\tWARN_ON(o.ctx != (void *)~0UL);\n\n\t/* nest_lock */\n\to.ctx = (void *)~0UL;\n\tww_mutex_base_lock_nest_lock(&o.base, &t);\n\tww_mutex_base_unlock(&o.base);\n\tWARN_ON(o.ctx != (void *)~0UL);\n}",
        "static int alloc_try_nid_bottom_up_cap_max_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_bottom_up_cap_max_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_256;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM() + SZ_1K;\n\tmax_addr = memblock_end_of_DRAM() + SZ_256;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr,\n\t\t\t\t\t       NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == min_addr);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static int bnx2x_prev_unload_common(struct bnx2x *bp)\n{\n\tu32 reset_reg, tmp_reg = 0, rc;\n\tbool prev_undi = false;\n\tstruct bnx2x_mac_vals mac_vals;": "static int bnx2x_prev_unload_common(struct bnx2x *bp)\n{\n\tu32 reset_reg, tmp_reg = 0, rc;\n\tbool prev_undi = false;\n\tstruct bnx2x_mac_vals mac_vals;\n\n\t/* It is possible a previous function received 'common' answer,\n\t * but hasn't loaded yet, therefore creating a scenario of\n\t * multiple functions receiving 'common' on the same path.\n\t */\n\tBNX2X_DEV_INFO(\"Common unload Flow\\n\");\n\n\tmemset(&mac_vals, 0, sizeof(mac_vals));\n\n\tif (bnx2x_prev_is_path_marked(bp))\n\t\treturn bnx2x_prev_mcp_done(bp);\n\n\treset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);\n\n\t/* Reset should be performed after BRB is emptied */\n\tif (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {\n\t\tu32 timer_count = 1000;\n\n\t\t/* Close the MAC Rx to prevent BRB from filling up */\n\t\tbnx2x_prev_unload_close_mac(bp, &mac_vals);\n\n\t\t/* close LLH filters for both ports towards the BRB */\n\t\tbnx2x_set_rx_filter(&bp->link_params, 0);\n\t\tbp->link_params.port ^= 1;\n\t\tbnx2x_set_rx_filter(&bp->link_params, 0);\n\t\tbp->link_params.port ^= 1;\n\n\t\t/* Check if the UNDI driver was previously loaded */\n\t\tif (bnx2x_prev_is_after_undi(bp)) {\n\t\t\tprev_undi = true;\n\t\t\t/* clear the UNDI indication */\n\t\t\tREG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);\n\t\t\t/* clear possible idle check errors */\n\t\t\tREG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);\n\t\t}\n\t\tif (!CHIP_IS_E1x(bp))\n\t\t\t/* block FW from writing to host */\n\t\t\tREG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);\n\n\t\t/* wait until BRB is empty */\n\t\ttmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);\n\t\twhile (timer_count) {\n\t\t\tu32 prev_brb = tmp_reg;\n\n\t\t\ttmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);\n\t\t\tif (!tmp_reg)\n\t\t\t\tbreak;\n\n\t\t\tBNX2X_DEV_INFO(\"BRB still has 0x%08x\\n\", tmp_reg);\n\n\t\t\t/* reset timer as long as BRB actually gets emptied */\n\t\t\tif (prev_brb > tmp_reg)\n\t\t\t\ttimer_count = 1000;\n\t\t\telse\n\t\t\t\ttimer_count--;\n\n\t\t\t/* If UNDI resides in memory, manually increment it */\n\t\t\tif (prev_undi)\n\t\t\t\tbnx2x_prev_unload_undi_inc(bp, 1);\n\n\t\t\tudelay(10);\n\t\t}\n\n\t\tif (!timer_count)\n\t\t\tBNX2X_ERR(\"Failed to empty BRB, hope for the best\\n\");\n\t}\n\n\t/* No packets are in the pipeline, path is ready for reset */\n\tbnx2x_reset_common(bp);\n\n\tif (mac_vals.xmac_addr)\n\t\tREG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);\n\tif (mac_vals.umac_addr[0])\n\t\tREG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);\n\tif (mac_vals.umac_addr[1])\n\t\tREG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);\n\tif (mac_vals.emac_addr)\n\t\tREG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);\n\tif (mac_vals.bmac_addr) {\n\t\tREG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);\n\t\tREG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);\n\t}\n\n\trc = bnx2x_prev_mark_path(bp, prev_undi);\n\tif (rc) {\n\t\tbnx2x_prev_mcp_done(bp);\n\t\treturn rc;\n\t}\n\n\treturn bnx2x_prev_mcp_done(bp);\n}",
        "static int bpf_object__collect_externs(struct bpf_object *obj)\n{\n\tstruct btf_type *sec, *kcfg_sec = NULL, *ksym_sec = NULL;\n\tconst struct btf_type *t;\n\tstruct extern_desc *ext;": "static int bpf_object__collect_externs(struct bpf_object *obj)\n{\n\tstruct btf_type *sec, *kcfg_sec = NULL, *ksym_sec = NULL;\n\tconst struct btf_type *t;\n\tstruct extern_desc *ext;\n\tint i, n, off, dummy_var_btf_id;\n\tconst char *ext_name, *sec_name;\n\tElf_Scn *scn;\n\tElf64_Shdr *sh;\n\n\tif (!obj->efile.symbols)\n\t\treturn 0;\n\n\tscn = elf_sec_by_idx(obj, obj->efile.symbols_shndx);\n\tsh = elf_sec_hdr(obj, scn);\n\tif (!sh || sh->sh_entsize != sizeof(Elf64_Sym))\n\t\treturn -LIBBPF_ERRNO__FORMAT;\n\n\tdummy_var_btf_id = add_dummy_ksym_var(obj->btf);\n\tif (dummy_var_btf_id < 0)\n\t\treturn dummy_var_btf_id;\n\n\tn = sh->sh_size / sh->sh_entsize;\n\tpr_debug(\"looking for externs among %d symbols...\\n\", n);\n\n\tfor (i = 0; i < n; i++) {\n\t\tElf64_Sym *sym = elf_sym_by_idx(obj, i);\n\n\t\tif (!sym)\n\t\t\treturn -LIBBPF_ERRNO__FORMAT;\n\t\tif (!sym_is_extern(sym))\n\t\t\tcontinue;\n\t\text_name = elf_sym_str(obj, sym->st_name);\n\t\tif (!ext_name || !ext_name[0])\n\t\t\tcontinue;\n\n\t\text = obj->externs;\n\t\text = libbpf_reallocarray(ext, obj->nr_extern + 1, sizeof(*ext));\n\t\tif (!ext)\n\t\t\treturn -ENOMEM;\n\t\tobj->externs = ext;\n\t\text = &ext[obj->nr_extern];\n\t\tmemset(ext, 0, sizeof(*ext));\n\t\tobj->nr_extern++;\n\n\t\text->btf_id = find_extern_btf_id(obj->btf, ext_name);\n\t\tif (ext->btf_id <= 0) {\n\t\t\tpr_warn(\"failed to find BTF for extern '%s': %d\\n\",\n\t\t\t\text_name, ext->btf_id);\n\t\t\treturn ext->btf_id;\n\t\t}\n\t\tt = btf__type_by_id(obj->btf, ext->btf_id);\n\t\text->name = btf__name_by_offset(obj->btf, t->name_off);\n\t\text->sym_idx = i;\n\t\text->is_weak = ELF64_ST_BIND(sym->st_info) == STB_WEAK;\n\n\t\text->sec_btf_id = find_extern_sec_btf_id(obj->btf, ext->btf_id);\n\t\tif (ext->sec_btf_id <= 0) {\n\t\t\tpr_warn(\"failed to find BTF for extern '%s' [%d] section: %d\\n\",\n\t\t\t\text_name, ext->btf_id, ext->sec_btf_id);\n\t\t\treturn ext->sec_btf_id;\n\t\t}\n\t\tsec = (void *)btf__type_by_id(obj->btf, ext->sec_btf_id);\n\t\tsec_name = btf__name_by_offset(obj->btf, sec->name_off);\n\n\t\tif (strcmp(sec_name, KCONFIG_SEC) == 0) {\n\t\t\tif (btf_is_func(t)) {\n\t\t\t\tpr_warn(\"extern function %s is unsupported under %s section\\n\",\n\t\t\t\t\text->name, KCONFIG_SEC);\n\t\t\t\treturn -ENOTSUP;\n\t\t\t}\n\t\t\tkcfg_sec = sec;\n\t\t\text->type = EXT_KCFG;\n\t\t\text->kcfg.sz = btf__resolve_size(obj->btf, t->type);\n\t\t\tif (ext->kcfg.sz <= 0) {\n\t\t\t\tpr_warn(\"failed to resolve size of extern (kcfg) '%s': %d\\n\",\n\t\t\t\t\text_name, ext->kcfg.sz);\n\t\t\t\treturn ext->kcfg.sz;\n\t\t\t}\n\t\t\text->kcfg.align = btf__align_of(obj->btf, t->type);\n\t\t\tif (ext->kcfg.align <= 0) {\n\t\t\t\tpr_warn(\"failed to determine alignment of extern (kcfg) '%s': %d\\n\",\n\t\t\t\t\text_name, ext->kcfg.align);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\text->kcfg.type = find_kcfg_type(obj->btf, t->type,\n\t\t\t\t\t\t        &ext->kcfg.is_signed);\n\t\t\tif (ext->kcfg.type == KCFG_UNKNOWN) {\n\t\t\t\tpr_warn(\"extern (kcfg) '%s' type is unsupported\\n\", ext_name);\n\t\t\t\treturn -ENOTSUP;\n\t\t\t}\n\t\t} else if (strcmp(sec_name, KSYMS_SEC) == 0) {\n\t\t\tksym_sec = sec;\n\t\t\text->type = EXT_KSYM;\n\t\t\tskip_mods_and_typedefs(obj->btf, t->type,\n\t\t\t\t\t       &ext->ksym.type_id);\n\t\t} else {\n\t\t\tpr_warn(\"unrecognized extern section '%s'\\n\", sec_name);\n\t\t\treturn -ENOTSUP;\n\t\t}\n\t}\n\tpr_debug(\"collected %d externs total\\n\", obj->nr_extern);\n\n\tif (!obj->nr_extern)\n\t\treturn 0;\n\n\t/* sort externs by type, for kcfg ones also by (align, size, name) */\n\tqsort(obj->externs, obj->nr_extern, sizeof(*ext), cmp_externs);\n\n\t/* for .ksyms section, we need to turn all externs into allocated\n\t * variables in BTF to pass kernel verification; we do this by\n\t * pretending that each extern is a 8-byte variable\n\t */\n\tif (ksym_sec) {\n\t\t/* find existing 4-byte integer type in BTF to use for fake\n\t\t * extern variables in DATASEC\n\t\t */\n\t\tint int_btf_id = find_int_btf_id(obj->btf);\n\t\t/* For extern function, a dummy_var added earlier\n\t\t * will be used to replace the vs->type and\n\t\t * its name string will be used to refill\n\t\t * the missing param's name.\n\t\t */\n\t\tconst struct btf_type *dummy_var;\n\n\t\tdummy_var = btf__type_by_id(obj->btf, dummy_var_btf_id);\n\t\tfor (i = 0; i < obj->nr_extern; i++) {\n\t\t\text = &obj->externs[i];\n\t\t\tif (ext->type != EXT_KSYM)\n\t\t\t\tcontinue;\n\t\t\tpr_debug(\"extern (ksym) #%d: symbol %d, name %s\\n\",\n\t\t\t\t i, ext->sym_idx, ext->name);\n\t\t}\n\n\t\tsec = ksym_sec;\n\t\tn = btf_vlen(sec);\n\t\tfor (i = 0, off = 0; i < n; i++, off += sizeof(int)) {\n\t\t\tstruct btf_var_secinfo *vs = btf_var_secinfos(sec) + i;\n\t\t\tstruct btf_type *vt;\n\n\t\t\tvt = (void *)btf__type_by_id(obj->btf, vs->type);\n\t\t\text_name = btf__name_by_offset(obj->btf, vt->name_off);\n\t\t\text = find_extern_by_name(obj, ext_name);\n\t\t\tif (!ext) {\n\t\t\t\tpr_warn(\"failed to find extern definition for BTF %s '%s'\\n\",\n\t\t\t\t\tbtf_kind_str(vt), ext_name);\n\t\t\t\treturn -ESRCH;\n\t\t\t}\n\t\t\tif (btf_is_func(vt)) {\n\t\t\t\tconst struct btf_type *func_proto;\n\t\t\t\tstruct btf_param *param;\n\t\t\t\tint j;\n\n\t\t\t\tfunc_proto = btf__type_by_id(obj->btf,\n\t\t\t\t\t\t\t     vt->type);\n\t\t\t\tparam = btf_params(func_proto);\n\t\t\t\t/* Reuse the dummy_var string if the\n\t\t\t\t * func proto does not have param name.\n\t\t\t\t */\n\t\t\t\tfor (j = 0; j < btf_vlen(func_proto); j++)\n\t\t\t\t\tif (param[j].type && !param[j].name_off)\n\t\t\t\t\t\tparam[j].name_off =\n\t\t\t\t\t\t\tdummy_var->name_off;\n\t\t\t\tvs->type = dummy_var_btf_id;\n\t\t\t\tvt->info &= ~0xffff;\n\t\t\t\tvt->info |= BTF_FUNC_GLOBAL;\n\t\t\t} else {\n\t\t\t\tbtf_var(vt)->linkage = BTF_VAR_GLOBAL_ALLOCATED;\n\t\t\t\tvt->type = int_btf_id;\n\t\t\t}\n\t\t\tvs->offset = off;\n\t\t\tvs->size = sizeof(int);\n\t\t}\n\t\tsec->size = off;\n\t}\n\n\tif (kcfg_sec) {\n\t\tsec = kcfg_sec;\n\t\t/* for kcfg externs calculate their offsets within a .kconfig map */\n\t\toff = 0;\n\t\tfor (i = 0; i < obj->nr_extern; i++) {\n\t\t\text = &obj->externs[i];\n\t\t\tif (ext->type != EXT_KCFG)\n\t\t\t\tcontinue;\n\n\t\t\text->kcfg.data_off = roundup(off, ext->kcfg.align);\n\t\t\toff = ext->kcfg.data_off + ext->kcfg.sz;\n\t\t\tpr_debug(\"extern (kcfg) #%d: symbol %d, off %u, name %s\\n\",\n\t\t\t\t i, ext->sym_idx, ext->kcfg.data_off, ext->name);\n\t\t}\n\t\tsec->size = off;\n\t\tn = btf_vlen(sec);\n\t\tfor (i = 0; i < n; i++) {\n\t\t\tstruct btf_var_secinfo *vs = btf_var_secinfos(sec) + i;\n\n\t\t\tt = btf__type_by_id(obj->btf, vs->type);\n\t\t\text_name = btf__name_by_offset(obj->btf, t->name_off);\n\t\t\text = find_extern_by_name(obj, ext_name);\n\t\t\tif (!ext) {\n\t\t\t\tpr_warn(\"failed to find extern definition for BTF var '%s'\\n\",\n\t\t\t\t\text_name);\n\t\t\t\treturn -ESRCH;\n\t\t\t}\n\t\t\tbtf_var(t)->linkage = BTF_VAR_GLOBAL_ALLOCATED;\n\t\t\tvs->offset = ext->kcfg.data_off;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int nf_tables_commit_chain_prepare(struct net *net, struct nft_chain *chain)\n{\n\tconst struct nft_expr *expr, *last;\n\tstruct nft_regs_track track = {};\n\tunsigned int size, data_size;": "static int nf_tables_commit_chain_prepare(struct net *net, struct nft_chain *chain)\n{\n\tconst struct nft_expr *expr, *last;\n\tstruct nft_regs_track track = {};\n\tunsigned int size, data_size;\n\tvoid *data, *data_boundary;\n\tstruct nft_rule_dp *prule;\n\tstruct nft_rule *rule;\n\n\t/* already handled or inactive chain? */\n\tif (chain->blob_next || !nft_is_active_next(net, chain))\n\t\treturn 0;\n\n\tdata_size = 0;\n\tlist_for_each_entry(rule, &chain->rules, list) {\n\t\tif (nft_is_active_next(net, rule)) {\n\t\t\tdata_size += sizeof(*prule) + rule->dlen;\n\t\t\tif (data_size > INT_MAX)\n\t\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\tdata_size += offsetof(struct nft_rule_dp, data);\t/* last rule */\n\n\tchain->blob_next = nf_tables_chain_alloc_rules(data_size);\n\tif (!chain->blob_next)\n\t\treturn -ENOMEM;\n\n\tdata = (void *)chain->blob_next->data;\n\tdata_boundary = data + data_size;\n\tsize = 0;\n\n\tlist_for_each_entry(rule, &chain->rules, list) {\n\t\tif (!nft_is_active_next(net, rule))\n\t\t\tcontinue;\n\n\t\tprule = (struct nft_rule_dp *)data;\n\t\tdata += offsetof(struct nft_rule_dp, data);\n\t\tif (WARN_ON_ONCE(data > data_boundary))\n\t\t\treturn -ENOMEM;\n\n\t\tsize = 0;\n\t\ttrack.last = nft_expr_last(rule);\n\t\tnft_rule_for_each_expr(expr, last, rule) {\n\t\t\ttrack.cur = expr;\n\n\t\t\tif (nft_expr_reduce(&track, expr)) {\n\t\t\t\texpr = track.cur;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (WARN_ON_ONCE(data + expr->ops->size > data_boundary))\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tmemcpy(data + size, expr, expr->ops->size);\n\t\t\tsize += expr->ops->size;\n\t\t}\n\t\tif (WARN_ON_ONCE(size >= 1 << 12))\n\t\t\treturn -ENOMEM;\n\n\t\tprule->handle = rule->handle;\n\t\tprule->dlen = size;\n\t\tprule->is_last = 0;\n\n\t\tdata += size;\n\t\tsize = 0;\n\t\tchain->blob_next->size += (unsigned long)(data - (void *)prule);\n\t}\n\n\tprule = (struct nft_rule_dp *)data;\n\tdata += offsetof(struct nft_rule_dp, data);\n\tif (WARN_ON_ONCE(data > data_boundary))\n\t\treturn -ENOMEM;\n\n\tnft_last_rule(chain->blob_next, prule);\n\n\treturn 0;\n}",
        "static inline int todrop_entry(struct ip_vs_conn *cp)\n{\n\t/*\n\t * The drop rate array needs tuning for real environments.\n\t * Called from timer bh only => no locking": "static inline int todrop_entry(struct ip_vs_conn *cp)\n{\n\t/*\n\t * The drop rate array needs tuning for real environments.\n\t * Called from timer bh only => no locking\n\t */\n\tstatic const char todrop_rate[9] = {0, 1, 2, 3, 4, 5, 6, 7, 8};\n\tstatic char todrop_counter[9] = {0};\n\tint i;\n\n\t/* if the conn entry hasn't lasted for 60 seconds, don't drop it.\n\t   This will leave enough time for normal connection to get\n\t   through. */\n\tif (time_before(cp->timeout + jiffies, cp->timer.expires + 60*HZ))\n\t\treturn 0;\n\n\t/* Don't drop the entry if its number of incoming packets is not\n\t   located in [0, 8] */\n\ti = atomic_read(&cp->in_pkts);\n\tif (i > 8 || i < 0) return 0;\n\n\tif (!todrop_rate[i]) return 0;\n\tif (--todrop_counter[i] > 0) return 0;\n\n\ttodrop_counter[i] = todrop_rate[i];\n\treturn 1;\n}",
        "static int m88ds3103b_select_mclk(struct m88ds3103_dev *dev)\n{\n\tstruct i2c_client *client = dev->client;\n\tstruct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;\n\tu32 adc_Freq_MHz[3] = {96, 93, 99};": "static int m88ds3103b_select_mclk(struct m88ds3103_dev *dev)\n{\n\tstruct i2c_client *client = dev->client;\n\tstruct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;\n\tu32 adc_Freq_MHz[3] = {96, 93, 99};\n\tu8  reg16_list[3] = {96, 92, 100}, reg16, reg15;\n\tu32 offset_MHz[3];\n\tu32 max_offset = 0;\n\tu32 old_setting = dev->mclk;\n\tu32 tuner_freq_MHz = c->frequency / 1000;\n\tu8 i;\n\tchar big_symbol = 0;\n\n\tbig_symbol = (c->symbol_rate > 45010000) ? 1 : 0;\n\n\tif (big_symbol) {\n\t\treg16 = 115;\n\t} else {\n\t\treg16 = 96;\n\n\t\t/* TODO: IS THIS NECESSARY ? */\n\t\tfor (i = 0; i < 3; i++) {\n\t\t\toffset_MHz[i] = tuner_freq_MHz % adc_Freq_MHz[i];\n\n\t\t\tif (offset_MHz[i] > (adc_Freq_MHz[i] / 2))\n\t\t\t\toffset_MHz[i] = adc_Freq_MHz[i] - offset_MHz[i];\n\n\t\t\tif (offset_MHz[i] > max_offset) {\n\t\t\t\tmax_offset = offset_MHz[i];\n\t\t\t\treg16 = reg16_list[i];\n\t\t\t\tdev->mclk = adc_Freq_MHz[i] * 1000 * 1000;\n\n\t\t\t\tif (big_symbol)\n\t\t\t\t\tdev->mclk /= 2;\n\n\t\t\t\tdev_dbg(&client->dev, \"modifying mclk %u -> %u\\n\",\n\t\t\t\t\told_setting, dev->mclk);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (dev->mclk == 93000000)\n\t\tregmap_write(dev->regmap, 0xA0, 0x42);\n\telse if (dev->mclk == 96000000)\n\t\tregmap_write(dev->regmap, 0xA0, 0x44);\n\telse if (dev->mclk == 99000000)\n\t\tregmap_write(dev->regmap, 0xA0, 0x46);\n\telse if (dev->mclk == 110250000)\n\t\tregmap_write(dev->regmap, 0xA0, 0x4E);\n\telse\n\t\tregmap_write(dev->regmap, 0xA0, 0x44);\n\n\treg15 = m88ds3103b_dt_read(dev, 0x15);\n\n\tm88ds3103b_dt_write(dev, 0x05, 0x40);\n\tm88ds3103b_dt_write(dev, 0x11, 0x08);\n\n\tif (big_symbol)\n\t\treg15 |= 0x02;\n\telse\n\t\treg15 &= ~0x02;\n\n\tm88ds3103b_dt_write(dev, 0x15, reg15);\n\tm88ds3103b_dt_write(dev, 0x16, reg16);\n\n\tusleep_range(5000, 5500);\n\n\tm88ds3103b_dt_write(dev, 0x05, 0x00);\n\tm88ds3103b_dt_write(dev, 0x11, (u8)(big_symbol ? 0x0E : 0x0A));\n\n\tusleep_range(5000, 5500);\n\n\treturn 0;\n}",
        "static void tx_set_idle(struct slgt_info *info)\n{\n\tunsigned char val;\n\tunsigned short tcr;\n": "static void tx_set_idle(struct slgt_info *info)\n{\n\tunsigned char val;\n\tunsigned short tcr;\n\n\t/* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits\n\t * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits\n\t */\n\ttcr = rd_reg16(info, TCR);\n\tif (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {\n\t\t/* disable preamble, set idle size to 16 bits */\n\t\ttcr = (tcr & ~(BIT6 + BIT5)) | BIT4;\n\t\t/* MSB of 16 bit idle specified in tx preamble register (TPR) */\n\t\twr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));\n\t} else if (!(tcr & BIT6)) {\n\t\t/* preamble is disabled, set idle size to 8 bits */\n\t\ttcr &= ~(BIT5 + BIT4);\n\t}\n\twr_reg16(info, TCR, tcr);\n\n\tif (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {\n\t\t/* LSB of custom tx idle specified in tx idle register */\n\t\tval = (unsigned char)(info->idle_mode & 0xff);\n\t} else {\n\t\t/* standard 8 bit idle patterns */\n\t\tswitch(info->idle_mode)\n\t\t{\n\t\tcase HDLC_TXIDLE_FLAGS:          val = 0x7e; break;\n\t\tcase HDLC_TXIDLE_ALT_ZEROS_ONES:\n\t\tcase HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;\n\t\tcase HDLC_TXIDLE_ZEROS:\n\t\tcase HDLC_TXIDLE_SPACE:          val = 0x00; break;\n\t\tdefault:                         val = 0xff;\n\t\t}\n\t}\n\n\twr_reg8(info, TIR, val);\n}",
        "static void lsm_subtest(struct test_bpf_cookie *skel)\n{\n\t__u64 cookie;\n\tint prog_fd;\n\tint lsm_fd = -1;": "static void lsm_subtest(struct test_bpf_cookie *skel)\n{\n\t__u64 cookie;\n\tint prog_fd;\n\tint lsm_fd = -1;\n\tLIBBPF_OPTS(bpf_link_create_opts, link_opts);\n\n\tskel->bss->lsm_res = 0;\n\n\tcookie = 0x90000000000090L;\n\tprog_fd = bpf_program__fd(skel->progs.test_int_hook);\n\tlink_opts.tracing.cookie = cookie;\n\tlsm_fd = bpf_link_create(prog_fd, 0, BPF_LSM_MAC, &link_opts);\n\tif (!ASSERT_GE(lsm_fd, 0, \"lsm.link_create\"))\n\t\tgoto cleanup;\n\n\tstack_mprotect();\n\tif (!ASSERT_EQ(errno, EPERM, \"stack_mprotect\"))\n\t\tgoto cleanup;\n\n\tusleep(1);\n\n\tASSERT_EQ(skel->bss->lsm_res, 0x90000000000090L, \"fentry_res\");\n\ncleanup:\n\tif (lsm_fd >= 0)\n\t\tclose(lsm_fd);\n}",
        "static int ca_get_slot_info(struct dst_state *state, struct ca_slot_info *p_ca_slot_info, void __user *arg)\n{\n\tint i;\n\tstatic u8 slot_command[8] = {0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff};\n": "static int ca_get_slot_info(struct dst_state *state, struct ca_slot_info *p_ca_slot_info, void __user *arg)\n{\n\tint i;\n\tstatic u8 slot_command[8] = {0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff};\n\n\tu8 *slot_info = state->messages;\n\n\tput_checksum(&slot_command[0], 7);\n\tif ((dst_put_ci(state, slot_command, sizeof (slot_command), slot_info, GET_REPLY)) < 0) {\n\t\tdprintk(verbose, DST_CA_ERROR, 1, \" -->dst_put_ci FAILED !\");\n\t\treturn -EIO;\n\t}\n\tdprintk(verbose, DST_CA_INFO, 1, \" -->dst_put_ci SUCCESS !\");\n\n\t/*\tWill implement the rest soon\t\t*/\n\n\tdprintk(verbose, DST_CA_INFO, 1, \" Slot info = [%d]\", slot_info[3]);\n\tdprintk(verbose, DST_CA_INFO, 0, \"===================================\\n\");\n\tfor (i = 0; i < 8; i++)\n\t\tdprintk(verbose, DST_CA_INFO, 0, \" %d\", slot_info[i]);\n\tdprintk(verbose, DST_CA_INFO, 0, \"\\n\");\n\n\tif (slot_info[4] & 0x80) {\n\t\tp_ca_slot_info->flags = CA_CI_MODULE_PRESENT;\n\t\tp_ca_slot_info->num = 1;\n\t\tp_ca_slot_info->type = CA_CI;\n\t} else if (slot_info[4] & 0x40) {\n\t\tp_ca_slot_info->flags = CA_CI_MODULE_READY;\n\t\tp_ca_slot_info->num = 1;\n\t\tp_ca_slot_info->type = CA_CI;\n\t} else\n\t\tp_ca_slot_info->flags = 0;\n\n\tif (copy_to_user(arg, p_ca_slot_info, sizeof (struct ca_slot_info)))\n\t\treturn -EFAULT;\n\n\treturn 0;\n}",
        "static void cas_init_tx_dma(struct cas *cp)\n{\n\tu64 desc_dma = cp->block_dvma;\n\tunsigned long off;\n\tu32 val;": "static void cas_init_tx_dma(struct cas *cp)\n{\n\tu64 desc_dma = cp->block_dvma;\n\tunsigned long off;\n\tu32 val;\n\tint i;\n\n\t/* set up tx completion writeback registers. must be 8-byte aligned */\n#ifdef USE_TX_COMPWB\n\toff = offsetof(struct cas_init_block, tx_compwb);\n\twritel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);\n\twritel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);\n#endif\n\n\t/* enable completion writebacks, enable paced mode,\n\t * disable read pipe, and disable pre-interrupt compwbs\n\t */\n\tval =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |\n\t\tTX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |\n\t\tTX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |\n\t\tTX_CFG_INTR_COMPWB_DIS;\n\n\t/* write out tx ring info and tx desc bases */\n\tfor (i = 0; i < MAX_TX_RINGS; i++) {\n\t\toff = (unsigned long) cp->init_txds[i] -\n\t\t\t(unsigned long) cp->init_block;\n\n\t\tval |= CAS_TX_RINGN_BASE(i);\n\t\twritel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));\n\t\twritel((desc_dma + off) & 0xffffffff, cp->regs +\n\t\t       REG_TX_DBN_LOW(i));\n\t\t/* don't zero out the kick register here as the system\n\t\t * will wedge\n\t\t */\n\t}\n\twritel(val, cp->regs + REG_TX_CFG);\n\n\t/* program max burst sizes. these numbers should be different\n\t * if doing QoS.\n\t */\n#ifdef USE_QOS\n\twritel(0x800, cp->regs + REG_TX_MAXBURST_0);\n\twritel(0x1600, cp->regs + REG_TX_MAXBURST_1);\n\twritel(0x2400, cp->regs + REG_TX_MAXBURST_2);\n\twritel(0x4800, cp->regs + REG_TX_MAXBURST_3);\n#else\n\twritel(0x800, cp->regs + REG_TX_MAXBURST_0);\n\twritel(0x800, cp->regs + REG_TX_MAXBURST_1);\n\twritel(0x800, cp->regs + REG_TX_MAXBURST_2);\n\twritel(0x800, cp->regs + REG_TX_MAXBURST_3);\n#endif\n}",
        "static int ucsi_displayport_status_update(struct ucsi_dp *dp)\n{\n\tu32 cap = dp->alt->vdo;\n\n\tdp->data.status = DP_STATUS_ENABLED;": "static int ucsi_displayport_status_update(struct ucsi_dp *dp)\n{\n\tu32 cap = dp->alt->vdo;\n\n\tdp->data.status = DP_STATUS_ENABLED;\n\n\t/*\n\t * If pin assignement D is supported, claiming always\n\t * that Multi-function is preferred.\n\t */\n\tif (DP_CAP_CAPABILITY(cap) & DP_CAP_UFP_D) {\n\t\tdp->data.status |= DP_STATUS_CON_UFP_D;\n\n\t\tif (DP_CAP_UFP_D_PIN_ASSIGN(cap) & BIT(DP_PIN_ASSIGN_D))\n\t\t\tdp->data.status |= DP_STATUS_PREFER_MULTI_FUNC;\n\t} else {\n\t\tdp->data.status |= DP_STATUS_CON_DFP_D;\n\n\t\tif (DP_CAP_DFP_D_PIN_ASSIGN(cap) & BIT(DP_PIN_ASSIGN_D))\n\t\t\tdp->data.status |= DP_STATUS_PREFER_MULTI_FUNC;\n\t}\n\n\tdp->vdo_data = &dp->data.status;\n\tdp->vdo_size = 2;\n\n\treturn 0;\n}",
        "static void reset(struct tda_state *state)\n{\n\tu32   ulIFLevelAnalog = 0;\n\tu32   ulIFLevelDigital = 2;\n\tu32   ulIFLevelDVBC = 7;": "static void reset(struct tda_state *state)\n{\n\tu32   ulIFLevelAnalog = 0;\n\tu32   ulIFLevelDigital = 2;\n\tu32   ulIFLevelDVBC = 7;\n\tu32   ulIFLevelDVBT = 6;\n\tu32   ulXTOut = 0;\n\tu32   ulStandbyMode = 0x06;    /* Send in stdb, but leave osc on */\n\tu32   ulSlave = 0;\n\tu32   ulFMInput = 0;\n\tu32   ulSettlingTime = 100;\n\n\tstate->m_Frequency         = 0;\n\tstate->m_SettlingTime = 100;\n\tstate->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;\n\tstate->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;\n\tstate->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;\n\tstate->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;\n\n\tstate->m_EP4 = 0x20;\n\tif (ulXTOut != 0)\n\t\tstate->m_EP4 |= 0x40;\n\n\tstate->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;\n\tstate->m_bMaster = (ulSlave == 0);\n\n\tstate->m_SettlingTime = ulSettlingTime;\n\n\tstate->m_bFMInput = (ulFMInput == 2);\n}",
        "static int hvcs_partner_connect(struct hvcs_struct *hvcsd)\n{\n\tint retval;\n\tunsigned int unit_address = hvcsd->vdev->unit_address;\n": "static int hvcs_partner_connect(struct hvcs_struct *hvcsd)\n{\n\tint retval;\n\tunsigned int unit_address = hvcsd->vdev->unit_address;\n\n\t/*\n\t * If there wasn't any pi when the device was added it doesn't meant\n\t * there isn't any now.  This driver isn't notified when a new partner\n\t * vty is added to a vty-server so we discover changes on our own.\n\t * Please see comments in hvcs_register_connection() for justification\n\t * of this bizarre code.\n\t */\n\tretval = hvcs_register_connection(unit_address,\n\t\t\thvcsd->p_partition_ID,\n\t\t\thvcsd->p_unit_address);\n\tif (!retval) {\n\t\thvcsd->connected = 1;\n\t\treturn 0;\n\t} else if (retval != -EINVAL)\n\t\treturn retval;\n\n\t/*\n\t * As per the spec re-get the pi and try again if -EINVAL after the\n\t * first connection attempt.\n\t */\n\tif (hvcs_get_pi(hvcsd))\n\t\treturn -ENOMEM;\n\n\tif (!hvcs_has_pi(hvcsd))\n\t\treturn -ENODEV;\n\n\tretval = hvcs_register_connection(unit_address,\n\t\t\thvcsd->p_partition_ID,\n\t\t\thvcsd->p_unit_address);\n\tif (retval != -EINVAL) {\n\t\thvcsd->connected = 1;\n\t\treturn retval;\n\t}\n\n\t/*\n\t * EBUSY is the most likely scenario though the vty could have been\n\t * removed or there really could be an hcall error due to the parameter\n\t * data but thanks to ambiguous firmware return codes we can't really\n\t * tell.\n\t */\n\tprintk(KERN_INFO \"HVCS: vty-server or partner\"\n\t\t\t\" vty is busy.  Try again later.\\n\");\n\treturn -EBUSY;\n}",
        "static int mmcra_thresh_marked_sample(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\tu64 dummy;": "static int mmcra_thresh_marked_sample(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\tu64 dummy;\n\n\t/* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\n\t/* Init the event for the sampling test */\n\tevent_init_sampling(&event, EventCode);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop_with_ll_sc(1000000, &dummy);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/*\n\t * Verify that thresh sel/start/stop, marked, random sample\n\t * eligibility, sdar mode and sample mode fields match with\n\t * the corresponding event code fields\n\t */\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_sel) !=\n\t\t\tget_mmcra_thd_sel(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_start) !=\n\t\t\tget_mmcra_thd_start(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_stop) !=\n\t\t\tget_mmcra_thd_stop(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, marked) !=\n\t\t\tget_mmcra_marked(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample >> 2) !=\n\t\t\tget_mmcra_rand_samp_elig(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample & 0x3) !=\n\t\t\tget_mmcra_sample_mode(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, sm) !=\n\t\t\tget_mmcra_sm(get_reg_value(intr_regs, \"MMCRA\"), 4));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static int csi_idmac_setup_channel(struct csi_priv *priv)\n{\n\tstruct imx_media_video_dev *vdev = priv->vdev;\n\tconst struct imx_media_pixfmt *incc;\n\tstruct v4l2_mbus_framefmt *infmt;": "static int csi_idmac_setup_channel(struct csi_priv *priv)\n{\n\tstruct imx_media_video_dev *vdev = priv->vdev;\n\tconst struct imx_media_pixfmt *incc;\n\tstruct v4l2_mbus_framefmt *infmt;\n\tstruct v4l2_mbus_framefmt *outfmt;\n\tbool passthrough, interweave;\n\tstruct ipu_image image;\n\tu32 passthrough_bits;\n\tu32 passthrough_cycles;\n\tdma_addr_t phys[2];\n\tu32 burst_size;\n\tint ret;\n\n\tinfmt = &priv->format_mbus[CSI_SINK_PAD];\n\tincc = priv->cc[CSI_SINK_PAD];\n\toutfmt = &priv->format_mbus[CSI_SRC_PAD_IDMAC];\n\n\tipu_cpmem_zero(priv->idmac_ch);\n\n\tmemset(&image, 0, sizeof(image));\n\timage.pix = vdev->fmt;\n\timage.rect = vdev->compose;\n\n\tcsi_idmac_setup_vb2_buf(priv, phys);\n\n\timage.phys0 = phys[0];\n\timage.phys1 = phys[1];\n\n\tpassthrough = requires_passthrough(&priv->upstream_ep, infmt, incc);\n\tpassthrough_cycles = 1;\n\n\t/*\n\t * If the field type at capture interface is interlaced, and\n\t * the output IDMAC pad is sequential, enable interweave at\n\t * the IDMAC output channel.\n\t */\n\tinterweave = V4L2_FIELD_IS_INTERLACED(image.pix.field) &&\n\t\tV4L2_FIELD_IS_SEQUENTIAL(outfmt->field);\n\tpriv->interweave_swap = interweave &&\n\t\timage.pix.field == V4L2_FIELD_INTERLACED_BT;\n\n\tswitch (image.pix.pixelformat) {\n\tcase V4L2_PIX_FMT_SBGGR8:\n\tcase V4L2_PIX_FMT_SGBRG8:\n\tcase V4L2_PIX_FMT_SGRBG8:\n\tcase V4L2_PIX_FMT_SRGGB8:\n\tcase V4L2_PIX_FMT_GREY:\n\t\tburst_size = 16;\n\t\tpassthrough_bits = 8;\n\t\tbreak;\n\tcase V4L2_PIX_FMT_SBGGR16:\n\tcase V4L2_PIX_FMT_SGBRG16:\n\tcase V4L2_PIX_FMT_SGRBG16:\n\tcase V4L2_PIX_FMT_SRGGB16:\n\tcase V4L2_PIX_FMT_Y10:\n\tcase V4L2_PIX_FMT_Y12:\n\t\tburst_size = 8;\n\t\tpassthrough_bits = 16;\n\t\tbreak;\n\tcase V4L2_PIX_FMT_YUV420:\n\tcase V4L2_PIX_FMT_YVU420:\n\tcase V4L2_PIX_FMT_NV12:\n\t\tburst_size = (image.pix.width & 0x3f) ?\n\t\t\t     ((image.pix.width & 0x1f) ?\n\t\t\t      ((image.pix.width & 0xf) ? 8 : 16) : 32) : 64;\n\t\tpassthrough_bits = 16;\n\t\t/*\n\t\t * Skip writing U and V components to odd rows (but not\n\t\t * when enabling IDMAC interweaving, they are incompatible).\n\t\t */\n\t\tif (!interweave)\n\t\t\tipu_cpmem_skip_odd_chroma_rows(priv->idmac_ch);\n\t\tbreak;\n\tcase V4L2_PIX_FMT_YUYV:\n\tcase V4L2_PIX_FMT_UYVY:\n\t\tburst_size = (image.pix.width & 0x1f) ?\n\t\t\t     ((image.pix.width & 0xf) ? 8 : 16) : 32;\n\t\tpassthrough_bits = 16;\n\t\tbreak;\n\tcase V4L2_PIX_FMT_RGB565:\n\t\tif (passthrough) {\n\t\t\tburst_size = 16;\n\t\t\tpassthrough_bits = 8;\n\t\t\tpassthrough_cycles = incc->cycles;\n\t\t\tbreak;\n\t\t}\n\t\tfallthrough;\t/* non-passthrough RGB565 (CSI-2 bus) */\n\tdefault:\n\t\tburst_size = (image.pix.width & 0xf) ? 8 : 16;\n\t\tpassthrough_bits = 16;\n\t\tbreak;\n\t}\n\n\tif (passthrough) {\n\t\tif (priv->interweave_swap) {\n\t\t\t/* start interweave scan at 1st top line (2nd line) */\n\t\t\timage.phys0 += image.pix.bytesperline;\n\t\t\timage.phys1 += image.pix.bytesperline;\n\t\t}\n\n\t\tipu_cpmem_set_resolution(priv->idmac_ch,\n\t\t\t\t\t image.rect.width * passthrough_cycles,\n\t\t\t\t\t image.rect.height);\n\t\tipu_cpmem_set_stride(priv->idmac_ch, image.pix.bytesperline);\n\t\tipu_cpmem_set_buffer(priv->idmac_ch, 0, image.phys0);\n\t\tipu_cpmem_set_buffer(priv->idmac_ch, 1, image.phys1);\n\t\tipu_cpmem_set_format_passthrough(priv->idmac_ch,\n\t\t\t\t\t\t passthrough_bits);\n\t} else {\n\t\tif (priv->interweave_swap) {\n\t\t\t/* start interweave scan at 1st top line (2nd line) */\n\t\t\timage.rect.top = 1;\n\t\t}\n\n\t\tret = ipu_cpmem_set_image(priv->idmac_ch, &image);\n\t\tif (ret)\n\t\t\tgoto unsetup_vb2;\n\t}\n\n\tipu_cpmem_set_burstsize(priv->idmac_ch, burst_size);\n\n\t/*\n\t * Set the channel for the direct CSI-->memory via SMFC\n\t * use-case to very high priority, by enabling the watermark\n\t * signal in the SMFC, enabling WM in the channel, and setting\n\t * the channel priority to high.\n\t *\n\t * Refer to the i.mx6 rev. D TRM Table 36-8: Calculated priority\n\t * value.\n\t *\n\t * The WM's are set very low by intention here to ensure that\n\t * the SMFC FIFOs do not overflow.\n\t */\n\tipu_smfc_set_watermark(priv->smfc, 0x02, 0x01);\n\tipu_cpmem_set_high_priority(priv->idmac_ch);\n\tipu_idmac_enable_watermark(priv->idmac_ch, true);\n\tipu_cpmem_set_axi_id(priv->idmac_ch, 0);\n\n\tburst_size = passthrough ?\n\t\t(burst_size >> 3) - 1 : (burst_size >> 2) - 1;\n\n\tipu_smfc_set_burstsize(priv->smfc, burst_size);\n\n\tif (interweave)\n\t\tipu_cpmem_interlaced_scan(priv->idmac_ch,\n\t\t\t\t\t  priv->interweave_swap ?\n\t\t\t\t\t  -image.pix.bytesperline :\n\t\t\t\t\t  image.pix.bytesperline,\n\t\t\t\t\t  image.pix.pixelformat);\n\n\tipu_idmac_set_double_buffer(priv->idmac_ch, true);\n\n\treturn 0;\n\nunsetup_vb2:\n\tcsi_idmac_unsetup_vb2_buf(priv, VB2_BUF_STATE_QUEUED);\n\treturn ret;\n}",
        "static int mmcr0_fc56_pmc1ce(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n": "static int mmcr0_fc56_pmc1ce(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\n\t/* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\n\t/* Init the event for the sampling test */\n\tevent_init_sampling(&event, 0x1001e);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop(10000);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/* Verify that fc56, pmc1ce fields are set in MMCR0 */\n\tFAIL_IF(!get_mmcr0_fc56(get_reg_value(intr_regs, \"MMCR0\"), 1));\n\tFAIL_IF(!get_mmcr0_pmc1ce(get_reg_value(intr_regs, \"MMCR0\"), 1));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static void mana_hwc_comp_event(void *ctx, struct gdma_queue *q_self)\n{\n\tstruct hwc_rx_oob comp_data = {};\n\tstruct gdma_comp *completions;\n\tstruct hwc_cq *hwc_cq = ctx;": "static void mana_hwc_comp_event(void *ctx, struct gdma_queue *q_self)\n{\n\tstruct hwc_rx_oob comp_data = {};\n\tstruct gdma_comp *completions;\n\tstruct hwc_cq *hwc_cq = ctx;\n\tint comp_read, i;\n\n\tWARN_ON_ONCE(hwc_cq->gdma_cq != q_self);\n\n\tcompletions = hwc_cq->comp_buf;\n\tcomp_read = mana_gd_poll_cq(q_self, completions, hwc_cq->queue_depth);\n\tWARN_ON_ONCE(comp_read <= 0 || comp_read > hwc_cq->queue_depth);\n\n\tfor (i = 0; i < comp_read; ++i) {\n\t\tcomp_data = *(struct hwc_rx_oob *)completions[i].cqe_data;\n\n\t\tif (completions[i].is_sq)\n\t\t\thwc_cq->tx_event_handler(hwc_cq->tx_event_ctx,\n\t\t\t\t\t\tcompletions[i].wq_num,\n\t\t\t\t\t\t&comp_data);\n\t\telse\n\t\t\thwc_cq->rx_event_handler(hwc_cq->rx_event_ctx,\n\t\t\t\t\t\tcompletions[i].wq_num,\n\t\t\t\t\t\t&comp_data);\n\t}\n\n\tmana_gd_ring_cq(q_self, SET_ARM_BIT);\n}",
        "static int intel_link_power_down(struct sdw_intel *sdw)\n{\n\tu32 link_control, spa_mask, cpa_mask;\n\tunsigned int link_id = sdw->instance;\n\tvoid __iomem *shim = sdw->link_res->shim;": "static int intel_link_power_down(struct sdw_intel *sdw)\n{\n\tu32 link_control, spa_mask, cpa_mask;\n\tunsigned int link_id = sdw->instance;\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tu32 *shim_mask = sdw->link_res->shim_mask;\n\tint ret = 0;\n\n\tmutex_lock(sdw->link_res->shim_lock);\n\n\tif (!(*shim_mask & BIT(link_id)))\n\t\tdev_err(sdw->cdns.dev,\n\t\t\t\"%s: Unbalanced power-up/down calls\\n\", __func__);\n\n\tsdw->cdns.link_up = false;\n\n\tintel_shim_master_ip_to_glue(sdw);\n\n\t*shim_mask &= ~BIT(link_id);\n\n\tif (!*shim_mask) {\n\n\t\tdev_dbg(sdw->cdns.dev, \"%s: powering down all links\\n\", __func__);\n\n\t\t/* Link power down sequence */\n\t\tlink_control = intel_readl(shim, SDW_SHIM_LCTL);\n\n\t\t/* only power-down enabled links */\n\t\tspa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);\n\t\tcpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);\n\n\t\tlink_control &=  spa_mask;\n\n\t\tret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);\n\t\tif (ret < 0) {\n\t\t\tdev_err(sdw->cdns.dev, \"%s: could not power down link\\n\", __func__);\n\n\t\t\t/*\n\t\t\t * we leave the sdw->cdns.link_up flag as false since we've disabled\n\t\t\t * the link at this point and cannot handle interrupts any longer.\n\t\t\t */\n\t\t}\n\t}\n\n\tmutex_unlock(sdw->link_res->shim_lock);\n\n\treturn ret;\n}",
        "static int io_req_prep_async(struct io_kiocb *req)\n{\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\n\t/* assign early for deferred execution for non-fixed file */": "static int io_req_prep_async(struct io_kiocb *req)\n{\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\n\t/* assign early for deferred execution for non-fixed file */\n\tif (def->needs_file && !(req->flags & REQ_F_FIXED_FILE))\n\t\treq->file = io_file_get_normal(req, req->cqe.fd);\n\tif (!def->needs_async_setup)\n\t\treturn 0;\n\tif (WARN_ON_ONCE(req_has_async_data(req)))\n\t\treturn -EFAULT;\n\tif (io_alloc_async_data(req))\n\t\treturn -EAGAIN;\n\n\tswitch (req->opcode) {\n\tcase IORING_OP_READV:\n\t\treturn io_readv_prep_async(req);\n\tcase IORING_OP_WRITEV:\n\t\treturn io_writev_prep_async(req);\n\tcase IORING_OP_SENDMSG:\n\t\treturn io_sendmsg_prep_async(req);\n\tcase IORING_OP_RECVMSG:\n\t\treturn io_recvmsg_prep_async(req);\n\tcase IORING_OP_CONNECT:\n\t\treturn io_connect_prep_async(req);\n\tcase IORING_OP_URING_CMD:\n\t\treturn io_uring_cmd_prep_async(req);\n\t}\n\tprintk_once(KERN_WARNING \"io_uring: prep_async() bad opcode %d\\n\",\n\t\t    req->opcode);\n\treturn -EFAULT;\n}",
        "static int latency_exceeded(struct rq_wb *rwb, struct blk_rq_stat *stat)\n{\n\tstruct backing_dev_info *bdi = rwb->rqos.q->disk->bdi;\n\tstruct rq_depth *rqd = &rwb->rq_depth;\n\tu64 thislat;": "static int latency_exceeded(struct rq_wb *rwb, struct blk_rq_stat *stat)\n{\n\tstruct backing_dev_info *bdi = rwb->rqos.q->disk->bdi;\n\tstruct rq_depth *rqd = &rwb->rq_depth;\n\tu64 thislat;\n\n\t/*\n\t * If our stored sync issue exceeds the window size, or it\n\t * exceeds our min target AND we haven't logged any entries,\n\t * flag the latency as exceeded. wbt works off completion latencies,\n\t * but for a flooded device, a single sync IO can take a long time\n\t * to complete after being issued. If this time exceeds our\n\t * monitoring window AND we didn't see any other completions in that\n\t * window, then count that sync IO as a violation of the latency.\n\t */\n\tthislat = rwb_sync_issue_lat(rwb);\n\tif (thislat > rwb->cur_win_nsec ||\n\t    (thislat > rwb->min_lat_nsec && !stat[READ].nr_samples)) {\n\t\ttrace_wbt_lat(bdi, thislat);\n\t\treturn LAT_EXCEEDED;\n\t}\n\n\t/*\n\t * No read/write mix, if stat isn't valid\n\t */\n\tif (!stat_sample_valid(stat)) {\n\t\t/*\n\t\t * If we had writes in this stat window and the window is\n\t\t * current, we're only doing writes. If a task recently\n\t\t * waited or still has writes in flights, consider us doing\n\t\t * just writes as well.\n\t\t */\n\t\tif (stat[WRITE].nr_samples || wb_recent_wait(rwb) ||\n\t\t    wbt_inflight(rwb))\n\t\t\treturn LAT_UNKNOWN_WRITES;\n\t\treturn LAT_UNKNOWN;\n\t}\n\n\t/*\n\t * If the 'min' latency exceeds our target, step down.\n\t */\n\tif (stat[READ].min > rwb->min_lat_nsec) {\n\t\ttrace_wbt_lat(bdi, stat[READ].min);\n\t\ttrace_wbt_stat(bdi, stat);\n\t\treturn LAT_EXCEEDED;\n\t}\n\n\tif (rqd->scale_step)\n\t\ttrace_wbt_stat(bdi, stat);\n\n\treturn LAT_OK;\n}",
        "static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg)\n{\n\tu64 field[FIELDS_PER_ALG];\n\tstruct nix_hw *hw;\n\tint fid, rc;": "static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg)\n{\n\tu64 field[FIELDS_PER_ALG];\n\tstruct nix_hw *hw;\n\tint fid, rc;\n\n\thw = get_nix_hw(rvu->hw, blkaddr);\n\tif (!hw)\n\t\treturn NIX_AF_ERR_INVALID_NIXBLK;\n\n\t/* No room to add new flow hash algoritham */\n\tif (hw->flowkey.in_use >= NIX_FLOW_KEY_ALG_MAX)\n\t\treturn NIX_AF_ERR_RSS_NOSPC_ALGO;\n\n\t/* Generate algo fields for the given flow_cfg */\n\trc = set_flowkey_fields((struct nix_rx_flowkey_alg *)field, flow_cfg);\n\tif (rc)\n\t\treturn rc;\n\n\t/* Update ALGX_FIELDX register with generated fields */\n\tfor (fid = 0; fid < FIELDS_PER_ALG; fid++)\n\t\trvu_write64(rvu, blkaddr,\n\t\t\t    NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(hw->flowkey.in_use,\n\t\t\t\t\t\t\t   fid), field[fid]);\n\n\t/* Store the flow_cfg for futher lookup */\n\trc = hw->flowkey.in_use;\n\thw->flowkey.flowkey[rc] = flow_cfg;\n\thw->flowkey.in_use++;\n\n\treturn rc;\n}",
        "static void s2io_reset(struct s2io_nic *sp)\n{\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;\n\tu64 val64;\n\tu16 subid, pci_cmd;": "static void s2io_reset(struct s2io_nic *sp)\n{\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;\n\tu64 val64;\n\tu16 subid, pci_cmd;\n\tint i;\n\tu16 val16;\n\tunsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;\n\tunsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;\n\tstruct stat_block *stats;\n\tstruct swStat *swstats;\n\n\tDBG_PRINT(INIT_DBG, \"%s: Resetting XFrame card %s\\n\",\n\t\t  __func__, pci_name(sp->pdev));\n\n\t/* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */\n\tpci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));\n\n\tval64 = SW_RESET_ALL;\n\twriteq(val64, &bar0->sw_reset);\n\tif (strstr(sp->product_name, \"CX4\"))\n\t\tmsleep(750);\n\tmsleep(250);\n\tfor (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {\n\n\t\t/* Restore the PCI state saved during initialization. */\n\t\tpci_restore_state(sp->pdev);\n\t\tpci_save_state(sp->pdev);\n\t\tpci_read_config_word(sp->pdev, 0x2, &val16);\n\t\tif (check_pci_device_id(val16) != (u16)PCI_ANY_ID)\n\t\t\tbreak;\n\t\tmsleep(200);\n\t}\n\n\tif (check_pci_device_id(val16) == (u16)PCI_ANY_ID)\n\t\tDBG_PRINT(ERR_DBG, \"%s SW_Reset failed!\\n\", __func__);\n\n\tpci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);\n\n\ts2io_init_pci(sp);\n\n\t/* Set swapper to enable I/O register access */\n\ts2io_set_swapper(sp);\n\n\t/* restore mac_addr entries */\n\tdo_s2io_restore_unicast_mc(sp);\n\n\t/* Restore the MSIX table entries from local variables */\n\trestore_xmsi_data(sp);\n\n\t/* Clear certain PCI/PCI-X fields after reset */\n\tif (sp->device_type == XFRAME_II_DEVICE) {\n\t\t/* Clear \"detected parity error\" bit */\n\t\tpci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);\n\n\t\t/* Clearing PCIX Ecc status register */\n\t\tpci_write_config_dword(sp->pdev, 0x68, 0x7C);\n\n\t\t/* Clearing PCI_STATUS error reflected here */\n\t\twriteq(s2BIT(62), &bar0->txpic_int_reg);\n\t}\n\n\t/* Reset device statistics maintained by OS */\n\tmemset(&sp->stats, 0, sizeof(struct net_device_stats));\n\n\tstats = sp->mac_control.stats_info;\n\tswstats = &stats->sw_stat;\n\n\t/* save link up/down time/cnt, reset/memory/watchdog cnt */\n\tup_cnt = swstats->link_up_cnt;\n\tdown_cnt = swstats->link_down_cnt;\n\tup_time = swstats->link_up_time;\n\tdown_time = swstats->link_down_time;\n\treset_cnt = swstats->soft_reset_cnt;\n\tmem_alloc_cnt = swstats->mem_allocated;\n\tmem_free_cnt = swstats->mem_freed;\n\twatchdog_cnt = swstats->watchdog_timer_cnt;\n\n\tmemset(stats, 0, sizeof(struct stat_block));\n\n\t/* restore link up/down time/cnt, reset/memory/watchdog cnt */\n\tswstats->link_up_cnt = up_cnt;\n\tswstats->link_down_cnt = down_cnt;\n\tswstats->link_up_time = up_time;\n\tswstats->link_down_time = down_time;\n\tswstats->soft_reset_cnt = reset_cnt;\n\tswstats->mem_allocated = mem_alloc_cnt;\n\tswstats->mem_freed = mem_free_cnt;\n\tswstats->watchdog_timer_cnt = watchdog_cnt;\n\n\t/* SXE-002: Configure link and activity LED to turn it off */\n\tsubid = sp->pdev->subsystem_device;\n\tif (((subid & 0xFF) >= 0x07) &&\n\t    (sp->device_type == XFRAME_I_DEVICE)) {\n\t\tval64 = readq(&bar0->gpio_control);\n\t\tval64 |= 0x0000800000000000ULL;\n\t\twriteq(val64, &bar0->gpio_control);\n\t\tval64 = 0x0411040400000000ULL;\n\t\twriteq(val64, (void __iomem *)bar0 + 0x2700);\n\t}\n\n\t/*\n\t * Clear spurious ECC interrupts that would have occurred on\n\t * XFRAME II cards after reset.\n\t */\n\tif (sp->device_type == XFRAME_II_DEVICE) {\n\t\tval64 = readq(&bar0->pcc_err_reg);\n\t\twriteq(val64, &bar0->pcc_err_reg);\n\t}\n\n\tsp->device_enabled_once = false;\n}",
        "static int t7xx_dpmaif_bat_release_and_add(const struct dpmaif_rx_queue *rxq)\n{\n\tunsigned int bid_cnt;\n\tint ret;\n": "static int t7xx_dpmaif_bat_release_and_add(const struct dpmaif_rx_queue *rxq)\n{\n\tunsigned int bid_cnt;\n\tint ret;\n\n\tbid_cnt = t7xx_dpmaif_avail_pkt_bat_cnt(rxq->bat_req);\n\tif (bid_cnt < DPMAIF_BAT_CNT_THRESHOLD)\n\t\treturn 0;\n\n\tret = t7xx_dpmaif_release_bat_entry(rxq, bid_cnt, BAT_TYPE_NORMAL);\n\tif (ret <= 0) {\n\t\tdev_err(rxq->dpmaif_ctrl->dev, \"Release PKT BAT failed: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tret = t7xx_dpmaif_rx_buf_alloc(rxq->dpmaif_ctrl, rxq->bat_req, rxq->index, bid_cnt, false);\n\tif (ret < 0)\n\t\tdev_err(rxq->dpmaif_ctrl->dev, \"Allocate new RX buffer failed: %d\\n\", ret);\n\n\treturn ret;\n}",
        "static void set_us_coefficients(struct vpe_ctx *ctx)\n{\n\tstruct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;\n\tstruct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];\n\tu32 *us1_reg = &mmr_adb->us1_regs[0];": "static void set_us_coefficients(struct vpe_ctx *ctx)\n{\n\tstruct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;\n\tstruct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];\n\tu32 *us1_reg = &mmr_adb->us1_regs[0];\n\tu32 *us2_reg = &mmr_adb->us2_regs[0];\n\tu32 *us3_reg = &mmr_adb->us3_regs[0];\n\tconst unsigned short *cp, *end_cp;\n\n\tcp = &us_coeffs[0].anchor_fid0_c0;\n\n\tif (s_q_data->flags & Q_IS_INTERLACED)\t\t/* interlaced */\n\t\tcp += sizeof(us_coeffs[0]) / sizeof(*cp);\n\n\tend_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);\n\n\twhile (cp < end_cp) {\n\t\twrite_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);\n\t\twrite_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);\n\t\t*us2_reg++ = *us1_reg;\n\t\t*us3_reg++ = *us1_reg++;\n\t}\n\tctx->load_mmrs = true;\n}",
        "static int free_tail_pages_check(struct page *head_page, struct page *page)\n{\n\tint ret = 1;\n\n\t/*": "static int free_tail_pages_check(struct page *head_page, struct page *page)\n{\n\tint ret = 1;\n\n\t/*\n\t * We rely page->lru.next never has bit 0 set, unless the page\n\t * is PageTail(). Let's make sure that's true even for poisoned ->lru.\n\t */\n\tBUILD_BUG_ON((unsigned long)LIST_POISON1 & 1);\n\n\tif (!IS_ENABLED(CONFIG_DEBUG_VM)) {\n\t\tret = 0;\n\t\tgoto out;\n\t}\n\tswitch (page - head_page) {\n\tcase 1:\n\t\t/* the first tail page: ->mapping may be compound_mapcount() */\n\t\tif (unlikely(compound_mapcount(page))) {\n\t\t\tbad_page(page, \"nonzero compound_mapcount\");\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tcase 2:\n\t\t/*\n\t\t * the second tail page: ->mapping is\n\t\t * deferred_list.next -- ignore value.\n\t\t */\n\t\tbreak;\n\tdefault:\n\t\tif (page->mapping != TAIL_MAPPING) {\n\t\t\tbad_page(page, \"corrupted mapping in tail page\");\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\t}\n\tif (unlikely(!PageTail(page))) {\n\t\tbad_page(page, \"PageTail not set\");\n\t\tgoto out;\n\t}\n\tif (unlikely(compound_head(page) != head_page)) {\n\t\tbad_page(page, \"compound_head not consistent\");\n\t\tgoto out;\n\t}\n\tret = 0;\nout:\n\tpage->mapping = NULL;\n\tclear_compound_head(page);\n\treturn ret;\n}",
        "static void br_multicast_sg_del_exclude_ports(struct net_bridge_mdb_entry *sgmp)\n{\n\tstruct net_bridge_port_group __rcu **pp;\n\tstruct net_bridge_port_group *p;\n": "static void br_multicast_sg_del_exclude_ports(struct net_bridge_mdb_entry *sgmp)\n{\n\tstruct net_bridge_port_group __rcu **pp;\n\tstruct net_bridge_port_group *p;\n\n\t/* *,G exclude ports are only added to S,G entries */\n\tif (WARN_ON(br_multicast_is_star_g(&sgmp->addr)))\n\t\treturn;\n\n\t/* we need the STAR_EXCLUDE ports if there are non-STAR_EXCLUDE ports\n\t * we should ignore perm entries since they're managed by user-space\n\t */\n\tfor (pp = &sgmp->ports;\n\t     (p = mlock_dereference(*pp, sgmp->br)) != NULL;\n\t     pp = &p->next)\n\t\tif (!(p->flags & (MDB_PG_FLAGS_STAR_EXCL |\n\t\t\t\t  MDB_PG_FLAGS_PERMANENT)))\n\t\t\treturn;\n\n\t/* currently the host can only have joined the *,G which means\n\t * we treat it as EXCLUDE {}, so for an S,G it's considered a\n\t * STAR_EXCLUDE entry and we can safely leave it\n\t */\n\tsgmp->host_joined = false;\n\n\tfor (pp = &sgmp->ports;\n\t     (p = mlock_dereference(*pp, sgmp->br)) != NULL;) {\n\t\tif (!(p->flags & MDB_PG_FLAGS_PERMANENT))\n\t\t\tbr_multicast_del_pg(sgmp, p, pp);\n\t\telse\n\t\t\tpp = &p->next;\n\t}\n}",
        "static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)\n{\n\tstruct cgx_link_user_info *linfo;\n\tstruct cgx_link_info_msg *msg;\n\tunsigned long pfmap;": "static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)\n{\n\tstruct cgx_link_user_info *linfo;\n\tstruct cgx_link_info_msg *msg;\n\tunsigned long pfmap;\n\tint err, pfid;\n\n\tlinfo = &event->link_uinfo;\n\tpfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);\n\n\tdo {\n\t\tpfid = find_first_bit(&pfmap, 16);\n\t\tclear_bit(pfid, &pfmap);\n\n\t\t/* check if notification is enabled */\n\t\tif (!test_bit(pfid, &rvu->pf_notify_bmap)) {\n\t\t\tdev_info(rvu->dev, \"cgx %d: lmac %d Link status %s\\n\",\n\t\t\t\t event->cgx_id, event->lmac_id,\n\t\t\t\t linfo->link_up ? \"UP\" : \"DOWN\");\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Send mbox message to PF */\n\t\tmsg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);\n\t\tif (!msg)\n\t\t\tcontinue;\n\t\tmsg->link_info = *linfo;\n\t\totx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid);\n\t\terr = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid);\n\t\tif (err)\n\t\t\tdev_warn(rvu->dev, \"notification to pf %d failed\\n\",\n\t\t\t\t pfid);\n\t} while (pfmap);\n}",
        "static struct bpf_map *array_map_alloc(union bpf_attr *attr)\n{\n\tbool percpu = attr->map_type == BPF_MAP_TYPE_PERCPU_ARRAY;\n\tint numa_node = bpf_map_attr_numa_node(attr);\n\tu32 elem_size, index_mask, max_entries;": "static struct bpf_map *array_map_alloc(union bpf_attr *attr)\n{\n\tbool percpu = attr->map_type == BPF_MAP_TYPE_PERCPU_ARRAY;\n\tint numa_node = bpf_map_attr_numa_node(attr);\n\tu32 elem_size, index_mask, max_entries;\n\tbool bypass_spec_v1 = bpf_bypass_spec_v1();\n\tu64 array_size, mask64;\n\tstruct bpf_array *array;\n\n\telem_size = round_up(attr->value_size, 8);\n\n\tmax_entries = attr->max_entries;\n\n\t/* On 32 bit archs roundup_pow_of_two() with max_entries that has\n\t * upper most bit set in u32 space is undefined behavior due to\n\t * resulting 1U << 32, so do it manually here in u64 space.\n\t */\n\tmask64 = fls_long(max_entries - 1);\n\tmask64 = 1ULL << mask64;\n\tmask64 -= 1;\n\n\tindex_mask = mask64;\n\tif (!bypass_spec_v1) {\n\t\t/* round up array size to nearest power of 2,\n\t\t * since cpu will speculate within index_mask limits\n\t\t */\n\t\tmax_entries = index_mask + 1;\n\t\t/* Check for overflows. */\n\t\tif (max_entries < attr->max_entries)\n\t\t\treturn ERR_PTR(-E2BIG);\n\t}\n\n\tarray_size = sizeof(*array);\n\tif (percpu) {\n\t\tarray_size += (u64) max_entries * sizeof(void *);\n\t} else {\n\t\t/* rely on vmalloc() to return page-aligned memory and\n\t\t * ensure array->value is exactly page-aligned\n\t\t */\n\t\tif (attr->map_flags & BPF_F_MMAPABLE) {\n\t\t\tarray_size = PAGE_ALIGN(array_size);\n\t\t\tarray_size += PAGE_ALIGN((u64) max_entries * elem_size);\n\t\t} else {\n\t\t\tarray_size += (u64) max_entries * elem_size;\n\t\t}\n\t}\n\n\t/* allocate all map elements and zero-initialize them */\n\tif (attr->map_flags & BPF_F_MMAPABLE) {\n\t\tvoid *data;\n\n\t\t/* kmalloc'ed memory can't be mmap'ed, use explicit vmalloc */\n\t\tdata = bpf_map_area_mmapable_alloc(array_size, numa_node);\n\t\tif (!data)\n\t\t\treturn ERR_PTR(-ENOMEM);\n\t\tarray = data + PAGE_ALIGN(sizeof(struct bpf_array))\n\t\t\t- offsetof(struct bpf_array, value);\n\t} else {\n\t\tarray = bpf_map_area_alloc(array_size, numa_node);\n\t}\n\tif (!array)\n\t\treturn ERR_PTR(-ENOMEM);\n\tarray->index_mask = index_mask;\n\tarray->map.bypass_spec_v1 = bypass_spec_v1;\n\n\t/* copy mandatory map attributes */\n\tbpf_map_init_from_attr(&array->map, attr);\n\tarray->elem_size = elem_size;\n\n\tif (percpu && bpf_array_alloc_percpu(array)) {\n\t\tbpf_map_area_free(array);\n\t\treturn ERR_PTR(-ENOMEM);\n\t}\n\n\treturn &array->map;\n}",
        "static int scan_chunks_sanity_check(struct device *dev)\n{\n\tint metadata_size, curr_pkg, cpu, ret = -ENOMEM;\n\tstruct ifs_data *ifsd = ifs_get_data(dev);\n\tbool *package_authenticated;": "static int scan_chunks_sanity_check(struct device *dev)\n{\n\tint metadata_size, curr_pkg, cpu, ret = -ENOMEM;\n\tstruct ifs_data *ifsd = ifs_get_data(dev);\n\tbool *package_authenticated;\n\tstruct ifs_work local_work;\n\tchar *test_ptr;\n\n\tpackage_authenticated = kcalloc(topology_max_packages(), sizeof(bool), GFP_KERNEL);\n\tif (!package_authenticated)\n\t\treturn ret;\n\n\tmetadata_size = ifs_header_ptr->metadata_size;\n\n\t/* Spec says that if the Meta Data Size = 0 then it should be treated as 2000 */\n\tif (metadata_size == 0)\n\t\tmetadata_size = 2000;\n\n\t/* Scan chunk start must be 256 byte aligned */\n\tif ((metadata_size + IFS_HEADER_SIZE) % 256) {\n\t\tdev_err(dev, \"Scan pattern offset within the binary is not 256 byte aligned\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\ttest_ptr = (char *)ifs_header_ptr + IFS_HEADER_SIZE + metadata_size;\n\tifsd->loading_error = false;\n\n\tifs_test_image_ptr = (u64)test_ptr;\n\tifsd->loaded_version = ifs_header_ptr->blob_revision;\n\n\t/* copy the scan hash and authenticate per package */\n\tcpus_read_lock();\n\tfor_each_online_cpu(cpu) {\n\t\tcurr_pkg = topology_physical_package_id(cpu);\n\t\tif (package_authenticated[curr_pkg])\n\t\t\tcontinue;\n\t\treinit_completion(&ifs_done);\n\t\tlocal_work.dev = dev;\n\t\tINIT_WORK(&local_work.w, copy_hashes_authenticate_chunks);\n\t\tschedule_work_on(cpu, &local_work.w);\n\t\twait_for_completion(&ifs_done);\n\t\tif (ifsd->loading_error)\n\t\t\tgoto out;\n\t\tpackage_authenticated[curr_pkg] = 1;\n\t}\n\tret = 0;\nout:\n\tcpus_read_unlock();\n\tkfree(package_authenticated);\n\n\treturn ret;\n}",
        "static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)\n{\n\tu32 offset;\n\n\toffset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;": "static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)\n{\n\tu32 offset;\n\n\toffset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;\n\tadsp->dram_offset = offset;\n\toffset >>= DRAM_REMAP_SHIFT;\n\n\tdev_dbg(sdev->dev, \"adsp->pa_dram %pa, offset %#x\\n\", &adsp->pa_dram, offset);\n\n\tsnd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);\n\tsnd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);\n\n\tif (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||\n\t    offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {\n\t\tdev_err(sdev->dev, \"emi remap fail\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}",
        "static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)\n{\n\tint num_groups, vf_headroom = 0;\n\tint is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;\n": "static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)\n{\n\tint num_groups, vf_headroom = 0;\n\tint is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;\n\n\t/* number of queues for statistics is number of eth queues + FCoE */\n\tu8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;\n\n\t/* Total number of FW statistics requests =\n\t * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper\n\t * and fcoe l2 queue) stats + num of queues (which includes another 1\n\t * for fcoe l2 queue if applicable)\n\t */\n\tbp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;\n\n\t/* vf stats appear in the request list, but their data is allocated by\n\t * the VFs themselves. We don't include them in the bp->fw_stats_num as\n\t * it is used to determine where to place the vf stats queries in the\n\t * request struct\n\t */\n\tif (IS_SRIOV(bp))\n\t\tvf_headroom = bnx2x_vf_headroom(bp);\n\n\t/* Request is built from stats_query_header and an array of\n\t * stats_query_cmd_group each of which contains\n\t * STATS_QUERY_CMD_COUNT rules. The real number or requests is\n\t * configured in the stats_query_header.\n\t */\n\tnum_groups =\n\t\t(((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +\n\t\t (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?\n\t\t 1 : 0));\n\n\tDP(BNX2X_MSG_SP, \"stats fw_stats_num %d, vf headroom %d, num_groups %d\\n\",\n\t   bp->fw_stats_num, vf_headroom, num_groups);\n\tbp->fw_stats_req_sz = sizeof(struct stats_query_header) +\n\t\tnum_groups * sizeof(struct stats_query_cmd_group);\n\n\t/* Data for statistics requests + stats_counter\n\t * stats_counter holds per-STORM counters that are incremented\n\t * when STORM has finished with the current request.\n\t * memory for FCoE offloaded statistics are counted anyway,\n\t * even if they will not be sent.\n\t * VF stats are not accounted for here as the data of VF stats is stored\n\t * in memory allocated by the VF, not here.\n\t */\n\tbp->fw_stats_data_sz = sizeof(struct per_port_stats) +\n\t\tsizeof(struct per_pf_stats) +\n\t\tsizeof(struct fcoe_statistics_params) +\n\t\tsizeof(struct per_queue_stats) * num_queue_stats +\n\t\tsizeof(struct stats_counter);\n\n\tbp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,\n\t\t\t\t       bp->fw_stats_data_sz + bp->fw_stats_req_sz);\n\tif (!bp->fw_stats)\n\t\tgoto alloc_mem_err;\n\n\t/* Set shortcuts */\n\tbp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;\n\tbp->fw_stats_req_mapping = bp->fw_stats_mapping;\n\tbp->fw_stats_data = (struct bnx2x_fw_stats_data *)\n\t\t((u8 *)bp->fw_stats + bp->fw_stats_req_sz);\n\tbp->fw_stats_data_mapping = bp->fw_stats_mapping +\n\t\tbp->fw_stats_req_sz;\n\n\tDP(BNX2X_MSG_SP, \"statistics request base address set to %x %x\\n\",\n\t   U64_HI(bp->fw_stats_req_mapping),\n\t   U64_LO(bp->fw_stats_req_mapping));\n\tDP(BNX2X_MSG_SP, \"statistics data base address set to %x %x\\n\",\n\t   U64_HI(bp->fw_stats_data_mapping),\n\t   U64_LO(bp->fw_stats_data_mapping));\n\treturn 0;\n\nalloc_mem_err:\n\tbnx2x_free_fw_stats_mem(bp);\n\tBNX2X_ERR(\"Can't allocate FW stats memory\\n\");\n\treturn -ENOMEM;\n}",
        "static void spkup_write(const u16 *in_buf, int count)\n{\n\tstatic int rep_count;\n\tstatic u16 ch = '\\0', old_ch = '\\0';\n\tstatic u_short char_type, last_type;": "static void spkup_write(const u16 *in_buf, int count)\n{\n\tstatic int rep_count;\n\tstatic u16 ch = '\\0', old_ch = '\\0';\n\tstatic u_short char_type, last_type;\n\tint in_count = count;\n\n\tspk_keydown = 0;\n\twhile (count--) {\n\t\tif (cursor_track == read_all_mode) {\n\t\t\t/* Insert Sentence Index */\n\t\t\tif ((in_buf == sentmarks[bn][currsentence]) &&\n\t\t\t    (currsentence <= numsentences[bn]))\n\t\t\t\tsynth_insert_next_index(currsentence++);\n\t\t}\n\t\tch = *in_buf++;\n\t\tif (ch < 0x100)\n\t\t\tchar_type = spk_chartab[ch];\n\t\telse\n\t\t\tchar_type = ALPHA;\n\t\tif (ch == old_ch && !(char_type & B_NUM)) {\n\t\t\tif (++rep_count > 2)\n\t\t\t\tcontinue;\n\t\t} else {\n\t\t\tif ((last_type & CH_RPT) && rep_count > 2) {\n\t\t\t\tsynth_printf(\" \");\n\t\t\t\tsynth_printf(spk_msg_get(MSG_REPEAT_DESC),\n\t\t\t\t\t     ++rep_count);\n\t\t\t\tsynth_printf(\" \");\n\t\t\t}\n\t\t\trep_count = 0;\n\t\t}\n\t\tif (ch == spk_lastkey) {\n\t\t\trep_count = 0;\n\t\t\tif (spk_key_echo == 1 && ch >= MINECHOCHAR)\n\t\t\t\tspeak_char(ch);\n\t\t} else if (char_type & B_ALPHA) {\n\t\t\tif ((synth_flags & SF_DEC) && (last_type & PUNC))\n\t\t\t\tsynth_buffer_add(SPACE);\n\t\t\tsynth_putwc_s(ch);\n\t\t} else if (char_type & B_NUM) {\n\t\t\trep_count = 0;\n\t\t\tsynth_putwc_s(ch);\n\t\t} else if (char_type & spk_punc_mask) {\n\t\t\tspeak_char(ch);\n\t\t\tchar_type &= ~PUNC;\t/* for dec nospell processing */\n\t\t} else if (char_type & SYNTH_OK) {\n\t\t\t/* these are usually puncts like . and , which synth\n\t\t\t * needs for expression.\n\t\t\t * suppress multiple to get rid of long pauses and\n\t\t\t * clear repeat count\n\t\t\t * so if someone has\n\t\t\t * repeats on you don't get nothing repeated count\n\t\t\t */\n\t\t\tif (ch != old_ch)\n\t\t\t\tsynth_putwc_s(ch);\n\t\t\telse\n\t\t\t\trep_count = 0;\n\t\t} else {\n/* send space and record position, if next is num overwrite space */\n\t\t\tif (old_ch != ch)\n\t\t\t\tsynth_buffer_add(SPACE);\n\t\t\telse\n\t\t\t\trep_count = 0;\n\t\t}\n\t\told_ch = ch;\n\t\tlast_type = char_type;\n\t}\n\tspk_lastkey = 0;\n\tif (in_count > 2 && rep_count > 2) {\n\t\tif (last_type & CH_RPT) {\n\t\t\tsynth_printf(\" \");\n\t\t\tsynth_printf(spk_msg_get(MSG_REPEAT_DESC2),\n\t\t\t\t     ++rep_count);\n\t\t\tsynth_printf(\" \");\n\t\t}\n\t\trep_count = 0;\n\t}\n}",
        "static bool rate_limit_report(unsigned long frame1, unsigned long frame2)\n{\n\tstruct report_time *use_entry = &report_times[0];\n\tunsigned long invalid_before;\n\tint i;": "static bool rate_limit_report(unsigned long frame1, unsigned long frame2)\n{\n\tstruct report_time *use_entry = &report_times[0];\n\tunsigned long invalid_before;\n\tint i;\n\n\tBUILD_BUG_ON(CONFIG_KCSAN_REPORT_ONCE_IN_MS != 0 && REPORT_TIMES_SIZE == 0);\n\n\tif (CONFIG_KCSAN_REPORT_ONCE_IN_MS == 0)\n\t\treturn false;\n\n\tinvalid_before = jiffies - msecs_to_jiffies(CONFIG_KCSAN_REPORT_ONCE_IN_MS);\n\n\t/* Check if a matching race report exists. */\n\tfor (i = 0; i < REPORT_TIMES_SIZE; ++i) {\n\t\tstruct report_time *rt = &report_times[i];\n\n\t\t/*\n\t\t * Must always select an entry for use to store info as we\n\t\t * cannot resize report_times; at the end of the scan, use_entry\n\t\t * will be the oldest entry, which ideally also happened before\n\t\t * KCSAN_REPORT_ONCE_IN_MS ago.\n\t\t */\n\t\tif (time_before(rt->time, use_entry->time))\n\t\t\tuse_entry = rt;\n\n\t\t/*\n\t\t * Initially, no need to check any further as this entry as well\n\t\t * as following entries have never been used.\n\t\t */\n\t\tif (rt->time == 0)\n\t\t\tbreak;\n\n\t\t/* Check if entry expired. */\n\t\tif (time_before(rt->time, invalid_before))\n\t\t\tcontinue; /* before KCSAN_REPORT_ONCE_IN_MS ago */\n\n\t\t/* Reported recently, check if race matches. */\n\t\tif ((rt->frame1 == frame1 && rt->frame2 == frame2) ||\n\t\t    (rt->frame1 == frame2 && rt->frame2 == frame1))\n\t\t\treturn true;\n\t}\n\n\tuse_entry->time = jiffies;\n\tuse_entry->frame1 = frame1;\n\tuse_entry->frame2 = frame2;\n\treturn false;\n}",
        "static int rkisp1_config_isp(struct rkisp1_device *rkisp1)\n{\n\tu32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;\n\tconst struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt;\n\tstruct rkisp1_sensor_async *sensor;": "static int rkisp1_config_isp(struct rkisp1_device *rkisp1)\n{\n\tu32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;\n\tconst struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt;\n\tstruct rkisp1_sensor_async *sensor;\n\tstruct v4l2_mbus_framefmt *sink_frm;\n\tstruct v4l2_rect *sink_crop;\n\n\tsensor = rkisp1->active_sensor;\n\tsink_fmt = rkisp1->isp.sink_fmt;\n\tsrc_fmt = rkisp1->isp.src_fmt;\n\tsink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,\n\t\t\t\t\t  RKISP1_ISP_PAD_SINK_VIDEO,\n\t\t\t\t\t  V4L2_SUBDEV_FORMAT_ACTIVE);\n\tsink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,\n\t\t\t\t\t    RKISP1_ISP_PAD_SINK_VIDEO,\n\t\t\t\t\t    V4L2_SUBDEV_FORMAT_ACTIVE);\n\n\tif (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {\n\t\tacq_mult = 1;\n\t\tif (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {\n\t\t\tif (sensor->mbus_type == V4L2_MBUS_BT656)\n\t\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;\n\t\t\telse\n\t\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT;\n\t\t} else {\n\t\t\trkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc),\n\t\t\t\t     RKISP1_CIF_ISP_DEMOSAIC);\n\n\t\t\tif (sensor->mbus_type == V4L2_MBUS_BT656)\n\t\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;\n\t\t\telse\n\t\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;\n\t\t}\n\t} else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) {\n\t\tacq_mult = 2;\n\t\tif (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {\n\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;\n\t\t} else {\n\t\t\tif (sensor->mbus_type == V4L2_MBUS_BT656)\n\t\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656;\n\t\t\telse\n\t\t\t\tisp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;\n\t\t}\n\n\t\tirq_mask |= RKISP1_CIF_ISP_DATA_LOSS;\n\t}\n\n\t/* Set up input acquisition properties */\n\tif (sensor->mbus_type == V4L2_MBUS_BT656 ||\n\t    sensor->mbus_type == V4L2_MBUS_PARALLEL) {\n\t\tif (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)\n\t\t\tsignal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE;\n\t}\n\n\tif (sensor->mbus_type == V4L2_MBUS_PARALLEL) {\n\t\tif (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)\n\t\t\tsignal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW;\n\n\t\tif (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)\n\t\t\tsignal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW;\n\t}\n\n\trkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL);\n\trkisp1_write(rkisp1, signal | sink_fmt->yuv_seq |\n\t\t     RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |\n\t\t     RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL,\n\t\t     RKISP1_CIF_ISP_ACQ_PROP);\n\trkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES);\n\n\t/* Acquisition Size */\n\trkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS);\n\trkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS);\n\trkisp1_write(rkisp1,\n\t\t     acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE);\n\trkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE);\n\n\t/* ISP Out Area */\n\trkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS);\n\trkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS);\n\trkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE);\n\trkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE);\n\n\tirq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START |\n\t\t    RKISP1_CIF_ISP_PIC_SIZE_ERROR;\n\trkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC);\n\n\tif (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {\n\t\trkisp1_params_disable(&rkisp1->params);\n\t} else {\n\t\tstruct v4l2_mbus_framefmt *src_frm;\n\n\t\tsrc_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,\n\t\t\t\t\t\t RKISP1_ISP_PAD_SINK_VIDEO,\n\t\t\t\t\t\t V4L2_SUBDEV_FORMAT_ACTIVE);\n\t\trkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat,\n\t\t\t\t\tsrc_frm->quantization);\n\t}\n\n\treturn 0;\n}",
        "static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tint retval, i;\n\tu8 val;": "static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tint retval, i;\n\tu8 val;\n\n\tretval = ms_set_rw_reg_addr(chip, PRO_STATUS_REG, 6, SYSTEM_PARAM, 1);\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\tfor (i = 0; i < MS_MAX_RETRY_COUNT; i++) {\n\t\tretval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,\n\t\t\t\t\t 6, NO_WAIT_INT);\n\t\tif (retval == STATUS_SUCCESS)\n\t\t\tbreak;\n\t}\n\tif (i == MS_MAX_RETRY_COUNT)\n\t\treturn STATUS_FAIL;\n\n\tretval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val);\n\tif (retval)\n\t\treturn retval;\n\n\tdev_dbg(rtsx_dev(chip), \"Type register: 0x%x\\n\", val);\n\tif (val != 0x01) {\n\t\tif (val != 0x02)\n\t\t\tms_card->check_ms_flow = 1;\n\n\t\treturn STATUS_FAIL;\n\t}\n\n\tretval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val);\n\tif (retval)\n\t\treturn retval;\n\n\tdev_dbg(rtsx_dev(chip), \"Category register: 0x%x\\n\", val);\n\tif (val != 0) {\n\t\tms_card->check_ms_flow = 1;\n\t\treturn STATUS_FAIL;\n\t}\n\n\tretval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val);\n\tif (retval)\n\t\treturn retval;\n\n\tdev_dbg(rtsx_dev(chip), \"Class register: 0x%x\\n\", val);\n\tif (val == 0) {\n\t\tretval = rtsx_read_register(chip, PPBUF_BASE2, &val);\n\t\tif (retval)\n\t\t\treturn retval;\n\n\t\tif (val & WRT_PRTCT)\n\t\t\tchip->card_wp |= MS_CARD;\n\t\telse\n\t\t\tchip->card_wp &= ~MS_CARD;\n\n\t} else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {\n\t\tchip->card_wp |= MS_CARD;\n\t} else {\n\t\tms_card->check_ms_flow = 1;\n\t\treturn STATUS_FAIL;\n\t}\n\n\tms_card->ms_type |= TYPE_MSPRO;\n\n\tretval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val);\n\tif (retval)\n\t\treturn retval;\n\n\tdev_dbg(rtsx_dev(chip), \"IF Mode register: 0x%x\\n\", val);\n\tif (val == 0) {\n\t\tms_card->ms_type &= 0x0F;\n\t} else if (val == 7) {\n\t\tif (switch_8bit_bus)\n\t\t\tms_card->ms_type |= MS_HG;\n\t\telse\n\t\t\tms_card->ms_type &= 0x0F;\n\n\t} else {\n\t\treturn STATUS_FAIL;\n\t}\n\n\treturn STATUS_SUCCESS;\n}",
        "static void lan78xx_link_status_change(struct net_device *net)\n{\n\tstruct phy_device *phydev = net->phydev;\n\tint temp;\n": "static void lan78xx_link_status_change(struct net_device *net)\n{\n\tstruct phy_device *phydev = net->phydev;\n\tint temp;\n\n\t/* At forced 100 F/H mode, chip may fail to set mode correctly\n\t * when cable is switched between long(~50+m) and short one.\n\t * As workaround, set to 10 before setting to 100\n\t * at forced 100 F/H mode.\n\t */\n\tif (!phydev->autoneg && (phydev->speed == 100)) {\n\t\t/* disable phy interrupt */\n\t\ttemp = phy_read(phydev, LAN88XX_INT_MASK);\n\t\ttemp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;\n\t\tphy_write(phydev, LAN88XX_INT_MASK, temp);\n\n\t\ttemp = phy_read(phydev, MII_BMCR);\n\t\ttemp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);\n\t\tphy_write(phydev, MII_BMCR, temp); /* set to 10 first */\n\t\ttemp |= BMCR_SPEED100;\n\t\tphy_write(phydev, MII_BMCR, temp); /* set to 100 later */\n\n\t\t/* clear pending interrupt generated while workaround */\n\t\ttemp = phy_read(phydev, LAN88XX_INT_STS);\n\n\t\t/* enable phy interrupt back */\n\t\ttemp = phy_read(phydev, LAN88XX_INT_MASK);\n\t\ttemp |= LAN88XX_INT_MASK_MDINTPIN_EN_;\n\t\tphy_write(phydev, LAN88XX_INT_MASK, temp);\n\t}\n}",
        "static void gc_worker(struct work_struct *work)\n{\n\tunsigned int i, hashsz, nf_conntrack_max95 = 0;\n\tu32 end_time, start_time = nfct_time_stamp;\n\tstruct conntrack_gc_work *gc_work;": "static void gc_worker(struct work_struct *work)\n{\n\tunsigned int i, hashsz, nf_conntrack_max95 = 0;\n\tu32 end_time, start_time = nfct_time_stamp;\n\tstruct conntrack_gc_work *gc_work;\n\tunsigned int expired_count = 0;\n\tunsigned long next_run;\n\ts32 delta_time;\n\n\tgc_work = container_of(work, struct conntrack_gc_work, dwork.work);\n\n\ti = gc_work->next_bucket;\n\tif (gc_work->early_drop)\n\t\tnf_conntrack_max95 = nf_conntrack_max / 100u * 95u;\n\n\tif (i == 0) {\n\t\tgc_work->avg_timeout = GC_SCAN_INTERVAL_INIT;\n\t\tgc_work->start_time = start_time;\n\t}\n\n\tnext_run = gc_work->avg_timeout;\n\n\tend_time = start_time + GC_SCAN_MAX_DURATION;\n\n\tdo {\n\t\tstruct nf_conntrack_tuple_hash *h;\n\t\tstruct hlist_nulls_head *ct_hash;\n\t\tstruct hlist_nulls_node *n;\n\t\tstruct nf_conn *tmp;\n\n\t\trcu_read_lock();\n\n\t\tnf_conntrack_get_ht(&ct_hash, &hashsz);\n\t\tif (i >= hashsz) {\n\t\t\trcu_read_unlock();\n\t\t\tbreak;\n\t\t}\n\n\t\thlist_nulls_for_each_entry_rcu(h, n, &ct_hash[i], hnnode) {\n\t\t\tstruct nf_conntrack_net *cnet;\n\t\t\tunsigned long expires;\n\t\t\tstruct net *net;\n\n\t\t\ttmp = nf_ct_tuplehash_to_ctrack(h);\n\n\t\t\tif (test_bit(IPS_OFFLOAD_BIT, &tmp->status)) {\n\t\t\t\tnf_ct_offload_timeout(tmp);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (expired_count > GC_SCAN_EXPIRED_MAX) {\n\t\t\t\trcu_read_unlock();\n\n\t\t\t\tgc_work->next_bucket = i;\n\t\t\t\tgc_work->avg_timeout = next_run;\n\n\t\t\t\tdelta_time = nfct_time_stamp - gc_work->start_time;\n\n\t\t\t\t/* re-sched immediately if total cycle time is exceeded */\n\t\t\t\tnext_run = delta_time < (s32)GC_SCAN_INTERVAL_MAX;\n\t\t\t\tgoto early_exit;\n\t\t\t}\n\n\t\t\tif (nf_ct_is_expired(tmp)) {\n\t\t\t\tnf_ct_gc_expired(tmp);\n\t\t\t\texpired_count++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\texpires = clamp(nf_ct_expires(tmp), GC_SCAN_INTERVAL_MIN, GC_SCAN_INTERVAL_CLAMP);\n\t\t\tnext_run += expires;\n\t\t\tnext_run /= 2u;\n\n\t\t\tif (nf_conntrack_max95 == 0 || gc_worker_skip_ct(tmp))\n\t\t\t\tcontinue;\n\n\t\t\tnet = nf_ct_net(tmp);\n\t\t\tcnet = nf_ct_pernet(net);\n\t\t\tif (atomic_read(&cnet->count) < nf_conntrack_max95)\n\t\t\t\tcontinue;\n\n\t\t\t/* need to take reference to avoid possible races */\n\t\t\tif (!refcount_inc_not_zero(&tmp->ct_general.use))\n\t\t\t\tcontinue;\n\n\t\t\tif (gc_worker_skip_ct(tmp)) {\n\t\t\t\tnf_ct_put(tmp);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (gc_worker_can_early_drop(tmp)) {\n\t\t\t\tnf_ct_kill(tmp);\n\t\t\t\texpired_count++;\n\t\t\t}\n\n\t\t\tnf_ct_put(tmp);\n\t\t}\n\n\t\t/* could check get_nulls_value() here and restart if ct\n\t\t * was moved to another chain.  But given gc is best-effort\n\t\t * we will just continue with next hash slot.\n\t\t */\n\t\trcu_read_unlock();\n\t\tcond_resched();\n\t\ti++;\n\n\t\tdelta_time = nfct_time_stamp - end_time;\n\t\tif (delta_time > 0 && i < hashsz) {\n\t\t\tgc_work->avg_timeout = next_run;\n\t\t\tgc_work->next_bucket = i;\n\t\t\tnext_run = 0;\n\t\t\tgoto early_exit;\n\t\t}\n\t} while (i < hashsz);\n\n\tgc_work->next_bucket = 0;\n\n\tnext_run = clamp(next_run, GC_SCAN_INTERVAL_MIN, GC_SCAN_INTERVAL_MAX);\n\n\tdelta_time = max_t(s32, nfct_time_stamp - gc_work->start_time, 1);\n\tif (next_run > (unsigned long)delta_time)\n\t\tnext_run -= delta_time;\n\telse\n\t\tnext_run = 1;\n\nearly_exit:\n\tif (gc_work->exiting)\n\t\treturn;\n\n\tif (next_run)\n\t\tgc_work->early_drop = false;\n\n\tqueue_delayed_work(system_power_efficient_wq, &gc_work->dwork, next_run);\n}",
        "static int io_refill_buffer_cache(struct io_ring_ctx *ctx)\n{\n\tstruct io_buffer *buf;\n\tstruct page *page;\n\tint bufs_in_page;": "static int io_refill_buffer_cache(struct io_ring_ctx *ctx)\n{\n\tstruct io_buffer *buf;\n\tstruct page *page;\n\tint bufs_in_page;\n\n\t/*\n\t * Completions that don't happen inline (eg not under uring_lock) will\n\t * add to ->io_buffers_comp. If we don't have any free buffers, check\n\t * the completion list and splice those entries first.\n\t */\n\tif (!list_empty_careful(&ctx->io_buffers_comp)) {\n\t\tspin_lock(&ctx->completion_lock);\n\t\tif (!list_empty(&ctx->io_buffers_comp)) {\n\t\t\tlist_splice_init(&ctx->io_buffers_comp,\n\t\t\t\t\t\t&ctx->io_buffers_cache);\n\t\t\tspin_unlock(&ctx->completion_lock);\n\t\t\treturn 0;\n\t\t}\n\t\tspin_unlock(&ctx->completion_lock);\n\t}\n\n\t/*\n\t * No free buffers and no completion entries either. Allocate a new\n\t * page worth of buffer entries and add those to our freelist.\n\t */\n\tpage = alloc_page(GFP_KERNEL_ACCOUNT);\n\tif (!page)\n\t\treturn -ENOMEM;\n\n\tlist_add(&page->lru, &ctx->io_buffers_pages);\n\n\tbuf = page_address(page);\n\tbufs_in_page = PAGE_SIZE / sizeof(*buf);\n\twhile (bufs_in_page) {\n\t\tlist_add_tail(&buf->list, &ctx->io_buffers_cache);\n\t\tbuf++;\n\t\tbufs_in_page--;\n\t}\n\n\treturn 0;\n}",
        "static int alloc_in_between_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tstruct region r1, r2;\n\tvoid *allocated_ptr = NULL;": "static int alloc_in_between_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tstruct region r1, r2;\n\tvoid *allocated_ptr = NULL;\n\n\tphys_addr_t gap_size = SMP_CACHE_BYTES;\n\tphys_addr_t r3_size = SZ_64;\n\t/*\n\t * Calculate regions size so there's just enough space for the new entry\n\t */\n\tphys_addr_t rgn_size = (MEM_SIZE - (2 * gap_size + r3_size)) / 2;\n\tphys_addr_t total_size;\n\n\tsetup_memblock();\n\n\tr1.size = rgn_size;\n\tr1.base = memblock_end_of_DRAM() - (gap_size + rgn_size);\n\n\tr2.size = rgn_size;\n\tr2.base = memblock_start_of_DRAM() + gap_size;\n\n\ttotal_size = r1.size + r2.size + r3_size;\n\n\tmemblock_reserve(r1.base, r1.size);\n\tmemblock_reserve(r2.base, r2.size);\n\n\tallocated_ptr = memblock_alloc(r3_size, SMP_CACHE_BYTES);\n\n\tassert(allocated_ptr);\n\tassert(rgn->size == total_size);\n\tassert(rgn->base == r1.base - r2.size - r3_size);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static void do_profile_hits(int type, void *__pc, unsigned int nr_hits)\n{\n\tunsigned long primary, secondary, flags, pc = (unsigned long)__pc;\n\tint i, j, cpu;\n\tstruct profile_hit *hits;": "static void do_profile_hits(int type, void *__pc, unsigned int nr_hits)\n{\n\tunsigned long primary, secondary, flags, pc = (unsigned long)__pc;\n\tint i, j, cpu;\n\tstruct profile_hit *hits;\n\n\tpc = min((pc - (unsigned long)_stext) >> prof_shift, prof_len - 1);\n\ti = primary = (pc & (NR_PROFILE_GRP - 1)) << PROFILE_GRPSHIFT;\n\tsecondary = (~(pc << 1) & (NR_PROFILE_GRP - 1)) << PROFILE_GRPSHIFT;\n\tcpu = get_cpu();\n\thits = per_cpu(cpu_profile_hits, cpu)[per_cpu(cpu_profile_flip, cpu)];\n\tif (!hits) {\n\t\tput_cpu();\n\t\treturn;\n\t}\n\t/*\n\t * We buffer the global profiler buffer into a per-CPU\n\t * queue and thus reduce the number of global (and possibly\n\t * NUMA-alien) accesses. The write-queue is self-coalescing:\n\t */\n\tlocal_irq_save(flags);\n\tdo {\n\t\tfor (j = 0; j < PROFILE_GRPSZ; ++j) {\n\t\t\tif (hits[i + j].pc == pc) {\n\t\t\t\thits[i + j].hits += nr_hits;\n\t\t\t\tgoto out;\n\t\t\t} else if (!hits[i + j].hits) {\n\t\t\t\thits[i + j].pc = pc;\n\t\t\t\thits[i + j].hits = nr_hits;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t\ti = (i + secondary) & (NR_PROFILE_HIT - 1);\n\t} while (i != primary);\n\n\t/*\n\t * Add the current hit(s) and flush the write-queue out\n\t * to the global buffer:\n\t */\n\tatomic_add(nr_hits, &prof_buffer[pc]);\n\tfor (i = 0; i < NR_PROFILE_HIT; ++i) {\n\t\tatomic_add(hits[i].hits, &prof_buffer[hits[i].pc]);\n\t\thits[i].pc = hits[i].hits = 0;\n\t}\nout:\n\tlocal_irq_restore(flags);\n\tput_cpu();\n}",
        "static long linereq_get_values(struct linereq *lr, void __user *ip)\n{\n\tstruct gpio_v2_line_values lv;\n\tDECLARE_BITMAP(vals, GPIO_V2_LINES_MAX);\n\tstruct gpio_desc **descs;": "static long linereq_get_values(struct linereq *lr, void __user *ip)\n{\n\tstruct gpio_v2_line_values lv;\n\tDECLARE_BITMAP(vals, GPIO_V2_LINES_MAX);\n\tstruct gpio_desc **descs;\n\tunsigned int i, didx, num_get;\n\tbool val;\n\tint ret;\n\n\t/* NOTE: It's ok to read values of output lines. */\n\tif (copy_from_user(&lv, ip, sizeof(lv)))\n\t\treturn -EFAULT;\n\n\tfor (num_get = 0, i = 0; i < lr->num_lines; i++) {\n\t\tif (lv.mask & BIT_ULL(i)) {\n\t\t\tnum_get++;\n\t\t\tdescs = &lr->lines[i].desc;\n\t\t}\n\t}\n\n\tif (num_get == 0)\n\t\treturn -EINVAL;\n\n\tif (num_get != 1) {\n\t\tdescs = kmalloc_array(num_get, sizeof(*descs), GFP_KERNEL);\n\t\tif (!descs)\n\t\t\treturn -ENOMEM;\n\t\tfor (didx = 0, i = 0; i < lr->num_lines; i++) {\n\t\t\tif (lv.mask & BIT_ULL(i)) {\n\t\t\t\tdescs[didx] = lr->lines[i].desc;\n\t\t\t\tdidx++;\n\t\t\t}\n\t\t}\n\t}\n\tret = gpiod_get_array_value_complex(false, true, num_get,\n\t\t\t\t\t    descs, NULL, vals);\n\n\tif (num_get != 1)\n\t\tkfree(descs);\n\tif (ret)\n\t\treturn ret;\n\n\tlv.bits = 0;\n\tfor (didx = 0, i = 0; i < lr->num_lines; i++) {\n\t\tif (lv.mask & BIT_ULL(i)) {\n\t\t\tif (lr->lines[i].sw_debounced)\n\t\t\t\tval = debounced_value(&lr->lines[i]);\n\t\t\telse\n\t\t\t\tval = test_bit(didx, vals);\n\t\t\tif (val)\n\t\t\t\tlv.bits |= BIT_ULL(i);\n\t\t\tdidx++;\n\t\t}\n\t}\n\n\tif (copy_to_user(ip, &lv, sizeof(lv)))\n\t\treturn -EFAULT;\n\n\treturn 0;\n}",
        "static void ww_test_edeadlk_acquire_wrong(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_acquire_wrong(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\to2.ctx = &t2;\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\tif (!ret)\n\t\tWWU(&o2);\n\n\tWWU(&o);\n\n\tret = WWL(&o3, &t);\n}",
        "static int bond_check_params(struct bond_params *params)\n{\n\tint arp_validate_value, fail_over_mac_value, primary_reselect_value, i;\n\tstruct bond_opt_value newval;\n\tconst struct bond_opt_value *valptr;": "static int bond_check_params(struct bond_params *params)\n{\n\tint arp_validate_value, fail_over_mac_value, primary_reselect_value, i;\n\tstruct bond_opt_value newval;\n\tconst struct bond_opt_value *valptr;\n\tint arp_all_targets_value = 0;\n\tu16 ad_actor_sys_prio = 0;\n\tu16 ad_user_port_key = 0;\n\t__be32 arp_target[BOND_MAX_ARP_TARGETS] = { 0 };\n\tint arp_ip_count;\n\tint bond_mode\t= BOND_MODE_ROUNDROBIN;\n\tint xmit_hashtype = BOND_XMIT_POLICY_LAYER2;\n\tint lacp_fast = 0;\n\tint tlb_dynamic_lb;\n\n\t/* Convert string parameters. */\n\tif (mode) {\n\t\tbond_opt_initstr(&newval, mode);\n\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_MODE), &newval);\n\t\tif (!valptr) {\n\t\t\tpr_err(\"Error: Invalid bonding mode \\\"%s\\\"\\n\", mode);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbond_mode = valptr->value;\n\t}\n\n\tif (xmit_hash_policy) {\n\t\tif (bond_mode == BOND_MODE_ROUNDROBIN ||\n\t\t    bond_mode == BOND_MODE_ACTIVEBACKUP ||\n\t\t    bond_mode == BOND_MODE_BROADCAST) {\n\t\t\tpr_info(\"xmit_hash_policy param is irrelevant in mode %s\\n\",\n\t\t\t\tbond_mode_name(bond_mode));\n\t\t} else {\n\t\t\tbond_opt_initstr(&newval, xmit_hash_policy);\n\t\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_XMIT_HASH),\n\t\t\t\t\t\t&newval);\n\t\t\tif (!valptr) {\n\t\t\t\tpr_err(\"Error: Invalid xmit_hash_policy \\\"%s\\\"\\n\",\n\t\t\t\t       xmit_hash_policy);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\txmit_hashtype = valptr->value;\n\t\t}\n\t}\n\n\tif (lacp_rate) {\n\t\tif (bond_mode != BOND_MODE_8023AD) {\n\t\t\tpr_info(\"lacp_rate param is irrelevant in mode %s\\n\",\n\t\t\t\tbond_mode_name(bond_mode));\n\t\t} else {\n\t\t\tbond_opt_initstr(&newval, lacp_rate);\n\t\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_LACP_RATE),\n\t\t\t\t\t\t&newval);\n\t\t\tif (!valptr) {\n\t\t\t\tpr_err(\"Error: Invalid lacp rate \\\"%s\\\"\\n\",\n\t\t\t\t       lacp_rate);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tlacp_fast = valptr->value;\n\t\t}\n\t}\n\n\tif (ad_select) {\n\t\tbond_opt_initstr(&newval, ad_select);\n\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_AD_SELECT),\n\t\t\t\t\t&newval);\n\t\tif (!valptr) {\n\t\t\tpr_err(\"Error: Invalid ad_select \\\"%s\\\"\\n\", ad_select);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tparams->ad_select = valptr->value;\n\t\tif (bond_mode != BOND_MODE_8023AD)\n\t\t\tpr_warn(\"ad_select param only affects 802.3ad mode\\n\");\n\t} else {\n\t\tparams->ad_select = BOND_AD_STABLE;\n\t}\n\n\tif (max_bonds < 0) {\n\t\tpr_warn(\"Warning: max_bonds (%d) not in range %d-%d, so it was reset to BOND_DEFAULT_MAX_BONDS (%d)\\n\",\n\t\t\tmax_bonds, 0, INT_MAX, BOND_DEFAULT_MAX_BONDS);\n\t\tmax_bonds = BOND_DEFAULT_MAX_BONDS;\n\t}\n\n\tif (miimon < 0) {\n\t\tpr_warn(\"Warning: miimon module parameter (%d), not in range 0-%d, so it was reset to 0\\n\",\n\t\t\tmiimon, INT_MAX);\n\t\tmiimon = 0;\n\t}\n\n\tif (updelay < 0) {\n\t\tpr_warn(\"Warning: updelay module parameter (%d), not in range 0-%d, so it was reset to 0\\n\",\n\t\t\tupdelay, INT_MAX);\n\t\tupdelay = 0;\n\t}\n\n\tif (downdelay < 0) {\n\t\tpr_warn(\"Warning: downdelay module parameter (%d), not in range 0-%d, so it was reset to 0\\n\",\n\t\t\tdowndelay, INT_MAX);\n\t\tdowndelay = 0;\n\t}\n\n\tif ((use_carrier != 0) && (use_carrier != 1)) {\n\t\tpr_warn(\"Warning: use_carrier module parameter (%d), not of valid value (0/1), so it was set to 1\\n\",\n\t\t\tuse_carrier);\n\t\tuse_carrier = 1;\n\t}\n\n\tif (num_peer_notif < 0 || num_peer_notif > 255) {\n\t\tpr_warn(\"Warning: num_grat_arp/num_unsol_na (%d) not in range 0-255 so it was reset to 1\\n\",\n\t\t\tnum_peer_notif);\n\t\tnum_peer_notif = 1;\n\t}\n\n\t/* reset values for 802.3ad/TLB/ALB */\n\tif (!bond_mode_uses_arp(bond_mode)) {\n\t\tif (!miimon) {\n\t\t\tpr_warn(\"Warning: miimon must be specified, otherwise bonding will not detect link failure, speed and duplex which are essential for 802.3ad operation\\n\");\n\t\t\tpr_warn(\"Forcing miimon to 100msec\\n\");\n\t\t\tmiimon = BOND_DEFAULT_MIIMON;\n\t\t}\n\t}\n\n\tif (tx_queues < 1 || tx_queues > 255) {\n\t\tpr_warn(\"Warning: tx_queues (%d) should be between 1 and 255, resetting to %d\\n\",\n\t\t\ttx_queues, BOND_DEFAULT_TX_QUEUES);\n\t\ttx_queues = BOND_DEFAULT_TX_QUEUES;\n\t}\n\n\tif ((all_slaves_active != 0) && (all_slaves_active != 1)) {\n\t\tpr_warn(\"Warning: all_slaves_active module parameter (%d), not of valid value (0/1), so it was set to 0\\n\",\n\t\t\tall_slaves_active);\n\t\tall_slaves_active = 0;\n\t}\n\n\tif (resend_igmp < 0 || resend_igmp > 255) {\n\t\tpr_warn(\"Warning: resend_igmp (%d) should be between 0 and 255, resetting to %d\\n\",\n\t\t\tresend_igmp, BOND_DEFAULT_RESEND_IGMP);\n\t\tresend_igmp = BOND_DEFAULT_RESEND_IGMP;\n\t}\n\n\tbond_opt_initval(&newval, packets_per_slave);\n\tif (!bond_opt_parse(bond_opt_get(BOND_OPT_PACKETS_PER_SLAVE), &newval)) {\n\t\tpr_warn(\"Warning: packets_per_slave (%d) should be between 0 and %u resetting to 1\\n\",\n\t\t\tpackets_per_slave, USHRT_MAX);\n\t\tpackets_per_slave = 1;\n\t}\n\n\tif (bond_mode == BOND_MODE_ALB) {\n\t\tpr_notice(\"In ALB mode you might experience client disconnections upon reconnection of a link if the bonding module updelay parameter (%d msec) is incompatible with the forwarding delay time of the switch\\n\",\n\t\t\t  updelay);\n\t}\n\n\tif (!miimon) {\n\t\tif (updelay || downdelay) {\n\t\t\t/* just warn the user the up/down delay will have\n\t\t\t * no effect since miimon is zero...\n\t\t\t */\n\t\t\tpr_warn(\"Warning: miimon module parameter not set and updelay (%d) or downdelay (%d) module parameter is set; updelay and downdelay have no effect unless miimon is set\\n\",\n\t\t\t\tupdelay, downdelay);\n\t\t}\n\t} else {\n\t\t/* don't allow arp monitoring */\n\t\tif (arp_interval) {\n\t\t\tpr_warn(\"Warning: miimon (%d) and arp_interval (%d) can't be used simultaneously, disabling ARP monitoring\\n\",\n\t\t\t\tmiimon, arp_interval);\n\t\t\tarp_interval = 0;\n\t\t}\n\n\t\tif ((updelay % miimon) != 0) {\n\t\t\tpr_warn(\"Warning: updelay (%d) is not a multiple of miimon (%d), updelay rounded to %d ms\\n\",\n\t\t\t\tupdelay, miimon, (updelay / miimon) * miimon);\n\t\t}\n\n\t\tupdelay /= miimon;\n\n\t\tif ((downdelay % miimon) != 0) {\n\t\t\tpr_warn(\"Warning: downdelay (%d) is not a multiple of miimon (%d), downdelay rounded to %d ms\\n\",\n\t\t\t\tdowndelay, miimon,\n\t\t\t\t(downdelay / miimon) * miimon);\n\t\t}\n\n\t\tdowndelay /= miimon;\n\t}\n\n\tif (arp_interval < 0) {\n\t\tpr_warn(\"Warning: arp_interval module parameter (%d), not in range 0-%d, so it was reset to 0\\n\",\n\t\t\tarp_interval, INT_MAX);\n\t\tarp_interval = 0;\n\t}\n\n\tfor (arp_ip_count = 0, i = 0;\n\t     (arp_ip_count < BOND_MAX_ARP_TARGETS) && arp_ip_target[i]; i++) {\n\t\t__be32 ip;\n\n\t\t/* not a complete check, but good enough to catch mistakes */\n\t\tif (!in4_pton(arp_ip_target[i], -1, (u8 *)&ip, -1, NULL) ||\n\t\t    !bond_is_ip_target_ok(ip)) {\n\t\t\tpr_warn(\"Warning: bad arp_ip_target module parameter (%s), ARP monitoring will not be performed\\n\",\n\t\t\t\tarp_ip_target[i]);\n\t\t\tarp_interval = 0;\n\t\t} else {\n\t\t\tif (bond_get_targets_ip(arp_target, ip) == -1)\n\t\t\t\tarp_target[arp_ip_count++] = ip;\n\t\t\telse\n\t\t\t\tpr_warn(\"Warning: duplicate address %pI4 in arp_ip_target, skipping\\n\",\n\t\t\t\t\t&ip);\n\t\t}\n\t}\n\n\tif (arp_interval && !arp_ip_count) {\n\t\t/* don't allow arping if no arp_ip_target given... */\n\t\tpr_warn(\"Warning: arp_interval module parameter (%d) specified without providing an arp_ip_target parameter, arp_interval was reset to 0\\n\",\n\t\t\tarp_interval);\n\t\tarp_interval = 0;\n\t}\n\n\tif (arp_validate) {\n\t\tif (!arp_interval) {\n\t\t\tpr_err(\"arp_validate requires arp_interval\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tbond_opt_initstr(&newval, arp_validate);\n\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_ARP_VALIDATE),\n\t\t\t\t\t&newval);\n\t\tif (!valptr) {\n\t\t\tpr_err(\"Error: invalid arp_validate \\\"%s\\\"\\n\",\n\t\t\t       arp_validate);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tarp_validate_value = valptr->value;\n\t} else {\n\t\tarp_validate_value = 0;\n\t}\n\n\tif (arp_all_targets) {\n\t\tbond_opt_initstr(&newval, arp_all_targets);\n\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_ARP_ALL_TARGETS),\n\t\t\t\t\t&newval);\n\t\tif (!valptr) {\n\t\t\tpr_err(\"Error: invalid arp_all_targets_value \\\"%s\\\"\\n\",\n\t\t\t       arp_all_targets);\n\t\t\tarp_all_targets_value = 0;\n\t\t} else {\n\t\t\tarp_all_targets_value = valptr->value;\n\t\t}\n\t}\n\n\tif (miimon) {\n\t\tpr_info(\"MII link monitoring set to %d ms\\n\", miimon);\n\t} else if (arp_interval) {\n\t\tvalptr = bond_opt_get_val(BOND_OPT_ARP_VALIDATE,\n\t\t\t\t\t  arp_validate_value);\n\t\tpr_info(\"ARP monitoring set to %d ms, validate %s, with %d target(s):\",\n\t\t\tarp_interval, valptr->string, arp_ip_count);\n\n\t\tfor (i = 0; i < arp_ip_count; i++)\n\t\t\tpr_cont(\" %s\", arp_ip_target[i]);\n\n\t\tpr_cont(\"\\n\");\n\n\t} else if (max_bonds) {\n\t\t/* miimon and arp_interval not set, we need one so things\n\t\t * work as expected, see bonding.txt for details\n\t\t */\n\t\tpr_debug(\"Warning: either miimon or arp_interval and arp_ip_target module parameters must be specified, otherwise bonding will not detect link failures! see bonding.txt for details\\n\");\n\t}\n\n\tif (primary && !bond_mode_uses_primary(bond_mode)) {\n\t\t/* currently, using a primary only makes sense\n\t\t * in active backup, TLB or ALB modes\n\t\t */\n\t\tpr_warn(\"Warning: %s primary device specified but has no effect in %s mode\\n\",\n\t\t\tprimary, bond_mode_name(bond_mode));\n\t\tprimary = NULL;\n\t}\n\n\tif (primary && primary_reselect) {\n\t\tbond_opt_initstr(&newval, primary_reselect);\n\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_PRIMARY_RESELECT),\n\t\t\t\t\t&newval);\n\t\tif (!valptr) {\n\t\t\tpr_err(\"Error: Invalid primary_reselect \\\"%s\\\"\\n\",\n\t\t\t       primary_reselect);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tprimary_reselect_value = valptr->value;\n\t} else {\n\t\tprimary_reselect_value = BOND_PRI_RESELECT_ALWAYS;\n\t}\n\n\tif (fail_over_mac) {\n\t\tbond_opt_initstr(&newval, fail_over_mac);\n\t\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_FAIL_OVER_MAC),\n\t\t\t\t\t&newval);\n\t\tif (!valptr) {\n\t\t\tpr_err(\"Error: invalid fail_over_mac \\\"%s\\\"\\n\",\n\t\t\t       fail_over_mac);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tfail_over_mac_value = valptr->value;\n\t\tif (bond_mode != BOND_MODE_ACTIVEBACKUP)\n\t\t\tpr_warn(\"Warning: fail_over_mac only affects active-backup mode\\n\");\n\t} else {\n\t\tfail_over_mac_value = BOND_FOM_NONE;\n\t}\n\n\tbond_opt_initstr(&newval, \"default\");\n\tvalptr = bond_opt_parse(\n\t\t\tbond_opt_get(BOND_OPT_AD_ACTOR_SYS_PRIO),\n\t\t\t\t     &newval);\n\tif (!valptr) {\n\t\tpr_err(\"Error: No ad_actor_sys_prio default value\");\n\t\treturn -EINVAL;\n\t}\n\tad_actor_sys_prio = valptr->value;\n\n\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_AD_USER_PORT_KEY),\n\t\t\t\t&newval);\n\tif (!valptr) {\n\t\tpr_err(\"Error: No ad_user_port_key default value\");\n\t\treturn -EINVAL;\n\t}\n\tad_user_port_key = valptr->value;\n\n\tbond_opt_initstr(&newval, \"default\");\n\tvalptr = bond_opt_parse(bond_opt_get(BOND_OPT_TLB_DYNAMIC_LB), &newval);\n\tif (!valptr) {\n\t\tpr_err(\"Error: No tlb_dynamic_lb default value\");\n\t\treturn -EINVAL;\n\t}\n\ttlb_dynamic_lb = valptr->value;\n\n\tif (lp_interval == 0) {\n\t\tpr_warn(\"Warning: ip_interval must be between 1 and %d, so it was reset to %d\\n\",\n\t\t\tINT_MAX, BOND_ALB_DEFAULT_LP_INTERVAL);\n\t\tlp_interval = BOND_ALB_DEFAULT_LP_INTERVAL;\n\t}\n\n\t/* fill params struct with the proper values */\n\tparams->mode = bond_mode;\n\tparams->xmit_policy = xmit_hashtype;\n\tparams->miimon = miimon;\n\tparams->num_peer_notif = num_peer_notif;\n\tparams->arp_interval = arp_interval;\n\tparams->arp_validate = arp_validate_value;\n\tparams->arp_all_targets = arp_all_targets_value;\n\tparams->missed_max = 2;\n\tparams->updelay = updelay;\n\tparams->downdelay = downdelay;\n\tparams->peer_notif_delay = 0;\n\tparams->use_carrier = use_carrier;\n\tparams->lacp_active = 1;\n\tparams->lacp_fast = lacp_fast;\n\tparams->primary[0] = 0;\n\tparams->primary_reselect = primary_reselect_value;\n\tparams->fail_over_mac = fail_over_mac_value;\n\tparams->tx_queues = tx_queues;\n\tparams->all_slaves_active = all_slaves_active;\n\tparams->resend_igmp = resend_igmp;\n\tparams->min_links = min_links;\n\tparams->lp_interval = lp_interval;\n\tparams->packets_per_slave = packets_per_slave;\n\tparams->tlb_dynamic_lb = tlb_dynamic_lb;\n\tparams->ad_actor_sys_prio = ad_actor_sys_prio;\n\teth_zero_addr(params->ad_actor_system);\n\tparams->ad_user_port_key = ad_user_port_key;\n\tif (packets_per_slave > 0) {\n\t\tparams->reciprocal_packets_per_slave =\n\t\t\treciprocal_value(packets_per_slave);\n\t} else {\n\t\t/* reciprocal_packets_per_slave is unused if\n\t\t * packets_per_slave is 0 or 1, just initialize it\n\t\t */\n\t\tparams->reciprocal_packets_per_slave =\n\t\t\t(struct reciprocal_value) { 0 };\n\t}\n\n\tif (primary)\n\t\tstrscpy_pad(params->primary, primary, sizeof(params->primary));\n\n\tmemcpy(params->arp_targets, arp_target, sizeof(arp_target));\n#if IS_ENABLED(CONFIG_IPV6)\n\tmemset(params->ns_targets, 0, sizeof(struct in6_addr) * BOND_MAX_NS_TARGETS);\n#endif\n\n\treturn 0;\n}",
        "static int mb_mark_used(struct ext4_buddy *e4b, struct ext4_free_extent *ex)\n{\n\tint ord;\n\tint mlen = 0;\n\tint max = 0;": "static int mb_mark_used(struct ext4_buddy *e4b, struct ext4_free_extent *ex)\n{\n\tint ord;\n\tint mlen = 0;\n\tint max = 0;\n\tint cur;\n\tint start = ex->fe_start;\n\tint len = ex->fe_len;\n\tunsigned ret = 0;\n\tint len0 = len;\n\tvoid *buddy;\n\n\tBUG_ON(start + len > (e4b->bd_sb->s_blocksize << 3));\n\tBUG_ON(e4b->bd_group != ex->fe_group);\n\tassert_spin_locked(ext4_group_lock_ptr(e4b->bd_sb, e4b->bd_group));\n\tmb_check_buddy(e4b);\n\tmb_mark_used_double(e4b, start, len);\n\n\tthis_cpu_inc(discard_pa_seq);\n\te4b->bd_info->bb_free -= len;\n\tif (e4b->bd_info->bb_first_free == start)\n\t\te4b->bd_info->bb_first_free += len;\n\n\t/* let's maintain fragments counter */\n\tif (start != 0)\n\t\tmlen = !mb_test_bit(start - 1, e4b->bd_bitmap);\n\tif (start + len < EXT4_SB(e4b->bd_sb)->s_mb_maxs[0])\n\t\tmax = !mb_test_bit(start + len, e4b->bd_bitmap);\n\tif (mlen && max)\n\t\te4b->bd_info->bb_fragments++;\n\telse if (!mlen && !max)\n\t\te4b->bd_info->bb_fragments--;\n\n\t/* let's maintain buddy itself */\n\twhile (len) {\n\t\tord = mb_find_order_for_block(e4b, start);\n\n\t\tif (((start >> ord) << ord) == start && len >= (1 << ord)) {\n\t\t\t/* the whole chunk may be allocated at once! */\n\t\t\tmlen = 1 << ord;\n\t\t\tbuddy = mb_find_buddy(e4b, ord, &max);\n\t\t\tBUG_ON((start >> ord) >= max);\n\t\t\tmb_set_bit(start >> ord, buddy);\n\t\t\te4b->bd_info->bb_counters[ord]--;\n\t\t\tstart += mlen;\n\t\t\tlen -= mlen;\n\t\t\tBUG_ON(len < 0);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* store for history */\n\t\tif (ret == 0)\n\t\t\tret = len | (ord << 16);\n\n\t\t/* we have to split large buddy */\n\t\tBUG_ON(ord <= 0);\n\t\tbuddy = mb_find_buddy(e4b, ord, &max);\n\t\tmb_set_bit(start >> ord, buddy);\n\t\te4b->bd_info->bb_counters[ord]--;\n\n\t\tord--;\n\t\tcur = (start >> ord) & ~1U;\n\t\tbuddy = mb_find_buddy(e4b, ord, &max);\n\t\tmb_clear_bit(cur, buddy);\n\t\tmb_clear_bit(cur + 1, buddy);\n\t\te4b->bd_info->bb_counters[ord]++;\n\t\te4b->bd_info->bb_counters[ord]++;\n\t}\n\tmb_set_largest_free_order(e4b->bd_sb, e4b->bd_info);\n\n\tmb_update_avg_fragment_size(e4b->bd_sb, e4b->bd_info);\n\tmb_set_bits(e4b->bd_bitmap, ex->fe_start, len0);\n\tmb_check_buddy(e4b);\n\n\treturn ret;\n}",
        "static int fw_cfg_cmdline_set(const char *arg, const struct kernel_param *kp)\n{\n\tstruct resource res[4] = {};\n\tchar *str;\n\tphys_addr_t base;": "static int fw_cfg_cmdline_set(const char *arg, const struct kernel_param *kp)\n{\n\tstruct resource res[4] = {};\n\tchar *str;\n\tphys_addr_t base;\n\tresource_size_t size, ctrl_off, data_off, dma_off;\n\tint processed, consumed = 0;\n\n\t/* only one fw_cfg device can exist system-wide, so if one\n\t * was processed on the command line already, we might as\n\t * well stop here.\n\t */\n\tif (fw_cfg_cmdline_dev) {\n\t\t/* avoid leaking previously registered device */\n\t\tplatform_device_unregister(fw_cfg_cmdline_dev);\n\t\treturn -EINVAL;\n\t}\n\n\t/* consume \"<size>\" portion of command line argument */\n\tsize = memparse(arg, &str);\n\n\t/* get \"@<base>[:<ctrl_off>:<data_off>[:<dma_off>]]\" chunks */\n\tprocessed = sscanf(str, PH_ADDR_SCAN_FMT,\n\t\t\t   &base, &consumed,\n\t\t\t   &ctrl_off, &data_off, &consumed,\n\t\t\t   &dma_off, &consumed);\n\n\t/* sscanf() must process precisely 1, 3 or 4 chunks:\n\t * <base> is mandatory, optionally followed by <ctrl_off>\n\t * and <data_off>, and <dma_off>;\n\t * there must be no extra characters after the last chunk,\n\t * so str[consumed] must be '\\0'.\n\t */\n\tif (str[consumed] ||\n\t    (processed != 1 && processed != 3 && processed != 4))\n\t\treturn -EINVAL;\n\n\tres[0].start = base;\n\tres[0].end = base + size - 1;\n\tres[0].flags = !strcmp(kp->name, \"mmio\") ? IORESOURCE_MEM :\n\t\t\t\t\t\t   IORESOURCE_IO;\n\n\t/* insert register offsets, if provided */\n\tif (processed > 1) {\n\t\tres[1].name = \"ctrl\";\n\t\tres[1].start = ctrl_off;\n\t\tres[1].flags = IORESOURCE_REG;\n\t\tres[2].name = \"data\";\n\t\tres[2].start = data_off;\n\t\tres[2].flags = IORESOURCE_REG;\n\t}\n\tif (processed > 3) {\n\t\tres[3].name = \"dma\";\n\t\tres[3].start = dma_off;\n\t\tres[3].flags = IORESOURCE_REG;\n\t}\n\n\t/* \"processed\" happens to nicely match the number of resources\n\t * we need to pass in to this platform device.\n\t */\n\tfw_cfg_cmdline_dev = platform_device_register_simple(\"fw_cfg\",\n\t\t\t\t\tPLATFORM_DEVID_NONE, res, processed);\n\n\treturn PTR_ERR_OR_ZERO(fw_cfg_cmdline_dev);\n}",
        "static void k_pad(struct vc_data *vc, unsigned char value, char up_flag)\n{\n\tstatic const char pad_chars[] = \"0123456789+-*/\\015,.?()#\";\n\tstatic const char app_map[] = \"pqrstuvwxylSRQMnnmPQS\";\n": "static void k_pad(struct vc_data *vc, unsigned char value, char up_flag)\n{\n\tstatic const char pad_chars[] = \"0123456789+-*/\\015,.?()#\";\n\tstatic const char app_map[] = \"pqrstuvwxylSRQMnnmPQS\";\n\n\tif (up_flag)\n\t\treturn;\t\t/* no action, if this is a key release */\n\n\t/* kludge... shift forces cursor/number keys */\n\tif (vc_kbd_mode(kbd, VC_APPLIC) && !shift_down[KG_SHIFT]) {\n\t\tapplkey(vc, app_map[value], 1);\n\t\treturn;\n\t}\n\n\tif (!vc_kbd_led(kbd, VC_NUMLOCK)) {\n\n\t\tswitch (value) {\n\t\tcase KVAL(K_PCOMMA):\n\t\tcase KVAL(K_PDOT):\n\t\t\tk_fn(vc, KVAL(K_REMOVE), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P0):\n\t\t\tk_fn(vc, KVAL(K_INSERT), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P1):\n\t\t\tk_fn(vc, KVAL(K_SELECT), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P2):\n\t\t\tk_cur(vc, KVAL(K_DOWN), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P3):\n\t\t\tk_fn(vc, KVAL(K_PGDN), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P4):\n\t\t\tk_cur(vc, KVAL(K_LEFT), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P6):\n\t\t\tk_cur(vc, KVAL(K_RIGHT), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P7):\n\t\t\tk_fn(vc, KVAL(K_FIND), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P8):\n\t\t\tk_cur(vc, KVAL(K_UP), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P9):\n\t\t\tk_fn(vc, KVAL(K_PGUP), 0);\n\t\t\treturn;\n\t\tcase KVAL(K_P5):\n\t\t\tapplkey(vc, 'G', vc_kbd_mode(kbd, VC_APPLIC));\n\t\t\treturn;\n\t\t}\n\t}\n\n\tput_queue(vc, pad_chars[value]);\n\tif (value == KVAL(K_PENTER) && vc_kbd_mode(kbd, VC_CRLF))\n\t\tput_queue(vc, '\\n');\n}",
        "static int cio2_queue_init(struct cio2_device *cio2, struct cio2_queue *q)\n{\n\tstatic const u32 default_width = 1936;\n\tstatic const u32 default_height = 1096;\n\tconst struct ipu3_cio2_fmt dflt_fmt = formats[0];": "static int cio2_queue_init(struct cio2_device *cio2, struct cio2_queue *q)\n{\n\tstatic const u32 default_width = 1936;\n\tstatic const u32 default_height = 1096;\n\tconst struct ipu3_cio2_fmt dflt_fmt = formats[0];\n\tstruct device *dev = &cio2->pci_dev->dev;\n\tstruct video_device *vdev = &q->vdev;\n\tstruct vb2_queue *vbq = &q->vbq;\n\tstruct v4l2_subdev *subdev = &q->subdev;\n\tstruct v4l2_mbus_framefmt *fmt;\n\tint r;\n\n\t/* Initialize miscellaneous variables */\n\tmutex_init(&q->lock);\n\tmutex_init(&q->subdev_lock);\n\n\t/* Initialize formats to default values */\n\tfmt = &q->subdev_fmt;\n\tfmt->width = default_width;\n\tfmt->height = default_height;\n\tfmt->code = dflt_fmt.mbus_code;\n\tfmt->field = V4L2_FIELD_NONE;\n\n\tq->format.width = default_width;\n\tq->format.height = default_height;\n\tq->format.pixelformat = dflt_fmt.fourcc;\n\tq->format.colorspace = V4L2_COLORSPACE_RAW;\n\tq->format.field = V4L2_FIELD_NONE;\n\tq->format.num_planes = 1;\n\tq->format.plane_fmt[0].bytesperline =\n\t\t\t\tcio2_bytesperline(q->format.width);\n\tq->format.plane_fmt[0].sizeimage = q->format.plane_fmt[0].bytesperline *\n\t\t\t\t\t\tq->format.height;\n\n\t/* Initialize fbpt */\n\tr = cio2_fbpt_init(cio2, q);\n\tif (r)\n\t\tgoto fail_fbpt;\n\n\t/* Initialize media entities */\n\tq->subdev_pads[CIO2_PAD_SINK].flags = MEDIA_PAD_FL_SINK |\n\t\tMEDIA_PAD_FL_MUST_CONNECT;\n\tq->subdev_pads[CIO2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;\n\tsubdev->entity.ops = &cio2_media_ops;\n\tsubdev->internal_ops = &cio2_subdev_internal_ops;\n\tr = media_entity_pads_init(&subdev->entity, CIO2_PADS, q->subdev_pads);\n\tif (r) {\n\t\tdev_err(dev, \"failed initialize subdev media entity (%d)\\n\", r);\n\t\tgoto fail_subdev_media_entity;\n\t}\n\n\tq->vdev_pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;\n\tvdev->entity.ops = &cio2_video_entity_ops;\n\tr = media_entity_pads_init(&vdev->entity, 1, &q->vdev_pad);\n\tif (r) {\n\t\tdev_err(dev, \"failed initialize videodev media entity (%d)\\n\",\n\t\t\tr);\n\t\tgoto fail_vdev_media_entity;\n\t}\n\n\t/* Initialize subdev */\n\tv4l2_subdev_init(subdev, &cio2_subdev_ops);\n\tsubdev->flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;\n\tsubdev->owner = THIS_MODULE;\n\tsnprintf(subdev->name, sizeof(subdev->name),\n\t\t CIO2_ENTITY_NAME \" %td\", q - cio2->queue);\n\tsubdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;\n\tv4l2_set_subdevdata(subdev, cio2);\n\tr = v4l2_device_register_subdev(&cio2->v4l2_dev, subdev);\n\tif (r) {\n\t\tdev_err(dev, \"failed initialize subdev (%d)\\n\", r);\n\t\tgoto fail_subdev;\n\t}\n\n\t/* Initialize vbq */\n\tvbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;\n\tvbq->io_modes = VB2_USERPTR | VB2_MMAP | VB2_DMABUF;\n\tvbq->ops = &cio2_vb2_ops;\n\tvbq->mem_ops = &vb2_dma_sg_memops;\n\tvbq->buf_struct_size = sizeof(struct cio2_buffer);\n\tvbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n\tvbq->min_buffers_needed = 1;\n\tvbq->drv_priv = cio2;\n\tvbq->lock = &q->lock;\n\tr = vb2_queue_init(vbq);\n\tif (r) {\n\t\tdev_err(dev, \"failed to initialize videobuf2 queue (%d)\\n\", r);\n\t\tgoto fail_subdev;\n\t}\n\n\t/* Initialize vdev */\n\tsnprintf(vdev->name, sizeof(vdev->name),\n\t\t \"%s %td\", CIO2_NAME, q - cio2->queue);\n\tvdev->release = video_device_release_empty;\n\tvdev->fops = &cio2_v4l2_fops;\n\tvdev->ioctl_ops = &cio2_v4l2_ioctl_ops;\n\tvdev->lock = &cio2->lock;\n\tvdev->v4l2_dev = &cio2->v4l2_dev;\n\tvdev->queue = &q->vbq;\n\tvdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;\n\tvideo_set_drvdata(vdev, cio2);\n\tr = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n\tif (r) {\n\t\tdev_err(dev, \"failed to register video device (%d)\\n\", r);\n\t\tgoto fail_vdev;\n\t}\n\n\t/* Create link from CIO2 subdev to output node */\n\tr = media_create_pad_link(\n\t\t&subdev->entity, CIO2_PAD_SOURCE, &vdev->entity, 0,\n\t\tMEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);\n\tif (r)\n\t\tgoto fail_link;\n\n\treturn 0;\n\nfail_link:\n\tvb2_video_unregister_device(&q->vdev);\nfail_vdev:\n\tv4l2_device_unregister_subdev(subdev);\nfail_subdev:\n\tmedia_entity_cleanup(&vdev->entity);\nfail_vdev_media_entity:\n\tmedia_entity_cleanup(&subdev->entity);\nfail_subdev_media_entity:\n\tcio2_fbpt_exit(q, dev);\nfail_fbpt:\n\tmutex_destroy(&q->subdev_lock);\n\tmutex_destroy(&q->lock);\n\n\treturn r;\n}",
        "static void br_multicast_fwd_src_add(struct net_bridge_group_src *src)\n{\n\tstruct net_bridge_mdb_entry *star_mp;\n\tstruct net_bridge_mcast_port *pmctx;\n\tstruct net_bridge_port_group *sg;": "static void br_multicast_fwd_src_add(struct net_bridge_group_src *src)\n{\n\tstruct net_bridge_mdb_entry *star_mp;\n\tstruct net_bridge_mcast_port *pmctx;\n\tstruct net_bridge_port_group *sg;\n\tstruct net_bridge_mcast *brmctx;\n\tstruct br_ip sg_ip;\n\n\tif (src->flags & BR_SGRP_F_INSTALLED)\n\t\treturn;\n\n\tmemset(&sg_ip, 0, sizeof(sg_ip));\n\tpmctx = br_multicast_pg_to_port_ctx(src->pg);\n\tif (!pmctx)\n\t\treturn;\n\tbrmctx = br_multicast_port_ctx_get_global(pmctx);\n\tsg_ip = src->pg->key.addr;\n\tsg_ip.src = src->addr.src;\n\n\tsg = __br_multicast_add_group(brmctx, pmctx, &sg_ip,\n\t\t\t\t      src->pg->eth_addr, MCAST_INCLUDE, false,\n\t\t\t\t      !timer_pending(&src->timer));\n\tif (IS_ERR_OR_NULL(sg))\n\t\treturn;\n\tsrc->flags |= BR_SGRP_F_INSTALLED;\n\tsg->flags &= ~MDB_PG_FLAGS_STAR_EXCL;\n\n\t/* if it was added by user-space as perm we can skip next steps */\n\tif (sg->rt_protocol != RTPROT_KERNEL &&\n\t    (sg->flags & MDB_PG_FLAGS_PERMANENT))\n\t\treturn;\n\n\t/* the kernel is now responsible for removing this S,G */\n\tdel_timer(&sg->timer);\n\tstar_mp = br_mdb_ip_get(src->br, &src->pg->key.addr);\n\tif (!star_mp)\n\t\treturn;\n\n\tbr_multicast_sg_add_exclude_ports(star_mp, sg);\n}",
        "static int __init console_setup(char *str)\n{\n\tchar buf[sizeof(console_cmdline[0].name) + 4]; /* 4 for \"ttyS\" */\n\tchar *s, *options, *brl_options = NULL;\n\tint idx;": "static int __init console_setup(char *str)\n{\n\tchar buf[sizeof(console_cmdline[0].name) + 4]; /* 4 for \"ttyS\" */\n\tchar *s, *options, *brl_options = NULL;\n\tint idx;\n\n\t/*\n\t * console=\"\" or console=null have been suggested as a way to\n\t * disable console output. Use ttynull that has been created\n\t * for exactly this purpose.\n\t */\n\tif (str[0] == 0 || strcmp(str, \"null\") == 0) {\n\t\t__add_preferred_console(\"ttynull\", 0, NULL, NULL, true);\n\t\treturn 1;\n\t}\n\n\tif (_braille_console_setup(&str, &brl_options))\n\t\treturn 1;\n\n\t/*\n\t * Decode str into name, index, options.\n\t */\n\tif (str[0] >= '0' && str[0] <= '9') {\n\t\tstrcpy(buf, \"ttyS\");\n\t\tstrncpy(buf + 4, str, sizeof(buf) - 5);\n\t} else {\n\t\tstrncpy(buf, str, sizeof(buf) - 1);\n\t}\n\tbuf[sizeof(buf) - 1] = 0;\n\toptions = strchr(str, ',');\n\tif (options)\n\t\t*(options++) = 0;\n#ifdef __sparc__\n\tif (!strcmp(str, \"ttya\"))\n\t\tstrcpy(buf, \"ttyS0\");\n\tif (!strcmp(str, \"ttyb\"))\n\t\tstrcpy(buf, \"ttyS1\");\n#endif\n\tfor (s = buf; *s; s++)\n\t\tif (isdigit(*s) || *s == ',')\n\t\t\tbreak;\n\tidx = simple_strtoul(s, NULL, 10);\n\t*s = 0;\n\n\t__add_preferred_console(buf, idx, options, brl_options, true);\n\treturn 1;\n}",
        "static void lpss_iosf_exit_d3_state(void)\n{\n\tu32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |\n\t\t     LPSS_GPIODEF0_DMA_LLP;\n\tu32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;": "static void lpss_iosf_exit_d3_state(void)\n{\n\tu32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |\n\t\t     LPSS_GPIODEF0_DMA_LLP;\n\tu32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;\n\tu32 value2 = LPSS_PMCSR_D0;\n\tu32 mask2 = LPSS_PMCSR_Dx_MASK;\n\n\tmutex_lock(&lpss_iosf_mutex);\n\n\tif (!lpss_iosf_d3_entered)\n\t\tgoto exit;\n\n\tlpss_iosf_d3_entered = false;\n\n\tiosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,\n\t\t\tLPSS_IOSF_GPIODEF0, value1, mask1);\n\n\tiosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,\n\t\t\tLPSS_IOSF_PMCSR, value2, mask2);\n\n\tiosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,\n\t\t\tLPSS_IOSF_PMCSR, value2, mask2);\n\nexit:\n\tmutex_unlock(&lpss_iosf_mutex);\n}",
        "static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)\n{\n\t/*\n\t * We need to differentiate between GPIO and non-GPIO signals to\n\t * implement the gpio_request_enable() interface. For better or worse": "static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)\n{\n\t/*\n\t * We need to differentiate between GPIO and non-GPIO signals to\n\t * implement the gpio_request_enable() interface. For better or worse\n\t * the ASPEED pinctrl driver uses the expression names to determine\n\t * whether an expression will mux a pin for GPIO.\n\t *\n\t * Generally we have the following - A GPIO such as B1 has:\n\t *\n\t *    - expr->signal set to \"GPIOB1\"\n\t *    - expr->function set to \"GPIOB1\"\n\t *\n\t * Using this fact we can determine whether the provided expression is\n\t * a GPIO expression by testing the signal name for the string prefix\n\t * \"GPIO\".\n\t *\n\t * However, some GPIOs are input-only, and the ASPEED datasheets name\n\t * them differently. An input-only GPIO such as T0 has:\n\t *\n\t *    - expr->signal set to \"GPIT0\"\n\t *    - expr->function set to \"GPIT0\"\n\t *\n\t * It's tempting to generalise the prefix test from \"GPIO\" to \"GPI\" to\n\t * account for both GPIOs and GPIs, but in doing so we run aground on\n\t * another feature:\n\t *\n\t * Some pins in the ASPEED BMC SoCs have a \"pass-through\" GPIO\n\t * function where the input state of one pin is replicated as the\n\t * output state of another (as if they were shorted together - a mux\n\t * configuration that is typically enabled by hardware strapping).\n\t * This feature allows the BMC to pass e.g. power button state through\n\t * to the host while the BMC is yet to boot, but take control of the\n\t * button state once the BMC has booted by muxing each pin as a\n\t * separate, pin-specific GPIO.\n\t *\n\t * Conceptually this pass-through mode is a form of GPIO and is named\n\t * as such in the datasheets, e.g. \"GPID0\". This naming similarity\n\t * trips us up with the simple GPI-prefixed-signal-name scheme\n\t * discussed above, as the pass-through configuration is not what we\n\t * want when muxing a pin as GPIO for the GPIO subsystem.\n\t *\n\t * On e.g. the AST2400, a pass-through function \"GPID0\" is grouped on\n\t * balls A18 and D16, where we have:\n\t *\n\t *    For ball A18:\n\t *    - expr->signal set to \"GPID0IN\"\n\t *    - expr->function set to \"GPID0\"\n\t *\n\t *    For ball D16:\n\t *    - expr->signal set to \"GPID0OUT\"\n\t *    - expr->function set to \"GPID0\"\n\t *\n\t * By contrast, the pin-specific GPIO expressions for the same pins are\n\t * as follows:\n\t *\n\t *    For ball A18:\n\t *    - expr->signal looks like \"GPIOD0\"\n\t *    - expr->function looks like \"GPIOD0\"\n\t *\n\t *    For ball D16:\n\t *    - expr->signal looks like \"GPIOD1\"\n\t *    - expr->function looks like \"GPIOD1\"\n\t *\n\t * Testing both the signal _and_ function names gives us the means\n\t * differentiate the pass-through GPIO pinmux configuration from the\n\t * pin-specific configuration that the GPIO subsystem is after: An\n\t * expression is a pin-specific (non-pass-through) GPIO configuration\n\t * if the signal prefix is \"GPI\" and the signal name matches the\n\t * function name.\n\t */\n\treturn !strncmp(expr->signal, \"GPI\", 3) &&\n\t\t\t!strcmp(expr->signal, expr->function);\n}",
        "static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)\n{\n\tunsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;\n\tunsigned int last_len = nfc_op->len % 4;\n\tunsigned int offset, dir;": "static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)\n{\n\tunsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;\n\tunsigned int last_len = nfc_op->len % 4;\n\tunsigned int offset, dir;\n\tu8 *buf = nfc_op->buf;\n\tint ret, i;\n\n\tfor (i = 0; i < nfc_op->steps; i++) {\n\t\tdir = nfc_op->read ? READ_READY : WRITE_READY;\n\t\tret = anfc_wait_for_event(nfc, dir);\n\t\tif (ret) {\n\t\t\tdev_err(nfc->dev, \"PIO %s ready signal not received\\n\",\n\t\t\t\tnfc_op->read ? \"Read\" : \"Write\");\n\t\t\treturn ret;\n\t\t}\n\n\t\toffset = i * (dwords * 4);\n\t\tif (nfc_op->read)\n\t\t\tioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],\n\t\t\t\t     dwords);\n\t\telse\n\t\t\tiowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],\n\t\t\t\t      dwords);\n\t}\n\n\tif (last_len) {\n\t\tu32 remainder;\n\n\t\toffset = nfc_op->len - last_len;\n\n\t\tif (nfc_op->read) {\n\t\t\tremainder = readl_relaxed(nfc->base + DATA_PORT_REG);\n\t\t\tmemcpy(&buf[offset], &remainder, last_len);\n\t\t} else {\n\t\t\tmemcpy(&remainder, &buf[offset], last_len);\n\t\t\twritel_relaxed(remainder, nfc->base + DATA_PORT_REG);\n\t\t}\n\t}\n\n\treturn anfc_wait_for_event(nfc, XFER_COMPLETE);\n}",
        "static inline bool usage_skip(struct lock_list *entry, void *mask)\n{\n\t/*\n\t * Skip local_lock() for irq inversion detection.\n\t *": "static inline bool usage_skip(struct lock_list *entry, void *mask)\n{\n\t/*\n\t * Skip local_lock() for irq inversion detection.\n\t *\n\t * For !RT, local_lock() is not a real lock, so it won't carry any\n\t * dependency.\n\t *\n\t * For RT, an irq inversion happens when we have lock A and B, and on\n\t * some CPU we can have:\n\t *\n\t *\tlock(A);\n\t *\t<interrupted>\n\t *\t  lock(B);\n\t *\n\t * where lock(B) cannot sleep, and we have a dependency B -> ... -> A.\n\t *\n\t * Now we prove local_lock() cannot exist in that dependency. First we\n\t * have the observation for any lock chain L1 -> ... -> Ln, for any\n\t * 1 <= i <= n, Li.inner_wait_type <= L1.inner_wait_type, otherwise\n\t * wait context check will complain. And since B is not a sleep lock,\n\t * therefore B.inner_wait_type >= 2, and since the inner_wait_type of\n\t * local_lock() is 3, which is greater than 2, therefore there is no\n\t * way the local_lock() exists in the dependency B -> ... -> A.\n\t *\n\t * As a result, we will skip local_lock(), when we search for irq\n\t * inversion bugs.\n\t */\n\tif (entry->class->lock_type == LD_LOCK_PERCPU) {\n\t\tif (DEBUG_LOCKS_WARN_ON(entry->class->wait_type_inner < LD_WAIT_CONFIG))\n\t\t\treturn false;\n\n\t\treturn true;\n\t}\n\n\treturn false;\n}",
        "static int hst_create(struct path_selector *ps, unsigned int argc, char **argv)\n{\n\tstruct selector *s;\n\tunsigned int base_weight = HST_FIXED_95;\n\tunsigned int threshold_multiplier = 0;": "static int hst_create(struct path_selector *ps, unsigned int argc, char **argv)\n{\n\tstruct selector *s;\n\tunsigned int base_weight = HST_FIXED_95;\n\tunsigned int threshold_multiplier = 0;\n\tchar dummy;\n\n\t/*\n\t * Arguments: [<base_weight> [<threshold_multiplier>]]\n\t *   <base_weight>: Base weight for ema [0, 1024) 10-bit fixed point. A\n\t *                  value of 0 will completely ignore any history.\n\t *                  If not given, default (HST_FIXED_95) is used.\n\t *   <threshold_multiplier>: Minimum threshold multiplier for paths to\n\t *                  be considered different. That is, a path is\n\t *                  considered different iff (p1 > N * p2) where p1\n\t *                  is the path with higher service time. A threshold\n\t *                  of 1 or 0 has no effect. Defaults to 0.\n\t */\n\tif (argc > 2)\n\t\treturn -EINVAL;\n\n\tif (argc && (sscanf(argv[0], \"%u%c\", &base_weight, &dummy) != 1 ||\n\t     base_weight >= HST_FIXED_1)) {\n\t\treturn -EINVAL;\n\t}\n\n\tif (argc > 1 && (sscanf(argv[1], \"%u%c\",\n\t\t\t\t&threshold_multiplier, &dummy) != 1)) {\n\t\treturn -EINVAL;\n\t}\n\n\ts = alloc_selector();\n\tif (!s)\n\t\treturn -ENOMEM;\n\n\tps->context = s;\n\n\thst_set_weights(ps, base_weight);\n\ts->threshold_multiplier = threshold_multiplier;\n\treturn 0;\n}",
        "static inline void tm2rtc(struct rtc_time *t, struct bd70528_rtc_data *r)\n{\n\tr->day &= ~BD70528_MASK_RTC_DAY;\n\tr->week &= ~BD70528_MASK_RTC_WEEK;\n\tr->month &= ~BD70528_MASK_RTC_MONTH;": "static inline void tm2rtc(struct rtc_time *t, struct bd70528_rtc_data *r)\n{\n\tr->day &= ~BD70528_MASK_RTC_DAY;\n\tr->week &= ~BD70528_MASK_RTC_WEEK;\n\tr->month &= ~BD70528_MASK_RTC_MONTH;\n\t/*\n\t * PM and 24H bits are not used by Wake - thus we clear them\n\t * here and not in tmday2rtc() which is also used by wake.\n\t */\n\tr->time.hour &= ~(BD70528_MASK_RTC_HOUR_PM | BD70528_MASK_RTC_HOUR_24H);\n\n\ttmday2rtc(t, &r->time);\n\t/*\n\t * We do always set time in 24H mode.\n\t */\n\tr->time.hour |= BD70528_MASK_RTC_HOUR_24H;\n\tr->day |= bin2bcd(t->tm_mday);\n\tr->week |= bin2bcd(t->tm_wday);\n\tr->month |= bin2bcd(t->tm_mon + 1);\n\tr->year = bin2bcd(t->tm_year - 100);\n}",
        "static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)\n{\n/* fixme (low): add error handling */\n\tu32 ratio;\n\tu32 tmp, fclk, BDRI;": "static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)\n{\n/* fixme (low): add error handling */\n\tu32 ratio;\n\tu32 tmp, fclk, BDRI;\n\n\tstatic const u32 bands[]={5000000UL,15000000UL,90999000UL/2};\n\tint i;\n\n\tdprintk(\"cx24110 debug: entering %s(%d)\\n\",__func__,srate);\n\tif (srate>90999000UL/2)\n\t\tsrate=90999000UL/2;\n\tif (srate<500000)\n\t\tsrate=500000;\n\n\tfor(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)\n\t\t;\n\t/* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,\n\t   and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,\n\t   R06[3:0] PLLphaseDetGain */\n\ttmp=cx24110_readreg(state,0x07)&0xfc;\n\tif(srate<90999000UL/4) { /* sample rate 45MHz*/\n\t\tcx24110_writereg(state,0x07,tmp);\n\t\tcx24110_writereg(state,0x06,0x78);\n\t\tfclk=90999000UL/2;\n\t} else if(srate<60666000UL/2) { /* sample rate 60MHz */\n\t\tcx24110_writereg(state,0x07,tmp|0x1);\n\t\tcx24110_writereg(state,0x06,0xa5);\n\t\tfclk=60666000UL;\n\t} else if(srate<80888000UL/2) { /* sample rate 80MHz */\n\t\tcx24110_writereg(state,0x07,tmp|0x2);\n\t\tcx24110_writereg(state,0x06,0x87);\n\t\tfclk=80888000UL;\n\t} else { /* sample rate 90MHz */\n\t\tcx24110_writereg(state,0x07,tmp|0x3);\n\t\tcx24110_writereg(state,0x06,0x78);\n\t\tfclk=90999000UL;\n\t}\n\tdprintk(\"cx24110 debug: fclk %d Hz\\n\",fclk);\n\t/* we need to divide two integers with approx. 27 bits in 32 bit\n\t   arithmetic giving a 25 bit result */\n\t/* the maximum dividend is 90999000/2, 0x02b6446c, this number is\n\t   also the most complex divisor. Hence, the dividend has,\n\t   assuming 32bit unsigned arithmetic, 6 clear bits on top, the\n\t   divisor 2 unused bits at the bottom. Also, the quotient is\n\t   always less than 1/2. Borrowed from VES1893.c, of course */\n\n\ttmp=srate<<6;\n\tBDRI=fclk>>2;\n\tratio=(tmp/BDRI);\n\n\ttmp=(tmp%BDRI)<<8;\n\tratio=(ratio<<8)+(tmp/BDRI);\n\n\ttmp=(tmp%BDRI)<<8;\n\tratio=(ratio<<8)+(tmp/BDRI);\n\n\ttmp=(tmp%BDRI)<<1;\n\tratio=(ratio<<1)+(tmp/BDRI);\n\n\tdprintk(\"srate= %d (range %d, up to %d)\\n\", srate,i,bands[i]);\n\tdprintk(\"fclk = %d\\n\", fclk);\n\tdprintk(\"ratio= %08x\\n\", ratio);\n\n\tcx24110_writereg(state, 0x1, (ratio>>16)&0xff);\n\tcx24110_writereg(state, 0x2, (ratio>>8)&0xff);\n\tcx24110_writereg(state, 0x3, (ratio)&0xff);\n\n\treturn 0;\n\n}",
        "static void put_cpu_partial(struct kmem_cache *s, struct slab *slab, int drain)\n{\n\tstruct slab *oldslab;\n\tstruct slab *slab_to_unfreeze = NULL;\n\tunsigned long flags;": "static void put_cpu_partial(struct kmem_cache *s, struct slab *slab, int drain)\n{\n\tstruct slab *oldslab;\n\tstruct slab *slab_to_unfreeze = NULL;\n\tunsigned long flags;\n\tint slabs = 0;\n\n\tlocal_lock_irqsave(&s->cpu_slab->lock, flags);\n\n\toldslab = this_cpu_read(s->cpu_slab->partial);\n\n\tif (oldslab) {\n\t\tif (drain && oldslab->slabs >= s->cpu_partial_slabs) {\n\t\t\t/*\n\t\t\t * Partial array is full. Move the existing set to the\n\t\t\t * per node partial list. Postpone the actual unfreezing\n\t\t\t * outside of the critical section.\n\t\t\t */\n\t\t\tslab_to_unfreeze = oldslab;\n\t\t\toldslab = NULL;\n\t\t} else {\n\t\t\tslabs = oldslab->slabs;\n\t\t}\n\t}\n\n\tslabs++;\n\n\tslab->slabs = slabs;\n\tslab->next = oldslab;\n\n\tthis_cpu_write(s->cpu_slab->partial, slab);\n\n\tlocal_unlock_irqrestore(&s->cpu_slab->lock, flags);\n\n\tif (slab_to_unfreeze) {\n\t\t__unfreeze_partials(s, slab_to_unfreeze);\n\t\tstat(s, CPU_PARTIAL_DRAIN);\n\t}\n}",
        "static int io_openat2(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct open_flags op;\n\tstruct file *file;\n\tbool resolve_nonblock, nonblock_set;": "static int io_openat2(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct open_flags op;\n\tstruct file *file;\n\tbool resolve_nonblock, nonblock_set;\n\tbool fixed = !!req->open.file_slot;\n\tint ret;\n\n\tret = build_open_flags(&req->open.how, &op);\n\tif (ret)\n\t\tgoto err;\n\tnonblock_set = op.open_flag & O_NONBLOCK;\n\tresolve_nonblock = req->open.how.resolve & RESOLVE_CACHED;\n\tif (issue_flags & IO_URING_F_NONBLOCK) {\n\t\t/*\n\t\t * Don't bother trying for O_TRUNC, O_CREAT, or O_TMPFILE open,\n\t\t * it'll always -EAGAIN\n\t\t */\n\t\tif (req->open.how.flags & (O_TRUNC | O_CREAT | O_TMPFILE))\n\t\t\treturn -EAGAIN;\n\t\top.lookup_flags |= LOOKUP_CACHED;\n\t\top.open_flag |= O_NONBLOCK;\n\t}\n\n\tif (!fixed) {\n\t\tret = __get_unused_fd_flags(req->open.how.flags, req->open.nofile);\n\t\tif (ret < 0)\n\t\t\tgoto err;\n\t}\n\n\tfile = do_filp_open(req->open.dfd, req->open.filename, &op);\n\tif (IS_ERR(file)) {\n\t\t/*\n\t\t * We could hang on to this 'fd' on retrying, but seems like\n\t\t * marginal gain for something that is now known to be a slower\n\t\t * path. So just put it, and we'll get a new one when we retry.\n\t\t */\n\t\tif (!fixed)\n\t\t\tput_unused_fd(ret);\n\n\t\tret = PTR_ERR(file);\n\t\t/* only retry if RESOLVE_CACHED wasn't already set by application */\n\t\tif (ret == -EAGAIN &&\n\t\t    (!resolve_nonblock && (issue_flags & IO_URING_F_NONBLOCK)))\n\t\t\treturn -EAGAIN;\n\t\tgoto err;\n\t}\n\n\tif ((issue_flags & IO_URING_F_NONBLOCK) && !nonblock_set)\n\t\tfile->f_flags &= ~O_NONBLOCK;\n\tfsnotify_open(file);\n\n\tif (!fixed)\n\t\tfd_install(ret, file);\n\telse\n\t\tret = io_fixed_fd_install(req, issue_flags, file,\n\t\t\t\t\t\treq->open.file_slot);\nerr:\n\tputname(req->open.filename);\n\treq->flags &= ~REQ_F_NEED_CLEANUP;\n\tif (ret < 0)\n\t\treq_set_fail(req);\n\t__io_req_complete(req, issue_flags, ret, 0);\n\treturn 0;\n}",
        "static void hisi_pcie_pmu_config_filter(struct perf_event *event)\n{\n\tstruct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);\n\tstruct hw_perf_event *hwc = &event->hw;\n\tu64 reg = HISI_PCIE_INIT_SET;": "static void hisi_pcie_pmu_config_filter(struct perf_event *event)\n{\n\tstruct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);\n\tstruct hw_perf_event *hwc = &event->hw;\n\tu64 reg = HISI_PCIE_INIT_SET;\n\tu64 port, trig_len, thr_len;\n\n\t/* Config HISI_PCIE_EVENT_CTRL according to event. */\n\treg |= FIELD_PREP(HISI_PCIE_EVENT_M, hisi_pcie_get_real_event(event));\n\n\t/* Config HISI_PCIE_EVENT_CTRL according to root port or EP device. */\n\tport = hisi_pcie_get_port(event);\n\tif (port)\n\t\treg |= FIELD_PREP(HISI_PCIE_TARGET_M, port);\n\telse\n\t\treg |= HISI_PCIE_TARGET_EN |\n\t\t       FIELD_PREP(HISI_PCIE_TARGET_M, hisi_pcie_get_bdf(event));\n\n\t/* Config HISI_PCIE_EVENT_CTRL according to trigger condition. */\n\ttrig_len = hisi_pcie_get_trig_len(event);\n\tif (trig_len) {\n\t\treg |= FIELD_PREP(HISI_PCIE_TRIG_M, trig_len);\n\t\treg |= FIELD_PREP(HISI_PCIE_TRIG_MODE_M, hisi_pcie_get_trig_mode(event));\n\t\treg |= HISI_PCIE_TRIG_EN;\n\t}\n\n\t/* Config HISI_PCIE_EVENT_CTRL according to threshold condition. */\n\tthr_len = hisi_pcie_get_thr_len(event);\n\tif (thr_len) {\n\t\treg |= FIELD_PREP(HISI_PCIE_THR_M, thr_len);\n\t\treg |= FIELD_PREP(HISI_PCIE_THR_MODE_M, hisi_pcie_get_thr_mode(event));\n\t\treg |= HISI_PCIE_THR_EN;\n\t}\n\n\thisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg);\n}",
        "static void three_out_pipe(struct adapter *adapter, bool wifi_cfg)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);\n\n\tif (wifi_cfg) {/* for WMM */": "static void three_out_pipe(struct adapter *adapter, bool wifi_cfg)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);\n\n\tif (wifi_cfg) {/* for WMM */\n\t\t/* BK, BE, VI, VO, BCN,\tCMD, MGT, HIGH, HCCA */\n\t\t/*  1,\t2,  1,  0,   0,   0,   0,    0,    0}; */\n\t\t/* 0:H, 1:N, 2:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\n\t} else {/* typical setting */\n\t\t/* BK, BE, VI, VO, BCN,\tCMD, MGT, HIGH, HCCA */\n\t\t/*  2,  2,  1,  0,   0,   0,   0,    0,    0}; */\n\t\t/* 0:H, 1:N, 2:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\t}\n}",
        "static int cobalt_start_streaming(struct vb2_queue *q, unsigned int count)\n{\n\tstruct cobalt_stream *s = q->drv_priv;\n\tstruct cobalt *cobalt = s->cobalt;\n\tstruct m00233_video_measure_regmap __iomem *vmr;": "static int cobalt_start_streaming(struct vb2_queue *q, unsigned int count)\n{\n\tstruct cobalt_stream *s = q->drv_priv;\n\tstruct cobalt *cobalt = s->cobalt;\n\tstruct m00233_video_measure_regmap __iomem *vmr;\n\tstruct m00473_freewheel_regmap __iomem *fw;\n\tstruct m00479_clk_loss_detector_regmap __iomem *clkloss;\n\tint rx = s->video_channel;\n\tstruct m00389_cvi_regmap __iomem *cvi = COBALT_CVI(cobalt, rx);\n\tstruct m00460_evcnt_regmap __iomem *evcnt = COBALT_CVI_EVCNT(cobalt, rx);\n\tstruct v4l2_bt_timings *bt = &s->timings.bt;\n\tu64 tot_size;\n\tu32 clk_freq;\n\n\tif (s->is_audio)\n\t\tgoto done;\n\tif (s->is_output) {\n\t\ts->unstable_frame = false;\n\t\tcobalt_enable_output(s);\n\t\tgoto done;\n\t}\n\n\tcobalt_enable_input(s);\n\n\tfw = COBALT_CVI_FREEWHEEL(cobalt, rx);\n\tvmr = COBALT_CVI_VMR(cobalt, rx);\n\tclkloss = COBALT_CVI_CLK_LOSS(cobalt, rx);\n\n\tiowrite32(M00460_CONTROL_BITMAP_CLEAR_MSK, &evcnt->control);\n\tiowrite32(M00460_CONTROL_BITMAP_ENABLE_MSK, &evcnt->control);\n\tiowrite32(bt->width, &cvi->frame_width);\n\tiowrite32(bt->height, &cvi->frame_height);\n\ttot_size = V4L2_DV_BT_FRAME_WIDTH(bt) * V4L2_DV_BT_FRAME_HEIGHT(bt);\n\tiowrite32(div_u64((u64)V4L2_DV_BT_FRAME_WIDTH(bt) * COBALT_CLK * 4,\n\t\t\t  bt->pixelclock), &vmr->hsync_timeout_val);\n\tiowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK, &vmr->control);\n\tclk_freq = ioread32(&fw->clk_freq);\n\tiowrite32(clk_freq / 1000000, &clkloss->ref_clk_cnt_val);\n\t/* The lower bound for the clock frequency is 0.5% lower as is\n\t * allowed by the spec */\n\tiowrite32(div_u64(bt->pixelclock * 995, 1000000000),\n\t\t  &clkloss->test_clk_cnt_val);\n\t/* will be enabled after the first frame has been received */\n\tiowrite32(bt->width * bt->height, &fw->active_length);\n\tiowrite32(div_u64((u64)clk_freq * tot_size, bt->pixelclock),\n\t\t  &fw->total_length);\n\tiowrite32(M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_MSK |\n\t\t  M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_MSK,\n\t\t  &vmr->irq_triggers);\n\tiowrite32(0, &cvi->control);\n\tiowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK, &vmr->control);\n\n\tiowrite32(0xff, &fw->output_color);\n\tiowrite32(M00479_CTRL_BITMAP_ENABLE_MSK, &clkloss->ctrl);\n\tiowrite32(M00473_CTRL_BITMAP_ENABLE_MSK |\n\t\t  M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_MSK, &fw->ctrl);\n\ts->unstable_frame = true;\n\ts->enable_freewheel = false;\n\ts->enable_cvi = false;\n\ts->skip_first_frames = 0;\n\ndone:\n\ts->sequence = 0;\n\tcobalt_dma_start_streaming(s);\n\treturn 0;\n}",
        "static bool mem_cgroup_under_move(struct mem_cgroup *memcg)\n{\n\tstruct mem_cgroup *from;\n\tstruct mem_cgroup *to;\n\tbool ret = false;": "static bool mem_cgroup_under_move(struct mem_cgroup *memcg)\n{\n\tstruct mem_cgroup *from;\n\tstruct mem_cgroup *to;\n\tbool ret = false;\n\t/*\n\t * Unlike task_move routines, we access mc.to, mc.from not under\n\t * mutual exclusion by cgroup_mutex. Here, we take spinlock instead.\n\t */\n\tspin_lock(&mc.lock);\n\tfrom = mc.from;\n\tto = mc.to;\n\tif (!from)\n\t\tgoto unlock;\n\n\tret = mem_cgroup_is_descendant(from, memcg) ||\n\t\tmem_cgroup_is_descendant(to, memcg);\nunlock:\n\tspin_unlock(&mc.lock);\n\treturn ret;\n}",
        "static void do_balance_runtime(struct rt_rq *rt_rq)\n{\n\tstruct rt_bandwidth *rt_b = sched_rt_bandwidth(rt_rq);\n\tstruct root_domain *rd = rq_of_rt_rq(rt_rq)->rd;\n\tint i, weight;": "static void do_balance_runtime(struct rt_rq *rt_rq)\n{\n\tstruct rt_bandwidth *rt_b = sched_rt_bandwidth(rt_rq);\n\tstruct root_domain *rd = rq_of_rt_rq(rt_rq)->rd;\n\tint i, weight;\n\tu64 rt_period;\n\n\tweight = cpumask_weight(rd->span);\n\n\traw_spin_lock(&rt_b->rt_runtime_lock);\n\trt_period = ktime_to_ns(rt_b->rt_period);\n\tfor_each_cpu(i, rd->span) {\n\t\tstruct rt_rq *iter = sched_rt_period_rt_rq(rt_b, i);\n\t\ts64 diff;\n\n\t\tif (iter == rt_rq)\n\t\t\tcontinue;\n\n\t\traw_spin_lock(&iter->rt_runtime_lock);\n\t\t/*\n\t\t * Either all rqs have inf runtime and there's nothing to steal\n\t\t * or __disable_runtime() below sets a specific rq to inf to\n\t\t * indicate its been disabled and disallow stealing.\n\t\t */\n\t\tif (iter->rt_runtime == RUNTIME_INF)\n\t\t\tgoto next;\n\n\t\t/*\n\t\t * From runqueues with spare time, take 1/n part of their\n\t\t * spare time, but no more than our period.\n\t\t */\n\t\tdiff = iter->rt_runtime - iter->rt_time;\n\t\tif (diff > 0) {\n\t\t\tdiff = div_u64((u64)diff, weight);\n\t\t\tif (rt_rq->rt_runtime + diff > rt_period)\n\t\t\t\tdiff = rt_period - rt_rq->rt_runtime;\n\t\t\titer->rt_runtime -= diff;\n\t\t\trt_rq->rt_runtime += diff;\n\t\t\tif (rt_rq->rt_runtime == rt_period) {\n\t\t\t\traw_spin_unlock(&iter->rt_runtime_lock);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\nnext:\n\t\traw_spin_unlock(&iter->rt_runtime_lock);\n\t}\n\traw_spin_unlock(&rt_b->rt_runtime_lock);\n}",
        "static void debug_print_rx_mipi_port_state(mipi_port_state_t *state)\n{\n\tint i;\n\tunsigned int bits, infos;\n": "static void debug_print_rx_mipi_port_state(mipi_port_state_t *state)\n{\n\tint i;\n\tunsigned int bits, infos;\n\n\tassert(state);\n\n\tbits = state->irq_status;\n\tinfos = ia_css_isys_rx_translate_irq_infos(bits);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: (irq reg = 0x%X)\\n\",\n\t\t\t    \"receiver errors\", bits);\n\n\tif (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tbuffer overrun\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tstart-of-transmission error\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tstart-of-transmission sync error\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tcontrol error\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\t2 or more ECC errors\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tCRC mismatch\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tunknown error\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tframe sync error\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tframe data error\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tdata timeout\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tunknown escape command entry\\n\");\n\tif (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)\n\t\tia_css_debug_dtrace(2, \"\\t\\t\\tline sync error\\n\");\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"device_ready\", state->device_ready);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"irq_status\", state->irq_status);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"irq_enable\", state->irq_enable);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"timeout_count\", state->timeout_count);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"init_count\", state->init_count);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"raw16_18\", state->raw16_18);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"sync_count\", state->sync_count);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"rx_count\", state->rx_count);\n\n\tfor (i = 0; i < MIPI_4LANE_CFG; i++) {\n\t\tia_css_debug_dtrace(2, \"\\t\\t%-32s%d%-32s: %d\\n\",\n\t\t\t\t    \"lane_sync_count[\", i, \"]\",\n\t\t\t\t    state->lane_sync_count[i]);\n\t}\n\n\tfor (i = 0; i < MIPI_4LANE_CFG; i++) {\n\t\tia_css_debug_dtrace(2, \"\\t\\t%-32s%d%-32s: %d\\n\",\n\t\t\t\t    \"lane_rx_count[\", i, \"]\",\n\t\t\t\t    state->lane_rx_count[i]);\n\t}\n\n\treturn;\n}",
        "static int reconnect_dfs_server(struct TCP_Server_Info *server)\n{\n\tint rc = 0;\n\tconst char *refpath = server->current_fullpath + 1;\n\tstruct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);": "static int reconnect_dfs_server(struct TCP_Server_Info *server)\n{\n\tint rc = 0;\n\tconst char *refpath = server->current_fullpath + 1;\n\tstruct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);\n\tstruct dfs_cache_tgt_iterator *target_hint = NULL;\n\tint num_targets = 0;\n\n\t/*\n\t * Determine the number of dfs targets the referral path in @cifs_sb resolves to.\n\t *\n\t * smb2_reconnect() needs to know how long it should wait based upon the number of dfs\n\t * targets (server->nr_targets).  It's also possible that the cached referral was cleared\n\t * through /proc/fs/cifs/dfscache or the target list is empty due to server settings after\n\t * refreshing the referral, so, in this case, default it to 1.\n\t */\n\tif (!dfs_cache_noreq_find(refpath, NULL, &tl))\n\t\tnum_targets = dfs_cache_get_nr_tgts(&tl);\n\tif (!num_targets)\n\t\tnum_targets = 1;\n\n\tif (!cifs_tcp_ses_needs_reconnect(server, num_targets))\n\t\treturn 0;\n\n\t/*\n\t * Unconditionally mark all sessions & tcons for reconnect as we might be connecting to a\n\t * different server or share during failover.  It could be improved by adding some logic to\n\t * only do that in case it connects to a different server or share, though.\n\t */\n\tcifs_mark_tcp_ses_conns_for_reconnect(server, true);\n\n\tcifs_abort_connection(server);\n\n\tdo {\n\t\ttry_to_freeze();\n\t\tcifs_server_lock(server);\n\n\t\trc = reconnect_target_unlocked(server, &tl, &target_hint);\n\t\tif (rc) {\n\t\t\t/* Failed to reconnect socket */\n\t\t\tcifs_server_unlock(server);\n\t\t\tcifs_dbg(FYI, \"%s: reconnect error %d\\n\", __func__, rc);\n\t\t\tmsleep(3000);\n\t\t\tcontinue;\n\t\t}\n\t\t/*\n\t\t * Socket was created.  Update tcp session status to CifsNeedNegotiate so that a\n\t\t * process waiting for reconnect will know it needs to re-establish session and tcon\n\t\t * through the reconnected target server.\n\t\t */\n\t\tatomic_inc(&tcpSesReconnectCount);\n\t\tset_credits(server, 1);\n\t\tspin_lock(&cifs_tcp_ses_lock);\n\t\tif (server->tcpStatus != CifsExiting)\n\t\t\tserver->tcpStatus = CifsNeedNegotiate;\n\t\tspin_unlock(&cifs_tcp_ses_lock);\n\t\tcifs_swn_reset_server_dstaddr(server);\n\t\tcifs_server_unlock(server);\n\t\tmod_delayed_work(cifsiod_wq, &server->reconnect, 0);\n\t} while (server->tcpStatus == CifsNeedReconnect);\n\n\tif (target_hint)\n\t\tdfs_cache_noreq_update_tgthint(refpath, target_hint);\n\n\tdfs_cache_free_tgts(&tl);\n\n\t/* Need to set up echo worker again once connection has been established */\n\tspin_lock(&cifs_tcp_ses_lock);\n\tif (server->tcpStatus == CifsNeedNegotiate)\n\t\tmod_delayed_work(cifsiod_wq, &server->echo, 0);\n\n\tspin_unlock(&cifs_tcp_ses_lock);\n\n\twake_up(&server->response_q);\n\treturn rc;\n}",
        "static void t7xx_dpmaif_register_pcie_irq(struct dpmaif_ctrl *dpmaif_ctrl)\n{\n\tstruct t7xx_pci_dev *t7xx_dev = dpmaif_ctrl->t7xx_dev;\n\tstruct dpmaif_isr_para *isr_para;\n\tenum t7xx_int int_type;": "static void t7xx_dpmaif_register_pcie_irq(struct dpmaif_ctrl *dpmaif_ctrl)\n{\n\tstruct t7xx_pci_dev *t7xx_dev = dpmaif_ctrl->t7xx_dev;\n\tstruct dpmaif_isr_para *isr_para;\n\tenum t7xx_int int_type;\n\tint i;\n\n\tt7xx_dpmaif_isr_parameter_init(dpmaif_ctrl);\n\n\tfor (i = 0; i < DPMAIF_RXQ_NUM; i++) {\n\t\tisr_para = &dpmaif_ctrl->isr_para[i];\n\t\tint_type = isr_para->pcie_int;\n\t\tt7xx_pcie_mac_clear_int(t7xx_dev, int_type);\n\n\t\tt7xx_dev->intr_handler[int_type] = t7xx_dpmaif_isr_handler;\n\t\tt7xx_dev->intr_thread[int_type] = NULL;\n\t\tt7xx_dev->callback_param[int_type] = isr_para;\n\n\t\tt7xx_pcie_mac_clear_int_status(t7xx_dev, int_type);\n\t\tt7xx_pcie_mac_set_int(t7xx_dev, int_type);\n\t}\n}",
        "static void quirk_ich4_lpc_acpi(struct pci_dev *dev)\n{\n\tu8 enable;\n\n\t/*": "static void quirk_ich4_lpc_acpi(struct pci_dev *dev)\n{\n\tu8 enable;\n\n\t/*\n\t * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict\n\t * with low legacy (and fixed) ports. We don't know the decoding\n\t * priority and can't tell whether the legacy device or the one created\n\t * here is really at that address.  This happens on boards with broken\n\t * BIOSes.\n\t */\n\tpci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);\n\tif (enable & ICH4_ACPI_EN)\n\t\tquirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,\n\t\t\t\t \"ICH4 ACPI/GPIO/TCO\");\n\n\tpci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);\n\tif (enable & ICH4_GPIO_EN)\n\t\tquirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,\n\t\t\t\t\"ICH4 GPIO\");\n}",
        "static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct kcqe kcqe;\n\tstruct kcqe *cqes[1];": "static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct kcqe kcqe;\n\tstruct kcqe *cqes[1];\n\tu32 cid;\n\tu32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);\n\tu32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;\n\tu32 kcqe_op;\n\tint ulp_type;\n\n\tcid = kwqe->kwqe_info0;\n\tmemset(&kcqe, 0, sizeof(kcqe));\n\n\tif (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {\n\t\tu32 l5_cid = 0;\n\n\t\tulp_type = CNIC_ULP_FCOE;\n\t\tif (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {\n\t\t\tstruct fcoe_kwqe_conn_enable_disable *req;\n\n\t\t\treq = (struct fcoe_kwqe_conn_enable_disable *) kwqe;\n\t\t\tkcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;\n\t\t\tcid = req->context_id;\n\t\t\tl5_cid = req->conn_id;\n\t\t} else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {\n\t\t\tkcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;\n\t\t} else {\n\t\t\treturn;\n\t\t}\n\t\tkcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;\n\t\tkcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;\n\t\tkcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;\n\t\tkcqe.kcqe_info2 = cid;\n\t\tkcqe.kcqe_info0 = l5_cid;\n\n\t} else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {\n\t\tulp_type = CNIC_ULP_ISCSI;\n\t\tif (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)\n\t\t\tcid = kwqe->kwqe_info1;\n\n\t\tkcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;\n\t\tkcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;\n\t\tkcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;\n\t\tkcqe.kcqe_info2 = cid;\n\t\tcnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);\n\n\t} else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {\n\t\tstruct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;\n\n\t\tulp_type = CNIC_ULP_L4;\n\t\tif (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)\n\t\t\tkcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;\n\t\telse if (opcode == L4_KWQE_OPCODE_VALUE_RESET)\n\t\t\tkcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;\n\t\telse if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)\n\t\t\tkcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;\n\t\telse\n\t\t\treturn;\n\n\t\tkcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |\n\t\t\t\t    KCQE_FLAGS_LAYER_MASK_L4;\n\t\tl4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;\n\t\tl4kcqe->cid = cid;\n\t\tcnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);\n\t} else {\n\t\treturn;\n\t}\n\n\tcqes[0] = &kcqe;\n\tcnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);\n}",
        "static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)\n{\n\tint timeout = 5000; /* 3ms according to i.MX28 Ref Manual */\n\t/*\n\t * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010": "static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)\n{\n\tint timeout = 5000; /* 3ms according to i.MX28 Ref Manual */\n\t/*\n\t * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010\n\t * states:\n\t * | The order in which registers are updated is\n\t * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.\n\t * | (This list is in bitfield order, from LSB to MSB, as they would\n\t * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT\n\t * | register. For example, the Seconds register corresponds to\n\t * | STALE_REGS or NEW_REGS containing 0x80.)\n\t */\n\tdo {\n\t\tif (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &\n\t\t\t\t(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))\n\t\t\treturn 0;\n\t\tudelay(1);\n\t} while (--timeout > 0);\n\treturn (readl(rtc_data->io + STMP3XXX_RTC_STAT) &\n\t\t(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;\n}",
        "static bool __wake_q_add(struct wake_q_head *head, struct task_struct *task)\n{\n\tstruct wake_q_node *node = &task->wake_q;\n\n\t/*": "static bool __wake_q_add(struct wake_q_head *head, struct task_struct *task)\n{\n\tstruct wake_q_node *node = &task->wake_q;\n\n\t/*\n\t * Atomically grab the task, if ->wake_q is !nil already it means\n\t * it's already queued (either by us or someone else) and will get the\n\t * wakeup due to that.\n\t *\n\t * In order to ensure that a pending wakeup will observe our pending\n\t * state, even in the failed case, an explicit smp_mb() must be used.\n\t */\n\tsmp_mb__before_atomic();\n\tif (unlikely(cmpxchg_relaxed(&node->next, NULL, WAKE_Q_TAIL)))\n\t\treturn false;\n\n\t/*\n\t * The head is context local, there can be no concurrency.\n\t */\n\t*head->lastp = node;\n\thead->lastp = &node->next;\n\treturn true;\n}",
        "static int io_arm_poll_handler(struct io_kiocb *req, unsigned issue_flags)\n{\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct async_poll *apoll;": "static int io_arm_poll_handler(struct io_kiocb *req, unsigned issue_flags)\n{\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct async_poll *apoll;\n\tstruct io_poll_table ipt;\n\t__poll_t mask = POLLPRI | POLLERR;\n\tint ret;\n\n\tif (!def->pollin && !def->pollout)\n\t\treturn IO_APOLL_ABORTED;\n\tif (!file_can_poll(req->file))\n\t\treturn IO_APOLL_ABORTED;\n\tif ((req->flags & (REQ_F_POLLED|REQ_F_PARTIAL_IO)) == REQ_F_POLLED)\n\t\treturn IO_APOLL_ABORTED;\n\tif (!(req->flags & REQ_F_APOLL_MULTISHOT))\n\t\tmask |= EPOLLONESHOT;\n\n\tif (def->pollin) {\n\t\tmask |= EPOLLIN | EPOLLRDNORM;\n\n\t\t/* If reading from MSG_ERRQUEUE using recvmsg, ignore POLLIN */\n\t\tif ((req->opcode == IORING_OP_RECVMSG) &&\n\t\t    (req->sr_msg.msg_flags & MSG_ERRQUEUE))\n\t\t\tmask &= ~EPOLLIN;\n\t} else {\n\t\tmask |= EPOLLOUT | EPOLLWRNORM;\n\t}\n\tif (def->poll_exclusive)\n\t\tmask |= EPOLLEXCLUSIVE;\n\tif (req->flags & REQ_F_POLLED) {\n\t\tapoll = req->apoll;\n\t} else if (!(issue_flags & IO_URING_F_UNLOCKED) &&\n\t\t   !list_empty(&ctx->apoll_cache)) {\n\t\tapoll = list_first_entry(&ctx->apoll_cache, struct async_poll,\n\t\t\t\t\t\tpoll.wait.entry);\n\t\tlist_del_init(&apoll->poll.wait.entry);\n\t} else {\n\t\tapoll = kmalloc(sizeof(*apoll), GFP_ATOMIC);\n\t\tif (unlikely(!apoll))\n\t\t\treturn IO_APOLL_ABORTED;\n\t}\n\tapoll->double_poll = NULL;\n\treq->apoll = apoll;\n\treq->flags |= REQ_F_POLLED;\n\tipt.pt._qproc = io_async_queue_proc;\n\n\tio_kbuf_recycle(req, issue_flags);\n\n\tret = __io_arm_poll_handler(req, &apoll->poll, &ipt, mask);\n\tif (ret || ipt.error)\n\t\treturn ret ? IO_APOLL_READY : IO_APOLL_ABORTED;\n\n\ttrace_io_uring_poll_arm(ctx, req, req->cqe.user_data, req->opcode,\n\t\t\t\tmask, apoll->poll.events);\n\treturn IO_APOLL_OK;\n}",
        "static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)\n{\n\tu8 val;\n\n\t/*": "static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)\n{\n\tu8 val;\n\n\t/*\n\t * override HW issue: I2C may fail to supply stop condition in Master\n\t * Write operation.\n\t * Need to delay at least 5 us from the last int, before issueing a stop\n\t */\n\tudelay(10); /* function called from interrupt, can't sleep */\n\tval = ioread8(bus->reg + NPCM_I2CCTL1);\n\tval &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);\n\tval |= NPCM_I2CCTL1_STOP;\n\tiowrite8(val, bus->reg + NPCM_I2CCTL1);\n\n\tif (!bus->fifo_use)\n\t\treturn;\n\n\tnpcm_i2c_select_bank(bus, I2C_BANK_1);\n\n\tif (bus->operation == I2C_READ_OPER)\n\t\tnpcm_i2c_clear_rx_fifo(bus);\n\telse\n\t\tnpcm_i2c_clear_tx_fifo(bus);\n\tnpcm_i2c_clear_fifo_int(bus);\n\tiowrite8(0, bus->reg + NPCM_I2CTXF_CTL);\n}",
        "static void cx0342_6810_init(struct gspca_dev *gspca_dev)\n{\n\tstatic const struct cmd reg_init_1[] = {\n\t\t{TP6800_R2F_TIMING_CFG, 0x2f},\n\t\t{0x25, 0x02},": "static void cx0342_6810_init(struct gspca_dev *gspca_dev)\n{\n\tstatic const struct cmd reg_init_1[] = {\n\t\t{TP6800_R2F_TIMING_CFG, 0x2f},\n\t\t{0x25, 0x02},\n\t\t{TP6800_R21_ENDP_1_CTL, 0x00},\n\t\t{TP6800_R3F_FRAME_RATE, 0x80},\n\t\t{TP6800_R2F_TIMING_CFG, 0x2f},\n\t\t{TP6800_R18_GPIO_DATA, 0xe1},\n\t\t{TP6800_R18_GPIO_DATA, 0xc1},\n\t\t{TP6800_R18_GPIO_DATA, 0xe1},\n\t\t{TP6800_R11_SIF_CONTROL, 0x00},\n\t};\n\tstatic const struct cmd reg_init_2[] = {\n\t\t{TP6800_R78_FORMAT, 0x48},\n\t\t{TP6800_R11_SIF_CONTROL, 0x00},\n\t};\n\tstatic const struct cmd sensor_init[] = {\n\t\t{CX0342_OUTPUT_CTRL, 0x07},\n\t\t{CX0342_BYPASS_MODE, 0x58},\n\t\t{CX0342_GPXLTHD_L, 0x28},\n\t\t{CX0342_RBPXLTHD_L, 0x28},\n\t\t{CX0342_PLANETHD_L, 0x50},\n\t\t{CX0342_PLANETHD_H, 0x03},\n\t\t{CX0342_RB_GAP_L, 0xff},\n\t\t{CX0342_RB_GAP_H, 0x07},\n\t\t{CX0342_G_GAP_L, 0xff},\n\t\t{CX0342_G_GAP_H, 0x07},\n\t\t{CX0342_RST_OVERFLOW_L, 0x5c},\n\t\t{CX0342_RST_OVERFLOW_H, 0x01},\n\t\t{CX0342_DATA_OVERFLOW_L, 0xfc},\n\t\t{CX0342_DATA_OVERFLOW_H, 0x03},\n\t\t{CX0342_DATA_UNDERFLOW_L, 0x00},\n\t\t{CX0342_DATA_UNDERFLOW_H, 0x00},\n\t\t{CX0342_SYS_CTRL_0, 0x40},\n\t\t{CX0342_GLOBAL_GAIN, 0x01},\n\t\t{CX0342_CLOCK_GEN, 0x00},\n\t\t{CX0342_SYS_CTRL_0, 0x02},\n\t\t{CX0342_IDLE_CTRL, 0x05},\n\t\t{CX0342_ADCGN, 0x00},\n\t\t{CX0342_ADC_CTL, 0x00},\n\t\t{CX0342_LVRST_BLBIAS, 0x01},\n\t\t{CX0342_VTHSEL, 0x0b},\n\t\t{CX0342_RAMP_RIV, 0x0b},\n\t\t{CX0342_LDOSEL, 0x07},\n\t\t{CX0342_SPV_VALUE_L, 0x40},\n\t\t{CX0342_SPV_VALUE_H, 0x02},\n\n\t\t{CX0342_AUTO_ADC_CALIB, 0x81},\n\t\t{CX0342_TIMING_EN, 0x01},\n\t};\n\n\treg_w_buf(gspca_dev, reg_init_1, ARRAY_SIZE(reg_init_1));\n\treg_w_buf(gspca_dev, tp6810_cx_init_common,\n\t\t\tARRAY_SIZE(tp6810_cx_init_common));\n\treg_w_buf(gspca_dev, reg_init_2, ARRAY_SIZE(reg_init_2));\n\n\treg_w(gspca_dev, TP6800_R12_SIF_ADDR_S, 0x20);\t/* cx0342 I2C addr */\n\ti2c_w_buf(gspca_dev, sensor_init, ARRAY_SIZE(sensor_init));\n\ti2c_w_buf(gspca_dev, cx0342_timing_seq, ARRAY_SIZE(cx0342_timing_seq));\n}",
        "static void fscache_perform_lookup(struct fscache_cookie *cookie)\n{\n\tenum fscache_access_trace trace = fscache_access_lookup_cookie_end_failed;\n\tbool need_withdraw = false;\n": "static void fscache_perform_lookup(struct fscache_cookie *cookie)\n{\n\tenum fscache_access_trace trace = fscache_access_lookup_cookie_end_failed;\n\tbool need_withdraw = false;\n\n\t_enter(\"\");\n\n\tif (!cookie->volume->cache_priv) {\n\t\tfscache_create_volume(cookie->volume, true);\n\t\tif (!cookie->volume->cache_priv) {\n\t\t\tfscache_set_cookie_state(cookie, FSCACHE_COOKIE_STATE_QUIESCENT);\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (!cookie->volume->cache->ops->lookup_cookie(cookie)) {\n\t\tif (cookie->state != FSCACHE_COOKIE_STATE_FAILED)\n\t\t\tfscache_set_cookie_state(cookie, FSCACHE_COOKIE_STATE_QUIESCENT);\n\t\tneed_withdraw = true;\n\t\t_leave(\" [fail]\");\n\t\tgoto out;\n\t}\n\n\tfscache_see_cookie(cookie, fscache_cookie_see_active);\n\tfscache_set_cookie_state(cookie, FSCACHE_COOKIE_STATE_ACTIVE);\n\ttrace = fscache_access_lookup_cookie_end;\n\nout:\n\tfscache_end_cookie_access(cookie, trace);\n\tif (need_withdraw)\n\t\tfscache_withdraw_cookie(cookie);\n\tfscache_end_volume_access(cookie->volume, cookie, trace);\n}",
        "static int m_can_check_core_release(struct m_can_classdev *cdev)\n{\n\tu32 crel_reg;\n\tu8 rel;\n\tu8 step;": "static int m_can_check_core_release(struct m_can_classdev *cdev)\n{\n\tu32 crel_reg;\n\tu8 rel;\n\tu8 step;\n\tint res;\n\n\t/* Read Core Release Version and split into version number\n\t * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;\n\t */\n\tcrel_reg = m_can_read(cdev, M_CAN_CREL);\n\trel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);\n\tstep = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);\n\n\tif (rel == 3) {\n\t\t/* M_CAN v3.x.y: create return value */\n\t\tres = 30 + step;\n\t} else {\n\t\t/* Unsupported M_CAN version */\n\t\tres = 0;\n\t}\n\n\treturn res;\n}",
        "static void ep_poll_safewake(struct eventpoll *ep, struct epitem *epi)\n{\n\tstruct eventpoll *ep_src;\n\tunsigned long flags;\n\tu8 nests = 0;": "static void ep_poll_safewake(struct eventpoll *ep, struct epitem *epi)\n{\n\tstruct eventpoll *ep_src;\n\tunsigned long flags;\n\tu8 nests = 0;\n\n\t/*\n\t * To set the subclass or nesting level for spin_lock_irqsave_nested()\n\t * it might be natural to create a per-cpu nest count. However, since\n\t * we can recurse on ep->poll_wait.lock, and a non-raw spinlock can\n\t * schedule() in the -rt kernel, the per-cpu variable are no longer\n\t * protected. Thus, we are introducing a per eventpoll nest field.\n\t * If we are not being call from ep_poll_callback(), epi is NULL and\n\t * we are at the first level of nesting, 0. Otherwise, we are being\n\t * called from ep_poll_callback() and if a previous wakeup source is\n\t * not an epoll file itself, we are at depth 1 since the wakeup source\n\t * is depth 0. If the wakeup source is a previous epoll file in the\n\t * wakeup chain then we use its nests value and record ours as\n\t * nests + 1. The previous epoll file nests value is stable since its\n\t * already holding its own poll_wait.lock.\n\t */\n\tif (epi) {\n\t\tif ((is_file_epoll(epi->ffd.file))) {\n\t\t\tep_src = epi->ffd.file->private_data;\n\t\t\tnests = ep_src->nests;\n\t\t} else {\n\t\t\tnests = 1;\n\t\t}\n\t}\n\tspin_lock_irqsave_nested(&ep->poll_wait.lock, flags, nests);\n\tep->nests = nests + 1;\n\twake_up_locked_poll(&ep->poll_wait, EPOLLIN);\n\tep->nests = 0;\n\tspin_unlock_irqrestore(&ep->poll_wait.lock, flags);\n}",
        "static int rtl2831u_read_config(struct dvb_usb_device *d)\n{\n\tstruct rtl28xxu_dev *dev = d_to_priv(d);\n\tint ret;\n\tu8 buf[1];": "static int rtl2831u_read_config(struct dvb_usb_device *d)\n{\n\tstruct rtl28xxu_dev *dev = d_to_priv(d);\n\tint ret;\n\tu8 buf[1];\n\t/* open RTL2831U/RTL2830 I2C gate */\n\tstruct rtl28xxu_req req_gate_open = {0x0120, 0x0011, 0x0001, \"\\x08\"};\n\t/* tuner probes */\n\tstruct rtl28xxu_req req_mt2060 = {0x00c0, CMD_I2C_RD, 1, buf};\n\tstruct rtl28xxu_req req_qt1010 = {0x0fc4, CMD_I2C_RD, 1, buf};\n\n\tdev_dbg(&d->intf->dev, \"\\n\");\n\n\t/*\n\t * RTL2831U GPIOs\n\t * =========================================================\n\t * GPIO0 | tuner#0 | 0 off | 1 on  | MXL5005S (?)\n\t * GPIO2 | LED     | 0 off | 1 on  |\n\t * GPIO4 | tuner#1 | 0 on  | 1 off | MT2060\n\t */\n\n\t/* GPIO direction */\n\tret = rtl28xxu_wr_reg(d, SYS_GPIO_DIR, 0x0a);\n\tif (ret)\n\t\tgoto err;\n\n\t/* enable as output GPIO0, GPIO2, GPIO4 */\n\tret = rtl28xxu_wr_reg(d, SYS_GPIO_OUT_EN, 0x15);\n\tif (ret)\n\t\tgoto err;\n\n\t/*\n\t * Probe used tuner. We need to know used tuner before demod attach\n\t * since there is some demod params needed to set according to tuner.\n\t */\n\n\t/* demod needs some time to wake up */\n\tmsleep(20);\n\n\tdev->tuner_name = \"NONE\";\n\n\t/* open demod I2C gate */\n\tret = rtl28xxu_ctrl_msg(d, &req_gate_open);\n\tif (ret)\n\t\tgoto err;\n\n\t/* check QT1010 ID(?) register; reg=0f val=2c */\n\tret = rtl28xxu_ctrl_msg(d, &req_qt1010);\n\tif (ret == 0 && buf[0] == 0x2c) {\n\t\tdev->tuner = TUNER_RTL2830_QT1010;\n\t\tdev->tuner_name = \"QT1010\";\n\t\tgoto found;\n\t}\n\n\t/* open demod I2C gate */\n\tret = rtl28xxu_ctrl_msg(d, &req_gate_open);\n\tif (ret)\n\t\tgoto err;\n\n\t/* check MT2060 ID register; reg=00 val=63 */\n\tret = rtl28xxu_ctrl_msg(d, &req_mt2060);\n\tif (ret == 0 && buf[0] == 0x63) {\n\t\tdev->tuner = TUNER_RTL2830_MT2060;\n\t\tdev->tuner_name = \"MT2060\";\n\t\tgoto found;\n\t}\n\n\t/* assume MXL5005S */\n\tdev->tuner = TUNER_RTL2830_MXL5005S;\n\tdev->tuner_name = \"MXL5005S\";\n\tgoto found;\n\nfound:\n\tdev_dbg(&d->intf->dev, \"tuner=%s\\n\", dev->tuner_name);\n\n\treturn 0;\nerr:\n\tdev_dbg(&d->intf->dev, \"failed=%d\\n\", ret);\n\treturn ret;\n}",
        "static void llc_shdlc_reset_t2(struct llc_shdlc *shdlc, int y_nr)\n{\n\tstruct sk_buff *skb;\n\tint dnr = shdlc->dnr;\t/* MUST initially be < y_nr */\n": "static void llc_shdlc_reset_t2(struct llc_shdlc *shdlc, int y_nr)\n{\n\tstruct sk_buff *skb;\n\tint dnr = shdlc->dnr;\t/* MUST initially be < y_nr */\n\n\tpr_debug(\"release ack pending up to frame %d excluded\\n\", y_nr);\n\n\twhile (dnr != y_nr) {\n\t\tpr_debug(\"release ack pending frame %d\\n\", dnr);\n\n\t\tskb = skb_dequeue(&shdlc->ack_pending_q);\n\t\tkfree_skb(skb);\n\n\t\tdnr = (dnr + 1) % 8;\n\t}\n\n\tif (skb_queue_empty(&shdlc->ack_pending_q)) {\n\t\tif (shdlc->t2_active) {\n\t\t\tdel_timer_sync(&shdlc->t2_timer);\n\t\t\tshdlc->t2_active = false;\n\n\t\t\tpr_debug(\"All sent frames acked. Stopped T2(retransmit)\\n\");\n\t\t}\n\t} else {\n\t\tskb = skb_peek(&shdlc->ack_pending_q);\n\n\t\tmod_timer(&shdlc->t2_timer, *(unsigned long *)skb->cb +\n\t\t\t  msecs_to_jiffies(SHDLC_T2_VALUE_MS));\n\t\tshdlc->t2_active = true;\n\n\t\tpr_debug(\"Start T2(retransmit) for remaining unacked sent frames\\n\");\n\t}\n}",
        "static int create_host_video_pipeline(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_pipeline_stage_desc stage_desc;\n\tstruct ia_css_binary *copy_binary, *video_binary,\n\t\t       *yuv_scaler_binary, *vf_pp_binary;": "static int create_host_video_pipeline(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_pipeline_stage_desc stage_desc;\n\tstruct ia_css_binary *copy_binary, *video_binary,\n\t\t       *yuv_scaler_binary, *vf_pp_binary;\n\tstruct ia_css_pipeline_stage *copy_stage  = NULL;\n\tstruct ia_css_pipeline_stage *video_stage = NULL;\n\tstruct ia_css_pipeline_stage *yuv_scaler_stage  = NULL;\n\tstruct ia_css_pipeline_stage *vf_pp_stage = NULL;\n\tstruct ia_css_pipeline *me;\n\tstruct ia_css_frame *in_frame = NULL;\n\tstruct ia_css_frame *out_frame;\n\tstruct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS];\n\tstruct ia_css_frame *vf_frame = NULL;\n\tint err = 0;\n\tbool need_copy   = false;\n\tbool need_vf_pp  = false;\n\tbool need_yuv_pp = false;\n\tbool need_in_frameinfo_memory = false;\n\n\tunsigned int i, num_yuv_scaler;\n\tbool *is_output_stage = NULL;\n\n\tIA_CSS_ENTER_PRIVATE(\"pipe = %p\", pipe);\n\tif ((!pipe) || (!pipe->stream) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(-EINVAL);\n\t\treturn -EINVAL;\n\t}\n\tia_css_pipe_util_create_output_frames(out_frames);\n\tout_frame = &pipe->out_frame_struct;\n\n\t/* pipeline already created as part of create_host_pipeline_structure */\n\tme = &pipe->pipeline;\n\tia_css_pipeline_clean(me);\n\n\tme->dvs_frame_delay = pipe->dvs_frame_delay;\n\n#ifdef ISP2401\n\t/*\n\t * When the input system is 2401, always enable 'in_frameinfo_memory'\n\t * except for the following: online or continuous\n\t */\n\tneed_in_frameinfo_memory = !(pipe->stream->config.online ||\n\t\t\t\t     pipe->stream->config.continuous);\n#else\n\t/* Construct in_frame info (only in case we have dynamic input */\n\tneed_in_frameinfo_memory = pipe->stream->config.mode ==\n\t\t\t\t   IA_CSS_INPUT_MODE_MEMORY;\n#endif\n\n\t/* Construct in_frame info (only in case we have dynamic input */\n\tif (need_in_frameinfo_memory) {\n\t\tin_frame = &pipe->in_frame_struct;\n\t\terr = init_in_frameinfo_memory_defaults(pipe, in_frame,\n\t\t\t\t\t\t\tIA_CSS_FRAME_FORMAT_RAW);\n\t\tif (err)\n\t\t\tgoto ERR;\n\t}\n\n\tout_frame->data = 0;\n\terr = init_out_frameinfo_defaults(pipe, out_frame, 0);\n\tif (err)\n\t\tgoto ERR;\n\n\tif (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) {\n\t\tvf_frame = &pipe->vf_frame_struct;\n\t\tvf_frame->data = 0;\n\t\terr = init_vf_frameinfo_defaults(pipe, vf_frame, 0);\n\t\tif (err)\n\t\t\tgoto ERR;\n\t}\n\n\tcopy_binary  = &pipe->pipe_settings.video.copy_binary;\n\tvideo_binary = &pipe->pipe_settings.video.video_binary;\n\tvf_pp_binary = &pipe->pipe_settings.video.vf_pp_binary;\n\n\tyuv_scaler_binary = pipe->pipe_settings.video.yuv_scaler_binary;\n\tnum_yuv_scaler  = pipe->pipe_settings.video.num_yuv_scaler;\n\tis_output_stage = pipe->pipe_settings.video.is_output_stage;\n\n\tneed_copy   = (copy_binary && copy_binary->info);\n\tneed_vf_pp  = (vf_pp_binary && vf_pp_binary->info);\n\tneed_yuv_pp = (yuv_scaler_binary && yuv_scaler_binary->info);\n\n\tif (need_copy) {\n\t\tia_css_pipe_util_set_output_frames(out_frames, 0, NULL);\n\t\tia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary,\n\t\t\t\t\t\t   out_frames, NULL, NULL);\n\t\terr = ia_css_pipeline_create_and_add_stage(me, &stage_desc,\n\t\t\t\t\t\t\t   &copy_stage);\n\t\tif (err)\n\t\t\tgoto ERR;\n\t\tin_frame = me->stages->args.out_frame[0];\n\t} else if (pipe->stream->config.continuous) {\n#ifdef ISP2401\n\t\t/*\n\t\t * When continuous is enabled, configure in_frame with the\n\t\t * last pipe, which is the copy pipe.\n\t\t */\n\t\tin_frame = pipe->stream->last_pipe->continuous_frames[0];\n#else\n\t\tin_frame = pipe->continuous_frames[0];\n#endif\n\t}\n\n\tia_css_pipe_util_set_output_frames(out_frames, 0,\n\t\t\t\t\t   need_yuv_pp ? NULL : out_frame);\n\n\t/*\n\t * when the video binary supports a second output pin,\n\t * it can directly produce the vf_frame.\n\t */\n\tif (need_vf_pp) {\n\t\tia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary,\n\t\t\t\t\t\t   out_frames, in_frame, NULL);\n\t} else {\n\t\tia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary,\n\t\t\t\t\t\t   out_frames, in_frame, vf_frame);\n\t}\n\terr = ia_css_pipeline_create_and_add_stage(me, &stage_desc,\n\t\t\t\t\t\t   &video_stage);\n\tif (err)\n\t\tgoto ERR;\n\n\t/* If we use copy iso video, the input must be yuv iso raw */\n\tif (video_stage) {\n\t\tvideo_stage->args.copy_vf =\n\t\t    video_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY;\n\t\tvideo_stage->args.copy_output = video_stage->args.copy_vf;\n\t}\n\n\t/* when the video binary supports only 1 output pin, vf_pp is needed to\n\tproduce the vf_frame.*/\n\tif (need_vf_pp && video_stage) {\n\t\tin_frame = video_stage->args.out_vf_frame;\n\t\terr = add_vf_pp_stage(pipe, in_frame, vf_frame, vf_pp_binary,\n\t\t\t\t      &vf_pp_stage);\n\t\tif (err)\n\t\t\tgoto ERR;\n\t}\n\tif (video_stage) {\n\t\tint frm;\n\n\t\tfor (frm = 0; frm < NUM_VIDEO_TNR_FRAMES; frm++) {\n\t\t\tvideo_stage->args.tnr_frames[frm] =\n\t\t\t    pipe->pipe_settings.video.tnr_frames[frm];\n\t\t}\n\t\tfor (frm = 0; frm < MAX_NUM_VIDEO_DELAY_FRAMES; frm++) {\n\t\t\tvideo_stage->args.delay_frames[frm] =\n\t\t\t    pipe->pipe_settings.video.delay_frames[frm];\n\t\t}\n\t}\n\n\t/* Append Extension on Video out, if enabled */\n\tif (!need_vf_pp && video_stage && pipe->config.acc_extension &&\n\t    (pipe->config.acc_extension->info.isp.type == IA_CSS_ACC_OUTPUT)) {\n\t\tstruct ia_css_frame *out = NULL;\n\t\tstruct ia_css_frame *in = NULL;\n\n\t\tif ((pipe->config.acc_extension->info.isp.sp.enable.output) &&\n\t\t    (pipe->config.acc_extension->info.isp.sp.enable.in_frame) &&\n\t\t    (pipe->config.acc_extension->info.isp.sp.enable.out_frame)) {\n\t\t\t/* In/Out Frame mapping to support output frame extension.*/\n\t\t\tout = video_stage->args.out_frame[0];\n\t\t\terr = ia_css_frame_allocate_from_info(&in, &pipe->output_info[0]);\n\t\t\tif (err)\n\t\t\t\tgoto ERR;\n\t\t\tvideo_stage->args.out_frame[0] = in;\n\t\t}\n\n\t\terr = add_firmwares(me, video_binary, pipe->output_stage,\n\t\t\t\t    last_output_firmware(pipe->output_stage),\n\t\t\t\t    IA_CSS_BINARY_MODE_VIDEO,\n\t\t\t\t    in, out, NULL, &video_stage, NULL);\n\t\tif (err)\n\t\t\tgoto ERR;\n\t}\n\n\tif (need_yuv_pp && video_stage) {\n\t\tstruct ia_css_frame *tmp_in_frame = video_stage->args.out_frame[0];\n\t\tstruct ia_css_frame *tmp_out_frame = NULL;\n\n\t\tfor (i = 0; i < num_yuv_scaler; i++) {\n\t\t\ttmp_out_frame = is_output_stage[i] ? out_frame : NULL;\n\n\t\t\terr = add_yuv_scaler_stage(pipe, me, tmp_in_frame,\n\t\t\t\t\t\t   tmp_out_frame, NULL,\n\t\t\t\t\t\t   &yuv_scaler_binary[i],\n\t\t\t\t\t\t   &yuv_scaler_stage);\n\n\t\t\tif (err) {\n\t\t\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\t\t\treturn err;\n\t\t\t}\n\t\t\t/* we use output port 1 as internal output port */\n\t\t\tif (yuv_scaler_stage)\n\t\t\t\ttmp_in_frame = yuv_scaler_stage->args.out_frame[1];\n\t\t}\n\t}\n\n\tpipe->pipeline.acquire_isp_each_stage = false;\n\tia_css_pipeline_finalize_stages(&pipe->pipeline,\n\t\t\t\t\tpipe->stream->config.continuous);\n\nERR:\n\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\treturn err;\n}",
        "static long sm750le_i2c_init(unsigned char clk_gpio, unsigned char data_gpio)\n{\n\tint i;\n\n\t/* Initialize the GPIO pin for the i2c Clock Register */": "static long sm750le_i2c_init(unsigned char clk_gpio, unsigned char data_gpio)\n{\n\tint i;\n\n\t/* Initialize the GPIO pin for the i2c Clock Register */\n\tsw_i2c_clk_gpio_data_reg = GPIO_DATA_SM750LE;\n\tsw_i2c_clk_gpio_data_dir_reg = GPIO_DATA_DIRECTION_SM750LE;\n\n\t/* Initialize the Clock GPIO Offset */\n\tsw_i2c_clk_gpio = clk_gpio;\n\n\t/* Initialize the GPIO pin for the i2c Data Register */\n\tsw_i2c_data_gpio_data_reg = GPIO_DATA_SM750LE;\n\tsw_i2c_data_gpio_data_dir_reg = GPIO_DATA_DIRECTION_SM750LE;\n\n\t/* Initialize the Data GPIO Offset */\n\tsw_i2c_data_gpio = data_gpio;\n\n\t/* Note that SM750LE don't have GPIO MUX and power is always on */\n\n\t/* Clear the i2c lines. */\n\tfor (i = 0; i < 9; i++)\n\t\tsw_i2c_stop();\n\n\treturn 0;\n}",
        "static void set_aead_auth_iv(struct sec_ctx *ctx, struct sec_req *req)\n{\n\tstruct aead_request *aead_req = req->aead_req.aead_req;\n\tstruct sec_cipher_req *c_req = &req->c_req;\n\tstruct sec_aead_req *a_req = &req->aead_req;": "static void set_aead_auth_iv(struct sec_ctx *ctx, struct sec_req *req)\n{\n\tstruct aead_request *aead_req = req->aead_req.aead_req;\n\tstruct sec_cipher_req *c_req = &req->c_req;\n\tstruct sec_aead_req *a_req = &req->aead_req;\n\tsize_t authsize = ctx->a_ctx.mac_len;\n\tu32 data_size = aead_req->cryptlen;\n\tu8 flage = 0;\n\tu8 cm, cl;\n\n\t/* the specification has been checked in aead_iv_demension_check() */\n\tcl = c_req->c_ivin[0] + 1;\n\tc_req->c_ivin[ctx->c_ctx.ivsize - cl] = 0x00;\n\tmemset(&c_req->c_ivin[ctx->c_ctx.ivsize - cl], 0, cl);\n\tc_req->c_ivin[ctx->c_ctx.ivsize - IV_LAST_BYTE1] = IV_CTR_INIT;\n\n\t/* the last 3bit is L' */\n\tflage |= c_req->c_ivin[0] & IV_CL_MASK;\n\n\t/* the M' is bit3~bit5, the Flags is bit6 */\n\tcm = (authsize - IV_CM_CAL_NUM) / IV_CM_CAL_NUM;\n\tflage |= cm << IV_CM_OFFSET;\n\tif (aead_req->assoclen)\n\t\tflage |= 0x01 << IV_FLAGS_OFFSET;\n\n\tmemcpy(a_req->a_ivin, c_req->c_ivin, ctx->c_ctx.ivsize);\n\ta_req->a_ivin[0] = flage;\n\n\t/*\n\t * the last 32bit is counter's initial number,\n\t * but the nonce uses the first 16bit\n\t * the tail 16bit fill with the cipher length\n\t */\n\tif (!c_req->encrypt)\n\t\tdata_size = aead_req->cryptlen - authsize;\n\n\ta_req->a_ivin[ctx->c_ctx.ivsize - IV_LAST_BYTE1] =\n\t\t\tdata_size & IV_LAST_BYTE_MASK;\n\tdata_size >>= IV_BYTE_OFFSET;\n\ta_req->a_ivin[ctx->c_ctx.ivsize - IV_LAST_BYTE2] =\n\t\t\tdata_size & IV_LAST_BYTE_MASK;\n}",
        "static int nl80211_req_set_reg(struct sk_buff *skb, struct genl_info *info)\n{\n\tchar *data = NULL;\n\tbool is_indoor;\n\tenum nl80211_user_reg_hint_type user_reg_hint_type;": "static int nl80211_req_set_reg(struct sk_buff *skb, struct genl_info *info)\n{\n\tchar *data = NULL;\n\tbool is_indoor;\n\tenum nl80211_user_reg_hint_type user_reg_hint_type;\n\tu32 owner_nlportid;\n\n\t/*\n\t * You should only get this when cfg80211 hasn't yet initialized\n\t * completely when built-in to the kernel right between the time\n\t * window between nl80211_init() and regulatory_init(), if that is\n\t * even possible.\n\t */\n\tif (unlikely(!rcu_access_pointer(cfg80211_regdomain)))\n\t\treturn -EINPROGRESS;\n\n\tif (info->attrs[NL80211_ATTR_USER_REG_HINT_TYPE])\n\t\tuser_reg_hint_type =\n\t\t  nla_get_u32(info->attrs[NL80211_ATTR_USER_REG_HINT_TYPE]);\n\telse\n\t\tuser_reg_hint_type = NL80211_USER_REG_HINT_USER;\n\n\tswitch (user_reg_hint_type) {\n\tcase NL80211_USER_REG_HINT_USER:\n\tcase NL80211_USER_REG_HINT_CELL_BASE:\n\t\tif (!info->attrs[NL80211_ATTR_REG_ALPHA2])\n\t\t\treturn -EINVAL;\n\n\t\tdata = nla_data(info->attrs[NL80211_ATTR_REG_ALPHA2]);\n\t\treturn regulatory_hint_user(data, user_reg_hint_type);\n\tcase NL80211_USER_REG_HINT_INDOOR:\n\t\tif (info->attrs[NL80211_ATTR_SOCKET_OWNER]) {\n\t\t\towner_nlportid = info->snd_portid;\n\t\t\tis_indoor = !!info->attrs[NL80211_ATTR_REG_INDOOR];\n\t\t} else {\n\t\t\towner_nlportid = 0;\n\t\t\tis_indoor = true;\n\t\t}\n\n\t\treturn regulatory_hint_indoor(is_indoor, owner_nlportid);\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n}",
        "static int cineS2_probe(struct ngene_channel *chan)\n{\n\tstruct device *pdev = &chan->dev->pci_dev->dev;\n\tstruct i2c_adapter *i2c = i2c_adapter_from_chan(chan);\n\tstruct stv090x_config *fe_conf;": "static int cineS2_probe(struct ngene_channel *chan)\n{\n\tstruct device *pdev = &chan->dev->pci_dev->dev;\n\tstruct i2c_adapter *i2c = i2c_adapter_from_chan(chan);\n\tstruct stv090x_config *fe_conf;\n\tu8 buf[3];\n\tu8 xo2_type, xo2_id, xo2_demodtype;\n\tu8 sony_osc24 = 0;\n\tstruct i2c_msg i2c_msg = { .flags = 0, .buf = buf };\n\tint rc;\n\n\tif (port_has_xo2(i2c, &xo2_type, &xo2_id)) {\n\t\txo2_id >>= 2;\n\t\tdev_dbg(pdev, \"XO2 on channel %d (type %d, id %d)\\n\",\n\t\t\tchan->number, xo2_type, xo2_id);\n\n\t\tswitch (xo2_type) {\n\t\tcase NGENE_XO2_TYPE_DUOFLEX:\n\t\t\tif (chan->number & 1)\n\t\t\t\tdev_dbg(pdev,\n\t\t\t\t\t\"skipping XO2 init on odd channel %d\",\n\t\t\t\t\tchan->number);\n\t\t\telse\n\t\t\t\tinit_xo2(chan, i2c);\n\n\t\t\txo2_demodtype = DEMOD_TYPE_XO2 + xo2_id;\n\n\t\t\tswitch (xo2_demodtype) {\n\t\t\tcase DEMOD_TYPE_SONY_CT2:\n\t\t\tcase DEMOD_TYPE_SONY_ISDBT:\n\t\t\tcase DEMOD_TYPE_SONY_C2T2:\n\t\t\tcase DEMOD_TYPE_SONY_C2T2I:\n\t\t\t\tdev_info(pdev, \"%s (XO2) on channel %d\\n\",\n\t\t\t\t\t xo2names[xo2_id], chan->number);\n\t\t\t\tchan->demod_type = xo2_demodtype;\n\t\t\t\tif (xo2_demodtype == DEMOD_TYPE_SONY_C2T2I)\n\t\t\t\t\tsony_osc24 = 1;\n\n\t\t\t\tdemod_attach_cxd28xx(chan, i2c, sony_osc24);\n\t\t\t\tbreak;\n\t\t\tcase DEMOD_TYPE_STV0910:\n\t\t\t\tdev_info(pdev, \"%s (XO2) on channel %d\\n\",\n\t\t\t\t\t xo2names[xo2_id], chan->number);\n\t\t\t\tchan->demod_type = xo2_demodtype;\n\t\t\t\tdemod_attach_stv0910(chan, i2c);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tdev_warn(pdev,\n\t\t\t\t\t \"Unsupported XO2 module on channel %d\\n\",\n\t\t\t\t\t chan->number);\n\t\t\t\treturn -ENODEV;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase NGENE_XO2_TYPE_CI:\n\t\t\tdev_info(pdev, \"DuoFlex CI modules not supported\\n\");\n\t\t\treturn -ENODEV;\n\t\tdefault:\n\t\t\tdev_info(pdev, \"Unsupported XO2 module type\\n\");\n\t\t\treturn -ENODEV;\n\t\t}\n\t} else if (port_has_stv0900(i2c, chan->number)) {\n\t\tchan->demod_type = DEMOD_TYPE_STV090X;\n\t\tfe_conf = chan->dev->card_info->fe_config[chan->number];\n\t\t/* demod found, attach it */\n\t\trc = demod_attach_stv0900(chan);\n\t\tif (rc < 0 || chan->number < 2)\n\t\t\treturn rc;\n\n\t\t/* demod #2: reprogram outputs DPN1 & DPN2 */\n\t\ti2c_msg.addr = fe_conf->address;\n\t\ti2c_msg.len = 3;\n\t\tbuf[0] = 0xf1;\n\t\tswitch (chan->number) {\n\t\tcase 2:\n\t\t\tbuf[1] = 0x5c;\n\t\t\tbuf[2] = 0xc2;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tbuf[1] = 0x61;\n\t\t\tbuf[2] = 0xcc;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -ENODEV;\n\t\t}\n\t\trc = i2c_transfer(i2c, &i2c_msg, 1);\n\t\tif (rc != 1) {\n\t\t\tdev_err(pdev, \"Could not setup DPNx\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t} else if (port_has_drxk(i2c, chan->number^2)) {\n\t\tchan->demod_type = DEMOD_TYPE_DRXK;\n\t\tdemod_attach_drxk(chan, i2c);\n\t} else if (port_has_stv0367(i2c)) {\n\t\tchan->demod_type = DEMOD_TYPE_STV0367;\n\t\tdev_info(pdev, \"STV0367 on channel %d\\n\", chan->number);\n\t\tdemod_attach_stv0367(chan, i2c);\n\t} else {\n\t\tdev_info(pdev, \"No demod found on chan %d\\n\", chan->number);\n\t\treturn -ENODEV;\n\t}\n\treturn 0;\n}",
        "static int ntlm_authenticate(struct ksmbd_work *work)\n{\n\tstruct smb2_sess_setup_req *req = smb2_get_msg(work->request_buf);\n\tstruct smb2_sess_setup_rsp *rsp = smb2_get_msg(work->response_buf);\n\tstruct ksmbd_conn *conn = work->conn;": "static int ntlm_authenticate(struct ksmbd_work *work)\n{\n\tstruct smb2_sess_setup_req *req = smb2_get_msg(work->request_buf);\n\tstruct smb2_sess_setup_rsp *rsp = smb2_get_msg(work->response_buf);\n\tstruct ksmbd_conn *conn = work->conn;\n\tstruct ksmbd_session *sess = work->sess;\n\tstruct channel *chann = NULL;\n\tstruct ksmbd_user *user;\n\tu64 prev_id;\n\tint sz, rc;\n\n\tksmbd_debug(SMB, \"authenticate phase\\n\");\n\tif (conn->use_spnego) {\n\t\tunsigned char *spnego_blob;\n\t\tu16 spnego_blob_len;\n\n\t\trc = build_spnego_ntlmssp_auth_blob(&spnego_blob,\n\t\t\t\t\t\t    &spnego_blob_len,\n\t\t\t\t\t\t    0);\n\t\tif (rc)\n\t\t\treturn -ENOMEM;\n\n\t\tsz = le16_to_cpu(rsp->SecurityBufferOffset);\n\t\tmemcpy((char *)&rsp->hdr.ProtocolId + sz, spnego_blob, spnego_blob_len);\n\t\trsp->SecurityBufferLength = cpu_to_le16(spnego_blob_len);\n\t\tkfree(spnego_blob);\n\t\tinc_rfc1001_len(work->response_buf, spnego_blob_len - 1);\n\t}\n\n\tuser = session_user(conn, req);\n\tif (!user) {\n\t\tksmbd_debug(SMB, \"Unknown user name or an error\\n\");\n\t\treturn -EPERM;\n\t}\n\n\t/* Check for previous session */\n\tprev_id = le64_to_cpu(req->PreviousSessionId);\n\tif (prev_id && prev_id != sess->id)\n\t\tdestroy_previous_session(user, prev_id);\n\n\tif (sess->state == SMB2_SESSION_VALID) {\n\t\t/*\n\t\t * Reuse session if anonymous try to connect\n\t\t * on reauthetication.\n\t\t */\n\t\tif (ksmbd_anonymous_user(user)) {\n\t\t\tksmbd_free_user(user);\n\t\t\treturn 0;\n\t\t}\n\n\t\tif (!ksmbd_compare_user(sess->user, user)) {\n\t\t\tksmbd_free_user(user);\n\t\t\treturn -EPERM;\n\t\t}\n\t\tksmbd_free_user(user);\n\t} else {\n\t\tsess->user = user;\n\t}\n\n\tif (user_guest(sess->user)) {\n\t\trsp->SessionFlags = SMB2_SESSION_FLAG_IS_GUEST_LE;\n\t} else {\n\t\tstruct authenticate_message *authblob;\n\n\t\tauthblob = user_authblob(conn, req);\n\t\tsz = le16_to_cpu(req->SecurityBufferLength);\n\t\trc = ksmbd_decode_ntlmssp_auth_blob(authblob, sz, conn, sess);\n\t\tif (rc) {\n\t\t\tset_user_flag(sess->user, KSMBD_USER_FLAG_BAD_PASSWORD);\n\t\t\tksmbd_debug(SMB, \"authentication failed\\n\");\n\t\t\treturn -EPERM;\n\t\t}\n\t}\n\n\t/*\n\t * If session state is SMB2_SESSION_VALID, We can assume\n\t * that it is reauthentication. And the user/password\n\t * has been verified, so return it here.\n\t */\n\tif (sess->state == SMB2_SESSION_VALID) {\n\t\tif (conn->binding)\n\t\t\tgoto binding_session;\n\t\treturn 0;\n\t}\n\n\tif ((rsp->SessionFlags != SMB2_SESSION_FLAG_IS_GUEST_LE &&\n\t     (conn->sign || server_conf.enforced_signing)) ||\n\t    (req->SecurityMode & SMB2_NEGOTIATE_SIGNING_REQUIRED))\n\t\tsess->sign = true;\n\n\tif (smb3_encryption_negotiated(conn) &&\n\t\t\t!(req->Flags & SMB2_SESSION_REQ_FLAG_BINDING)) {\n\t\trc = conn->ops->generate_encryptionkey(sess);\n\t\tif (rc) {\n\t\t\tksmbd_debug(SMB,\n\t\t\t\t\t\"SMB3 encryption key generation failed\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tsess->enc = true;\n\t\trsp->SessionFlags = SMB2_SESSION_FLAG_ENCRYPT_DATA_LE;\n\t\t/*\n\t\t * signing is disable if encryption is enable\n\t\t * on this session\n\t\t */\n\t\tsess->sign = false;\n\t}\n\nbinding_session:\n\tif (conn->dialect >= SMB30_PROT_ID) {\n\t\tchann = lookup_chann_list(sess, conn);\n\t\tif (!chann) {\n\t\t\tchann = kmalloc(sizeof(struct channel), GFP_KERNEL);\n\t\t\tif (!chann)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tchann->conn = conn;\n\t\t\tINIT_LIST_HEAD(&chann->chann_list);\n\t\t\tlist_add(&chann->chann_list, &sess->ksmbd_chann_list);\n\t\t}\n\t}\n\n\tif (conn->ops->generate_signingkey) {\n\t\trc = conn->ops->generate_signingkey(sess, conn);\n\t\tif (rc) {\n\t\t\tksmbd_debug(SMB, \"SMB3 signing key generation failed\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tif (!ksmbd_conn_lookup_dialect(conn)) {\n\t\tpr_err(\"fail to verify the dialect\\n\");\n\t\treturn -ENOENT;\n\t}\n\treturn 0;\n}",
        "static int io_files_update(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_uring_rsrc_update2 up;\n\tint ret;": "static int io_files_update(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tstruct io_uring_rsrc_update2 up;\n\tint ret;\n\n\tup.offset = req->rsrc_update.offset;\n\tup.data = req->rsrc_update.arg;\n\tup.nr = 0;\n\tup.tags = 0;\n\tup.resv = 0;\n\tup.resv2 = 0;\n\n\tif (req->rsrc_update.offset == IORING_FILE_INDEX_ALLOC) {\n\t\tret = io_files_update_with_index_alloc(req, issue_flags);\n\t} else {\n\t\tio_ring_submit_lock(ctx, issue_flags);\n\t\tret = __io_register_rsrc_update(ctx, IORING_RSRC_FILE,\n\t\t\t\t&up, req->rsrc_update.nr_args);\n\t\tio_ring_submit_unlock(ctx, issue_flags);\n\t}\n\n\tif (ret < 0)\n\t\treq_set_fail(req);\n\t__io_req_complete(req, issue_flags, ret, 0);\n\treturn 0;\n}",
        "static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)\n{\n\tstruct intel_priv_data *intel_priv = intel_data;\n\tstruct stmmac_priv *priv = netdev_priv(ndev);\n\tint serdes_phy_addr = 0;": "static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)\n{\n\tstruct intel_priv_data *intel_priv = intel_data;\n\tstruct stmmac_priv *priv = netdev_priv(ndev);\n\tint serdes_phy_addr = 0;\n\tu32 data = 0;\n\n\tserdes_phy_addr = intel_priv->mdio_adhoc_addr;\n\n\t/* Determine the link speed mode: 2.5Gbps/1Gbps */\n\tdata = mdiobus_read(priv->mii, serdes_phy_addr,\n\t\t\t    SERDES_GCR);\n\n\tif (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==\n\t    SERDES_LINK_MODE_2G5) {\n\t\tdev_info(priv->device, \"Link Speed Mode: 2.5Gbps\\n\");\n\t\tpriv->plat->max_speed = 2500;\n\t\tpriv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;\n\t\tpriv->plat->mdio_bus_data->xpcs_an_inband = false;\n\t} else {\n\t\tpriv->plat->max_speed = 1000;\n\t\tpriv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;\n\t\tpriv->plat->mdio_bus_data->xpcs_an_inband = true;\n\t}\n}",
        "static int decode_MOSDOpReply(const struct ceph_msg *msg, struct MOSDOpReply *m)\n{\n\tvoid *p = msg->front.iov_base;\n\tvoid *const end = p + msg->front.iov_len;\n\tu16 version = le16_to_cpu(msg->hdr.version);": "static int decode_MOSDOpReply(const struct ceph_msg *msg, struct MOSDOpReply *m)\n{\n\tvoid *p = msg->front.iov_base;\n\tvoid *const end = p + msg->front.iov_len;\n\tu16 version = le16_to_cpu(msg->hdr.version);\n\tstruct ceph_eversion bad_replay_version;\n\tu8 decode_redir;\n\tu32 len;\n\tint ret;\n\tint i;\n\n\tceph_decode_32_safe(&p, end, len, e_inval);\n\tceph_decode_need(&p, end, len, e_inval);\n\tp += len; /* skip oid */\n\n\tret = ceph_decode_pgid(&p, end, &m->pgid);\n\tif (ret)\n\t\treturn ret;\n\n\tceph_decode_64_safe(&p, end, m->flags, e_inval);\n\tceph_decode_32_safe(&p, end, m->result, e_inval);\n\tceph_decode_need(&p, end, sizeof(bad_replay_version), e_inval);\n\tmemcpy(&bad_replay_version, p, sizeof(bad_replay_version));\n\tp += sizeof(bad_replay_version);\n\tceph_decode_32_safe(&p, end, m->epoch, e_inval);\n\n\tceph_decode_32_safe(&p, end, m->num_ops, e_inval);\n\tif (m->num_ops > ARRAY_SIZE(m->outdata_len))\n\t\tgoto e_inval;\n\n\tceph_decode_need(&p, end, m->num_ops * sizeof(struct ceph_osd_op),\n\t\t\t e_inval);\n\tfor (i = 0; i < m->num_ops; i++) {\n\t\tstruct ceph_osd_op *op = p;\n\n\t\tm->outdata_len[i] = le32_to_cpu(op->payload_len);\n\t\tp += sizeof(*op);\n\t}\n\n\tceph_decode_32_safe(&p, end, m->retry_attempt, e_inval);\n\tfor (i = 0; i < m->num_ops; i++)\n\t\tceph_decode_32_safe(&p, end, m->rval[i], e_inval);\n\n\tif (version >= 5) {\n\t\tceph_decode_need(&p, end, sizeof(m->replay_version), e_inval);\n\t\tmemcpy(&m->replay_version, p, sizeof(m->replay_version));\n\t\tp += sizeof(m->replay_version);\n\t\tceph_decode_64_safe(&p, end, m->user_version, e_inval);\n\t} else {\n\t\tm->replay_version = bad_replay_version; /* struct */\n\t\tm->user_version = le64_to_cpu(m->replay_version.version);\n\t}\n\n\tif (version >= 6) {\n\t\tif (version >= 7)\n\t\t\tceph_decode_8_safe(&p, end, decode_redir, e_inval);\n\t\telse\n\t\t\tdecode_redir = 1;\n\t} else {\n\t\tdecode_redir = 0;\n\t}\n\n\tif (decode_redir) {\n\t\tret = ceph_redirect_decode(&p, end, &m->redirect);\n\t\tif (ret)\n\t\t\treturn ret;\n\t} else {\n\t\tceph_oloc_init(&m->redirect.oloc);\n\t}\n\n\treturn 0;\n\ne_inval:\n\treturn -EINVAL;\n}",
        "static void miro_pinnacle_gpio(struct bttv *btv)\n{\n\tint id,msp,gpio;\n\tchar *info;\n": "static void miro_pinnacle_gpio(struct bttv *btv)\n{\n\tint id,msp,gpio;\n\tchar *info;\n\n\tgpio_inout(0xffffff, 0);\n\tgpio = gpio_read();\n\tid   = ((gpio>>10) & 63) -1;\n\tmsp  = bttv_I2CRead(btv, I2C_ADDR_MSP3400, \"MSP34xx\");\n\tif (id < 32) {\n\t\tbtv->tuner_type = miro_tunermap[id];\n\t\tif (0 == (gpio & 0x20)) {\n\t\t\tbtv->has_radio = 1;\n\t\t\tif (!miro_fmtuner[id]) {\n\t\t\t\tbtv->has_tea575x = 1;\n\t\t\t\tbtv->tea_gpio.wren = 6;\n\t\t\t\tbtv->tea_gpio.most = 7;\n\t\t\t\tbtv->tea_gpio.clk  = 8;\n\t\t\t\tbtv->tea_gpio.data = 9;\n\t\t\t\ttea575x_init(btv);\n\t\t\t}\n\t\t} else {\n\t\t\tbtv->has_radio = 0;\n\t\t}\n\t\tif (-1 != msp) {\n\t\t\tif (btv->c.type == BTTV_BOARD_MIRO)\n\t\t\t\tbtv->c.type = BTTV_BOARD_MIROPRO;\n\t\t\tif (btv->c.type == BTTV_BOARD_PINNACLE)\n\t\t\t\tbtv->c.type = BTTV_BOARD_PINNACLEPRO;\n\t\t}\n\t\tpr_info(\"%d: miro: id=%d tuner=%d radio=%s stereo=%s\\n\",\n\t\t\tbtv->c.nr, id+1, btv->tuner_type,\n\t\t\t!btv->has_radio ? \"no\" :\n\t\t\t(btv->has_tea575x ? \"tea575x\" : \"fmtuner\"),\n\t\t\t(-1 == msp) ? \"no\" : \"yes\");\n\t} else {\n\t\t/* new cards with microtune tuner */\n\t\tid = 63 - id;\n\t\tbtv->has_radio = 0;\n\t\tswitch (id) {\n\t\tcase 1:\n\t\t\tinfo = \"PAL / mono\";\n\t\t\tbtv->tda9887_conf = TDA9887_INTERCARRIER;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tinfo = \"PAL+SECAM / stereo\";\n\t\t\tbtv->has_radio = 1;\n\t\t\tbtv->tda9887_conf = TDA9887_QSS;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tinfo = \"NTSC / stereo\";\n\t\t\tbtv->has_radio = 1;\n\t\t\tbtv->tda9887_conf = TDA9887_QSS;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\tinfo = \"PAL+SECAM / mono\";\n\t\t\tbtv->tda9887_conf = TDA9887_QSS;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tinfo = \"NTSC / mono\";\n\t\t\tbtv->tda9887_conf = TDA9887_INTERCARRIER;\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tinfo = \"NTSC / stereo\";\n\t\t\tbtv->tda9887_conf = TDA9887_INTERCARRIER;\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\tinfo = \"PAL / stereo\";\n\t\t\tbtv->tda9887_conf = TDA9887_INTERCARRIER;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tinfo = \"oops: unknown card\";\n\t\t\tbreak;\n\t\t}\n\t\tif (-1 != msp)\n\t\t\tbtv->c.type = BTTV_BOARD_PINNACLEPRO;\n\t\tpr_info(\"%d: pinnacle/mt: id=%d info=\\\"%s\\\" radio=%s\\n\",\n\t\t\tbtv->c.nr, id, info, btv->has_radio ? \"yes\" : \"no\");\n\t\tbtv->tuner_type = TUNER_MT2032;\n\t}\n}",
        "static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec, bool clr)\n{\n\t__be32 raw_ip[4];\n\n\tspec->smac_47_16 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, smac_47_16, clr);": "static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec, bool clr)\n{\n\t__be32 raw_ip[4];\n\n\tspec->smac_47_16 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, smac_47_16, clr);\n\n\tspec->smac_15_0 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, smac_15_0, clr);\n\tspec->ethertype = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ethertype, clr);\n\n\tspec->dmac_47_16 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, dmac_47_16, clr);\n\n\tspec->dmac_15_0 = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, dmac_15_0, clr);\n\tspec->first_prio = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_prio, clr);\n\tspec->first_cfi = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_cfi, clr);\n\tspec->first_vid = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, first_vid, clr);\n\n\tspec->ip_protocol = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_protocol, clr);\n\tspec->ip_dscp = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_dscp, clr);\n\tspec->ip_ecn = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_ecn, clr);\n\tspec->cvlan_tag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, cvlan_tag, clr);\n\tspec->svlan_tag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, svlan_tag, clr);\n\tspec->frag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, frag, clr);\n\tspec->ip_version = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ip_version, clr);\n\tspec->tcp_flags = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, tcp_flags, clr);\n\tspec->tcp_sport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, tcp_sport, clr);\n\tspec->tcp_dport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, tcp_dport, clr);\n\n\tspec->ipv4_ihl = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ipv4_ihl, clr);\n\tspec->ttl_hoplimit = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, ttl_hoplimit, clr);\n\n\tspec->udp_sport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, udp_sport, clr);\n\tspec->udp_dport = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, udp_dport, clr);\n\n\tmemcpy_and_clear(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,\n\t\t\t\t\t      src_ipv4_src_ipv6.ipv6_layout.ipv6),\n\t\t\t sizeof(raw_ip), clr);\n\n\tspec->src_ip_127_96 = be32_to_cpu(raw_ip[0]);\n\tspec->src_ip_95_64 = be32_to_cpu(raw_ip[1]);\n\tspec->src_ip_63_32 = be32_to_cpu(raw_ip[2]);\n\tspec->src_ip_31_0 = be32_to_cpu(raw_ip[3]);\n\n\tmemcpy_and_clear(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,\n\t\t\t\t\t      dst_ipv4_dst_ipv6.ipv6_layout.ipv6),\n\t\t\t sizeof(raw_ip), clr);\n\n\tspec->dst_ip_127_96 = be32_to_cpu(raw_ip[0]);\n\tspec->dst_ip_95_64 = be32_to_cpu(raw_ip[1]);\n\tspec->dst_ip_63_32 = be32_to_cpu(raw_ip[2]);\n\tspec->dst_ip_31_0 = be32_to_cpu(raw_ip[3]);\n}",
        "static void launch_tests(void)\n{\n\tchar buf[1024];\n\tunsigned int tests = 0;\n\tint len, local, global, i;": "static void launch_tests(void)\n{\n\tchar buf[1024];\n\tunsigned int tests = 0;\n\tint len, local, global, i;\n\n\ttests += 3 * COUNT_ISN_BPS;\n\ttests += sizeof(long) / 2 * 3 * COUNT_WPS;\n\ttests += sizeof(long) / 2 * 3 * COUNT_WPS;\n\ttests += 2;\n\tksft_set_plan(tests);\n\n\t/* Instruction breakpoints */\n\tfor (local = 0; local < 2; local++) {\n\t\tfor (global = 0; global < 2; global++) {\n\t\t\tif (!local && !global)\n\t\t\t\tcontinue;\n\t\t\tlaunch_instruction_breakpoints(buf, local, global);\n\t\t}\n\t}\n\n\t/* Write watchpoint */\n\tfor (len = 1; len <= sizeof(long); len <<= 1) {\n\t\tfor (local = 0; local < 2; local++) {\n\t\t\tfor (global = 0; global < 2; global++) {\n\t\t\t\tif (!local && !global)\n\t\t\t\t\tcontinue;\n\t\t\t\tlaunch_watchpoints(buf, BP_W, len,\n\t\t\t\t\t\t   local, global);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Read-Write watchpoint */\n\tfor (len = 1; len <= sizeof(long); len <<= 1) {\n\t\tfor (local = 0; local < 2; local++) {\n\t\t\tfor (global = 0; global < 2; global++) {\n\t\t\t\tif (!local && !global)\n\t\t\t\t\tcontinue;\n\t\t\t\tlaunch_watchpoints(buf, BP_RW, len,\n\t\t\t\t\t\t   local, global);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Icebp traps */\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(\"Test icebp\\n\");\n\n\t/* Int 3 traps */\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\tcheck_success(\"Test int 3 trap\\n\");\n\n\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n}",
        "static void send_pulse_irdeo(unsigned int length, ktime_t target)\n{\n\tlong rawbits;\n\tint i;\n\tunsigned char output;": "static void send_pulse_irdeo(unsigned int length, ktime_t target)\n{\n\tlong rawbits;\n\tint i;\n\tunsigned char output;\n\tunsigned char chunk, shifted;\n\n\t/* how many bits have to be sent ? */\n\trawbits = length * 1152 / 10000;\n\tif (serial_ir.duty_cycle > 50)\n\t\tchunk = 3;\n\telse\n\t\tchunk = 1;\n\tfor (i = 0, output = 0x7f; rawbits > 0; rawbits -= 3) {\n\t\tshifted = chunk << (i * 3);\n\t\tshifted >>= 1;\n\t\toutput &= (~shifted);\n\t\ti++;\n\t\tif (i == 3) {\n\t\t\tsoutp(UART_TX, output);\n\t\t\twhile (!(sinp(UART_LSR) & UART_LSR_THRE))\n\t\t\t\t;\n\t\t\toutput = 0x7f;\n\t\t\ti = 0;\n\t\t}\n\t}\n\tif (i != 0) {\n\t\tsoutp(UART_TX, output);\n\t\twhile (!(sinp(UART_LSR) & UART_LSR_TEMT))\n\t\t\t;\n\t}\n}",
        "static int xcvr_init_10g_mrvl88x2011(struct niu *np)\n{\n\tint\terr;\n\n\t/* Set LED functions */": "static int xcvr_init_10g_mrvl88x2011(struct niu *np)\n{\n\tint\terr;\n\n\t/* Set LED functions */\n\terr = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);\n\tif (err)\n\t\treturn err;\n\n\t/* led activity */\n\terr = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);\n\tif (err)\n\t\treturn err;\n\n\terr = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,\n\t\t\tMRVL88X2011_GENERAL_CTL);\n\tif (err < 0)\n\t\treturn err;\n\n\terr |= MRVL88X2011_ENA_XFPREFCLK;\n\n\terr = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,\n\t\t\t MRVL88X2011_GENERAL_CTL, err);\n\tif (err < 0)\n\t\treturn err;\n\n\terr = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,\n\t\t\tMRVL88X2011_PMA_PMD_CTL_1);\n\tif (err < 0)\n\t\treturn err;\n\n\tif (np->link_config.loopback_mode == LOOPBACK_MAC)\n\t\terr |= MRVL88X2011_LOOPBACK;\n\telse\n\t\terr &= ~MRVL88X2011_LOOPBACK;\n\n\terr = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,\n\t\t\t MRVL88X2011_PMA_PMD_CTL_1, err);\n\tif (err < 0)\n\t\treturn err;\n\n\t/* Enable PMD  */\n\treturn mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,\n\t\t\t  MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);\n}",
        "static bool __init test_barrier(void)\n{\n#ifdef CONFIG_KCSAN_WEAK_MEMORY\n\tstruct kcsan_scoped_access *reorder_access = &current->kcsan_ctx.reorder_access;\n#else": "static bool __init test_barrier(void)\n{\n#ifdef CONFIG_KCSAN_WEAK_MEMORY\n\tstruct kcsan_scoped_access *reorder_access = &current->kcsan_ctx.reorder_access;\n#else\n\tstruct kcsan_scoped_access *reorder_access = NULL;\n#endif\n\tbool ret = true;\n\tarch_spinlock_t arch_spinlock = __ARCH_SPIN_LOCK_UNLOCKED;\n\tatomic_t dummy;\n\tlong test_var;\n\n\tif (!reorder_access || !IS_ENABLED(CONFIG_SMP))\n\t\treturn true;\n\n#define __KCSAN_CHECK_BARRIER(access_type, barrier, name)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\t\t\t\\\n\t\treorder_access->type = (access_type) | KCSAN_ACCESS_SCOPED;\t\t\t\\\n\t\treorder_access->size = 1;\t\t\t\t\t\t\t\\\n\t\tbarrier;\t\t\t\t\t\t\t\t\t\\\n\t\tif (reorder_access->size != 0) {\t\t\t\t\t\t\\\n\t\t\tpr_err(\"improperly instrumented type=(\" #access_type \"): \" name \"\\n\");\t\\\n\t\t\tret = false;\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\\\n\t} while (0)\n#define KCSAN_CHECK_READ_BARRIER(b)  __KCSAN_CHECK_BARRIER(0, b, #b)\n#define KCSAN_CHECK_WRITE_BARRIER(b) __KCSAN_CHECK_BARRIER(KCSAN_ACCESS_WRITE, b, #b)\n#define KCSAN_CHECK_RW_BARRIER(b)    __KCSAN_CHECK_BARRIER(KCSAN_ACCESS_WRITE | KCSAN_ACCESS_COMPOUND, b, #b)\n\n\tkcsan_nestable_atomic_begin(); /* No watchpoints in called functions. */\n\n\tKCSAN_CHECK_READ_BARRIER(mb());\n\tKCSAN_CHECK_READ_BARRIER(rmb());\n\tKCSAN_CHECK_READ_BARRIER(smp_mb());\n\tKCSAN_CHECK_READ_BARRIER(smp_rmb());\n\tKCSAN_CHECK_READ_BARRIER(dma_rmb());\n\tKCSAN_CHECK_READ_BARRIER(smp_mb__before_atomic());\n\tKCSAN_CHECK_READ_BARRIER(smp_mb__after_atomic());\n\tKCSAN_CHECK_READ_BARRIER(smp_mb__after_spinlock());\n\tKCSAN_CHECK_READ_BARRIER(smp_store_mb(test_var, 0));\n\tKCSAN_CHECK_READ_BARRIER(smp_store_release(&test_var, 0));\n\tKCSAN_CHECK_READ_BARRIER(xchg(&test_var, 0));\n\tKCSAN_CHECK_READ_BARRIER(xchg_release(&test_var, 0));\n\tKCSAN_CHECK_READ_BARRIER(cmpxchg(&test_var, 0,  0));\n\tKCSAN_CHECK_READ_BARRIER(cmpxchg_release(&test_var, 0,  0));\n\tKCSAN_CHECK_READ_BARRIER(atomic_set_release(&dummy, 0));\n\tKCSAN_CHECK_READ_BARRIER(atomic_add_return(1, &dummy));\n\tKCSAN_CHECK_READ_BARRIER(atomic_add_return_release(1, &dummy));\n\tKCSAN_CHECK_READ_BARRIER(atomic_fetch_add(1, &dummy));\n\tKCSAN_CHECK_READ_BARRIER(atomic_fetch_add_release(1, &dummy));\n\tKCSAN_CHECK_READ_BARRIER(test_and_set_bit(0, &test_var));\n\tKCSAN_CHECK_READ_BARRIER(test_and_clear_bit(0, &test_var));\n\tKCSAN_CHECK_READ_BARRIER(test_and_change_bit(0, &test_var));\n\tKCSAN_CHECK_READ_BARRIER(clear_bit_unlock(0, &test_var));\n\tKCSAN_CHECK_READ_BARRIER(__clear_bit_unlock(0, &test_var));\n\tarch_spin_lock(&arch_spinlock);\n\tKCSAN_CHECK_READ_BARRIER(arch_spin_unlock(&arch_spinlock));\n\tspin_lock(&test_spinlock);\n\tKCSAN_CHECK_READ_BARRIER(spin_unlock(&test_spinlock));\n\n\tKCSAN_CHECK_WRITE_BARRIER(mb());\n\tKCSAN_CHECK_WRITE_BARRIER(wmb());\n\tKCSAN_CHECK_WRITE_BARRIER(smp_mb());\n\tKCSAN_CHECK_WRITE_BARRIER(smp_wmb());\n\tKCSAN_CHECK_WRITE_BARRIER(dma_wmb());\n\tKCSAN_CHECK_WRITE_BARRIER(smp_mb__before_atomic());\n\tKCSAN_CHECK_WRITE_BARRIER(smp_mb__after_atomic());\n\tKCSAN_CHECK_WRITE_BARRIER(smp_mb__after_spinlock());\n\tKCSAN_CHECK_WRITE_BARRIER(smp_store_mb(test_var, 0));\n\tKCSAN_CHECK_WRITE_BARRIER(smp_store_release(&test_var, 0));\n\tKCSAN_CHECK_WRITE_BARRIER(xchg(&test_var, 0));\n\tKCSAN_CHECK_WRITE_BARRIER(xchg_release(&test_var, 0));\n\tKCSAN_CHECK_WRITE_BARRIER(cmpxchg(&test_var, 0,  0));\n\tKCSAN_CHECK_WRITE_BARRIER(cmpxchg_release(&test_var, 0,  0));\n\tKCSAN_CHECK_WRITE_BARRIER(atomic_set_release(&dummy, 0));\n\tKCSAN_CHECK_WRITE_BARRIER(atomic_add_return(1, &dummy));\n\tKCSAN_CHECK_WRITE_BARRIER(atomic_add_return_release(1, &dummy));\n\tKCSAN_CHECK_WRITE_BARRIER(atomic_fetch_add(1, &dummy));\n\tKCSAN_CHECK_WRITE_BARRIER(atomic_fetch_add_release(1, &dummy));\n\tKCSAN_CHECK_WRITE_BARRIER(test_and_set_bit(0, &test_var));\n\tKCSAN_CHECK_WRITE_BARRIER(test_and_clear_bit(0, &test_var));\n\tKCSAN_CHECK_WRITE_BARRIER(test_and_change_bit(0, &test_var));\n\tKCSAN_CHECK_WRITE_BARRIER(clear_bit_unlock(0, &test_var));\n\tKCSAN_CHECK_WRITE_BARRIER(__clear_bit_unlock(0, &test_var));\n\tarch_spin_lock(&arch_spinlock);\n\tKCSAN_CHECK_WRITE_BARRIER(arch_spin_unlock(&arch_spinlock));\n\tspin_lock(&test_spinlock);\n\tKCSAN_CHECK_WRITE_BARRIER(spin_unlock(&test_spinlock));\n\n\tKCSAN_CHECK_RW_BARRIER(mb());\n\tKCSAN_CHECK_RW_BARRIER(wmb());\n\tKCSAN_CHECK_RW_BARRIER(rmb());\n\tKCSAN_CHECK_RW_BARRIER(smp_mb());\n\tKCSAN_CHECK_RW_BARRIER(smp_wmb());\n\tKCSAN_CHECK_RW_BARRIER(smp_rmb());\n\tKCSAN_CHECK_RW_BARRIER(dma_wmb());\n\tKCSAN_CHECK_RW_BARRIER(dma_rmb());\n\tKCSAN_CHECK_RW_BARRIER(smp_mb__before_atomic());\n\tKCSAN_CHECK_RW_BARRIER(smp_mb__after_atomic());\n\tKCSAN_CHECK_RW_BARRIER(smp_mb__after_spinlock());\n\tKCSAN_CHECK_RW_BARRIER(smp_store_mb(test_var, 0));\n\tKCSAN_CHECK_RW_BARRIER(smp_store_release(&test_var, 0));\n\tKCSAN_CHECK_RW_BARRIER(xchg(&test_var, 0));\n\tKCSAN_CHECK_RW_BARRIER(xchg_release(&test_var, 0));\n\tKCSAN_CHECK_RW_BARRIER(cmpxchg(&test_var, 0,  0));\n\tKCSAN_CHECK_RW_BARRIER(cmpxchg_release(&test_var, 0,  0));\n\tKCSAN_CHECK_RW_BARRIER(atomic_set_release(&dummy, 0));\n\tKCSAN_CHECK_RW_BARRIER(atomic_add_return(1, &dummy));\n\tKCSAN_CHECK_RW_BARRIER(atomic_add_return_release(1, &dummy));\n\tKCSAN_CHECK_RW_BARRIER(atomic_fetch_add(1, &dummy));\n\tKCSAN_CHECK_RW_BARRIER(atomic_fetch_add_release(1, &dummy));\n\tKCSAN_CHECK_RW_BARRIER(test_and_set_bit(0, &test_var));\n\tKCSAN_CHECK_RW_BARRIER(test_and_clear_bit(0, &test_var));\n\tKCSAN_CHECK_RW_BARRIER(test_and_change_bit(0, &test_var));\n\tKCSAN_CHECK_RW_BARRIER(clear_bit_unlock(0, &test_var));\n\tKCSAN_CHECK_RW_BARRIER(__clear_bit_unlock(0, &test_var));\n\tarch_spin_lock(&arch_spinlock);\n\tKCSAN_CHECK_RW_BARRIER(arch_spin_unlock(&arch_spinlock));\n\tspin_lock(&test_spinlock);\n\tKCSAN_CHECK_RW_BARRIER(spin_unlock(&test_spinlock));\n\n#ifdef clear_bit_unlock_is_negative_byte\n\tKCSAN_CHECK_RW_BARRIER(clear_bit_unlock_is_negative_byte(0, &test_var));\n\tKCSAN_CHECK_READ_BARRIER(clear_bit_unlock_is_negative_byte(0, &test_var));\n\tKCSAN_CHECK_WRITE_BARRIER(clear_bit_unlock_is_negative_byte(0, &test_var));\n#endif\n\tkcsan_nestable_atomic_end();\n\n\treturn ret;\n}",
        "static int process_banner_payload(struct ceph_connection *con)\n{\n\tvoid *end = con->v2.in_kvecs[0].iov_base + con->v2.in_kvecs[0].iov_len;\n\tu64 feat = CEPH_MSGR2_SUPPORTED_FEATURES;\n\tu64 req_feat = CEPH_MSGR2_REQUIRED_FEATURES;": "static int process_banner_payload(struct ceph_connection *con)\n{\n\tvoid *end = con->v2.in_kvecs[0].iov_base + con->v2.in_kvecs[0].iov_len;\n\tu64 feat = CEPH_MSGR2_SUPPORTED_FEATURES;\n\tu64 req_feat = CEPH_MSGR2_REQUIRED_FEATURES;\n\tu64 server_feat, server_req_feat;\n\tvoid *p;\n\tint ret;\n\n\tp = con->v2.in_kvecs[0].iov_base;\n\tceph_decode_64_safe(&p, end, server_feat, bad);\n\tceph_decode_64_safe(&p, end, server_req_feat, bad);\n\n\tdout(\"%s con %p server_feat 0x%llx server_req_feat 0x%llx\\n\",\n\t     __func__, con, server_feat, server_req_feat);\n\n\tif (req_feat & ~server_feat) {\n\t\tpr_err(\"msgr2 feature set mismatch: my required > server's supported 0x%llx, need 0x%llx\\n\",\n\t\t       server_feat, req_feat & ~server_feat);\n\t\tcon->error_msg = \"missing required protocol features\";\n\t\treturn -EINVAL;\n\t}\n\tif (server_req_feat & ~feat) {\n\t\tpr_err(\"msgr2 feature set mismatch: server's required > my supported 0x%llx, missing 0x%llx\\n\",\n\t\t       feat, server_req_feat & ~feat);\n\t\tcon->error_msg = \"missing required protocol features\";\n\t\treturn -EINVAL;\n\t}\n\n\t/* no reset_out_kvecs() as our banner may still be pending */\n\tret = prepare_hello(con);\n\tif (ret) {\n\t\tpr_err(\"prepare_hello failed: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tcon->state = CEPH_CON_S_V2_HELLO;\n\tprepare_read_preamble(con);\n\treturn 0;\n\nbad:\n\tpr_err(\"failed to decode banner payload\\n\");\n\treturn -EINVAL;\n}",
        "static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tregister u64 gen_int_mask = 0;\n\tu64 interruptible;": "static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tregister u64 gen_int_mask = 0;\n\tu64 interruptible;\n\n\twriteq(DISABLE_ALL_INTRS, &bar0->general_int_mask);\n\tif (mask & TX_DMA_INTR) {\n\t\tgen_int_mask |= TXDMA_INT_M;\n\n\t\tdo_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |\n\t\t\t\t   TXDMA_PCC_INT | TXDMA_TTI_INT |\n\t\t\t\t   TXDMA_LSO_INT | TXDMA_TPA_INT |\n\t\t\t\t   TXDMA_SM_INT, flag, &bar0->txdma_int_mask);\n\n\t\tdo_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |\n\t\t\t\t   PFC_MISC_0_ERR | PFC_MISC_1_ERR |\n\t\t\t\t   PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,\n\t\t\t\t   &bar0->pfc_err_mask);\n\n\t\tdo_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |\n\t\t\t\t   TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |\n\t\t\t\t   TDA_PCIX_ERR, flag, &bar0->tda_err_mask);\n\n\t\tdo_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |\n\t\t\t\t   PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |\n\t\t\t\t   PCC_N_SERR | PCC_6_COF_OV_ERR |\n\t\t\t\t   PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |\n\t\t\t\t   PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |\n\t\t\t\t   PCC_TXB_ECC_SG_ERR,\n\t\t\t\t   flag, &bar0->pcc_err_mask);\n\n\t\tdo_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |\n\t\t\t\t   TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);\n\n\t\tdo_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |\n\t\t\t\t   LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |\n\t\t\t\t   LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,\n\t\t\t\t   flag, &bar0->lso_err_mask);\n\n\t\tdo_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,\n\t\t\t\t   flag, &bar0->tpa_err_mask);\n\n\t\tdo_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);\n\t}\n\n\tif (mask & TX_MAC_INTR) {\n\t\tgen_int_mask |= TXMAC_INT_M;\n\t\tdo_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,\n\t\t\t\t   &bar0->mac_int_mask);\n\t\tdo_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |\n\t\t\t\t   TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |\n\t\t\t\t   TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,\n\t\t\t\t   flag, &bar0->mac_tmac_err_mask);\n\t}\n\n\tif (mask & TX_XGXS_INTR) {\n\t\tgen_int_mask |= TXXGXS_INT_M;\n\t\tdo_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,\n\t\t\t\t   &bar0->xgxs_int_mask);\n\t\tdo_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |\n\t\t\t\t   TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,\n\t\t\t\t   flag, &bar0->xgxs_txgxs_err_mask);\n\t}\n\n\tif (mask & RX_DMA_INTR) {\n\t\tgen_int_mask |= RXDMA_INT_M;\n\t\tdo_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |\n\t\t\t\t   RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,\n\t\t\t\t   flag, &bar0->rxdma_int_mask);\n\t\tdo_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |\n\t\t\t\t   RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |\n\t\t\t\t   RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |\n\t\t\t\t   RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);\n\t\tdo_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |\n\t\t\t\t   PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |\n\t\t\t\t   PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,\n\t\t\t\t   &bar0->prc_pcix_err_mask);\n\t\tdo_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |\n\t\t\t\t   RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,\n\t\t\t\t   &bar0->rpa_err_mask);\n\t\tdo_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |\n\t\t\t\t   RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |\n\t\t\t\t   RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |\n\t\t\t\t   RDA_FRM_ECC_SG_ERR |\n\t\t\t\t   RDA_MISC_ERR|RDA_PCIX_ERR,\n\t\t\t\t   flag, &bar0->rda_err_mask);\n\t\tdo_s2io_write_bits(RTI_SM_ERR_ALARM |\n\t\t\t\t   RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,\n\t\t\t\t   flag, &bar0->rti_err_mask);\n\t}\n\n\tif (mask & RX_MAC_INTR) {\n\t\tgen_int_mask |= RXMAC_INT_M;\n\t\tdo_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,\n\t\t\t\t   &bar0->mac_int_mask);\n\t\tinterruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |\n\t\t\t\t RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |\n\t\t\t\t RMAC_DOUBLE_ECC_ERR);\n\t\tif (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)\n\t\t\tinterruptible |= RMAC_LINK_STATE_CHANGE_INT;\n\t\tdo_s2io_write_bits(interruptible,\n\t\t\t\t   flag, &bar0->mac_rmac_err_mask);\n\t}\n\n\tif (mask & RX_XGXS_INTR) {\n\t\tgen_int_mask |= RXXGXS_INT_M;\n\t\tdo_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,\n\t\t\t\t   &bar0->xgxs_int_mask);\n\t\tdo_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,\n\t\t\t\t   &bar0->xgxs_rxgxs_err_mask);\n\t}\n\n\tif (mask & MC_INTR) {\n\t\tgen_int_mask |= MC_INT_M;\n\t\tdo_s2io_write_bits(MC_INT_MASK_MC_INT,\n\t\t\t\t   flag, &bar0->mc_int_mask);\n\t\tdo_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |\n\t\t\t\t   MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,\n\t\t\t\t   &bar0->mc_err_mask);\n\t}\n\tnic->general_int_mask = gen_int_mask;\n\n\t/* Remove this line when alarm interrupts are enabled */\n\tnic->general_int_mask = 0;\n}",
        "static int test1_prpw_aligned_4096bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0x6000) & ~(ADI_BLKSZ - 1);": "static int test1_prpw_aligned_4096bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0x6000) & ~(ADI_BLKSZ - 1);\n\tunsigned char version[TEST1_VERSION_SZ],\n\t\texpected_version[TEST1_VERSION_SZ];\n\tloff_t offset;\n\tint ret, i;\n\n\tfor (i = 0; i < TEST1_VERSION_SZ; i++) {\n\t\tversion[i] = random_version();\n\t\texpected_version[i] = version[i];\n\t}\n\n\toffset = paddr / ADI_BLKSZ;\n\n\tret = pwrite_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tret = pread_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tfor (i = 0; i < TEST1_VERSION_SZ; i++) {\n\t\tif (expected_version[i] != version[i]) {\n\t\t\tDEBUG_PRINT_L2(\n\t\t\t\t\"\\tExpected version %d but read version %d\\n\",\n\t\t\t\texpected_version, version[0]);\n\t\t\tTEST_STEP_FAILURE(-expected_version[i]);\n\t\t}\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static void gp_device_rst(const gp_device_ID_t\t\tID)\n{\n\tassert(ID < N_GP_DEVICE_ID);\n\n\tgp_device_reg_store(ID, _REG_GP_SYNCGEN_ENABLE_ADDR, ZERO);": "static void gp_device_rst(const gp_device_ID_t\t\tID)\n{\n\tassert(ID < N_GP_DEVICE_ID);\n\n\tgp_device_reg_store(ID, _REG_GP_SYNCGEN_ENABLE_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNCGEN_FREE_RUNNING_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNCGEN_PAUSE_ADDR, ONE);\n\t// gp_device_reg_store(ID, _REG_GP_NR_FRAMES_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_LINES_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR, ZERO);\n\t// gp_device_reg_store(ID, _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR, ZERO);\n// AM: Following calls cause strange warnings. Probably they should not be initialized.\n//\tgp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ZERO);\n//\tgp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ZERO);\n//\tgp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ZERO);\n//\tgp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_B_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_B_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_MASK_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_MASK_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_XY_CNT_MASK_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_DELTA_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_DELTA_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_MODE_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED1_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN1_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE1_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED2_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN2_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE2_ADDR, ZERO);\n\t//gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO);\n\t//gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO);\n\t//\tgp_device_reg_store(ID, _REG_GP_SYNCGEN_HOR_CNT_ADDR, ZERO);\n\t//\tgp_device_reg_store(ID, _REG_GP_SYNCGEN_VER_CNT_ADDR, ZERO);\n\t//\tgp_device_reg_store(ID, _REG_GP_SYNCGEN_FRAME_CNT_ADDR, ZERO);\n\tgp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR,\n\t\t\t    ZERO); // AM: Maybe this soft reset is not safe.\n}",
        "static int dr_table_create_sw_owned_tbl(struct mlx5dr_table *tbl)\n{\n\tbool en_encap = !!(tbl->flags & MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT);\n\tbool en_decap = !!(tbl->flags & MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);\n\tstruct mlx5dr_cmd_create_flow_table_attr ft_attr = {};": "static int dr_table_create_sw_owned_tbl(struct mlx5dr_table *tbl)\n{\n\tbool en_encap = !!(tbl->flags & MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT);\n\tbool en_decap = !!(tbl->flags & MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);\n\tstruct mlx5dr_cmd_create_flow_table_attr ft_attr = {};\n\tu64 icm_addr_rx = 0;\n\tu64 icm_addr_tx = 0;\n\tint ret;\n\n\tif (tbl->rx.s_anchor)\n\t\ticm_addr_rx = mlx5dr_icm_pool_get_chunk_icm_addr(tbl->rx.s_anchor->chunk);\n\n\tif (tbl->tx.s_anchor)\n\t\ticm_addr_tx = mlx5dr_icm_pool_get_chunk_icm_addr(tbl->tx.s_anchor->chunk);\n\n\tft_attr.table_type = tbl->table_type;\n\tft_attr.icm_addr_rx = icm_addr_rx;\n\tft_attr.icm_addr_tx = icm_addr_tx;\n\tft_attr.level = tbl->dmn->info.caps.max_ft_level - 1;\n\tft_attr.sw_owner = true;\n\tft_attr.decap_en = en_decap;\n\tft_attr.reformat_en = en_encap;\n\n\tret = mlx5dr_cmd_create_flow_table(tbl->dmn->mdev, &ft_attr,\n\t\t\t\t\t   NULL, &tbl->table_id);\n\n\treturn ret;\n}",
        "static int __bpf_array_map_seq_show(struct seq_file *seq, void *v)\n{\n\tstruct bpf_iter_seq_array_map_info *info = seq->private;\n\tstruct bpf_iter__bpf_map_elem ctx = {};\n\tstruct bpf_map *map = info->map;": "static int __bpf_array_map_seq_show(struct seq_file *seq, void *v)\n{\n\tstruct bpf_iter_seq_array_map_info *info = seq->private;\n\tstruct bpf_iter__bpf_map_elem ctx = {};\n\tstruct bpf_map *map = info->map;\n\tstruct bpf_iter_meta meta;\n\tstruct bpf_prog *prog;\n\tint off = 0, cpu = 0;\n\tvoid __percpu **pptr;\n\tu32 size;\n\n\tmeta.seq = seq;\n\tprog = bpf_iter_get_info(&meta, v == NULL);\n\tif (!prog)\n\t\treturn 0;\n\n\tctx.meta = &meta;\n\tctx.map = info->map;\n\tif (v) {\n\t\tctx.key = &info->index;\n\n\t\tif (!info->percpu_value_buf) {\n\t\t\tctx.value = v;\n\t\t} else {\n\t\t\tpptr = v;\n\t\t\tsize = round_up(map->value_size, 8);\n\t\t\tfor_each_possible_cpu(cpu) {\n\t\t\t\tbpf_long_memcpy(info->percpu_value_buf + off,\n\t\t\t\t\t\tper_cpu_ptr(pptr, cpu),\n\t\t\t\t\t\tsize);\n\t\t\t\toff += size;\n\t\t\t}\n\t\t\tctx.value = info->percpu_value_buf;\n\t\t}\n\t}\n\n\treturn bpf_iter_run_prog(prog, &ctx);\n}",
        "static int patch_sigmatel_stac9758(struct snd_ac97 * ac97)\n{\n\tstatic const unsigned short regs[4] = {\n\t\tAC97_SIGMATEL_OUTSEL,\n\t\tAC97_SIGMATEL_IOMISC,": "static int patch_sigmatel_stac9758(struct snd_ac97 * ac97)\n{\n\tstatic const unsigned short regs[4] = {\n\t\tAC97_SIGMATEL_OUTSEL,\n\t\tAC97_SIGMATEL_IOMISC,\n\t\tAC97_SIGMATEL_INSEL,\n\t\tAC97_SIGMATEL_VARIOUS\n\t};\n\tstatic const unsigned short def_regs[4] = {\n\t\t/* OUTSEL */ 0xd794, /* CL:CL, SR:SR, LO:MX, LI:DS, MI:DS */\n\t\t/* IOMISC */ 0x2001,\n\t\t/* INSEL */ 0x0201, /* LI:LI, MI:M1 */\n\t\t/* VARIOUS */ 0x0040\n\t};\n\tstatic const unsigned short m675_regs[4] = {\n\t\t/* OUTSEL */ 0xfc70, /* CL:MX, SR:MX, LO:DS, LI:MX, MI:DS */\n\t\t/* IOMISC */ 0x2102, /* HP amp on */\n\t\t/* INSEL */ 0x0203, /* LI:LI, MI:FR */\n\t\t/* VARIOUS */ 0x0041 /* stereo mic */\n\t};\n\tconst unsigned short *pregs = def_regs;\n\tint i;\n\n\t/* Gateway M675 notebook */\n\tif (ac97->pci && \n\t    ac97->subsystem_vendor == 0x107b &&\n\t    ac97->subsystem_device == 0x0601)\n\t    \tpregs = m675_regs;\n\n\t// patch for SigmaTel\n\tac97->build_ops = &patch_sigmatel_stac9758_ops;\n\t/* FIXME: assume only page 0 for writing cache */\n\tsnd_ac97_update_bits(ac97, AC97_INT_PAGING, AC97_PAGE_MASK, AC97_PAGE_VENDOR);\n\tfor (i = 0; i < 4; i++)\n\t\tsnd_ac97_write_cache(ac97, regs[i], pregs[i]);\n\n\tac97->flags |= AC97_STEREO_MUTES;\n\treturn 0;\n}",
        "static int do_check_common(struct bpf_verifier_env *env, int subprog)\n{\n\tbool pop_log = !(env->log.level & BPF_LOG_LEVEL2);\n\tstruct bpf_verifier_state *state;\n\tstruct bpf_reg_state *regs;": "static int do_check_common(struct bpf_verifier_env *env, int subprog)\n{\n\tbool pop_log = !(env->log.level & BPF_LOG_LEVEL2);\n\tstruct bpf_verifier_state *state;\n\tstruct bpf_reg_state *regs;\n\tint ret, i;\n\n\tenv->prev_linfo = NULL;\n\tenv->pass_cnt++;\n\n\tstate = kzalloc(sizeof(struct bpf_verifier_state), GFP_KERNEL);\n\tif (!state)\n\t\treturn -ENOMEM;\n\tstate->curframe = 0;\n\tstate->speculative = false;\n\tstate->branches = 1;\n\tstate->frame[0] = kzalloc(sizeof(struct bpf_func_state), GFP_KERNEL);\n\tif (!state->frame[0]) {\n\t\tkfree(state);\n\t\treturn -ENOMEM;\n\t}\n\tenv->cur_state = state;\n\tinit_func_state(env, state->frame[0],\n\t\t\tBPF_MAIN_FUNC /* callsite */,\n\t\t\t0 /* frameno */,\n\t\t\tsubprog);\n\n\tregs = state->frame[state->curframe]->regs;\n\tif (subprog || env->prog->type == BPF_PROG_TYPE_EXT) {\n\t\tret = btf_prepare_func_args(env, subprog, regs);\n\t\tif (ret)\n\t\t\tgoto out;\n\t\tfor (i = BPF_REG_1; i <= BPF_REG_5; i++) {\n\t\t\tif (regs[i].type == PTR_TO_CTX)\n\t\t\t\tmark_reg_known_zero(env, regs, i);\n\t\t\telse if (regs[i].type == SCALAR_VALUE)\n\t\t\t\tmark_reg_unknown(env, regs, i);\n\t\t\telse if (base_type(regs[i].type) == PTR_TO_MEM) {\n\t\t\t\tconst u32 mem_size = regs[i].mem_size;\n\n\t\t\t\tmark_reg_known_zero(env, regs, i);\n\t\t\t\tregs[i].mem_size = mem_size;\n\t\t\t\tregs[i].id = ++env->id_gen;\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/* 1st arg to a function */\n\t\tregs[BPF_REG_1].type = PTR_TO_CTX;\n\t\tmark_reg_known_zero(env, regs, BPF_REG_1);\n\t\tret = btf_check_subprog_arg_match(env, subprog, regs);\n\t\tif (ret == -EFAULT)\n\t\t\t/* unlikely verifier bug. abort.\n\t\t\t * ret == 0 and ret < 0 are sadly acceptable for\n\t\t\t * main() function due to backward compatibility.\n\t\t\t * Like socket filter program may be written as:\n\t\t\t * int bpf_prog(struct pt_regs *ctx)\n\t\t\t * and never dereference that ctx in the program.\n\t\t\t * 'struct pt_regs' is a type mismatch for socket\n\t\t\t * filter that should be using 'struct __sk_buff'.\n\t\t\t */\n\t\t\tgoto out;\n\t}\n\n\tret = do_check(env);\nout:\n\t/* check for NULL is necessary, since cur_state can be freed inside\n\t * do_check() under memory pressure.\n\t */\n\tif (env->cur_state) {\n\t\tfree_verifier_state(env->cur_state, true);\n\t\tenv->cur_state = NULL;\n\t}\n\twhile (!pop_stack(env, NULL, NULL, false));\n\tif (!ret && pop_log)\n\t\tbpf_vlog_reset(&env->log, 0);\n\tfree_states(env);\n\treturn ret;\n}",
        "static void collapse_max_ptes_swap(void)\n{\n\tint max_ptes_swap = read_num(\"khugepaged/max_ptes_swap\");\n\tvoid *p;\n": "static void collapse_max_ptes_swap(void)\n{\n\tint max_ptes_swap = read_num(\"khugepaged/max_ptes_swap\");\n\tvoid *p;\n\n\tp = alloc_mapping();\n\n\tfill_memory(p, 0, hpage_pmd_size);\n\tprintf(\"Swapout %d of %d pages...\", max_ptes_swap + 1, hpage_pmd_nr);\n\tif (madvise(p, (max_ptes_swap + 1) * page_size, MADV_PAGEOUT)) {\n\t\tperror(\"madvise(MADV_PAGEOUT)\");\n\t\texit(EXIT_FAILURE);\n\t}\n\tif (check_swap(p, (max_ptes_swap + 1) * page_size)) {\n\t\tsuccess(\"OK\");\n\t} else {\n\t\tfail(\"Fail\");\n\t\tgoto out;\n\t}\n\n\tif (wait_for_scan(\"Do not collapse with max_ptes_swap exceeded\", p))\n\t\tfail(\"Timeout\");\n\telse if (check_huge(p))\n\t\tfail(\"Fail\");\n\telse\n\t\tsuccess(\"OK\");\n\tvalidate_memory(p, 0, hpage_pmd_size);\n\n\tfill_memory(p, 0, hpage_pmd_size);\n\tprintf(\"Swapout %d of %d pages...\", max_ptes_swap, hpage_pmd_nr);\n\tif (madvise(p, max_ptes_swap * page_size, MADV_PAGEOUT)) {\n\t\tperror(\"madvise(MADV_PAGEOUT)\");\n\t\texit(EXIT_FAILURE);\n\t}\n\tif (check_swap(p, max_ptes_swap * page_size)) {\n\t\tsuccess(\"OK\");\n\t} else {\n\t\tfail(\"Fail\");\n\t\tgoto out;\n\t}\n\n\tif (wait_for_scan(\"Collapse with max_ptes_swap pages swapped out\", p))\n\t\tfail(\"Timeout\");\n\telse if (check_huge(p))\n\t\tsuccess(\"OK\");\n\telse\n\t\tfail(\"Fail\");\n\tvalidate_memory(p, 0, hpage_pmd_size);\nout:\n\tmunmap(p, hpage_pmd_size);\n}",
        "static void pipapo_lt_bits_adjust(struct nft_pipapo_field *f)\n{\n\tunsigned long *new_lt;\n\tint groups, bb;\n\tsize_t lt_size;": "static void pipapo_lt_bits_adjust(struct nft_pipapo_field *f)\n{\n\tunsigned long *new_lt;\n\tint groups, bb;\n\tsize_t lt_size;\n\n\tlt_size = f->groups * NFT_PIPAPO_BUCKETS(f->bb) * f->bsize *\n\t\t  sizeof(*f->lt);\n\n\tif (f->bb == NFT_PIPAPO_GROUP_BITS_SMALL_SET &&\n\t    lt_size > NFT_PIPAPO_LT_SIZE_HIGH) {\n\t\tgroups = f->groups * 2;\n\t\tbb = NFT_PIPAPO_GROUP_BITS_LARGE_SET;\n\n\t\tlt_size = groups * NFT_PIPAPO_BUCKETS(bb) * f->bsize *\n\t\t\t  sizeof(*f->lt);\n\t} else if (f->bb == NFT_PIPAPO_GROUP_BITS_LARGE_SET &&\n\t\t   lt_size < NFT_PIPAPO_LT_SIZE_LOW) {\n\t\tgroups = f->groups / 2;\n\t\tbb = NFT_PIPAPO_GROUP_BITS_SMALL_SET;\n\n\t\tlt_size = groups * NFT_PIPAPO_BUCKETS(bb) * f->bsize *\n\t\t\t  sizeof(*f->lt);\n\n\t\t/* Don't increase group width if the resulting lookup table size\n\t\t * would exceed the upper size threshold for a \"small\" set.\n\t\t */\n\t\tif (lt_size > NFT_PIPAPO_LT_SIZE_HIGH)\n\t\t\treturn;\n\t} else {\n\t\treturn;\n\t}\n\n\tnew_lt = kvzalloc(lt_size + NFT_PIPAPO_ALIGN_HEADROOM, GFP_KERNEL);\n\tif (!new_lt)\n\t\treturn;\n\n\tNFT_PIPAPO_GROUP_BITS_ARE_8_OR_4;\n\tif (f->bb == 4 && bb == 8) {\n\t\tpipapo_lt_4b_to_8b(f->groups, f->bsize,\n\t\t\t\t   NFT_PIPAPO_LT_ALIGN(f->lt),\n\t\t\t\t   NFT_PIPAPO_LT_ALIGN(new_lt));\n\t} else if (f->bb == 8 && bb == 4) {\n\t\tpipapo_lt_8b_to_4b(f->groups, f->bsize,\n\t\t\t\t   NFT_PIPAPO_LT_ALIGN(f->lt),\n\t\t\t\t   NFT_PIPAPO_LT_ALIGN(new_lt));\n\t} else {\n\t\tBUG();\n\t}\n\n\tf->groups = groups;\n\tf->bb = bb;\n\tkvfree(f->lt);\n\tNFT_PIPAPO_LT_ASSIGN(f, new_lt);\n}",
        "static void snd_soc_tplg_test_load_empty_tplg_bad_payload_size(struct kunit *test)\n{\n\tstruct kunit_soc_component *kunit_comp;\n\tstruct tplg_tmpl_001 *data;\n\tint size;": "static void snd_soc_tplg_test_load_empty_tplg_bad_payload_size(struct kunit *test)\n{\n\tstruct kunit_soc_component *kunit_comp;\n\tstruct tplg_tmpl_001 *data;\n\tint size;\n\tint ret;\n\n\t/* prepare */\n\tkunit_comp = kunit_kzalloc(test, sizeof(*kunit_comp), GFP_KERNEL);\n\tKUNIT_EXPECT_NOT_ERR_OR_NULL(test, kunit_comp);\n\tkunit_comp->kunit = test;\n\tkunit_comp->expect = -EINVAL; /* expect failure */\n\n\tsize = sizeof(tplg_tmpl_empty);\n\tdata = kunit_kzalloc(kunit_comp->kunit, size, GFP_KERNEL);\n\tKUNIT_EXPECT_NOT_ERR_OR_NULL(kunit_comp->kunit, data);\n\n\tmemcpy(data, &tplg_tmpl_empty, sizeof(tplg_tmpl_empty));\n\t/*\n\t * override payload size\n\t * there is only explicit check for 0, so check with it, other values\n\t * are handled by just not reading behind EOF\n\t */\n\tdata->header.payload_size = 0;\n\n\tkunit_comp->fw.data = (u8 *)data;\n\tkunit_comp->fw.size = size;\n\n\tkunit_comp->card.dev = test_dev,\n\tkunit_comp->card.name = \"kunit-card\",\n\tkunit_comp->card.owner = THIS_MODULE,\n\tkunit_comp->card.dai_link = kunit_dai_links,\n\tkunit_comp->card.num_links = ARRAY_SIZE(kunit_dai_links),\n\tkunit_comp->card.fully_routed = true,\n\n\t/* run test */\n\tret = snd_soc_register_card(&kunit_comp->card);\n\tif (ret != 0 && ret != -EPROBE_DEFER)\n\t\tKUNIT_FAIL(test, \"Failed to register card\");\n\n\tret = snd_soc_component_initialize(&kunit_comp->comp, &test_component, test_dev);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\tret = snd_soc_add_component(&kunit_comp->comp, NULL, 0);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\t/* cleanup */\n\tsnd_soc_unregister_component(test_dev);\n\n\tret = snd_soc_unregister_card(&kunit_comp->card);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n}",
        "static struct sk_buff *tls_sw_fallback(struct sock *sk, struct sk_buff *skb)\n{\n\tint tcp_payload_offset = skb_transport_offset(skb) + tcp_hdrlen(skb);\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_offload_context_tx *ctx = tls_offload_ctx_tx(tls_ctx);": "static struct sk_buff *tls_sw_fallback(struct sock *sk, struct sk_buff *skb)\n{\n\tint tcp_payload_offset = skb_transport_offset(skb) + tcp_hdrlen(skb);\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_offload_context_tx *ctx = tls_offload_ctx_tx(tls_ctx);\n\tint payload_len = skb->len - tcp_payload_offset;\n\tstruct scatterlist *sg_in, sg_out[3];\n\tstruct sk_buff *nskb = NULL;\n\tint sg_in_max_elements;\n\tint resync_sgs = 0;\n\ts32 sync_size = 0;\n\tu64 rcd_sn;\n\n\t/* worst case is:\n\t * MAX_SKB_FRAGS in tls_record_info\n\t * MAX_SKB_FRAGS + 1 in SKB head and frags.\n\t */\n\tsg_in_max_elements = 2 * MAX_SKB_FRAGS + 1;\n\n\tif (!payload_len)\n\t\treturn skb;\n\n\tsg_in = kmalloc_array(sg_in_max_elements, sizeof(*sg_in), GFP_ATOMIC);\n\tif (!sg_in)\n\t\tgoto free_orig;\n\n\tsg_init_table(sg_in, sg_in_max_elements);\n\tsg_init_table(sg_out, ARRAY_SIZE(sg_out));\n\n\tif (fill_sg_in(sg_in, skb, ctx, &rcd_sn, &sync_size, &resync_sgs)) {\n\t\t/* bypass packets before kernel TLS socket option was set */\n\t\tif (sync_size < 0 && payload_len <= -sync_size)\n\t\t\tnskb = skb_get(skb);\n\t\tgoto put_sg;\n\t}\n\n\tnskb = tls_enc_skb(tls_ctx, sg_out, sg_in, skb, sync_size, rcd_sn);\n\nput_sg:\n\twhile (resync_sgs)\n\t\tput_page(sg_page(&sg_in[--resync_sgs]));\n\tkfree(sg_in);\nfree_orig:\n\tif (nskb)\n\t\tconsume_skb(skb);\n\telse\n\t\tkfree_skb(skb);\n\treturn nskb;\n}",
        "static int test_cgcore_lesser_euid_open(const char *root)\n{\n\tconst uid_t test_euid = 65534;\t/* usually nobody, any !root is fine */\n\tint ret = KSFT_FAIL;\n\tchar *cg_test_a = NULL, *cg_test_b = NULL;": "static int test_cgcore_lesser_euid_open(const char *root)\n{\n\tconst uid_t test_euid = 65534;\t/* usually nobody, any !root is fine */\n\tint ret = KSFT_FAIL;\n\tchar *cg_test_a = NULL, *cg_test_b = NULL;\n\tchar *cg_test_a_procs = NULL, *cg_test_b_procs = NULL;\n\tint cg_test_b_procs_fd = -1;\n\tuid_t saved_uid;\n\n\tcg_test_a = cg_name(root, \"cg_test_a\");\n\tcg_test_b = cg_name(root, \"cg_test_b\");\n\n\tif (!cg_test_a || !cg_test_b)\n\t\tgoto cleanup;\n\n\tcg_test_a_procs = cg_name(cg_test_a, \"cgroup.procs\");\n\tcg_test_b_procs = cg_name(cg_test_b, \"cgroup.procs\");\n\n\tif (!cg_test_a_procs || !cg_test_b_procs)\n\t\tgoto cleanup;\n\n\tif (cg_create(cg_test_a) || cg_create(cg_test_b))\n\t\tgoto cleanup;\n\n\tif (cg_enter_current(cg_test_a))\n\t\tgoto cleanup;\n\n\tif (chown(cg_test_a_procs, test_euid, -1) ||\n\t    chown(cg_test_b_procs, test_euid, -1))\n\t\tgoto cleanup;\n\n\tsaved_uid = geteuid();\n\tif (seteuid(test_euid))\n\t\tgoto cleanup;\n\n\tcg_test_b_procs_fd = open(cg_test_b_procs, O_RDWR);\n\n\tif (seteuid(saved_uid))\n\t\tgoto cleanup;\n\n\tif (cg_test_b_procs_fd < 0)\n\t\tgoto cleanup;\n\n\tif (write(cg_test_b_procs_fd, \"0\", 1) >= 0 || errno != EACCES)\n\t\tgoto cleanup;\n\n\tret = KSFT_PASS;\n\ncleanup:\n\tcg_enter_current(root);\n\tif (cg_test_b_procs_fd >= 0)\n\t\tclose(cg_test_b_procs_fd);\n\tif (cg_test_b)\n\t\tcg_destroy(cg_test_b);\n\tif (cg_test_a)\n\t\tcg_destroy(cg_test_a);\n\tfree(cg_test_b_procs);\n\tfree(cg_test_a_procs);\n\tfree(cg_test_b);\n\tfree(cg_test_a);\n\treturn ret;\n}",
        "static int get_mem_bw_imc(int cpu_no, char *bw_report, float *bw_imc)\n{\n\tfloat reads, writes, of_mul_read, of_mul_write;\n\tint imc, j, ret;\n": "static int get_mem_bw_imc(int cpu_no, char *bw_report, float *bw_imc)\n{\n\tfloat reads, writes, of_mul_read, of_mul_write;\n\tint imc, j, ret;\n\n\t/* Start all iMC counters to log values (both read and write) */\n\treads = 0, writes = 0, of_mul_read = 1, of_mul_write = 1;\n\tfor (imc = 0; imc < imcs; imc++) {\n\t\tfor (j = 0; j < 2; j++) {\n\t\t\tret = open_perf_event(imc, cpu_no, j);\n\t\t\tif (ret)\n\t\t\t\treturn -1;\n\t\t}\n\t\tfor (j = 0; j < 2; j++)\n\t\t\tmembw_ioctl_perf_event_ioc_reset_enable(imc, j);\n\t}\n\n\tsleep(1);\n\n\t/* Stop counters after a second to get results (both read and write) */\n\tfor (imc = 0; imc < imcs; imc++) {\n\t\tfor (j = 0; j < 2; j++)\n\t\t\tmembw_ioctl_perf_event_ioc_disable(imc, j);\n\t}\n\n\t/*\n\t * Get results which are stored in struct type imc_counter_config\n\t * Take over flow into consideration before calculating total b/w\n\t */\n\tfor (imc = 0; imc < imcs; imc++) {\n\t\tstruct imc_counter_config *r =\n\t\t\t&imc_counters_config[imc][READ];\n\t\tstruct imc_counter_config *w =\n\t\t\t&imc_counters_config[imc][WRITE];\n\n\t\tif (read(r->fd, &r->return_value,\n\t\t\t sizeof(struct membw_read_format)) == -1) {\n\t\t\tperror(\"Couldn't get read b/w through iMC\");\n\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (read(w->fd, &w->return_value,\n\t\t\t sizeof(struct membw_read_format)) == -1) {\n\t\t\tperror(\"Couldn't get write bw through iMC\");\n\n\t\t\treturn -1;\n\t\t}\n\n\t\t__u64 r_time_enabled = r->return_value.time_enabled;\n\t\t__u64 r_time_running = r->return_value.time_running;\n\n\t\tif (r_time_enabled != r_time_running)\n\t\t\tof_mul_read = (float)r_time_enabled /\n\t\t\t\t\t(float)r_time_running;\n\n\t\t__u64 w_time_enabled = w->return_value.time_enabled;\n\t\t__u64 w_time_running = w->return_value.time_running;\n\n\t\tif (w_time_enabled != w_time_running)\n\t\t\tof_mul_write = (float)w_time_enabled /\n\t\t\t\t\t(float)w_time_running;\n\t\treads += r->return_value.value * of_mul_read * SCALE;\n\t\twrites += w->return_value.value * of_mul_write * SCALE;\n\t}\n\n\tfor (imc = 0; imc < imcs; imc++) {\n\t\tclose(imc_counters_config[imc][READ].fd);\n\t\tclose(imc_counters_config[imc][WRITE].fd);\n\t}\n\n\tif (strcmp(bw_report, \"reads\") == 0) {\n\t\t*bw_imc = reads;\n\t\treturn 0;\n\t}\n\n\tif (strcmp(bw_report, \"writes\") == 0) {\n\t\t*bw_imc = writes;\n\t\treturn 0;\n\t}\n\n\t*bw_imc = reads + writes;\n\treturn 0;\n}",
        "static int vp9_update_header(struct amvdec_core *core, struct vb2_buffer *buf)\n{\n\tu8 *dp;\n\tu8 marker;\n\tint dsize;": "static int vp9_update_header(struct amvdec_core *core, struct vb2_buffer *buf)\n{\n\tu8 *dp;\n\tu8 marker;\n\tint dsize;\n\tint num_frames, cur_frame;\n\tint cur_mag, mag, mag_ptr;\n\tint frame_size[8], tot_frame_size[8];\n\tint total_datasize = 0;\n\tint new_frame_size;\n\tunsigned char *old_header = NULL;\n\n\tdp = (uint8_t *)vb2_plane_vaddr(buf, 0);\n\tdsize = vb2_get_plane_payload(buf, 0);\n\n\tif (dsize == vb2_plane_size(buf, 0)) {\n\t\tdev_warn(core->dev, \"%s: unable to update header\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tmarker = dp[dsize - 1];\n\tif ((marker & 0xe0) == 0xc0) {\n\t\tnum_frames = (marker & 0x7) + 1;\n\t\tmag = ((marker >> 3) & 0x3) + 1;\n\t\tmag_ptr = dsize - mag * num_frames - 2;\n\t\tif (dp[mag_ptr] != marker)\n\t\t\treturn 0;\n\n\t\tmag_ptr++;\n\t\tfor (cur_frame = 0; cur_frame < num_frames; cur_frame++) {\n\t\t\tframe_size[cur_frame] = 0;\n\t\t\tfor (cur_mag = 0; cur_mag < mag; cur_mag++) {\n\t\t\t\tframe_size[cur_frame] |=\n\t\t\t\t\t(dp[mag_ptr] << (cur_mag * 8));\n\t\t\t\tmag_ptr++;\n\t\t\t}\n\t\t\tif (cur_frame == 0)\n\t\t\t\ttot_frame_size[cur_frame] =\n\t\t\t\t\tframe_size[cur_frame];\n\t\t\telse\n\t\t\t\ttot_frame_size[cur_frame] =\n\t\t\t\t\ttot_frame_size[cur_frame - 1] +\n\t\t\t\t\tframe_size[cur_frame];\n\t\t\ttotal_datasize += frame_size[cur_frame];\n\t\t}\n\t} else {\n\t\tnum_frames = 1;\n\t\tframe_size[0] = dsize;\n\t\ttot_frame_size[0] = dsize;\n\t\ttotal_datasize = dsize;\n\t}\n\n\tnew_frame_size = total_datasize + num_frames * VP9_HEADER_SIZE;\n\n\tif (new_frame_size >= vb2_plane_size(buf, 0)) {\n\t\tdev_warn(core->dev, \"%s: unable to update header\\n\", __func__);\n\t\treturn 0;\n\t}\n\n\tfor (cur_frame = num_frames - 1; cur_frame >= 0; cur_frame--) {\n\t\tint framesize = frame_size[cur_frame];\n\t\tint framesize_header = framesize + 4;\n\t\tint oldframeoff = tot_frame_size[cur_frame] - framesize;\n\t\tint outheaderoff =  oldframeoff + cur_frame * VP9_HEADER_SIZE;\n\t\tu8 *fdata = dp + outheaderoff;\n\t\tu8 *old_framedata = dp + oldframeoff;\n\n\t\tmemmove(fdata + VP9_HEADER_SIZE, old_framedata, framesize);\n\n\t\tfdata[0] = (framesize_header >> 24) & 0xff;\n\t\tfdata[1] = (framesize_header >> 16) & 0xff;\n\t\tfdata[2] = (framesize_header >> 8) & 0xff;\n\t\tfdata[3] = (framesize_header >> 0) & 0xff;\n\t\tfdata[4] = ((framesize_header >> 24) & 0xff) ^ 0xff;\n\t\tfdata[5] = ((framesize_header >> 16) & 0xff) ^ 0xff;\n\t\tfdata[6] = ((framesize_header >> 8) & 0xff) ^ 0xff;\n\t\tfdata[7] = ((framesize_header >> 0) & 0xff) ^ 0xff;\n\t\tfdata[8] = 0;\n\t\tfdata[9] = 0;\n\t\tfdata[10] = 0;\n\t\tfdata[11] = 1;\n\t\tfdata[12] = 'A';\n\t\tfdata[13] = 'M';\n\t\tfdata[14] = 'L';\n\t\tfdata[15] = 'V';\n\n\t\tif (!old_header) {\n\t\t\t/* nothing */\n\t\t} else if (old_header > fdata + 16 + framesize) {\n\t\t\tdev_dbg(core->dev, \"%s: data has gaps, setting to 0\\n\",\n\t\t\t\t__func__);\n\t\t\tmemset(fdata + 16 + framesize, 0,\n\t\t\t       (old_header - fdata + 16 + framesize));\n\t\t} else if (old_header < fdata + 16 + framesize) {\n\t\t\tdev_err(core->dev, \"%s: data overwritten\\n\", __func__);\n\t\t}\n\t\told_header = fdata;\n\t}\n\n\treturn new_frame_size;\n}",
        "static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)\n{\n\tu8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;\n\tu32 reg_function_hide, tmp, eng_mask, low_pfs_mask;\n\tstruct qed_dev *cdev = p_hwfn->cdev;": "static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)\n{\n\tu8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;\n\tu32 reg_function_hide, tmp, eng_mask, low_pfs_mask;\n\tstruct qed_dev *cdev = p_hwfn->cdev;\n\n\tnum_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;\n\n\t/* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values\n\t * in the other bits are selected.\n\t * Bits 1-15 are for functions 1-15, respectively, and their value is\n\t * '0' only for enabled functions (function 0 always exists and\n\t * enabled).\n\t * In case of CMT, only the \"even\" functions are enabled, and thus the\n\t * number of functions for both hwfns is learnt from the same bits.\n\t */\n\treg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);\n\n\tif (reg_function_hide & 0x1) {\n\t\tif (QED_IS_BB(cdev)) {\n\t\t\tif (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {\n\t\t\t\tnum_funcs = 0;\n\t\t\t\teng_mask = 0xaaaa;\n\t\t\t} else {\n\t\t\t\tnum_funcs = 1;\n\t\t\t\teng_mask = 0x5554;\n\t\t\t}\n\t\t} else {\n\t\t\tnum_funcs = 1;\n\t\t\teng_mask = 0xfffe;\n\t\t}\n\n\t\t/* Get the number of the enabled functions on the engine */\n\t\ttmp = (reg_function_hide ^ 0xffffffff) & eng_mask;\n\t\twhile (tmp) {\n\t\t\tif (tmp & 0x1)\n\t\t\t\tnum_funcs++;\n\t\t\ttmp >>= 0x1;\n\t\t}\n\n\t\t/* Get the PF index within the enabled functions */\n\t\tlow_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;\n\t\ttmp = reg_function_hide & eng_mask & low_pfs_mask;\n\t\twhile (tmp) {\n\t\t\tif (tmp & 0x1)\n\t\t\t\tenabled_func_idx--;\n\t\t\ttmp >>= 0x1;\n\t\t}\n\t}\n\n\tp_hwfn->num_funcs_on_engine = num_funcs;\n\tp_hwfn->enabled_func_idx = enabled_func_idx;\n\n\tDP_VERBOSE(p_hwfn,\n\t\t   NETIF_MSG_PROBE,\n\t\t   \"PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\\n\",\n\t\t   p_hwfn->rel_pf_id,\n\t\t   p_hwfn->abs_pf_id,\n\t\t   p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);\n}",
        "static void set_ref_pic_list(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tconst struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;": "static void set_ref_pic_list(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tconst struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;\n\tu32 list0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};\n\tu32 list1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};\n\tstatic const struct hantro_reg ref_pic_regs0[] = {\n\t\thevc_rlist_f0,\n\t\thevc_rlist_f1,\n\t\thevc_rlist_f2,\n\t\thevc_rlist_f3,\n\t\thevc_rlist_f4,\n\t\thevc_rlist_f5,\n\t\thevc_rlist_f6,\n\t\thevc_rlist_f7,\n\t\thevc_rlist_f8,\n\t\thevc_rlist_f9,\n\t\thevc_rlist_f10,\n\t\thevc_rlist_f11,\n\t\thevc_rlist_f12,\n\t\thevc_rlist_f13,\n\t\thevc_rlist_f14,\n\t\thevc_rlist_f15,\n\t};\n\tstatic const struct hantro_reg ref_pic_regs1[] = {\n\t\thevc_rlist_b0,\n\t\thevc_rlist_b1,\n\t\thevc_rlist_b2,\n\t\thevc_rlist_b3,\n\t\thevc_rlist_b4,\n\t\thevc_rlist_b5,\n\t\thevc_rlist_b6,\n\t\thevc_rlist_b7,\n\t\thevc_rlist_b8,\n\t\thevc_rlist_b9,\n\t\thevc_rlist_b10,\n\t\thevc_rlist_b11,\n\t\thevc_rlist_b12,\n\t\thevc_rlist_b13,\n\t\thevc_rlist_b14,\n\t\thevc_rlist_b15,\n\t};\n\tunsigned int i, j;\n\n\t/* List 0 contains: short term before, short term after and long term */\n\tj = 0;\n\tfor (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list0); i++)\n\t\tlist0[j++] = decode_params->poc_st_curr_before[i];\n\tfor (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list0); i++)\n\t\tlist0[j++] = decode_params->poc_st_curr_after[i];\n\tfor (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list0); i++)\n\t\tlist0[j++] = decode_params->poc_lt_curr[i];\n\n\t/* Fill the list, copying over and over */\n\ti = 0;\n\twhile (j < ARRAY_SIZE(list0))\n\t\tlist0[j++] = list0[i++];\n\n\tj = 0;\n\tfor (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list1); i++)\n\t\tlist1[j++] = decode_params->poc_st_curr_after[i];\n\tfor (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list1); i++)\n\t\tlist1[j++] = decode_params->poc_st_curr_before[i];\n\tfor (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list1); i++)\n\t\tlist1[j++] = decode_params->poc_lt_curr[i];\n\n\ti = 0;\n\twhile (j < ARRAY_SIZE(list1))\n\t\tlist1[j++] = list1[i++];\n\n\tfor (i = 0; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {\n\t\thantro_reg_write(vpu, &ref_pic_regs0[i], list0[i]);\n\t\thantro_reg_write(vpu, &ref_pic_regs1[i], list1[i]);\n\t}\n}",
        "static void rt1719_update_operating_status(struct rt1719_data *data)\n{\n\tenum power_supply_usb_type usb_type = POWER_SUPPLY_USB_TYPE_PD;\n\tu32 voltage, max_current, op_current;\n\tint i, snk_sel;": "static void rt1719_update_operating_status(struct rt1719_data *data)\n{\n\tenum power_supply_usb_type usb_type = POWER_SUPPLY_USB_TYPE_PD;\n\tu32 voltage, max_current, op_current;\n\tint i, snk_sel;\n\n\tfor (i = 0; i < data->spdo_num; i++) {\n\t\tu32 pdo = data->spdos[i];\n\t\tenum pd_pdo_type type = pdo_type(pdo);\n\n\t\tif (type == PDO_TYPE_APDO) {\n\t\t\tusb_type = POWER_SUPPLY_USB_TYPE_PD_PPS;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tdata->spdo_sel = FIELD_GET(RT1719_SPDOSEL_MASK, data->conn_info);\n\tif (data->spdo_sel <= 0)\n\t\treturn;\n\n\tdata->usb_type = usb_type;\n\n\tvoltage = pdo_fixed_voltage(data->spdos[data->spdo_sel - 1]);\n\tmax_current = pdo_max_current(data->spdos[data->spdo_sel - 1]);\n\n\tswitch (voltage) {\n\tcase 5000:\n\t\tsnk_sel = RT1719_SNKCAP_5V;\n\t\tbreak;\n\tcase 9000:\n\t\tsnk_sel = RT1719_SNKCAP_9V;\n\t\tbreak;\n\tcase 12000:\n\t\tsnk_sel = RT1719_SNKCAP_12V;\n\t\tbreak;\n\tcase 15000:\n\t\tsnk_sel = RT1719_SNKCAP_15V;\n\t\tbreak;\n\tcase 20000:\n\t\tsnk_sel = RT1719_SNKCAP_20V;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\top_current = min(max_current, pdo_max_current(data->snkcaps[snk_sel]));\n\n\t/* covert mV/mA to uV/uA */\n\tdata->voltage = voltage * 1000;\n\tdata->max_current = max_current * 1000;\n\tdata->op_current = op_current * 1000;\n\n\tpower_supply_changed(data->psy);\n}",
        "static void mtdswap_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd)\n{\n\tstruct mtdswap_dev *d;\n\tstruct mtd_blktrans_dev *mbd_dev;\n\tchar *parts;": "static void mtdswap_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd)\n{\n\tstruct mtdswap_dev *d;\n\tstruct mtd_blktrans_dev *mbd_dev;\n\tchar *parts;\n\tchar *this_opt;\n\tunsigned long part;\n\tunsigned int eblocks, eavailable, bad_blocks, spare_cnt;\n\tuint64_t swap_size, use_size, size_limit;\n\tint ret;\n\n\tparts = &partitions[0];\n\tif (!*parts)\n\t\treturn;\n\n\twhile ((this_opt = strsep(&parts, \",\")) != NULL) {\n\t\tif (kstrtoul(this_opt, 0, &part) < 0)\n\t\t\treturn;\n\n\t\tif (mtd->index == part)\n\t\t\tbreak;\n\t}\n\n\tif (mtd->index != part)\n\t\treturn;\n\n\tif (mtd->erasesize < PAGE_SIZE || mtd->erasesize % PAGE_SIZE) {\n\t\tprintk(KERN_ERR \"%s: Erase size %u not multiple of PAGE_SIZE \"\n\t\t\t\"%lu\\n\", MTDSWAP_PREFIX, mtd->erasesize, PAGE_SIZE);\n\t\treturn;\n\t}\n\n\tif (PAGE_SIZE % mtd->writesize || mtd->writesize > PAGE_SIZE) {\n\t\tprintk(KERN_ERR \"%s: PAGE_SIZE %lu not multiple of write size\"\n\t\t\t\" %u\\n\", MTDSWAP_PREFIX, PAGE_SIZE, mtd->writesize);\n\t\treturn;\n\t}\n\n\tif (!mtd->oobsize || mtd->oobavail < MTDSWAP_OOBSIZE) {\n\t\tprintk(KERN_ERR \"%s: Not enough free bytes in OOB, \"\n\t\t\t\"%d available, %zu needed.\\n\",\n\t\t\tMTDSWAP_PREFIX, mtd->oobavail, MTDSWAP_OOBSIZE);\n\t\treturn;\n\t}\n\n\tif (spare_eblocks > 100)\n\t\tspare_eblocks = 100;\n\n\tuse_size = mtd->size;\n\tsize_limit = (uint64_t) BLOCK_MAX * PAGE_SIZE;\n\n\tif (mtd->size > size_limit) {\n\t\tprintk(KERN_WARNING \"%s: Device too large. Limiting size to \"\n\t\t\t\"%llu bytes\\n\", MTDSWAP_PREFIX, size_limit);\n\t\tuse_size = size_limit;\n\t}\n\n\teblocks = mtd_div_by_eb(use_size, mtd);\n\tuse_size = (uint64_t)eblocks * mtd->erasesize;\n\tbad_blocks = mtdswap_badblocks(mtd, use_size);\n\teavailable = eblocks - bad_blocks;\n\n\tif (eavailable < MIN_ERASE_BLOCKS) {\n\t\tprintk(KERN_ERR \"%s: Not enough erase blocks. %u available, \"\n\t\t\t\"%d needed\\n\", MTDSWAP_PREFIX, eavailable,\n\t\t\tMIN_ERASE_BLOCKS);\n\t\treturn;\n\t}\n\n\tspare_cnt = div_u64((uint64_t)eavailable * spare_eblocks, 100);\n\n\tif (spare_cnt < MIN_SPARE_EBLOCKS)\n\t\tspare_cnt = MIN_SPARE_EBLOCKS;\n\n\tif (spare_cnt > eavailable - 1)\n\t\tspare_cnt = eavailable - 1;\n\n\tswap_size = (uint64_t)(eavailable - spare_cnt) * mtd->erasesize +\n\t\t(header ? PAGE_SIZE : 0);\n\n\tprintk(KERN_INFO \"%s: Enabling MTD swap on device %lu, size %llu KB, \"\n\t\t\"%u spare, %u bad blocks\\n\",\n\t\tMTDSWAP_PREFIX, part, swap_size / 1024, spare_cnt, bad_blocks);\n\n\td = kzalloc(sizeof(struct mtdswap_dev), GFP_KERNEL);\n\tif (!d)\n\t\treturn;\n\n\tmbd_dev = kzalloc(sizeof(struct mtd_blktrans_dev), GFP_KERNEL);\n\tif (!mbd_dev) {\n\t\tkfree(d);\n\t\treturn;\n\t}\n\n\td->mbd_dev = mbd_dev;\n\tmbd_dev->priv = d;\n\n\tmbd_dev->mtd = mtd;\n\tmbd_dev->devnum = mtd->index;\n\tmbd_dev->size = swap_size >> PAGE_SHIFT;\n\tmbd_dev->tr = tr;\n\n\tif (!(mtd->flags & MTD_WRITEABLE))\n\t\tmbd_dev->readonly = 1;\n\n\tif (mtdswap_init(d, eblocks, spare_cnt) < 0)\n\t\tgoto init_failed;\n\n\tif (add_mtd_blktrans_dev(mbd_dev) < 0)\n\t\tgoto cleanup;\n\n\td->dev = disk_to_dev(mbd_dev->disk);\n\n\tret = mtdswap_add_debugfs(d);\n\tif (ret < 0)\n\t\tgoto debugfs_failed;\n\n\treturn;\n\ndebugfs_failed:\n\tdel_mtd_blktrans_dev(mbd_dev);\n\ncleanup:\n\tmtdswap_cleanup(d);\n\ninit_failed:\n\tkfree(mbd_dev);\n\tkfree(d);\n}",
        "static int otx2_do_add_macfilter(struct otx2_nic *pf, const u8 *mac)\n{\n\tstruct otx2_flow_config *flow_cfg = pf->flow_cfg;\n\tstruct npc_install_flow_req *req;\n\tint err, i;": "static int otx2_do_add_macfilter(struct otx2_nic *pf, const u8 *mac)\n{\n\tstruct otx2_flow_config *flow_cfg = pf->flow_cfg;\n\tstruct npc_install_flow_req *req;\n\tint err, i;\n\n\tif (!(pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT))\n\t\treturn -ENOMEM;\n\n\t/* dont have free mcam entries or uc list is greater than alloted */\n\tif (netdev_uc_count(pf->netdev) > OTX2_MAX_UNICAST_FLOWS)\n\t\treturn -ENOMEM;\n\n\tmutex_lock(&pf->mbox.lock);\n\treq = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);\n\tif (!req) {\n\t\tmutex_unlock(&pf->mbox.lock);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* unicast offset starts with 32 0..31 for ntuple */\n\tfor (i = 0; i <  OTX2_MAX_UNICAST_FLOWS; i++) {\n\t\tif (pf->mac_table[i].inuse)\n\t\t\tcontinue;\n\t\tether_addr_copy(pf->mac_table[i].addr, mac);\n\t\tpf->mac_table[i].inuse = true;\n\t\tpf->mac_table[i].mcam_entry =\n\t\t\tflow_cfg->def_ent[i + flow_cfg->unicast_offset];\n\t\treq->entry =  pf->mac_table[i].mcam_entry;\n\t\tbreak;\n\t}\n\n\tether_addr_copy(req->packet.dmac, mac);\n\teth_broadcast_addr((u8 *)&req->mask.dmac);\n\treq->features = BIT_ULL(NPC_DMAC);\n\treq->channel = pf->hw.rx_chan_base;\n\treq->intf = NIX_INTF_RX;\n\treq->op = NIX_RX_ACTION_DEFAULT;\n\treq->set_cntr = 1;\n\n\terr = otx2_sync_mbox_msg(&pf->mbox);\n\tmutex_unlock(&pf->mbox.lock);\n\n\treturn err;\n}",
        "static int raid10_check_reshape(struct mddev *mddev)\n{\n\t/* Called when there is a request to change\n\t * - layout (to ->new_layout)\n\t * - chunk size (to ->new_chunk_sectors)": "static int raid10_check_reshape(struct mddev *mddev)\n{\n\t/* Called when there is a request to change\n\t * - layout (to ->new_layout)\n\t * - chunk size (to ->new_chunk_sectors)\n\t * - raid_disks (by delta_disks)\n\t * or when trying to restart a reshape that was ongoing.\n\t *\n\t * We need to validate the request and possibly allocate\n\t * space if that might be an issue later.\n\t *\n\t * Currently we reject any reshape of a 'far' mode array,\n\t * allow chunk size to change if new is generally acceptable,\n\t * allow raid_disks to increase, and allow\n\t * a switch between 'near' mode and 'offset' mode.\n\t */\n\tstruct r10conf *conf = mddev->private;\n\tstruct geom geo;\n\n\tif (conf->geo.far_copies != 1 && !conf->geo.far_offset)\n\t\treturn -EINVAL;\n\n\tif (setup_geo(&geo, mddev, geo_start) != conf->copies)\n\t\t/* mustn't change number of copies */\n\t\treturn -EINVAL;\n\tif (geo.far_copies > 1 && !geo.far_offset)\n\t\t/* Cannot switch to 'far' mode */\n\t\treturn -EINVAL;\n\n\tif (mddev->array_sectors & geo.chunk_mask)\n\t\t\t/* not factor of array size */\n\t\t\treturn -EINVAL;\n\n\tif (!enough(conf, -1))\n\t\treturn -EINVAL;\n\n\tkfree(conf->mirrors_new);\n\tconf->mirrors_new = NULL;\n\tif (mddev->delta_disks > 0) {\n\t\t/* allocate new 'mirrors' list */\n\t\tconf->mirrors_new =\n\t\t\tkcalloc(mddev->raid_disks + mddev->delta_disks,\n\t\t\t\tsizeof(struct raid10_info),\n\t\t\t\tGFP_KERNEL);\n\t\tif (!conf->mirrors_new)\n\t\t\treturn -ENOMEM;\n\t}\n\treturn 0;\n}",
        "static int cit_init_ibm_netcam_pro(struct gspca_dev *gspca_dev)\n{\n\tcit_read_reg(gspca_dev, 0x128, 1);\n\tcit_write_reg(gspca_dev, 0x0003, 0x0133);\n\tcit_write_reg(gspca_dev, 0x0000, 0x0117);": "static int cit_init_ibm_netcam_pro(struct gspca_dev *gspca_dev)\n{\n\tcit_read_reg(gspca_dev, 0x128, 1);\n\tcit_write_reg(gspca_dev, 0x0003, 0x0133);\n\tcit_write_reg(gspca_dev, 0x0000, 0x0117);\n\tcit_write_reg(gspca_dev, 0x0008, 0x0123);\n\tcit_write_reg(gspca_dev, 0x0000, 0x0100);\n\tcit_read_reg(gspca_dev, 0x0116, 0);\n\tcit_write_reg(gspca_dev, 0x0060, 0x0116);\n\tcit_write_reg(gspca_dev, 0x0002, 0x0112);\n\tcit_write_reg(gspca_dev, 0x0000, 0x0133);\n\tcit_write_reg(gspca_dev, 0x0000, 0x0123);\n\tcit_write_reg(gspca_dev, 0x0001, 0x0117);\n\tcit_write_reg(gspca_dev, 0x0040, 0x0108);\n\tcit_write_reg(gspca_dev, 0x0019, 0x012c);\n\tcit_write_reg(gspca_dev, 0x0060, 0x0116);\n\tcit_write_reg(gspca_dev, 0x0002, 0x0115);\n\tcit_write_reg(gspca_dev, 0x000b, 0x0115);\n\n\tcit_write_reg(gspca_dev, 0x0078, 0x012d);\n\tcit_write_reg(gspca_dev, 0x0001, 0x012f);\n\tcit_write_reg(gspca_dev, 0xd141, 0x0124);\n\tcit_write_reg(gspca_dev, 0x0079, 0x012d);\n\tcit_write_reg(gspca_dev, 0x00ff, 0x0130);\n\tcit_write_reg(gspca_dev, 0xcd41, 0x0124);\n\tcit_write_reg(gspca_dev, 0xfffa, 0x0124);\n\tcit_read_reg(gspca_dev, 0x0126, 1);\n\n\tcit_model3_Packet1(gspca_dev, 0x0000, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0000, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x000b, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x000c, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x000d, 0x003a);\n\tcit_model3_Packet1(gspca_dev, 0x000e, 0x0060);\n\tcit_model3_Packet1(gspca_dev, 0x000f, 0x0060);\n\tcit_model3_Packet1(gspca_dev, 0x0010, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x0011, 0x0004);\n\tcit_model3_Packet1(gspca_dev, 0x0012, 0x0028);\n\tcit_model3_Packet1(gspca_dev, 0x0013, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0014, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0015, 0x00fb);\n\tcit_model3_Packet1(gspca_dev, 0x0016, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0017, 0x0037);\n\tcit_model3_Packet1(gspca_dev, 0x0018, 0x0036);\n\tcit_model3_Packet1(gspca_dev, 0x001e, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x001f, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x0020, 0x00c1);\n\tcit_model3_Packet1(gspca_dev, 0x0021, 0x0034);\n\tcit_model3_Packet1(gspca_dev, 0x0022, 0x0034);\n\tcit_model3_Packet1(gspca_dev, 0x0025, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0028, 0x0022);\n\tcit_model3_Packet1(gspca_dev, 0x0029, 0x000a);\n\tcit_model3_Packet1(gspca_dev, 0x002b, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x002c, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x002d, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x002e, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x002f, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x0030, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x0031, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x0032, 0x0007);\n\tcit_model3_Packet1(gspca_dev, 0x0033, 0x0005);\n\tcit_model3_Packet1(gspca_dev, 0x0037, 0x0040);\n\tcit_model3_Packet1(gspca_dev, 0x0039, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x003a, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x003b, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x003c, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0040, 0x000c);\n\tcit_model3_Packet1(gspca_dev, 0x0041, 0x00fb);\n\tcit_model3_Packet1(gspca_dev, 0x0042, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0043, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0045, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0046, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0047, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0048, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0049, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x004a, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x004b, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x004c, 0x00ff);\n\tcit_model3_Packet1(gspca_dev, 0x004f, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0050, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0051, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0055, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0056, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0057, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0058, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x0059, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x005c, 0x0016);\n\tcit_model3_Packet1(gspca_dev, 0x005d, 0x0022);\n\tcit_model3_Packet1(gspca_dev, 0x005e, 0x003c);\n\tcit_model3_Packet1(gspca_dev, 0x005f, 0x0050);\n\tcit_model3_Packet1(gspca_dev, 0x0060, 0x0044);\n\tcit_model3_Packet1(gspca_dev, 0x0061, 0x0005);\n\tcit_model3_Packet1(gspca_dev, 0x006a, 0x007e);\n\tcit_model3_Packet1(gspca_dev, 0x006f, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0072, 0x001b);\n\tcit_model3_Packet1(gspca_dev, 0x0073, 0x0005);\n\tcit_model3_Packet1(gspca_dev, 0x0074, 0x000a);\n\tcit_model3_Packet1(gspca_dev, 0x0075, 0x001b);\n\tcit_model3_Packet1(gspca_dev, 0x0076, 0x002a);\n\tcit_model3_Packet1(gspca_dev, 0x0077, 0x003c);\n\tcit_model3_Packet1(gspca_dev, 0x0078, 0x0050);\n\tcit_model3_Packet1(gspca_dev, 0x007b, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x007c, 0x0011);\n\tcit_model3_Packet1(gspca_dev, 0x007d, 0x0024);\n\tcit_model3_Packet1(gspca_dev, 0x007e, 0x0043);\n\tcit_model3_Packet1(gspca_dev, 0x007f, 0x005a);\n\tcit_model3_Packet1(gspca_dev, 0x0084, 0x0020);\n\tcit_model3_Packet1(gspca_dev, 0x0085, 0x0033);\n\tcit_model3_Packet1(gspca_dev, 0x0086, 0x000a);\n\tcit_model3_Packet1(gspca_dev, 0x0087, 0x0030);\n\tcit_model3_Packet1(gspca_dev, 0x0088, 0x0070);\n\tcit_model3_Packet1(gspca_dev, 0x008b, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x008f, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x0090, 0x0006);\n\tcit_model3_Packet1(gspca_dev, 0x0091, 0x0028);\n\tcit_model3_Packet1(gspca_dev, 0x0092, 0x005a);\n\tcit_model3_Packet1(gspca_dev, 0x0093, 0x0082);\n\tcit_model3_Packet1(gspca_dev, 0x0096, 0x0014);\n\tcit_model3_Packet1(gspca_dev, 0x0097, 0x0020);\n\tcit_model3_Packet1(gspca_dev, 0x0098, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00b0, 0x0046);\n\tcit_model3_Packet1(gspca_dev, 0x00b1, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00b2, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00b3, 0x0004);\n\tcit_model3_Packet1(gspca_dev, 0x00b4, 0x0007);\n\tcit_model3_Packet1(gspca_dev, 0x00b6, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x00b7, 0x0004);\n\tcit_model3_Packet1(gspca_dev, 0x00bb, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00bc, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x00bd, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00bf, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00c0, 0x00c8);\n\tcit_model3_Packet1(gspca_dev, 0x00c1, 0x0014);\n\tcit_model3_Packet1(gspca_dev, 0x00c2, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x00c3, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00c4, 0x0004);\n\tcit_model3_Packet1(gspca_dev, 0x00cb, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00cc, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00cd, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00ce, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00cf, 0x0020);\n\tcit_model3_Packet1(gspca_dev, 0x00d0, 0x0040);\n\tcit_model3_Packet1(gspca_dev, 0x00d1, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00d1, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00d2, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00d3, 0x00bf);\n\tcit_model3_Packet1(gspca_dev, 0x00ea, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x00eb, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00ec, 0x00e8);\n\tcit_model3_Packet1(gspca_dev, 0x00ed, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x00ef, 0x0022);\n\tcit_model3_Packet1(gspca_dev, 0x00f0, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00f2, 0x0028);\n\tcit_model3_Packet1(gspca_dev, 0x00f4, 0x0002);\n\tcit_model3_Packet1(gspca_dev, 0x00f5, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00fa, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00fb, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x00fc, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00fd, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00fe, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00ff, 0x0000);\n\n\tcit_model3_Packet1(gspca_dev, 0x00be, 0x0003);\n\tcit_model3_Packet1(gspca_dev, 0x00c8, 0x0000);\n\tcit_model3_Packet1(gspca_dev, 0x00c9, 0x0020);\n\tcit_model3_Packet1(gspca_dev, 0x00ca, 0x0040);\n\tcit_model3_Packet1(gspca_dev, 0x0053, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x0082, 0x000e);\n\tcit_model3_Packet1(gspca_dev, 0x0083, 0x0020);\n\tcit_model3_Packet1(gspca_dev, 0x0034, 0x003c);\n\tcit_model3_Packet1(gspca_dev, 0x006e, 0x0055);\n\tcit_model3_Packet1(gspca_dev, 0x0062, 0x0005);\n\tcit_model3_Packet1(gspca_dev, 0x0063, 0x0008);\n\tcit_model3_Packet1(gspca_dev, 0x0066, 0x000a);\n\tcit_model3_Packet1(gspca_dev, 0x0067, 0x0006);\n\tcit_model3_Packet1(gspca_dev, 0x006b, 0x0010);\n\tcit_model3_Packet1(gspca_dev, 0x005a, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x005b, 0x000a);\n\tcit_model3_Packet1(gspca_dev, 0x0023, 0x0006);\n\tcit_model3_Packet1(gspca_dev, 0x0026, 0x0004);\n\tcit_model3_Packet1(gspca_dev, 0x0036, 0x0069);\n\tcit_model3_Packet1(gspca_dev, 0x0038, 0x0064);\n\tcit_model3_Packet1(gspca_dev, 0x003d, 0x0003);\n\tcit_model3_Packet1(gspca_dev, 0x003e, 0x0001);\n\tcit_model3_Packet1(gspca_dev, 0x00b8, 0x0014);\n\tcit_model3_Packet1(gspca_dev, 0x00b9, 0x0014);\n\tcit_model3_Packet1(gspca_dev, 0x00e6, 0x0004);\n\tcit_model3_Packet1(gspca_dev, 0x00e8, 0x0001);\n\n\treturn 0;\n}",
        "static void build_mod8_tables(struct bch_control *bch, const uint32_t *g)\n{\n\tint i, j, b, d;\n\tuint32_t data, hi, lo, *tab;\n\tconst int l = BCH_ECC_WORDS(bch);": "static void build_mod8_tables(struct bch_control *bch, const uint32_t *g)\n{\n\tint i, j, b, d;\n\tuint32_t data, hi, lo, *tab;\n\tconst int l = BCH_ECC_WORDS(bch);\n\tconst int plen = DIV_ROUND_UP(bch->ecc_bits+1, 32);\n\tconst int ecclen = DIV_ROUND_UP(bch->ecc_bits, 32);\n\n\tmemset(bch->mod8_tab, 0, 4*256*l*sizeof(*bch->mod8_tab));\n\n\tfor (i = 0; i < 256; i++) {\n\t\t/* p(X)=i is a small polynomial of weight <= 8 */\n\t\tfor (b = 0; b < 4; b++) {\n\t\t\t/* we want to compute (p(X).X^(8*b+deg(g))) mod g(X) */\n\t\t\ttab = bch->mod8_tab + (b*256+i)*l;\n\t\t\tdata = i << (8*b);\n\t\t\twhile (data) {\n\t\t\t\td = deg(data);\n\t\t\t\t/* subtract X^d.g(X) from p(X).X^(8*b+deg(g)) */\n\t\t\t\tdata ^= g[0] >> (31-d);\n\t\t\t\tfor (j = 0; j < ecclen; j++) {\n\t\t\t\t\thi = (d < 31) ? g[j] << (d+1) : 0;\n\t\t\t\t\tlo = (j+1 < plen) ?\n\t\t\t\t\t\tg[j+1] >> (31-d) : 0;\n\t\t\t\t\ttab[j] ^= hi|lo;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}",
        "static int ssam_serial_hub_pm_poweroff(struct device *dev)\n{\n\tstruct ssam_controller *c = dev_get_drvdata(dev);\n\tint status;\n": "static int ssam_serial_hub_pm_poweroff(struct device *dev)\n{\n\tstruct ssam_controller *c = dev_get_drvdata(dev);\n\tint status;\n\n\t/*\n\t * When entering hibernation and powering off the system, the EC, at\n\t * least on some models, may disable events. Without us taking care of\n\t * that, this leads to events not being enabled/restored when the\n\t * system resumes from hibernation, resulting SAM-HID subsystem devices\n\t * (i.e. keyboard, touchpad) not working, AC-plug/AC-unplug events being\n\t * gone, etc.\n\t *\n\t * To avoid these issues, we disable all registered events here (this is\n\t * likely not actually required) and restore them during the drivers PM\n\t * restore callback.\n\t *\n\t * Wakeup from the EC interrupt is not supported during hibernation,\n\t * so don't arm the IRQ here.\n\t */\n\n\tstatus = ssam_notifier_disable_registered(c);\n\tif (status) {\n\t\tssam_err(c, \"pm: failed to disable notifiers for hibernation: %d\\n\",\n\t\t\t status);\n\t\treturn status;\n\t}\n\n\tstatus = ssam_ctrl_notif_d0_exit(c);\n\tif (status) {\n\t\tssam_err(c, \"pm: D0-exit notification failed: %d\\n\", status);\n\t\tssam_notifier_restore_registered(c);\n\t\treturn status;\n\t}\n\n\tWARN_ON(ssam_controller_suspend(c));\n\treturn 0;\n}",
        "static int smcr_clnt_conf_first_link(struct smc_sock *smc)\n{\n\tstruct smc_link *link = smc->conn.lnk;\n\tstruct smc_llc_qentry *qentry;\n\tint rc;": "static int smcr_clnt_conf_first_link(struct smc_sock *smc)\n{\n\tstruct smc_link *link = smc->conn.lnk;\n\tstruct smc_llc_qentry *qentry;\n\tint rc;\n\n\t/* receive CONFIRM LINK request from server over RoCE fabric */\n\tqentry = smc_llc_wait(link->lgr, NULL, SMC_LLC_WAIT_TIME,\n\t\t\t      SMC_LLC_CONFIRM_LINK);\n\tif (!qentry) {\n\t\tstruct smc_clc_msg_decline dclc;\n\n\t\trc = smc_clc_wait_msg(smc, &dclc, sizeof(dclc),\n\t\t\t\t      SMC_CLC_DECLINE, CLC_WAIT_TIME_SHORT);\n\t\treturn rc == -EAGAIN ? SMC_CLC_DECL_TIMEOUT_CL : rc;\n\t}\n\tsmc_llc_save_peer_uid(qentry);\n\trc = smc_llc_eval_conf_link(qentry, SMC_LLC_REQ);\n\tsmc_llc_flow_qentry_del(&link->lgr->llc_flow_lcl);\n\tif (rc)\n\t\treturn SMC_CLC_DECL_RMBE_EC;\n\n\trc = smc_ib_modify_qp_rts(link);\n\tif (rc)\n\t\treturn SMC_CLC_DECL_ERR_RDYLNK;\n\n\tsmc_wr_remember_qp_attr(link);\n\n\tif (smcr_link_reg_rmb(link, smc->conn.rmb_desc))\n\t\treturn SMC_CLC_DECL_ERR_REGRMB;\n\n\t/* confirm_rkey is implicit on 1st contact */\n\tsmc->conn.rmb_desc->is_conf_rkey = true;\n\n\t/* send CONFIRM LINK response over RoCE fabric */\n\trc = smc_llc_send_confirm_link(link, SMC_LLC_RESP);\n\tif (rc < 0)\n\t\treturn SMC_CLC_DECL_TIMEOUT_CL;\n\n\tsmc_llc_link_active(link);\n\tsmcr_lgr_set_type(link->lgr, SMC_LGR_SINGLE);\n\n\t/* optional 2nd link, receive ADD LINK request from server */\n\tqentry = smc_llc_wait(link->lgr, NULL, SMC_LLC_WAIT_TIME,\n\t\t\t      SMC_LLC_ADD_LINK);\n\tif (!qentry) {\n\t\tstruct smc_clc_msg_decline dclc;\n\n\t\trc = smc_clc_wait_msg(smc, &dclc, sizeof(dclc),\n\t\t\t\t      SMC_CLC_DECLINE, CLC_WAIT_TIME_SHORT);\n\t\tif (rc == -EAGAIN)\n\t\t\trc = 0; /* no DECLINE received, go with one link */\n\t\treturn rc;\n\t}\n\tsmc_llc_flow_qentry_clr(&link->lgr->llc_flow_lcl);\n\tsmc_llc_cli_add_link(link, qentry);\n\treturn 0;\n}",
        "static void rackmeter_init_cpu_sniffer(struct rackmeter *rm)\n{\n\tunsigned int cpu;\n\n\t/* This driver works only with 1 or 2 CPUs numbered 0 and 1,": "static void rackmeter_init_cpu_sniffer(struct rackmeter *rm)\n{\n\tunsigned int cpu;\n\n\t/* This driver works only with 1 or 2 CPUs numbered 0 and 1,\n\t * but that's really all we have on Apple Xserve. It doesn't\n\t * play very nice with CPU hotplug neither but we don't do that\n\t * on those machines yet\n\t */\n\n\trm->cpu[0].rm = rm;\n\tINIT_DELAYED_WORK(&rm->cpu[0].sniffer, rackmeter_do_timer);\n\trm->cpu[1].rm = rm;\n\tINIT_DELAYED_WORK(&rm->cpu[1].sniffer, rackmeter_do_timer);\n\n\tfor_each_online_cpu(cpu) {\n\t\tstruct rackmeter_cpu *rcpu;\n\n\t\tif (cpu > 1)\n\t\t\tcontinue;\n\t\trcpu = &rm->cpu[cpu];\n\t\trcpu->prev_idle = get_cpu_idle_time(cpu);\n\t\trcpu->prev_wall = jiffies64_to_nsecs(get_jiffies_64());\n\t\tschedule_delayed_work_on(cpu, &rm->cpu[cpu].sniffer,\n\t\t\t\t\t msecs_to_jiffies(CPU_SAMPLING_RATE));\n\t}\n}",
        "static void smc_llc_event_handler(struct smc_llc_qentry *qentry)\n{\n\tunion smc_llc_msg *llc = &qentry->msg;\n\tstruct smc_link *link = qentry->link;\n\tstruct smc_link_group *lgr = link->lgr;": "static void smc_llc_event_handler(struct smc_llc_qentry *qentry)\n{\n\tunion smc_llc_msg *llc = &qentry->msg;\n\tstruct smc_link *link = qentry->link;\n\tstruct smc_link_group *lgr = link->lgr;\n\n\tif (!smc_link_usable(link))\n\t\tgoto out;\n\n\tswitch (llc->raw.hdr.common.llc_type) {\n\tcase SMC_LLC_TEST_LINK:\n\t\tllc->test_link.hd.flags |= SMC_LLC_FLAG_RESP;\n\t\tsmc_llc_send_message(link, llc);\n\t\tbreak;\n\tcase SMC_LLC_ADD_LINK:\n\t\tif (list_empty(&lgr->list))\n\t\t\tgoto out;\t/* lgr is terminating */\n\t\tif (lgr->role == SMC_CLNT) {\n\t\t\tif (smc_llc_is_local_add_link(llc)) {\n\t\t\t\tif (lgr->llc_flow_lcl.type ==\n\t\t\t\t    SMC_LLC_FLOW_ADD_LINK)\n\t\t\t\t\tbreak;\t/* add_link in progress */\n\t\t\t\tif (smc_llc_flow_start(&lgr->llc_flow_lcl,\n\t\t\t\t\t\t       qentry)) {\n\t\t\t\t\tschedule_work(&lgr->llc_add_link_work);\n\t\t\t\t}\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (lgr->llc_flow_lcl.type == SMC_LLC_FLOW_ADD_LINK &&\n\t\t\t    !lgr->llc_flow_lcl.qentry) {\n\t\t\t\t/* a flow is waiting for this message */\n\t\t\t\tsmc_llc_flow_qentry_set(&lgr->llc_flow_lcl,\n\t\t\t\t\t\t\tqentry);\n\t\t\t\twake_up(&lgr->llc_msg_waiter);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (lgr->llc_flow_lcl.type ==\n\t\t\t\t\tSMC_LLC_FLOW_REQ_ADD_LINK) {\n\t\t\t\t/* server started add_link processing */\n\t\t\t\tlgr->llc_flow_lcl.type = SMC_LLC_FLOW_ADD_LINK;\n\t\t\t\tsmc_llc_flow_qentry_set(&lgr->llc_flow_lcl,\n\t\t\t\t\t\t\tqentry);\n\t\t\t\tschedule_work(&lgr->llc_add_link_work);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (smc_llc_flow_start(&lgr->llc_flow_lcl, qentry)) {\n\t\t\t\tschedule_work(&lgr->llc_add_link_work);\n\t\t\t}\n\t\t} else if (smc_llc_flow_start(&lgr->llc_flow_lcl, qentry)) {\n\t\t\t/* as smc server, handle client suggestion */\n\t\t\tschedule_work(&lgr->llc_add_link_work);\n\t\t}\n\t\treturn;\n\tcase SMC_LLC_CONFIRM_LINK:\n\tcase SMC_LLC_ADD_LINK_CONT:\n\t\tif (lgr->llc_flow_lcl.type != SMC_LLC_FLOW_NONE) {\n\t\t\t/* a flow is waiting for this message */\n\t\t\tsmc_llc_flow_qentry_set(&lgr->llc_flow_lcl, qentry);\n\t\t\twake_up(&lgr->llc_msg_waiter);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase SMC_LLC_DELETE_LINK:\n\t\tif (lgr->llc_flow_lcl.type == SMC_LLC_FLOW_ADD_LINK &&\n\t\t    !lgr->llc_flow_lcl.qentry) {\n\t\t\t/* DEL LINK REQ during ADD LINK SEQ */\n\t\t\tsmc_llc_flow_qentry_set(&lgr->llc_flow_lcl, qentry);\n\t\t\twake_up(&lgr->llc_msg_waiter);\n\t\t} else if (smc_llc_flow_start(&lgr->llc_flow_lcl, qentry)) {\n\t\t\tschedule_work(&lgr->llc_del_link_work);\n\t\t}\n\t\treturn;\n\tcase SMC_LLC_CONFIRM_RKEY:\n\t\t/* new request from remote, assign to remote flow */\n\t\tif (smc_llc_flow_start(&lgr->llc_flow_rmt, qentry)) {\n\t\t\t/* process here, does not wait for more llc msgs */\n\t\t\tsmc_llc_rmt_conf_rkey(lgr);\n\t\t\tsmc_llc_flow_stop(lgr, &lgr->llc_flow_rmt);\n\t\t}\n\t\treturn;\n\tcase SMC_LLC_CONFIRM_RKEY_CONT:\n\t\t/* not used because max links is 3, and 3 rkeys fit into\n\t\t * one CONFIRM_RKEY message\n\t\t */\n\t\tbreak;\n\tcase SMC_LLC_DELETE_RKEY:\n\t\t/* new request from remote, assign to remote flow */\n\t\tif (smc_llc_flow_start(&lgr->llc_flow_rmt, qentry)) {\n\t\t\t/* process here, does not wait for more llc msgs */\n\t\t\tsmc_llc_rmt_delete_rkey(lgr);\n\t\t\tsmc_llc_flow_stop(lgr, &lgr->llc_flow_rmt);\n\t\t}\n\t\treturn;\n\tcase SMC_LLC_REQ_ADD_LINK:\n\t\t/* handle response here, smc_llc_flow_stop() cannot be called\n\t\t * in tasklet context\n\t\t */\n\t\tif (lgr->role == SMC_CLNT &&\n\t\t    lgr->llc_flow_lcl.type == SMC_LLC_FLOW_REQ_ADD_LINK &&\n\t\t    (llc->raw.hdr.flags & SMC_LLC_FLAG_RESP)) {\n\t\t\tsmc_llc_flow_stop(link->lgr, &lgr->llc_flow_lcl);\n\t\t} else if (lgr->role == SMC_SERV) {\n\t\t\tif (smc_llc_flow_start(&lgr->llc_flow_lcl, qentry)) {\n\t\t\t\t/* as smc server, handle client suggestion */\n\t\t\t\tlgr->llc_flow_lcl.type = SMC_LLC_FLOW_ADD_LINK;\n\t\t\t\tschedule_work(&lgr->llc_add_link_work);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tsmc_llc_protocol_violation(lgr, llc->raw.hdr.common.type);\n\t\tbreak;\n\t}\nout:\n\tkfree(qentry);\n}",
        "static void ipc_pm_on_link_wake(struct iosm_pm *ipc_pm, bool ack)\n{\n\tipc_pm->ap_state = IPC_MEM_DEV_PM_ACTIVE;\n\n\tif (ack) {": "static void ipc_pm_on_link_wake(struct iosm_pm *ipc_pm, bool ack)\n{\n\tipc_pm->ap_state = IPC_MEM_DEV_PM_ACTIVE;\n\n\tif (ack) {\n\t\tipc_pm->cp_state = IPC_MEM_DEV_PM_ACTIVE;\n\n\t\tipc_cp_irq_sleep_control(ipc_pm->pcie, IPC_MEM_DEV_PM_ACTIVE);\n\n\t\t/* check the consume state !!! */\n\t\tif (test_bit(CONSUME_STATE, &ipc_pm->host_sleep_pend))\n\t\t\tcomplete(&ipc_pm->host_sleep_complete);\n\t}\n\n\t/* Check for pending HPDA update.\n\t * Pending HP update could be because of sending message was\n\t * put on hold due to Device sleep state or due to TD update\n\t * which could be because of Device Sleep and Host Sleep\n\t * states.\n\t */\n\tif (ipc_pm->pending_hpda_update &&\n\t    ipc_pm->host_pm_state == IPC_MEM_HOST_PM_ACTIVE)\n\t\tipc_pm_signal_hpda_doorbell(ipc_pm, IPC_HP_PM_TRIGGER, true);\n}",
        "static int intel_register_dai(struct sdw_intel *sdw)\n{\n\tstruct sdw_cdns *cdns = &sdw->cdns;\n\tstruct sdw_cdns_streams *stream;\n\tstruct snd_soc_dai_driver *dais;": "static int intel_register_dai(struct sdw_intel *sdw)\n{\n\tstruct sdw_cdns *cdns = &sdw->cdns;\n\tstruct sdw_cdns_streams *stream;\n\tstruct snd_soc_dai_driver *dais;\n\tint num_dai, ret, off = 0;\n\n\t/* DAIs are created based on total number of PDIs supported */\n\tnum_dai = cdns->pcm.num_pdi;\n\n\tdais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);\n\tif (!dais)\n\t\treturn -ENOMEM;\n\n\t/* Create PCM DAIs */\n\tstream = &cdns->pcm;\n\n\tret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,\n\t\t\t       off, stream->num_ch_in);\n\tif (ret)\n\t\treturn ret;\n\n\toff += cdns->pcm.num_in;\n\tret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,\n\t\t\t       off, stream->num_ch_out);\n\tif (ret)\n\t\treturn ret;\n\n\toff += cdns->pcm.num_out;\n\tret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,\n\t\t\t       off, stream->num_ch_bd);\n\tif (ret)\n\t\treturn ret;\n\n\treturn snd_soc_register_component(cdns->dev, &dai_component,\n\t\t\t\t\t  dais, num_dai);\n}",
        "static void test_success_cases(void)\n{\n\tLIBBPF_OPTS(bpf_map_create_opts, opts);\n\tchar value[11];\n\tint fd, err;": "static void test_success_cases(void)\n{\n\tLIBBPF_OPTS(bpf_map_create_opts, opts);\n\tchar value[11];\n\tint fd, err;\n\n\t/* Create a map */\n\topts.map_flags = BPF_F_ZERO_SEED | BPF_F_NUMA_NODE;\n\tfd = bpf_map_create(BPF_MAP_TYPE_BLOOM_FILTER, NULL, 0, sizeof(value), 100, &opts);\n\tif (!ASSERT_GE(fd, 0, \"bpf_map_create bloom filter success case\"))\n\t\treturn;\n\n\t/* Add a value to the bloom filter */\n\terr = bpf_map_update_elem(fd, NULL, &value, 0);\n\tif (!ASSERT_OK(err, \"bpf_map_update_elem bloom filter success case\"))\n\t\tgoto done;\n\n\t /* Lookup a value in the bloom filter */\n\terr = bpf_map_lookup_elem(fd, NULL, &value);\n\tASSERT_OK(err, \"bpf_map_update_elem bloom filter success case\");\n\ndone:\n\tclose(fd);\n}",
        "static int receive_SyncParam(struct drbd_connection *connection, struct packet_info *pi)\n{\n\tstruct drbd_peer_device *peer_device;\n\tstruct drbd_device *device;\n\tstruct p_rs_param_95 *p;": "static int receive_SyncParam(struct drbd_connection *connection, struct packet_info *pi)\n{\n\tstruct drbd_peer_device *peer_device;\n\tstruct drbd_device *device;\n\tstruct p_rs_param_95 *p;\n\tunsigned int header_size, data_size, exp_max_sz;\n\tstruct crypto_shash *verify_tfm = NULL;\n\tstruct crypto_shash *csums_tfm = NULL;\n\tstruct net_conf *old_net_conf, *new_net_conf = NULL;\n\tstruct disk_conf *old_disk_conf = NULL, *new_disk_conf = NULL;\n\tconst int apv = connection->agreed_pro_version;\n\tstruct fifo_buffer *old_plan = NULL, *new_plan = NULL;\n\tunsigned int fifo_size = 0;\n\tint err;\n\n\tpeer_device = conn_peer_device(connection, pi->vnr);\n\tif (!peer_device)\n\t\treturn config_unknown_volume(connection, pi);\n\tdevice = peer_device->device;\n\n\texp_max_sz  = apv <= 87 ? sizeof(struct p_rs_param)\n\t\t    : apv == 88 ? sizeof(struct p_rs_param)\n\t\t\t\t\t+ SHARED_SECRET_MAX\n\t\t    : apv <= 94 ? sizeof(struct p_rs_param_89)\n\t\t    : /* apv >= 95 */ sizeof(struct p_rs_param_95);\n\n\tif (pi->size > exp_max_sz) {\n\t\tdrbd_err(device, \"SyncParam packet too long: received %u, expected <= %u bytes\\n\",\n\t\t    pi->size, exp_max_sz);\n\t\treturn -EIO;\n\t}\n\n\tif (apv <= 88) {\n\t\theader_size = sizeof(struct p_rs_param);\n\t\tdata_size = pi->size - header_size;\n\t} else if (apv <= 94) {\n\t\theader_size = sizeof(struct p_rs_param_89);\n\t\tdata_size = pi->size - header_size;\n\t\tD_ASSERT(device, data_size == 0);\n\t} else {\n\t\theader_size = sizeof(struct p_rs_param_95);\n\t\tdata_size = pi->size - header_size;\n\t\tD_ASSERT(device, data_size == 0);\n\t}\n\n\t/* initialize verify_alg and csums_alg */\n\tp = pi->data;\n\tBUILD_BUG_ON(sizeof(p->algs) != 2 * SHARED_SECRET_MAX);\n\tmemset(&p->algs, 0, sizeof(p->algs));\n\n\terr = drbd_recv_all(peer_device->connection, p, header_size);\n\tif (err)\n\t\treturn err;\n\n\tmutex_lock(&connection->resource->conf_update);\n\told_net_conf = peer_device->connection->net_conf;\n\tif (get_ldev(device)) {\n\t\tnew_disk_conf = kzalloc(sizeof(struct disk_conf), GFP_KERNEL);\n\t\tif (!new_disk_conf) {\n\t\t\tput_ldev(device);\n\t\t\tmutex_unlock(&connection->resource->conf_update);\n\t\t\tdrbd_err(device, \"Allocation of new disk_conf failed\\n\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\told_disk_conf = device->ldev->disk_conf;\n\t\t*new_disk_conf = *old_disk_conf;\n\n\t\tnew_disk_conf->resync_rate = be32_to_cpu(p->resync_rate);\n\t}\n\n\tif (apv >= 88) {\n\t\tif (apv == 88) {\n\t\t\tif (data_size > SHARED_SECRET_MAX || data_size == 0) {\n\t\t\t\tdrbd_err(device, \"verify-alg of wrong size, \"\n\t\t\t\t\t\"peer wants %u, accepting only up to %u byte\\n\",\n\t\t\t\t\tdata_size, SHARED_SECRET_MAX);\n\t\t\t\tgoto reconnect;\n\t\t\t}\n\n\t\t\terr = drbd_recv_all(peer_device->connection, p->verify_alg, data_size);\n\t\t\tif (err)\n\t\t\t\tgoto reconnect;\n\t\t\t/* we expect NUL terminated string */\n\t\t\t/* but just in case someone tries to be evil */\n\t\t\tD_ASSERT(device, p->verify_alg[data_size-1] == 0);\n\t\t\tp->verify_alg[data_size-1] = 0;\n\n\t\t} else /* apv >= 89 */ {\n\t\t\t/* we still expect NUL terminated strings */\n\t\t\t/* but just in case someone tries to be evil */\n\t\t\tD_ASSERT(device, p->verify_alg[SHARED_SECRET_MAX-1] == 0);\n\t\t\tD_ASSERT(device, p->csums_alg[SHARED_SECRET_MAX-1] == 0);\n\t\t\tp->verify_alg[SHARED_SECRET_MAX-1] = 0;\n\t\t\tp->csums_alg[SHARED_SECRET_MAX-1] = 0;\n\t\t}\n\n\t\tif (strcmp(old_net_conf->verify_alg, p->verify_alg)) {\n\t\t\tif (device->state.conn == C_WF_REPORT_PARAMS) {\n\t\t\t\tdrbd_err(device, \"Different verify-alg settings. me=\\\"%s\\\" peer=\\\"%s\\\"\\n\",\n\t\t\t\t    old_net_conf->verify_alg, p->verify_alg);\n\t\t\t\tgoto disconnect;\n\t\t\t}\n\t\t\tverify_tfm = drbd_crypto_alloc_digest_safe(device,\n\t\t\t\t\tp->verify_alg, \"verify-alg\");\n\t\t\tif (IS_ERR(verify_tfm)) {\n\t\t\t\tverify_tfm = NULL;\n\t\t\t\tgoto disconnect;\n\t\t\t}\n\t\t}\n\n\t\tif (apv >= 89 && strcmp(old_net_conf->csums_alg, p->csums_alg)) {\n\t\t\tif (device->state.conn == C_WF_REPORT_PARAMS) {\n\t\t\t\tdrbd_err(device, \"Different csums-alg settings. me=\\\"%s\\\" peer=\\\"%s\\\"\\n\",\n\t\t\t\t    old_net_conf->csums_alg, p->csums_alg);\n\t\t\t\tgoto disconnect;\n\t\t\t}\n\t\t\tcsums_tfm = drbd_crypto_alloc_digest_safe(device,\n\t\t\t\t\tp->csums_alg, \"csums-alg\");\n\t\t\tif (IS_ERR(csums_tfm)) {\n\t\t\t\tcsums_tfm = NULL;\n\t\t\t\tgoto disconnect;\n\t\t\t}\n\t\t}\n\n\t\tif (apv > 94 && new_disk_conf) {\n\t\t\tnew_disk_conf->c_plan_ahead = be32_to_cpu(p->c_plan_ahead);\n\t\t\tnew_disk_conf->c_delay_target = be32_to_cpu(p->c_delay_target);\n\t\t\tnew_disk_conf->c_fill_target = be32_to_cpu(p->c_fill_target);\n\t\t\tnew_disk_conf->c_max_rate = be32_to_cpu(p->c_max_rate);\n\n\t\t\tfifo_size = (new_disk_conf->c_plan_ahead * 10 * SLEEP_TIME) / HZ;\n\t\t\tif (fifo_size != device->rs_plan_s->size) {\n\t\t\t\tnew_plan = fifo_alloc(fifo_size);\n\t\t\t\tif (!new_plan) {\n\t\t\t\t\tdrbd_err(device, \"kmalloc of fifo_buffer failed\");\n\t\t\t\t\tput_ldev(device);\n\t\t\t\t\tgoto disconnect;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (verify_tfm || csums_tfm) {\n\t\t\tnew_net_conf = kzalloc(sizeof(struct net_conf), GFP_KERNEL);\n\t\t\tif (!new_net_conf)\n\t\t\t\tgoto disconnect;\n\n\t\t\t*new_net_conf = *old_net_conf;\n\n\t\t\tif (verify_tfm) {\n\t\t\t\tstrcpy(new_net_conf->verify_alg, p->verify_alg);\n\t\t\t\tnew_net_conf->verify_alg_len = strlen(p->verify_alg) + 1;\n\t\t\t\tcrypto_free_shash(peer_device->connection->verify_tfm);\n\t\t\t\tpeer_device->connection->verify_tfm = verify_tfm;\n\t\t\t\tdrbd_info(device, \"using verify-alg: \\\"%s\\\"\\n\", p->verify_alg);\n\t\t\t}\n\t\t\tif (csums_tfm) {\n\t\t\t\tstrcpy(new_net_conf->csums_alg, p->csums_alg);\n\t\t\t\tnew_net_conf->csums_alg_len = strlen(p->csums_alg) + 1;\n\t\t\t\tcrypto_free_shash(peer_device->connection->csums_tfm);\n\t\t\t\tpeer_device->connection->csums_tfm = csums_tfm;\n\t\t\t\tdrbd_info(device, \"using csums-alg: \\\"%s\\\"\\n\", p->csums_alg);\n\t\t\t}\n\t\t\trcu_assign_pointer(connection->net_conf, new_net_conf);\n\t\t}\n\t}\n\n\tif (new_disk_conf) {\n\t\trcu_assign_pointer(device->ldev->disk_conf, new_disk_conf);\n\t\tput_ldev(device);\n\t}\n\n\tif (new_plan) {\n\t\told_plan = device->rs_plan_s;\n\t\trcu_assign_pointer(device->rs_plan_s, new_plan);\n\t}\n\n\tmutex_unlock(&connection->resource->conf_update);\n\tsynchronize_rcu();\n\tif (new_net_conf)\n\t\tkfree(old_net_conf);\n\tkfree(old_disk_conf);\n\tkfree(old_plan);\n\n\treturn 0;\n\nreconnect:\n\tif (new_disk_conf) {\n\t\tput_ldev(device);\n\t\tkfree(new_disk_conf);\n\t}\n\tmutex_unlock(&connection->resource->conf_update);\n\treturn -EIO;\n\ndisconnect:\n\tkfree(new_plan);\n\tif (new_disk_conf) {\n\t\tput_ldev(device);\n\t\tkfree(new_disk_conf);\n\t}\n\tmutex_unlock(&connection->resource->conf_update);\n\t/* just for completeness: actually not needed,\n\t * as this is not reached if csums_tfm was ok. */\n\tcrypto_free_shash(csums_tfm);\n\t/* but free the verify_tfm again, if csums_tfm did not work out */\n\tcrypto_free_shash(verify_tfm);\n\tconn_request_state(peer_device->connection, NS(conn, C_DISCONNECTING), CS_HARD);\n\treturn -EIO;\n}",
        "static int fsi_spi_transfer_init(struct fsi_spi *ctx)\n{\n\tint rc;\n\tbool reset = false;\n\tunsigned long end;": "static int fsi_spi_transfer_init(struct fsi_spi *ctx)\n{\n\tint rc;\n\tbool reset = false;\n\tunsigned long end;\n\tu64 seq_state;\n\tu64 clock_cfg = 0ULL;\n\tu64 status = 0ULL;\n\tu64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |\n\t\tSPI_FSI_CLOCK_CFG_SCK_NO_DEL |\n\t\tFIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);\n\n\tend = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);\n\tdo {\n\t\tif (time_after(jiffies, end))\n\t\t\treturn -ETIMEDOUT;\n\n\t\trc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);\n\t\tif (rc)\n\t\t\treturn rc;\n\n\t\tseq_state = status & SPI_FSI_STATUS_SEQ_STATE;\n\n\t\tif (status & (SPI_FSI_STATUS_ANY_ERROR |\n\t\t\t      SPI_FSI_STATUS_TDR_FULL |\n\t\t\t      SPI_FSI_STATUS_RDR_FULL)) {\n\t\t\tif (reset) {\n\t\t\t\tdev_err(ctx->dev,\n\t\t\t\t\t\"Initialization error: %08llx\\n\",\n\t\t\t\t\tstatus);\n\t\t\t\treturn -EIO;\n\t\t\t}\n\n\t\t\trc = fsi_spi_reset(ctx);\n\t\t\tif (rc)\n\t\t\t\treturn rc;\n\n\t\t\treset = true;\n\t\t\tcontinue;\n\t\t}\n\t} while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));\n\n\trc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);\n\tif (rc)\n\t\treturn rc;\n\n\trc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);\n\tif (rc)\n\t\treturn rc;\n\n\tif ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |\n\t\t\t  SPI_FSI_CLOCK_CFG_ECC_DISABLE |\n\t\t\t  SPI_FSI_CLOCK_CFG_MODE |\n\t\t\t  SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |\n\t\t\t  SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)\n\t\trc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,\n\t\t\t\t       wanted_clock_cfg);\n\n\treturn rc;\n}",
        "static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tstruct cnic_context *ctx = &cp->ctx_tbl[l5_cid];": "static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tstruct cnic_context *ctx = &cp->ctx_tbl[l5_cid];\n\tunion l5cm_specific_data l5_data;\n\tint ret;\n\tu32 hw_cid;\n\n\tinit_waitqueue_head(&ctx->waitq);\n\tctx->wait_cond = 0;\n\tmemset(&l5_data, 0, sizeof(l5_data));\n\thw_cid = BNX2X_HW_CID(bp, ctx->cid);\n\n\tret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,\n\t\t\t\t  hw_cid, NONE_CONNECTION_TYPE, &l5_data);\n\n\tif (ret == 0) {\n\t\twait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);\n\t\tif (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))\n\t\t\treturn -EBUSY;\n\t}\n\n\treturn 0;\n}",
        "static int test__kmod_path__parse(struct test_suite *t __maybe_unused, int subtest __maybe_unused)\n{\n\t/* path                alloc_name  kmod  comp   name   */\n\tT(\"/xxxx/xxxx/x-x.ko\", true      , true, 0    , \"[x_x]\");\n\tT(\"/xxxx/xxxx/x-x.ko\", false     , true, 0    , NULL   );": "static int test__kmod_path__parse(struct test_suite *t __maybe_unused, int subtest __maybe_unused)\n{\n\t/* path                alloc_name  kmod  comp   name   */\n\tT(\"/xxxx/xxxx/x-x.ko\", true      , true, 0    , \"[x_x]\");\n\tT(\"/xxxx/xxxx/x-x.ko\", false     , true, 0    , NULL   );\n\tT(\"/xxxx/xxxx/x-x.ko\", true      , true, 0    , \"[x_x]\");\n\tT(\"/xxxx/xxxx/x-x.ko\", false     , true, 0    , NULL   );\n\tM(\"/xxxx/xxxx/x-x.ko\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);\n\tM(\"/xxxx/xxxx/x-x.ko\", PERF_RECORD_MISC_KERNEL, true);\n\tM(\"/xxxx/xxxx/x-x.ko\", PERF_RECORD_MISC_USER, false);\n\n#ifdef HAVE_ZLIB_SUPPORT\n\t/* path                alloc_name   kmod  comp  name  */\n\tT(\"/xxxx/xxxx/x.ko.gz\", true     , true, 1   , \"[x]\");\n\tT(\"/xxxx/xxxx/x.ko.gz\", false    , true, 1   , NULL );\n\tT(\"/xxxx/xxxx/x.ko.gz\", true     , true, 1   , \"[x]\");\n\tT(\"/xxxx/xxxx/x.ko.gz\", false    , true, 1   , NULL );\n\tM(\"/xxxx/xxxx/x.ko.gz\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);\n\tM(\"/xxxx/xxxx/x.ko.gz\", PERF_RECORD_MISC_KERNEL, true);\n\tM(\"/xxxx/xxxx/x.ko.gz\", PERF_RECORD_MISC_USER, false);\n\n\t/* path              alloc_name  kmod   comp  name  */\n\tT(\"/xxxx/xxxx/x.gz\", true      , false, 1   , \"x.gz\");\n\tT(\"/xxxx/xxxx/x.gz\", false     , false, 1   , NULL  );\n\tT(\"/xxxx/xxxx/x.gz\", true      , false, 1   , \"x.gz\");\n\tT(\"/xxxx/xxxx/x.gz\", false     , false, 1   , NULL  );\n\tM(\"/xxxx/xxxx/x.gz\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"/xxxx/xxxx/x.gz\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"/xxxx/xxxx/x.gz\", PERF_RECORD_MISC_USER, false);\n\n\t/* path   alloc_name  kmod   comp  name   */\n\tT(\"x.gz\", true      , false, 1   , \"x.gz\");\n\tT(\"x.gz\", false     , false, 1   , NULL  );\n\tT(\"x.gz\", true      , false, 1   , \"x.gz\");\n\tT(\"x.gz\", false     , false, 1   , NULL  );\n\tM(\"x.gz\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"x.gz\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"x.gz\", PERF_RECORD_MISC_USER, false);\n\n\t/* path      alloc_name  kmod  comp  name  */\n\tT(\"x.ko.gz\", true      , true, 1   , \"[x]\");\n\tT(\"x.ko.gz\", false     , true, 1   , NULL );\n\tT(\"x.ko.gz\", true      , true, 1   , \"[x]\");\n\tT(\"x.ko.gz\", false     , true, 1   , NULL );\n\tM(\"x.ko.gz\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);\n\tM(\"x.ko.gz\", PERF_RECORD_MISC_KERNEL, true);\n\tM(\"x.ko.gz\", PERF_RECORD_MISC_USER, false);\n#endif\n\n\t/* path            alloc_name  kmod  comp   name           */\n\tT(\"[test_module]\", true      , true, false, \"[test_module]\");\n\tT(\"[test_module]\", false     , true, false, NULL           );\n\tT(\"[test_module]\", true      , true, false, \"[test_module]\");\n\tT(\"[test_module]\", false     , true, false, NULL           );\n\tM(\"[test_module]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);\n\tM(\"[test_module]\", PERF_RECORD_MISC_KERNEL, true);\n\tM(\"[test_module]\", PERF_RECORD_MISC_USER, false);\n\n\t/* path            alloc_name  kmod  comp   name           */\n\tT(\"[test.module]\", true      , true, false, \"[test.module]\");\n\tT(\"[test.module]\", false     , true, false, NULL           );\n\tT(\"[test.module]\", true      , true, false, \"[test.module]\");\n\tT(\"[test.module]\", false     , true, false, NULL           );\n\tM(\"[test.module]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);\n\tM(\"[test.module]\", PERF_RECORD_MISC_KERNEL, true);\n\tM(\"[test.module]\", PERF_RECORD_MISC_USER, false);\n\n\t/* path     alloc_name  kmod   comp   name    */\n\tT(\"[vdso]\", true      , false, false, \"[vdso]\");\n\tT(\"[vdso]\", false     , false, false, NULL    );\n\tT(\"[vdso]\", true      , false, false, \"[vdso]\");\n\tT(\"[vdso]\", false     , false, false, NULL    );\n\tM(\"[vdso]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"[vdso]\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"[vdso]\", PERF_RECORD_MISC_USER, false);\n\n\tT(\"[vdso32]\", true      , false, false, \"[vdso32]\");\n\tT(\"[vdso32]\", false     , false, false, NULL      );\n\tT(\"[vdso32]\", true      , false, false, \"[vdso32]\");\n\tT(\"[vdso32]\", false     , false, false, NULL      );\n\tM(\"[vdso32]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"[vdso32]\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"[vdso32]\", PERF_RECORD_MISC_USER, false);\n\n\tT(\"[vdsox32]\", true      , false, false, \"[vdsox32]\");\n\tT(\"[vdsox32]\", false     , false, false, NULL       );\n\tT(\"[vdsox32]\", true      , false, false, \"[vdsox32]\");\n\tT(\"[vdsox32]\", false     , false, false, NULL       );\n\tM(\"[vdsox32]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"[vdsox32]\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"[vdsox32]\", PERF_RECORD_MISC_USER, false);\n\n\t/* path         alloc_name  kmod   comp   name        */\n\tT(\"[vsyscall]\", true      , false, false, \"[vsyscall]\");\n\tT(\"[vsyscall]\", false     , false, false, NULL        );\n\tT(\"[vsyscall]\", true      , false, false, \"[vsyscall]\");\n\tT(\"[vsyscall]\", false     , false, false, NULL        );\n\tM(\"[vsyscall]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"[vsyscall]\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"[vsyscall]\", PERF_RECORD_MISC_USER, false);\n\n\t/* path                alloc_name  kmod   comp   name      */\n\tT(\"[kernel.kallsyms]\", true      , false, false, \"[kernel.kallsyms]\");\n\tT(\"[kernel.kallsyms]\", false     , false, false, NULL               );\n\tT(\"[kernel.kallsyms]\", true      , false, false, \"[kernel.kallsyms]\");\n\tT(\"[kernel.kallsyms]\", false     , false, false, NULL               );\n\tM(\"[kernel.kallsyms]\", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);\n\tM(\"[kernel.kallsyms]\", PERF_RECORD_MISC_KERNEL, false);\n\tM(\"[kernel.kallsyms]\", PERF_RECORD_MISC_USER, false);\n\n\treturn 0;\n}",
        "static void prepare_tile_info_buffer(struct hantro_ctx *ctx)\n{\n\tstruct hantro_dev *vpu = ctx->dev;\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;": "static void prepare_tile_info_buffer(struct hantro_ctx *ctx)\n{\n\tstruct hantro_dev *vpu = ctx->dev;\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;\n\tconst struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;\n\tu16 *p = (u16 *)((u8 *)ctx->hevc_dec.tile_sizes.cpu);\n\tunsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1;\n\tunsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;\n\tunsigned int pic_width_in_ctbs, pic_height_in_ctbs;\n\tunsigned int max_log2_ctb_size, ctb_size;\n\tbool tiles_enabled, uniform_spacing;\n\tu32 no_chroma = 0;\n\n\ttiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);\n\tuniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);\n\n\thantro_reg_write(vpu, &g2_tile_e, tiles_enabled);\n\n\tmax_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +\n\t\t\t    sps->log2_diff_max_min_luma_coding_block_size;\n\tpic_width_in_ctbs = (sps->pic_width_in_luma_samples +\n\t\t\t    (1 << max_log2_ctb_size) - 1) >> max_log2_ctb_size;\n\tpic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1)\n\t\t\t     >> max_log2_ctb_size;\n\tctb_size = 1 << max_log2_ctb_size;\n\n\tvpu_debug(1, \"Preparing tile sizes buffer for %dx%d CTBs (CTB size %d)\\n\",\n\t\t  pic_width_in_ctbs, pic_height_in_ctbs, ctb_size);\n\n\tif (tiles_enabled) {\n\t\tunsigned int i, j, h;\n\n\t\tvpu_debug(1, \"Tiles enabled! %dx%d\\n\", num_tile_cols, num_tile_rows);\n\n\t\thantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows);\n\t\thantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);\n\n\t\t/* write width + height for each tile in pic */\n\t\tif (!uniform_spacing) {\n\t\t\tu32 tmp_w = 0, tmp_h = 0;\n\n\t\t\tfor (i = 0; i < num_tile_rows; i++) {\n\t\t\t\tif (i == num_tile_rows - 1)\n\t\t\t\t\th = pic_height_in_ctbs - tmp_h;\n\t\t\t\telse\n\t\t\t\t\th = pps->row_height_minus1[i] + 1;\n\t\t\t\ttmp_h += h;\n\t\t\t\tif (i == 0 && h == 1 && ctb_size == 16)\n\t\t\t\t\tno_chroma = 1;\n\t\t\t\tfor (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) {\n\t\t\t\t\ttmp_w += pps->column_width_minus1[j] + 1;\n\t\t\t\t\t*p++ = pps->column_width_minus1[j] + 1;\n\t\t\t\t\t*p++ = h;\n\t\t\t\t\tif (i == 0 && h == 1 && ctb_size == 16)\n\t\t\t\t\t\tno_chroma = 1;\n\t\t\t\t}\n\t\t\t\t/* last column */\n\t\t\t\t*p++ = pic_width_in_ctbs - tmp_w;\n\t\t\t\t*p++ = h;\n\t\t\t}\n\t\t} else { /* uniform spacing */\n\t\t\tu32 tmp, prev_h, prev_w;\n\n\t\t\tfor (i = 0, prev_h = 0; i < num_tile_rows; i++) {\n\t\t\t\ttmp = (i + 1) * pic_height_in_ctbs / num_tile_rows;\n\t\t\t\th = tmp - prev_h;\n\t\t\t\tprev_h = tmp;\n\t\t\t\tif (i == 0 && h == 1 && ctb_size == 16)\n\t\t\t\t\tno_chroma = 1;\n\t\t\t\tfor (j = 0, prev_w = 0; j < num_tile_cols; j++) {\n\t\t\t\t\ttmp = (j + 1) * pic_width_in_ctbs / num_tile_cols;\n\t\t\t\t\t*p++ = tmp - prev_w;\n\t\t\t\t\t*p++ = h;\n\t\t\t\t\tif (j == 0 &&\n\t\t\t\t\t    (pps->column_width_minus1[0] + 1) == 1 &&\n\t\t\t\t\t    ctb_size == 16)\n\t\t\t\t\t\tno_chroma = 1;\n\t\t\t\t\tprev_w = tmp;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\thantro_reg_write(vpu, &g2_num_tile_rows, 1);\n\t\thantro_reg_write(vpu, &g2_num_tile_cols, 1);\n\n\t\t/* There's one tile, with dimensions equal to pic size. */\n\t\tp[0] = pic_width_in_ctbs;\n\t\tp[1] = pic_height_in_ctbs;\n\t}\n\n\tif (no_chroma)\n\t\tvpu_debug(1, \"%s: no chroma!\\n\", __func__);\n}",
        "static int set_init_regions(struct damon_ctx *c, const char *str, ssize_t len)\n{\n\tstruct damon_target *t;\n\tstruct damon_region *r, *next;\n\tint pos = 0, parsed, ret;": "static int set_init_regions(struct damon_ctx *c, const char *str, ssize_t len)\n{\n\tstruct damon_target *t;\n\tstruct damon_region *r, *next;\n\tint pos = 0, parsed, ret;\n\tint target_idx;\n\tstruct damon_addr_range ar;\n\tint err;\n\n\tdamon_for_each_target(t, c) {\n\t\tdamon_for_each_region_safe(r, next, t)\n\t\t\tdamon_destroy_region(r, t);\n\t}\n\n\twhile (pos < len) {\n\t\tret = sscanf(&str[pos], \"%d %lu %lu%n\",\n\t\t\t\t&target_idx, &ar.start, &ar.end, &parsed);\n\t\tif (ret != 3)\n\t\t\tbreak;\n\t\terr = add_init_region(c, target_idx, &ar);\n\t\tif (err)\n\t\t\tgoto fail;\n\t\tpos += parsed;\n\t}\n\n\treturn 0;\n\nfail:\n\tdamon_for_each_target(t, c) {\n\t\tdamon_for_each_region_safe(r, next, t)\n\t\t\tdamon_destroy_region(r, t);\n\t}\n\treturn err;\n}",
        "static void ssh_ptl_pending_push(struct ssh_packet *p)\n{\n\tstruct ssh_ptl *ptl = p->ptl;\n\tconst ktime_t timestamp = ktime_get_coarse_boottime();\n\tconst ktime_t timeout = ptl->rtx_timeout.timeout;": "static void ssh_ptl_pending_push(struct ssh_packet *p)\n{\n\tstruct ssh_ptl *ptl = p->ptl;\n\tconst ktime_t timestamp = ktime_get_coarse_boottime();\n\tconst ktime_t timeout = ptl->rtx_timeout.timeout;\n\n\t/*\n\t * Note: We can get the time for the timestamp before acquiring the\n\t * lock as this is the only place we're setting it and this function\n\t * is called only from the transmitter thread. Thus it is not possible\n\t * to overwrite the timestamp with an outdated value below.\n\t */\n\n\tspin_lock(&ptl->pending.lock);\n\n\t/* If we are canceling/completing this packet, do not add it. */\n\tif (test_bit(SSH_PACKET_SF_LOCKED_BIT, &p->state)) {\n\t\tspin_unlock(&ptl->pending.lock);\n\t\treturn;\n\t}\n\n\t/*\n\t * On re-submission, the packet has already been added the pending\n\t * set. We still need to update the timestamp as the packet timeout is\n\t * reset for each (re-)submission.\n\t */\n\tp->timestamp = timestamp;\n\n\t/* In case it is already pending (e.g. re-submission), do not add it. */\n\tif (!test_and_set_bit(SSH_PACKET_SF_PENDING_BIT, &p->state)) {\n\t\tatomic_inc(&ptl->pending.count);\n\t\tlist_add_tail(&ssh_packet_get(p)->pending_node, &ptl->pending.head);\n\t}\n\n\tspin_unlock(&ptl->pending.lock);\n\n\t/* Arm/update timeout reaper. */\n\tssh_ptl_timeout_reaper_mod(ptl, timestamp, timestamp + timeout);\n}",
        "static void hfa384x_ctlxout_callback(struct urb *urb)\n{\n\tstruct hfa384x *hw = urb->context;\n\tint delete_resptimer = 0;\n\tint timer_ok = 1;": "static void hfa384x_ctlxout_callback(struct urb *urb)\n{\n\tstruct hfa384x *hw = urb->context;\n\tint delete_resptimer = 0;\n\tint timer_ok = 1;\n\tint run_queue = 0;\n\tstruct hfa384x_usbctlx *ctlx;\n\tunsigned long flags;\n\n\tpr_debug(\"urb->status=%d\\n\", urb->status);\n#ifdef DEBUG_USB\n\tdbprint_urb(urb);\n#endif\n\tif ((urb->status == -ESHUTDOWN) ||\n\t    (urb->status == -ENODEV) || !hw)\n\t\treturn;\n\nretry:\n\tspin_lock_irqsave(&hw->ctlxq.lock, flags);\n\n\t/*\n\t * Only one CTLX at a time on the \"active\" list, and\n\t * none at all if we are unplugged. However, we can\n\t * rely on the disconnect function to clean everything\n\t * up if someone unplugged the adapter.\n\t */\n\tif (list_empty(&hw->ctlxq.active)) {\n\t\tspin_unlock_irqrestore(&hw->ctlxq.lock, flags);\n\t\treturn;\n\t}\n\n\t/*\n\t * Having something on the \"active\" queue means\n\t * that we have timers to worry about ...\n\t */\n\tif (del_timer(&hw->reqtimer) == 0) {\n\t\tif (hw->req_timer_done == 0) {\n\t\t\t/*\n\t\t\t * This timer was actually running while we\n\t\t\t * were trying to delete it. Let it terminate\n\t\t\t * gracefully instead.\n\t\t\t */\n\t\t\tspin_unlock_irqrestore(&hw->ctlxq.lock, flags);\n\t\t\tgoto retry;\n\t\t}\n\t} else {\n\t\thw->req_timer_done = 1;\n\t}\n\n\tctlx = get_active_ctlx(hw);\n\n\tif (urb->status == 0) {\n\t\t/* Request portion of a CTLX is successful */\n\t\tswitch (ctlx->state) {\n\t\tcase CTLX_REQ_SUBMITTED:\n\t\t\t/* This OUT-ACK received before IN */\n\t\t\tctlx->state = CTLX_REQ_COMPLETE;\n\t\t\tbreak;\n\n\t\tcase CTLX_RESP_COMPLETE:\n\t\t\t/* IN already received before this OUT-ACK,\n\t\t\t * so this command must now be complete.\n\t\t\t */\n\t\t\tctlx->state = CTLX_COMPLETE;\n\t\t\tunlocked_usbctlx_complete(hw, ctlx);\n\t\t\trun_queue = 1;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* This is NOT a valid CTLX \"success\" state! */\n\t\t\tnetdev_err(hw->wlandev->netdev,\n\t\t\t\t   \"Illegal CTLX[%d] success state(%s, %d) in OUT URB\\n\",\n\t\t\t\t   le16_to_cpu(ctlx->outbuf.type),\n\t\t\t\t   ctlxstr(ctlx->state), urb->status);\n\t\t\tbreak;\n\t\t}\t\t/* switch */\n\t} else {\n\t\t/* If the pipe has stalled then we need to reset it */\n\t\tif ((urb->status == -EPIPE) &&\n\t\t    !test_and_set_bit(WORK_TX_HALT, &hw->usb_flags)) {\n\t\t\tnetdev_warn(hw->wlandev->netdev,\n\t\t\t\t    \"%s tx pipe stalled: requesting reset\\n\",\n\t\t\t\t    hw->wlandev->netdev->name);\n\t\t\tschedule_work(&hw->usb_work);\n\t\t}\n\n\t\t/* If someone cancels the OUT URB then its status\n\t\t * should be either -ECONNRESET or -ENOENT.\n\t\t */\n\t\tctlx->state = CTLX_REQ_FAILED;\n\t\tunlocked_usbctlx_complete(hw, ctlx);\n\t\tdelete_resptimer = 1;\n\t\trun_queue = 1;\n\t}\n\ndelresp:\n\tif (delete_resptimer) {\n\t\ttimer_ok = del_timer(&hw->resptimer);\n\t\tif (timer_ok != 0)\n\t\t\thw->resp_timer_done = 1;\n\t}\n\n\tspin_unlock_irqrestore(&hw->ctlxq.lock, flags);\n\n\tif (!timer_ok && (hw->resp_timer_done == 0)) {\n\t\tspin_lock_irqsave(&hw->ctlxq.lock, flags);\n\t\tgoto delresp;\n\t}\n\n\tif (run_queue)\n\t\thfa384x_usbctlxq_run(hw);\n}",
        "static int rt6_mtu_change_route(struct fib6_info *f6i, void *p_arg)\n{\n\tstruct rt6_mtu_change_arg *arg = (struct rt6_mtu_change_arg *) p_arg;\n\tstruct inet6_dev *idev;\n": "static int rt6_mtu_change_route(struct fib6_info *f6i, void *p_arg)\n{\n\tstruct rt6_mtu_change_arg *arg = (struct rt6_mtu_change_arg *) p_arg;\n\tstruct inet6_dev *idev;\n\n\t/* In IPv6 pmtu discovery is not optional,\n\t   so that RTAX_MTU lock cannot disable it.\n\t   We still use this lock to block changes\n\t   caused by addrconf/ndisc.\n\t*/\n\n\tidev = __in6_dev_get(arg->dev);\n\tif (!idev)\n\t\treturn 0;\n\n\tif (fib6_metric_locked(f6i, RTAX_MTU))\n\t\treturn 0;\n\n\targ->f6i = f6i;\n\tif (f6i->nh) {\n\t\t/* fib6_nh_mtu_change only returns 0, so this is safe */\n\t\treturn nexthop_for_each_fib6_nh(f6i->nh, fib6_nh_mtu_change,\n\t\t\t\t\t\targ);\n\t}\n\n\treturn fib6_nh_mtu_change(f6i->fib6_nh, arg);\n}",
        "static int rpcrdma_sendctxs_create(struct rpcrdma_xprt *r_xprt)\n{\n\tstruct rpcrdma_buffer *buf = &r_xprt->rx_buf;\n\tstruct rpcrdma_sendctx *sc;\n\tunsigned long i;": "static int rpcrdma_sendctxs_create(struct rpcrdma_xprt *r_xprt)\n{\n\tstruct rpcrdma_buffer *buf = &r_xprt->rx_buf;\n\tstruct rpcrdma_sendctx *sc;\n\tunsigned long i;\n\n\t/* Maximum number of concurrent outstanding Send WRs. Capping\n\t * the circular queue size stops Send Queue overflow by causing\n\t * the ->send_request call to fail temporarily before too many\n\t * Sends are posted.\n\t */\n\ti = r_xprt->rx_ep->re_max_requests + RPCRDMA_MAX_BC_REQUESTS;\n\tbuf->rb_sc_ctxs = kcalloc(i, sizeof(sc), GFP_KERNEL);\n\tif (!buf->rb_sc_ctxs)\n\t\treturn -ENOMEM;\n\n\tbuf->rb_sc_last = i - 1;\n\tfor (i = 0; i <= buf->rb_sc_last; i++) {\n\t\tsc = rpcrdma_sendctx_create(r_xprt->rx_ep);\n\t\tif (!sc)\n\t\t\treturn -ENOMEM;\n\n\t\tbuf->rb_sc_ctxs[i] = sc;\n\t}\n\n\tbuf->rb_sc_head = 0;\n\tbuf->rb_sc_tail = 0;\n\treturn 0;\n}",
        "static void npc_load_kpu_profile(struct rvu *rvu)\n{\n\tstruct npc_kpu_profile_adapter *profile = &rvu->kpu;\n\tconst char *kpu_profile = rvu->kpu_pfl_name;\n\tconst struct firmware *fw = NULL;": "static void npc_load_kpu_profile(struct rvu *rvu)\n{\n\tstruct npc_kpu_profile_adapter *profile = &rvu->kpu;\n\tconst char *kpu_profile = rvu->kpu_pfl_name;\n\tconst struct firmware *fw = NULL;\n\tbool retry_fwdb = false;\n\n\t/* If user not specified profile customization */\n\tif (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN))\n\t\tgoto revert_to_default;\n\t/* First prepare default KPU, then we'll customize top entries. */\n\tnpc_prepare_default_kpu(profile);\n\n\t/* Order of preceedence for load loading NPC profile (high to low)\n\t * Firmware binary in filesystem.\n\t * Firmware database method.\n\t * Default KPU profile.\n\t */\n\tif (!request_firmware(&fw, kpu_profile, rvu->dev)) {\n\t\tdev_info(rvu->dev, \"Loading KPU profile from firmware: %s\\n\",\n\t\t\t kpu_profile);\n\t\trvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL);\n\t\tif (rvu->kpu_fwdata) {\n\t\t\tmemcpy(rvu->kpu_fwdata, fw->data, fw->size);\n\t\t\trvu->kpu_fwdata_sz = fw->size;\n\t\t}\n\t\trelease_firmware(fw);\n\t\tretry_fwdb = true;\n\t\tgoto program_kpu;\n\t}\n\nload_image_fwdb:\n\t/* Loading the KPU profile using firmware database */\n\tif (npc_load_kpu_profile_fwdb(rvu, kpu_profile))\n\t\tgoto revert_to_default;\n\nprogram_kpu:\n\t/* Apply profile customization if firmware was loaded. */\n\tif (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) {\n\t\t/* If image from firmware filesystem fails to load or invalid\n\t\t * retry with firmware database method.\n\t\t */\n\t\tif (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) {\n\t\t\t/* Loading image from firmware database failed. */\n\t\t\tif (rvu->kpu_prfl_addr) {\n\t\t\t\tiounmap(rvu->kpu_prfl_addr);\n\t\t\t\trvu->kpu_prfl_addr = NULL;\n\t\t\t} else {\n\t\t\t\tkfree(rvu->kpu_fwdata);\n\t\t\t}\n\t\t\trvu->kpu_fwdata = NULL;\n\t\t\trvu->kpu_fwdata_sz = 0;\n\t\t\tif (retry_fwdb) {\n\t\t\t\tretry_fwdb = false;\n\t\t\t\tgoto load_image_fwdb;\n\t\t\t}\n\t\t}\n\n\t\tdev_warn(rvu->dev,\n\t\t\t \"Can't load KPU profile %s. Using default.\\n\",\n\t\t\t kpu_profile);\n\t\tkfree(rvu->kpu_fwdata);\n\t\trvu->kpu_fwdata = NULL;\n\t\tgoto revert_to_default;\n\t}\n\n\tdev_info(rvu->dev, \"Using custom profile '%s', version %d.%d.%d\\n\",\n\t\t profile->name, NPC_KPU_VER_MAJ(profile->version),\n\t\t NPC_KPU_VER_MIN(profile->version),\n\t\t NPC_KPU_VER_PATCH(profile->version));\n\n\treturn;\n\nrevert_to_default:\n\tnpc_prepare_default_kpu(profile);\n}",
        "static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)\n{\n\tint ret;\n\tint size = 0;\n\tu8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];": "static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)\n{\n\tint ret;\n\tint size = 0;\n\tu8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];\n\n\tscode->need_data = 0;\n\n\tret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));\n\tif (ret < 0)\n\t\treturn ret;\n\tsize = ret;\n\n\tset_vc1_rcv_seqhdr(rcv_seqhdr,\n\t\t\t   vb2_plane_vaddr(scode->vb, 0),\n\t\t\t   scode->inst->out_format.width,\n\t\t\t   scode->inst->out_format.height);\n\tret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,\n\t\t\t\t\t       &scode->wptr,\n\t\t\t\t\t       sizeof(rcv_seqhdr),\n\t\t\t\t\t       rcv_seqhdr);\n\n\tif (ret < 0)\n\t\treturn ret;\n\tsize += sizeof(rcv_seqhdr);\n\treturn size;\n}",
        "static void set_params(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;": "static void set_params(struct hantro_ctx *ctx)\n{\n\tconst struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;\n\tconst struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;\n\tconst struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;\n\tconst struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tu32 min_log2_cb_size, max_log2_ctb_size, min_cb_size, max_ctb_size;\n\tu32 pic_width_in_min_cbs, pic_height_in_min_cbs;\n\tu32 pic_width_aligned, pic_height_aligned;\n\tu32 partial_ctb_x, partial_ctb_y;\n\n\thantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8);\n\thantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8);\n\n\thantro_reg_write(vpu, &g2_output_8_bits, 0);\n\n\thantro_reg_write(vpu, &g2_hdr_skip_length, ctrls->hevc_hdr_skip_length);\n\n\tmin_log2_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;\n\tmax_log2_ctb_size = min_log2_cb_size + sps->log2_diff_max_min_luma_coding_block_size;\n\n\thantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size);\n\thantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size);\n\n\tmin_cb_size = 1 << min_log2_cb_size;\n\tmax_ctb_size = 1 << max_log2_ctb_size;\n\n\tpic_width_in_min_cbs = sps->pic_width_in_luma_samples / min_cb_size;\n\tpic_height_in_min_cbs = sps->pic_height_in_luma_samples / min_cb_size;\n\tpic_width_aligned = ALIGN(sps->pic_width_in_luma_samples, max_ctb_size);\n\tpic_height_aligned = ALIGN(sps->pic_height_in_luma_samples, max_ctb_size);\n\n\tpartial_ctb_x = !!(sps->pic_width_in_luma_samples != pic_width_aligned);\n\tpartial_ctb_y = !!(sps->pic_height_in_luma_samples != pic_height_aligned);\n\n\thantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x);\n\thantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y);\n\n\thantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs);\n\thantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs);\n\n\thantro_reg_write(vpu, &g2_pic_width_4x4,\n\t\t\t (pic_width_in_min_cbs * min_cb_size) / 4);\n\thantro_reg_write(vpu, &g2_pic_height_4x4,\n\t\t\t (pic_height_in_min_cbs * min_cb_size) / 4);\n\n\thantro_reg_write(vpu, &hevc_max_inter_hierdepth,\n\t\t\t sps->max_transform_hierarchy_depth_inter);\n\thantro_reg_write(vpu, &hevc_max_intra_hierdepth,\n\t\t\t sps->max_transform_hierarchy_depth_intra);\n\thantro_reg_write(vpu, &hevc_min_trb_size,\n\t\t\t sps->log2_min_luma_transform_block_size_minus2 + 2);\n\thantro_reg_write(vpu, &hevc_max_trb_size,\n\t\t\t sps->log2_min_luma_transform_block_size_minus2 + 2 +\n\t\t\t sps->log2_diff_max_min_luma_transform_block_size);\n\n\thantro_reg_write(vpu, &g2_tempor_mvp_e,\n\t\t\t !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) &&\n\t\t\t !(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC));\n\thantro_reg_write(vpu, &g2_strong_smooth_e,\n\t\t\t !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED));\n\thantro_reg_write(vpu, &g2_asym_pred_e,\n\t\t\t !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));\n\thantro_reg_write(vpu, &g2_sao_e,\n\t\t\t !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));\n\thantro_reg_write(vpu, &g2_sign_data_hide,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));\n\n\tif (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {\n\t\thantro_reg_write(vpu, &g2_cu_qpd_e, 1);\n\t\thantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);\n\t} else {\n\t\thantro_reg_write(vpu, &g2_cu_qpd_e, 0);\n\t\thantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);\n\t}\n\n\thantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);\n\thantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);\n\n\thantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);\n\thantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);\n\thantro_reg_write(vpu, &g2_slice_hdr_ext_e,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));\n\thantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);\n\thantro_reg_write(vpu, &g2_slice_chqp_present,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));\n\thantro_reg_write(vpu, &g2_weight_bipr_idc,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));\n\thantro_reg_write(vpu, &g2_transq_bypass,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));\n\thantro_reg_write(vpu, &g2_list_mod_e,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));\n\thantro_reg_write(vpu, &g2_entropy_sync_e,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));\n\thantro_reg_write(vpu, &g2_cabac_init_present,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));\n\thantro_reg_write(vpu, &g2_idr_pic_e,\n\t\t\t !!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC));\n\thantro_reg_write(vpu, &hevc_parallel_merge,\n\t\t\t pps->log2_parallel_merge_level_minus2 + 2);\n\thantro_reg_write(vpu, &g2_pcm_filt_d,\n\t\t\t !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));\n\thantro_reg_write(vpu, &g2_pcm_e,\n\t\t\t !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED));\n\tif (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {\n\t\thantro_reg_write(vpu, &g2_max_pcm_size,\n\t\t\t\t sps->log2_diff_max_min_pcm_luma_coding_block_size +\n\t\t\t\t sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);\n\t\thantro_reg_write(vpu, &g2_min_pcm_size,\n\t\t\t\t sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);\n\t\thantro_reg_write(vpu, &g2_bit_depth_pcm_y,\n\t\t\t\t sps->pcm_sample_bit_depth_luma_minus1 + 1);\n\t\thantro_reg_write(vpu, &g2_bit_depth_pcm_c,\n\t\t\t\t sps->pcm_sample_bit_depth_chroma_minus1 + 1);\n\t} else {\n\t\thantro_reg_write(vpu, &g2_max_pcm_size, 0);\n\t\thantro_reg_write(vpu, &g2_min_pcm_size, 0);\n\t\thantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0);\n\t\thantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0);\n\t}\n\n\thantro_reg_write(vpu, &g2_start_code_e, 1);\n\thantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);\n\thantro_reg_write(vpu, &g2_weight_pred_e,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));\n\thantro_reg_write(vpu, &g2_cabac_init_present,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));\n\thantro_reg_write(vpu, &g2_const_intra_e,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));\n\thantro_reg_write(vpu, &g2_transform_skip,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));\n\thantro_reg_write(vpu, &g2_out_filtering_dis,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));\n\thantro_reg_write(vpu, &g2_filt_ctrl_pres,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));\n\thantro_reg_write(vpu, &g2_dependent_slice,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));\n\thantro_reg_write(vpu, &g2_filter_override,\n\t\t\t !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));\n\thantro_reg_write(vpu, &g2_refidx0_active,\n\t\t\t pps->num_ref_idx_l0_default_active_minus1 + 1);\n\thantro_reg_write(vpu, &g2_refidx1_active,\n\t\t\t pps->num_ref_idx_l1_default_active_minus1 + 1);\n\thantro_reg_write(vpu, &g2_apf_threshold, 8);\n}",
        "static int do_sched_cfs_period_timer(struct cfs_bandwidth *cfs_b, int overrun, unsigned long flags)\n{\n\tint throttled;\n\n\t/* no need to continue the timer with no bandwidth constraint */": "static int do_sched_cfs_period_timer(struct cfs_bandwidth *cfs_b, int overrun, unsigned long flags)\n{\n\tint throttled;\n\n\t/* no need to continue the timer with no bandwidth constraint */\n\tif (cfs_b->quota == RUNTIME_INF)\n\t\tgoto out_deactivate;\n\n\tthrottled = !list_empty(&cfs_b->throttled_cfs_rq);\n\tcfs_b->nr_periods += overrun;\n\n\t/* Refill extra burst quota even if cfs_b->idle */\n\t__refill_cfs_bandwidth_runtime(cfs_b);\n\n\t/*\n\t * idle depends on !throttled (for the case of a large deficit), and if\n\t * we're going inactive then everything else can be deferred\n\t */\n\tif (cfs_b->idle && !throttled)\n\t\tgoto out_deactivate;\n\n\tif (!throttled) {\n\t\t/* mark as potentially idle for the upcoming period */\n\t\tcfs_b->idle = 1;\n\t\treturn 0;\n\t}\n\n\t/* account preceding periods in which throttling occurred */\n\tcfs_b->nr_throttled += overrun;\n\n\t/*\n\t * This check is repeated as we release cfs_b->lock while we unthrottle.\n\t */\n\twhile (throttled && cfs_b->runtime > 0) {\n\t\traw_spin_unlock_irqrestore(&cfs_b->lock, flags);\n\t\t/* we can't nest cfs_b->lock while distributing bandwidth */\n\t\tdistribute_cfs_runtime(cfs_b);\n\t\traw_spin_lock_irqsave(&cfs_b->lock, flags);\n\n\t\tthrottled = !list_empty(&cfs_b->throttled_cfs_rq);\n\t}\n\n\t/*\n\t * While we are ensured activity in the period following an\n\t * unthrottle, this also covers the case in which the new bandwidth is\n\t * insufficient to cover the existing bandwidth deficit.  (Forcing the\n\t * timer to remain active while there are any throttled entities.)\n\t */\n\tcfs_b->idle = 0;\n\n\treturn 0;\n\nout_deactivate:\n\treturn 1;\n}",
        "static int cops_jumpstart(struct net_device *dev)\n{\n\tstruct cops_local *lp = netdev_priv(dev);\n\n\t/*": "static int cops_jumpstart(struct net_device *dev)\n{\n\tstruct cops_local *lp = netdev_priv(dev);\n\n\t/*\n         *      Once the card has the firmware loaded and has acquired\n         *      the nodeid, if it is reset it will lose it all.\n         */\n        cops_reset(dev,1);\t/* Need to reset card before load firmware. */\n        cops_load(dev);\t\t/* Load the firmware. */\n\n\t/*\n\t *\tIf atalkd already gave us a nodeid we will use that\n\t *\tone again, else we wait for atalkd to give us a nodeid\n\t *\tin cops_ioctl. This may cause a problem if someone steals\n\t *\tour nodeid while we are resetting.\n\t */\t\n\tif(lp->nodeid == 1)\n\t\tcops_nodeid(dev,lp->node_acquire);\n\n\treturn 0;\n}",
        "static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)\n{\n\tstruct hwrm_func_backing_store_cfg_input *req;\n\tstruct bnxt_ctx_mem_info *ctx = bp->ctx;\n\tstruct bnxt_ctx_pg_info *ctx_pg;": "static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)\n{\n\tstruct hwrm_func_backing_store_cfg_input *req;\n\tstruct bnxt_ctx_mem_info *ctx = bp->ctx;\n\tstruct bnxt_ctx_pg_info *ctx_pg;\n\tvoid **__req = (void **)&req;\n\tu32 req_len = sizeof(*req);\n\t__le32 *num_entries;\n\t__le64 *pg_dir;\n\tu32 flags = 0;\n\tu8 *pg_attr;\n\tu32 ena;\n\tint rc;\n\tint i;\n\n\tif (!ctx)\n\t\treturn 0;\n\n\tif (req_len > bp->hwrm_max_ext_req_len)\n\t\treq_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;\n\trc = __hwrm_req_init(bp, __req, HWRM_FUNC_BACKING_STORE_CFG, req_len);\n\tif (rc)\n\t\treturn rc;\n\n\treq->enables = cpu_to_le32(enables);\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {\n\t\tctx_pg = &ctx->qp_mem;\n\t\treq->qp_num_entries = cpu_to_le32(ctx_pg->entries);\n\t\treq->qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);\n\t\treq->qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);\n\t\treq->qp_entry_size = cpu_to_le16(ctx->qp_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->qpc_pg_size_qpc_lvl,\n\t\t\t\t      &req->qpc_page_dir);\n\t}\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {\n\t\tctx_pg = &ctx->srq_mem;\n\t\treq->srq_num_entries = cpu_to_le32(ctx_pg->entries);\n\t\treq->srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);\n\t\treq->srq_entry_size = cpu_to_le16(ctx->srq_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->srq_pg_size_srq_lvl,\n\t\t\t\t      &req->srq_page_dir);\n\t}\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {\n\t\tctx_pg = &ctx->cq_mem;\n\t\treq->cq_num_entries = cpu_to_le32(ctx_pg->entries);\n\t\treq->cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);\n\t\treq->cq_entry_size = cpu_to_le16(ctx->cq_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->cq_pg_size_cq_lvl,\n\t\t\t\t      &req->cq_page_dir);\n\t}\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {\n\t\tctx_pg = &ctx->vnic_mem;\n\t\treq->vnic_num_vnic_entries =\n\t\t\tcpu_to_le16(ctx->vnic_max_vnic_entries);\n\t\treq->vnic_num_ring_table_entries =\n\t\t\tcpu_to_le16(ctx->vnic_max_ring_table_entries);\n\t\treq->vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->vnic_pg_size_vnic_lvl,\n\t\t\t\t      &req->vnic_page_dir);\n\t}\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {\n\t\tctx_pg = &ctx->stat_mem;\n\t\treq->stat_num_entries = cpu_to_le32(ctx->stat_max_entries);\n\t\treq->stat_entry_size = cpu_to_le16(ctx->stat_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->stat_pg_size_stat_lvl,\n\t\t\t\t      &req->stat_page_dir);\n\t}\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {\n\t\tctx_pg = &ctx->mrav_mem;\n\t\treq->mrav_num_entries = cpu_to_le32(ctx_pg->entries);\n\t\tif (ctx->mrav_num_entries_units)\n\t\t\tflags |=\n\t\t\tFUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;\n\t\treq->mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->mrav_pg_size_mrav_lvl,\n\t\t\t\t      &req->mrav_page_dir);\n\t}\n\tif (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {\n\t\tctx_pg = &ctx->tim_mem;\n\t\treq->tim_num_entries = cpu_to_le32(ctx_pg->entries);\n\t\treq->tim_entry_size = cpu_to_le16(ctx->tim_entry_size);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n\t\t\t\t      &req->tim_pg_size_tim_lvl,\n\t\t\t\t      &req->tim_page_dir);\n\t}\n\tfor (i = 0, num_entries = &req->tqm_sp_num_entries,\n\t     pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl,\n\t     pg_dir = &req->tqm_sp_page_dir,\n\t     ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;\n\t     i < BNXT_MAX_TQM_RINGS;\n\t     i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {\n\t\tif (!(enables & ena))\n\t\t\tcontinue;\n\n\t\treq->tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);\n\t\tctx_pg = ctx->tqm_mem[i];\n\t\t*num_entries = cpu_to_le32(ctx_pg->entries);\n\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);\n\t}\n\treq->flags = cpu_to_le32(flags);\n\treturn hwrm_req_send(bp, req);\n}",
        "static int ca0132_alt_select_out(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp, outfx_set;\n\tint jack_present;": "static int ca0132_alt_select_out(struct hda_codec *codec)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int tmp, outfx_set;\n\tint jack_present;\n\tint auto_jack;\n\tint err;\n\t/* Default Headphone is rear headphone */\n\thda_nid_t headphone_nid = spec->out_pins[1];\n\n\tcodec_dbg(codec, \"%s\\n\", __func__);\n\n\tsnd_hda_power_up_pm(codec);\n\n\tauto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];\n\n\t/*\n\t * If headphone rear or front is plugged in, set to headphone.\n\t * If neither is plugged in, set to rear line out. Only if\n\t * hp/speaker auto detect is enabled.\n\t */\n\tif (auto_jack) {\n\t\tjack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||\n\t\t\t   snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);\n\n\t\tif (jack_present)\n\t\t\tspec->cur_out_type = HEADPHONE_OUT;\n\t\telse\n\t\t\tspec->cur_out_type = SPEAKER_OUT;\n\t} else\n\t\tspec->cur_out_type = spec->out_enum_val;\n\n\toutfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];\n\n\t/* Begin DSP output switch, mute DSP volume. */\n\terr = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);\n\tif (err < 0)\n\t\tgoto exit;\n\n\tif (ca0132_alt_select_out_quirk_set(codec) < 0)\n\t\tgoto exit;\n\n\tswitch (spec->cur_out_type) {\n\tcase SPEAKER_OUT:\n\t\tcodec_dbg(codec, \"%s speaker\\n\", __func__);\n\n\t\t/* Enable EAPD */\n\t\tsnd_hda_codec_write(codec, spec->out_pins[0], 0,\n\t\t\tAC_VERB_SET_EAPD_BTLENABLE, 0x01);\n\n\t\t/* Disable headphone node. */\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);\n\t\t/* Set front L-R to output. */\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);\n\t\t/* Set Center/LFE to output. */\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);\n\t\t/* Set rear surround to output. */\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);\n\n\t\t/*\n\t\t * Without PlayEnhancement being enabled, if we've got a 2.0\n\t\t * setup, set it to floating point eight to disable any DSP\n\t\t * processing effects.\n\t\t */\n\t\tif (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)\n\t\t\ttmp = FLOAT_EIGHT;\n\t\telse\n\t\t\ttmp = speaker_channel_cfgs[spec->channel_cfg_val].val;\n\n\t\terr = dspio_set_uint_param(codec, 0x80, 0x04, tmp);\n\t\tif (err < 0)\n\t\t\tgoto exit;\n\n\t\tbreak;\n\tcase HEADPHONE_OUT:\n\t\tcodec_dbg(codec, \"%s hp\\n\", __func__);\n\t\tsnd_hda_codec_write(codec, spec->out_pins[0], 0,\n\t\t\tAC_VERB_SET_EAPD_BTLENABLE, 0x00);\n\n\t\t/* Disable all speaker nodes. */\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);\n\t\tca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);\n\n\t\t/* enable headphone, either front or rear */\n\t\tif (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))\n\t\t\theadphone_nid = spec->out_pins[2];\n\t\telse if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))\n\t\t\theadphone_nid = spec->out_pins[1];\n\n\t\tca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);\n\n\t\tif (outfx_set)\n\t\t\terr = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);\n\t\telse\n\t\t\terr = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);\n\n\t\tif (err < 0)\n\t\t\tgoto exit;\n\t\tbreak;\n\t}\n\t/*\n\t * If output effects are enabled, set the X-Bass effect value again to\n\t * make sure that it's properly enabled/disabled for speaker\n\t * configurations with an LFE channel.\n\t */\n\tif (outfx_set)\n\t\tca0132_effects_set(codec, X_BASS,\n\t\t\tspec->effects_switch[X_BASS - EFFECT_START_NID]);\n\n\t/* Set speaker EQ bypass attenuation to 0. */\n\terr = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);\n\tif (err < 0)\n\t\tgoto exit;\n\n\t/*\n\t * Although unused on all cards but the AE series, this is always set\n\t * to zero when setting the output.\n\t */\n\terr = dspio_set_uint_param(codec, 0x96,\n\t\t\tSPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);\n\tif (err < 0)\n\t\tgoto exit;\n\n\tif (spec->cur_out_type == SPEAKER_OUT)\n\t\terr = ca0132_alt_surround_set_bass_redirection(codec,\n\t\t\t\tspec->bass_redirection_val);\n\telse\n\t\terr = ca0132_alt_surround_set_bass_redirection(codec, 0);\n\n\t/* Unmute DSP now that we're done with output selection. */\n\terr = dspio_set_uint_param(codec, 0x96,\n\t\t\tSPEAKER_TUNING_MUTE, FLOAT_ZERO);\n\tif (err < 0)\n\t\tgoto exit;\n\n\tif (spec->cur_out_type == SPEAKER_OUT) {\n\t\terr = ca0132_alt_set_full_range_speaker(codec);\n\t\tif (err < 0)\n\t\t\tgoto exit;\n\t}\n\nexit:\n\tsnd_hda_power_down_pm(codec);\n\n\treturn err < 0 ? err : 0;\n}",
        "static int ravb_ptp_update_compare(struct ravb_private *priv, u32 ns)\n{\n\tstruct net_device *ndev = priv->ndev;\n\t/* When the comparison value (GPTC.PTCV) is in range of\n\t * [x-1 to x+1] (x is the configured increment value in": "static int ravb_ptp_update_compare(struct ravb_private *priv, u32 ns)\n{\n\tstruct net_device *ndev = priv->ndev;\n\t/* When the comparison value (GPTC.PTCV) is in range of\n\t * [x-1 to x+1] (x is the configured increment value in\n\t * GTI.TIV), it may happen that a comparison match is\n\t * not detected when the timer wraps around.\n\t */\n\tu32 gti_ns_plus_1 = (priv->ptp.current_addend >> 20) + 1;\n\tu32 gccr;\n\n\tif (ns < gti_ns_plus_1)\n\t\tns = gti_ns_plus_1;\n\telse if (ns > 0 - gti_ns_plus_1)\n\t\tns = 0 - gti_ns_plus_1;\n\n\tgccr = ravb_read(ndev, GCCR);\n\tif (gccr & GCCR_LPTC)\n\t\treturn -EBUSY;\n\travb_write(ndev, ns, GPTC);\n\travb_write(ndev, gccr | GCCR_LPTC, GCCR);\n\n\treturn 0;\n}",
        "static void vm_dirty_log_verify(enum vm_guest_mode mode, unsigned long *bmap)\n{\n\tuint64_t step = vm_num_host_pages(mode, 1);\n\tuint64_t page;\n\tuint64_t *value_ptr;": "static void vm_dirty_log_verify(enum vm_guest_mode mode, unsigned long *bmap)\n{\n\tuint64_t step = vm_num_host_pages(mode, 1);\n\tuint64_t page;\n\tuint64_t *value_ptr;\n\tuint64_t min_iter = 0;\n\n\tfor (page = 0; page < host_num_pages; page += step) {\n\t\tvalue_ptr = host_test_mem + page * host_page_size;\n\n\t\t/* If this is a special page that we were tracking... */\n\t\tif (test_and_clear_bit_le(page, host_bmap_track)) {\n\t\t\thost_track_next_count++;\n\t\t\tTEST_ASSERT(test_bit_le(page, bmap),\n\t\t\t\t    \"Page %\"PRIu64\" should have its dirty bit \"\n\t\t\t\t    \"set in this iteration but it is missing\",\n\t\t\t\t    page);\n\t\t}\n\n\t\tif (test_and_clear_bit_le(page, bmap)) {\n\t\t\tbool matched;\n\n\t\t\thost_dirty_count++;\n\n\t\t\t/*\n\t\t\t * If the bit is set, the value written onto\n\t\t\t * the corresponding page should be either the\n\t\t\t * previous iteration number or the current one.\n\t\t\t */\n\t\t\tmatched = (*value_ptr == iteration ||\n\t\t\t\t   *value_ptr == iteration - 1);\n\n\t\t\tif (host_log_mode == LOG_MODE_DIRTY_RING && !matched) {\n\t\t\t\tif (*value_ptr == iteration - 2 && min_iter <= iteration - 2) {\n\t\t\t\t\t/*\n\t\t\t\t\t * Short answer: this case is special\n\t\t\t\t\t * only for dirty ring test where the\n\t\t\t\t\t * page is the last page before a kvm\n\t\t\t\t\t * dirty ring full in iteration N-2.\n\t\t\t\t\t *\n\t\t\t\t\t * Long answer: Assuming ring size R,\n\t\t\t\t\t * one possible condition is:\n\t\t\t\t\t *\n\t\t\t\t\t *      main thr       vcpu thr\n\t\t\t\t\t *      --------       --------\n\t\t\t\t\t *    iter=1\n\t\t\t\t\t *                   write 1 to page 0~(R-1)\n\t\t\t\t\t *                   full, vmexit\n\t\t\t\t\t *    collect 0~(R-1)\n\t\t\t\t\t *    kick vcpu\n\t\t\t\t\t *                   write 1 to (R-1)~(2R-2)\n\t\t\t\t\t *                   full, vmexit\n\t\t\t\t\t *    iter=2\n\t\t\t\t\t *    collect (R-1)~(2R-2)\n\t\t\t\t\t *    kick vcpu\n\t\t\t\t\t *                   write 1 to (2R-2)\n\t\t\t\t\t *                   (NOTE!!! \"1\" cached in cpu reg)\n\t\t\t\t\t *                   write 2 to (2R-1)~(3R-3)\n\t\t\t\t\t *                   full, vmexit\n\t\t\t\t\t *    iter=3\n\t\t\t\t\t *    collect (2R-2)~(3R-3)\n\t\t\t\t\t *    (here if we read value on page\n\t\t\t\t\t *     \"2R-2\" is 1, while iter=3!!!)\n\t\t\t\t\t *\n\t\t\t\t\t * This however can only happen once per iteration.\n\t\t\t\t\t */\n\t\t\t\t\tmin_iter = iteration - 1;\n\t\t\t\t\tcontinue;\n\t\t\t\t} else if (page == dirty_ring_last_page) {\n\t\t\t\t\t/*\n\t\t\t\t\t * Please refer to comments in\n\t\t\t\t\t * dirty_ring_last_page.\n\t\t\t\t\t */\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tTEST_ASSERT(matched,\n\t\t\t\t    \"Set page %\"PRIu64\" value %\"PRIu64\n\t\t\t\t    \" incorrect (iteration=%\"PRIu64\")\",\n\t\t\t\t    page, *value_ptr, iteration);\n\t\t} else {\n\t\t\thost_clear_count++;\n\t\t\t/*\n\t\t\t * If cleared, the value written can be any\n\t\t\t * value smaller or equals to the iteration\n\t\t\t * number.  Note that the value can be exactly\n\t\t\t * (iteration-1) if that write can happen\n\t\t\t * like this:\n\t\t\t *\n\t\t\t * (1) increase loop count to \"iteration-1\"\n\t\t\t * (2) write to page P happens (with value\n\t\t\t *     \"iteration-1\")\n\t\t\t * (3) get dirty log for \"iteration-1\"; we'll\n\t\t\t *     see that page P bit is set (dirtied),\n\t\t\t *     and not set the bit in host_bmap_track\n\t\t\t * (4) increase loop count to \"iteration\"\n\t\t\t *     (which is current iteration)\n\t\t\t * (5) get dirty log for current iteration,\n\t\t\t *     we'll see that page P is cleared, with\n\t\t\t *     value \"iteration-1\".\n\t\t\t */\n\t\t\tTEST_ASSERT(*value_ptr <= iteration,\n\t\t\t\t    \"Clear page %\"PRIu64\" value %\"PRIu64\n\t\t\t\t    \" incorrect (iteration=%\"PRIu64\")\",\n\t\t\t\t    page, *value_ptr, iteration);\n\t\t\tif (*value_ptr == iteration) {\n\t\t\t\t/*\n\t\t\t\t * This page is _just_ modified; it\n\t\t\t\t * should report its dirtyness in the\n\t\t\t\t * next run\n\t\t\t\t */\n\t\t\t\tset_bit_le(page, host_bmap_track);\n\t\t\t}\n\t\t}\n\t}\n}",
        "static int rt1719_usbpd_request_voltage(struct rt1719_data *data)\n{\n\tu32 src_voltage;\n\tint snk_sel, src_sel = -1;\n\tint i, ret;": "static int rt1719_usbpd_request_voltage(struct rt1719_data *data)\n{\n\tu32 src_voltage;\n\tint snk_sel, src_sel = -1;\n\tint i, ret;\n\n\tif (!data->attached || !data->pd_capable || data->spdo_sel <= 0)\n\t\treturn -EINVAL;\n\n\tsrc_voltage = pdo_fixed_voltage(data->spdos[data->spdo_sel - 1]);\n\tif (src_voltage == data->req_voltage)\n\t\treturn 0;\n\n\tswitch (data->req_voltage) {\n\tcase 5000:\n\t\tsnk_sel = RT1719_SNKCAP_5V;\n\t\tbreak;\n\tcase 9000:\n\t\tsnk_sel = RT1719_SNKCAP_9V;\n\t\tbreak;\n\tcase 12000:\n\t\tsnk_sel = RT1719_SNKCAP_12V;\n\t\tbreak;\n\tcase 15000:\n\t\tsnk_sel = RT1719_SNKCAP_15V;\n\t\tbreak;\n\tcase 20000:\n\t\tsnk_sel = RT1719_SNKCAP_20V;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tif (!(data->snkcaps[snk_sel] & RT1719_PSEL_SUPPORT))\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < data->spdo_num; i++) {\n\t\tenum pd_pdo_type type = pdo_type(data->spdos[i]);\n\n\t\tif (type != PDO_TYPE_FIXED)\n\t\t\tcontinue;\n\n\t\tsrc_voltage = pdo_fixed_voltage(data->spdos[i]);\n\t\tif (src_voltage == data->req_voltage) {\n\t\t\tsrc_sel = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (src_sel == -1)\n\t\treturn -EOPNOTSUPP;\n\n\tret = regmap_update_bits(data->regmap, RT1719_REG_TXCTRL1,\n\t\t\t\t RT1719_EVALMODE_MASK | RT1719_REQSRCPDO_MASK,\n\t\t\t\t RT1719_EVALMODE_MASK | (src_sel + 1));\n\tret |= regmap_update_bits(data->regmap, RT1719_REG_TXCTRL2,\n\t\t\t\t  RT1719_TXSPDOREQ_MASK, RT1719_TXSPDOREQ_MASK);\n\tif (ret)\n\t\treturn ret;\n\n\treinit_completion(&data->req_completion);\n\tret = wait_for_completion_timeout(&data->req_completion,\n\t\t\t\t\t  msecs_to_jiffies(400));\n\tif (!ret)\n\t\treturn -ETIMEDOUT;\n\n\treturn 0;\n}",
        "static int raid10_resize(struct mddev *mddev, sector_t sectors)\n{\n\t/* Resize of 'far' arrays is not supported.\n\t * For 'near' and 'offset' arrays we can set the\n\t * number of sectors used to be an appropriate multiple": "static int raid10_resize(struct mddev *mddev, sector_t sectors)\n{\n\t/* Resize of 'far' arrays is not supported.\n\t * For 'near' and 'offset' arrays we can set the\n\t * number of sectors used to be an appropriate multiple\n\t * of the chunk size.\n\t * For 'offset', this is far_copies*chunksize.\n\t * For 'near' the multiplier is the LCM of\n\t * near_copies and raid_disks.\n\t * So if far_copies > 1 && !far_offset, fail.\n\t * Else find LCM(raid_disks, near_copy)*far_copies and\n\t * multiply by chunk_size.  Then round to this number.\n\t * This is mostly done by raid10_size()\n\t */\n\tstruct r10conf *conf = mddev->private;\n\tsector_t oldsize, size;\n\n\tif (mddev->reshape_position != MaxSector)\n\t\treturn -EBUSY;\n\n\tif (conf->geo.far_copies > 1 && !conf->geo.far_offset)\n\t\treturn -EINVAL;\n\n\toldsize = raid10_size(mddev, 0, 0);\n\tsize = raid10_size(mddev, sectors, 0);\n\tif (mddev->external_size &&\n\t    mddev->array_sectors > size)\n\t\treturn -EINVAL;\n\tif (mddev->bitmap) {\n\t\tint ret = md_bitmap_resize(mddev->bitmap, size, 0, 0);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\tmd_set_array_sectors(mddev, size);\n\tif (sectors > mddev->dev_sectors &&\n\t    mddev->recovery_cp > oldsize) {\n\t\tmddev->recovery_cp = oldsize;\n\t\tset_bit(MD_RECOVERY_NEEDED, &mddev->recovery);\n\t}\n\tcalc_sectors(conf, sectors);\n\tmddev->dev_sectors = conf->dev_sectors;\n\tmddev->resync_max_sectors = size;\n\treturn 0;\n}",
        "static void ext4_mb_add_n_trim(struct ext4_allocation_context *ac)\n{\n\tint order, added = 0, lg_prealloc_count = 1;\n\tstruct super_block *sb = ac->ac_sb;\n\tstruct ext4_locality_group *lg = ac->ac_lg;": "static void ext4_mb_add_n_trim(struct ext4_allocation_context *ac)\n{\n\tint order, added = 0, lg_prealloc_count = 1;\n\tstruct super_block *sb = ac->ac_sb;\n\tstruct ext4_locality_group *lg = ac->ac_lg;\n\tstruct ext4_prealloc_space *tmp_pa, *pa = ac->ac_pa;\n\n\torder = fls(pa->pa_free) - 1;\n\tif (order > PREALLOC_TB_SIZE - 1)\n\t\t/* The max size of hash table is PREALLOC_TB_SIZE */\n\t\torder = PREALLOC_TB_SIZE - 1;\n\t/* Add the prealloc space to lg */\n\tspin_lock(&lg->lg_prealloc_lock);\n\tlist_for_each_entry_rcu(tmp_pa, &lg->lg_prealloc_list[order],\n\t\t\t\tpa_inode_list,\n\t\t\t\tlockdep_is_held(&lg->lg_prealloc_lock)) {\n\t\tspin_lock(&tmp_pa->pa_lock);\n\t\tif (tmp_pa->pa_deleted) {\n\t\t\tspin_unlock(&tmp_pa->pa_lock);\n\t\t\tcontinue;\n\t\t}\n\t\tif (!added && pa->pa_free < tmp_pa->pa_free) {\n\t\t\t/* Add to the tail of the previous entry */\n\t\t\tlist_add_tail_rcu(&pa->pa_inode_list,\n\t\t\t\t\t\t&tmp_pa->pa_inode_list);\n\t\t\tadded = 1;\n\t\t\t/*\n\t\t\t * we want to count the total\n\t\t\t * number of entries in the list\n\t\t\t */\n\t\t}\n\t\tspin_unlock(&tmp_pa->pa_lock);\n\t\tlg_prealloc_count++;\n\t}\n\tif (!added)\n\t\tlist_add_tail_rcu(&pa->pa_inode_list,\n\t\t\t\t\t&lg->lg_prealloc_list[order]);\n\tspin_unlock(&lg->lg_prealloc_lock);\n\n\t/* Now trim the list to be not more than 8 elements */\n\tif (lg_prealloc_count > 8) {\n\t\text4_mb_discard_lg_preallocations(sb, lg,\n\t\t\t\t\t\t  order, lg_prealloc_count);\n\t\treturn;\n\t}\n\treturn ;\n}",
        "static int dvb_net_ule_ts_pusi(struct dvb_net_ule_handle *h)\n{\n\tif (h->ts[1] & TS_PUSI) {\n\t\t/* Find beginning of first ULE SNDU in current TS cell. */\n\t\t/* Synchronize continuity counter. */": "static int dvb_net_ule_ts_pusi(struct dvb_net_ule_handle *h)\n{\n\tif (h->ts[1] & TS_PUSI) {\n\t\t/* Find beginning of first ULE SNDU in current TS cell. */\n\t\t/* Synchronize continuity counter. */\n\t\th->priv->tscc = h->ts[3] & 0x0F;\n\t\t/* There is a pointer field here. */\n\t\tif (h->ts[4] > h->ts_remain) {\n\t\t\tpr_err(\"%lu: Invalid ULE packet (pointer field %d)\\n\",\n\t\t\t\th->priv->ts_count, h->ts[4]);\n\t\t\th->ts += TS_SZ;\n\t\t\th->priv->ts_count++;\n\t\t\treturn 1;\n\t\t}\n\t\t/* Skip to destination of pointer field. */\n\t\th->from_where = &h->ts[5] + h->ts[4];\n\t\th->ts_remain -= 1 + h->ts[4];\n\t\th->skipped = 0;\n\t} else {\n\t\th->skipped++;\n\t\th->ts += TS_SZ;\n\t\th->priv->ts_count++;\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}",
        "static int optee_probe(struct platform_device *pdev)\n{\n\toptee_invoke_fn *invoke_fn;\n\tstruct tee_shm_pool *pool = ERR_PTR(-EINVAL);\n\tstruct optee *optee = NULL;": "static int optee_probe(struct platform_device *pdev)\n{\n\toptee_invoke_fn *invoke_fn;\n\tstruct tee_shm_pool *pool = ERR_PTR(-EINVAL);\n\tstruct optee *optee = NULL;\n\tvoid *memremaped_shm = NULL;\n\tunsigned int rpc_param_count;\n\tstruct tee_device *teedev;\n\tstruct tee_context *ctx;\n\tu32 max_notif_value;\n\tu32 arg_cache_flags;\n\tu32 sec_caps;\n\tint rc;\n\n\tinvoke_fn = get_invoke_func(&pdev->dev);\n\tif (IS_ERR(invoke_fn))\n\t\treturn PTR_ERR(invoke_fn);\n\n\tif (!optee_msg_api_uid_is_optee_api(invoke_fn)) {\n\t\tpr_warn(\"api uid mismatch\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\toptee_msg_get_os_revision(invoke_fn);\n\n\tif (!optee_msg_api_revision_is_compatible(invoke_fn)) {\n\t\tpr_warn(\"api revision mismatch\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (!optee_msg_exchange_capabilities(invoke_fn, &sec_caps,\n\t\t\t\t\t     &max_notif_value,\n\t\t\t\t\t     &rpc_param_count)) {\n\t\tpr_warn(\"capabilities mismatch\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * Try to use dynamic shared memory if possible\n\t */\n\tif (sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM) {\n\t\t/*\n\t\t * If we have OPTEE_SMC_SEC_CAP_RPC_ARG we can ask\n\t\t * optee_get_msg_arg() to pre-register (by having\n\t\t * OPTEE_SHM_ARG_ALLOC_PRIV cleared) the page used to pass\n\t\t * an argument struct.\n\t\t *\n\t\t * With the page is pre-registered we can use a non-zero\n\t\t * offset for argument struct, this is indicated with\n\t\t * OPTEE_SHM_ARG_SHARED.\n\t\t *\n\t\t * This means that optee_smc_do_call_with_arg() will use\n\t\t * OPTEE_SMC_CALL_WITH_REGD_ARG for pre-registered pages.\n\t\t */\n\t\tif (sec_caps & OPTEE_SMC_SEC_CAP_RPC_ARG)\n\t\t\targ_cache_flags = OPTEE_SHM_ARG_SHARED;\n\t\telse\n\t\t\targ_cache_flags = OPTEE_SHM_ARG_ALLOC_PRIV;\n\n\t\tpool = optee_shm_pool_alloc_pages();\n\t}\n\n\t/*\n\t * If dynamic shared memory is not available or failed - try static one\n\t */\n\tif (IS_ERR(pool) && (sec_caps & OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM)) {\n\t\t/*\n\t\t * The static memory pool can use non-zero page offsets so\n\t\t * let optee_get_msg_arg() know that with OPTEE_SHM_ARG_SHARED.\n\t\t *\n\t\t * optee_get_msg_arg() should not pre-register the\n\t\t * allocated page used to pass an argument struct, this is\n\t\t * indicated with OPTEE_SHM_ARG_ALLOC_PRIV.\n\t\t *\n\t\t * This means that optee_smc_do_call_with_arg() will use\n\t\t * OPTEE_SMC_CALL_WITH_ARG if rpc_param_count is 0, else\n\t\t * OPTEE_SMC_CALL_WITH_RPC_ARG.\n\t\t */\n\t\targ_cache_flags = OPTEE_SHM_ARG_SHARED |\n\t\t\t\t  OPTEE_SHM_ARG_ALLOC_PRIV;\n\t\tpool = optee_config_shm_memremap(invoke_fn, &memremaped_shm);\n\t}\n\n\tif (IS_ERR(pool))\n\t\treturn PTR_ERR(pool);\n\n\toptee = kzalloc(sizeof(*optee), GFP_KERNEL);\n\tif (!optee) {\n\t\trc = -ENOMEM;\n\t\tgoto err_free_pool;\n\t}\n\n\toptee->ops = &optee_ops;\n\toptee->smc.invoke_fn = invoke_fn;\n\toptee->smc.sec_caps = sec_caps;\n\toptee->rpc_param_count = rpc_param_count;\n\n\tteedev = tee_device_alloc(&optee_clnt_desc, NULL, pool, optee);\n\tif (IS_ERR(teedev)) {\n\t\trc = PTR_ERR(teedev);\n\t\tgoto err_free_optee;\n\t}\n\toptee->teedev = teedev;\n\n\tteedev = tee_device_alloc(&optee_supp_desc, NULL, pool, optee);\n\tif (IS_ERR(teedev)) {\n\t\trc = PTR_ERR(teedev);\n\t\tgoto err_unreg_teedev;\n\t}\n\toptee->supp_teedev = teedev;\n\n\trc = tee_device_register(optee->teedev);\n\tif (rc)\n\t\tgoto err_unreg_supp_teedev;\n\n\trc = tee_device_register(optee->supp_teedev);\n\tif (rc)\n\t\tgoto err_unreg_supp_teedev;\n\n\tmutex_init(&optee->call_queue.mutex);\n\tINIT_LIST_HEAD(&optee->call_queue.waiters);\n\toptee_supp_init(&optee->supp);\n\toptee->smc.memremaped_shm = memremaped_shm;\n\toptee->pool = pool;\n\toptee_shm_arg_cache_init(optee, arg_cache_flags);\n\n\tplatform_set_drvdata(pdev, optee);\n\tctx = teedev_open(optee->teedev);\n\tif (IS_ERR(ctx)) {\n\t\trc = PTR_ERR(ctx);\n\t\tgoto err_supp_uninit;\n\t}\n\toptee->ctx = ctx;\n\trc = optee_notif_init(optee, max_notif_value);\n\tif (rc)\n\t\tgoto err_close_ctx;\n\n\tif (sec_caps & OPTEE_SMC_SEC_CAP_ASYNC_NOTIF) {\n\t\tunsigned int irq;\n\n\t\trc = platform_get_irq(pdev, 0);\n\t\tif (rc < 0) {\n\t\t\tpr_err(\"platform_get_irq: ret %d\\n\", rc);\n\t\t\tgoto err_notif_uninit;\n\t\t}\n\t\tirq = rc;\n\n\t\trc = optee_smc_notif_init_irq(optee, irq);\n\t\tif (rc) {\n\t\t\tirq_dispose_mapping(irq);\n\t\t\tgoto err_notif_uninit;\n\t\t}\n\t\tenable_async_notif(optee->smc.invoke_fn);\n\t\tpr_info(\"Asynchronous notifications enabled\\n\");\n\t}\n\n\t/*\n\t * Ensure that there are no pre-existing shm objects before enabling\n\t * the shm cache so that there's no chance of receiving an invalid\n\t * address during shutdown. This could occur, for example, if we're\n\t * kexec booting from an older kernel that did not properly cleanup the\n\t * shm cache.\n\t */\n\toptee_disable_unmapped_shm_cache(optee);\n\n\t/*\n\t * Only enable the shm cache in case we're not able to pass the RPC\n\t * arg struct right after the normal arg struct.\n\t */\n\tif (!optee->rpc_param_count)\n\t\toptee_enable_shm_cache(optee);\n\n\tif (optee->smc.sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM)\n\t\tpr_info(\"dynamic shared memory is enabled\\n\");\n\n\trc = optee_enumerate_devices(PTA_CMD_GET_DEVICES);\n\tif (rc)\n\t\tgoto err_disable_shm_cache;\n\n\tpr_info(\"initialized driver\\n\");\n\treturn 0;\n\nerr_disable_shm_cache:\n\tif (!optee->rpc_param_count)\n\t\toptee_disable_shm_cache(optee);\n\toptee_smc_notif_uninit_irq(optee);\n\toptee_unregister_devices();\nerr_notif_uninit:\n\toptee_notif_uninit(optee);\nerr_close_ctx:\n\tteedev_close_context(ctx);\nerr_supp_uninit:\n\toptee_shm_arg_cache_uninit(optee);\n\toptee_supp_uninit(&optee->supp);\n\tmutex_destroy(&optee->call_queue.mutex);\nerr_unreg_supp_teedev:\n\ttee_device_unregister(optee->supp_teedev);\nerr_unreg_teedev:\n\ttee_device_unregister(optee->teedev);\nerr_free_optee:\n\tkfree(optee);\nerr_free_pool:\n\ttee_shm_pool_free(pool);\n\tif (memremaped_shm)\n\t\tmemunmap(memremaped_shm);\n\treturn rc;\n}",
        "static int adv748x_power_up_tx(struct adv748x_csi2 *tx)\n{\n\tstruct adv748x_state *state = tx->state;\n\tu8 page = is_txa(tx) ? ADV748X_PAGE_TXA : ADV748X_PAGE_TXB;\n\tint ret = 0;": "static int adv748x_power_up_tx(struct adv748x_csi2 *tx)\n{\n\tstruct adv748x_state *state = tx->state;\n\tu8 page = is_txa(tx) ? ADV748X_PAGE_TXA : ADV748X_PAGE_TXB;\n\tint ret = 0;\n\n\t/* Enable n-lane MIPI */\n\tadv748x_write_check(state, page, 0x00, 0x80 | tx->active_lanes, &ret);\n\n\t/* Set Auto DPHY Timing */\n\tadv748x_write_check(state, page, 0x00, 0xa0 | tx->active_lanes, &ret);\n\n\t/* ADI Required Write */\n\tif (tx->src == &state->hdmi.sd) {\n\t\tadv748x_write_check(state, page, 0xdb, 0x10, &ret);\n\t\tadv748x_write_check(state, page, 0xd6, 0x07, &ret);\n\t} else {\n\t\tadv748x_write_check(state, page, 0xd2, 0x40, &ret);\n\t}\n\n\tadv748x_write_check(state, page, 0xc4, 0x0a, &ret);\n\tadv748x_write_check(state, page, 0x71, 0x33, &ret);\n\tadv748x_write_check(state, page, 0x72, 0x11, &ret);\n\n\t/* i2c_dphy_pwdn - 1'b0 */\n\tadv748x_write_check(state, page, 0xf0, 0x00, &ret);\n\n\t/* ADI Required Writes*/\n\tadv748x_write_check(state, page, 0x31, 0x82, &ret);\n\tadv748x_write_check(state, page, 0x1e, 0x40, &ret);\n\n\t/* i2c_mipi_pll_en - 1'b1 */\n\tadv748x_write_check(state, page, 0xda, 0x01, &ret);\n\tusleep_range(2000, 2500);\n\n\t/* Power-up CSI-TX */\n\tadv748x_write_check(state, page, 0x00, 0x20 | tx->active_lanes, &ret);\n\tusleep_range(1000, 1500);\n\n\t/* ADI Required Writes */\n\tadv748x_write_check(state, page, 0xc1, 0x2b, &ret);\n\tusleep_range(1000, 1500);\n\tadv748x_write_check(state, page, 0x31, 0x80, &ret);\n\n\treturn ret;\n}",
        "static void ssh_ptl_resubmit_pending(struct ssh_ptl *ptl)\n{\n\tstruct ssh_packet *p;\n\tbool resub = false;\n": "static void ssh_ptl_resubmit_pending(struct ssh_ptl *ptl)\n{\n\tstruct ssh_packet *p;\n\tbool resub = false;\n\n\t/*\n\t * Note: We deliberately do not remove/attempt to cancel and complete\n\t * packets that are out of tires in this function. The packet will be\n\t * eventually canceled and completed by the timeout. Removing the packet\n\t * here could lead to overly eager cancellation if the packet has not\n\t * been re-transmitted yet but the tries-counter already updated (i.e\n\t * ssh_ptl_tx_next() removed the packet from the queue and updated the\n\t * counter, but re-transmission for the last try has not actually\n\t * started yet).\n\t */\n\n\tspin_lock(&ptl->pending.lock);\n\n\t/* Re-queue all pending packets. */\n\tlist_for_each_entry(p, &ptl->pending.head, pending_node) {\n\t\t/*\n\t\t * Re-submission fails if the packet is out of tries, has been\n\t\t * locked, is already queued, or the layer is being shut down.\n\t\t * No need to re-schedule tx-thread in those cases.\n\t\t */\n\t\tif (!__ssh_ptl_resubmit(p))\n\t\t\tresub = true;\n\t}\n\n\tspin_unlock(&ptl->pending.lock);\n\n\tif (resub)\n\t\tssh_ptl_tx_wakeup_packet(ptl);\n}",
        "static void dcon_wiggle_xo_1(void)\n{\n\tint x;\n\n\t/*": "static void dcon_wiggle_xo_1(void)\n{\n\tint x;\n\n\t/*\n\t * According to HiMax, when powering the DCON up we should hold\n\t * SMB_DATA high for 8 SMB_CLK cycles.  This will force the DCON\n\t * state machine to reset to a (sane) initial state.  Mitch Bradley\n\t * did some testing and discovered that holding for 16 SMB_CLK cycles\n\t * worked a lot more reliably, so that's what we do here.\n\t *\n\t * According to the cs5536 spec, to set GPIO14 to SMB_CLK we must\n\t * simultaneously set AUX1 IN/OUT to GPIO14; ditto for SMB_DATA and\n\t * GPIO15.\n\t */\n\tcs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_VAL);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_ENABLE);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_ENABLE);\n\tcs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX1);\n\tcs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);\n\tcs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX2);\n\tcs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX2);\n\tcs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_INPUT_AUX1);\n\tcs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);\n\n\tfor (x = 0; x < 16; x++) {\n\t\tudelay(5);\n\t\tcs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);\n\t\tudelay(5);\n\t\tcs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);\n\t}\n\tudelay(5);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX1);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_INPUT_AUX1);\n\tcs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);\n}",
        "static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)\n{\n\tint status;\n\tu8 adr = state->demod_address, mm1[4], mm2[4], len;\n": "static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)\n{\n\tint status;\n\tu8 adr = state->demod_address, mm1[4], mm2[4], len;\n\n\tif (state->single_master)\n\t\tflags |= 0xC0;\n\n\tif (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {\n\t\tmm1[0] = (((reg << 1) & 0xFF) | 0x01);\n\t\tmm1[1] = ((reg >> 16) & 0xFF);\n\t\tmm1[2] = ((reg >> 24) & 0xFF) | flags;\n\t\tmm1[3] = ((reg >> 7) & 0xFF);\n\t\tlen = 4;\n\t} else {\n\t\tmm1[0] = ((reg << 1) & 0xFF);\n\t\tmm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));\n\t\tlen = 2;\n\t}\n\tdprintk(2, \"(0x%08x, 0x%02x)\\n\", reg, flags);\n\tstatus = i2c_read(state, adr, mm1, len, mm2, 4);\n\tif (status < 0)\n\t\treturn status;\n\tif (data)\n\t\t*data = mm2[0] | (mm2[1] << 8) |\n\t\t    (mm2[2] << 16) | (mm2[3] << 24);\n\n\treturn 0;\n}",
        "static int rzn1_rtc_set_offset(struct device *dev, long offset)\n{\n\tstruct rzn1_rtc *rtc = dev_get_drvdata(dev);\n\tint stepsh, stepsl, steps;\n\tu32 subu = 0, ctl2;": "static int rzn1_rtc_set_offset(struct device *dev, long offset)\n{\n\tstruct rzn1_rtc *rtc = dev_get_drvdata(dev);\n\tint stepsh, stepsl, steps;\n\tu32 subu = 0, ctl2;\n\tint ret;\n\n\t/*\n\t * Check which resolution mode (every 20 or 60s) can be used.\n\t * Between 2 and 124 clock pulses can be added or substracted.\n\t *\n\t * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is\n\t * close to 3051 ppb. In 60s mode, the resolution is closer to 1017.\n\t */\n\tstepsh = DIV_ROUND_CLOSEST(offset, 1017);\n\tstepsl = DIV_ROUND_CLOSEST(offset, 3051);\n\n\tif (stepsh >= -0x3E && stepsh <= 0x3E) {\n\t\t/* 1017 ppb per step */\n\t\tsteps = stepsh;\n\t\tsubu |= RZN1_RTC_SUBU_DEV;\n\t} else if (stepsl >= -0x3E && stepsl <= 0x3E) {\n\t\t/* 3051 ppb per step */\n\t\tsteps = stepsl;\n\t} else {\n\t\treturn -ERANGE;\n\t}\n\n\tif (!steps)\n\t\treturn 0;\n\n\tif (steps > 0) {\n\t\tsubu |= steps + 1;\n\t} else {\n\t\tsubu |= RZN1_RTC_SUBU_DECR;\n\t\tsubu |= (~(-steps - 1)) & 0x3F;\n\t}\n\n\tret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,\n\t\t\t\t !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000);\n\tif (ret)\n\t\treturn ret;\n\n\twritel(subu, rtc->base + RZN1_RTC_SUBU);\n\n\treturn 0;\n}",
        "static void stm32_cryp_irq_write_ccm_padded_data(struct stm32_cryp *cryp)\n{\n\tint err = 0;\n\tu32 cfg, iv1tmp;\n\tu32 cstmp1[AES_BLOCK_32], cstmp2[AES_BLOCK_32];": "static void stm32_cryp_irq_write_ccm_padded_data(struct stm32_cryp *cryp)\n{\n\tint err = 0;\n\tu32 cfg, iv1tmp;\n\tu32 cstmp1[AES_BLOCK_32], cstmp2[AES_BLOCK_32];\n\tu32 block[AES_BLOCK_32] = {0};\n\tunsigned int i;\n\n\t/* 'Special workaround' procedure described in the datasheet */\n\n\t/* a) disable ip */\n\tstm32_cryp_write(cryp, CRYP_IMSCR, 0);\n\n\tcfg = stm32_cryp_read(cryp, CRYP_CR);\n\tcfg &= ~CR_CRYPEN;\n\tstm32_cryp_write(cryp, CRYP_CR, cfg);\n\n\t/* b) get IV1 from CRYP_CSGCMCCM7 */\n\tiv1tmp = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + 7 * 4);\n\n\t/* c) Load CRYP_CSGCMCCMxR */\n\tfor (i = 0; i < ARRAY_SIZE(cstmp1); i++)\n\t\tcstmp1[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);\n\n\t/* d) Write IV1R */\n\tstm32_cryp_write(cryp, CRYP_IV1RR, iv1tmp);\n\n\t/* e) change mode to CTR */\n\tcfg &= ~CR_ALGO_MASK;\n\tcfg |= CR_AES_CTR;\n\tstm32_cryp_write(cryp, CRYP_CR, cfg);\n\n\t/* a) enable IP */\n\tcfg |= CR_CRYPEN;\n\tstm32_cryp_write(cryp, CRYP_CR, cfg);\n\n\t/* b) pad and write the last block */\n\tstm32_cryp_irq_write_block(cryp);\n\t/* wait end of process */\n\terr = stm32_cryp_wait_output(cryp);\n\tif (err) {\n\t\tdev_err(cryp->dev, \"Timeout (wite ccm padded data)\\n\");\n\t\treturn stm32_cryp_finish_req(cryp, err);\n\t}\n\n\t/* c) get and store decrypted data */\n\t/*\n\t * Same code as stm32_cryp_irq_read_data(), but we want to store\n\t * block value\n\t */\n\tfor (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)\n\t\tblock[i] = stm32_cryp_read(cryp, CRYP_DOUT);\n\n\tscatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,\n\t\t\t\t\t\t\t     cryp->payload_out), 1);\n\tcryp->payload_out -= min_t(size_t, cryp->hw_blocksize, cryp->payload_out);\n\n\t/* d) Load again CRYP_CSGCMCCMxR */\n\tfor (i = 0; i < ARRAY_SIZE(cstmp2); i++)\n\t\tcstmp2[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);\n\n\t/* e) change mode back to AES CCM */\n\tcfg &= ~CR_ALGO_MASK;\n\tcfg |= CR_AES_CCM;\n\tstm32_cryp_write(cryp, CRYP_CR, cfg);\n\n\t/* f) change phase to header */\n\tcfg &= ~CR_PH_MASK;\n\tcfg |= CR_PH_HEADER;\n\tstm32_cryp_write(cryp, CRYP_CR, cfg);\n\n\t/* g) XOR and write padded data */\n\tfor (i = 0; i < ARRAY_SIZE(block); i++) {\n\t\tblock[i] ^= cstmp1[i];\n\t\tblock[i] ^= cstmp2[i];\n\t\tstm32_cryp_write(cryp, CRYP_DIN, block[i]);\n\t}\n\n\t/* h) wait for completion */\n\terr = stm32_cryp_wait_busy(cryp);\n\tif (err)\n\t\tdev_err(cryp->dev, \"Timeout (wite ccm padded data)\\n\");\n\n\t/* i) run the he normal Final phase */\n\tstm32_cryp_finish_req(cryp, err);\n}",
        "static void show_mba_info(unsigned long *bw_imc, unsigned long *bw_resc)\n{\n\tint allocation, runs;\n\tbool failed = false;\n": "static void show_mba_info(unsigned long *bw_imc, unsigned long *bw_resc)\n{\n\tint allocation, runs;\n\tbool failed = false;\n\n\tksft_print_msg(\"Results are displayed in (MB)\\n\");\n\t/* Memory bandwidth from 100% down to 10% */\n\tfor (allocation = 0; allocation < ALLOCATION_MAX / ALLOCATION_STEP;\n\t     allocation++) {\n\t\tunsigned long avg_bw_imc, avg_bw_resc;\n\t\tunsigned long sum_bw_imc = 0, sum_bw_resc = 0;\n\t\tint avg_diff_per;\n\t\tfloat avg_diff;\n\n\t\t/*\n\t\t * The first run is discarded due to inaccurate value from\n\t\t * phase transition.\n\t\t */\n\t\tfor (runs = NUM_OF_RUNS * allocation + 1;\n\t\t     runs < NUM_OF_RUNS * allocation + NUM_OF_RUNS ; runs++) {\n\t\t\tsum_bw_imc += bw_imc[runs];\n\t\t\tsum_bw_resc += bw_resc[runs];\n\t\t}\n\n\t\tavg_bw_imc = sum_bw_imc / (NUM_OF_RUNS - 1);\n\t\tavg_bw_resc = sum_bw_resc / (NUM_OF_RUNS - 1);\n\t\tavg_diff = (float)labs(avg_bw_resc - avg_bw_imc) / avg_bw_imc;\n\t\tavg_diff_per = (int)(avg_diff * 100);\n\n\t\tksft_print_msg(\"%s Check MBA diff within %d%% for schemata %u\\n\",\n\t\t\t       avg_diff_per > MAX_DIFF_PERCENT ?\n\t\t\t       \"Fail:\" : \"Pass:\",\n\t\t\t       MAX_DIFF_PERCENT,\n\t\t\t       ALLOCATION_MAX - ALLOCATION_STEP * allocation);\n\n\t\tksft_print_msg(\"avg_diff_per: %d%%\\n\", avg_diff_per);\n\t\tksft_print_msg(\"avg_bw_imc: %lu\\n\", avg_bw_imc);\n\t\tksft_print_msg(\"avg_bw_resc: %lu\\n\", avg_bw_resc);\n\t\tif (avg_diff_per > MAX_DIFF_PERCENT)\n\t\t\tfailed = true;\n\t}\n\n\tksft_print_msg(\"%s Check schemata change using MBA\\n\",\n\t\t       failed ? \"Fail:\" : \"Pass:\");\n\tif (failed)\n\t\tksft_print_msg(\"At least one test failed\\n\");\n}",
        "static inline int update_counts(void *ctx, u32 pid, u64 delta)\n{\n\tstruct wokeby_t *woke;\n\tu64 zero = 0, *val;\n\tstruct key_t key;": "static inline int update_counts(void *ctx, u32 pid, u64 delta)\n{\n\tstruct wokeby_t *woke;\n\tu64 zero = 0, *val;\n\tstruct key_t key;\n\n\t__builtin_memset(&key.waker, 0, sizeof(key.waker));\n\tbpf_get_current_comm(&key.target, sizeof(key.target));\n\tkey.tret = bpf_get_stackid(ctx, &stackmap, STACKID_FLAGS);\n\tkey.wret = 0;\n\n\twoke = bpf_map_lookup_elem(&wokeby, &pid);\n\tif (woke) {\n\t\tkey.wret = woke->ret;\n\t\t__builtin_memcpy(&key.waker, woke->name, sizeof(key.waker));\n\t\tbpf_map_delete_elem(&wokeby, &pid);\n\t}\n\n\tval = bpf_map_lookup_elem(&counts, &key);\n\tif (!val) {\n\t\tbpf_map_update_elem(&counts, &key, &zero, BPF_NOEXIST);\n\t\tval = bpf_map_lookup_elem(&counts, &key);\n\t\tif (!val)\n\t\t\treturn 0;\n\t}\n\t(*val) += delta;\n\treturn 0;\n}",
        "static unsigned int kmp_find(struct ts_config *conf, struct ts_state *state)\n{\n\tstruct ts_kmp *kmp = ts_config_priv(conf);\n\tunsigned int i, q = 0, text_len, consumed = state->offset;\n\tconst u8 *text;": "static unsigned int kmp_find(struct ts_config *conf, struct ts_state *state)\n{\n\tstruct ts_kmp *kmp = ts_config_priv(conf);\n\tunsigned int i, q = 0, text_len, consumed = state->offset;\n\tconst u8 *text;\n\tconst int icase = conf->flags & TS_IGNORECASE;\n\n\tfor (;;) {\n\t\ttext_len = conf->get_next_block(consumed, &text, conf, state);\n\n\t\tif (unlikely(text_len == 0))\n\t\t\tbreak;\n\n\t\tfor (i = 0; i < text_len; i++) {\n\t\t\twhile (q > 0 && kmp->pattern[q]\n\t\t\t    != (icase ? toupper(text[i]) : text[i]))\n\t\t\t\tq = kmp->prefix_tbl[q - 1];\n\t\t\tif (kmp->pattern[q]\n\t\t\t    == (icase ? toupper(text[i]) : text[i]))\n\t\t\t\tq++;\n\t\t\tif (unlikely(q == kmp->pattern_len)) {\n\t\t\t\tstate->offset = consumed + i + 1;\n\t\t\t\treturn state->offset - kmp->pattern_len;\n\t\t\t}\n\t\t}\n\n\t\tconsumed += text_len;\n\t}\n\n\treturn UINT_MAX;\n}",
        "static void __rb_free_aux(struct perf_buffer *rb)\n{\n\tint pg;\n\n\t/*": "static void __rb_free_aux(struct perf_buffer *rb)\n{\n\tint pg;\n\n\t/*\n\t * Should never happen, the last reference should be dropped from\n\t * perf_mmap_close() path, which first stops aux transactions (which\n\t * in turn are the atomic holders of aux_refcount) and then does the\n\t * last rb_free_aux().\n\t */\n\tWARN_ON_ONCE(in_atomic());\n\n\tif (rb->aux_priv) {\n\t\trb->free_aux(rb->aux_priv);\n\t\trb->free_aux = NULL;\n\t\trb->aux_priv = NULL;\n\t}\n\n\tif (rb->aux_nr_pages) {\n\t\tfor (pg = 0; pg < rb->aux_nr_pages; pg++)\n\t\t\trb_free_aux_page(rb, pg);\n\n\t\tkfree(rb->aux_pages);\n\t\trb->aux_nr_pages = 0;\n\t}\n}",
        "static void mxl692_tx_swap(enum MXL_EAGLE_OPCODE_E opcode, u8 *buffer)\n{\n#ifdef __BIG_ENDIAN\n\treturn;\n#endif": "static void mxl692_tx_swap(enum MXL_EAGLE_OPCODE_E opcode, u8 *buffer)\n{\n#ifdef __BIG_ENDIAN\n\treturn;\n#endif\n\tbuffer += MXL_EAGLE_HOST_MSG_HEADER_SIZE; /* skip API header */\n\n\tswitch (opcode) {\n\tcase MXL_EAGLE_OPCODE_DEVICE_INTR_MASK_SET:\n\tcase MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET:\n\tcase MXL_EAGLE_OPCODE_SMA_TRANSMIT_SET:\n\t\tbuffer += convert_endian(sizeof(u32), buffer);\n\t\tbreak;\n\tcase MXL_EAGLE_OPCODE_QAM_PARAMS_SET:\n\t\tbuffer += 5;\n\t\tbuffer += convert_endian(2 * sizeof(u32), buffer);\n\t\tbreak;\n\tdefault:\n\t\t/* no swapping - all get opcodes */\n\t\t/* ATSC/OOB no swapping */\n\t\tbreak;\n\t}\n}",
        "static int dlfilter__init(struct dlfilter *d, const char *file, int dlargc, char **dlargv)\n{\n\tCHECK_FLAG(BRANCH);\n\tCHECK_FLAG(CALL);\n\tCHECK_FLAG(RETURN);": "static int dlfilter__init(struct dlfilter *d, const char *file, int dlargc, char **dlargv)\n{\n\tCHECK_FLAG(BRANCH);\n\tCHECK_FLAG(CALL);\n\tCHECK_FLAG(RETURN);\n\tCHECK_FLAG(CONDITIONAL);\n\tCHECK_FLAG(SYSCALLRET);\n\tCHECK_FLAG(ASYNC);\n\tCHECK_FLAG(INTERRUPT);\n\tCHECK_FLAG(TX_ABORT);\n\tCHECK_FLAG(TRACE_BEGIN);\n\tCHECK_FLAG(TRACE_END);\n\tCHECK_FLAG(IN_TX);\n\tCHECK_FLAG(VMENTRY);\n\tCHECK_FLAG(VMEXIT);\n\n\tmemset(d, 0, sizeof(*d));\n\td->file = find_dlfilter(file);\n\tif (!d->file)\n\t\treturn -1;\n\td->dlargc = dlargc;\n\td->dlargv = dlargv;\n\treturn 0;\n}",
        "static int gb_lights_light_v4l2_register(struct gb_light *light)\n{\n\tstruct gb_connection *connection = get_conn_from_light(light);\n\tstruct device *dev = &connection->bundle->dev;\n\tstruct v4l2_flash_config sd_cfg = { {0} }, sd_cfg_ind = { {0} };": "static int gb_lights_light_v4l2_register(struct gb_light *light)\n{\n\tstruct gb_connection *connection = get_conn_from_light(light);\n\tstruct device *dev = &connection->bundle->dev;\n\tstruct v4l2_flash_config sd_cfg = { {0} }, sd_cfg_ind = { {0} };\n\tstruct led_classdev_flash *fled;\n\tstruct led_classdev *iled = NULL;\n\tstruct gb_channel *channel_torch, *channel_ind, *channel_flash;\n\n\tchannel_torch = get_channel_from_mode(light, GB_CHANNEL_MODE_TORCH);\n\tif (channel_torch)\n\t\t__gb_lights_channel_v4l2_config(&channel_torch->intensity_uA,\n\t\t\t\t\t\t&sd_cfg.intensity);\n\n\tchannel_ind = get_channel_from_mode(light, GB_CHANNEL_MODE_INDICATOR);\n\tif (channel_ind) {\n\t\t__gb_lights_channel_v4l2_config(&channel_ind->intensity_uA,\n\t\t\t\t\t\t&sd_cfg_ind.intensity);\n\t\tiled = &channel_ind->fled.led_cdev;\n\t}\n\n\tchannel_flash = get_channel_from_mode(light, GB_CHANNEL_MODE_FLASH);\n\tWARN_ON(!channel_flash);\n\n\tfled = &channel_flash->fled;\n\n\tsnprintf(sd_cfg.dev_name, sizeof(sd_cfg.dev_name), \"%s\", light->name);\n\tsnprintf(sd_cfg_ind.dev_name, sizeof(sd_cfg_ind.dev_name),\n\t\t \"%s indicator\", light->name);\n\n\t/* Set the possible values to faults, in our case all faults */\n\tsd_cfg.flash_faults = LED_FAULT_OVER_VOLTAGE | LED_FAULT_TIMEOUT |\n\t\tLED_FAULT_OVER_TEMPERATURE | LED_FAULT_SHORT_CIRCUIT |\n\t\tLED_FAULT_OVER_CURRENT | LED_FAULT_INDICATOR |\n\t\tLED_FAULT_UNDER_VOLTAGE | LED_FAULT_INPUT_VOLTAGE |\n\t\tLED_FAULT_LED_OVER_TEMPERATURE;\n\n\tlight->v4l2_flash = v4l2_flash_init(dev, NULL, fled, &v4l2_flash_ops,\n\t\t\t\t\t    &sd_cfg);\n\tif (IS_ERR(light->v4l2_flash))\n\t\treturn PTR_ERR(light->v4l2_flash);\n\n\tif (channel_ind) {\n\t\tlight->v4l2_flash_ind =\n\t\t\tv4l2_flash_indicator_init(dev, NULL, iled, &sd_cfg_ind);\n\t\tif (IS_ERR(light->v4l2_flash_ind)) {\n\t\t\tv4l2_flash_release(light->v4l2_flash);\n\t\t\treturn PTR_ERR(light->v4l2_flash_ind);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static int __init init_ntfs_fs(void)\n{\n\tint err;\n\n\tpr_info(\"ntfs3: Max link count %u\\n\", NTFS_LINK_MAX);": "static int __init init_ntfs_fs(void)\n{\n\tint err;\n\n\tpr_info(\"ntfs3: Max link count %u\\n\", NTFS_LINK_MAX);\n\n\tif (IS_ENABLED(CONFIG_NTFS3_FS_POSIX_ACL))\n\t\tpr_info(\"ntfs3: Enabled Linux POSIX ACLs support\\n\");\n\tif (IS_ENABLED(CONFIG_NTFS3_64BIT_CLUSTER))\n\t\tpr_notice(\"ntfs3: Warning: Activated 64 bits per cluster. Windows does not support this\\n\");\n\tif (IS_ENABLED(CONFIG_NTFS3_LZX_XPRESS))\n\t\tpr_info(\"ntfs3: Read-only LZX/Xpress compression included\\n\");\n\n\terr = ntfs3_init_bitmap();\n\tif (err)\n\t\treturn err;\n\n\tntfs_inode_cachep = kmem_cache_create(\n\t\t\"ntfs_inode_cache\", sizeof(struct ntfs_inode), 0,\n\t\t(SLAB_RECLAIM_ACCOUNT | SLAB_MEM_SPREAD | SLAB_ACCOUNT),\n\t\tinit_once);\n\tif (!ntfs_inode_cachep) {\n\t\terr = -ENOMEM;\n\t\tgoto out1;\n\t}\n\n\terr = register_filesystem(&ntfs_fs_type);\n\tif (err)\n\t\tgoto out;\n\n\treturn 0;\nout:\n\tkmem_cache_destroy(ntfs_inode_cachep);\nout1:\n\tntfs3_exit_bitmap();\n\treturn err;\n}",
        "static void br_mrp_del_impl(struct net_bridge *br, struct br_mrp *mrp)\n{\n\tstruct net_bridge_port *p;\n\tu8 state;\n": "static void br_mrp_del_impl(struct net_bridge *br, struct br_mrp *mrp)\n{\n\tstruct net_bridge_port *p;\n\tu8 state;\n\n\t/* Stop sending MRP_Test frames */\n\tcancel_delayed_work_sync(&mrp->test_work);\n\tbr_mrp_switchdev_send_ring_test(br, mrp, 0, 0, 0, 0);\n\n\t/* Stop sending MRP_InTest frames if has an interconnect role */\n\tcancel_delayed_work_sync(&mrp->in_test_work);\n\tbr_mrp_switchdev_send_in_test(br, mrp, 0, 0, 0);\n\n\t/* Disable the roles */\n\tbr_mrp_switchdev_set_ring_role(br, mrp, BR_MRP_RING_ROLE_DISABLED);\n\tp = rtnl_dereference(mrp->i_port);\n\tif (p)\n\t\tbr_mrp_switchdev_set_in_role(br, mrp, mrp->in_id, mrp->ring_id,\n\t\t\t\t\t     BR_MRP_IN_ROLE_DISABLED);\n\n\tbr_mrp_switchdev_del(br, mrp);\n\n\t/* Reset the ports */\n\tp = rtnl_dereference(mrp->p_port);\n\tif (p) {\n\t\tspin_lock_bh(&br->lock);\n\t\tstate = netif_running(br->dev) ?\n\t\t\t\tBR_STATE_FORWARDING : BR_STATE_DISABLED;\n\t\tp->state = state;\n\t\tp->flags &= ~BR_MRP_AWARE;\n\t\tspin_unlock_bh(&br->lock);\n\t\tbr_mrp_port_switchdev_set_state(p, state);\n\t\trcu_assign_pointer(mrp->p_port, NULL);\n\t}\n\n\tp = rtnl_dereference(mrp->s_port);\n\tif (p) {\n\t\tspin_lock_bh(&br->lock);\n\t\tstate = netif_running(br->dev) ?\n\t\t\t\tBR_STATE_FORWARDING : BR_STATE_DISABLED;\n\t\tp->state = state;\n\t\tp->flags &= ~BR_MRP_AWARE;\n\t\tspin_unlock_bh(&br->lock);\n\t\tbr_mrp_port_switchdev_set_state(p, state);\n\t\trcu_assign_pointer(mrp->s_port, NULL);\n\t}\n\n\tp = rtnl_dereference(mrp->i_port);\n\tif (p) {\n\t\tspin_lock_bh(&br->lock);\n\t\tstate = netif_running(br->dev) ?\n\t\t\t\tBR_STATE_FORWARDING : BR_STATE_DISABLED;\n\t\tp->state = state;\n\t\tp->flags &= ~BR_MRP_AWARE;\n\t\tspin_unlock_bh(&br->lock);\n\t\tbr_mrp_port_switchdev_set_state(p, state);\n\t\trcu_assign_pointer(mrp->i_port, NULL);\n\t}\n\n\thlist_del_rcu(&mrp->list);\n\tkfree_rcu(mrp, rcu);\n\n\tif (hlist_empty(&br->mrp_list))\n\t\tbr_del_frame(br, &mrp_frame_type);\n}",
        "static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct mtk_adsp_chip_info *adsp = data;\n\tu32 shared_size;": "static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct mtk_adsp_chip_info *adsp = data;\n\tu32 shared_size;\n\n\t/* remap shared-dram base to be non-cachable */\n\tshared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;\n\tadsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;\n\tif (adsp->va_dram) {\n\t\tadsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;\n\t} else {\n\t\tadsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,\n\t\t\t\t\t\t shared_size);\n\t\tif (!adsp->shared_dram) {\n\t\t\tdev_err(dev, \"ioremap failed for shared DRAM\\n\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\tdev_dbg(dev, \"shared-dram vbase=%p, phy addr :%pa,  size=%#x\\n\",\n\t\tadsp->shared_dram, &adsp->pa_shared_dram, shared_size);\n\n\treturn 0;\n}",
        "static int snd_trident_sis_reset(struct snd_trident *trident)\n{\n\tunsigned long end_time;\n\tunsigned int i;\n\tint r;": "static int snd_trident_sis_reset(struct snd_trident *trident)\n{\n\tunsigned long end_time;\n\tunsigned int i;\n\tint r;\n\n\tr = trident->in_suspend ? 0 : 2;\t/* count of retries */\n      __si7018_retry:\n\tpci_write_config_byte(trident->pci, 0x46, 0x04);\t/* SOFTWARE RESET */\n\tudelay(100);\n\tpci_write_config_byte(trident->pci, 0x46, 0x00);\n\tudelay(100);\n\t/* disable AC97 GPIO interrupt */\n\toutb(0x00, TRID_REG(trident, SI_AC97_GPIO));\n\t/* initialize serial interface, force cold reset */\n\ti = PCMOUT|SURROUT|CENTEROUT|LFEOUT|SECONDARY_ID|COLD_RESET;\n\toutl(i, TRID_REG(trident, SI_SERIAL_INTF_CTRL));\n\tudelay(1000);\n\t/* remove cold reset */\n\ti &= ~COLD_RESET;\n\toutl(i, TRID_REG(trident, SI_SERIAL_INTF_CTRL));\n\tudelay(2000);\n\t/* wait, until the codec is ready */\n\tend_time = (jiffies + (HZ * 3) / 4) + 1;\n\tdo {\n\t\tif ((inl(TRID_REG(trident, SI_SERIAL_INTF_CTRL)) & SI_AC97_PRIMARY_READY) != 0)\n\t\t\tgoto __si7018_ok;\n\t\tdo_delay(trident);\n\t} while (time_after_eq(end_time, jiffies));\n\tdev_err(trident->card->dev, \"AC'97 codec ready error [0x%x]\\n\",\n\t\tinl(TRID_REG(trident, SI_SERIAL_INTF_CTRL)));\n\tif (r-- > 0) {\n\t\tend_time = jiffies + HZ;\n\t\tdo {\n\t\t\tdo_delay(trident);\n\t\t} while (time_after_eq(end_time, jiffies));\n\t\tgoto __si7018_retry;\n\t}\n      __si7018_ok:\n\t/* wait for the second codec */\n\tdo {\n\t\tif ((inl(TRID_REG(trident, SI_SERIAL_INTF_CTRL)) & SI_AC97_SECONDARY_READY) != 0)\n\t\t\tbreak;\n\t\tdo_delay(trident);\n\t} while (time_after_eq(end_time, jiffies));\n\t/* enable 64 channel mode */\n\toutl(BANK_B_EN, TRID_REG(trident, T4D_LFO_GC_CIR));\n\treturn 0;\n}",
        "static void rxrpc_rtt_estimator(struct rxrpc_peer *peer, long sample_rtt_us)\n{\n\tlong m = sample_rtt_us; /* RTT */\n\tu32 srtt = peer->srtt_us;\n": "static void rxrpc_rtt_estimator(struct rxrpc_peer *peer, long sample_rtt_us)\n{\n\tlong m = sample_rtt_us; /* RTT */\n\tu32 srtt = peer->srtt_us;\n\n\t/*\tThe following amusing code comes from Jacobson's\n\t *\tarticle in SIGCOMM '88.  Note that rtt and mdev\n\t *\tare scaled versions of rtt and mean deviation.\n\t *\tThis is designed to be as fast as possible\n\t *\tm stands for \"measurement\".\n\t *\n\t *\tOn a 1990 paper the rto value is changed to:\n\t *\tRTO = rtt + 4 * mdev\n\t *\n\t * Funny. This algorithm seems to be very broken.\n\t * These formulae increase RTO, when it should be decreased, increase\n\t * too slowly, when it should be increased quickly, decrease too quickly\n\t * etc. I guess in BSD RTO takes ONE value, so that it is absolutely\n\t * does not matter how to _calculate_ it. Seems, it was trap\n\t * that VJ failed to avoid. 8)\n\t */\n\tif (srtt != 0) {\n\t\tm -= (srtt >> 3);\t/* m is now error in rtt est */\n\t\tsrtt += m;\t\t/* rtt = 7/8 rtt + 1/8 new */\n\t\tif (m < 0) {\n\t\t\tm = -m;\t\t/* m is now abs(error) */\n\t\t\tm -= (peer->mdev_us >> 2);   /* similar update on mdev */\n\t\t\t/* This is similar to one of Eifel findings.\n\t\t\t * Eifel blocks mdev updates when rtt decreases.\n\t\t\t * This solution is a bit different: we use finer gain\n\t\t\t * for mdev in this case (alpha*beta).\n\t\t\t * Like Eifel it also prevents growth of rto,\n\t\t\t * but also it limits too fast rto decreases,\n\t\t\t * happening in pure Eifel.\n\t\t\t */\n\t\t\tif (m > 0)\n\t\t\t\tm >>= 3;\n\t\t} else {\n\t\t\tm -= (peer->mdev_us >> 2);   /* similar update on mdev */\n\t\t}\n\n\t\tpeer->mdev_us += m;\t\t/* mdev = 3/4 mdev + 1/4 new */\n\t\tif (peer->mdev_us > peer->mdev_max_us) {\n\t\t\tpeer->mdev_max_us = peer->mdev_us;\n\t\t\tif (peer->mdev_max_us > peer->rttvar_us)\n\t\t\t\tpeer->rttvar_us = peer->mdev_max_us;\n\t\t}\n\t} else {\n\t\t/* no previous measure. */\n\t\tsrtt = m << 3;\t\t/* take the measured time to be rtt */\n\t\tpeer->mdev_us = m << 1;\t/* make sure rto = 3*rtt */\n\t\tpeer->rttvar_us = max(peer->mdev_us, rxrpc_rto_min_us(peer));\n\t\tpeer->mdev_max_us = peer->rttvar_us;\n\t}\n\n\tpeer->srtt_us = max(1U, srtt);\n}",
        "static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)\n{\n\tu32 osc, osc_reference, osc_mask;\n\tint err;\n": "static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)\n{\n\tu32 osc, osc_reference, osc_mask;\n\tint err;\n\n\t/* For normal sleep on MCP2517FD and MCP2518FD, clearing\n\t * \"Oscillator Disable\" will wake the chip. For low power mode\n\t * on MCP2518FD, asserting the chip select will wake the\n\t * chip. Writing to the Oscillator register will wake it in\n\t * both cases.\n\t */\n\tosc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,\n\t\t\t MCP251XFD_REG_OSC_CLKODIV_10);\n\n\t/* We cannot check for the PLL ready bit (either set or\n\t * unset), as the PLL might be enabled. This can happen if the\n\t * system reboots, while the mcp251xfd stays powered.\n\t */\n\tosc_reference = MCP251XFD_REG_OSC_OSCRDY;\n\tosc_mask = MCP251XFD_REG_OSC_OSCRDY;\n\n\t/* If the controller is in Sleep Mode the following write only\n\t * removes the \"Oscillator Disable\" bit and powers it up. All\n\t * other bits are unaffected.\n\t */\n\terr = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);\n\tif (err)\n\t\treturn err;\n\n\t/* Sometimes the PLL is stuck enabled, the controller never\n\t * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our\n\t * caller takes care of retry.\n\t */\n\treturn mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);\n}",
        "static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)\n{\n\tu32 msg = 0;\n\n\t/* Serialize power state transitions */": "static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)\n{\n\tu32 msg = 0;\n\n\t/* Serialize power state transitions */\n\tif (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))\n\t\treturn;\n\n\tif (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)\n\t\tmsg = TG3_GPIO_MSG_NEED_VAUX;\n\n\tmsg = tg3_set_function_status(tp, msg);\n\n\tif (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)\n\t\tgoto done;\n\n\tif (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)\n\t\ttg3_pwrsrc_switch_to_vaux(tp);\n\telse\n\t\ttg3_pwrsrc_die_with_vmain(tp);\n\ndone:\n\ttg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);\n}",
        "static void vdec_abort(struct vpu_inst *inst)\n{\n\tstruct vdec_t *vdec = inst->priv;\n\tstruct vpu_rpc_buffer_desc desc;\n\tint ret;": "static void vdec_abort(struct vpu_inst *inst)\n{\n\tstruct vdec_t *vdec = inst->priv;\n\tstruct vpu_rpc_buffer_desc desc;\n\tint ret;\n\n\tvpu_trace(inst->dev, \"[%d] state = %d\\n\", inst->id, inst->state);\n\tvpu_iface_add_scode(inst, SCODE_PADDING_ABORT);\n\tvdec->params.end_flag = 1;\n\tvpu_iface_set_decode_params(inst, &vdec->params, 1);\n\n\tvpu_session_abort(inst);\n\n\tret = vpu_iface_get_stream_buffer_desc(inst, &desc);\n\tif (!ret)\n\t\tvpu_iface_update_stream_buffer(inst, desc.rptr, 1);\n\n\tvpu_session_rst_buf(inst);\n\tvpu_trace(inst->dev, \"[%d] input : %d, decoded : %d, display : %d, sequence : %d\\n\",\n\t\t  inst->id,\n\t\t  vdec->params.frame_count,\n\t\t  vdec->decoded_frame_count,\n\t\t  vdec->display_frame_count,\n\t\t  vdec->sequence);\n\tvdec->params.end_flag = 0;\n\tvdec->drain = 0;\n\tvdec->params.frame_count = 0;\n\tvdec->decoded_frame_count = 0;\n\tvdec->display_frame_count = 0;\n\tvdec->sequence = 0;\n}",
        "static void tcp_sndbuf_expand(struct sock *sk)\n{\n\tconst struct tcp_sock *tp = tcp_sk(sk);\n\tconst struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops;\n\tint sndmem, per_mss;": "static void tcp_sndbuf_expand(struct sock *sk)\n{\n\tconst struct tcp_sock *tp = tcp_sk(sk);\n\tconst struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops;\n\tint sndmem, per_mss;\n\tu32 nr_segs;\n\n\t/* Worst case is non GSO/TSO : each frame consumes one skb\n\t * and skb->head is kmalloced using power of two area of memory\n\t */\n\tper_mss = max_t(u32, tp->rx_opt.mss_clamp, tp->mss_cache) +\n\t\t  MAX_TCP_HEADER +\n\t\t  SKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n\n\tper_mss = roundup_pow_of_two(per_mss) +\n\t\t  SKB_DATA_ALIGN(sizeof(struct sk_buff));\n\n\tnr_segs = max_t(u32, TCP_INIT_CWND, tcp_snd_cwnd(tp));\n\tnr_segs = max_t(u32, nr_segs, tp->reordering + 1);\n\n\t/* Fast Recovery (RFC 5681 3.2) :\n\t * Cubic needs 1.7 factor, rounded to 2 to include\n\t * extra cushion (application might react slowly to EPOLLOUT)\n\t */\n\tsndmem = ca_ops->sndbuf_expand ? ca_ops->sndbuf_expand(sk) : 2;\n\tsndmem *= nr_segs * per_mss;\n\n\tif (sk->sk_sndbuf < sndmem)\n\t\tWRITE_ONCE(sk->sk_sndbuf,\n\t\t\t   min(sndmem, sock_net(sk)->ipv4.sysctl_tcp_wmem[2]));\n}",
        "static bool convert_bpf_ld_abs(struct sock_filter *fp, struct bpf_insn **insnp)\n{\n\tconst bool unaligned_ok = IS_BUILTIN(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS);\n\tint size = bpf_size_to_bytes(BPF_SIZE(fp->code));\n\tbool endian = BPF_SIZE(fp->code) == BPF_H ||": "static bool convert_bpf_ld_abs(struct sock_filter *fp, struct bpf_insn **insnp)\n{\n\tconst bool unaligned_ok = IS_BUILTIN(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS);\n\tint size = bpf_size_to_bytes(BPF_SIZE(fp->code));\n\tbool endian = BPF_SIZE(fp->code) == BPF_H ||\n\t\t      BPF_SIZE(fp->code) == BPF_W;\n\tbool indirect = BPF_MODE(fp->code) == BPF_IND;\n\tconst int ip_align = NET_IP_ALIGN;\n\tstruct bpf_insn *insn = *insnp;\n\tint offset = fp->k;\n\n\tif (!indirect &&\n\t    ((unaligned_ok && offset >= 0) ||\n\t     (!unaligned_ok && offset >= 0 &&\n\t      offset + ip_align >= 0 &&\n\t      offset + ip_align % size == 0))) {\n\t\tbool ldx_off_ok = offset <= S16_MAX;\n\n\t\t*insn++ = BPF_MOV64_REG(BPF_REG_TMP, BPF_REG_H);\n\t\tif (offset)\n\t\t\t*insn++ = BPF_ALU64_IMM(BPF_SUB, BPF_REG_TMP, offset);\n\t\t*insn++ = BPF_JMP_IMM(BPF_JSLT, BPF_REG_TMP,\n\t\t\t\t      size, 2 + endian + (!ldx_off_ok * 2));\n\t\tif (ldx_off_ok) {\n\t\t\t*insn++ = BPF_LDX_MEM(BPF_SIZE(fp->code), BPF_REG_A,\n\t\t\t\t\t      BPF_REG_D, offset);\n\t\t} else {\n\t\t\t*insn++ = BPF_MOV64_REG(BPF_REG_TMP, BPF_REG_D);\n\t\t\t*insn++ = BPF_ALU64_IMM(BPF_ADD, BPF_REG_TMP, offset);\n\t\t\t*insn++ = BPF_LDX_MEM(BPF_SIZE(fp->code), BPF_REG_A,\n\t\t\t\t\t      BPF_REG_TMP, 0);\n\t\t}\n\t\tif (endian)\n\t\t\t*insn++ = BPF_ENDIAN(BPF_FROM_BE, BPF_REG_A, size * 8);\n\t\t*insn++ = BPF_JMP_A(8);\n\t}\n\n\t*insn++ = BPF_MOV64_REG(BPF_REG_ARG1, BPF_REG_CTX);\n\t*insn++ = BPF_MOV64_REG(BPF_REG_ARG2, BPF_REG_D);\n\t*insn++ = BPF_MOV64_REG(BPF_REG_ARG3, BPF_REG_H);\n\tif (!indirect) {\n\t\t*insn++ = BPF_MOV64_IMM(BPF_REG_ARG4, offset);\n\t} else {\n\t\t*insn++ = BPF_MOV64_REG(BPF_REG_ARG4, BPF_REG_X);\n\t\tif (fp->k)\n\t\t\t*insn++ = BPF_ALU64_IMM(BPF_ADD, BPF_REG_ARG4, offset);\n\t}\n\n\tswitch (BPF_SIZE(fp->code)) {\n\tcase BPF_B:\n\t\t*insn++ = BPF_EMIT_CALL(bpf_skb_load_helper_8);\n\t\tbreak;\n\tcase BPF_H:\n\t\t*insn++ = BPF_EMIT_CALL(bpf_skb_load_helper_16);\n\t\tbreak;\n\tcase BPF_W:\n\t\t*insn++ = BPF_EMIT_CALL(bpf_skb_load_helper_32);\n\t\tbreak;\n\tdefault:\n\t\treturn false;\n\t}\n\n\t*insn++ = BPF_JMP_IMM(BPF_JSGE, BPF_REG_A, 0, 2);\n\t*insn++ = BPF_ALU32_REG(BPF_XOR, BPF_REG_A, BPF_REG_A);\n\t*insn   = BPF_EXIT_INSN();\n\n\t*insnp = insn;\n\treturn true;\n}",
        "static bool srh1_mt6(const struct sk_buff *skb, struct xt_action_param *par)\n{\n\tint hdrlen, psidoff, nsidoff, lsidoff, srhoff = 0;\n\tconst struct ip6t_srh1 *srhinfo = par->matchinfo;\n\tstruct in6_addr *psid, *nsid, *lsid;": "static bool srh1_mt6(const struct sk_buff *skb, struct xt_action_param *par)\n{\n\tint hdrlen, psidoff, nsidoff, lsidoff, srhoff = 0;\n\tconst struct ip6t_srh1 *srhinfo = par->matchinfo;\n\tstruct in6_addr *psid, *nsid, *lsid;\n\tstruct in6_addr _psid, _nsid, _lsid;\n\tstruct ipv6_sr_hdr *srh;\n\tstruct ipv6_sr_hdr _srh;\n\n\tif (ipv6_find_hdr(skb, &srhoff, IPPROTO_ROUTING, NULL, NULL) < 0)\n\t\treturn false;\n\tsrh = skb_header_pointer(skb, srhoff, sizeof(_srh), &_srh);\n\tif (!srh)\n\t\treturn false;\n\n\thdrlen = ipv6_optlen(srh);\n\tif (skb->len - srhoff < hdrlen)\n\t\treturn false;\n\n\tif (srh->type != IPV6_SRCRT_TYPE_4)\n\t\treturn false;\n\n\tif (srh->segments_left > srh->first_segment)\n\t\treturn false;\n\n\t/* Next Header matching */\n\tif (srhinfo->mt_flags & IP6T_SRH_NEXTHDR)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_NEXTHDR,\n\t\t\t\t!(srh->nexthdr == srhinfo->next_hdr)))\n\t\t\treturn false;\n\n\t/* Header Extension Length matching */\n\tif (srhinfo->mt_flags & IP6T_SRH_LEN_EQ)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LEN_EQ,\n\t\t\t\t!(srh->hdrlen == srhinfo->hdr_len)))\n\t\t\treturn false;\n\tif (srhinfo->mt_flags & IP6T_SRH_LEN_GT)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LEN_GT,\n\t\t\t\t!(srh->hdrlen > srhinfo->hdr_len)))\n\t\t\treturn false;\n\tif (srhinfo->mt_flags & IP6T_SRH_LEN_LT)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LEN_LT,\n\t\t\t\t!(srh->hdrlen < srhinfo->hdr_len)))\n\t\t\treturn false;\n\n\t/* Segments Left matching */\n\tif (srhinfo->mt_flags & IP6T_SRH_SEGS_EQ)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_SEGS_EQ,\n\t\t\t\t!(srh->segments_left == srhinfo->segs_left)))\n\t\t\treturn false;\n\tif (srhinfo->mt_flags & IP6T_SRH_SEGS_GT)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_SEGS_GT,\n\t\t\t\t!(srh->segments_left > srhinfo->segs_left)))\n\t\t\treturn false;\n\tif (srhinfo->mt_flags & IP6T_SRH_SEGS_LT)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_SEGS_LT,\n\t\t\t\t!(srh->segments_left < srhinfo->segs_left)))\n\t\t\treturn false;\n\n\t/**\n\t * Last Entry matching\n\t * Last_Entry field was introduced in revision 6 of the SRH draft.\n\t * It was called First_Segment in the previous revision\n\t */\n\tif (srhinfo->mt_flags & IP6T_SRH_LAST_EQ)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LAST_EQ,\n\t\t\t\t!(srh->first_segment == srhinfo->last_entry)))\n\t\t\treturn false;\n\tif (srhinfo->mt_flags & IP6T_SRH_LAST_GT)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LAST_GT,\n\t\t\t\t!(srh->first_segment > srhinfo->last_entry)))\n\t\t\treturn false;\n\tif (srhinfo->mt_flags & IP6T_SRH_LAST_LT)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LAST_LT,\n\t\t\t\t!(srh->first_segment < srhinfo->last_entry)))\n\t\t\treturn false;\n\n\t/**\n\t * Tag matchig\n\t * Tag field was introduced in revision 6 of the SRH draft\n\t */\n\tif (srhinfo->mt_flags & IP6T_SRH_TAG)\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_TAG,\n\t\t\t\t!(srh->tag == srhinfo->tag)))\n\t\t\treturn false;\n\n\t/* Previous SID matching */\n\tif (srhinfo->mt_flags & IP6T_SRH_PSID) {\n\t\tif (srh->segments_left == srh->first_segment)\n\t\t\treturn false;\n\t\tpsidoff = srhoff + sizeof(struct ipv6_sr_hdr) +\n\t\t\t  ((srh->segments_left + 1) * sizeof(struct in6_addr));\n\t\tpsid = skb_header_pointer(skb, psidoff, sizeof(_psid), &_psid);\n\t\tif (!psid)\n\t\t\treturn false;\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_PSID,\n\t\t\t\tipv6_masked_addr_cmp(psid, &srhinfo->psid_msk,\n\t\t\t\t\t\t     &srhinfo->psid_addr)))\n\t\t\treturn false;\n\t}\n\n\t/* Next SID matching */\n\tif (srhinfo->mt_flags & IP6T_SRH_NSID) {\n\t\tif (srh->segments_left == 0)\n\t\t\treturn false;\n\t\tnsidoff = srhoff + sizeof(struct ipv6_sr_hdr) +\n\t\t\t  ((srh->segments_left - 1) * sizeof(struct in6_addr));\n\t\tnsid = skb_header_pointer(skb, nsidoff, sizeof(_nsid), &_nsid);\n\t\tif (!nsid)\n\t\t\treturn false;\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_NSID,\n\t\t\t\tipv6_masked_addr_cmp(nsid, &srhinfo->nsid_msk,\n\t\t\t\t\t\t     &srhinfo->nsid_addr)))\n\t\t\treturn false;\n\t}\n\n\t/* Last SID matching */\n\tif (srhinfo->mt_flags & IP6T_SRH_LSID) {\n\t\tlsidoff = srhoff + sizeof(struct ipv6_sr_hdr);\n\t\tlsid = skb_header_pointer(skb, lsidoff, sizeof(_lsid), &_lsid);\n\t\tif (!lsid)\n\t\t\treturn false;\n\t\tif (NF_SRH_INVF(srhinfo, IP6T_SRH_INV_LSID,\n\t\t\t\tipv6_masked_addr_cmp(lsid, &srhinfo->lsid_msk,\n\t\t\t\t\t\t     &srhinfo->lsid_addr)))\n\t\t\treturn false;\n\t}\n\treturn true;\n}",
        "static void guest_code_test_memslot_move(void)\n{\n\tstruct sync_area *sync = (typeof(sync))MEM_SYNC_GPA;\n\tuintptr_t base = (typeof(base))READ_ONCE(sync->move_area_ptr);\n": "static void guest_code_test_memslot_move(void)\n{\n\tstruct sync_area *sync = (typeof(sync))MEM_SYNC_GPA;\n\tuintptr_t base = (typeof(base))READ_ONCE(sync->move_area_ptr);\n\n\tGUEST_SYNC(0);\n\n\tguest_spin_until_start();\n\n\twhile (!guest_should_exit()) {\n\t\tuintptr_t ptr;\n\n\t\tfor (ptr = base; ptr < base + MEM_TEST_MOVE_SIZE;\n\t\t     ptr += 4096)\n\t\t\t*(uint64_t *)ptr = MEM_TEST_VAL_1;\n\n\t\t/*\n\t\t * No host sync here since the MMIO exits are so expensive\n\t\t * that the host would spend most of its time waiting for\n\t\t * the guest and so instead of measuring memslot move\n\t\t * performance we would measure the performance and\n\t\t * likelihood of MMIO exits\n\t\t */\n\t}\n\n\tGUEST_DONE();\n}",
        "static void avs_dsp_process_notification(struct avs_dev *adev, u64 header)\n{\n\tstruct avs_notify_mod_data mod_data;\n\tunion avs_notify_msg msg = AVS_MSG(header);\n\tsize_t data_size = 0;": "static void avs_dsp_process_notification(struct avs_dev *adev, u64 header)\n{\n\tstruct avs_notify_mod_data mod_data;\n\tunion avs_notify_msg msg = AVS_MSG(header);\n\tsize_t data_size = 0;\n\tvoid *data = NULL;\n\tu64 reg;\n\n\treg = readq(avs_sram_addr(adev, AVS_FW_REGS_WINDOW));\n\ttrace_avs_ipc_notify_msg(header, reg);\n\n\t/* Ignore spurious notifications until handshake is established. */\n\tif (!adev->ipc->ready && msg.notify_msg_type != AVS_NOTIFY_FW_READY) {\n\t\tdev_dbg(adev->dev, \"FW not ready, skip notification: 0x%08x\\n\", msg.primary);\n\t\treturn;\n\t}\n\n\t/* Calculate notification payload size. */\n\tswitch (msg.notify_msg_type) {\n\tcase AVS_NOTIFY_FW_READY:\n\t\tbreak;\n\n\tcase AVS_NOTIFY_PHRASE_DETECTED:\n\t\tdata_size = sizeof(struct avs_notify_voice_data);\n\t\tbreak;\n\n\tcase AVS_NOTIFY_RESOURCE_EVENT:\n\t\tdata_size = sizeof(struct avs_notify_res_data);\n\t\tbreak;\n\n\tcase AVS_NOTIFY_LOG_BUFFER_STATUS:\n\tcase AVS_NOTIFY_EXCEPTION_CAUGHT:\n\t\tbreak;\n\n\tcase AVS_NOTIFY_MODULE_EVENT:\n\t\t/* To know the total payload size, header needs to be read first. */\n\t\tmemcpy_fromio(&mod_data, avs_uplink_addr(adev), sizeof(mod_data));\n\t\tdata_size = sizeof(mod_data) + mod_data.data_size;\n\t\tbreak;\n\n\tdefault:\n\t\tdev_info(adev->dev, \"unknown notification: 0x%08x\\n\", msg.primary);\n\t\tbreak;\n\t}\n\n\tif (data_size) {\n\t\tdata = kmalloc(data_size, GFP_KERNEL);\n\t\tif (!data)\n\t\t\treturn;\n\n\t\tmemcpy_fromio(data, avs_uplink_addr(adev), data_size);\n\t\ttrace_avs_msg_payload(data, data_size);\n\t}\n\n\t/* Perform notification-specific operations. */\n\tswitch (msg.notify_msg_type) {\n\tcase AVS_NOTIFY_FW_READY:\n\t\tdev_dbg(adev->dev, \"FW READY 0x%08x\\n\", msg.primary);\n\t\tadev->ipc->ready = true;\n\t\tcomplete(&adev->fw_ready);\n\t\tbreak;\n\n\tcase AVS_NOTIFY_LOG_BUFFER_STATUS:\n\t\tavs_dsp_op(adev, log_buffer_status, &msg);\n\t\tbreak;\n\n\tcase AVS_NOTIFY_EXCEPTION_CAUGHT:\n\t\tavs_dsp_exception_caught(adev, &msg);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tkfree(data);\n}",
        "static int ice_set_per_vf_res(struct ice_pf *pf, u16 num_vfs)\n{\n\tint max_valid_res_idx = ice_get_max_valid_res_idx(pf->irq_tracker);\n\tu16 num_msix_per_vf, num_txq, num_rxq, avail_qs;\n\tint msix_avail_per_vf, msix_avail_for_sriov;": "static int ice_set_per_vf_res(struct ice_pf *pf, u16 num_vfs)\n{\n\tint max_valid_res_idx = ice_get_max_valid_res_idx(pf->irq_tracker);\n\tu16 num_msix_per_vf, num_txq, num_rxq, avail_qs;\n\tint msix_avail_per_vf, msix_avail_for_sriov;\n\tstruct device *dev = ice_pf_to_dev(pf);\n\tint err;\n\n\tlockdep_assert_held(&pf->vfs.table_lock);\n\n\tif (!num_vfs)\n\t\treturn -EINVAL;\n\n\tif (max_valid_res_idx < 0)\n\t\treturn -ENOSPC;\n\n\t/* determine MSI-X resources per VF */\n\tmsix_avail_for_sriov = pf->hw.func_caps.common_cap.num_msix_vectors -\n\t\tpf->irq_tracker->num_entries;\n\tmsix_avail_per_vf = msix_avail_for_sriov / num_vfs;\n\tif (msix_avail_per_vf >= ICE_NUM_VF_MSIX_MED) {\n\t\tnum_msix_per_vf = ICE_NUM_VF_MSIX_MED;\n\t} else if (msix_avail_per_vf >= ICE_NUM_VF_MSIX_SMALL) {\n\t\tnum_msix_per_vf = ICE_NUM_VF_MSIX_SMALL;\n\t} else if (msix_avail_per_vf >= ICE_NUM_VF_MSIX_MULTIQ_MIN) {\n\t\tnum_msix_per_vf = ICE_NUM_VF_MSIX_MULTIQ_MIN;\n\t} else if (msix_avail_per_vf >= ICE_MIN_INTR_PER_VF) {\n\t\tnum_msix_per_vf = ICE_MIN_INTR_PER_VF;\n\t} else {\n\t\tdev_err(dev, \"Only %d MSI-X interrupts available for SR-IOV. Not enough to support minimum of %d MSI-X interrupts per VF for %d VFs\\n\",\n\t\t\tmsix_avail_for_sriov, ICE_MIN_INTR_PER_VF,\n\t\t\tnum_vfs);\n\t\treturn -ENOSPC;\n\t}\n\n\tnum_txq = min_t(u16, num_msix_per_vf - ICE_NONQ_VECS_VF,\n\t\t\tICE_MAX_RSS_QS_PER_VF);\n\tavail_qs = ice_get_avail_txq_count(pf) / num_vfs;\n\tif (!avail_qs)\n\t\tnum_txq = 0;\n\telse if (num_txq > avail_qs)\n\t\tnum_txq = rounddown_pow_of_two(avail_qs);\n\n\tnum_rxq = min_t(u16, num_msix_per_vf - ICE_NONQ_VECS_VF,\n\t\t\tICE_MAX_RSS_QS_PER_VF);\n\tavail_qs = ice_get_avail_rxq_count(pf) / num_vfs;\n\tif (!avail_qs)\n\t\tnum_rxq = 0;\n\telse if (num_rxq > avail_qs)\n\t\tnum_rxq = rounddown_pow_of_two(avail_qs);\n\n\tif (num_txq < ICE_MIN_QS_PER_VF || num_rxq < ICE_MIN_QS_PER_VF) {\n\t\tdev_err(dev, \"Not enough queues to support minimum of %d queue pairs per VF for %d VFs\\n\",\n\t\t\tICE_MIN_QS_PER_VF, num_vfs);\n\t\treturn -ENOSPC;\n\t}\n\n\terr = ice_sriov_set_msix_res(pf, num_msix_per_vf * num_vfs);\n\tif (err) {\n\t\tdev_err(dev, \"Unable to set MSI-X resources for %d VFs, err %d\\n\",\n\t\t\tnum_vfs, err);\n\t\treturn err;\n\t}\n\n\t/* only allow equal Tx/Rx queue count (i.e. queue pairs) */\n\tpf->vfs.num_qps_per = min_t(int, num_txq, num_rxq);\n\tpf->vfs.num_msix_per = num_msix_per_vf;\n\tdev_info(dev, \"Enabling %d VFs with %d vectors and %d queues per VF\\n\",\n\t\t num_vfs, pf->vfs.num_msix_per, pf->vfs.num_qps_per);\n\n\treturn 0;\n}",
        "static int atmel_nand_pmecc_init(struct nand_chip *chip)\n{\n\tconst struct nand_ecc_props *requirements =\n\t\tnanddev_get_ecc_requirements(&chip->base);\n\tstruct mtd_info *mtd = nand_to_mtd(chip);": "static int atmel_nand_pmecc_init(struct nand_chip *chip)\n{\n\tconst struct nand_ecc_props *requirements =\n\t\tnanddev_get_ecc_requirements(&chip->base);\n\tstruct mtd_info *mtd = nand_to_mtd(chip);\n\tstruct nand_device *nanddev = mtd_to_nanddev(mtd);\n\tstruct atmel_nand *nand = to_atmel_nand(chip);\n\tstruct atmel_nand_controller *nc;\n\tstruct atmel_pmecc_user_req req;\n\n\tnc = to_nand_controller(chip->controller);\n\n\tif (!nc->pmecc) {\n\t\tdev_err(nc->dev, \"HW ECC not supported\\n\");\n\t\treturn -ENOTSUPP;\n\t}\n\n\tif (nc->caps->legacy_of_bindings) {\n\t\tu32 val;\n\n\t\tif (!of_property_read_u32(nc->dev->of_node, \"atmel,pmecc-cap\",\n\t\t\t\t\t  &val))\n\t\t\tchip->ecc.strength = val;\n\n\t\tif (!of_property_read_u32(nc->dev->of_node,\n\t\t\t\t\t  \"atmel,pmecc-sector-size\",\n\t\t\t\t\t  &val))\n\t\t\tchip->ecc.size = val;\n\t}\n\n\tif (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)\n\t\treq.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;\n\telse if (chip->ecc.strength)\n\t\treq.ecc.strength = chip->ecc.strength;\n\telse if (requirements->strength)\n\t\treq.ecc.strength = requirements->strength;\n\telse\n\t\treq.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;\n\n\tif (chip->ecc.size)\n\t\treq.ecc.sectorsize = chip->ecc.size;\n\telse if (requirements->step_size)\n\t\treq.ecc.sectorsize = requirements->step_size;\n\telse\n\t\treq.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;\n\n\treq.pagesize = mtd->writesize;\n\treq.oobsize = mtd->oobsize;\n\n\tif (mtd->writesize <= 512) {\n\t\treq.ecc.bytes = 4;\n\t\treq.ecc.ooboffset = 0;\n\t} else {\n\t\treq.ecc.bytes = mtd->oobsize - 2;\n\t\treq.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;\n\t}\n\n\tnand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);\n\tif (IS_ERR(nand->pmecc))\n\t\treturn PTR_ERR(nand->pmecc);\n\n\tchip->ecc.algo = NAND_ECC_ALGO_BCH;\n\tchip->ecc.size = req.ecc.sectorsize;\n\tchip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;\n\tchip->ecc.strength = req.ecc.strength;\n\n\tchip->options |= NAND_NO_SUBPAGE_WRITE;\n\n\tmtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());\n\n\treturn 0;\n}",
        "static int damon_sysfs_upd_schemes_stats(struct damon_sysfs_kdamond *kdamond)\n{\n\tstruct damon_ctx *ctx = kdamond->damon_ctx;\n\tstruct damon_sysfs_schemes *sysfs_schemes;\n\tstruct damos *scheme;": "static int damon_sysfs_upd_schemes_stats(struct damon_sysfs_kdamond *kdamond)\n{\n\tstruct damon_ctx *ctx = kdamond->damon_ctx;\n\tstruct damon_sysfs_schemes *sysfs_schemes;\n\tstruct damos *scheme;\n\tint schemes_idx = 0;\n\n\tif (!ctx)\n\t\treturn -EINVAL;\n\tsysfs_schemes = kdamond->contexts->contexts_arr[0]->schemes;\n\tdamon_for_each_scheme(scheme, ctx) {\n\t\tstruct damon_sysfs_stats *sysfs_stats;\n\n\t\tsysfs_stats = sysfs_schemes->schemes_arr[schemes_idx++]->stats;\n\t\tsysfs_stats->nr_tried = scheme->stat.nr_tried;\n\t\tsysfs_stats->sz_tried = scheme->stat.sz_tried;\n\t\tsysfs_stats->nr_applied = scheme->stat.nr_applied;\n\t\tsysfs_stats->sz_applied = scheme->stat.sz_applied;\n\t\tsysfs_stats->qt_exceeds = scheme->stat.qt_exceeds;\n\t}\n\treturn 0;\n}",
        "static int alloc_try_nid_top_down_cap_min_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_top_down_cap_min_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_1K;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM() - SZ_256;\n\tmax_addr = memblock_end_of_DRAM();\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == memblock_end_of_DRAM() - size);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static int read_partial_message(struct ceph_connection *con)\n{\n\tstruct ceph_msg *m = con->in_msg;\n\tint size;\n\tint end;": "static int read_partial_message(struct ceph_connection *con)\n{\n\tstruct ceph_msg *m = con->in_msg;\n\tint size;\n\tint end;\n\tint ret;\n\tunsigned int front_len, middle_len, data_len;\n\tbool do_datacrc = !ceph_test_opt(from_msgr(con->msgr), NOCRC);\n\tbool need_sign = (con->peer_features & CEPH_FEATURE_MSG_AUTH);\n\tu64 seq;\n\tu32 crc;\n\n\tdout(\"read_partial_message con %p msg %p\\n\", con, m);\n\n\t/* header */\n\tsize = sizeof(con->v1.in_hdr);\n\tend = size;\n\tret = read_partial(con, end, size, &con->v1.in_hdr);\n\tif (ret <= 0)\n\t\treturn ret;\n\n\tcrc = crc32c(0, &con->v1.in_hdr, offsetof(struct ceph_msg_header, crc));\n\tif (cpu_to_le32(crc) != con->v1.in_hdr.crc) {\n\t\tpr_err(\"read_partial_message bad hdr crc %u != expected %u\\n\",\n\t\t       crc, con->v1.in_hdr.crc);\n\t\treturn -EBADMSG;\n\t}\n\n\tfront_len = le32_to_cpu(con->v1.in_hdr.front_len);\n\tif (front_len > CEPH_MSG_MAX_FRONT_LEN)\n\t\treturn -EIO;\n\tmiddle_len = le32_to_cpu(con->v1.in_hdr.middle_len);\n\tif (middle_len > CEPH_MSG_MAX_MIDDLE_LEN)\n\t\treturn -EIO;\n\tdata_len = le32_to_cpu(con->v1.in_hdr.data_len);\n\tif (data_len > CEPH_MSG_MAX_DATA_LEN)\n\t\treturn -EIO;\n\n\t/* verify seq# */\n\tseq = le64_to_cpu(con->v1.in_hdr.seq);\n\tif ((s64)seq - (s64)con->in_seq < 1) {\n\t\tpr_info(\"skipping %s%lld %s seq %lld expected %lld\\n\",\n\t\t\tENTITY_NAME(con->peer_name),\n\t\t\tceph_pr_addr(&con->peer_addr),\n\t\t\tseq, con->in_seq + 1);\n\t\tcon->v1.in_base_pos = -front_len - middle_len - data_len -\n\t\t\t\t      sizeof_footer(con);\n\t\tcon->v1.in_tag = CEPH_MSGR_TAG_READY;\n\t\treturn 1;\n\t} else if ((s64)seq - (s64)con->in_seq > 1) {\n\t\tpr_err(\"read_partial_message bad seq %lld expected %lld\\n\",\n\t\t       seq, con->in_seq + 1);\n\t\tcon->error_msg = \"bad message sequence # for incoming message\";\n\t\treturn -EBADE;\n\t}\n\n\t/* allocate message? */\n\tif (!con->in_msg) {\n\t\tint skip = 0;\n\n\t\tdout(\"got hdr type %d front %d data %d\\n\", con->v1.in_hdr.type,\n\t\t     front_len, data_len);\n\t\tret = ceph_con_in_msg_alloc(con, &con->v1.in_hdr, &skip);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tBUG_ON((!con->in_msg) ^ skip);\n\t\tif (skip) {\n\t\t\t/* skip this message */\n\t\t\tdout(\"alloc_msg said skip message\\n\");\n\t\t\tcon->v1.in_base_pos = -front_len - middle_len -\n\t\t\t\t\t      data_len - sizeof_footer(con);\n\t\t\tcon->v1.in_tag = CEPH_MSGR_TAG_READY;\n\t\t\tcon->in_seq++;\n\t\t\treturn 1;\n\t\t}\n\n\t\tBUG_ON(!con->in_msg);\n\t\tBUG_ON(con->in_msg->con != con);\n\t\tm = con->in_msg;\n\t\tm->front.iov_len = 0;    /* haven't read it yet */\n\t\tif (m->middle)\n\t\t\tm->middle->vec.iov_len = 0;\n\n\t\t/* prepare for data payload, if any */\n\n\t\tif (data_len)\n\t\t\tprepare_message_data(con->in_msg, data_len);\n\t}\n\n\t/* front */\n\tret = read_partial_message_section(con, &m->front, front_len,\n\t\t\t\t\t   &con->in_front_crc);\n\tif (ret <= 0)\n\t\treturn ret;\n\n\t/* middle */\n\tif (m->middle) {\n\t\tret = read_partial_message_section(con, &m->middle->vec,\n\t\t\t\t\t\t   middle_len,\n\t\t\t\t\t\t   &con->in_middle_crc);\n\t\tif (ret <= 0)\n\t\t\treturn ret;\n\t}\n\n\t/* (page) data */\n\tif (data_len) {\n\t\tif (!m->num_data_items)\n\t\t\treturn -EIO;\n\n\t\tif (ceph_test_opt(from_msgr(con->msgr), RXBOUNCE))\n\t\t\tret = read_partial_msg_data_bounce(con);\n\t\telse\n\t\t\tret = read_partial_msg_data(con);\n\t\tif (ret <= 0)\n\t\t\treturn ret;\n\t}\n\n\t/* footer */\n\tsize = sizeof_footer(con);\n\tend += size;\n\tret = read_partial(con, end, size, &m->footer);\n\tif (ret <= 0)\n\t\treturn ret;\n\n\tif (!need_sign) {\n\t\tm->footer.flags = m->old_footer.flags;\n\t\tm->footer.sig = 0;\n\t}\n\n\tdout(\"read_partial_message got msg %p %d (%u) + %d (%u) + %d (%u)\\n\",\n\t     m, front_len, m->footer.front_crc, middle_len,\n\t     m->footer.middle_crc, data_len, m->footer.data_crc);\n\n\t/* crc ok? */\n\tif (con->in_front_crc != le32_to_cpu(m->footer.front_crc)) {\n\t\tpr_err(\"read_partial_message %p front crc %u != exp. %u\\n\",\n\t\t       m, con->in_front_crc, m->footer.front_crc);\n\t\treturn -EBADMSG;\n\t}\n\tif (con->in_middle_crc != le32_to_cpu(m->footer.middle_crc)) {\n\t\tpr_err(\"read_partial_message %p middle crc %u != exp %u\\n\",\n\t\t       m, con->in_middle_crc, m->footer.middle_crc);\n\t\treturn -EBADMSG;\n\t}\n\tif (do_datacrc &&\n\t    (m->footer.flags & CEPH_MSG_FOOTER_NOCRC) == 0 &&\n\t    con->in_data_crc != le32_to_cpu(m->footer.data_crc)) {\n\t\tpr_err(\"read_partial_message %p data crc %u != exp. %u\\n\", m,\n\t\t       con->in_data_crc, le32_to_cpu(m->footer.data_crc));\n\t\treturn -EBADMSG;\n\t}\n\n\tif (need_sign && con->ops->check_message_signature &&\n\t    con->ops->check_message_signature(m)) {\n\t\tpr_err(\"read_partial_message %p signature check failed\\n\", m);\n\t\treturn -EBADMSG;\n\t}\n\n\treturn 1; /* done! */\n}",
        "static int fmvj18x_config(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct local_info *lp = netdev_priv(dev);\n    int i, ret;": "static int fmvj18x_config(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct local_info *lp = netdev_priv(dev);\n    int i, ret;\n    unsigned int ioaddr;\n    enum cardtype cardtype;\n    char *card_name = \"unknown\";\n    u8 *buf;\n    size_t len;\n    u_char buggybuf[32];\n    u8 addr[ETH_ALEN];\n\n    dev_dbg(&link->dev, \"fmvj18x_config\\n\");\n\n    link->io_lines = 5;\n\n    len = pcmcia_get_tuple(link, CISTPL_FUNCE, &buf);\n    kfree(buf);\n\n    if (len) {\n\t/* Yes, I have CISTPL_FUNCE. Let's check CISTPL_MANFID */\n\tret = pcmcia_loop_config(link, fmvj18x_ioprobe, NULL);\n\tif (ret != 0)\n\t\tgoto failed;\n\n\tswitch (link->manf_id) {\n\tcase MANFID_TDK:\n\t    cardtype = TDK;\n\t    if (link->card_id == PRODID_TDK_GN3410 ||\n\t\tlink->card_id == PRODID_TDK_NP9610 ||\n\t\tlink->card_id == PRODID_TDK_MN3200) {\n\t\t/* MultiFunction Card */\n\t\tlink->config_base = 0x800;\n\t\tlink->config_index = 0x47;\n\t\tlink->resource[1]->end = 8;\n\t    }\n\t    break;\n\tcase MANFID_NEC:\n\t    cardtype = NEC; /* MultiFunction Card */\n\t    link->config_base = 0x800;\n\t    link->config_index = 0x47;\n\t    link->resource[1]->end = 8;\n\t    break;\n\tcase MANFID_KME:\n\t    cardtype = KME; /* MultiFunction Card */\n\t    link->config_base = 0x800;\n\t    link->config_index = 0x47;\n\t    link->resource[1]->end = 8;\n\t    break;\n\tcase MANFID_CONTEC:\n\t    cardtype = CONTEC;\n\t    break;\n\tcase MANFID_FUJITSU:\n\t    if (link->config_base == 0x0fe0)\n\t\tcardtype = MBH10302;\n\t    else if (link->card_id == PRODID_FUJITSU_MBH10302) \n                /* RATOC REX-5588/9822/4886's PRODID are 0004(=MBH10302),\n                   but these are MBH10304 based card. */ \n\t\tcardtype = MBH10304;\n\t    else if (link->card_id == PRODID_FUJITSU_MBH10304)\n\t\tcardtype = MBH10304;\n\t    else\n\t\tcardtype = LA501;\n\t    break;\n\tdefault:\n\t    cardtype = MBH10304;\n\t}\n    } else {\n\t/* old type card */\n\tswitch (link->manf_id) {\n\tcase MANFID_FUJITSU:\n\t    if (link->card_id == PRODID_FUJITSU_MBH10304) {\n\t\tcardtype = XXX10304;    /* MBH10304 with buggy CIS */\n\t\tlink->config_index = 0x20;\n\t    } else {\n\t\tcardtype = MBH10302;    /* NextCom NC5310, etc. */\n\t\tlink->config_index = 1;\n\t    }\n\t    break;\n\tcase MANFID_UNGERMANN:\n\t    cardtype = UNGERMANN;\n\t    break;\n\tdefault:\n\t    cardtype = MBH10302;\n\t    link->config_index = 1;\n\t}\n    }\n\n    if (link->resource[1]->end != 0) {\n\tret = mfc_try_io_port(link);\n\tif (ret != 0) goto failed;\n    } else if (cardtype == UNGERMANN) {\n\tret = ungermann_try_io_port(link);\n\tif (ret != 0) goto failed;\n    } else { \n\t    ret = pcmcia_request_io(link);\n\t    if (ret)\n\t\t    goto failed;\n    }\n    ret = pcmcia_request_irq(link, fjn_interrupt);\n    if (ret)\n\t    goto failed;\n    ret = pcmcia_enable_device(link);\n    if (ret)\n\t    goto failed;\n\n    dev->irq = link->irq;\n    dev->base_addr = link->resource[0]->start;\n\n    if (resource_size(link->resource[1]) != 0) {\n\tret = fmvj18x_setup_mfc(link);\n\tif (ret != 0) goto failed;\n    }\n\n    ioaddr = dev->base_addr;\n\n    /* Reset controller */\n    if (sram_config == 0) \n\toutb(CONFIG0_RST, ioaddr + CONFIG_0);\n    else\n\toutb(CONFIG0_RST_1, ioaddr + CONFIG_0);\n\n    /* Power On chip and select bank 0 */\n    if (cardtype == MBH10302)\n\toutb(BANK_0, ioaddr + CONFIG_1);\n    else\n\toutb(BANK_0U, ioaddr + CONFIG_1);\n    \n    /* Set hardware address */\n    switch (cardtype) {\n    case MBH10304:\n    case TDK:\n    case LA501:\n    case CONTEC:\n    case NEC:\n    case KME:\n\tif (cardtype == MBH10304) {\n\t    card_name = \"FMV-J182\";\n\n\t    len = pcmcia_get_tuple(link, CISTPL_FUNCE, &buf);\n\t    if (len < 11) {\n\t\t    kfree(buf);\n\t\t    goto failed;\n\t    }\n\t    /* Read MACID from CIS */\n\t    eth_hw_addr_set(dev, &buf[5]);\n\t    kfree(buf);\n\t} else {\n\t    if (pcmcia_get_mac_from_cis(link, dev))\n\t\tgoto failed;\n\t    if( cardtype == TDK ) {\n\t\tcard_name = \"TDK LAK-CD021\";\n\t    } else if( cardtype == LA501 ) {\n\t\tcard_name = \"LA501\";\n\t    } else if( cardtype == NEC ) {\n\t\tcard_name = \"PK-UG-J001\";\n\t    } else if( cardtype == KME ) {\n\t\tcard_name = \"Panasonic\";\n\t    } else {\n\t\tcard_name = \"C-NET(PC)C\";\n\t    }\n\t}\n\tbreak;\n    case UNGERMANN:\n\t/* Read MACID from register */\n\tfor (i = 0; i < 6; i++) \n\t    addr[i] = inb(ioaddr + UNGERMANN_MAC_ID + i);\n\teth_hw_addr_set(dev, addr);\n\tcard_name = \"Access/CARD\";\n\tbreak;\n    case XXX10304:\n\t/* Read MACID from Buggy CIS */\n\tif (fmvj18x_get_hwinfo(link, buggybuf) == -1) {\n\t    pr_notice(\"unable to read hardware net address\\n\");\n\t    goto failed;\n\t}\n\teth_hw_addr_set(dev, buggybuf);\n\tcard_name = \"FMV-J182\";\n\tbreak;\n    case MBH10302:\n    default:\n\t/* Read MACID from register */\n\tfor (i = 0; i < 6; i++) \n\t    addr[i] = inb(ioaddr + MAC_ID + i);\n\teth_hw_addr_set(dev, addr);\n\tcard_name = \"FMV-J181\";\n\tbreak;\n    }\n\n    lp->cardtype = cardtype;\n    SET_NETDEV_DEV(dev, &link->dev);\n\n    if (register_netdev(dev) != 0) {\n\tpr_notice(\"register_netdev() failed\\n\");\n\tgoto failed;\n    }\n\n    /* print current configuration */\n    netdev_info(dev, \"%s, sram %s, port %#3lx, irq %d, hw_addr %pM\\n\",\n\t\tcard_name, sram_config == 0 ? \"4K TX*2\" : \"8K TX*2\",\n\t\tdev->base_addr, dev->irq, dev->dev_addr);\n\n    return 0;\n    \nfailed:\n    fmvj18x_release(link);\n    return -ENODEV;\n} /* fmvj18x_config */\n/*====================================================================*/\n\nstatic int fmvj18x_get_hwinfo(struct pcmcia_device *link, u_char *node_id)\n{\n    u_char __iomem *base;\n    int i, j;\n\n    /* Allocate a small memory window */\n    link->resource[2]->flags |= WIN_DATA_WIDTH_8|WIN_MEMORY_TYPE_AM|WIN_ENABLE;\n    link->resource[2]->start = 0; link->resource[2]->end = 0;\n    i = pcmcia_request_window(link, link->resource[2], 0);\n    if (i != 0)\n\treturn -1;\n\n    base = ioremap(link->resource[2]->start, resource_size(link->resource[2]));\n    if (!base) {\n\tpcmcia_release_window(link, link->resource[2]);\n\treturn -1;\n    }\n\n    pcmcia_map_mem_page(link, link->resource[2], 0);\n\n    /*\n     *  MBH10304 CISTPL_FUNCE_LAN_NODE_ID format\n     *  22 0d xx xx xx 04 06 yy yy yy yy yy yy ff\n     *  'xx' is garbage.\n     *  'yy' is MAC address.\n    */ \n    for (i = 0; i < 0x200; i++) {\n\tif (readb(base+i*2) == 0x22) {\t\n\t\tif (readb(base+(i-1)*2) == 0xff &&\n\t\t    readb(base+(i+5)*2) == 0x04 &&\n\t\t    readb(base+(i+6)*2) == 0x06 &&\n\t\t    readb(base+(i+13)*2) == 0xff)\n\t\t\tbreak;\n\t}\n    }\n\n    if (i != 0x200) {\n\tfor (j = 0 ; j < 6; j++,i++) {\n\t    node_id[j] = readb(base+(i+7)*2);\n\t}\n    }\n\n    iounmap(base);\n    j = pcmcia_release_window(link, link->resource[2]);\n    return (i != 0x200) ? 0 : -1;\n\n} /* fmvj18x_get_hwinfo */\n/*====================================================================*/\n\nstatic int fmvj18x_setup_mfc(struct pcmcia_device *link)\n{\n    int i;\n    struct net_device *dev = link->priv;\n    unsigned int ioaddr;\n    struct local_info *lp = netdev_priv(dev);\n\n    /* Allocate a small memory window */\n    link->resource[3]->flags = WIN_DATA_WIDTH_8|WIN_MEMORY_TYPE_AM|WIN_ENABLE;\n    link->resource[3]->start = link->resource[3]->end = 0;\n    i = pcmcia_request_window(link, link->resource[3], 0);\n    if (i != 0)\n\treturn -1;\n\n    lp->base = ioremap(link->resource[3]->start,\n\t\t       resource_size(link->resource[3]));\n    if (lp->base == NULL) {\n\tnetdev_notice(dev, \"ioremap failed\\n\");\n\treturn -1;\n    }\n\n    i = pcmcia_map_mem_page(link, link->resource[3], 0);\n    if (i != 0) {\n\tiounmap(lp->base);\n\tlp->base = NULL;\n\treturn -1;\n    }\n    \n    ioaddr = dev->base_addr;\n    writeb(0x47, lp->base+0x800);\t/* Config Option Register of LAN */\n    writeb(0x0,  lp->base+0x802);\t/* Config and Status Register */\n\n    writeb(ioaddr & 0xff, lp->base+0x80a);\t  /* I/O Base(Low) of LAN */\n    writeb((ioaddr >> 8) & 0xff, lp->base+0x80c); /* I/O Base(High) of LAN */\n   \n    writeb(0x45, lp->base+0x820);\t/* Config Option Register of Modem */\n    writeb(0x8,  lp->base+0x822);\t/* Config and Status Register */\n\n    return 0;\n\n}",
        "static int disk_change(int drive)\n{\n\tint fdc = FDC(drive);\n\n\tif (time_before(jiffies, drive_state[drive].select_date + drive_params[drive].select_delay))": "static int disk_change(int drive)\n{\n\tint fdc = FDC(drive);\n\n\tif (time_before(jiffies, drive_state[drive].select_date + drive_params[drive].select_delay))\n\t\tDPRINT(\"WARNING disk change called early\\n\");\n\tif (!(fdc_state[fdc].dor & (0x10 << UNIT(drive))) ||\n\t    (fdc_state[fdc].dor & 3) != UNIT(drive) || fdc != FDC(drive)) {\n\t\tDPRINT(\"probing disk change on unselected drive\\n\");\n\t\tDPRINT(\"drive=%d fdc=%d dor=%x\\n\", drive, FDC(drive),\n\t\t       (unsigned int)fdc_state[fdc].dor);\n\t}\n\n\tdebug_dcl(drive_params[drive].flags,\n\t\t  \"checking disk change line for drive %d\\n\", drive);\n\tdebug_dcl(drive_params[drive].flags, \"jiffies=%lu\\n\", jiffies);\n\tdebug_dcl(drive_params[drive].flags, \"disk change line=%x\\n\",\n\t\t  fdc_inb(fdc, FD_DIR) & 0x80);\n\tdebug_dcl(drive_params[drive].flags, \"flags=%lx\\n\",\n\t\t  drive_state[drive].flags);\n\n\tif (drive_params[drive].flags & FD_BROKEN_DCL)\n\t\treturn test_bit(FD_DISK_CHANGED_BIT,\n\t\t\t\t&drive_state[drive].flags);\n\tif ((fdc_inb(fdc, FD_DIR) ^ drive_params[drive].flags) & 0x80) {\n\t\tset_bit(FD_VERIFY_BIT, &drive_state[drive].flags);\n\t\t\t\t\t/* verify write protection */\n\n\t\tif (drive_state[drive].maxblock)\t/* mark it changed */\n\t\t\tset_bit(FD_DISK_CHANGED_BIT,\n\t\t\t\t&drive_state[drive].flags);\n\n\t\t/* invalidate its geometry */\n\t\tif (drive_state[drive].keep_data >= 0) {\n\t\t\tif ((drive_params[drive].flags & FTD_MSG) &&\n\t\t\t    current_type[drive] != NULL)\n\t\t\t\tDPRINT(\"Disk type is undefined after disk change\\n\");\n\t\t\tcurrent_type[drive] = NULL;\n\t\t\tfloppy_sizes[TOMINOR(drive)] = MAX_DISK_SIZE << 1;\n\t\t}\n\n\t\treturn 1;\n\t} else {\n\t\tdrive_state[drive].last_checked = jiffies;\n\t\tclear_bit(FD_DISK_NEWCHANGE_BIT, &drive_state[drive].flags);\n\t}\n\treturn 0;\n}",
        "static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)\n{\n\tstruct device *dev = &pcie->pdev->dev;\n\n\t/*": "static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)\n{\n\tstruct device *dev = &pcie->pdev->dev;\n\n\t/*\n\t * Trying to start a new PIO transfer when previous has not completed\n\t * cause External Abort on CPU which results in kernel panic:\n\t *\n\t *     SError Interrupt on CPU0, code 0xbf000002 -- SError\n\t *     Kernel panic - not syncing: Asynchronous SError Interrupt\n\t *\n\t * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected\n\t * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent\n\t * concurrent calls at the same time. But because PIO transfer may take\n\t * about 1.5s when link is down or card is disconnected, it means that\n\t * advk_pcie_wait_pio() does not always have to wait for completion.\n\t *\n\t * Some versions of ARM Trusted Firmware handles this External Abort at\n\t * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:\n\t * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50\n\t */\n\tif (advk_readl(pcie, PIO_START)) {\n\t\tdev_err(dev, \"Previous PIO read/write transfer is still running\\n\");\n\t\treturn true;\n\t}\n\n\treturn false;\n}",
        "static int drxj_close(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tenum drx_power_mode power_mode = DRX_POWER_UP;": "static int drxj_close(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tenum drx_power_mode power_mode = DRX_POWER_UP;\n\n\tif ((demod->my_common_attr == NULL) ||\n\t    (demod->my_ext_attr == NULL) ||\n\t    (demod->my_i2c_dev_addr == NULL) ||\n\t    (!demod->my_common_attr->is_opened)) {\n\t\treturn -EINVAL;\n\t}\n\n\t/* power up */\n\trc = ctrl_power_mode(demod, &power_mode);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\trc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tpower_mode = DRX_POWER_DOWN;\n\trc = ctrl_power_mode(demod, &power_mode);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\tDRX_ATTR_ISOPENED(demod) = false;\n\n\treturn 0;\nrw_error:\n\tDRX_ATTR_ISOPENED(demod) = false;\n\n\treturn rc;\n}",
        "static void __attribute__((noreturn)) cs_usage(const char *bin)\n{\n\tprintf(\"Usage: %s [opts] <dst host> <dst port / service>\\n\", bin);\n\tprintf(\"Options:\\n\"\n\t       \"\\t\\t-s      Silent send() failures\\n\"": "static void __attribute__((noreturn)) cs_usage(const char *bin)\n{\n\tprintf(\"Usage: %s [opts] <dst host> <dst port / service>\\n\", bin);\n\tprintf(\"Options:\\n\"\n\t       \"\\t\\t-s      Silent send() failures\\n\"\n\t       \"\\t\\t-S      send() size\\n\"\n\t       \"\\t\\t-4/-6   Force IPv4 / IPv6 only\\n\"\n\t       \"\\t\\t-p prot Socket protocol\\n\"\n\t       \"\\t\\t        (u = UDP (default); i = ICMP; r = RAW)\\n\"\n\t       \"\\n\"\n\t       \"\\t\\t-m val  Set SO_MARK with given value\\n\"\n\t       \"\\t\\t-M val  Set SO_MARK via setsockopt\\n\"\n\t       \"\\t\\t-d val  Set SO_TXTIME with given delay (usec)\\n\"\n\t       \"\\t\\t-t      Enable time stamp reporting\\n\"\n\t       \"\\t\\t-f val  Set don't fragment via cmsg\\n\"\n\t       \"\\t\\t-F val  Set don't fragment via setsockopt\\n\"\n\t       \"\\t\\t-c val  Set TCLASS via cmsg\\n\"\n\t       \"\\t\\t-C val  Set TCLASS via setsockopt\\n\"\n\t       \"\\t\\t-l val  Set HOPLIMIT via cmsg\\n\"\n\t       \"\\t\\t-L val  Set HOPLIMIT via setsockopt\\n\"\n\t       \"\\t\\t-H type Add an IPv6 header option\\n\"\n\t       \"\\t\\t        (h = HOP; d = DST; r = RTDST)\"\n\t       \"\");\n\texit(ERN_HELP);\n}",
        "static int es58x_alloc_rx_urbs(struct es58x_device *es58x_dev)\n{\n\tconst struct device *dev = es58x_dev->dev;\n\tconst struct es58x_parameters *param = es58x_dev->param;\n\tsize_t rx_buf_len = es58x_dev->rx_max_packet_size;": "static int es58x_alloc_rx_urbs(struct es58x_device *es58x_dev)\n{\n\tconst struct device *dev = es58x_dev->dev;\n\tconst struct es58x_parameters *param = es58x_dev->param;\n\tsize_t rx_buf_len = es58x_dev->rx_max_packet_size;\n\tstruct urb *urb;\n\tu8 *buf;\n\tint i;\n\tint ret = -EINVAL;\n\n\tfor (i = 0; i < param->rx_urb_max; i++) {\n\t\tret = es58x_alloc_urb(es58x_dev, &urb, &buf, rx_buf_len,\n\t\t\t\t      GFP_KERNEL);\n\t\tif (ret)\n\t\t\tbreak;\n\n\t\tusb_fill_bulk_urb(urb, es58x_dev->udev, es58x_dev->rx_pipe,\n\t\t\t\t  buf, rx_buf_len, es58x_read_bulk_callback,\n\t\t\t\t  es58x_dev);\n\t\tusb_anchor_urb(urb, &es58x_dev->rx_urbs);\n\n\t\tret = usb_submit_urb(urb, GFP_KERNEL);\n\t\tif (ret) {\n\t\t\tusb_unanchor_urb(urb);\n\t\t\tusb_free_coherent(es58x_dev->udev, rx_buf_len,\n\t\t\t\t\t  buf, urb->transfer_dma);\n\t\t\tusb_free_urb(urb);\n\t\t\tbreak;\n\t\t}\n\t\tusb_free_urb(urb);\n\t}\n\n\tif (i == 0) {\n\t\tdev_err(dev, \"%s: Could not setup any rx URBs\\n\", __func__);\n\t\treturn ret;\n\t}\n\tdev_dbg(dev, \"%s: Allocated %d rx URBs each of size %zu\\n\",\n\t\t__func__, i, rx_buf_len);\n\n\treturn ret;\n}",
        "static bool tcpm_vdm_ams(struct tcpm_port *port)\n{\n\tswitch (port->ams) {\n\tcase DISCOVER_IDENTITY:\n\tcase SOURCE_STARTUP_CABLE_PLUG_DISCOVER_IDENTITY:": "static bool tcpm_vdm_ams(struct tcpm_port *port)\n{\n\tswitch (port->ams) {\n\tcase DISCOVER_IDENTITY:\n\tcase SOURCE_STARTUP_CABLE_PLUG_DISCOVER_IDENTITY:\n\tcase DISCOVER_SVIDS:\n\tcase DISCOVER_MODES:\n\tcase DFP_TO_UFP_ENTER_MODE:\n\tcase DFP_TO_UFP_EXIT_MODE:\n\tcase DFP_TO_CABLE_PLUG_ENTER_MODE:\n\tcase DFP_TO_CABLE_PLUG_EXIT_MODE:\n\tcase ATTENTION:\n\tcase UNSTRUCTURED_VDMS:\n\tcase STRUCTURED_VDMS:\n\t\tbreak;\n\tdefault:\n\t\treturn false;\n\t}\n\n\treturn true;\n}",
        "static int reset_sd(struct rtsx_chip *chip)\n{\n\tstruct sd_info *sd_card = &chip->sd_card;\n\tbool hi_cap_flow = false;\n\tint retval, i = 0, j = 0, k = 0;": "static int reset_sd(struct rtsx_chip *chip)\n{\n\tstruct sd_info *sd_card = &chip->sd_card;\n\tbool hi_cap_flow = false;\n\tint retval, i = 0, j = 0, k = 0;\n\tbool sd_dont_switch = false;\n\tbool support_1v8 = false;\n\tbool try_sdio = true;\n\tu8 rsp[16];\n\tu8 switch_bus_width;\n\tu32 voltage = 0;\n\tbool sd20_mode = false;\n\n\tSET_SD(sd_card);\n\nswitch_fail:\n\n\ti = 0;\n\tj = 0;\n\tk = 0;\n\thi_cap_flow = false;\n\n#ifdef SUPPORT_SD_LOCK\n\tif (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)\n\t\tgoto SD_UNLOCK_ENTRY;\n#endif\n\n\tretval = sd_prepare_reset(chip);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tretval = sd_dummy_clock(chip);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tif (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {\n\t\tint rty_cnt = 0;\n\n\t\tfor (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {\n\t\t\tif (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {\n\t\t\t\tsd_set_err_code(chip, SD_NO_CARD);\n\t\t\t\tgoto status_fail;\n\t\t\t}\n\n\t\t\tretval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,\n\t\t\t\t\t\t     SD_RSP_TYPE_R4, rsp, 5);\n\t\t\tif (retval == STATUS_SUCCESS) {\n\t\t\t\tint func_num = (rsp[1] >> 4) & 0x07;\n\n\t\t\t\tif (func_num) {\n\t\t\t\t\tdev_dbg(rtsx_dev(chip), \"SD_IO card (Function number: %d)!\\n\",\n\t\t\t\t\t\tfunc_num);\n\t\t\t\t\tchip->sd_io = 1;\n\t\t\t\t\tgoto status_fail;\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tsd_init_power(chip);\n\n\t\t\tsd_dummy_clock(chip);\n\t\t}\n\n\t\tdev_dbg(rtsx_dev(chip), \"Normal card!\\n\");\n\t}\n\n\t/* Start Initialization Process of SD Card */\nRTY_SD_RST:\n\tretval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,\n\t\t\t\t     NULL, 0);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\twait_timeout(20);\n\n\tretval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,\n\t\t\t\t     SD_RSP_TYPE_R7, rsp, 5);\n\tif (retval == STATUS_SUCCESS) {\n\t\tif (rsp[4] == 0xAA && ((rsp[3] & 0x0f) == 0x01)) {\n\t\t\thi_cap_flow = true;\n\t\t\tvoltage = SUPPORT_VOLTAGE | 0x40000000;\n\t\t}\n\t}\n\n\tif (!hi_cap_flow) {\n\t\tvoltage = SUPPORT_VOLTAGE;\n\n\t\tretval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,\n\t\t\t\t\t     SD_RSP_TYPE_R0, NULL, 0);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\n\t\twait_timeout(20);\n\t}\n\n\tdo {\n\t\tretval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,\n\t\t\t\t\t     NULL, 0);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tif (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {\n\t\t\t\tsd_set_err_code(chip, SD_NO_CARD);\n\t\t\t\tgoto status_fail;\n\t\t\t}\n\n\t\t\tj++;\n\t\t\tif (j < 3)\n\t\t\t\tgoto RTY_SD_RST;\n\t\t\telse\n\t\t\t\tgoto status_fail;\n\t\t}\n\n\t\tretval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,\n\t\t\t\t\t     SD_RSP_TYPE_R3, rsp, 5);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tk++;\n\t\t\tif (k < 3)\n\t\t\t\tgoto RTY_SD_RST;\n\t\t\telse\n\t\t\t\tgoto status_fail;\n\t\t}\n\n\t\ti++;\n\t\twait_timeout(20);\n\t} while (!(rsp[1] & 0x80) && (i < 255));\n\n\tif (i == 255)\n\t\tgoto status_fail;\n\n\tif (hi_cap_flow) {\n\t\tif (rsp[1] & 0x40)\n\t\t\tSET_SD_HCXC(sd_card);\n\t\telse\n\t\t\tCLR_SD_HCXC(sd_card);\n\n\t\tsupport_1v8 = false;\n\t} else {\n\t\tCLR_SD_HCXC(sd_card);\n\t\tsupport_1v8 = false;\n\t}\n\tdev_dbg(rtsx_dev(chip), \"support_1v8 = %d\\n\", support_1v8);\n\n\tif (support_1v8) {\n\t\tretval = sd_voltage_switch(chip);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\t}\n\n\tretval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,\n\t\t\t\t     NULL, 0);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tfor (i = 0; i < 3; i++) {\n\t\tretval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,\n\t\t\t\t\t     SD_RSP_TYPE_R6, rsp, 5);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\n\t\tsd_card->sd_addr = (u32)rsp[1] << 24;\n\t\tsd_card->sd_addr += (u32)rsp[2] << 16;\n\n\t\tif (sd_card->sd_addr)\n\t\t\tbreak;\n\t}\n\n\tretval = sd_check_csd(chip, 1);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tretval = sd_select_card(chip, 1);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n#ifdef SUPPORT_SD_LOCK\nSD_UNLOCK_ENTRY:\n\tretval = sd_update_lock_status(chip);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tif (sd_card->sd_lock_status & SD_LOCKED) {\n\t\tsd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);\n\t\treturn STATUS_SUCCESS;\n\t} else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {\n\t\tsd_card->sd_lock_status &= ~SD_PWD_EXIST;\n\t}\n#endif\n\n\tretval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,\n\t\t\t\t     SD_RSP_TYPE_R1, NULL, 0);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tretval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,\n\t\t\t\t     SD_RSP_TYPE_R1, NULL, 0);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tif (support_1v8) {\n\t\tretval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,\n\t\t\t\t\t     SD_RSP_TYPE_R1, NULL, 0);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\n\t\tretval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,\n\t\t\t\t\t     SD_RSP_TYPE_R1, NULL, 0);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\n\t\tswitch_bus_width = SD_BUS_WIDTH_4;\n\t} else {\n\t\tswitch_bus_width = SD_BUS_WIDTH_1;\n\t}\n\n\tretval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,\n\t\t\t\t     NULL, 0);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tretval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tif (!(sd_card->raw_csd[4] & 0x40))\n\t\tsd_dont_switch = true;\n\n\tif (!sd_dont_switch) {\n\t\tif (sd20_mode) {\n\t\t\t/* Set sd_switch_fail here, because we needn't\n\t\t\t * switch to UHS mode\n\t\t\t */\n\t\t\tsd_card->sd_switch_fail = SDR104_SUPPORT_MASK |\n\t\t\t\tDDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;\n\t\t}\n\n\t\t/* Check the card whether follow SD1.1 spec or higher */\n\t\tretval = sd_check_spec(chip, switch_bus_width);\n\t\tif (retval == STATUS_SUCCESS) {\n\t\t\tretval = sd_switch_function(chip, switch_bus_width);\n\t\t\tif (retval != STATUS_SUCCESS) {\n\t\t\t\tsd_init_power(chip);\n\t\t\t\tsd_dont_switch = true;\n\t\t\t\ttry_sdio = false;\n\n\t\t\t\tgoto switch_fail;\n\t\t\t}\n\t\t} else {\n\t\t\tif (support_1v8) {\n\t\t\t\tsd_init_power(chip);\n\t\t\t\tsd_dont_switch = true;\n\t\t\t\ttry_sdio = false;\n\n\t\t\t\tgoto switch_fail;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (!support_1v8) {\n\t\tretval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,\n\t\t\t\t\t     SD_RSP_TYPE_R1, NULL, 0);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\n\t\tretval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,\n\t\t\t\t\t     SD_RSP_TYPE_R1, NULL, 0);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\t}\n\n#ifdef SUPPORT_SD_LOCK\n\tsd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;\n#endif\n\n\tif (!sd20_mode && CHK_SD30_SPEED(sd_card)) {\n\t\tint read_lba0 = 1;\n\n\t\tretval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07,\n\t\t\t\t\t     chip->sd30_drive_sel_1v8);\n\t\tif (retval)\n\t\t\treturn retval;\n\n\t\tretval = sd_set_init_para(chip);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\tgoto status_fail;\n\n\t\tif (CHK_SD_DDR50(sd_card))\n\t\t\tretval = sd_ddr_tuning(chip);\n\t\telse\n\t\t\tretval = sd_sdr_tuning(chip);\n\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tretval = sd_init_power(chip);\n\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\tgoto status_fail;\n\n\t\t\ttry_sdio = false;\n\t\t\tsd20_mode = true;\n\t\t\tgoto switch_fail;\n\t\t}\n\n\t\tsd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,\n\t\t\t\t    SD_RSP_TYPE_R1, NULL, 0);\n\n\t\tif (CHK_SD_DDR50(sd_card)) {\n\t\t\tretval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);\n\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\tread_lba0 = 0;\n\t\t}\n\n\t\tif (read_lba0) {\n\t\t\tretval = sd_read_lba0(chip);\n\t\t\tif (retval != STATUS_SUCCESS) {\n\t\t\t\tretval = sd_init_power(chip);\n\t\t\t\tif (retval != STATUS_SUCCESS)\n\t\t\t\t\tgoto status_fail;\n\n\t\t\t\ttry_sdio = false;\n\t\t\t\tsd20_mode = true;\n\t\t\t\tgoto switch_fail;\n\t\t\t}\n\t\t}\n\t}\n\n\tretval = sd_check_wp_state(chip);\n\tif (retval != STATUS_SUCCESS)\n\t\tgoto status_fail;\n\n\tchip->card_bus_width[chip->card2lun[SD_CARD]] = 4;\n\n#ifdef SUPPORT_SD_LOCK\n\tif (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {\n\t\tretval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,\n\t\t\t\t\t     0x02);\n\t\tif (retval)\n\t\t\treturn retval;\n\t\tretval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,\n\t\t\t\t\t     0x00);\n\t\tif (retval)\n\t\t\treturn retval;\n\t}\n#endif\n\n\treturn STATUS_SUCCESS;\n\nstatus_fail:\n\treturn STATUS_FAIL;\n}",
        "static void sh7760_i2c_msend(struct cami2c *id)\n{\n\tint len;\n\n\tid->flags |= IDF_SEND;": "static void sh7760_i2c_msend(struct cami2c *id)\n{\n\tint len;\n\n\tid->flags |= IDF_SEND;\n\n\t/* set the slave addr reg; otherwise xmit wont work! */\n\tOUT32(id, I2CSAR, 0xfe);\n\tOUT32(id, I2CMAR, (id->msg->addr << 1) | 0);\n\n\t/* adjust tx fifo trigger */\n\tif (id->msg->len >= FIFO_SIZE)\n\t\tlen = 2;\t/* trig: 2 bytes left in TX fifo */\n\telse\n\t\tlen = 0;\t/* trig: 8 bytes left in TX fifo */\n\n\tOUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);\n\tOUT32(id, I2CFCR, FCR_RFRST | ((len & 3) << 2));\n\n\twhile (id->msg->len && IN32(id, I2CTFDR) < FIFO_SIZE) {\n\t\tOUT32(id, I2CRXTX, *(id->msg->buf));\n\t\t(id->msg->len)--;\n\t\t(id->msg->buf)++;\n\t}\n\n\tOUT32(id, I2CMSR, 0);\n\tOUT32(id, I2CMCR, MCR_MIE | MCR_ESG);\n\tOUT32(id, I2CFSR, 0);\n\tOUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);\n\tOUT32(id, I2CFIER, FIER_TEIE | (id->msg->len ? FIER_TXIE : 0));\n}",
        "static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)\n{\n\tu32 *arg = data;\n\tint i, ret;\n\tu32 xsr;": "static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)\n{\n\tu32 *arg = data;\n\tint i, ret;\n\tu32 xsr;\n\tu32 size, max_size, num_tr;\n\n\tif (priv->dcfg->type & IMX_MU_V2_S4) {\n\t\tsize = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;\n\t\tmax_size = sizeof(struct imx_s4_rpc_msg_max);\n\t\tnum_tr = 8;\n\t} else {\n\t\tsize = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;\n\t\tmax_size = sizeof(struct imx_sc_rpc_msg_max);\n\t\tnum_tr = 4;\n\t}\n\n\tswitch (cp->type) {\n\tcase IMX_MU_TYPE_TX:\n\t\t/*\n\t\t * msg->hdr.size specifies the number of u32 words while\n\t\t * sizeof yields bytes.\n\t\t */\n\n\t\tif (size > max_size / 4) {\n\t\t\t/*\n\t\t\t * The real message size can be different to\n\t\t\t * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size\n\t\t\t */\n\t\t\tdev_err(priv->dev, \"Maximal message size (%u bytes) exceeded on TX; got: %i bytes\\n\", max_size, size << 2);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tfor (i = 0; i < num_tr && i < size; i++)\n\t\t\timx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);\n\t\tfor (; i < size; i++) {\n\t\t\tret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],\n\t\t\t\t\t\t xsr,\n\t\t\t\t\t\t xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),\n\t\t\t\t\t\t 0, 5 * USEC_PER_SEC);\n\t\t\tif (ret) {\n\t\t\t\tdev_err(priv->dev, \"Send data index: %d timeout\\n\", i);\n\t\t\t\treturn ret;\n\t\t\t}\n\t\t\timx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);\n\t\t}\n\n\t\timx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);\n\t\tbreak;\n\tdefault:\n\t\tdev_warn_ratelimited(priv->dev, \"Send data on wrong channel type: %d\\n\", cp->type);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}",
        "static void print_cfs_group_stats(struct seq_file *m, int cpu, struct task_group *tg)\n{\n\tstruct sched_entity *se = tg->se[cpu];\n\n#define P(F)\t\tSEQ_printf(m, \"  .%-30s: %lld\\n\",\t#F, (long long)F)": "static void print_cfs_group_stats(struct seq_file *m, int cpu, struct task_group *tg)\n{\n\tstruct sched_entity *se = tg->se[cpu];\n\n#define P(F)\t\tSEQ_printf(m, \"  .%-30s: %lld\\n\",\t#F, (long long)F)\n#define P_SCHEDSTAT(F)\tSEQ_printf(m, \"  .%-30s: %lld\\n\",\t\\\n\t\t#F, (long long)schedstat_val(stats->F))\n#define PN(F)\t\tSEQ_printf(m, \"  .%-30s: %lld.%06ld\\n\", #F, SPLIT_NS((long long)F))\n#define PN_SCHEDSTAT(F)\tSEQ_printf(m, \"  .%-30s: %lld.%06ld\\n\", \\\n\t\t#F, SPLIT_NS((long long)schedstat_val(stats->F)))\n\n\tif (!se)\n\t\treturn;\n\n\tPN(se->exec_start);\n\tPN(se->vruntime);\n\tPN(se->sum_exec_runtime);\n\n\tif (schedstat_enabled()) {\n\t\tstruct sched_statistics *stats;\n\t\tstats = __schedstats_from_se(se);\n\n\t\tPN_SCHEDSTAT(wait_start);\n\t\tPN_SCHEDSTAT(sleep_start);\n\t\tPN_SCHEDSTAT(block_start);\n\t\tPN_SCHEDSTAT(sleep_max);\n\t\tPN_SCHEDSTAT(block_max);\n\t\tPN_SCHEDSTAT(exec_max);\n\t\tPN_SCHEDSTAT(slice_max);\n\t\tPN_SCHEDSTAT(wait_max);\n\t\tPN_SCHEDSTAT(wait_sum);\n\t\tP_SCHEDSTAT(wait_count);\n\t}\n\n\tP(se->load.weight);\n#ifdef CONFIG_SMP\n\tP(se->avg.load_avg);\n\tP(se->avg.util_avg);\n\tP(se->avg.runnable_avg);\n#endif\n\n#undef PN_SCHEDSTAT\n#undef PN\n#undef P_SCHEDSTAT\n#undef P\n}",
        "static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)\n{\n\tu32 cache_size, cache_config;\n\n\tif (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {": "static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)\n{\n\tu32 cache_size, cache_config;\n\n\tif (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {\n\t\t/* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */\n\t\tcache_size = 0x20262024;\n\t\tcache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;\n\t} else {\n\t\t/* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */\n\t\tcache_size = 0x02440243;\n\t\tcache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;\n\t}\n\tcoda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);\n\tif (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {\n\t\tcache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |\n\t\t\t\t16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |\n\t\t\t\t0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;\n\t} else {\n\t\tcache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |\n\t\t\t\t8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |\n\t\t\t\t8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;\n\t}\n\tcoda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);\n}",
        "static int init_tti(struct s2io_nic *nic, int link, bool may_sleep)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tregister u64 val64 = 0;\n\tint i;": "static int init_tti(struct s2io_nic *nic, int link, bool may_sleep)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tregister u64 val64 = 0;\n\tint i;\n\tstruct config_param *config = &nic->config;\n\n\tfor (i = 0; i < config->tx_fifo_num; i++) {\n\t\t/*\n\t\t * TTI Initialization. Default Tx timer gets us about\n\t\t * 250 interrupts per sec. Continuous interrupts are enabled\n\t\t * by default.\n\t\t */\n\t\tif (nic->device_type == XFRAME_II_DEVICE) {\n\t\t\tint count = (nic->config.bus_speed * 125)/2;\n\t\t\tval64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);\n\t\t} else\n\t\t\tval64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);\n\n\t\tval64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |\n\t\t\tTTI_DATA1_MEM_TX_URNG_B(0x10) |\n\t\t\tTTI_DATA1_MEM_TX_URNG_C(0x30) |\n\t\t\tTTI_DATA1_MEM_TX_TIMER_AC_EN;\n\t\tif (i == 0)\n\t\t\tif (use_continuous_tx_intrs && (link == LINK_UP))\n\t\t\t\tval64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;\n\t\twriteq(val64, &bar0->tti_data1_mem);\n\n\t\tif (nic->config.intr_type == MSI_X) {\n\t\t\tval64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |\n\t\t\t\tTTI_DATA2_MEM_TX_UFC_B(0x100) |\n\t\t\t\tTTI_DATA2_MEM_TX_UFC_C(0x200) |\n\t\t\t\tTTI_DATA2_MEM_TX_UFC_D(0x300);\n\t\t} else {\n\t\t\tif ((nic->config.tx_steering_type ==\n\t\t\t     TX_DEFAULT_STEERING) &&\n\t\t\t    (config->tx_fifo_num > 1) &&\n\t\t\t    (i >= nic->udp_fifo_idx) &&\n\t\t\t    (i < (nic->udp_fifo_idx +\n\t\t\t\t  nic->total_udp_fifos)))\n\t\t\t\tval64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |\n\t\t\t\t\tTTI_DATA2_MEM_TX_UFC_B(0x80) |\n\t\t\t\t\tTTI_DATA2_MEM_TX_UFC_C(0x100) |\n\t\t\t\t\tTTI_DATA2_MEM_TX_UFC_D(0x120);\n\t\t\telse\n\t\t\t\tval64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |\n\t\t\t\t\tTTI_DATA2_MEM_TX_UFC_B(0x20) |\n\t\t\t\t\tTTI_DATA2_MEM_TX_UFC_C(0x40) |\n\t\t\t\t\tTTI_DATA2_MEM_TX_UFC_D(0x80);\n\t\t}\n\n\t\twriteq(val64, &bar0->tti_data2_mem);\n\n\t\tval64 = TTI_CMD_MEM_WE |\n\t\t\tTTI_CMD_MEM_STROBE_NEW_CMD |\n\t\t\tTTI_CMD_MEM_OFFSET(i);\n\t\twriteq(val64, &bar0->tti_command_mem);\n\n\t\tif (wait_for_cmd_complete(&bar0->tti_command_mem,\n\t\t\t\t\t  TTI_CMD_MEM_STROBE_NEW_CMD,\n\t\t\t\t\t  S2IO_BIT_RESET, may_sleep) != SUCCESS)\n\t\t\treturn FAILURE;\n\t}\n\n\treturn SUCCESS;\n}",
        "static int mmcr0_exceptionbits(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n": "static int mmcr0_exceptionbits(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\n\t/* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\n\t/* Init the event for the sampling test */\n\tevent_init_sampling(&event, 0x500fa);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop(10000);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/* Verify that pmae is cleared and pmao is set in MMCR0 */\n\tFAIL_IF(get_mmcr0_pmae(get_reg_value(intr_regs, \"MMCR0\"), 5));\n\tFAIL_IF(!get_mmcr0_pmao(get_reg_value(intr_regs, \"MMCR0\"), 5));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static int alloc_try_nid_top_down_narrow_range_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_top_down_narrow_range_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_256;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM() + SZ_512;\n\tmax_addr = min_addr + SMP_CACHE_BYTES;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == max_addr - size);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static int t7xx_dpmaif_dl_bat_init_done(struct dpmaif_hw_info *hw_info, bool frg_en)\n{\n\tu32 value, dl_bat_init = 0;\n\tint ret;\n": "static int t7xx_dpmaif_dl_bat_init_done(struct dpmaif_hw_info *hw_info, bool frg_en)\n{\n\tu32 value, dl_bat_init = 0;\n\tint ret;\n\n\tif (frg_en)\n\t\tdl_bat_init = DPMAIF_DL_BAT_FRG_INIT;\n\n\tdl_bat_init |= DPMAIF_DL_BAT_INIT_ALLSET;\n\tdl_bat_init |= DPMAIF_DL_BAT_INIT_EN;\n\n\tret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT,\n\t\t\t\t\t   value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,\n\t\t\t\t\t   DPMAIF_CHECK_INIT_TIMEOUT_US);\n\tif (ret) {\n\t\tdev_err(hw_info->dev, \"Data plane modem DL BAT is not ready\\n\");\n\t\treturn ret;\n\t}\n\n\tiowrite32(dl_bat_init, hw_info->pcie_base + DPMAIF_DL_BAT_INIT);\n\n\tret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT,\n\t\t\t\t\t   value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,\n\t\t\t\t\t   DPMAIF_CHECK_INIT_TIMEOUT_US);\n\tif (ret)\n\t\tdev_err(hw_info->dev, \"Data plane modem DL BAT initialization failed\\n\");\n\n\treturn ret;\n}",
        "static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)\n{\n\tunsigned long flags;\n\tu32 data, tmp;\n\tint reg_nr = nr / 32;": "static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)\n{\n\tunsigned long flags;\n\tu32 data, tmp;\n\tint reg_nr = nr / 32;\n\tint bit = nr & 0x1f;\n\n\tspin_lock_irqsave(&ichx_priv.lock, flags);\n\n\tif (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)\n\t\tdata = ichx_priv.outlvl_cache[reg_nr];\n\telse\n\t\tdata = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],\n\t\t\t\t ichx_priv.gpio_base);\n\n\tif (val)\n\t\tdata |= BIT(bit);\n\telse\n\t\tdata &= ~BIT(bit);\n\tICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],\n\t\t\t ichx_priv.gpio_base);\n\tif (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)\n\t\tichx_priv.outlvl_cache[reg_nr] = data;\n\n\ttmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],\n\t\t\tichx_priv.gpio_base);\n\n\tspin_unlock_irqrestore(&ichx_priv.lock, flags);\n\n\treturn (verify && data != tmp) ? -EPERM : 0;\n}",
        "static void ww_test_edeadlk_normal(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_normal(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\to2.ctx = &t2;\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\n\to2.ctx = NULL;\n\tmutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);\n\tww_mutex_base_unlock(&o2.base);\n\tWWU(&o);\n\n\tWWL(&o2, &t);\n}",
        "static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)\n{\n\tstatic const u32 test_pat[4][6] = {\n\t{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },\n\t{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },": "static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)\n{\n\tstatic const u32 test_pat[4][6] = {\n\t{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },\n\t{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },\n\t{ 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },\n\t{ 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }\n\t};\n\tint chan;\n\n\tfor (chan = 0; chan < 4; chan++) {\n\t\tint i;\n\n\t\ttg3_writephy(tp, MII_TG3_DSP_ADDRESS,\n\t\t\t     (chan * 0x2000) | 0x0200);\n\t\ttg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);\n\n\t\tfor (i = 0; i < 6; i++)\n\t\t\ttg3_writephy(tp, MII_TG3_DSP_RW_PORT,\n\t\t\t\t     test_pat[chan][i]);\n\n\t\ttg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);\n\t\tif (tg3_wait_macro_done(tp)) {\n\t\t\t*resetp = 1;\n\t\t\treturn -EBUSY;\n\t\t}\n\n\t\ttg3_writephy(tp, MII_TG3_DSP_ADDRESS,\n\t\t\t     (chan * 0x2000) | 0x0200);\n\t\ttg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);\n\t\tif (tg3_wait_macro_done(tp)) {\n\t\t\t*resetp = 1;\n\t\t\treturn -EBUSY;\n\t\t}\n\n\t\ttg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);\n\t\tif (tg3_wait_macro_done(tp)) {\n\t\t\t*resetp = 1;\n\t\t\treturn -EBUSY;\n\t\t}\n\n\t\tfor (i = 0; i < 6; i += 2) {\n\t\t\tu32 low, high;\n\n\t\t\tif (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||\n\t\t\t    tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||\n\t\t\t    tg3_wait_macro_done(tp)) {\n\t\t\t\t*resetp = 1;\n\t\t\t\treturn -EBUSY;\n\t\t\t}\n\t\t\tlow &= 0x7fff;\n\t\t\thigh &= 0x000f;\n\t\t\tif (low != test_pat[chan][i] ||\n\t\t\t    high != test_pat[chan][i+1]) {\n\t\t\t\ttg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);\n\t\t\t\ttg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);\n\t\t\t\ttg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);\n\n\t\t\t\treturn -EBUSY;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static void sun6i_csi_set_window(struct sun6i_csi_dev *sdev)\n{\n\tstruct sun6i_csi_config *config = &sdev->csi.config;\n\tu32 bytesperline_y;\n\tu32 bytesperline_c;": "static void sun6i_csi_set_window(struct sun6i_csi_dev *sdev)\n{\n\tstruct sun6i_csi_config *config = &sdev->csi.config;\n\tu32 bytesperline_y;\n\tu32 bytesperline_c;\n\tint *planar_offset = sdev->planar_offset;\n\tu32 width = config->width;\n\tu32 height = config->height;\n\tu32 hor_len = width;\n\n\tswitch (config->pixelformat) {\n\tcase V4L2_PIX_FMT_YUYV:\n\tcase V4L2_PIX_FMT_YVYU:\n\tcase V4L2_PIX_FMT_UYVY:\n\tcase V4L2_PIX_FMT_VYUY:\n\t\tdev_dbg(sdev->dev,\n\t\t\t\"Horizontal length should be 2 times of width for packed YUV formats!\\n\");\n\t\thor_len = width * 2;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tregmap_write(sdev->regmap, CSI_CH_HSIZE_REG,\n\t\t     CSI_CH_HSIZE_HOR_LEN(hor_len) |\n\t\t     CSI_CH_HSIZE_HOR_START(0));\n\tregmap_write(sdev->regmap, CSI_CH_VSIZE_REG,\n\t\t     CSI_CH_VSIZE_VER_LEN(height) |\n\t\t     CSI_CH_VSIZE_VER_START(0));\n\n\tplanar_offset[0] = 0;\n\tswitch (config->pixelformat) {\n\tcase V4L2_PIX_FMT_NV12_16L16:\n\tcase V4L2_PIX_FMT_NV12:\n\tcase V4L2_PIX_FMT_NV21:\n\tcase V4L2_PIX_FMT_NV16:\n\tcase V4L2_PIX_FMT_NV61:\n\t\tbytesperline_y = width;\n\t\tbytesperline_c = width;\n\t\tplanar_offset[1] = bytesperline_y * height;\n\t\tplanar_offset[2] = -1;\n\t\tbreak;\n\tcase V4L2_PIX_FMT_YUV420:\n\tcase V4L2_PIX_FMT_YVU420:\n\t\tbytesperline_y = width;\n\t\tbytesperline_c = width / 2;\n\t\tplanar_offset[1] = bytesperline_y * height;\n\t\tplanar_offset[2] = planar_offset[1] +\n\t\t\t\tbytesperline_c * height / 2;\n\t\tbreak;\n\tcase V4L2_PIX_FMT_YUV422P:\n\t\tbytesperline_y = width;\n\t\tbytesperline_c = width / 2;\n\t\tplanar_offset[1] = bytesperline_y * height;\n\t\tplanar_offset[2] = planar_offset[1] +\n\t\t\t\tbytesperline_c * height;\n\t\tbreak;\n\tdefault: /* raw */\n\t\tdev_dbg(sdev->dev,\n\t\t\t\"Calculating pixelformat(0x%x)'s bytesperline as a packed format\\n\",\n\t\t\tconfig->pixelformat);\n\t\tbytesperline_y = (sun6i_csi_get_bpp(config->pixelformat) *\n\t\t\t\t  config->width) / 8;\n\t\tbytesperline_c = 0;\n\t\tplanar_offset[1] = -1;\n\t\tplanar_offset[2] = -1;\n\t\tbreak;\n\t}\n\n\tregmap_write(sdev->regmap, CSI_CH_BUF_LEN_REG,\n\t\t     CSI_CH_BUF_LEN_BUF_LEN_C(bytesperline_c) |\n\t\t     CSI_CH_BUF_LEN_BUF_LEN_Y(bytesperline_y));\n}",
        "static void fib_select_default(const struct flowi4 *flp, struct fib_result *res)\n{\n\tstruct fib_info *fi = NULL, *last_resort = NULL;\n\tstruct hlist_head *fa_head = res->fa_head;\n\tstruct fib_table *tb = res->table;": "static void fib_select_default(const struct flowi4 *flp, struct fib_result *res)\n{\n\tstruct fib_info *fi = NULL, *last_resort = NULL;\n\tstruct hlist_head *fa_head = res->fa_head;\n\tstruct fib_table *tb = res->table;\n\tu8 slen = 32 - res->prefixlen;\n\tint order = -1, last_idx = -1;\n\tstruct fib_alias *fa, *fa1 = NULL;\n\tu32 last_prio = res->fi->fib_priority;\n\tdscp_t last_dscp = 0;\n\n\thlist_for_each_entry_rcu(fa, fa_head, fa_list) {\n\t\tstruct fib_info *next_fi = fa->fa_info;\n\t\tstruct fib_nh_common *nhc;\n\n\t\tif (fa->fa_slen != slen)\n\t\t\tcontinue;\n\t\tif (fa->fa_dscp &&\n\t\t    fa->fa_dscp != inet_dsfield_to_dscp(flp->flowi4_tos))\n\t\t\tcontinue;\n\t\tif (fa->tb_id != tb->tb_id)\n\t\t\tcontinue;\n\t\tif (next_fi->fib_priority > last_prio &&\n\t\t    fa->fa_dscp == last_dscp) {\n\t\t\tif (last_dscp)\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\t\t}\n\t\tif (next_fi->fib_flags & RTNH_F_DEAD)\n\t\t\tcontinue;\n\t\tlast_dscp = fa->fa_dscp;\n\t\tlast_prio = next_fi->fib_priority;\n\n\t\tif (next_fi->fib_scope != res->scope ||\n\t\t    fa->fa_type != RTN_UNICAST)\n\t\t\tcontinue;\n\n\t\tnhc = fib_info_nhc(next_fi, 0);\n\t\tif (!nhc->nhc_gw_family || nhc->nhc_scope != RT_SCOPE_LINK)\n\t\t\tcontinue;\n\n\t\tfib_alias_accessed(fa);\n\n\t\tif (!fi) {\n\t\t\tif (next_fi != res->fi)\n\t\t\t\tbreak;\n\t\t\tfa1 = fa;\n\t\t} else if (!fib_detect_death(fi, order, &last_resort,\n\t\t\t\t\t     &last_idx, fa1->fa_default)) {\n\t\t\tfib_result_assign(res, fi);\n\t\t\tfa1->fa_default = order;\n\t\t\tgoto out;\n\t\t}\n\t\tfi = next_fi;\n\t\torder++;\n\t}\n\n\tif (order <= 0 || !fi) {\n\t\tif (fa1)\n\t\t\tfa1->fa_default = -1;\n\t\tgoto out;\n\t}\n\n\tif (!fib_detect_death(fi, order, &last_resort, &last_idx,\n\t\t\t      fa1->fa_default)) {\n\t\tfib_result_assign(res, fi);\n\t\tfa1->fa_default = order;\n\t\tgoto out;\n\t}\n\n\tif (last_idx >= 0)\n\t\tfib_result_assign(res, last_resort);\n\tfa1->fa_default = last_idx;\nout:\n\treturn;\n}",
        "static void __raid10_find_phys(struct geom *geo, struct r10bio *r10bio)\n{\n\tint n,f;\n\tsector_t sector;\n\tsector_t chunk;": "static void __raid10_find_phys(struct geom *geo, struct r10bio *r10bio)\n{\n\tint n,f;\n\tsector_t sector;\n\tsector_t chunk;\n\tsector_t stripe;\n\tint dev;\n\tint slot = 0;\n\tint last_far_set_start, last_far_set_size;\n\n\tlast_far_set_start = (geo->raid_disks / geo->far_set_size) - 1;\n\tlast_far_set_start *= geo->far_set_size;\n\n\tlast_far_set_size = geo->far_set_size;\n\tlast_far_set_size += (geo->raid_disks % geo->far_set_size);\n\n\t/* now calculate first sector/dev */\n\tchunk = r10bio->sector >> geo->chunk_shift;\n\tsector = r10bio->sector & geo->chunk_mask;\n\n\tchunk *= geo->near_copies;\n\tstripe = chunk;\n\tdev = sector_div(stripe, geo->raid_disks);\n\tif (geo->far_offset)\n\t\tstripe *= geo->far_copies;\n\n\tsector += stripe << geo->chunk_shift;\n\n\t/* and calculate all the others */\n\tfor (n = 0; n < geo->near_copies; n++) {\n\t\tint d = dev;\n\t\tint set;\n\t\tsector_t s = sector;\n\t\tr10bio->devs[slot].devnum = d;\n\t\tr10bio->devs[slot].addr = s;\n\t\tslot++;\n\n\t\tfor (f = 1; f < geo->far_copies; f++) {\n\t\t\tset = d / geo->far_set_size;\n\t\t\td += geo->near_copies;\n\n\t\t\tif ((geo->raid_disks % geo->far_set_size) &&\n\t\t\t    (d > last_far_set_start)) {\n\t\t\t\td -= last_far_set_start;\n\t\t\t\td %= last_far_set_size;\n\t\t\t\td += last_far_set_start;\n\t\t\t} else {\n\t\t\t\td %= geo->far_set_size;\n\t\t\t\td += geo->far_set_size * set;\n\t\t\t}\n\t\t\ts += geo->stride;\n\t\t\tr10bio->devs[slot].devnum = d;\n\t\t\tr10bio->devs[slot].addr = s;\n\t\t\tslot++;\n\t\t}\n\t\tdev++;\n\t\tif (dev >= geo->raid_disks) {\n\t\t\tdev = 0;\n\t\t\tsector += (geo->chunk_mask + 1);\n\t\t}\n\t}\n}",
        "static int __t7xx_pci_pm_resume(struct pci_dev *pdev, bool state_check)\n{\n\tstruct t7xx_pci_dev *t7xx_dev;\n\tstruct md_pm_entity *entity;\n\tu32 prev_state;": "static int __t7xx_pci_pm_resume(struct pci_dev *pdev, bool state_check)\n{\n\tstruct t7xx_pci_dev *t7xx_dev;\n\tstruct md_pm_entity *entity;\n\tu32 prev_state;\n\tint ret = 0;\n\n\tt7xx_dev = pci_get_drvdata(pdev);\n\tif (atomic_read(&t7xx_dev->md_pm_state) <= MTK_PM_INIT) {\n\t\tiowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);\n\t\treturn 0;\n\t}\n\n\tt7xx_pcie_mac_interrupts_en(t7xx_dev);\n\tprev_state = ioread32(IREG_BASE(t7xx_dev) + T7XX_PCIE_PM_RESUME_STATE);\n\n\tif (state_check) {\n\t\t/* For D3/L3 resume, the device could boot so quickly that the\n\t\t * initial value of the dummy register might be overwritten.\n\t\t * Identify new boots if the ATR source address register is not initialized.\n\t\t */\n\t\tu32 atr_reg_val = ioread32(IREG_BASE(t7xx_dev) +\n\t\t\t\t\t   ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR);\n\t\tif (prev_state == PM_RESUME_REG_STATE_L3 ||\n\t\t    (prev_state == PM_RESUME_REG_STATE_INIT &&\n\t\t     atr_reg_val == ATR_SRC_ADDR_INVALID)) {\n\t\t\tret = t7xx_send_fsm_command(t7xx_dev, FSM_CMD_STOP);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\tret = t7xx_pcie_reinit(t7xx_dev, true);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\tt7xx_clear_rgu_irq(t7xx_dev);\n\t\t\treturn t7xx_send_fsm_command(t7xx_dev, FSM_CMD_START);\n\t\t}\n\n\t\tif (prev_state == PM_RESUME_REG_STATE_EXP ||\n\t\t    prev_state == PM_RESUME_REG_STATE_L2_EXP) {\n\t\t\tif (prev_state == PM_RESUME_REG_STATE_L2_EXP) {\n\t\t\t\tret = t7xx_pcie_reinit(t7xx_dev, false);\n\t\t\t\tif (ret)\n\t\t\t\t\treturn ret;\n\t\t\t}\n\n\t\t\tatomic_set(&t7xx_dev->md_pm_state, MTK_PM_SUSPENDED);\n\t\t\tt7xx_dev->rgu_pci_irq_en = true;\n\t\t\tt7xx_pcie_mac_set_int(t7xx_dev, SAP_RGU_INT);\n\n\t\t\tt7xx_mhccif_mask_clr(t7xx_dev,\n\t\t\t\t\t     D2H_INT_EXCEPTION_INIT |\n\t\t\t\t\t     D2H_INT_EXCEPTION_INIT_DONE |\n\t\t\t\t\t     D2H_INT_EXCEPTION_CLEARQ_DONE |\n\t\t\t\t\t     D2H_INT_EXCEPTION_ALLQ_RESET |\n\t\t\t\t\t     D2H_INT_PORT_ENUM);\n\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (prev_state == PM_RESUME_REG_STATE_L2) {\n\t\t\tret = t7xx_pcie_reinit(t7xx_dev, false);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t} else if (prev_state != PM_RESUME_REG_STATE_L1 &&\n\t\t\t   prev_state != PM_RESUME_REG_STATE_INIT) {\n\t\t\tret = t7xx_send_fsm_command(t7xx_dev, FSM_CMD_STOP);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\tt7xx_clear_rgu_irq(t7xx_dev);\n\t\t\tatomic_set(&t7xx_dev->md_pm_state, MTK_PM_SUSPENDED);\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tiowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);\n\tt7xx_wait_pm_config(t7xx_dev);\n\n\tlist_for_each_entry(entity, &t7xx_dev->md_pm_entities, entity) {\n\t\tif (entity->resume_early)\n\t\t\tentity->resume_early(t7xx_dev, entity->entity_param);\n\t}\n\n\tret = t7xx_send_pm_request(t7xx_dev, H2D_CH_RESUME_REQ);\n\tif (ret)\n\t\tdev_err(&pdev->dev, \"[PM] MD resume error: %d\\n\", ret);\n\n\tret = t7xx_send_pm_request(t7xx_dev, H2D_CH_RESUME_REQ_AP);\n\tif (ret)\n\t\tdev_err(&pdev->dev, \"[PM] SAP resume error: %d\\n\", ret);\n\n\tlist_for_each_entry(entity, &t7xx_dev->md_pm_entities, entity) {\n\t\tif (entity->resume) {\n\t\t\tret = entity->resume(t7xx_dev, entity->entity_param);\n\t\t\tif (ret)\n\t\t\t\tdev_err(&pdev->dev, \"[PM] Resume entry ID: %d error: %d\\n\",\n\t\t\t\t\tentity->id, ret);\n\t\t}\n\t}\n\n\tt7xx_dev->rgu_pci_irq_en = true;\n\tt7xx_pcie_mac_set_int(t7xx_dev, SAP_RGU_INT);\n\tiowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);\n\tpm_runtime_mark_last_busy(&pdev->dev);\n\tatomic_set(&t7xx_dev->md_pm_state, MTK_PM_RESUMED);\n\n\treturn ret;\n}",
        "static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)\n{\n\tu32 bchdsr0 = ecc_sta[0];\n\tu32 bchdsr1 = ecc_sta[1];\n\tu32 bchdsr2 = ecc_sta[2];": "static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)\n{\n\tu32 bchdsr0 = ecc_sta[0];\n\tu32 bchdsr1 = ecc_sta[1];\n\tu32 bchdsr2 = ecc_sta[2];\n\tu32 bchdsr3 = ecc_sta[3];\n\tu32 bchdsr4 = ecc_sta[4];\n\tu16 pos[8];\n\tint i, den;\n\tunsigned int nb_errs = 0;\n\n\t/* No errors found */\n\tif (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))\n\t\treturn 0;\n\n\t/* Too many errors detected */\n\tif (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))\n\t\treturn -EBADMSG;\n\n\tpos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);\n\tpos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);\n\tpos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);\n\tpos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);\n\tpos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);\n\tpos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);\n\tpos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);\n\tpos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);\n\n\tden = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);\n\tfor (i = 0; i < den; i++) {\n\t\tif (pos[i] < eccsize * 8) {\n\t\t\tchange_bit(pos[i], (unsigned long *)dat);\n\t\t\tnb_errs++;\n\t\t}\n\t}\n\n\treturn nb_errs;\n}",
        "static int dspi_setup(struct spi_device *spi)\n{\n\tstruct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);\n\tunsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;\n\tu32 cs_sck_delay = 0, sck_cs_delay = 0;": "static int dspi_setup(struct spi_device *spi)\n{\n\tstruct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);\n\tunsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;\n\tu32 cs_sck_delay = 0, sck_cs_delay = 0;\n\tstruct fsl_dspi_platform_data *pdata;\n\tunsigned char pasc = 0, asc = 0;\n\tstruct chip_data *chip;\n\tunsigned long clkrate;\n\n\t/* Only alloc on first setup */\n\tchip = spi_get_ctldata(spi);\n\tif (chip == NULL) {\n\t\tchip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\n\t\tif (!chip)\n\t\t\treturn -ENOMEM;\n\t}\n\n\tpdata = dev_get_platdata(&dspi->pdev->dev);\n\n\tif (!pdata) {\n\t\tof_property_read_u32(spi->dev.of_node, \"fsl,spi-cs-sck-delay\",\n\t\t\t\t     &cs_sck_delay);\n\n\t\tof_property_read_u32(spi->dev.of_node, \"fsl,spi-sck-cs-delay\",\n\t\t\t\t     &sck_cs_delay);\n\t} else {\n\t\tcs_sck_delay = pdata->cs_sck_delay;\n\t\tsck_cs_delay = pdata->sck_cs_delay;\n\t}\n\n\tclkrate = clk_get_rate(dspi->clk);\n\thz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);\n\n\t/* Set PCS to SCK delay scale values */\n\tns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);\n\n\t/* Set After SCK delay scale values */\n\tns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);\n\n\tchip->ctar_val = 0;\n\tif (spi->mode & SPI_CPOL)\n\t\tchip->ctar_val |= SPI_CTAR_CPOL;\n\tif (spi->mode & SPI_CPHA)\n\t\tchip->ctar_val |= SPI_CTAR_CPHA;\n\n\tif (!spi_controller_is_slave(dspi->ctlr)) {\n\t\tchip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |\n\t\t\t\t  SPI_CTAR_CSSCK(cssck) |\n\t\t\t\t  SPI_CTAR_PASC(pasc) |\n\t\t\t\t  SPI_CTAR_ASC(asc) |\n\t\t\t\t  SPI_CTAR_PBR(pbr) |\n\t\t\t\t  SPI_CTAR_BR(br);\n\n\t\tif (spi->mode & SPI_LSB_FIRST)\n\t\t\tchip->ctar_val |= SPI_CTAR_LSBFE;\n\t}\n\n\tspi_set_ctldata(spi, chip);\n\n\treturn 0;\n}",
        "static int ice_ptp_init_phc_e822(struct ice_hw *hw)\n{\n\tint err;\n\tu32 regval;\n": "static int ice_ptp_init_phc_e822(struct ice_hw *hw)\n{\n\tint err;\n\tu32 regval;\n\n\t/* Enable reading switch and PHY registers over the sideband queue */\n#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)\n#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)\n\tregval = rd32(hw, PF_SB_REM_DEV_CTL);\n\tregval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |\n\t\t   PF_SB_REM_DEV_CTL_PHY0);\n\twr32(hw, PF_SB_REM_DEV_CTL, regval);\n\n\t/* Initialize the Clock Generation Unit */\n\terr = ice_init_cgu_e822(hw);\n\tif (err)\n\t\treturn err;\n\n\t/* Set window length for all the ports */\n\treturn ice_ptp_set_vernier_wl(hw);\n}",
        "static void bnx2x_ets_bw_limit_common(const struct link_params *params)\n{\n\t/* ETS disabled configuration */\n\tstruct bnx2x *bp = params->bp;\n\tDP(NETIF_MSG_LINK, \"ETS enabled BW limit configuration\\n\");": "static void bnx2x_ets_bw_limit_common(const struct link_params *params)\n{\n\t/* ETS disabled configuration */\n\tstruct bnx2x *bp = params->bp;\n\tDP(NETIF_MSG_LINK, \"ETS enabled BW limit configuration\\n\");\n\t/* Defines which entries (clients) are subjected to WFQ arbitration\n\t * COS0 0x8\n\t * COS1 0x10\n\t */\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);\n\t/* Mapping between the ARB_CREDIT_WEIGHT registers and actual\n\t * client numbers (WEIGHT_0 does not actually have to represent\n\t * client 0)\n\t *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0\n\t *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010\n\t */\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);\n\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,\n\t       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,\n\t       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n\n\t/* ETS mode enabled*/\n\tREG_WR(bp, PBF_REG_ETS_ENABLED, 1);\n\n\t/* Defines the number of consecutive slots for the strict priority */\n\tREG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);\n\t/* Bitmap of 5bits length. Each bit specifies whether the entry behaves\n\t * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0\n\t * entry, 4 - COS1 entry.\n\t * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT\n\t * bit4   bit3\t  bit2     bit1\t   bit0\n\t * MCP and debug are strict\n\t */\n\tREG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);\n\n\t/* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/\n\tREG_WR(bp, PBF_REG_COS0_UPPER_BOUND,\n\t       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n\tREG_WR(bp, PBF_REG_COS1_UPPER_BOUND,\n\t       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);\n}",
        "static int fan_get_speed(unsigned int *speed)\n{\n\tu8 hi, lo;\n\n\tswitch (fan_status_access_mode) {": "static int fan_get_speed(unsigned int *speed)\n{\n\tu8 hi, lo;\n\n\tswitch (fan_status_access_mode) {\n\tcase TPACPI_FAN_RD_TPEC:\n\t\t/* all except 570, 600e/x, 770e, 770x */\n\t\tif (unlikely(!fan_select_fan1()))\n\t\t\treturn -EIO;\n\t\tif (unlikely(!acpi_ec_read(fan_rpm_offset, &lo) ||\n\t\t\t     !acpi_ec_read(fan_rpm_offset + 1, &hi)))\n\t\t\treturn -EIO;\n\n\t\tif (likely(speed))\n\t\t\t*speed = (hi << 8) | lo;\n\n\t\tbreak;\n\n\tdefault:\n\t\treturn -ENXIO;\n\t}\n\n\treturn 0;\n}",
        "static void smc_conn_kill(struct smc_connection *conn, bool soft)\n{\n\tstruct smc_sock *smc = container_of(conn, struct smc_sock, conn);\n\n\tif (conn->lgr->is_smcd && conn->lgr->peer_shutdown)": "static void smc_conn_kill(struct smc_connection *conn, bool soft)\n{\n\tstruct smc_sock *smc = container_of(conn, struct smc_sock, conn);\n\n\tif (conn->lgr->is_smcd && conn->lgr->peer_shutdown)\n\t\tconn->local_tx_ctrl.conn_state_flags.peer_conn_abort = 1;\n\telse\n\t\tsmc_close_abort(conn);\n\tconn->killed = 1;\n\tsmc->sk.sk_err = ECONNABORTED;\n\tsmc_sk_wake_ups(smc);\n\tif (conn->lgr->is_smcd) {\n\t\tsmc_ism_unset_conn(conn);\n\t\tif (soft)\n\t\t\ttasklet_kill(&conn->rx_tsklet);\n\t\telse\n\t\t\ttasklet_unlock_wait(&conn->rx_tsklet);\n\t} else {\n\t\tsmc_cdc_wait_pend_tx_wr(conn);\n\t}\n\tsmc_lgr_unregister_conn(conn);\n\tsmc_close_active_abort(smc);\n}",
        "static void test_tc_redirect_neigh(struct netns_setup_result *setup_result)\n{\n\tstruct nstoken *nstoken = NULL;\n\tstruct test_tc_neigh *skel = NULL;\n\tint err;": "static void test_tc_redirect_neigh(struct netns_setup_result *setup_result)\n{\n\tstruct nstoken *nstoken = NULL;\n\tstruct test_tc_neigh *skel = NULL;\n\tint err;\n\n\tnstoken = open_netns(NS_FWD);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns fwd\"))\n\t\treturn;\n\n\tskel = test_tc_neigh__open();\n\tif (!ASSERT_OK_PTR(skel, \"test_tc_neigh__open\"))\n\t\tgoto done;\n\n\tskel->rodata->IFINDEX_SRC = setup_result->ifindex_veth_src_fwd;\n\tskel->rodata->IFINDEX_DST = setup_result->ifindex_veth_dst_fwd;\n\n\terr = test_tc_neigh__load(skel);\n\tif (!ASSERT_OK(err, \"test_tc_neigh__load\"))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_src, SRC_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" SRC_PROG_PIN_FILE))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_chk, CHK_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" CHK_PROG_PIN_FILE))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_dst, DST_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" DST_PROG_PIN_FILE))\n\t\tgoto done;\n\n\tif (netns_load_bpf())\n\t\tgoto done;\n\n\tif (!ASSERT_OK(set_forwarding(false), \"disable forwarding\"))\n\t\tgoto done;\n\n\ttest_connectivity();\n\ndone:\n\tif (skel)\n\t\ttest_tc_neigh__destroy(skel);\n\tclose_netns(nstoken);\n}",
        "static int set_iqm_af(struct drx_demod_instance *demod, bool active)\n{\n\tu16 data = 0;\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;": "static int set_iqm_af(struct drx_demod_instance *demod, bool active)\n{\n\tu16 data = 0;\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\n\t/* Configure IQM */\n\trc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif (!active)\n\t\tdata &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));\n\telse\n\t\tdata |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);\n\trc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int hw_atl_b0_adj_clock_freq(struct aq_hw_s *self, s32 ppb)\n{\n\tstruct hw_fw_request_iface fwreq;\n\tsize_t size;\n": "static int hw_atl_b0_adj_clock_freq(struct aq_hw_s *self, s32 ppb)\n{\n\tstruct hw_fw_request_iface fwreq;\n\tsize_t size;\n\n\tmemset(&fwreq, 0, sizeof(fwreq));\n\n\tfwreq.msg_id = HW_AQ_FW_REQUEST_PTP_ADJ_FREQ;\n\thw_atl_b0_adj_params_get(AQ_HW_MAC_COUNTER_HZ, ppb,\n\t\t\t\t &fwreq.ptp_adj_freq.ns_mac,\n\t\t\t\t &fwreq.ptp_adj_freq.fns_mac);\n\thw_atl_b0_adj_params_get(AQ_HW_PHY_COUNTER_HZ, ppb,\n\t\t\t\t &fwreq.ptp_adj_freq.ns_phy,\n\t\t\t\t &fwreq.ptp_adj_freq.fns_phy);\n\thw_atl_b0_mac_adj_param_calc(&fwreq.ptp_adj_freq,\n\t\t\t\t     AQ_HW_PHY_COUNTER_HZ,\n\t\t\t\t     AQ_HW_MAC_COUNTER_HZ);\n\n\tsize = sizeof(fwreq.msg_id) + sizeof(fwreq.ptp_adj_freq);\n\treturn self->aq_fw_ops->send_fw_request(self, &fwreq, size);\n}",
        "static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n{\n\tstruct gdma_context *gc;\n\tvoid __iomem *bar0_va;\n\tint bar = 0;": "static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n{\n\tstruct gdma_context *gc;\n\tvoid __iomem *bar0_va;\n\tint bar = 0;\n\tint err;\n\n\t/* Each port has 2 CQs, each CQ has at most 1 EQE at a time */\n\tBUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE);\n\n\terr = pci_enable_device(pdev);\n\tif (err)\n\t\treturn -ENXIO;\n\n\tpci_set_master(pdev);\n\n\terr = pci_request_regions(pdev, \"mana\");\n\tif (err)\n\t\tgoto disable_dev;\n\n\terr = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));\n\tif (err)\n\t\tgoto release_region;\n\n\terr = -ENOMEM;\n\tgc = vzalloc(sizeof(*gc));\n\tif (!gc)\n\t\tgoto release_region;\n\n\tmutex_init(&gc->eq_test_event_mutex);\n\tpci_set_drvdata(pdev, gc);\n\n\tbar0_va = pci_iomap(pdev, bar, 0);\n\tif (!bar0_va)\n\t\tgoto free_gc;\n\n\tgc->bar0_va = bar0_va;\n\tgc->dev = &pdev->dev;\n\n\n\terr = mana_gd_setup(pdev);\n\tif (err)\n\t\tgoto unmap_bar;\n\n\terr = mana_probe(&gc->mana, false);\n\tif (err)\n\t\tgoto cleanup_gd;\n\n\treturn 0;\n\ncleanup_gd:\n\tmana_gd_cleanup(pdev);\nunmap_bar:\n\tpci_iounmap(pdev, bar0_va);\nfree_gc:\n\tpci_set_drvdata(pdev, NULL);\n\tvfree(gc);\nrelease_region:\n\tpci_release_regions(pdev);\ndisable_dev:\n\tpci_clear_master(pdev);\n\tpci_disable_device(pdev);\n\tdev_err(&pdev->dev, \"gdma probe failed: err = %d\\n\", err);\n\treturn err;\n}",
        "static int timer_mim(struct timer_mim *timer_skel)\n{\n\t__u64 cnt1, cnt2;\n\tint err, prog_fd, key1 = 1;\n\tLIBBPF_OPTS(bpf_test_run_opts, topts);": "static int timer_mim(struct timer_mim *timer_skel)\n{\n\t__u64 cnt1, cnt2;\n\tint err, prog_fd, key1 = 1;\n\tLIBBPF_OPTS(bpf_test_run_opts, topts);\n\n\terr = timer_mim__attach(timer_skel);\n\tif (!ASSERT_OK(err, \"timer_attach\"))\n\t\treturn err;\n\n\tprog_fd = bpf_program__fd(timer_skel->progs.test1);\n\terr = bpf_prog_test_run_opts(prog_fd, &topts);\n\tASSERT_OK(err, \"test_run\");\n\tASSERT_EQ(topts.retval, 0, \"test_run\");\n\ttimer_mim__detach(timer_skel);\n\n\t/* check that timer_cb[12] are incrementing 'cnt' */\n\tcnt1 = READ_ONCE(timer_skel->bss->cnt);\n\tfor (int i = 0; i < 100; i++) {\n\t\tcnt2 = READ_ONCE(timer_skel->bss->cnt);\n\t\tif (cnt2 != cnt1)\n\t\t\tbreak;\n\t\tusleep(200); /* 100 times more than interval */\n\t}\n\tASSERT_GT(cnt2, cnt1, \"cnt\");\n\n\tASSERT_EQ(timer_skel->bss->err, 0, \"err\");\n\t/* check that code paths completed */\n\tASSERT_EQ(timer_skel->bss->ok, 1 | 2, \"ok\");\n\n\tclose(bpf_map__fd(timer_skel->maps.inner_htab));\n\terr = bpf_map__delete_elem(timer_skel->maps.outer_arr, &key1, sizeof(key1), 0);\n\tASSERT_EQ(err, 0, \"delete inner map\");\n\n\t/* check that timer_cb[12] are no longer running */\n\tcnt1 = READ_ONCE(timer_skel->bss->cnt);\n\tfor (int i = 0; i < 100; i++) {\n\t\tusleep(200); /* 100 times more than interval */\n\t\tcnt2 = READ_ONCE(timer_skel->bss->cnt);\n\t\tif (cnt2 == cnt1)\n\t\t\tbreak;\n\t}\n\tASSERT_EQ(cnt2, cnt1, \"cnt\");\n\n\treturn 0;\n}",
        "static int i40e_vc_del_cloud_filter(struct i40e_vf *vf, u8 *msg)\n{\n\tstruct virtchnl_filter *vcf = (struct virtchnl_filter *)msg;\n\tstruct virtchnl_l4_spec mask = vcf->mask.tcp_spec;\n\tstruct virtchnl_l4_spec tcf = vcf->data.tcp_spec;": "static int i40e_vc_del_cloud_filter(struct i40e_vf *vf, u8 *msg)\n{\n\tstruct virtchnl_filter *vcf = (struct virtchnl_filter *)msg;\n\tstruct virtchnl_l4_spec mask = vcf->mask.tcp_spec;\n\tstruct virtchnl_l4_spec tcf = vcf->data.tcp_spec;\n\tstruct i40e_cloud_filter cfilter, *cf = NULL;\n\tstruct i40e_pf *pf = vf->pf;\n\tstruct i40e_vsi *vsi = NULL;\n\tstruct hlist_node *node;\n\ti40e_status aq_ret = 0;\n\tint i, ret;\n\n\tif (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {\n\t\taq_ret = I40E_ERR_PARAM;\n\t\tgoto err;\n\t}\n\n\tif (!vf->adq_enabled) {\n\t\tdev_info(&pf->pdev->dev,\n\t\t\t \"VF %d: ADq not enabled, can't apply cloud filter\\n\",\n\t\t\t vf->vf_id);\n\t\taq_ret = I40E_ERR_PARAM;\n\t\tgoto err;\n\t}\n\n\tif (i40e_validate_cloud_filter(vf, vcf)) {\n\t\tdev_info(&pf->pdev->dev,\n\t\t\t \"VF %d: Invalid input, can't apply cloud filter\\n\",\n\t\t\t vf->vf_id);\n\t\taq_ret = I40E_ERR_PARAM;\n\t\tgoto err;\n\t}\n\n\tmemset(&cfilter, 0, sizeof(cfilter));\n\t/* parse destination mac address */\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\tcfilter.dst_mac[i] = mask.dst_mac[i] & tcf.dst_mac[i];\n\n\t/* parse source mac address */\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\tcfilter.src_mac[i] = mask.src_mac[i] & tcf.src_mac[i];\n\n\tcfilter.vlan_id = mask.vlan_id & tcf.vlan_id;\n\tcfilter.dst_port = mask.dst_port & tcf.dst_port;\n\tcfilter.src_port = mask.src_port & tcf.src_port;\n\n\tswitch (vcf->flow_type) {\n\tcase VIRTCHNL_TCP_V4_FLOW:\n\t\tcfilter.n_proto = ETH_P_IP;\n\t\tif (mask.dst_ip[0] & tcf.dst_ip[0])\n\t\t\tmemcpy(&cfilter.ip.v4.dst_ip, tcf.dst_ip,\n\t\t\t       ARRAY_SIZE(tcf.dst_ip));\n\t\telse if (mask.src_ip[0] & tcf.dst_ip[0])\n\t\t\tmemcpy(&cfilter.ip.v4.src_ip, tcf.src_ip,\n\t\t\t       ARRAY_SIZE(tcf.dst_ip));\n\t\tbreak;\n\tcase VIRTCHNL_TCP_V6_FLOW:\n\t\tcfilter.n_proto = ETH_P_IPV6;\n\t\tif (mask.dst_ip[3] & tcf.dst_ip[3])\n\t\t\tmemcpy(&cfilter.ip.v6.dst_ip6, tcf.dst_ip,\n\t\t\t       sizeof(cfilter.ip.v6.dst_ip6));\n\t\tif (mask.src_ip[3] & tcf.src_ip[3])\n\t\t\tmemcpy(&cfilter.ip.v6.src_ip6, tcf.src_ip,\n\t\t\t       sizeof(cfilter.ip.v6.src_ip6));\n\t\tbreak;\n\tdefault:\n\t\t/* TC filter can be configured based on different combinations\n\t\t * and in this case IP is not a part of filter config\n\t\t */\n\t\tdev_info(&pf->pdev->dev, \"VF %d: Flow type not configured\\n\",\n\t\t\t vf->vf_id);\n\t}\n\n\t/* get the vsi to which the tc belongs to */\n\tvsi = pf->vsi[vf->ch[vcf->action_meta].vsi_idx];\n\tcfilter.seid = vsi->seid;\n\tcfilter.flags = vcf->field_flags;\n\n\t/* Deleting TC filter */\n\tif (tcf.dst_port)\n\t\tret = i40e_add_del_cloud_filter_big_buf(vsi, &cfilter, false);\n\telse\n\t\tret = i40e_add_del_cloud_filter(vsi, &cfilter, false);\n\tif (ret) {\n\t\tdev_err(&pf->pdev->dev,\n\t\t\t\"VF %d: Failed to delete cloud filter, err %s aq_err %s\\n\",\n\t\t\tvf->vf_id, i40e_stat_str(&pf->hw, ret),\n\t\t\ti40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));\n\t\tgoto err;\n\t}\n\n\thlist_for_each_entry_safe(cf, node,\n\t\t\t\t  &vf->cloud_filter_list, cloud_node) {\n\t\tif (cf->seid != cfilter.seid)\n\t\t\tcontinue;\n\t\tif (mask.dst_port)\n\t\t\tif (cfilter.dst_port != cf->dst_port)\n\t\t\t\tcontinue;\n\t\tif (mask.dst_mac[0])\n\t\t\tif (!ether_addr_equal(cf->src_mac, cfilter.src_mac))\n\t\t\t\tcontinue;\n\t\t/* for ipv4 data to be valid, only first byte of mask is set */\n\t\tif (cfilter.n_proto == ETH_P_IP && mask.dst_ip[0])\n\t\t\tif (memcmp(&cfilter.ip.v4.dst_ip, &cf->ip.v4.dst_ip,\n\t\t\t\t   ARRAY_SIZE(tcf.dst_ip)))\n\t\t\t\tcontinue;\n\t\t/* for ipv6, mask is set for all sixteen bytes (4 words) */\n\t\tif (cfilter.n_proto == ETH_P_IPV6 && mask.dst_ip[3])\n\t\t\tif (memcmp(&cfilter.ip.v6.dst_ip6, &cf->ip.v6.dst_ip6,\n\t\t\t\t   sizeof(cfilter.ip.v6.src_ip6)))\n\t\t\t\tcontinue;\n\t\tif (mask.vlan_id)\n\t\t\tif (cfilter.vlan_id != cf->vlan_id)\n\t\t\t\tcontinue;\n\n\t\thlist_del(&cf->cloud_node);\n\t\tkfree(cf);\n\t\tvf->num_cloud_filters--;\n\t}\n\nerr:\n\treturn i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DEL_CLOUD_FILTER,\n\t\t\t\t       aq_ret);\n}",
        "static void hpre_curve25519_cb(struct hpre_ctx *ctx, void *resp)\n{\n\tstruct hpre_dfx *dfx = ctx->hpre->debug.dfx;\n\tstruct hpre_asym_request *req = NULL;\n\tstruct kpp_request *areq;": "static void hpre_curve25519_cb(struct hpre_ctx *ctx, void *resp)\n{\n\tstruct hpre_dfx *dfx = ctx->hpre->debug.dfx;\n\tstruct hpre_asym_request *req = NULL;\n\tstruct kpp_request *areq;\n\tu64 overtime_thrhld;\n\tint ret;\n\n\tret = hpre_alg_res_post_hf(ctx, resp, (void **)&req);\n\tareq = req->areq.curve25519;\n\tareq->dst_len = ctx->key_sz;\n\n\tovertime_thrhld = atomic64_read(&dfx[HPRE_OVERTIME_THRHLD].value);\n\tif (overtime_thrhld && hpre_is_bd_timeout(req, overtime_thrhld))\n\t\tatomic64_inc(&dfx[HPRE_OVER_THRHLD_CNT].value);\n\n\thpre_key_to_big_end(sg_virt(areq->dst), CURVE25519_KEY_SIZE);\n\n\thpre_curve25519_hw_data_clr_all(ctx, req, areq->dst, areq->src);\n\tkpp_request_complete(areq, ret);\n\n\tatomic64_inc(&dfx[HPRE_RECV_CNT].value);\n}",
        "static int flash_erase (struct mtd_info *mtd,struct erase_info *instr)\n{\n   __u32 addr,len;\n   int i,first;\n": "static int flash_erase (struct mtd_info *mtd,struct erase_info *instr)\n{\n   __u32 addr,len;\n   int i,first;\n\n#ifdef LART_DEBUG\n   printk (KERN_DEBUG \"%s(addr = 0x%.8x, len = %d)\\n\", __func__, instr->addr, instr->len);\n#endif\n\n   /*\n\t* check that both start and end of the requested erase are\n\t* aligned with the erasesize at the appropriate addresses.\n\t*\n\t* skip all erase regions which are ended before the start of\n\t* the requested erase. Actually, to save on the calculations,\n\t* we skip to the first erase region which starts after the\n\t* start of the requested erase, and then go back one.\n\t*/\n   for (i = 0; i < mtd->numeraseregions && instr->addr >= mtd->eraseregions[i].offset; i++) ;\n   i--;\n\n   /*\n\t* ok, now i is pointing at the erase region in which this\n\t* erase request starts. Check the start of the requested\n\t* erase range is aligned with the erase size which is in\n\t* effect here.\n\t*/\n   if (i < 0 || (instr->addr & (mtd->eraseregions[i].erasesize - 1)))\n      return -EINVAL;\n\n   /* Remember the erase region we start on */\n   first = i;\n\n   /*\n\t* next, check that the end of the requested erase is aligned\n\t* with the erase region at that address.\n\t*\n\t* as before, drop back one to point at the region in which\n\t* the address actually falls\n\t*/\n   for (; i < mtd->numeraseregions && instr->addr + instr->len >= mtd->eraseregions[i].offset; i++) ;\n   i--;\n\n   /* is the end aligned on a block boundary? */\n   if (i < 0 || ((instr->addr + instr->len) & (mtd->eraseregions[i].erasesize - 1)))\n      return -EINVAL;\n\n   addr = instr->addr;\n   len = instr->len;\n\n   i = first;\n\n   /* now erase those blocks */\n   while (len)\n\t {\n\t\tif (!erase_block (addr))\n\t\t\t return (-EIO);\n\n\t\taddr += mtd->eraseregions[i].erasesize;\n\t\tlen -= mtd->eraseregions[i].erasesize;\n\n\t\tif (addr == mtd->eraseregions[i].offset + (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++;\n\t }\n\n   return (0);\n}",
        "static int kdamond_fn(void *data)\n{\n\tstruct damon_ctx *ctx = data;\n\tstruct damon_target *t;\n\tstruct damon_region *r, *next;": "static int kdamond_fn(void *data)\n{\n\tstruct damon_ctx *ctx = data;\n\tstruct damon_target *t;\n\tstruct damon_region *r, *next;\n\tunsigned int max_nr_accesses = 0;\n\tunsigned long sz_limit = 0;\n\tbool done = false;\n\n\tpr_debug(\"kdamond (%d) starts\\n\", current->pid);\n\n\tif (ctx->ops.init)\n\t\tctx->ops.init(ctx);\n\tif (ctx->callback.before_start && ctx->callback.before_start(ctx))\n\t\tdone = true;\n\n\tsz_limit = damon_region_sz_limit(ctx);\n\n\twhile (!kdamond_need_stop(ctx) && !done) {\n\t\tif (kdamond_wait_activation(ctx)) {\n\t\t\tdone = true;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (ctx->ops.prepare_access_checks)\n\t\t\tctx->ops.prepare_access_checks(ctx);\n\t\tif (ctx->callback.after_sampling &&\n\t\t\t\tctx->callback.after_sampling(ctx)) {\n\t\t\tdone = true;\n\t\t\tcontinue;\n\t\t}\n\n\t\tkdamond_usleep(ctx->sample_interval);\n\n\t\tif (ctx->ops.check_accesses)\n\t\t\tmax_nr_accesses = ctx->ops.check_accesses(ctx);\n\n\t\tif (kdamond_aggregate_interval_passed(ctx)) {\n\t\t\tkdamond_merge_regions(ctx,\n\t\t\t\t\tmax_nr_accesses / 10,\n\t\t\t\t\tsz_limit);\n\t\t\tif (ctx->callback.after_aggregation &&\n\t\t\t\t\tctx->callback.after_aggregation(ctx)) {\n\t\t\t\tdone = true;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tkdamond_apply_schemes(ctx);\n\t\t\tkdamond_reset_aggregated(ctx);\n\t\t\tkdamond_split_regions(ctx);\n\t\t\tif (ctx->ops.reset_aggregated)\n\t\t\t\tctx->ops.reset_aggregated(ctx);\n\t\t}\n\n\t\tif (kdamond_need_update_operations(ctx)) {\n\t\t\tif (ctx->ops.update)\n\t\t\t\tctx->ops.update(ctx);\n\t\t\tsz_limit = damon_region_sz_limit(ctx);\n\t\t}\n\t}\n\tdamon_for_each_target(t, ctx) {\n\t\tdamon_for_each_region_safe(r, next, t)\n\t\t\tdamon_destroy_region(r, t);\n\t}\n\n\tif (ctx->callback.before_terminate)\n\t\tctx->callback.before_terminate(ctx);\n\tif (ctx->ops.cleanup)\n\t\tctx->ops.cleanup(ctx);\n\n\tpr_debug(\"kdamond (%d) finishes\\n\", current->pid);\n\tmutex_lock(&ctx->kdamond_lock);\n\tctx->kdamond = NULL;\n\tmutex_unlock(&ctx->kdamond_lock);\n\n\tmutex_lock(&damon_lock);\n\tnr_running_ctxs--;\n\tif (!nr_running_ctxs && running_exclusive_ctxs)\n\t\trunning_exclusive_ctxs = false;\n\tmutex_unlock(&damon_lock);\n\n\treturn 0;\n}",
        "static int rcu_is_cpu_rrupt_from_idle(void)\n{\n\tlong nesting;\n\n\t/*": "static int rcu_is_cpu_rrupt_from_idle(void)\n{\n\tlong nesting;\n\n\t/*\n\t * Usually called from the tick; but also used from smp_function_call()\n\t * for expedited grace periods. This latter can result in running from\n\t * the idle task, instead of an actual IPI.\n\t */\n\tlockdep_assert_irqs_disabled();\n\n\t/* Check for counter underflows */\n\tRCU_LOCKDEP_WARN(__this_cpu_read(rcu_data.dynticks_nesting) < 0,\n\t\t\t \"RCU dynticks_nesting counter underflow!\");\n\tRCU_LOCKDEP_WARN(__this_cpu_read(rcu_data.dynticks_nmi_nesting) <= 0,\n\t\t\t \"RCU dynticks_nmi_nesting counter underflow/zero!\");\n\n\t/* Are we at first interrupt nesting level? */\n\tnesting = __this_cpu_read(rcu_data.dynticks_nmi_nesting);\n\tif (nesting > 1)\n\t\treturn false;\n\n\t/*\n\t * If we're not in an interrupt, we must be in the idle task!\n\t */\n\tWARN_ON_ONCE(!nesting && !is_idle_task(current));\n\n\t/* Does CPU appear to be idle from an RCU standpoint? */\n\treturn __this_cpu_read(rcu_data.dynticks_nesting) == 0;\n}",
        "static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en)\n{\n\tu32 slice, sl_bit_shift, line_bit, val, reg;\n\tstruct tegra_hte_soc *gs;\n": "static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en)\n{\n\tu32 slice, sl_bit_shift, line_bit, val, reg;\n\tstruct tegra_hte_soc *gs;\n\n\tsl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE);\n\n\tif (!chip)\n\t\treturn -EINVAL;\n\n\tgs = chip->data;\n\n\tif (line_id > chip->nlines) {\n\t\tdev_err(chip->dev,\n\t\t\t\"line id: %u is not supported by this controller\\n\",\n\t\t\tline_id);\n\t\treturn -EINVAL;\n\t}\n\n\tslice = line_id >> sl_bit_shift;\n\tline_bit = line_id & (HTE_SLICE_SIZE - 1);\n\treg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN;\n\n\tspin_lock(&gs->sl[slice].s_lock);\n\n\tif (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) {\n\t\tspin_unlock(&gs->sl[slice].s_lock);\n\t\tdev_dbg(chip->dev, \"device suspended\");\n\t\treturn -EBUSY;\n\t}\n\n\tval = tegra_hte_readl(gs, reg);\n\tif (en)\n\t\tval = val | (1 << line_bit);\n\telse\n\t\tval = val & (~(1 << line_bit));\n\ttegra_hte_writel(gs, reg, val);\n\n\tspin_unlock(&gs->sl[slice].s_lock);\n\n\tdev_dbg(chip->dev, \"line: %u, slice %u, line_bit %u, reg:0x%x\\n\",\n\t\tline_id, slice, line_bit, reg);\n\n\treturn 0;\n}",
        "static int xenhcd_conn_notify(struct xenhcd_info *info, unsigned int *eoiflag)\n{\n\tstruct xenusb_conn_response res;\n\tstruct xenusb_conn_request *req;\n\tRING_IDX rc, rp;": "static int xenhcd_conn_notify(struct xenhcd_info *info, unsigned int *eoiflag)\n{\n\tstruct xenusb_conn_response res;\n\tstruct xenusb_conn_request *req;\n\tRING_IDX rc, rp;\n\t__u16 id;\n\t__u8 portnum, speed;\n\tint more_to_do = 0;\n\tint notify;\n\tint port_changed = 0;\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&info->lock, flags);\n\n\trc = info->conn_ring.rsp_cons;\n\trp = info->conn_ring.sring->rsp_prod;\n\tif (RING_RESPONSE_PROD_OVERFLOW(&info->conn_ring, rp)) {\n\t\txenhcd_set_error(info, \"Illegal index on conn-ring\");\n\t\tspin_unlock_irqrestore(&info->lock, flags);\n\t\treturn 0;\n\t}\n\trmb(); /* ensure we see queued responses up to \"rp\" */\n\n\twhile (rc != rp) {\n\t\tRING_COPY_RESPONSE(&info->conn_ring, rc, &res);\n\t\tid = res.id;\n\t\tportnum = res.portnum;\n\t\tspeed = res.speed;\n\t\tinfo->conn_ring.rsp_cons = ++rc;\n\n\t\tif (xenhcd_rhport_connect(info, portnum, speed)) {\n\t\t\txenhcd_set_error(info, \"Illegal data on conn-ring\");\n\t\t\tspin_unlock_irqrestore(&info->lock, flags);\n\t\t\treturn 0;\n\t\t}\n\n\t\tif (info->ports[portnum - 1].c_connection)\n\t\t\tport_changed = 1;\n\n\t\tbarrier();\n\n\t\treq = RING_GET_REQUEST(&info->conn_ring,\n\t\t\t\t       info->conn_ring.req_prod_pvt);\n\t\treq->id = id;\n\t\tinfo->conn_ring.req_prod_pvt++;\n\n\t\t*eoiflag = 0;\n\t}\n\n\tif (rc != info->conn_ring.req_prod_pvt)\n\t\tRING_FINAL_CHECK_FOR_RESPONSES(&info->conn_ring, more_to_do);\n\telse\n\t\tinfo->conn_ring.sring->rsp_event = rc + 1;\n\n\tRING_PUSH_REQUESTS_AND_CHECK_NOTIFY(&info->conn_ring, notify);\n\tif (notify)\n\t\tnotify_remote_via_irq(info->irq);\n\n\tspin_unlock_irqrestore(&info->lock, flags);\n\n\tif (port_changed)\n\t\tusb_hcd_poll_rh_status(xenhcd_info_to_hcd(info));\n\n\treturn more_to_do;\n}",
        "static inline int audit_add_rule(struct audit_entry *entry)\n{\n\tstruct audit_entry *e;\n\tstruct audit_watch *watch = entry->rule.watch;\n\tstruct audit_tree *tree = entry->rule.tree;": "static inline int audit_add_rule(struct audit_entry *entry)\n{\n\tstruct audit_entry *e;\n\tstruct audit_watch *watch = entry->rule.watch;\n\tstruct audit_tree *tree = entry->rule.tree;\n\tstruct list_head *list;\n\tint err = 0;\n#ifdef CONFIG_AUDITSYSCALL\n\tint dont_count = 0;\n\n\t/* If any of these, don't count towards total */\n\tswitch(entry->rule.listnr) {\n\tcase AUDIT_FILTER_USER:\n\tcase AUDIT_FILTER_EXCLUDE:\n\tcase AUDIT_FILTER_FS:\n\t\tdont_count = 1;\n\t}\n#endif\n\n\tmutex_lock(&audit_filter_mutex);\n\te = audit_find_rule(entry, &list);\n\tif (e) {\n\t\tmutex_unlock(&audit_filter_mutex);\n\t\terr = -EEXIST;\n\t\t/* normally audit_add_tree_rule() will free it on failure */\n\t\tif (tree)\n\t\t\taudit_put_tree(tree);\n\t\treturn err;\n\t}\n\n\tif (watch) {\n\t\t/* audit_filter_mutex is dropped and re-taken during this call */\n\t\terr = audit_add_watch(&entry->rule, &list);\n\t\tif (err) {\n\t\t\tmutex_unlock(&audit_filter_mutex);\n\t\t\t/*\n\t\t\t * normally audit_add_tree_rule() will free it\n\t\t\t * on failure\n\t\t\t */\n\t\t\tif (tree)\n\t\t\t\taudit_put_tree(tree);\n\t\t\treturn err;\n\t\t}\n\t}\n\tif (tree) {\n\t\terr = audit_add_tree_rule(&entry->rule);\n\t\tif (err) {\n\t\t\tmutex_unlock(&audit_filter_mutex);\n\t\t\treturn err;\n\t\t}\n\t}\n\n\tentry->rule.prio = ~0ULL;\n\tif (entry->rule.listnr == AUDIT_FILTER_EXIT ||\n\t    entry->rule.listnr == AUDIT_FILTER_URING_EXIT) {\n\t\tif (entry->rule.flags & AUDIT_FILTER_PREPEND)\n\t\t\tentry->rule.prio = ++prio_high;\n\t\telse\n\t\t\tentry->rule.prio = --prio_low;\n\t}\n\n\tif (entry->rule.flags & AUDIT_FILTER_PREPEND) {\n\t\tlist_add(&entry->rule.list,\n\t\t\t &audit_rules_list[entry->rule.listnr]);\n\t\tlist_add_rcu(&entry->list, list);\n\t\tentry->rule.flags &= ~AUDIT_FILTER_PREPEND;\n\t} else {\n\t\tlist_add_tail(&entry->rule.list,\n\t\t\t      &audit_rules_list[entry->rule.listnr]);\n\t\tlist_add_tail_rcu(&entry->list, list);\n\t}\n#ifdef CONFIG_AUDITSYSCALL\n\tif (!dont_count)\n\t\taudit_n_rules++;\n\n\tif (!audit_match_signal(entry))\n\t\taudit_signals++;\n#endif\n\tmutex_unlock(&audit_filter_mutex);\n\n\treturn err;\n}",
        "static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);\n\tconst struct tegra_mc_client *client = &mc->soc->clients[src->id];\n\tu64 peak_bandwidth = icc_units_to_bps(src->peak_bw);": "static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);\n\tconst struct tegra_mc_client *client = &mc->soc->clients[src->id];\n\tu64 peak_bandwidth = icc_units_to_bps(src->peak_bw);\n\n\t/*\n\t * Skip pre-initialization that is done by icc_node_add(), which sets\n\t * bandwidth to maximum for all clients before drivers are loaded.\n\t *\n\t * This doesn't make sense for us because we don't have drivers for all\n\t * clients and it's okay to keep configuration left from bootloader\n\t * during boot, at least for today.\n\t */\n\tif (src == dst)\n\t\treturn 0;\n\n\t/* convert bytes/sec to megabytes/sec */\n\tdo_div(peak_bandwidth, 1000000);\n\n\ttegra30_mc_tune_client_latency(mc, client, peak_bandwidth);\n\n\treturn 0;\n}",
        "static int t7xx_pci_pm_init(struct t7xx_pci_dev *t7xx_dev)\n{\n\tstruct pci_dev *pdev = t7xx_dev->pdev;\n\n\tINIT_LIST_HEAD(&t7xx_dev->md_pm_entities);": "static int t7xx_pci_pm_init(struct t7xx_pci_dev *t7xx_dev)\n{\n\tstruct pci_dev *pdev = t7xx_dev->pdev;\n\n\tINIT_LIST_HEAD(&t7xx_dev->md_pm_entities);\n\tmutex_init(&t7xx_dev->md_pm_entity_mtx);\n\tspin_lock_init(&t7xx_dev->md_pm_lock);\n\tinit_completion(&t7xx_dev->sleep_lock_acquire);\n\tinit_completion(&t7xx_dev->pm_sr_ack);\n\tatomic_set(&t7xx_dev->md_pm_state, MTK_PM_INIT);\n\n\tdevice_init_wakeup(&pdev->dev, true);\n\tdev_pm_set_driver_flags(&pdev->dev, pdev->dev.power.driver_flags |\n\t\t\t\tDPM_FLAG_NO_DIRECT_COMPLETE);\n\n\tiowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);\n\tpm_runtime_set_autosuspend_delay(&pdev->dev, PM_AUTOSUSPEND_MS);\n\tpm_runtime_use_autosuspend(&pdev->dev);\n\n\treturn t7xx_wait_pm_config(t7xx_dev);\n}",
        "static int mt8195_mt6359_dev_probe(struct platform_device *pdev)\n{\n\tstruct snd_soc_card *card = &mt8195_mt6359_soc_card;\n\tstruct snd_soc_dai_link *dai_link;\n\tstruct mt8195_mt6359_priv *priv;": "static int mt8195_mt6359_dev_probe(struct platform_device *pdev)\n{\n\tstruct snd_soc_card *card = &mt8195_mt6359_soc_card;\n\tstruct snd_soc_dai_link *dai_link;\n\tstruct mt8195_mt6359_priv *priv;\n\tstruct device_node *platform_node, *adsp_node, *dp_node, *hdmi_node;\n\tstruct mt8195_card_data *card_data;\n\tint is5682s = 0;\n\tint init6359 = 0;\n\tint sof_on = 0;\n\tint ret, i;\n\n\tcard_data = (struct mt8195_card_data *)of_device_get_match_data(&pdev->dev);\n\tcard->dev = &pdev->dev;\n\n\tret = snd_soc_of_parse_card_name(card, \"model\");\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"%s new card name parsing error %d\\n\",\n\t\t\t__func__, ret);\n\t\treturn ret;\n\t}\n\n\tif (!card->name)\n\t\tcard->name = card_data->name;\n\n\tif (strstr(card->name, \"_5682s\"))\n\t\tis5682s = 1;\n\n\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tif (of_property_read_bool(pdev->dev.of_node, \"mediatek,dai-link\")) {\n\t\tret = mt8195_dailink_parse_of(card, pdev->dev.of_node,\n\t\t\t\t\t      \"mediatek,dai-link\");\n\t\tif (ret) {\n\t\t\tdev_dbg(&pdev->dev, \"Parse dai-link fail\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t} else {\n\t\tif (!sof_on)\n\t\t\tcard->num_links = DAI_LINK_REGULAR_NUM;\n\t}\n\n\tplatform_node = of_parse_phandle(pdev->dev.of_node,\n\t\t\t\t\t \"mediatek,platform\", 0);\n\tif (!platform_node) {\n\t\tdev_dbg(&pdev->dev, \"Property 'platform' missing or invalid\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tadsp_node = of_parse_phandle(pdev->dev.of_node, \"mediatek,adsp\", 0);\n\tif (adsp_node)\n\t\tsof_on = 1;\n\n\tdp_node = of_parse_phandle(pdev->dev.of_node, \"mediatek,dptx-codec\", 0);\n\thdmi_node = of_parse_phandle(pdev->dev.of_node,\n\t\t\t\t     \"mediatek,hdmi-codec\", 0);\n\n\tfor_each_card_prelinks(card, i, dai_link) {\n\t\tif (!dai_link->platforms->name) {\n\t\t\tif (!strncmp(dai_link->name, \"AFE_SOF\", strlen(\"AFE_SOF\")) && sof_on)\n\t\t\t\tdai_link->platforms->of_node = adsp_node;\n\t\t\telse\n\t\t\t\tdai_link->platforms->of_node = platform_node;\n\t\t}\n\n\t\tif (strcmp(dai_link->name, \"DPTX_BE\") == 0) {\n\t\t\tif (!dp_node) {\n\t\t\t\tdev_dbg(&pdev->dev, \"No property 'dptx-codec'\\n\");\n\t\t\t} else {\n\t\t\t\tdai_link->codecs->of_node = dp_node;\n\t\t\t\tdai_link->codecs->name = NULL;\n\t\t\t\tdai_link->codecs->dai_name = \"i2s-hifi\";\n\t\t\t\tdai_link->init = mt8195_dptx_codec_init;\n\t\t\t}\n\t\t} else if (strcmp(dai_link->name, \"ETDM3_OUT_BE\") == 0) {\n\t\t\tif (!hdmi_node) {\n\t\t\t\tdev_dbg(&pdev->dev, \"No property 'hdmi-codec'\\n\");\n\t\t\t} else {\n\t\t\t\tdai_link->codecs->of_node = hdmi_node;\n\t\t\t\tdai_link->codecs->name = NULL;\n\t\t\t\tdai_link->codecs->dai_name = \"i2s-hifi\";\n\t\t\t\tdai_link->init = mt8195_hdmi_codec_init;\n\t\t\t}\n\t\t} else if (strcmp(dai_link->name, \"ETDM1_OUT_BE\") == 0 ||\n\t\t\t   strcmp(dai_link->name, \"ETDM2_IN_BE\") == 0) {\n\t\t\tdai_link->codecs->name =\n\t\t\t\tis5682s ? RT5682S_DEV0_NAME : RT5682_DEV0_NAME;\n\t\t\tdai_link->codecs->dai_name =\n\t\t\t\tis5682s ? RT5682S_CODEC_DAI : RT5682_CODEC_DAI;\n\t\t} else if (strcmp(dai_link->name, \"DL_SRC_BE\") == 0 ||\n\t\t\t   strcmp(dai_link->name, \"UL_SRC1_BE\") == 0 ||\n\t\t\t   strcmp(dai_link->name, \"UL_SRC2_BE\") == 0) {\n\t\t\tif (!init6359) {\n\t\t\t\tdai_link->init = mt8195_mt6359_init;\n\t\t\t\tinit6359 = 1;\n\t\t\t}\n\t\t} else if (strcmp(dai_link->name, \"ETDM2_OUT_BE\") == 0) {\n\t\t\tswitch (card_data->quirk) {\n\t\t\tcase RT1011_SPEAKER_AMP_PRESENT:\n\t\t\t\tdai_link->codecs = rt1011_comps;\n\t\t\t\tdai_link->num_codecs = ARRAY_SIZE(rt1011_comps);\n\t\t\t\tdai_link->init = mt8195_rt1011_init;\n\t\t\t\tdai_link->ops = &mt8195_rt1011_etdm_ops;\n\t\t\t\tdai_link->be_hw_params_fixup = mt8195_etdm_hw_params_fixup;\n\t\t\t\tcard->codec_conf = rt1011_codec_conf;\n\t\t\t\tcard->num_configs = ARRAY_SIZE(rt1011_codec_conf);\n\t\t\t\tbreak;\n\t\t\tcase RT1019_SPEAKER_AMP_PRESENT:\n\t\t\t\tdai_link->codecs = rt1019_comps;\n\t\t\t\tdai_link->num_codecs = ARRAY_SIZE(rt1019_comps);\n\t\t\t\tdai_link->init = mt8195_rt1019_init;\n\t\t\t\tbreak;\n\t\t\tcase MAX98390_SPEAKER_AMP_PRESENT:\n\t\t\t\tdai_link->codecs = max98390_comps;\n\t\t\t\tdai_link->num_codecs = ARRAY_SIZE(max98390_comps);\n\t\t\t\tdai_link->init = mt8195_max98390_init;\n\t\t\t\tcard->codec_conf = max98390_codec_conf;\n\t\t\t\tcard->num_configs = ARRAY_SIZE(max98390_codec_conf);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (sof_on)\n\t\tcard->late_probe = mt8195_mt6359_card_late_probe;\n\n\tsnd_soc_card_set_drvdata(card, priv);\n\n\tret = devm_snd_soc_register_card(&pdev->dev, card);\n\n\tof_node_put(platform_node);\n\tof_node_put(adsp_node);\n\tof_node_put(dp_node);\n\tof_node_put(hdmi_node);\n\treturn ret;\n}",
        "static int niu_init_hostinfo(struct niu *np)\n{\n\tstruct niu_parent *parent = np->parent;\n\tstruct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];\n\tint i, err, num_alt = niu_num_alt_addr(np);": "static int niu_init_hostinfo(struct niu *np)\n{\n\tstruct niu_parent *parent = np->parent;\n\tstruct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];\n\tint i, err, num_alt = niu_num_alt_addr(np);\n\tint first_rdc_table = tp->first_table_num;\n\n\terr = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);\n\tif (err)\n\t\treturn err;\n\n\terr = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);\n\tif (err)\n\t\treturn err;\n\n\tfor (i = 0; i < num_alt; i++) {\n\t\terr = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}",
        "static int tcpm_pd_build_pps_request(struct tcpm_port *port, u32 *rdo)\n{\n\tunsigned int out_mv, op_ma, op_mw, max_mv, max_ma, flags;\n\tenum pd_pdo_type type;\n\tunsigned int src_pdo_index;": "static int tcpm_pd_build_pps_request(struct tcpm_port *port, u32 *rdo)\n{\n\tunsigned int out_mv, op_ma, op_mw, max_mv, max_ma, flags;\n\tenum pd_pdo_type type;\n\tunsigned int src_pdo_index;\n\tu32 pdo;\n\n\tsrc_pdo_index = tcpm_pd_select_pps_apdo(port);\n\tif (!src_pdo_index)\n\t\treturn -EOPNOTSUPP;\n\n\tpdo = port->source_caps[src_pdo_index];\n\ttype = pdo_type(pdo);\n\n\tswitch (type) {\n\tcase PDO_TYPE_APDO:\n\t\tif (pdo_apdo_type(pdo) != APDO_TYPE_PPS) {\n\t\t\ttcpm_log(port, \"Invalid APDO selected!\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tmax_mv = port->pps_data.req_max_volt;\n\t\tmax_ma = port->pps_data.req_max_curr;\n\t\tout_mv = port->pps_data.req_out_volt;\n\t\top_ma = port->pps_data.req_op_curr;\n\t\tbreak;\n\tdefault:\n\t\ttcpm_log(port, \"Invalid PDO selected!\");\n\t\treturn -EINVAL;\n\t}\n\n\tflags = RDO_USB_COMM | RDO_NO_SUSPEND;\n\n\top_mw = (op_ma * out_mv) / 1000;\n\tif (op_mw < port->operating_snk_mw) {\n\t\t/*\n\t\t * Try raising current to meet power needs. If that's not enough\n\t\t * then try upping the voltage. If that's still not enough\n\t\t * then we've obviously chosen a PPS APDO which really isn't\n\t\t * suitable so abandon ship.\n\t\t */\n\t\top_ma = (port->operating_snk_mw * 1000) / out_mv;\n\t\tif ((port->operating_snk_mw * 1000) % out_mv)\n\t\t\t++op_ma;\n\t\top_ma += RDO_PROG_CURR_MA_STEP - (op_ma % RDO_PROG_CURR_MA_STEP);\n\n\t\tif (op_ma > max_ma) {\n\t\t\top_ma = max_ma;\n\t\t\tout_mv = (port->operating_snk_mw * 1000) / op_ma;\n\t\t\tif ((port->operating_snk_mw * 1000) % op_ma)\n\t\t\t\t++out_mv;\n\t\t\tout_mv += RDO_PROG_VOLT_MV_STEP -\n\t\t\t\t  (out_mv % RDO_PROG_VOLT_MV_STEP);\n\n\t\t\tif (out_mv > max_mv) {\n\t\t\t\ttcpm_log(port, \"Invalid PPS APDO selected!\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\t}\n\n\ttcpm_log(port, \"cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d\",\n\t\t port->cc_req, port->cc1, port->cc2, port->vbus_source,\n\t\t port->vconn_role == TYPEC_SOURCE ? \"source\" : \"sink\",\n\t\t port->polarity);\n\n\t*rdo = RDO_PROG(src_pdo_index + 1, out_mv, op_ma, flags);\n\n\ttcpm_log(port, \"Requesting APDO %d: %u mV, %u mA\",\n\t\t src_pdo_index, out_mv, op_ma);\n\n\tport->pps_data.req_op_curr = op_ma;\n\tport->pps_data.req_out_volt = out_mv;\n\n\treturn 0;\n}",
        "static struct sock *bpf_iter_tcp_batch(struct seq_file *seq)\n{\n\tstruct bpf_tcp_iter_state *iter = seq->private;\n\tstruct tcp_iter_state *st = &iter->state;\n\tunsigned int expected;": "static struct sock *bpf_iter_tcp_batch(struct seq_file *seq)\n{\n\tstruct bpf_tcp_iter_state *iter = seq->private;\n\tstruct tcp_iter_state *st = &iter->state;\n\tunsigned int expected;\n\tbool resized = false;\n\tstruct sock *sk;\n\n\t/* The st->bucket is done.  Directly advance to the next\n\t * bucket instead of having the tcp_seek_last_pos() to skip\n\t * one by one in the current bucket and eventually find out\n\t * it has to advance to the next bucket.\n\t */\n\tif (iter->st_bucket_done) {\n\t\tst->offset = 0;\n\t\tst->bucket++;\n\t\tif (st->state == TCP_SEQ_STATE_LISTENING &&\n\t\t    st->bucket > tcp_hashinfo.lhash2_mask) {\n\t\t\tst->state = TCP_SEQ_STATE_ESTABLISHED;\n\t\t\tst->bucket = 0;\n\t\t}\n\t}\n\nagain:\n\t/* Get a new batch */\n\titer->cur_sk = 0;\n\titer->end_sk = 0;\n\titer->st_bucket_done = false;\n\n\tsk = tcp_seek_last_pos(seq);\n\tif (!sk)\n\t\treturn NULL; /* Done */\n\n\tif (st->state == TCP_SEQ_STATE_LISTENING)\n\t\texpected = bpf_iter_tcp_listening_batch(seq, sk);\n\telse\n\t\texpected = bpf_iter_tcp_established_batch(seq, sk);\n\n\tif (iter->end_sk == expected) {\n\t\titer->st_bucket_done = true;\n\t\treturn sk;\n\t}\n\n\tif (!resized && !bpf_iter_tcp_realloc_batch(iter, expected * 3 / 2)) {\n\t\tresized = true;\n\t\tgoto again;\n\t}\n\n\treturn sk;\n}",
        "static bool flush_required(int cpu)\n{\n#if IS_ENABLED(CONFIG_RPS)\n\tstruct softnet_data *sd = &per_cpu(softnet_data, cpu);\n\tbool do_flush;": "static bool flush_required(int cpu)\n{\n#if IS_ENABLED(CONFIG_RPS)\n\tstruct softnet_data *sd = &per_cpu(softnet_data, cpu);\n\tbool do_flush;\n\n\trps_lock_irq_disable(sd);\n\n\t/* as insertion into process_queue happens with the rps lock held,\n\t * process_queue access may race only with dequeue\n\t */\n\tdo_flush = !skb_queue_empty(&sd->input_pkt_queue) ||\n\t\t   !skb_queue_empty_lockless(&sd->process_queue);\n\trps_unlock_irq_enable(sd);\n\n\treturn do_flush;\n#endif\n\t/* without RPS we can't safely check input_pkt_queue: during a\n\t * concurrent remote skb_queue_splice() we can detect as empty both\n\t * input_pkt_queue and process_queue even if the latter could end-up\n\t * containing a lot of packets.\n\t */\n\treturn true;\n}",
        "static int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc)\n{\n/* TODO This is to be re-visited and adjusted */\n#define DFC_WRITE_WAIT_COUNT\t1000\n\tu32 val, count = DFC_WRITE_WAIT_COUNT;": "static int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc)\n{\n/* TODO This is to be re-visited and adjusted */\n#define DFC_WRITE_WAIT_COUNT\t1000\n\tu32 val, count = DFC_WRITE_WAIT_COUNT;\n\n\tregw(dfc->dft_corr_vert[index], DFCMEM0);\n\tregw(dfc->dft_corr_horz[index], DFCMEM1);\n\tregw(dfc->dft_corr_sub1[index], DFCMEM2);\n\tregw(dfc->dft_corr_sub2[index], DFCMEM3);\n\tregw(dfc->dft_corr_sub3[index], DFCMEM4);\n\t/* set WR bit to write */\n\tval = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK;\n\tregw(val, DFCMEMCTL);\n\n\t/*\n\t * Assume, it is very short. If we get an error, we need to\n\t * adjust this value\n\t */\n\twhile (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK)\n\t\tcount--;\n\t/*\n\t * TODO We expect the count to be non-zero to be successful. Adjust\n\t * the count if write requires more time\n\t */\n\n\tif (count) {\n\t\tdev_err(ccdc_cfg.dev, \"defect table write timeout !!!\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}",
        "static int record__init_thread_user_masks(struct record *rec, struct perf_cpu_map *cpus)\n{\n\tint t, ret;\n\tu32 s, nr_spec = 0;\n\tchar **maps_spec = NULL, **affinity_spec = NULL, **tmp_spec;": "static int record__init_thread_user_masks(struct record *rec, struct perf_cpu_map *cpus)\n{\n\tint t, ret;\n\tu32 s, nr_spec = 0;\n\tchar **maps_spec = NULL, **affinity_spec = NULL, **tmp_spec;\n\tchar *user_spec, *spec, *spec_ptr, *mask, *mask_ptr, *dup_mask = NULL;\n\n\tfor (t = 0, user_spec = (char *)rec->opts.threads_user_spec; ; t++, user_spec = NULL) {\n\t\tspec = strtok_r(user_spec, \":\", &spec_ptr);\n\t\tif (spec == NULL)\n\t\t\tbreak;\n\t\tpr_debug2(\"threads_spec[%d]: %s\\n\", t, spec);\n\t\tmask = strtok_r(spec, \"/\", &mask_ptr);\n\t\tif (mask == NULL)\n\t\t\tbreak;\n\t\tpr_debug2(\"  maps mask: %s\\n\", mask);\n\t\ttmp_spec = realloc(maps_spec, (nr_spec + 1) * sizeof(char *));\n\t\tif (!tmp_spec) {\n\t\t\tpr_err(\"Failed to reallocate maps spec\\n\");\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out_free;\n\t\t}\n\t\tmaps_spec = tmp_spec;\n\t\tmaps_spec[nr_spec] = dup_mask = strdup(mask);\n\t\tif (!maps_spec[nr_spec]) {\n\t\t\tpr_err(\"Failed to allocate maps spec[%d]\\n\", nr_spec);\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out_free;\n\t\t}\n\t\tmask = strtok_r(NULL, \"/\", &mask_ptr);\n\t\tif (mask == NULL) {\n\t\t\tpr_err(\"Invalid thread maps or affinity specs\\n\");\n\t\t\tret = -EINVAL;\n\t\t\tgoto out_free;\n\t\t}\n\t\tpr_debug2(\"  affinity mask: %s\\n\", mask);\n\t\ttmp_spec = realloc(affinity_spec, (nr_spec + 1) * sizeof(char *));\n\t\tif (!tmp_spec) {\n\t\t\tpr_err(\"Failed to reallocate affinity spec\\n\");\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out_free;\n\t\t}\n\t\taffinity_spec = tmp_spec;\n\t\taffinity_spec[nr_spec] = strdup(mask);\n\t\tif (!affinity_spec[nr_spec]) {\n\t\t\tpr_err(\"Failed to allocate affinity spec[%d]\\n\", nr_spec);\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out_free;\n\t\t}\n\t\tdup_mask = NULL;\n\t\tnr_spec++;\n\t}\n\n\tret = record__init_thread_masks_spec(rec, cpus, (const char **)maps_spec,\n\t\t\t\t\t     (const char **)affinity_spec, nr_spec);\n\nout_free:\n\tfree(dup_mask);\n\tfor (s = 0; s < nr_spec; s++) {\n\t\tif (maps_spec)\n\t\t\tfree(maps_spec[s]);\n\t\tif (affinity_spec)\n\t\t\tfree(affinity_spec[s]);\n\t}\n\tfree(affinity_spec);\n\tfree(maps_spec);\n\n\treturn ret;\n}",
        "static void defect7374_workaround(struct net2280 *dev, struct usb_ctrlrequest r)\n{\n\tu32 scratch, fsmvalue;\n\tu32 ack_wait_timeout, state;\n": "static void defect7374_workaround(struct net2280 *dev, struct usb_ctrlrequest r)\n{\n\tu32 scratch, fsmvalue;\n\tu32 ack_wait_timeout, state;\n\n\t/* Workaround for Defect 7374 (U1/U2 erroneously rejected): */\n\tscratch = get_idx_reg(dev->regs, SCRATCH);\n\tfsmvalue = scratch & (0xf << DEFECT7374_FSM_FIELD);\n\tscratch &= ~(0xf << DEFECT7374_FSM_FIELD);\n\n\tif (!((fsmvalue == DEFECT7374_FSM_WAITING_FOR_CONTROL_READ) &&\n\t\t\t\t(r.bRequestType & USB_DIR_IN)))\n\t\treturn;\n\n\t/* This is the first Control Read for this connection: */\n\tif (!(readl(&dev->usb->usbstat) & BIT(SUPER_SPEED_MODE))) {\n\t\t/*\n\t\t * Connection is NOT SS:\n\t\t * - Connection must be FS or HS.\n\t\t * - This FSM state should allow workaround software to\n\t\t * run after the next USB connection.\n\t\t */\n\t\tscratch |= DEFECT7374_FSM_NON_SS_CONTROL_READ;\n\t\tdev->bug7734_patched = 1;\n\t\tgoto restore_data_eps;\n\t}\n\n\t/* Connection is SS: */\n\tfor (ack_wait_timeout = 0;\n\t\t\tack_wait_timeout < DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS;\n\t\t\tack_wait_timeout++) {\n\n\t\tstate =\treadl(&dev->plregs->pl_ep_status_1)\n\t\t\t& (0xff << STATE);\n\t\tif ((state >= (ACK_GOOD_NORMAL << STATE)) &&\n\t\t\t(state <= (ACK_GOOD_MORE_ACKS_TO_COME << STATE))) {\n\t\t\tscratch |= DEFECT7374_FSM_SS_CONTROL_READ;\n\t\t\tdev->bug7734_patched = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\t/*\n\t\t * We have not yet received host's Data Phase ACK\n\t\t * - Wait and try again.\n\t\t */\n\t\tudelay(DEFECT_7374_PROCESSOR_WAIT_TIME);\n\t}\n\n\n\tif (ack_wait_timeout >= DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS) {\n\t\tep_err(dev, \"FAIL: Defect 7374 workaround waited but failed \"\n\t\t\"to detect SS host's data phase ACK.\");\n\t\tep_err(dev, \"PL_EP_STATUS_1(23:16):.Expected from 0x11 to 0x16\"\n\t\t\"got 0x%2.2x.\\n\", state >> STATE);\n\t} else {\n\t\tep_warn(dev, \"INFO: Defect 7374 workaround waited about\\n\"\n\t\t\"%duSec for Control Read Data Phase ACK\\n\",\n\t\t\tDEFECT_7374_PROCESSOR_WAIT_TIME * ack_wait_timeout);\n\t}\n\nrestore_data_eps:\n\t/*\n\t * Restore data EPs to their pre-workaround settings (disabled,\n\t * initialized, and other details).\n\t */\n\tdefect7374_disable_data_eps(dev);\n\n\tset_idx_reg(dev->regs, SCRATCH, scratch);\n\n\treturn;\n}",
        "static void peer_remove_after_dead(struct wg_peer *peer)\n{\n\tWARN_ON(!peer->is_dead);\n\n\t/* No more keypairs can be created for this peer, since is_dead protects": "static void peer_remove_after_dead(struct wg_peer *peer)\n{\n\tWARN_ON(!peer->is_dead);\n\n\t/* No more keypairs can be created for this peer, since is_dead protects\n\t * add_new_keypair, so we can now destroy existing ones.\n\t */\n\twg_noise_keypairs_clear(&peer->keypairs);\n\n\t/* Destroy all ongoing timers that were in-flight at the beginning of\n\t * this function.\n\t */\n\twg_timers_stop(peer);\n\n\t/* The transition between packet encryption/decryption queues isn't\n\t * guarded by is_dead, but each reference's life is strictly bounded by\n\t * two generations: once for parallel crypto and once for serial\n\t * ingestion, so we can simply flush twice, and be sure that we no\n\t * longer have references inside these queues.\n\t */\n\n\t/* a) For encrypt/decrypt. */\n\tflush_workqueue(peer->device->packet_crypt_wq);\n\t/* b.1) For send (but not receive, since that's napi). */\n\tflush_workqueue(peer->device->packet_crypt_wq);\n\t/* b.2.1) For receive (but not send, since that's wq). */\n\tnapi_disable(&peer->napi);\n\t/* b.2.1) It's now safe to remove the napi struct, which must be done\n\t * here from process context.\n\t */\n\tnetif_napi_del(&peer->napi);\n\n\t/* Ensure any workstructs we own (like transmit_handshake_work or\n\t * clear_peer_work) no longer are in use.\n\t */\n\tflush_workqueue(peer->device->handshake_send_wq);\n\n\t/* After the above flushes, a peer might still be active in a few\n\t * different contexts: 1) from xmit(), before hitting is_dead and\n\t * returning, 2) from wg_packet_consume_data(), before hitting is_dead\n\t * and returning, 3) from wg_receive_handshake_packet() after a point\n\t * where it has processed an incoming handshake packet, but where\n\t * all calls to pass it off to timers fails because of is_dead. We won't\n\t * have new references in (1) eventually, because we're removed from\n\t * allowedips; we won't have new references in (2) eventually, because\n\t * wg_index_hashtable_lookup will always return NULL, since we removed\n\t * all existing keypairs and no more can be created; we won't have new\n\t * references in (3) eventually, because we're removed from the pubkey\n\t * hash table, which allows for a maximum of one handshake response,\n\t * via the still-uncleared index hashtable entry, but not more than one,\n\t * and in wg_cookie_message_consume, the lookup eventually gets a peer\n\t * with a refcount of zero, so no new reference is taken.\n\t */\n\n\t--peer->device->num_peers;\n\twg_peer_put(peer);\n}",
        "static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)\n{\n\tint ret, status;\n\tstruct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];\n\tstruct acpi_pcct_shared_memory __iomem *generic_comm_base =": "static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)\n{\n\tint ret, status;\n\tstruct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];\n\tstruct acpi_pcct_shared_memory __iomem *generic_comm_base =\n\t\tpcc_ss_data->pcc_comm_addr;\n\n\tif (!pcc_ss_data->platform_owns_pcc)\n\t\treturn 0;\n\n\t/*\n\t * Poll PCC status register every 3us(delay_us) for maximum of\n\t * deadline_us(timeout_us) until PCC command complete bit is set(cond)\n\t */\n\tret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,\n\t\t\t\t\tstatus & PCC_CMD_COMPLETE_MASK, 3,\n\t\t\t\t\tpcc_ss_data->deadline_us);\n\n\tif (likely(!ret)) {\n\t\tpcc_ss_data->platform_owns_pcc = false;\n\t\tif (chk_err_bit && (status & PCC_ERROR_MASK))\n\t\t\tret = -EIO;\n\t}\n\n\tif (unlikely(ret))\n\t\tpr_err(\"PCC check channel failed for ss: %d. ret=%d\\n\",\n\t\t       pcc_ss_id, ret);\n\n\treturn ret;\n}",
        "static int smcr_cdc_get_slot_and_msg_send(struct smc_connection *conn)\n{\n\tstruct smc_cdc_tx_pend *pend;\n\tstruct smc_wr_buf *wr_buf;\n\tstruct smc_link *link;": "static int smcr_cdc_get_slot_and_msg_send(struct smc_connection *conn)\n{\n\tstruct smc_cdc_tx_pend *pend;\n\tstruct smc_wr_buf *wr_buf;\n\tstruct smc_link *link;\n\tbool again = false;\n\tint rc;\n\nagain:\n\tlink = conn->lnk;\n\tif (!smc_wr_tx_link_hold(link))\n\t\treturn -ENOLINK;\n\trc = smc_cdc_get_free_slot(conn, link, &wr_buf, NULL, &pend);\n\tif (rc)\n\t\tgoto put_out;\n\n\tspin_lock_bh(&conn->send_lock);\n\tif (link != conn->lnk) {\n\t\t/* link of connection changed, try again one time*/\n\t\tspin_unlock_bh(&conn->send_lock);\n\t\tsmc_wr_tx_put_slot(link,\n\t\t\t\t   (struct smc_wr_tx_pend_priv *)pend);\n\t\tsmc_wr_tx_link_put(link);\n\t\tif (again)\n\t\t\treturn -ENOLINK;\n\t\tagain = true;\n\t\tgoto again;\n\t}\n\trc = smc_cdc_msg_send(conn, wr_buf, pend);\n\tspin_unlock_bh(&conn->send_lock);\nput_out:\n\tsmc_wr_tx_link_put(link);\n\treturn rc;\n}",
        "static void cops_rx(struct net_device *dev)\n{\n        int pkt_len = 0;\n        int rsp_type = 0;\n        struct sk_buff *skb = NULL;": "static void cops_rx(struct net_device *dev)\n{\n        int pkt_len = 0;\n        int rsp_type = 0;\n        struct sk_buff *skb = NULL;\n        struct cops_local *lp = netdev_priv(dev);\n        int ioaddr = dev->base_addr;\n        int boguscount = 0;\n        unsigned long flags;\n\n\n\tspin_lock_irqsave(&lp->lock, flags);\n\t\n        if(lp->board==DAYNA)\n        {\n                outb(0, ioaddr);                /* Send out Zero length. */\n                outb(0, ioaddr);\n                outb(DATA_READ, ioaddr);        /* Send read command out. */\n\n                /* Wait for DMA to turn around. */\n                while(++boguscount<1000000)\n                {\n\t\t\tbarrier();\n                        if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_READY)\n                                break;\n                }\n\n                if(boguscount==1000000)\n                {\n                        printk(KERN_WARNING \"%s: DMA timed out.\\n\",dev->name);\n\t\t\tspin_unlock_irqrestore(&lp->lock, flags);\n                        return;\n                }\n        }\n\n        /* Get response length. */\n\tpkt_len = inb(ioaddr);\n        pkt_len |= (inb(ioaddr) << 8);\n        /* Input IO code. */\n        rsp_type=inb(ioaddr);\n\n        /* Malloc up new buffer. */\n        skb = dev_alloc_skb(pkt_len);\n        if(skb == NULL)\n        {\n                printk(KERN_WARNING \"%s: Memory squeeze, dropping packet.\\n\",\n\t\t\tdev->name);\n                dev->stats.rx_dropped++;\n                while(pkt_len--)        /* Discard packet */\n                        inb(ioaddr);\n                spin_unlock_irqrestore(&lp->lock, flags);\n                return;\n        }\n        skb->dev = dev;\n        skb_put(skb, pkt_len);\n        skb->protocol = htons(ETH_P_LOCALTALK);\n\n        insb(ioaddr, skb->data, pkt_len);               /* Eat the Data */\n\n        if(lp->board==DAYNA)\n                outb(1, ioaddr+DAYNA_INT_CARD);         /* Interrupt the card */\n\n        spin_unlock_irqrestore(&lp->lock, flags);  /* Restore interrupts. */\n\n        /* Check for bad response length */\n        if(pkt_len < 0 || pkt_len > MAX_LLAP_SIZE)\n        {\n\t\tprintk(KERN_WARNING \"%s: Bad packet length of %d bytes.\\n\", \n\t\t\tdev->name, pkt_len);\n                dev->stats.tx_errors++;\n                dev_kfree_skb_any(skb);\n                return;\n        }\n\n        /* Set nodeid and then get out. */\n        if(rsp_type == LAP_INIT_RSP)\n        {\t/* Nodeid taken from received packet. */\n                lp->node_acquire = skb->data[0];\n                dev_kfree_skb_any(skb);\n                return;\n        }\n\n        /* One last check to make sure we have a good packet. */\n        if(rsp_type != LAP_RESPONSE)\n        {\n                printk(KERN_WARNING \"%s: Bad packet type %d.\\n\", dev->name, rsp_type);\n                dev->stats.tx_errors++;\n                dev_kfree_skb_any(skb);\n                return;\n        }\n\n        skb_reset_mac_header(skb);    /* Point to entire packet. */\n        skb_pull(skb,3);\n        skb_reset_transport_header(skb);    /* Point to data (Skip header). */\n\n        /* Update the counters. */\n        dev->stats.rx_packets++;\n        dev->stats.rx_bytes += skb->len;\n\n        /* Send packet to a higher place. */\n        netif_rx(skb);\n}",
        "static int reset_ms(struct rtsx_chip *chip)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tint retval;\n\tu16 i, reg_addr, block_size;": "static int reset_ms(struct rtsx_chip *chip)\n{\n\tstruct ms_info *ms_card = &chip->ms_card;\n\tint retval;\n\tu16 i, reg_addr, block_size;\n\tu8 val, extra[MS_EXTRA_SIZE], j, *ptr;\n#ifndef SUPPORT_MAGIC_GATE\n\tu16 eblock_cnt;\n#endif\n\n\tretval = ms_prepare_reset(chip);\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\tms_card->ms_type |= TYPE_MS;\n\n\tretval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\tretval = ms_read_status_reg(chip);\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\tretval = rtsx_read_register(chip, PPBUF_BASE2, &val);\n\tif (retval)\n\t\treturn retval;\n\n\tif (val & WRT_PRTCT)\n\t\tchip->card_wp |= MS_CARD;\n\telse\n\t\tchip->card_wp &= ~MS_CARD;\n\n\ti = 0;\n\nRE_SEARCH:\n\t/* Search Boot Block */\n\twhile (i < (MAX_DEFECTIVE_BLOCK + 2)) {\n\t\tif (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {\n\t\t\tms_set_err_code(chip, MS_NO_CARD);\n\t\t\treturn STATUS_FAIL;\n\t\t}\n\n\t\tretval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\ti++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (extra[0] & BLOCK_OK) {\n\t\t\tif (!(extra[1] & NOT_BOOT_BLOCK)) {\n\t\t\t\tms_card->boot_block = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\ti++;\n\t}\n\n\tif (i == (MAX_DEFECTIVE_BLOCK + 2)) {\n\t\tdev_dbg(rtsx_dev(chip), \"No boot block found!\");\n\t\treturn STATUS_FAIL;\n\t}\n\n\tfor (j = 0; j < 3; j++) {\n\t\tretval = ms_read_page(chip, ms_card->boot_block, j);\n\t\tif (retval != STATUS_SUCCESS) {\n\t\t\tif (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {\n\t\t\t\ti = ms_card->boot_block + 1;\n\t\t\t\tms_set_err_code(chip, MS_NO_ERROR);\n\t\t\t\tgoto RE_SEARCH;\n\t\t\t}\n\t\t}\n\t}\n\n\tretval = ms_read_page(chip, ms_card->boot_block, 0);\n\tif (retval != STATUS_SUCCESS)\n\t\treturn STATUS_FAIL;\n\n\t/* Read MS system information as sys_info */\n\trtsx_init_cmd(chip);\n\n\tfor (i = 0; i < 96; i++)\n\t\trtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);\n\n\tretval = rtsx_send_cmd(chip, MS_CARD, 100);\n\tif (retval < 0)\n\t\treturn STATUS_FAIL;\n\n\tptr = rtsx_get_cmd_data(chip);\n\tmemcpy(ms_card->raw_sys_info, ptr, 96);\n\n\t/* Read useful block contents */\n\trtsx_init_cmd(chip);\n\n\trtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);\n\trtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);\n\n\tfor (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;\n\t     reg_addr++)\n\t\trtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);\n\n\tfor (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)\n\t\trtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);\n\n\trtsx_add_cmd(chip, READ_REG_CMD, MS_device_type, 0, 0);\n\trtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_support, 0, 0);\n\n\tretval = rtsx_send_cmd(chip, MS_CARD, 100);\n\tif (retval < 0)\n\t\treturn STATUS_FAIL;\n\n\tptr = rtsx_get_cmd_data(chip);\n\n\tdev_dbg(rtsx_dev(chip), \"Boot block data:\\n\");\n\tdev_dbg(rtsx_dev(chip), \"%*ph\\n\", 16, ptr);\n\n\t/* Block ID error\n\t * HEADER_ID0, HEADER_ID1\n\t */\n\tif (ptr[0] != 0x00 || ptr[1] != 0x01) {\n\t\ti = ms_card->boot_block + 1;\n\t\tgoto RE_SEARCH;\n\t}\n\n\t/* Page size error\n\t * PAGE_SIZE_0, PAGE_SIZE_1\n\t */\n\tif (ptr[12] != 0x02 || ptr[13] != 0x00) {\n\t\ti = ms_card->boot_block + 1;\n\t\tgoto RE_SEARCH;\n\t}\n\n\tif (ptr[14] == 1 || ptr[14] == 3)\n\t\tchip->card_wp |= MS_CARD;\n\n\t/* BLOCK_SIZE_0, BLOCK_SIZE_1 */\n\tblock_size = ((u16)ptr[6] << 8) | ptr[7];\n\tif (block_size == 0x0010) {\n\t\t/* Block size 16KB */\n\t\tms_card->block_shift = 5;\n\t\tms_card->page_off = 0x1F;\n\t} else if (block_size == 0x0008) {\n\t\t/* Block size 8KB */\n\t\tms_card->block_shift = 4;\n\t\tms_card->page_off = 0x0F;\n\t}\n\n\t/* BLOCK_COUNT_0, BLOCK_COUNT_1 */\n\tms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];\n\n#ifdef SUPPORT_MAGIC_GATE\n\tj = ptr[10];\n\n\tif (ms_card->block_shift == 4)  { /* 4MB or 8MB */\n\t\tif (j < 2)  { /* Effective block for 4MB: 0x1F0 */\n\t\t\tms_card->capacity = 0x1EE0;\n\t\t} else { /* Effective block for 8MB: 0x3E0 */\n\t\t\tms_card->capacity = 0x3DE0;\n\t\t}\n\t} else  { /* 16MB, 32MB, 64MB or 128MB */\n\t\tif (j < 5)  { /* Effective block for 16MB: 0x3E0 */\n\t\t\tms_card->capacity = 0x7BC0;\n\t\t} else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */\n\t\t\tms_card->capacity = 0xF7C0;\n\t\t} else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */\n\t\t\tms_card->capacity = 0x1EF80;\n\t\t} else { /* Effective block for 128MB: 0x1F00 */\n\t\t\tms_card->capacity = 0x3DF00;\n\t\t}\n\t}\n#else\n\t/* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */\n\teblock_cnt = ((u16)ptr[10] << 8) | ptr[11];\n\n\tms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;\n#endif\n\n\tchip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;\n\n\t/* Switch I/F Mode */\n\tif (ptr[15]) {\n\t\tretval = ms_set_rw_reg_addr(chip, 0, 0, SYSTEM_PARAM, 1);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\treturn STATUS_FAIL;\n\n\t\tretval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88);\n\t\tif (retval)\n\t\t\treturn retval;\n\n\t\tretval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0);\n\t\tif (retval)\n\t\t\treturn retval;\n\n\t\tretval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,\n\t\t\t\t\t NO_WAIT_INT);\n\t\tif (retval != STATUS_SUCCESS)\n\t\t\treturn STATUS_FAIL;\n\n\t\tretval = rtsx_write_register(chip, MS_CFG,\n\t\t\t\t\t     0x58 | MS_NO_CHECK_INT,\n\t\t\t\t\t     MS_BUS_WIDTH_4 |\n\t\t\t\t\t     PUSH_TIME_ODD |\n\t\t\t\t\t     MS_NO_CHECK_INT);\n\t\tif (retval)\n\t\t\treturn retval;\n\n\t\tms_card->ms_type |= MS_4BIT;\n\t}\n\n\tif (CHK_MS4BIT(ms_card))\n\t\tchip->card_bus_width[chip->card2lun[MS_CARD]] = 4;\n\telse\n\t\tchip->card_bus_width[chip->card2lun[MS_CARD]] = 1;\n\n\treturn STATUS_SUCCESS;\n}",
        "static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr)\n{\n\tu32 reg, sda_hold_cnt, speed_mode;\n\n\ti2c_parse_fw_timings(ctlr->dev, &ctlr->t, true);": "static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr)\n{\n\tu32 reg, sda_hold_cnt, speed_mode;\n\n\ti2c_parse_fw_timings(ctlr->dev, &ctlr->t, true);\n\tctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz);\n\n\tswitch (ctlr->t.bus_freq_hz) {\n\tcase I2C_MAX_FAST_MODE_FREQ:\n\t\tspeed_mode = HISI_I2C_FAST_SPEED_MODE;\n\t\thisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT);\n\t\tbreak;\n\tcase I2C_MAX_HIGH_SPEED_MODE_FREQ:\n\t\tspeed_mode = HISI_I2C_HIGH_SPEED_MODE;\n\t\thisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT);\n\t\tbreak;\n\tcase I2C_MAX_STANDARD_MODE_FREQ:\n\tdefault:\n\t\tspeed_mode = HISI_I2C_STD_SPEED_MODE;\n\n\t\t/* For default condition force the bus speed to standard mode. */\n\t\tctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;\n\t\thisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT);\n\t\tbreak;\n\t}\n\n\treg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);\n\treg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE;\n\treg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode);\n\twritel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);\n\n\tsda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz);\n\n\treg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt);\n\twritel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD);\n\n\twritel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN);\n\n\treg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH);\n\treg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH);\n\twritel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);\n}",
        "static int check_child_memory_mapping(int mem_type, int mode, int mapping)\n{\n\tchar *ptr;\n\tint run, result;\n\tint item = ARRAY_SIZE(sizes);": "static int check_child_memory_mapping(int mem_type, int mode, int mapping)\n{\n\tchar *ptr;\n\tint run, result;\n\tint item = ARRAY_SIZE(sizes);\n\n\titem = ARRAY_SIZE(sizes);\n\tmte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG);\n\tfor (run = 0; run < item; run++) {\n\t\tptr = (char *)mte_allocate_memory_tag_range(sizes[run], mem_type, mapping,\n\t\t\t\t\t\t\t    UNDERFLOW, OVERFLOW);\n\t\tif (check_allocated_memory_range(ptr, sizes[run], mem_type,\n\t\t\t\t\t\t UNDERFLOW, OVERFLOW) != KSFT_PASS)\n\t\t\treturn KSFT_FAIL;\n\t\tresult = check_child_tag_inheritance(ptr, sizes[run], mode);\n\t\tmte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, OVERFLOW);\n\t\tif (result == KSFT_FAIL)\n\t\t\treturn result;\n\t}\n\treturn KSFT_PASS;\n}",
        "static inline void forward_timer_base(struct timer_base *base)\n{\n\tunsigned long jnow = READ_ONCE(jiffies);\n\n\t/*": "static inline void forward_timer_base(struct timer_base *base)\n{\n\tunsigned long jnow = READ_ONCE(jiffies);\n\n\t/*\n\t * No need to forward if we are close enough below jiffies.\n\t * Also while executing timers, base->clk is 1 offset ahead\n\t * of jiffies to avoid endless requeuing to current jiffies.\n\t */\n\tif ((long)(jnow - base->clk) < 1)\n\t\treturn;\n\n\t/*\n\t * If the next expiry value is > jiffies, then we fast forward to\n\t * jiffies otherwise we forward to the next expiry value.\n\t */\n\tif (time_after(base->next_expiry, jnow)) {\n\t\tbase->clk = jnow;\n\t} else {\n\t\tif (WARN_ON_ONCE(time_before(base->next_expiry, base->clk)))\n\t\t\treturn;\n\t\tbase->clk = base->next_expiry;\n\t}\n}",
        "static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8125a_2[] = {\n\t\t{ 0x04, 0xffff, 0xd000 },\n\t\t{ 0x0a, 0xffff, 0x8653 },": "static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8125a_2[] = {\n\t\t{ 0x04, 0xffff, 0xd000 },\n\t\t{ 0x0a, 0xffff, 0x8653 },\n\t\t{ 0x23, 0xffff, 0xab66 },\n\t\t{ 0x20, 0xffff, 0x9455 },\n\t\t{ 0x21, 0xffff, 0x99ff },\n\t\t{ 0x29, 0xffff, 0xfe04 },\n\n\t\t{ 0x44, 0xffff, 0xd000 },\n\t\t{ 0x4a, 0xffff, 0x8653 },\n\t\t{ 0x63, 0xffff, 0xab66 },\n\t\t{ 0x60, 0xffff, 0x9455 },\n\t\t{ 0x61, 0xffff, 0x99ff },\n\t\t{ 0x69, 0xffff, 0xfe04 },\n\t};\n\n\trtl_set_def_aspm_entry_latency(tp);\n\n\t/* disable aspm and clock request before access ephy */\n\trtl_hw_aspm_clkreq_enable(tp, false);\n\trtl_ephy_init(tp, e_info_8125a_2);\n\n\trtl_hw_start_8125_common(tp);\n\trtl_hw_aspm_clkreq_enable(tp, true);\n}",
        "static void sc_generate_ltk(struct smp_chan *smp)\n{\n\t/* From core spec. Spells out in ASCII as 'brle'. */\n\tconst u8 brle[4] = { 0x65, 0x6c, 0x72, 0x62 };\n\tstruct hci_conn *hcon = smp->conn->hcon;": "static void sc_generate_ltk(struct smp_chan *smp)\n{\n\t/* From core spec. Spells out in ASCII as 'brle'. */\n\tconst u8 brle[4] = { 0x65, 0x6c, 0x72, 0x62 };\n\tstruct hci_conn *hcon = smp->conn->hcon;\n\tstruct hci_dev *hdev = hcon->hdev;\n\tstruct link_key *key;\n\n\tkey = hci_find_link_key(hdev, &hcon->dst);\n\tif (!key) {\n\t\tbt_dev_err(hdev, \"no Link Key found to generate LTK\");\n\t\treturn;\n\t}\n\n\tif (key->type == HCI_LK_DEBUG_COMBINATION)\n\t\tset_bit(SMP_FLAG_DEBUG_KEY, &smp->flags);\n\n\tif (test_bit(SMP_FLAG_CT2, &smp->flags)) {\n\t\t/* SALT = 0x000000000000000000000000746D7032 */\n\t\tconst u8 salt[16] = { 0x32, 0x70, 0x6d, 0x74 };\n\n\t\tif (smp_h7(smp->tfm_cmac, key->val, salt, smp->tk))\n\t\t\treturn;\n\t} else {\n\t\t/* From core spec. Spells out in ASCII as 'tmp2'. */\n\t\tconst u8 tmp2[4] = { 0x32, 0x70, 0x6d, 0x74 };\n\n\t\tif (smp_h6(smp->tfm_cmac, key->val, tmp2, smp->tk))\n\t\t\treturn;\n\t}\n\n\tif (smp_h6(smp->tfm_cmac, smp->tk, brle, smp->tk))\n\t\treturn;\n\n\tsc_add_ltk(smp);\n}",
        "static int btfgen_record_field_relo(struct btfgen_info *info, struct bpf_core_spec *targ_spec)\n{\n\tstruct btf *btf = info->src_btf;\n\tconst struct btf_type *btf_type;\n\tstruct btf_member *btf_member;": "static int btfgen_record_field_relo(struct btfgen_info *info, struct bpf_core_spec *targ_spec)\n{\n\tstruct btf *btf = info->src_btf;\n\tconst struct btf_type *btf_type;\n\tstruct btf_member *btf_member;\n\tstruct btf_array *array;\n\tunsigned int type_id = targ_spec->root_type_id;\n\tint idx, err;\n\n\t/* mark root type */\n\tbtf_type = btf__type_by_id(btf, type_id);\n\terr = btfgen_mark_type(info, type_id, false);\n\tif (err)\n\t\treturn err;\n\n\t/* mark types for complex types (arrays, unions, structures) */\n\tfor (int i = 1; i < targ_spec->raw_len; i++) {\n\t\t/* skip typedefs and mods */\n\t\twhile (btf_is_mod(btf_type) || btf_is_typedef(btf_type)) {\n\t\t\ttype_id = btf_type->type;\n\t\t\tbtf_type = btf__type_by_id(btf, type_id);\n\t\t}\n\n\t\tswitch (btf_kind(btf_type)) {\n\t\tcase BTF_KIND_STRUCT:\n\t\tcase BTF_KIND_UNION:\n\t\t\tidx = targ_spec->raw_spec[i];\n\t\t\tbtf_member = btf_members(btf_type) + idx;\n\n\t\t\t/* mark member */\n\t\t\tbtfgen_mark_member(info, type_id, idx);\n\n\t\t\t/* mark member's type */\n\t\t\ttype_id = btf_member->type;\n\t\t\tbtf_type = btf__type_by_id(btf, type_id);\n\t\t\terr = btfgen_mark_type(info, type_id, false);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\tbreak;\n\t\tcase BTF_KIND_ARRAY:\n\t\t\tarray = btf_array(btf_type);\n\t\t\ttype_id = array->type;\n\t\t\tbtf_type = btf__type_by_id(btf, type_id);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tp_err(\"unsupported kind: %s (%d)\",\n\t\t\t      btf_kind_str(btf_type), btf_type->type);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id)\n{\n\tstruct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];\n\tsize_t size = evt_ring->ring.count * GSI_RING_ELEMENT_SIZE;\n\tu32 val;": "static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id)\n{\n\tstruct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];\n\tsize_t size = evt_ring->ring.count * GSI_RING_ELEMENT_SIZE;\n\tu32 val;\n\n\t/* We program all event rings as GPI type/protocol */\n\tval = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, EV_CHTYPE_FMASK);\n\tval |= EV_INTYPE_FMASK;\n\tval |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, EV_ELEMENT_SIZE_FMASK);\n\tiowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id));\n\n\tval = ev_r_length_encoded(gsi->version, size);\n\tiowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_1_OFFSET(evt_ring_id));\n\n\t/* The context 2 and 3 registers store the low-order and\n\t * high-order 32 bits of the address of the event ring,\n\t * respectively.\n\t */\n\tval = lower_32_bits(evt_ring->ring.addr);\n\tiowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_2_OFFSET(evt_ring_id));\n\tval = upper_32_bits(evt_ring->ring.addr);\n\tiowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_3_OFFSET(evt_ring_id));\n\n\t/* Enable interrupt moderation by setting the moderation delay */\n\tval = u32_encode_bits(GSI_EVT_RING_INT_MODT, MODT_FMASK);\n\tval |= u32_encode_bits(1, MODC_FMASK);\t/* comes from channel */\n\tiowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_8_OFFSET(evt_ring_id));\n\n\t/* No MSI write data, and MSI address high and low address is 0 */\n\tiowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_9_OFFSET(evt_ring_id));\n\tiowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_10_OFFSET(evt_ring_id));\n\tiowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_11_OFFSET(evt_ring_id));\n\n\t/* We don't need to get event read pointer updates */\n\tiowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_12_OFFSET(evt_ring_id));\n\tiowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_13_OFFSET(evt_ring_id));\n\n\t/* Finally, tell the hardware we've completed event 0 (arbitrary) */\n\tgsi_evt_ring_doorbell(gsi, evt_ring_id, 0);\n}",
        "static inline void *alloc_rsttbl_from_idx(struct RESTART_TABLE **tbl, u32 vbo)\n{\n\tu32 off;\n\t__le32 *e;\n\tstruct RESTART_TABLE *rt = *tbl;": "static inline void *alloc_rsttbl_from_idx(struct RESTART_TABLE **tbl, u32 vbo)\n{\n\tu32 off;\n\t__le32 *e;\n\tstruct RESTART_TABLE *rt = *tbl;\n\tu32 bytes = bytes_per_rt(rt);\n\tu16 esize = le16_to_cpu(rt->size);\n\n\t/* If the entry is not the table, we will have to extend the table. */\n\tif (vbo >= bytes) {\n\t\t/*\n\t\t * Extend the size by computing the number of entries between\n\t\t * the existing size and the desired index and adding 1 to that.\n\t\t */\n\t\tu32 bytes2idx = vbo - bytes;\n\n\t\t/*\n\t\t * There should always be an integral number of entries\n\t\t * being added. Now extend the table.\n\t\t */\n\t\t*tbl = rt = extend_rsttbl(rt, bytes2idx / esize + 1, bytes);\n\t\tif (!rt)\n\t\t\treturn NULL;\n\t}\n\n\t/* See if the entry is already allocated, and just return if it is. */\n\te = Add2Ptr(rt, vbo);\n\n\tif (*e == RESTART_ENTRY_ALLOCATED_LE)\n\t\treturn e;\n\n\t/*\n\t * Walk through the table, looking for the entry we're\n\t * interested and the previous entry.\n\t */\n\toff = le32_to_cpu(rt->first_free);\n\te = Add2Ptr(rt, off);\n\n\tif (off == vbo) {\n\t\t/* this is a match */\n\t\trt->first_free = *e;\n\t\tgoto skip_looking;\n\t}\n\n\t/*\n\t * Need to walk through the list looking for the predecessor\n\t * of our entry.\n\t */\n\tfor (;;) {\n\t\t/* Remember the entry just found */\n\t\tu32 last_off = off;\n\t\t__le32 *last_e = e;\n\n\t\t/* Should never run of entries. */\n\n\t\t/* Lookup up the next entry the list. */\n\t\toff = le32_to_cpu(*last_e);\n\t\te = Add2Ptr(rt, off);\n\n\t\t/* If this is our match we are done. */\n\t\tif (off == vbo) {\n\t\t\t*last_e = *e;\n\n\t\t\t/*\n\t\t\t * If this was the last entry, we update that\n\t\t\t * table as well.\n\t\t\t */\n\t\t\tif (le32_to_cpu(rt->last_free) == off)\n\t\t\t\trt->last_free = cpu_to_le32(last_off);\n\t\t\tbreak;\n\t\t}\n\t}\n\nskip_looking:\n\t/* If the list is now empty, we fix the last_free as well. */\n\tif (!rt->first_free)\n\t\trt->last_free = 0;\n\n\t/* Zero this entry. */\n\tmemset(e, 0, esize);\n\t*e = RESTART_ENTRY_ALLOCATED_LE;\n\n\tle16_add_cpu(&rt->total, 1);\n\n\treturn e;\n}",
        "static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value)\n{\n\tstruct i2c_client *c = v4l2_get_subdevdata(sd);\n\tstruct mt9m114_device *dev = to_mt9m114_sensor(sd);\n\tint err;": "static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value)\n{\n\tstruct i2c_client *c = v4l2_get_subdevdata(sd);\n\tstruct mt9m114_device *dev = to_mt9m114_sensor(sd);\n\tint err;\n\t/* set for direct mode */\n\terr = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850);\n\tif (value) {\n\t\t/* enable H flip ctx A */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x01);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x01);\n\t\t/* ctx B */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x01);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x01);\n\n\t\terr += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE,\n\t\t\t\t\tMISENSOR_HFLIP_MASK, MISENSOR_FLIP_EN);\n\n\t\tdev->bpat = MT9M114_BPAT_GRGRBGBG;\n\t} else {\n\t\t/* disable H flip ctx A */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x00);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x00);\n\t\t/* ctx B */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x00);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x00);\n\n\t\terr += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE,\n\t\t\t\t\tMISENSOR_HFLIP_MASK, MISENSOR_FLIP_DIS);\n\n\t\tdev->bpat = MT9M114_BPAT_BGBGGRGR;\n\t}\n\n\terr += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06);\n\tudelay(10);\n\n\treturn !!err;\n}",
        "static int fan_get_status(u8 *status)\n{\n\tu8 s;\n\n\t/* TODO:": "static int fan_get_status(u8 *status)\n{\n\tu8 s;\n\n\t/* TODO:\n\t * Add TPACPI_FAN_RD_ACPI_FANS ? */\n\n\tswitch (fan_status_access_mode) {\n\tcase TPACPI_FAN_RD_ACPI_GFAN: {\n\t\t/* 570, 600e/x, 770e, 770x */\n\t\tint res;\n\n\t\tif (unlikely(!acpi_evalf(gfan_handle, &res, NULL, \"d\")))\n\t\t\treturn -EIO;\n\n\t\tif (likely(status))\n\t\t\t*status = res & 0x07;\n\n\t\tbreak;\n\t}\n\tcase TPACPI_FAN_RD_TPEC:\n\t\t/* all except 570, 600e/x, 770e, 770x */\n\t\tif (unlikely(!acpi_ec_read(fan_status_offset, &s)))\n\t\t\treturn -EIO;\n\n\t\tif (likely(status)) {\n\t\t\t*status = s;\n\t\t\tfan_quirk1_handle(status);\n\t\t}\n\n\t\tbreak;\n\n\tdefault:\n\t\treturn -ENXIO;\n\t}\n\n\treturn 0;\n}",
        "static void revoke_iomem(struct resource *res)\n{\n\t/* pairs with smp_store_release() in iomem_init_inode() */\n\tstruct inode *inode = smp_load_acquire(&iomem_inode);\n": "static void revoke_iomem(struct resource *res)\n{\n\t/* pairs with smp_store_release() in iomem_init_inode() */\n\tstruct inode *inode = smp_load_acquire(&iomem_inode);\n\n\t/*\n\t * Check that the initialization has completed. Losing the race\n\t * is ok because it means drivers are claiming resources before\n\t * the fs_initcall level of init and prevent iomem_get_mapping users\n\t * from establishing mappings.\n\t */\n\tif (!inode)\n\t\treturn;\n\n\t/*\n\t * The expectation is that the driver has successfully marked\n\t * the resource busy by this point, so devmem_is_allowed()\n\t * should start returning false, however for performance this\n\t * does not iterate the entire resource range.\n\t */\n\tif (devmem_is_allowed(PHYS_PFN(res->start)) &&\n\t    devmem_is_allowed(PHYS_PFN(res->end))) {\n\t\t/*\n\t\t * *cringe* iomem=relaxed says \"go ahead, what's the\n\t\t * worst that can happen?\"\n\t\t */\n\t\treturn;\n\t}\n\n\tunmap_mapping_range(inode->i_mapping, res->start, resource_size(res), 1);\n}",
        "static void t7xx_cldma_irq_work_cb(struct cldma_ctrl *md_ctrl)\n{\n\tunsigned long l2_tx_int_msk, l2_rx_int_msk, l2_tx_int, l2_rx_int, val;\n\tstruct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;\n\tint i;": "static void t7xx_cldma_irq_work_cb(struct cldma_ctrl *md_ctrl)\n{\n\tunsigned long l2_tx_int_msk, l2_rx_int_msk, l2_tx_int, l2_rx_int, val;\n\tstruct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info;\n\tint i;\n\n\t/* L2 raw interrupt status */\n\tl2_tx_int = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);\n\tl2_rx_int = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);\n\tl2_tx_int_msk = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TIMR0);\n\tl2_rx_int_msk = ioread32(hw_info->ap_ao_base + REG_CLDMA_L2RIMR0);\n\tl2_tx_int &= ~l2_tx_int_msk;\n\tl2_rx_int &= ~l2_rx_int_msk;\n\n\tif (l2_tx_int) {\n\t\tif (l2_tx_int & (TQ_ERR_INT_BITMASK | TQ_ACTIVE_START_ERR_INT_BITMASK)) {\n\t\t\t/* Read and clear L3 TX interrupt status */\n\t\t\tval = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3TISAR0);\n\t\t\tiowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3TISAR0);\n\t\t\tval = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3TISAR1);\n\t\t\tiowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3TISAR1);\n\t\t}\n\n\t\tt7xx_cldma_hw_tx_done(hw_info, l2_tx_int);\n\t\tif (l2_tx_int & (TXRX_STATUS_BITMASK | EMPTY_STATUS_BITMASK)) {\n\t\t\tfor_each_set_bit(i, &l2_tx_int, L2_INT_BIT_COUNT) {\n\t\t\t\tif (i < CLDMA_TXQ_NUM) {\n\t\t\t\t\tpm_runtime_get(md_ctrl->dev);\n\t\t\t\t\tt7xx_cldma_hw_irq_dis_eq(hw_info, i, MTK_TX);\n\t\t\t\t\tt7xx_cldma_hw_irq_dis_txrx(hw_info, i, MTK_TX);\n\t\t\t\t\tqueue_work(md_ctrl->txq[i].worker,\n\t\t\t\t\t\t   &md_ctrl->txq[i].cldma_work);\n\t\t\t\t} else {\n\t\t\t\t\tt7xx_cldma_txq_empty_hndl(&md_ctrl->txq[i - CLDMA_TXQ_NUM]);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tif (l2_rx_int) {\n\t\tif (l2_rx_int & (RQ_ERR_INT_BITMASK | RQ_ACTIVE_START_ERR_INT_BITMASK)) {\n\t\t\t/* Read and clear L3 RX interrupt status */\n\t\t\tval = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3RISAR0);\n\t\t\tiowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3RISAR0);\n\t\t\tval = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3RISAR1);\n\t\t\tiowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3RISAR1);\n\t\t}\n\n\t\tt7xx_cldma_hw_rx_done(hw_info, l2_rx_int);\n\t\tif (l2_rx_int & (TXRX_STATUS_BITMASK | EMPTY_STATUS_BITMASK)) {\n\t\t\tl2_rx_int |= l2_rx_int >> CLDMA_RXQ_NUM;\n\t\t\tfor_each_set_bit(i, &l2_rx_int, CLDMA_RXQ_NUM) {\n\t\t\t\tpm_runtime_get(md_ctrl->dev);\n\t\t\t\tt7xx_cldma_hw_irq_dis_eq(hw_info, i, MTK_RX);\n\t\t\t\tt7xx_cldma_hw_irq_dis_txrx(hw_info, i, MTK_RX);\n\t\t\t\tqueue_work(md_ctrl->rxq[i].worker, &md_ctrl->rxq[i].cldma_work);\n\t\t\t}\n\t\t}\n\t}\n}",
        "static void _rtl92e_dm_check_fsync(struct net_device *dev)\n{\n#define\tRegC38_Default\t\t\t0\n#define\tRegC38_NonFsync_Other_AP\t1\n#define\tRegC38_Fsync_AP_BCM\t\t2": "static void _rtl92e_dm_check_fsync(struct net_device *dev)\n{\n#define\tRegC38_Default\t\t\t0\n#define\tRegC38_NonFsync_Other_AP\t1\n#define\tRegC38_Fsync_AP_BCM\t\t2\n\tstruct r8192_priv *priv = rtllib_priv(dev);\n\tstatic u8 reg_c38_State = RegC38_Default;\n\tstatic u32 reset_cnt;\n\n\tRT_TRACE(COMP_HALDM,\n\t\t \"RSSI %d TimeInterval %d MultipleTimeInterval %d\\n\",\n\t\t priv->rtllib->fsync_rssi_threshold,\n\t\t priv->rtllib->fsync_time_interval,\n\t\t priv->rtllib->fsync_multiple_timeinterval);\n\tRT_TRACE(COMP_HALDM,\n\t\t \"RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\\n\",\n\t\t priv->rtllib->fsync_rate_bitmap,\n\t\t priv->rtllib->fsync_firstdiff_ratethreshold,\n\t\t priv->rtllib->fsync_seconddiff_ratethreshold);\n\n\tif (priv->rtllib->state == RTLLIB_LINKED &&\n\t    priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {\n\t\tif (priv->rtllib->bfsync_enable == 0) {\n\t\t\tswitch (priv->rtllib->fsync_state) {\n\t\t\tcase Default_Fsync:\n\t\t\t\t_rtl92e_dm_start_hw_fsync(dev);\n\t\t\t\tpriv->rtllib->fsync_state = HW_Fsync;\n\t\t\t\tbreak;\n\t\t\tcase SW_Fsync:\n\t\t\t\t_rtl92e_dm_end_sw_fsync(dev);\n\t\t\t\t_rtl92e_dm_start_hw_fsync(dev);\n\t\t\t\tpriv->rtllib->fsync_state = HW_Fsync;\n\t\t\t\tbreak;\n\t\t\tcase HW_Fsync:\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\tswitch (priv->rtllib->fsync_state) {\n\t\t\tcase Default_Fsync:\n\t\t\t\t_rtl92e_dm_start_sw_fsync(dev);\n\t\t\t\tpriv->rtllib->fsync_state = SW_Fsync;\n\t\t\t\tbreak;\n\t\t\tcase HW_Fsync:\n\t\t\t\t_rtl92e_dm_end_hw_fsync(dev);\n\t\t\t\t_rtl92e_dm_start_sw_fsync(dev);\n\t\t\t\tpriv->rtllib->fsync_state = SW_Fsync;\n\t\t\t\tbreak;\n\t\t\tcase SW_Fsync:\n\t\t\tdefault:\n\t\t\t\tbreak;\n\n\t\t\t}\n\t\t}\n\t\tif (priv->framesyncMonitor) {\n\t\t\tif (reg_c38_State != RegC38_Fsync_AP_BCM) {\n\t\t\t\trtl92e_writeb(dev, rOFDM0_RxDetector3, 0x95);\n\n\t\t\t\treg_c38_State = RegC38_Fsync_AP_BCM;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tswitch (priv->rtllib->fsync_state) {\n\t\tcase HW_Fsync:\n\t\t\t_rtl92e_dm_end_hw_fsync(dev);\n\t\t\tpriv->rtllib->fsync_state = Default_Fsync;\n\t\t\tbreak;\n\t\tcase SW_Fsync:\n\t\t\t_rtl92e_dm_end_sw_fsync(dev);\n\t\t\tpriv->rtllib->fsync_state = Default_Fsync;\n\t\t\tbreak;\n\t\tcase Default_Fsync:\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tif (priv->framesyncMonitor) {\n\t\t\tif (priv->rtllib->state == RTLLIB_LINKED) {\n\t\t\t\tif (priv->undecorated_smoothed_pwdb <=\n\t\t\t\t    RegC38_TH) {\n\t\t\t\t\tif (reg_c38_State !=\n\t\t\t\t\t    RegC38_NonFsync_Other_AP) {\n\t\t\t\t\t\trtl92e_writeb(dev,\n\t\t\t\t\t\t\t      rOFDM0_RxDetector3,\n\t\t\t\t\t\t\t      0x90);\n\n\t\t\t\t\t\treg_c38_State =\n\t\t\t\t\t\t     RegC38_NonFsync_Other_AP;\n\t\t\t\t\t}\n\t\t\t\t} else if (priv->undecorated_smoothed_pwdb >=\n\t\t\t\t\t   (RegC38_TH+5)) {\n\t\t\t\t\tif (reg_c38_State) {\n\t\t\t\t\t\trtl92e_writeb(dev,\n\t\t\t\t\t\t\trOFDM0_RxDetector3,\n\t\t\t\t\t\t\tpriv->framesync);\n\t\t\t\t\t\treg_c38_State = RegC38_Default;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (reg_c38_State) {\n\t\t\t\t\trtl92e_writeb(dev, rOFDM0_RxDetector3,\n\t\t\t\t\t\t      priv->framesync);\n\t\t\t\t\treg_c38_State = RegC38_Default;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tif (priv->framesyncMonitor) {\n\t\tif (priv->reset_count != reset_cnt) {\n\t\t\trtl92e_writeb(dev, rOFDM0_RxDetector3,\n\t\t\t\t       priv->framesync);\n\t\t\treg_c38_State = RegC38_Default;\n\t\t\treset_cnt = priv->reset_count;\n\t\t}\n\t} else {\n\t\tif (reg_c38_State) {\n\t\t\trtl92e_writeb(dev, rOFDM0_RxDetector3,\n\t\t\t\t       priv->framesync);\n\t\t\treg_c38_State = RegC38_Default;\n\t\t}\n\t}\n}",
        "static void update_fans_speed (struct thermostat *th)\n{\n\tint lastvar = 0; /* last variation, for iBook */\n\tint i = 0;\n": "static void update_fans_speed (struct thermostat *th)\n{\n\tint lastvar = 0; /* last variation, for iBook */\n\tint i = 0;\n\n\t/* we don't care about local sensor, so we start at sensor 1 */\n\tfor (i = 1; i < 3; i++) {\n\t\tbool started = false;\n\t\tint fan_number = (th->type == ADT7460 && i == 2);\n\t\tint var = th->temps[i] - th->limits[i];\n\n\t\tif (var > -1) {\n\t\t\tint step = (255 - fan_speed) / 7;\n\t\t\tint new_speed = 0;\n\n\t\t\t/* hysteresis : change fan speed only if variation is\n\t\t\t * more than two degrees */\n\t\t\tif (abs(var - th->last_var[fan_number]) < 2)\n\t\t\t\tcontinue;\n\n\t\t\tstarted = true;\n\t\t\tnew_speed = fan_speed + ((var-1)*step);\n\n\t\t\tif (new_speed < fan_speed)\n\t\t\t\tnew_speed = fan_speed;\n\t\t\tif (new_speed > 255)\n\t\t\t\tnew_speed = 255;\n\n\t\t\tif (verbose)\n\t\t\t\tprintk(KERN_DEBUG \"adt746x: Setting fans speed to %d \"\n\t\t\t\t\t\t \"(limit exceeded by %d on %s)\\n\",\n\t\t\t\t\t\tnew_speed, var,\n\t\t\t\t\t\tsensor_location[fan_number+1]);\n\t\t\twrite_both_fan_speed(th, new_speed);\n\t\t\tth->last_var[fan_number] = var;\n\t\t} else if (var < -2) {\n\t\t\t/* don't stop fan if sensor2 is cold and sensor1 is not\n\t\t\t * so cold (lastvar >= -1) */\n\t\t\tif (i == 2 && lastvar < -1) {\n\t\t\t\tif (th->last_speed[fan_number] != 0)\n\t\t\t\t\tif (verbose)\n\t\t\t\t\t\tprintk(KERN_DEBUG \"adt746x: Stopping \"\n\t\t\t\t\t\t\t\"fans.\\n\");\n\t\t\t\twrite_both_fan_speed(th, 0);\n\t\t\t}\n\t\t}\n\n\t\tlastvar = var;\n\n\t\tif (started)\n\t\t\treturn; /* we don't want to re-stop the fan\n\t\t\t\t* if sensor1 is heating and sensor2 is not */\n\t}\n}",
        "static void atmel_get_ip_name(struct uart_port *port)\n{\n\tstruct atmel_uart_port *atmel_port = to_atmel_uart_port(port);\n\tint name = atmel_uart_readl(port, ATMEL_US_NAME);\n\tu32 version;": "static void atmel_get_ip_name(struct uart_port *port)\n{\n\tstruct atmel_uart_port *atmel_port = to_atmel_uart_port(port);\n\tint name = atmel_uart_readl(port, ATMEL_US_NAME);\n\tu32 version;\n\tu32 usart, dbgu_uart, new_uart;\n\t/* ASCII decoding for IP version */\n\tusart = 0x55534152;\t/* USAR(T) */\n\tdbgu_uart = 0x44424755;\t/* DBGU */\n\tnew_uart = 0x55415254;\t/* UART */\n\n\t/*\n\t * Only USART devices from at91sam9260 SOC implement fractional\n\t * baudrate. It is available for all asynchronous modes, with the\n\t * following restriction: the sampling clock's duty cycle is not\n\t * constant.\n\t */\n\tatmel_port->has_frac_baudrate = false;\n\tatmel_port->has_hw_timer = false;\n\n\tif (name == new_uart) {\n\t\tdev_dbg(port->dev, \"Uart with hw timer\");\n\t\tatmel_port->has_hw_timer = true;\n\t\tatmel_port->rtor = ATMEL_UA_RTOR;\n\t} else if (name == usart) {\n\t\tdev_dbg(port->dev, \"Usart\\n\");\n\t\tatmel_port->has_frac_baudrate = true;\n\t\tatmel_port->has_hw_timer = true;\n\t\tatmel_port->rtor = ATMEL_US_RTOR;\n\t\tversion = atmel_uart_readl(port, ATMEL_US_VERSION);\n\t\tswitch (version) {\n\t\tcase 0x814:\t/* sama5d2 */\n\t\t\tfallthrough;\n\t\tcase 0x701:\t/* sama5d4 */\n\t\t\tatmel_port->fidi_min = 3;\n\t\t\tatmel_port->fidi_max = 65535;\n\t\t\tbreak;\n\t\tcase 0x502:\t/* sam9x5, sama5d3 */\n\t\t\tatmel_port->fidi_min = 3;\n\t\t\tatmel_port->fidi_max = 2047;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tatmel_port->fidi_min = 1;\n\t\t\tatmel_port->fidi_max = 2047;\n\t\t}\n\t} else if (name == dbgu_uart) {\n\t\tdev_dbg(port->dev, \"Dbgu or uart without hw timer\\n\");\n\t} else {\n\t\t/* fallback for older SoCs: use version field */\n\t\tversion = atmel_uart_readl(port, ATMEL_US_VERSION);\n\t\tswitch (version) {\n\t\tcase 0x302:\n\t\tcase 0x10213:\n\t\tcase 0x10302:\n\t\t\tdev_dbg(port->dev, \"This version is usart\\n\");\n\t\t\tatmel_port->has_frac_baudrate = true;\n\t\t\tatmel_port->has_hw_timer = true;\n\t\t\tatmel_port->rtor = ATMEL_US_RTOR;\n\t\t\tbreak;\n\t\tcase 0x203:\n\t\tcase 0x10202:\n\t\t\tdev_dbg(port->dev, \"This version is uart\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev_err(port->dev, \"Not supported ip name nor version, set to uart\\n\");\n\t\t}\n\t}\n}",
        "static int imgu_video_nodes_init(struct imgu_device *imgu)\n{\n\tstruct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES] = { NULL };\n\tstruct v4l2_rect *rects[IPU3_CSS_RECTS] = { NULL };\n\tstruct imgu_media_pipe *imgu_pipe;": "static int imgu_video_nodes_init(struct imgu_device *imgu)\n{\n\tstruct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES] = { NULL };\n\tstruct v4l2_rect *rects[IPU3_CSS_RECTS] = { NULL };\n\tstruct imgu_media_pipe *imgu_pipe;\n\tunsigned int i, j;\n\tint r;\n\n\timgu->buf_struct_size = sizeof(struct imgu_buffer);\n\n\tfor (j = 0; j < IMGU_MAX_PIPE_NUM; j++) {\n\t\timgu_pipe = &imgu->imgu_pipe[j];\n\n\t\tfor (i = 0; i < IMGU_NODE_NUM; i++) {\n\t\t\timgu_pipe->nodes[i].name = imgu_node_map[i].name;\n\t\t\timgu_pipe->nodes[i].output = i < IMGU_QUEUE_FIRST_INPUT;\n\t\t\timgu_pipe->nodes[i].enabled = false;\n\n\t\t\tif (i != IMGU_NODE_PARAMS && i != IMGU_NODE_STAT_3A)\n\t\t\t\tfmts[imgu_node_map[i].css_queue] =\n\t\t\t\t\t&imgu_pipe->nodes[i].vdev_fmt.fmt.pix_mp;\n\t\t\tatomic_set(&imgu_pipe->nodes[i].sequence, 0);\n\t\t}\n\t}\n\n\tr = imgu_v4l2_register(imgu);\n\tif (r)\n\t\treturn r;\n\n\t/* Set initial formats and initialize formats of video nodes */\n\tfor (j = 0; j < IMGU_MAX_PIPE_NUM; j++) {\n\t\timgu_pipe = &imgu->imgu_pipe[j];\n\n\t\trects[IPU3_CSS_RECT_EFFECTIVE] = &imgu_pipe->imgu_sd.rect.eff;\n\t\trects[IPU3_CSS_RECT_BDS] = &imgu_pipe->imgu_sd.rect.bds;\n\t\timgu_css_fmt_set(&imgu->css, fmts, rects, j);\n\n\t\t/* Pre-allocate dummy buffers */\n\t\tr = imgu_dummybufs_preallocate(imgu, j);\n\t\tif (r) {\n\t\t\tdev_err(&imgu->pci_dev->dev,\n\t\t\t\t\"failed to pre-allocate dummy buffers (%d)\", r);\n\t\t\tgoto out_cleanup;\n\t\t}\n\t}\n\n\treturn 0;\n\nout_cleanup:\n\timgu_video_nodes_exit(imgu);\n\n\treturn r;\n}",
        "static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)\n{\n\tint res = 0;\n\tstruct tg3_fiber_aneginfo aninfo;\n\tint status = ANEG_FAILED;": "static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)\n{\n\tint res = 0;\n\tstruct tg3_fiber_aneginfo aninfo;\n\tint status = ANEG_FAILED;\n\tunsigned int tick;\n\tu32 tmp;\n\n\ttw32_f(MAC_TX_AUTO_NEG, 0);\n\n\ttmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;\n\ttw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);\n\tudelay(40);\n\n\ttw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);\n\tudelay(40);\n\n\tmemset(&aninfo, 0, sizeof(aninfo));\n\taninfo.flags |= MR_AN_ENABLE;\n\taninfo.state = ANEG_STATE_UNKNOWN;\n\taninfo.cur_time = 0;\n\ttick = 0;\n\twhile (++tick < 195000) {\n\t\tstatus = tg3_fiber_aneg_smachine(tp, &aninfo);\n\t\tif (status == ANEG_DONE || status == ANEG_FAILED)\n\t\t\tbreak;\n\n\t\tudelay(1);\n\t}\n\n\ttp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;\n\ttw32_f(MAC_MODE, tp->mac_mode);\n\tudelay(40);\n\n\t*txflags = aninfo.txconfig;\n\t*rxflags = aninfo.flags;\n\n\tif (status == ANEG_DONE &&\n\t    (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |\n\t\t\t     MR_LP_ADV_FULL_DUPLEX)))\n\t\tres = 1;\n\n\treturn res;\n}",
        "static int serdes_init_niu_10g_serdes(struct niu *np)\n{\n\tstruct niu_link_config *lp = &np->link_config;\n\tu32 tx_cfg, rx_cfg, pll_cfg, pll_sts;\n\tint max_retry = 100;": "static int serdes_init_niu_10g_serdes(struct niu *np)\n{\n\tstruct niu_link_config *lp = &np->link_config;\n\tu32 tx_cfg, rx_cfg, pll_cfg, pll_sts;\n\tint max_retry = 100;\n\tu64 sig, mask, val;\n\tunsigned long i;\n\tint err;\n\n\ttx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);\n\trx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |\n\t\t  PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |\n\t\t  PLL_RX_CFG_EQ_LP_ADAPTIVE);\n\n\tif (lp->loopback_mode == LOOPBACK_PHY) {\n\t\tu16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;\n\n\t\tmdio_write(np, np->port, NIU_ESR2_DEV_ADDR,\n\t\t\t   ESR2_TI_PLL_TEST_CFG_L, test_cfg);\n\n\t\ttx_cfg |= PLL_TX_CFG_ENTEST;\n\t\trx_cfg |= PLL_RX_CFG_ENTEST;\n\t}\n\n\t/* Initialize PLL for 10G */\n\tpll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);\n\n\terr = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,\n\t\t\t ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);\n\tif (err) {\n\t\tnetdev_err(np->dev, \"NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\\n\",\n\t\t\t   np->port, __func__);\n\t\treturn err;\n\t}\n\n\tpll_sts = PLL_CFG_ENPLL;\n\n\terr = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,\n\t\t\t ESR2_TI_PLL_STS_L, pll_sts & 0xffff);\n\tif (err) {\n\t\tnetdev_err(np->dev, \"NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\\n\",\n\t\t\t   np->port, __func__);\n\t\treturn err;\n\t}\n\n\tudelay(200);\n\n\t/* Initialize all 4 lanes of the SERDES.  */\n\tfor (i = 0; i < 4; i++) {\n\t\terr = esr2_set_tx_cfg(np, i, tx_cfg);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tfor (i = 0; i < 4; i++) {\n\t\terr = esr2_set_rx_cfg(np, i, rx_cfg);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* check if serdes is ready */\n\n\tswitch (np->port) {\n\tcase 0:\n\t\tmask = ESR_INT_SIGNALS_P0_BITS;\n\t\tval = (ESR_INT_SRDY0_P0 |\n\t\t       ESR_INT_DET0_P0 |\n\t\t       ESR_INT_XSRDY_P0 |\n\t\t       ESR_INT_XDP_P0_CH3 |\n\t\t       ESR_INT_XDP_P0_CH2 |\n\t\t       ESR_INT_XDP_P0_CH1 |\n\t\t       ESR_INT_XDP_P0_CH0);\n\t\tbreak;\n\n\tcase 1:\n\t\tmask = ESR_INT_SIGNALS_P1_BITS;\n\t\tval = (ESR_INT_SRDY0_P1 |\n\t\t       ESR_INT_DET0_P1 |\n\t\t       ESR_INT_XSRDY_P1 |\n\t\t       ESR_INT_XDP_P1_CH3 |\n\t\t       ESR_INT_XDP_P1_CH2 |\n\t\t       ESR_INT_XDP_P1_CH1 |\n\t\t       ESR_INT_XDP_P1_CH0);\n\t\tbreak;\n\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\twhile (max_retry--) {\n\t\tsig = nr64(ESR_INT_SIGNALS);\n\t\tif ((sig & mask) == val)\n\t\t\tbreak;\n\n\t\tmdelay(500);\n\t}\n\n\tif ((sig & mask) != val) {\n\t\tpr_info(\"NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\\n\",\n\t\t\tnp->port, (int)(sig & mask), (int)val);\n\n\t\t/* 10G failed, try initializing at 1G */\n\t\terr = serdes_init_niu_1g_serdes(np);\n\t\tif (!err) {\n\t\t\tnp->flags &= ~NIU_FLAGS_10G;\n\t\t\tnp->mac_xcvr = MAC_XCVR_PCS;\n\t\t}  else {\n\t\t\tnetdev_err(np->dev, \"Port %u 10G/1G SERDES Link Failed\\n\",\n\t\t\t\t   np->port);\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int venus_boot_core(struct venus_hfi_device *hdev)\n{\n\tstruct device *dev = hdev->core->dev;\n\tstatic const unsigned int max_tries = 100;\n\tu32 ctrl_status = 0, mask_val;": "static int venus_boot_core(struct venus_hfi_device *hdev)\n{\n\tstruct device *dev = hdev->core->dev;\n\tstatic const unsigned int max_tries = 100;\n\tu32 ctrl_status = 0, mask_val;\n\tunsigned int count = 0;\n\tvoid __iomem *cpu_cs_base = hdev->core->cpu_cs_base;\n\tvoid __iomem *wrapper_base = hdev->core->wrapper_base;\n\tint ret = 0;\n\n\twritel(BIT(VIDC_CTRL_INIT_CTRL_SHIFT), cpu_cs_base + VIDC_CTRL_INIT);\n\tif (IS_V6(hdev->core)) {\n\t\tmask_val = readl(wrapper_base + WRAPPER_INTR_MASK);\n\t\tmask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BASK_V6 |\n\t\t\t      WRAPPER_INTR_MASK_A2HCPU_MASK);\n\t} else {\n\t\tmask_val = WRAPPER_INTR_MASK_A2HVCODEC_MASK;\n\t}\n\twritel(mask_val, wrapper_base + WRAPPER_INTR_MASK);\n\twritel(1, cpu_cs_base + CPU_CS_SCIACMDARG3);\n\n\twhile (!ctrl_status && count < max_tries) {\n\t\tctrl_status = readl(cpu_cs_base + CPU_CS_SCIACMDARG0);\n\t\tif ((ctrl_status & CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK) == 4) {\n\t\t\tdev_err(dev, \"invalid setting for UC_REGION\\n\");\n\t\t\tret = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\n\t\tusleep_range(500, 1000);\n\t\tcount++;\n\t}\n\n\tif (count >= max_tries)\n\t\tret = -ETIMEDOUT;\n\n\tif (IS_V6(hdev->core)) {\n\t\twritel(0x1, cpu_cs_base + CPU_CS_H2XSOFTINTEN_V6);\n\t\twritel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6);\n\t}\n\n\treturn ret;\n}",
        "static int bnxt_sriov_enable(struct bnxt *bp, int *num_vfs)\n{\n\tint rc = 0, vfs_supported;\n\tint min_rx_rings, min_tx_rings, min_rss_ctxs;\n\tstruct bnxt_hw_resc *hw_resc = &bp->hw_resc;": "static int bnxt_sriov_enable(struct bnxt *bp, int *num_vfs)\n{\n\tint rc = 0, vfs_supported;\n\tint min_rx_rings, min_tx_rings, min_rss_ctxs;\n\tstruct bnxt_hw_resc *hw_resc = &bp->hw_resc;\n\tint tx_ok = 0, rx_ok = 0, rss_ok = 0;\n\tint avail_cp, avail_stat;\n\n\t/* Check if we can enable requested num of vf's. At a mininum\n\t * we require 1 RX 1 TX rings for each VF. In this minimum conf\n\t * features like TPA will not be available.\n\t */\n\tvfs_supported = *num_vfs;\n\n\tavail_cp = bnxt_get_avail_cp_rings_for_en(bp);\n\tavail_stat = bnxt_get_avail_stat_ctxs_for_en(bp);\n\tavail_cp = min_t(int, avail_cp, avail_stat);\n\n\twhile (vfs_supported) {\n\t\tmin_rx_rings = vfs_supported;\n\t\tmin_tx_rings = vfs_supported;\n\t\tmin_rss_ctxs = vfs_supported;\n\n\t\tif (bp->flags & BNXT_FLAG_AGG_RINGS) {\n\t\t\tif (hw_resc->max_rx_rings - bp->rx_nr_rings * 2 >=\n\t\t\t    min_rx_rings)\n\t\t\t\trx_ok = 1;\n\t\t} else {\n\t\t\tif (hw_resc->max_rx_rings - bp->rx_nr_rings >=\n\t\t\t    min_rx_rings)\n\t\t\t\trx_ok = 1;\n\t\t}\n\t\tif (hw_resc->max_vnics - bp->nr_vnics < min_rx_rings ||\n\t\t    avail_cp < min_rx_rings)\n\t\t\trx_ok = 0;\n\n\t\tif (hw_resc->max_tx_rings - bp->tx_nr_rings >= min_tx_rings &&\n\t\t    avail_cp >= min_tx_rings)\n\t\t\ttx_ok = 1;\n\n\t\tif (hw_resc->max_rsscos_ctxs - bp->rsscos_nr_ctxs >=\n\t\t    min_rss_ctxs)\n\t\t\trss_ok = 1;\n\n\t\tif (tx_ok && rx_ok && rss_ok)\n\t\t\tbreak;\n\n\t\tvfs_supported--;\n\t}\n\n\tif (!vfs_supported) {\n\t\tnetdev_err(bp->dev, \"Cannot enable VF's as all resources are used by PF\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (vfs_supported != *num_vfs) {\n\t\tnetdev_info(bp->dev, \"Requested VFs %d, can enable %d\\n\",\n\t\t\t    *num_vfs, vfs_supported);\n\t\t*num_vfs = vfs_supported;\n\t}\n\n\trc = bnxt_alloc_vf_resources(bp, *num_vfs);\n\tif (rc)\n\t\tgoto err_out1;\n\n\trc = bnxt_cfg_hw_sriov(bp, num_vfs, false);\n\tif (rc)\n\t\tgoto err_out2;\n\n\trc = pci_enable_sriov(bp->pdev, *num_vfs);\n\tif (rc)\n\t\tgoto err_out2;\n\n\treturn 0;\n\nerr_out2:\n\t/* Free the resources reserved for various VF's */\n\tbnxt_hwrm_func_vf_resource_free(bp, *num_vfs);\n\nerr_out1:\n\tbnxt_free_vf_resources(bp);\n\n\treturn rc;\n}",
        "static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)\n{\n\tif (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {\n\t\t/* Unsolicited RESET_COMP or RESET_RECEIVED */\n\t\topcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;": "static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)\n{\n\tif (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {\n\t\t/* Unsolicited RESET_COMP or RESET_RECEIVED */\n\t\topcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;\n\t\tcsk->state = opcode;\n\t}\n\n\t/* 1. If event opcode matches the expected event in csk->state\n\t * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any\n\t *    event\n\t * 3. If the expected event is 0, meaning the connection was never\n\t *    never established, we accept the opcode from cm_abort.\n\t */\n\tif (opcode == csk->state || csk->state == 0 ||\n\t    csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||\n\t    csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {\n\t\tif (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {\n\t\t\tif (csk->state == 0)\n\t\t\t\tcsk->state = opcode;\n\t\t\treturn 1;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static bool svc_xprt_ready(struct svc_xprt *xprt)\n{\n\tunsigned long xpt_flags;\n\n\t/*": "static bool svc_xprt_ready(struct svc_xprt *xprt)\n{\n\tunsigned long xpt_flags;\n\n\t/*\n\t * If another cpu has recently updated xpt_flags,\n\t * sk_sock->flags, xpt_reserved, or xpt_nr_rqsts, we need to\n\t * know about it; otherwise it's possible that both that cpu and\n\t * this one could call svc_xprt_enqueue() without either\n\t * svc_xprt_enqueue() recognizing that the conditions below\n\t * are satisfied, and we could stall indefinitely:\n\t */\n\tsmp_rmb();\n\txpt_flags = READ_ONCE(xprt->xpt_flags);\n\n\tif (xpt_flags & BIT(XPT_BUSY))\n\t\treturn false;\n\tif (xpt_flags & (BIT(XPT_CONN) | BIT(XPT_CLOSE)))\n\t\treturn true;\n\tif (xpt_flags & (BIT(XPT_DATA) | BIT(XPT_DEFERRED))) {\n\t\tif (xprt->xpt_ops->xpo_has_wspace(xprt) &&\n\t\t    svc_xprt_slots_in_range(xprt))\n\t\t\treturn true;\n\t\ttrace_svc_xprt_no_write_space(xprt);\n\t\treturn false;\n\t}\n\treturn false;\n}",
        "static void test_xdp_bonding_redirect_multi(struct skeletons *skeletons)\n{\n\tstatic const char * const ifaces[] = {\"bond2\", \"veth2_1\", \"veth2_2\"};\n\tint veth1_1_rx, veth1_2_rx;\n\tint err;": "static void test_xdp_bonding_redirect_multi(struct skeletons *skeletons)\n{\n\tstatic const char * const ifaces[] = {\"bond2\", \"veth2_1\", \"veth2_2\"};\n\tint veth1_1_rx, veth1_2_rx;\n\tint err;\n\n\tif (bonding_setup(skeletons, BOND_MODE_ROUNDROBIN, BOND_XMIT_POLICY_LAYER23,\n\t\t\t  BOND_ONE_NO_ATTACH))\n\t\tgoto out;\n\n\n\tif (!ASSERT_OK(setns_by_name(\"ns_dst\"), \"could not set netns to ns_dst\"))\n\t\tgoto out;\n\n\t/* populate the devmap with the relevant interfaces */\n\tfor (int i = 0; i < ARRAY_SIZE(ifaces); i++) {\n\t\tint ifindex = if_nametoindex(ifaces[i]);\n\t\tint map_fd = bpf_map__fd(skeletons->xdp_redirect_multi_kern->maps.map_all);\n\n\t\tif (!ASSERT_GT(ifindex, 0, \"could not get interface index\"))\n\t\t\tgoto out;\n\n\t\terr = bpf_map_update_elem(map_fd, &ifindex, &ifindex, 0);\n\t\tif (!ASSERT_OK(err, \"add interface to map_all\"))\n\t\t\tgoto out;\n\t}\n\n\tif (xdp_attach(skeletons,\n\t\t       skeletons->xdp_redirect_multi_kern->progs.xdp_redirect_map_multi_prog,\n\t\t       \"bond2\"))\n\t\tgoto out;\n\n\trestore_root_netns();\n\n\tif (send_udp_packets(BOND_MODE_ROUNDROBIN))\n\t\tgoto out;\n\n\tveth1_1_rx = get_rx_packets(\"veth1_1\");\n\tveth1_2_rx = get_rx_packets(\"veth1_2\");\n\n\tASSERT_EQ(veth1_1_rx, 0, \"expected no packets on veth1_1\");\n\tASSERT_GE(veth1_2_rx, NPACKETS, \"expected packets on veth1_2\");\n\nout:\n\trestore_root_netns();\n\tbonding_cleanup(skeletons);\n}",
        "static void gdb_cmd_query(struct kgdb_state *ks)\n{\n\tstruct task_struct *g;\n\tstruct task_struct *p;\n\tunsigned char thref[BUF_THREAD_ID_SIZE];": "static void gdb_cmd_query(struct kgdb_state *ks)\n{\n\tstruct task_struct *g;\n\tstruct task_struct *p;\n\tunsigned char thref[BUF_THREAD_ID_SIZE];\n\tchar *ptr;\n\tint i;\n\tint cpu;\n\tint finished = 0;\n\n\tswitch (remcom_in_buffer[1]) {\n\tcase 's':\n\tcase 'f':\n\t\tif (memcmp(remcom_in_buffer + 2, \"ThreadInfo\", 10))\n\t\t\tbreak;\n\n\t\ti = 0;\n\t\tremcom_out_buffer[0] = 'm';\n\t\tptr = remcom_out_buffer + 1;\n\t\tif (remcom_in_buffer[1] == 'f') {\n\t\t\t/* Each cpu is a shadow thread */\n\t\t\tfor_each_online_cpu(cpu) {\n\t\t\t\tks->thr_query = 0;\n\t\t\t\tint_to_threadref(thref, -cpu - 2);\n\t\t\t\tptr = pack_threadid(ptr, thref);\n\t\t\t\t*(ptr++) = ',';\n\t\t\t\ti++;\n\t\t\t}\n\t\t}\n\n\t\tfor_each_process_thread(g, p) {\n\t\t\tif (i >= ks->thr_query && !finished) {\n\t\t\t\tint_to_threadref(thref, p->pid);\n\t\t\t\tptr = pack_threadid(ptr, thref);\n\t\t\t\t*(ptr++) = ',';\n\t\t\t\tks->thr_query++;\n\t\t\t\tif (ks->thr_query % KGDB_MAX_THREAD_QUERY == 0)\n\t\t\t\t\tfinished = 1;\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\n\t\t*(--ptr) = '\\0';\n\t\tbreak;\n\n\tcase 'C':\n\t\t/* Current thread id */\n\t\tstrcpy(remcom_out_buffer, \"QC\");\n\t\tks->threadid = shadow_pid(current->pid);\n\t\tint_to_threadref(thref, ks->threadid);\n\t\tpack_threadid(remcom_out_buffer + 2, thref);\n\t\tbreak;\n\tcase 'T':\n\t\tif (memcmp(remcom_in_buffer + 1, \"ThreadExtraInfo,\", 16))\n\t\t\tbreak;\n\n\t\tks->threadid = 0;\n\t\tptr = remcom_in_buffer + 17;\n\t\tkgdb_hex2long(&ptr, &ks->threadid);\n\t\tif (!getthread(ks->linux_regs, ks->threadid)) {\n\t\t\terror_packet(remcom_out_buffer, -EINVAL);\n\t\t\tbreak;\n\t\t}\n\t\tif ((int)ks->threadid > 0) {\n\t\t\tkgdb_mem2hex(getthread(ks->linux_regs,\n\t\t\t\t\tks->threadid)->comm,\n\t\t\t\t\tremcom_out_buffer, 16);\n\t\t} else {\n\t\t\tstatic char tmpstr[23 + BUF_THREAD_ID_SIZE];\n\n\t\t\tsprintf(tmpstr, \"shadowCPU%d\",\n\t\t\t\t\t(int)(-ks->threadid - 2));\n\t\t\tkgdb_mem2hex(tmpstr, remcom_out_buffer, strlen(tmpstr));\n\t\t}\n\t\tbreak;\n#ifdef CONFIG_KGDB_KDB\n\tcase 'R':\n\t\tif (strncmp(remcom_in_buffer, \"qRcmd,\", 6) == 0) {\n\t\t\tint len = strlen(remcom_in_buffer + 6);\n\n\t\t\tif ((len % 2) != 0) {\n\t\t\t\tstrcpy(remcom_out_buffer, \"E01\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tkgdb_hex2mem(remcom_in_buffer + 6,\n\t\t\t\t     remcom_out_buffer, len);\n\t\t\tlen = len / 2;\n\t\t\tremcom_out_buffer[len++] = 0;\n\n\t\t\tkdb_common_init_state(ks);\n\t\t\tkdb_parse(remcom_out_buffer);\n\t\t\tkdb_common_deinit_state();\n\n\t\t\tstrcpy(remcom_out_buffer, \"OK\");\n\t\t}\n\t\tbreak;\n#endif\n#ifdef CONFIG_HAVE_ARCH_KGDB_QXFER_PKT\n\tcase 'S':\n\t\tif (!strncmp(remcom_in_buffer, \"qSupported:\", 11))\n\t\t\tstrcpy(remcom_out_buffer, kgdb_arch_gdb_stub_feature);\n\t\tbreak;\n\tcase 'X':\n\t\tif (!strncmp(remcom_in_buffer, \"qXfer:\", 6))\n\t\t\tkgdb_arch_handle_qxfer_pkt(remcom_in_buffer,\n\t\t\t\t\t\t   remcom_out_buffer);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbreak;\n\t}\n}",
        "static int alauda_read_map(struct us_data *us, unsigned int zone)\n{\n\tunsigned char *data = us->iobuf;\n\tint result;\n\tint i, j;": "static int alauda_read_map(struct us_data *us, unsigned int zone)\n{\n\tunsigned char *data = us->iobuf;\n\tint result;\n\tint i, j;\n\tunsigned int zonesize = MEDIA_INFO(us).zonesize;\n\tunsigned int uzonesize = MEDIA_INFO(us).uzonesize;\n\tunsigned int lba_offset, lba_real, blocknum;\n\tunsigned int zone_base_lba = zone * uzonesize;\n\tunsigned int zone_base_pba = zone * zonesize;\n\tu16 *lba_to_pba = kcalloc(zonesize, sizeof(u16), GFP_NOIO);\n\tu16 *pba_to_lba = kcalloc(zonesize, sizeof(u16), GFP_NOIO);\n\tif (lba_to_pba == NULL || pba_to_lba == NULL) {\n\t\tresult = USB_STOR_TRANSPORT_ERROR;\n\t\tgoto error;\n\t}\n\n\tusb_stor_dbg(us, \"Mapping blocks for zone %d\\n\", zone);\n\n\t/* 1024 PBA's per zone */\n\tfor (i = 0; i < zonesize; i++)\n\t\tlba_to_pba[i] = pba_to_lba[i] = UNDEF;\n\n\tfor (i = 0; i < zonesize; i++) {\n\t\tblocknum = zone_base_pba + i;\n\n\t\tresult = alauda_get_redu_data(us, blocknum, data);\n\t\tif (result != USB_STOR_XFER_GOOD) {\n\t\t\tresult = USB_STOR_TRANSPORT_ERROR;\n\t\t\tgoto error;\n\t\t}\n\n\t\t/* special PBAs have control field 0^16 */\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tif (data[j] != 0)\n\t\t\t\tgoto nonz;\n\t\tpba_to_lba[i] = UNUSABLE;\n\t\tusb_stor_dbg(us, \"PBA %d has no logical mapping\\n\", blocknum);\n\t\tcontinue;\n\n\tnonz:\n\t\t/* unwritten PBAs have control field FF^16 */\n\t\tfor (j = 0; j < 16; j++)\n\t\t\tif (data[j] != 0xff)\n\t\t\t\tgoto nonff;\n\t\tcontinue;\n\n\tnonff:\n\t\t/* normal PBAs start with six FFs */\n\t\tif (j < 6) {\n\t\t\tusb_stor_dbg(us, \"PBA %d has no logical mapping: reserved area = %02X%02X%02X%02X data status %02X block status %02X\\n\",\n\t\t\t\t     blocknum,\n\t\t\t\t     data[0], data[1], data[2], data[3],\n\t\t\t\t     data[4], data[5]);\n\t\t\tpba_to_lba[i] = UNUSABLE;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif ((data[6] >> 4) != 0x01) {\n\t\t\tusb_stor_dbg(us, \"PBA %d has invalid address field %02X%02X/%02X%02X\\n\",\n\t\t\t\t     blocknum, data[6], data[7],\n\t\t\t\t     data[11], data[12]);\n\t\t\tpba_to_lba[i] = UNUSABLE;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* check even parity */\n\t\tif (parity[data[6] ^ data[7]]) {\n\t\t\tprintk(KERN_WARNING\n\t\t\t       \"alauda_read_map: Bad parity in LBA for block %d\"\n\t\t\t       \" (%02X %02X)\\n\", i, data[6], data[7]);\n\t\t\tpba_to_lba[i] = UNUSABLE;\n\t\t\tcontinue;\n\t\t}\n\n\t\tlba_offset = short_pack(data[7], data[6]);\n\t\tlba_offset = (lba_offset & 0x07FF) >> 1;\n\t\tlba_real = lba_offset + zone_base_lba;\n\n\t\t/*\n\t\t * Every 1024 physical blocks (\"zone\"), the LBA numbers\n\t\t * go back to zero, but are within a higher block of LBA's.\n\t\t * Also, there is a maximum of 1000 LBA's per zone.\n\t\t * In other words, in PBA 1024-2047 you will find LBA 0-999\n\t\t * which are really LBA 1000-1999. This allows for 24 bad\n\t\t * or special physical blocks per zone.\n\t\t */\n\n\t\tif (lba_offset >= uzonesize) {\n\t\t\tprintk(KERN_WARNING\n\t\t\t       \"alauda_read_map: Bad low LBA %d for block %d\\n\",\n\t\t\t       lba_real, blocknum);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (lba_to_pba[lba_offset] != UNDEF) {\n\t\t\tprintk(KERN_WARNING\n\t\t\t       \"alauda_read_map: \"\n\t\t\t       \"LBA %d seen for PBA %d and %d\\n\",\n\t\t\t       lba_real, lba_to_pba[lba_offset], blocknum);\n\t\t\tcontinue;\n\t\t}\n\n\t\tpba_to_lba[i] = lba_real;\n\t\tlba_to_pba[lba_offset] = blocknum;\n\t\tcontinue;\n\t}\n\n\tMEDIA_INFO(us).lba_to_pba[zone] = lba_to_pba;\n\tMEDIA_INFO(us).pba_to_lba[zone] = pba_to_lba;\n\tresult = 0;\n\tgoto out;\n\nerror:\n\tkfree(lba_to_pba);\n\tkfree(pba_to_lba);\nout:\n\treturn result;\n}",
        "static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)\n{\n\tstruct s2io_nic *sp = ring_data->nic;\n\tstruct net_device *dev = ring_data->dev;\n\tstruct sk_buff *skb = (struct sk_buff *)": "static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)\n{\n\tstruct s2io_nic *sp = ring_data->nic;\n\tstruct net_device *dev = ring_data->dev;\n\tstruct sk_buff *skb = (struct sk_buff *)\n\t\t((unsigned long)rxdp->Host_Control);\n\tint ring_no = ring_data->ring_no;\n\tu16 l3_csum, l4_csum;\n\tunsigned long long err = rxdp->Control_1 & RXD_T_CODE;\n\tstruct lro *lro;\n\tu8 err_mask;\n\tstruct swStat *swstats = &sp->mac_control.stats_info->sw_stat;\n\n\tskb->dev = dev;\n\n\tif (err) {\n\t\t/* Check for parity error */\n\t\tif (err & 0x1)\n\t\t\tswstats->parity_err_cnt++;\n\n\t\terr_mask = err >> 48;\n\t\tswitch (err_mask) {\n\t\tcase 1:\n\t\t\tswstats->rx_parity_err_cnt++;\n\t\t\tbreak;\n\n\t\tcase 2:\n\t\t\tswstats->rx_abort_cnt++;\n\t\t\tbreak;\n\n\t\tcase 3:\n\t\t\tswstats->rx_parity_abort_cnt++;\n\t\t\tbreak;\n\n\t\tcase 4:\n\t\t\tswstats->rx_rda_fail_cnt++;\n\t\t\tbreak;\n\n\t\tcase 5:\n\t\t\tswstats->rx_unkn_prot_cnt++;\n\t\t\tbreak;\n\n\t\tcase 6:\n\t\t\tswstats->rx_fcs_err_cnt++;\n\t\t\tbreak;\n\n\t\tcase 7:\n\t\t\tswstats->rx_buf_size_err_cnt++;\n\t\t\tbreak;\n\n\t\tcase 8:\n\t\t\tswstats->rx_rxd_corrupt_cnt++;\n\t\t\tbreak;\n\n\t\tcase 15:\n\t\t\tswstats->rx_unkn_err_cnt++;\n\t\t\tbreak;\n\t\t}\n\t\t/*\n\t\t * Drop the packet if bad transfer code. Exception being\n\t\t * 0x5, which could be due to unsupported IPv6 extension header.\n\t\t * In this case, we let stack handle the packet.\n\t\t * Note that in this case, since checksum will be incorrect,\n\t\t * stack will validate the same.\n\t\t */\n\t\tif (err_mask != 0x5) {\n\t\t\tDBG_PRINT(ERR_DBG, \"%s: Rx error Value: 0x%x\\n\",\n\t\t\t\t  dev->name, err_mask);\n\t\t\tdev->stats.rx_crc_errors++;\n\t\t\tswstats->mem_freed\n\t\t\t\t+= skb->truesize;\n\t\t\tdev_kfree_skb(skb);\n\t\t\tring_data->rx_bufs_left -= 1;\n\t\t\trxdp->Host_Control = 0;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\trxdp->Host_Control = 0;\n\tif (sp->rxd_mode == RXD_MODE_1) {\n\t\tint len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);\n\n\t\tskb_put(skb, len);\n\t} else if (sp->rxd_mode == RXD_MODE_3B) {\n\t\tint get_block = ring_data->rx_curr_get_info.block_index;\n\t\tint get_off = ring_data->rx_curr_get_info.offset;\n\t\tint buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);\n\t\tint buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);\n\t\tunsigned char *buff = skb_push(skb, buf0_len);\n\n\t\tstruct buffAdd *ba = &ring_data->ba[get_block][get_off];\n\t\tmemcpy(buff, ba->ba_0, buf0_len);\n\t\tskb_put(skb, buf2_len);\n\t}\n\n\tif ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&\n\t    ((!ring_data->lro) ||\n\t     (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG))) &&\n\t    (dev->features & NETIF_F_RXCSUM)) {\n\t\tl3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);\n\t\tl4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);\n\t\tif ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {\n\t\t\t/*\n\t\t\t * NIC verifies if the Checksum of the received\n\t\t\t * frame is Ok or not and accordingly returns\n\t\t\t * a flag in the RxD.\n\t\t\t */\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t\t\tif (ring_data->lro) {\n\t\t\t\tu32 tcp_len = 0;\n\t\t\t\tu8 *tcp;\n\t\t\t\tint ret = 0;\n\n\t\t\t\tret = s2io_club_tcp_session(ring_data,\n\t\t\t\t\t\t\t    skb->data, &tcp,\n\t\t\t\t\t\t\t    &tcp_len, &lro,\n\t\t\t\t\t\t\t    rxdp, sp);\n\t\t\t\tswitch (ret) {\n\t\t\t\tcase 3: /* Begin anew */\n\t\t\t\t\tlro->parent = skb;\n\t\t\t\t\tgoto aggregate;\n\t\t\t\tcase 1: /* Aggregate */\n\t\t\t\t\tlro_append_pkt(sp, lro, skb, tcp_len);\n\t\t\t\t\tgoto aggregate;\n\t\t\t\tcase 4: /* Flush session */\n\t\t\t\t\tlro_append_pkt(sp, lro, skb, tcp_len);\n\t\t\t\t\tqueue_rx_frame(lro->parent,\n\t\t\t\t\t\t       lro->vlan_tag);\n\t\t\t\t\tclear_lro_session(lro);\n\t\t\t\t\tswstats->flush_max_pkts++;\n\t\t\t\t\tgoto aggregate;\n\t\t\t\tcase 2: /* Flush both */\n\t\t\t\t\tlro->parent->data_len = lro->frags_len;\n\t\t\t\t\tswstats->sending_both++;\n\t\t\t\t\tqueue_rx_frame(lro->parent,\n\t\t\t\t\t\t       lro->vlan_tag);\n\t\t\t\t\tclear_lro_session(lro);\n\t\t\t\t\tgoto send_up;\n\t\t\t\tcase 0: /* sessions exceeded */\n\t\t\t\tcase -1: /* non-TCP or not L2 aggregatable */\n\t\t\t\tcase 5: /*\n\t\t\t\t\t * First pkt in session not\n\t\t\t\t\t * L3/L4 aggregatable\n\t\t\t\t\t */\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tDBG_PRINT(ERR_DBG,\n\t\t\t\t\t\t  \"%s: Samadhana!!\\n\",\n\t\t\t\t\t\t  __func__);\n\t\t\t\t\tBUG();\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\t/*\n\t\t\t * Packet with erroneous checksum, let the\n\t\t\t * upper layers deal with it.\n\t\t\t */\n\t\t\tskb_checksum_none_assert(skb);\n\t\t}\n\t} else\n\t\tskb_checksum_none_assert(skb);\n\n\tswstats->mem_freed += skb->truesize;\nsend_up:\n\tskb_record_rx_queue(skb, ring_no);\n\tqueue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));\naggregate:\n\tsp->mac_control.rings[ring_no].rx_bufs_left -= 1;\n\treturn SUCCESS;\n}",
        "static void w1_send_slave(struct w1_master *dev, u64 rn)\n{\n\tstruct w1_cb_block *block = dev->priv;\n\tstruct w1_netlink_cmd *cache_cmd = block->cmd;\n\tu64 *data;": "static void w1_send_slave(struct w1_master *dev, u64 rn)\n{\n\tstruct w1_cb_block *block = dev->priv;\n\tstruct w1_netlink_cmd *cache_cmd = block->cmd;\n\tu64 *data;\n\n\tw1_reply_make_space(block, sizeof(*data));\n\n\t/* Add cmd back if the packet was sent */\n\tif (!block->cmd) {\n\t\tcache_cmd->len = 0;\n\t\tw1_netlink_queue_cmd(block, cache_cmd);\n\t}\n\n\tdata = (u64 *)(block->cmd->data + block->cmd->len);\n\n\t*data = rn;\n\tblock->cn->len += sizeof(*data);\n\tblock->msg->len += sizeof(*data);\n\tblock->cmd->len += sizeof(*data);\n}",
        "static void task_tick_rt(struct rq *rq, struct task_struct *p, int queued)\n{\n\tstruct sched_rt_entity *rt_se = &p->rt;\n\n\tupdate_curr_rt(rq);": "static void task_tick_rt(struct rq *rq, struct task_struct *p, int queued)\n{\n\tstruct sched_rt_entity *rt_se = &p->rt;\n\n\tupdate_curr_rt(rq);\n\tupdate_rt_rq_load_avg(rq_clock_pelt(rq), rq, 1);\n\n\twatchdog(rq, p);\n\n\t/*\n\t * RR tasks need a special form of timeslice management.\n\t * FIFO tasks have no timeslices.\n\t */\n\tif (p->policy != SCHED_RR)\n\t\treturn;\n\n\tif (--p->rt.time_slice)\n\t\treturn;\n\n\tp->rt.time_slice = sched_rr_timeslice;\n\n\t/*\n\t * Requeue to the end of queue if we (and all of our ancestors) are not\n\t * the only element on the queue\n\t */\n\tfor_each_sched_rt_entity(rt_se) {\n\t\tif (rt_se->run_list.prev != rt_se->run_list.next) {\n\t\t\trequeue_task_rt(rq, p, 0);\n\t\t\tresched_curr(rq);\n\t\t\treturn;\n\t\t}\n\t}\n}",
        "static int test_aead_inauthentic_inputs(struct aead_extra_tests_ctx *ctx)\n{\n\tunsigned int i;\n\tint err;\n": "static int test_aead_inauthentic_inputs(struct aead_extra_tests_ctx *ctx)\n{\n\tunsigned int i;\n\tint err;\n\n\tfor (i = 0; i < fuzz_iterations * 8; i++) {\n\t\t/*\n\t\t * Since this part of the tests isn't comparing the\n\t\t * implementation to another, there's no point in testing any\n\t\t * test vectors other than inauthentic ones (vec.novrfy=1) here.\n\t\t *\n\t\t * If we're having trouble generating such a test vector, e.g.\n\t\t * if the algorithm keeps rejecting the generated keys, don't\n\t\t * retry forever; just continue on.\n\t\t */\n\t\ttry_to_generate_inauthentic_testvec(ctx);\n\t\tif (ctx->vec.novrfy) {\n\t\t\tgenerate_random_testvec_config(&ctx->cfg, ctx->cfgname,\n\t\t\t\t\t\t       sizeof(ctx->cfgname));\n\t\t\terr = test_aead_vec_cfg(DECRYPT, &ctx->vec,\n\t\t\t\t\t\tctx->vec_name, &ctx->cfg,\n\t\t\t\t\t\tctx->req, ctx->tsgls);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\t\tcond_resched();\n\t}\n\treturn 0;\n}",
        "static int wcd_measure_adc_continuous(struct wcd_mbhc *mbhc)\n{\n\tu8 adc_result;\n\tint output_mv;\n\tint retry = 3;": "static int wcd_measure_adc_continuous(struct wcd_mbhc *mbhc)\n{\n\tu8 adc_result;\n\tint output_mv;\n\tint retry = 3;\n\tu8 adc_en;\n\n\t/* Pre-requisites for ADC continuous measurement */\n\t/* Read legacy electircal detection and disable */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC, 0x00);\n\t/* Set ADC to continuous measurement */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 1);\n\t/* Read ADC Enable bit to restore after adc measurement */\n\tadc_en = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_EN);\n\t/* Disable ADC_ENABLE bit */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);\n\t/* Disable MBHC FSM */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);\n\t/* Set the MUX selection to IN2P */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_MUX_CTL, MUX_CTL_IN2P);\n\t/* Enable MBHC FSM */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);\n\t/* Enable ADC_ENABLE bit */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 1);\n\n\twhile (retry--) {\n\t\t/* wait for 3 msec before reading ADC result */\n\t\tusleep_range(3000, 3100);\n\t\tadc_result = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_RESULT);\n\t}\n\n\t/* Restore ADC Enable */\n\twcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, adc_en);\n\t/* Get voltage from ADC result */\n\toutput_mv = wcd_get_voltage_from_adc(adc_result, wcd_mbhc_get_micbias(mbhc));\n\n\treturn output_mv;\n}",
        "static void surface_dtx_pm_complete(struct device *dev)\n{\n\tstruct sdtx_device *ddev = dev_get_drvdata(dev);\n\n\t/*": "static void surface_dtx_pm_complete(struct device *dev)\n{\n\tstruct sdtx_device *ddev = dev_get_drvdata(dev);\n\n\t/*\n\t * Normally, the EC will store events while suspended (i.e. in\n\t * display-off state) and release them when resumed (i.e. transitioned\n\t * to display-on state). During hibernation, however, the EC will be\n\t * shut down and does not store events. Furthermore, events might be\n\t * dropped during prolonged suspension (it is currently unknown how\n\t * big this event buffer is and how it behaves on overruns).\n\t *\n\t * To prevent any problems, we update the device state here. We do\n\t * this delayed to ensure that any events sent by the EC directly\n\t * after resuming will be handled first. The delay below has been\n\t * chosen (experimentally), so that there should be ample time for\n\t * these events to be handled, before we check and, if necessary,\n\t * update the state.\n\t */\n\tsdtx_update_device_state(ddev, msecs_to_jiffies(1000));\n}",
        "static int phy_init(struct net_device *dev)\n{\n\tstruct fe_priv *np = get_nvpriv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 phyinterface;": "static int phy_init(struct net_device *dev)\n{\n\tstruct fe_priv *np = get_nvpriv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 phyinterface;\n\tu32 mii_status, mii_control, mii_control_1000, reg;\n\n\t/* phy errata for E3016 phy */\n\tif (np->phy_model == PHY_MODEL_MARVELL_E3016) {\n\t\treg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);\n\t\treg &= ~PHY_MARVELL_E3016_INITMASK;\n\t\tif (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {\n\t\t\tnetdev_info(dev, \"%s: phy write to errata reg failed\\n\",\n\t\t\t\t    pci_name(np->pci_dev));\n\t\t\treturn PHY_ERROR;\n\t\t}\n\t}\n\tif (np->phy_oui == PHY_OUI_REALTEK) {\n\t\tif (np->phy_model == PHY_MODEL_REALTEK_8211 &&\n\t\t    np->phy_rev == PHY_REV_REALTEK_8211B) {\n\t\t\tif (init_realtek_8211b(dev, np)) {\n\t\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t\t    pci_name(np->pci_dev));\n\t\t\t\treturn PHY_ERROR;\n\t\t\t}\n\t\t} else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&\n\t\t\t   np->phy_rev == PHY_REV_REALTEK_8211C) {\n\t\t\tif (init_realtek_8211c(dev, np)) {\n\t\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t\t    pci_name(np->pci_dev));\n\t\t\t\treturn PHY_ERROR;\n\t\t\t}\n\t\t} else if (np->phy_model == PHY_MODEL_REALTEK_8201) {\n\t\t\tif (init_realtek_8201(dev, np)) {\n\t\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t\t    pci_name(np->pci_dev));\n\t\t\t\treturn PHY_ERROR;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* set advertise register */\n\treg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);\n\treg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |\n\t\tADVERTISE_100HALF | ADVERTISE_100FULL |\n\t\tADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);\n\tif (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {\n\t\tnetdev_info(dev, \"%s: phy write to advertise failed\\n\",\n\t\t\t    pci_name(np->pci_dev));\n\t\treturn PHY_ERROR;\n\t}\n\n\t/* get phy interface type */\n\tphyinterface = readl(base + NvRegPhyInterface);\n\n\t/* see if gigabit phy */\n\tmii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);\n\tif (mii_status & PHY_GIGABIT) {\n\t\tnp->gigabit = PHY_GIGABIT;\n\t\tmii_control_1000 = mii_rw(dev, np->phyaddr,\n\t\t\t\t\t  MII_CTRL1000, MII_READ);\n\t\tmii_control_1000 &= ~ADVERTISE_1000HALF;\n\t\tif (phyinterface & PHY_RGMII)\n\t\t\tmii_control_1000 |= ADVERTISE_1000FULL;\n\t\telse\n\t\t\tmii_control_1000 &= ~ADVERTISE_1000FULL;\n\n\t\tif (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {\n\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t    pci_name(np->pci_dev));\n\t\t\treturn PHY_ERROR;\n\t\t}\n\t} else\n\t\tnp->gigabit = 0;\n\n\tmii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);\n\tmii_control |= BMCR_ANENABLE;\n\n\tif (np->phy_oui == PHY_OUI_REALTEK &&\n\t    np->phy_model == PHY_MODEL_REALTEK_8211 &&\n\t    np->phy_rev == PHY_REV_REALTEK_8211C) {\n\t\t/* start autoneg since we already performed hw reset above */\n\t\tmii_control |= BMCR_ANRESTART;\n\t\tif (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {\n\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t    pci_name(np->pci_dev));\n\t\t\treturn PHY_ERROR;\n\t\t}\n\t} else {\n\t\t/* reset the phy\n\t\t * (certain phys need bmcr to be setup with reset)\n\t\t */\n\t\tif (phy_reset(dev, mii_control)) {\n\t\t\tnetdev_info(dev, \"%s: phy reset failed\\n\",\n\t\t\t\t    pci_name(np->pci_dev));\n\t\t\treturn PHY_ERROR;\n\t\t}\n\t}\n\n\t/* phy vendor specific configuration */\n\tif (np->phy_oui == PHY_OUI_CICADA) {\n\t\tif (init_cicada(dev, np, phyinterface)) {\n\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t    pci_name(np->pci_dev));\n\t\t\treturn PHY_ERROR;\n\t\t}\n\t} else if (np->phy_oui == PHY_OUI_VITESSE) {\n\t\tif (init_vitesse(dev, np)) {\n\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t    pci_name(np->pci_dev));\n\t\t\treturn PHY_ERROR;\n\t\t}\n\t} else if (np->phy_oui == PHY_OUI_REALTEK) {\n\t\tif (np->phy_model == PHY_MODEL_REALTEK_8211 &&\n\t\t    np->phy_rev == PHY_REV_REALTEK_8211B) {\n\t\t\t/* reset could have cleared these out, set them back */\n\t\t\tif (init_realtek_8211b(dev, np)) {\n\t\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t\t    pci_name(np->pci_dev));\n\t\t\t\treturn PHY_ERROR;\n\t\t\t}\n\t\t} else if (np->phy_model == PHY_MODEL_REALTEK_8201) {\n\t\t\tif (init_realtek_8201(dev, np) ||\n\t\t\t    init_realtek_8201_cross(dev, np)) {\n\t\t\t\tnetdev_info(dev, \"%s: phy init failed\\n\",\n\t\t\t\t\t    pci_name(np->pci_dev));\n\t\t\t\treturn PHY_ERROR;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* some phys clear out pause advertisement on reset, set it back */\n\tmii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);\n\n\t/* restart auto negotiation, power down phy */\n\tmii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);\n\tmii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);\n\tif (phy_power_down)\n\t\tmii_control |= BMCR_PDOWN;\n\tif (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))\n\t\treturn PHY_ERROR;\n\n\treturn 0;\n}",
        "static inline bool list_add_leaf_cfs_rq(struct cfs_rq *cfs_rq)\n{\n\tstruct rq *rq = rq_of(cfs_rq);\n\tint cpu = cpu_of(rq);\n": "static inline bool list_add_leaf_cfs_rq(struct cfs_rq *cfs_rq)\n{\n\tstruct rq *rq = rq_of(cfs_rq);\n\tint cpu = cpu_of(rq);\n\n\tif (cfs_rq->on_list)\n\t\treturn rq->tmp_alone_branch == &rq->leaf_cfs_rq_list;\n\n\tcfs_rq->on_list = 1;\n\n\t/*\n\t * Ensure we either appear before our parent (if already\n\t * enqueued) or force our parent to appear after us when it is\n\t * enqueued. The fact that we always enqueue bottom-up\n\t * reduces this to two cases and a special case for the root\n\t * cfs_rq. Furthermore, it also means that we will always reset\n\t * tmp_alone_branch either when the branch is connected\n\t * to a tree or when we reach the top of the tree\n\t */\n\tif (cfs_rq->tg->parent &&\n\t    cfs_rq->tg->parent->cfs_rq[cpu]->on_list) {\n\t\t/*\n\t\t * If parent is already on the list, we add the child\n\t\t * just before. Thanks to circular linked property of\n\t\t * the list, this means to put the child at the tail\n\t\t * of the list that starts by parent.\n\t\t */\n\t\tlist_add_tail_rcu(&cfs_rq->leaf_cfs_rq_list,\n\t\t\t&(cfs_rq->tg->parent->cfs_rq[cpu]->leaf_cfs_rq_list));\n\t\t/*\n\t\t * The branch is now connected to its tree so we can\n\t\t * reset tmp_alone_branch to the beginning of the\n\t\t * list.\n\t\t */\n\t\trq->tmp_alone_branch = &rq->leaf_cfs_rq_list;\n\t\treturn true;\n\t}\n\n\tif (!cfs_rq->tg->parent) {\n\t\t/*\n\t\t * cfs rq without parent should be put\n\t\t * at the tail of the list.\n\t\t */\n\t\tlist_add_tail_rcu(&cfs_rq->leaf_cfs_rq_list,\n\t\t\t&rq->leaf_cfs_rq_list);\n\t\t/*\n\t\t * We have reach the top of a tree so we can reset\n\t\t * tmp_alone_branch to the beginning of the list.\n\t\t */\n\t\trq->tmp_alone_branch = &rq->leaf_cfs_rq_list;\n\t\treturn true;\n\t}\n\n\t/*\n\t * The parent has not already been added so we want to\n\t * make sure that it will be put after us.\n\t * tmp_alone_branch points to the begin of the branch\n\t * where we will add parent.\n\t */\n\tlist_add_rcu(&cfs_rq->leaf_cfs_rq_list, rq->tmp_alone_branch);\n\t/*\n\t * update tmp_alone_branch to points to the new begin\n\t * of the branch\n\t */\n\trq->tmp_alone_branch = &cfs_rq->leaf_cfs_rq_list;\n\treturn false;\n}",
        "static void tk_setup_internals(struct timekeeper *tk, struct clocksource *clock)\n{\n\tu64 interval;\n\tu64 tmp, ntpinterval;\n\tstruct clocksource *old_clock;": "static void tk_setup_internals(struct timekeeper *tk, struct clocksource *clock)\n{\n\tu64 interval;\n\tu64 tmp, ntpinterval;\n\tstruct clocksource *old_clock;\n\n\t++tk->cs_was_changed_seq;\n\told_clock = tk->tkr_mono.clock;\n\ttk->tkr_mono.clock = clock;\n\ttk->tkr_mono.mask = clock->mask;\n\ttk->tkr_mono.cycle_last = tk_clock_read(&tk->tkr_mono);\n\n\ttk->tkr_raw.clock = clock;\n\ttk->tkr_raw.mask = clock->mask;\n\ttk->tkr_raw.cycle_last = tk->tkr_mono.cycle_last;\n\n\t/* Do the ns -> cycle conversion first, using original mult */\n\ttmp = NTP_INTERVAL_LENGTH;\n\ttmp <<= clock->shift;\n\tntpinterval = tmp;\n\ttmp += clock->mult/2;\n\tdo_div(tmp, clock->mult);\n\tif (tmp == 0)\n\t\ttmp = 1;\n\n\tinterval = (u64) tmp;\n\ttk->cycle_interval = interval;\n\n\t/* Go back from cycles -> shifted ns */\n\ttk->xtime_interval = interval * clock->mult;\n\ttk->xtime_remainder = ntpinterval - tk->xtime_interval;\n\ttk->raw_interval = interval * clock->mult;\n\n\t /* if changing clocks, convert xtime_nsec shift units */\n\tif (old_clock) {\n\t\tint shift_change = clock->shift - old_clock->shift;\n\t\tif (shift_change < 0) {\n\t\t\ttk->tkr_mono.xtime_nsec >>= -shift_change;\n\t\t\ttk->tkr_raw.xtime_nsec >>= -shift_change;\n\t\t} else {\n\t\t\ttk->tkr_mono.xtime_nsec <<= shift_change;\n\t\t\ttk->tkr_raw.xtime_nsec <<= shift_change;\n\t\t}\n\t}\n\n\ttk->tkr_mono.shift = clock->shift;\n\ttk->tkr_raw.shift = clock->shift;\n\n\ttk->ntp_error = 0;\n\ttk->ntp_error_shift = NTP_SCALE_SHIFT - clock->shift;\n\ttk->ntp_tick = ntpinterval << tk->ntp_error_shift;\n\n\t/*\n\t * The timekeeper keeps its own mult values for the currently\n\t * active clocksource. These value will be adjusted via NTP\n\t * to counteract clock drifting.\n\t */\n\ttk->tkr_mono.mult = clock->mult;\n\ttk->tkr_raw.mult = clock->mult;\n\ttk->ntp_err_mult = 0;\n\ttk->skip_second_overflow = 0;\n}",
        "static int initialize_superblock(struct dm_integrity_c *ic, unsigned journal_sectors, unsigned interleave_sectors)\n{\n\tunsigned journal_sections;\n\tint test_bit;\n": "static int initialize_superblock(struct dm_integrity_c *ic, unsigned journal_sectors, unsigned interleave_sectors)\n{\n\tunsigned journal_sections;\n\tint test_bit;\n\n\tmemset(ic->sb, 0, SB_SECTORS << SECTOR_SHIFT);\n\tmemcpy(ic->sb->magic, SB_MAGIC, 8);\n\tic->sb->integrity_tag_size = cpu_to_le16(ic->tag_size);\n\tic->sb->log2_sectors_per_block = __ffs(ic->sectors_per_block);\n\tif (ic->journal_mac_alg.alg_string)\n\t\tic->sb->flags |= cpu_to_le32(SB_FLAG_HAVE_JOURNAL_MAC);\n\n\tcalculate_journal_section_size(ic);\n\tjournal_sections = journal_sectors / ic->journal_section_sectors;\n\tif (!journal_sections)\n\t\tjournal_sections = 1;\n\n\tif (ic->fix_hmac && (ic->internal_hash_alg.alg_string || ic->journal_mac_alg.alg_string)) {\n\t\tic->sb->flags |= cpu_to_le32(SB_FLAG_FIXED_HMAC);\n\t\tget_random_bytes(ic->sb->salt, SALT_SIZE);\n\t}\n\n\tif (!ic->meta_dev) {\n\t\tif (ic->fix_padding)\n\t\t\tic->sb->flags |= cpu_to_le32(SB_FLAG_FIXED_PADDING);\n\t\tic->sb->journal_sections = cpu_to_le32(journal_sections);\n\t\tif (!interleave_sectors)\n\t\t\tinterleave_sectors = DEFAULT_INTERLEAVE_SECTORS;\n\t\tic->sb->log2_interleave_sectors = __fls(interleave_sectors);\n\t\tic->sb->log2_interleave_sectors = max((__u8)MIN_LOG2_INTERLEAVE_SECTORS, ic->sb->log2_interleave_sectors);\n\t\tic->sb->log2_interleave_sectors = min((__u8)MAX_LOG2_INTERLEAVE_SECTORS, ic->sb->log2_interleave_sectors);\n\n\t\tget_provided_data_sectors(ic);\n\t\tif (!ic->provided_data_sectors)\n\t\t\treturn -EINVAL;\n\t} else {\n\t\tic->sb->log2_interleave_sectors = 0;\n\n\t\tget_provided_data_sectors(ic);\n\t\tif (!ic->provided_data_sectors)\n\t\t\treturn -EINVAL;\n\ntry_smaller_buffer:\n\t\tic->sb->journal_sections = cpu_to_le32(0);\n\t\tfor (test_bit = fls(journal_sections) - 1; test_bit >= 0; test_bit--) {\n\t\t\t__u32 prev_journal_sections = le32_to_cpu(ic->sb->journal_sections);\n\t\t\t__u32 test_journal_sections = prev_journal_sections | (1U << test_bit);\n\t\t\tif (test_journal_sections > journal_sections)\n\t\t\t\tcontinue;\n\t\t\tic->sb->journal_sections = cpu_to_le32(test_journal_sections);\n\t\t\tif (calculate_device_limits(ic))\n\t\t\t\tic->sb->journal_sections = cpu_to_le32(prev_journal_sections);\n\n\t\t}\n\t\tif (!le32_to_cpu(ic->sb->journal_sections)) {\n\t\t\tif (ic->log2_buffer_sectors > 3) {\n\t\t\t\tic->log2_buffer_sectors--;\n\t\t\t\tgoto try_smaller_buffer;\n\t\t\t}\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tic->sb->provided_data_sectors = cpu_to_le64(ic->provided_data_sectors);\n\n\tsb_set_version(ic);\n\n\treturn 0;\n}",
        "static void reshape_request_write(struct mddev *mddev, struct r10bio *r10_bio)\n{\n\t/* Reshape read completed.  Hopefully we have a block\n\t * to write out.\n\t * If we got a read error then we do sync 1-page reads from": "static void reshape_request_write(struct mddev *mddev, struct r10bio *r10_bio)\n{\n\t/* Reshape read completed.  Hopefully we have a block\n\t * to write out.\n\t * If we got a read error then we do sync 1-page reads from\n\t * elsewhere until we find the data - or give up.\n\t */\n\tstruct r10conf *conf = mddev->private;\n\tint s;\n\n\tif (!test_bit(R10BIO_Uptodate, &r10_bio->state))\n\t\tif (handle_reshape_read_error(mddev, r10_bio) < 0) {\n\t\t\t/* Reshape has been aborted */\n\t\t\tmd_done_sync(mddev, r10_bio->sectors, 0);\n\t\t\treturn;\n\t\t}\n\n\t/* We definitely have the data in the pages, schedule the\n\t * writes.\n\t */\n\tatomic_set(&r10_bio->remaining, 1);\n\tfor (s = 0; s < conf->copies*2; s++) {\n\t\tstruct bio *b;\n\t\tint d = r10_bio->devs[s/2].devnum;\n\t\tstruct md_rdev *rdev;\n\t\trcu_read_lock();\n\t\tif (s&1) {\n\t\t\trdev = rcu_dereference(conf->mirrors[d].replacement);\n\t\t\tb = r10_bio->devs[s/2].repl_bio;\n\t\t} else {\n\t\t\trdev = rcu_dereference(conf->mirrors[d].rdev);\n\t\t\tb = r10_bio->devs[s/2].bio;\n\t\t}\n\t\tif (!rdev || test_bit(Faulty, &rdev->flags)) {\n\t\t\trcu_read_unlock();\n\t\t\tcontinue;\n\t\t}\n\t\tatomic_inc(&rdev->nr_pending);\n\t\trcu_read_unlock();\n\t\tmd_sync_acct_bio(b, r10_bio->sectors);\n\t\tatomic_inc(&r10_bio->remaining);\n\t\tb->bi_next = NULL;\n\t\tsubmit_bio_noacct(b);\n\t}\n\tend_reshape_request(r10_bio);\n}",
        "static int ext4_fc_write_inode_data(struct inode *inode, u32 *crc)\n{\n\text4_lblk_t old_blk_size, cur_lblk_off, new_blk_size;\n\tstruct ext4_inode_info *ei = EXT4_I(inode);\n\tstruct ext4_map_blocks map;": "static int ext4_fc_write_inode_data(struct inode *inode, u32 *crc)\n{\n\text4_lblk_t old_blk_size, cur_lblk_off, new_blk_size;\n\tstruct ext4_inode_info *ei = EXT4_I(inode);\n\tstruct ext4_map_blocks map;\n\tstruct ext4_fc_add_range fc_ext;\n\tstruct ext4_fc_del_range lrange;\n\tstruct ext4_extent *ex;\n\tint ret;\n\n\tmutex_lock(&ei->i_fc_lock);\n\tif (ei->i_fc_lblk_len == 0) {\n\t\tmutex_unlock(&ei->i_fc_lock);\n\t\treturn 0;\n\t}\n\told_blk_size = ei->i_fc_lblk_start;\n\tnew_blk_size = ei->i_fc_lblk_start + ei->i_fc_lblk_len - 1;\n\tei->i_fc_lblk_len = 0;\n\tmutex_unlock(&ei->i_fc_lock);\n\n\tcur_lblk_off = old_blk_size;\n\tjbd_debug(1, \"%s: will try writing %d to %d for inode %ld\\n\",\n\t\t  __func__, cur_lblk_off, new_blk_size, inode->i_ino);\n\n\twhile (cur_lblk_off <= new_blk_size) {\n\t\tmap.m_lblk = cur_lblk_off;\n\t\tmap.m_len = new_blk_size - cur_lblk_off + 1;\n\t\tret = ext4_map_blocks(NULL, inode, &map, 0);\n\t\tif (ret < 0)\n\t\t\treturn -ECANCELED;\n\n\t\tif (map.m_len == 0) {\n\t\t\tcur_lblk_off++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (ret == 0) {\n\t\t\tlrange.fc_ino = cpu_to_le32(inode->i_ino);\n\t\t\tlrange.fc_lblk = cpu_to_le32(map.m_lblk);\n\t\t\tlrange.fc_len = cpu_to_le32(map.m_len);\n\t\t\tif (!ext4_fc_add_tlv(inode->i_sb, EXT4_FC_TAG_DEL_RANGE,\n\t\t\t\t\t    sizeof(lrange), (u8 *)&lrange, crc))\n\t\t\t\treturn -ENOSPC;\n\t\t} else {\n\t\t\tunsigned int max = (map.m_flags & EXT4_MAP_UNWRITTEN) ?\n\t\t\t\tEXT_UNWRITTEN_MAX_LEN : EXT_INIT_MAX_LEN;\n\n\t\t\t/* Limit the number of blocks in one extent */\n\t\t\tmap.m_len = min(max, map.m_len);\n\n\t\t\tfc_ext.fc_ino = cpu_to_le32(inode->i_ino);\n\t\t\tex = (struct ext4_extent *)&fc_ext.fc_ex;\n\t\t\tex->ee_block = cpu_to_le32(map.m_lblk);\n\t\t\tex->ee_len = cpu_to_le16(map.m_len);\n\t\t\text4_ext_store_pblock(ex, map.m_pblk);\n\t\t\tif (map.m_flags & EXT4_MAP_UNWRITTEN)\n\t\t\t\text4_ext_mark_unwritten(ex);\n\t\t\telse\n\t\t\t\text4_ext_mark_initialized(ex);\n\t\t\tif (!ext4_fc_add_tlv(inode->i_sb, EXT4_FC_TAG_ADD_RANGE,\n\t\t\t\t\t    sizeof(fc_ext), (u8 *)&fc_ext, crc))\n\t\t\t\treturn -ENOSPC;\n\t\t}\n\n\t\tcur_lblk_off += map.m_len;\n\t}\n\n\treturn 0;\n}",
        "static void cm9761_update_jacks(struct snd_ac97 *ac97)\n{\n\t/* FIXME: check the bits for each model\n\t *        model 83 is confirmed to work\n\t */": "static void cm9761_update_jacks(struct snd_ac97 *ac97)\n{\n\t/* FIXME: check the bits for each model\n\t *        model 83 is confirmed to work\n\t */\n\tstatic const unsigned short surr_on[3][2] = {\n\t\t{ 0x0008, 0x0000 }, /* 9761-78 & 82 */\n\t\t{ 0x0000, 0x0008 }, /* 9761-82 rev.B */\n\t\t{ 0x0000, 0x0008 }, /* 9761-83 */\n\t};\n\tstatic const unsigned short clfe_on[3][2] = {\n\t\t{ 0x0000, 0x1000 }, /* 9761-78 & 82 */\n\t\t{ 0x1000, 0x0000 }, /* 9761-82 rev.B */\n\t\t{ 0x0000, 0x1000 }, /* 9761-83 */\n\t};\n\tstatic const unsigned short surr_shared[3][2] = {\n\t\t{ 0x0000, 0x0400 }, /* 9761-78 & 82 */\n\t\t{ 0x0000, 0x0400 }, /* 9761-82 rev.B */\n\t\t{ 0x0000, 0x0400 }, /* 9761-83 */\n\t};\n\tstatic const unsigned short clfe_shared[3][2] = {\n\t\t{ 0x2000, 0x0880 }, /* 9761-78 & 82 */\n\t\t{ 0x0000, 0x2880 }, /* 9761-82 rev.B */\n\t\t{ 0x2000, 0x0800 }, /* 9761-83 */\n\t};\n\tunsigned short val = 0;\n\n\tval |= surr_on[ac97->spec.dev_flags][is_surround_on(ac97)];\n\tval |= clfe_on[ac97->spec.dev_flags][is_clfe_on(ac97)];\n\tval |= surr_shared[ac97->spec.dev_flags][is_shared_surrout(ac97)];\n\tval |= clfe_shared[ac97->spec.dev_flags][is_shared_clfeout(ac97)];\n\n\tsnd_ac97_update_bits(ac97, AC97_CM9761_MULTI_CHAN, 0x3c88, val);\n}",
        "static bool console_flush_all(bool do_cond_resched, u64 *next_seq, bool *handover)\n{\n\tstatic char dropped_text[DROPPED_TEXT_MAX];\n\tstatic char ext_text[CONSOLE_EXT_LOG_MAX];\n\tstatic char text[CONSOLE_LOG_MAX];": "static bool console_flush_all(bool do_cond_resched, u64 *next_seq, bool *handover)\n{\n\tstatic char dropped_text[DROPPED_TEXT_MAX];\n\tstatic char ext_text[CONSOLE_EXT_LOG_MAX];\n\tstatic char text[CONSOLE_LOG_MAX];\n\tbool any_usable = false;\n\tstruct console *con;\n\tbool any_progress;\n\n\t*next_seq = 0;\n\t*handover = false;\n\n\tdo {\n\t\t/* Let the kthread printers do the work if they can. */\n\t\tif (!allow_direct_printing())\n\t\t\treturn false;\n\n\t\tany_progress = false;\n\n\t\tfor_each_console(con) {\n\t\t\tbool progress;\n\n\t\t\tif (!console_is_usable(con))\n\t\t\t\tcontinue;\n\t\t\tany_usable = true;\n\n\t\t\tif (con->flags & CON_EXTENDED) {\n\t\t\t\t/* Extended consoles do not print \"dropped messages\". */\n\t\t\t\tprogress = console_emit_next_record_transferable(con, &text[0],\n\t\t\t\t\t\t\t\t&ext_text[0], NULL, handover);\n\t\t\t} else {\n\t\t\t\tprogress = console_emit_next_record_transferable(con, &text[0],\n\t\t\t\t\t\t\t\tNULL, &dropped_text[0], handover);\n\t\t\t}\n\t\t\tif (*handover)\n\t\t\t\treturn false;\n\n\t\t\t/* Track the next of the highest seq flushed. */\n\t\t\tif (con->seq > *next_seq)\n\t\t\t\t*next_seq = con->seq;\n\n\t\t\tif (!progress)\n\t\t\t\tcontinue;\n\t\t\tany_progress = true;\n\n\t\t\t/* Allow panic_cpu to take over the consoles safely. */\n\t\t\tif (abandon_console_lock_in_panic())\n\t\t\t\treturn false;\n\n\t\t\tif (do_cond_resched)\n\t\t\t\tcond_resched();\n\t\t}\n\t} while (any_progress);\n\n\treturn any_usable;\n}",
        "static void xsk_delete_from_maps(struct xdp_sock *xs)\n{\n\t/* This function removes the current XDP socket from all the\n\t * maps it resides in. We need to take extra care here, due to\n\t * the two locks involved. Each map has a lock synchronizing": "static void xsk_delete_from_maps(struct xdp_sock *xs)\n{\n\t/* This function removes the current XDP socket from all the\n\t * maps it resides in. We need to take extra care here, due to\n\t * the two locks involved. Each map has a lock synchronizing\n\t * updates to the entries, and each socket has a lock that\n\t * synchronizes access to the list of maps (map_list). For\n\t * deadlock avoidance the locks need to be taken in the order\n\t * \"map lock\"->\"socket map list lock\". We start off by\n\t * accessing the socket map list, and take a reference to the\n\t * map to guarantee existence between the\n\t * xsk_get_map_list_entry() and xsk_map_try_sock_delete()\n\t * calls. Then we ask the map to remove the socket, which\n\t * tries to remove the socket from the map. Note that there\n\t * might be updates to the map between\n\t * xsk_get_map_list_entry() and xsk_map_try_sock_delete().\n\t */\n\tstruct xdp_sock __rcu **map_entry = NULL;\n\tstruct xsk_map *map;\n\n\twhile ((map = xsk_get_map_list_entry(xs, &map_entry))) {\n\t\txsk_map_try_sock_delete(map, xs, map_entry);\n\t\tbpf_map_put(&map->map);\n\t}\n}",
        "static int __init nettel_init(void)\n{\n\tvolatile unsigned long *amdpar;\n\tunsigned long amdaddr, maxsize;\n\tint num_amd_partitions=0;": "static int __init nettel_init(void)\n{\n\tvolatile unsigned long *amdpar;\n\tunsigned long amdaddr, maxsize;\n\tint num_amd_partitions=0;\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\tvolatile unsigned long *intel0par, *intel1par;\n\tunsigned long orig_bootcspar, orig_romcs1par;\n\tunsigned long intel0addr, intel0size;\n\tunsigned long intel1addr, intel1size;\n\tint intelboot, intel0cs, intel1cs;\n\tint num_intel_partitions;\n#endif\n\tint rc = 0;\n\n\tnettel_mmcrp = (void *) ioremap(0xfffef000, 4096);\n\tif (nettel_mmcrp == NULL) {\n\t\tprintk(\"SNAPGEAR: failed to disable MMCR cache??\\n\");\n\t\treturn(-EIO);\n\t}\n\n\t/* Set CPU clock to be 33.000MHz */\n\t*((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;\n\n\tamdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);\n\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\tintelboot = 0;\n\tintel0cs = SC520_PAR_ROMCS1;\n\tintel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);\n\tintel1cs = SC520_PAR_ROMCS2;\n\tintel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);\n\n\t/*\n\t *\tSave the CS settings then ensure ROMCS1 and ROMCS2 are off,\n\t *\totherwise they might clash with where we try to map BOOTCS.\n\t */\n\torig_bootcspar = *amdpar;\n\torig_romcs1par = *intel0par;\n\t*intel0par = 0;\n\t*intel1par = 0;\n#endif\n\n\t/*\n\t *\tThe first thing to do is determine if we have a separate\n\t *\tboot FLASH device. Typically this is a small (1 to 2MB)\n\t *\tAMD FLASH part. It seems that device size is about the\n\t *\tonly way to tell if this is the case...\n\t */\n\tamdaddr = 0x20000000;\n\tmaxsize = AMD_WINDOW_MAXSIZE;\n\n\t*amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize);\n\t__asm__ (\"wbinvd\");\n\n\tnettel_amd_map.phys = amdaddr;\n\tnettel_amd_map.virt = ioremap(amdaddr, maxsize);\n\tif (!nettel_amd_map.virt) {\n\t\tprintk(\"SNAPGEAR: failed to ioremap() BOOTCS\\n\");\n\t\tiounmap(nettel_mmcrp);\n\t\treturn(-EIO);\n\t}\n\tsimple_map_init(&nettel_amd_map);\n\n\tif ((amd_mtd = do_map_probe(\"jedec_probe\", &nettel_amd_map))) {\n\t\tprintk(KERN_NOTICE \"SNAPGEAR: AMD flash device size = %dK\\n\",\n\t\t\t(int)(amd_mtd->size>>10));\n\n\t\tamd_mtd->owner = THIS_MODULE;\n\n\t\t/* The high BIOS partition is only present for 2MB units */\n\t\tnum_amd_partitions = NUM_AMD_PARTITIONS;\n\t\tif (amd_mtd->size < AMD_WINDOW_MAXSIZE)\n\t\t\tnum_amd_partitions--;\n\t\t/* Don't add the partition until after the primary INTEL's */\n\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\t\t/*\n\t\t *\tMap the Intel flash into memory after the AMD\n\t\t *\tIt has to start on a multiple of maxsize.\n\t\t */\n\t\tmaxsize = SC520_PAR_TO_SIZE(orig_romcs1par);\n\t\tif (maxsize < (32 * 1024 * 1024))\n\t\t\tmaxsize = (32 * 1024 * 1024);\n\t\tintel0addr = amdaddr + maxsize;\n#endif\n\t} else {\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\t\t/* INTEL boot FLASH */\n\t\tintelboot++;\n\n\t\tif (!orig_romcs1par) {\n\t\t\tintel0cs = SC520_PAR_BOOTCS;\n\t\t\tintel0par = (volatile unsigned long *)\n\t\t\t\t(nettel_mmcrp + 0xc4);\n\t\t\tintel1cs = SC520_PAR_ROMCS1;\n\t\t\tintel1par = (volatile unsigned long *)\n\t\t\t\t(nettel_mmcrp + 0xc0);\n\n\t\t\tintel0addr = SC520_PAR_TO_ADDR(orig_bootcspar);\n\t\t\tmaxsize = SC520_PAR_TO_SIZE(orig_bootcspar);\n\t\t} else {\n\t\t\t/* Kernel base is on ROMCS1, not BOOTCS */\n\t\t\tintel0cs = SC520_PAR_ROMCS1;\n\t\t\tintel0par = (volatile unsigned long *)\n\t\t\t\t(nettel_mmcrp + 0xc0);\n\t\t\tintel1cs = SC520_PAR_BOOTCS;\n\t\t\tintel1par = (volatile unsigned long *)\n\t\t\t\t(nettel_mmcrp + 0xc4);\n\n\t\t\tintel0addr = SC520_PAR_TO_ADDR(orig_romcs1par);\n\t\t\tmaxsize = SC520_PAR_TO_SIZE(orig_romcs1par);\n\t\t}\n\n\t\t/* Destroy useless AMD MTD mapping */\n\t\tamd_mtd = NULL;\n\t\tiounmap(nettel_amd_map.virt);\n\t\tnettel_amd_map.virt = NULL;\n#else\n\t\t/* Only AMD flash supported */\n\t\trc = -ENXIO;\n\t\tgoto out_unmap2;\n#endif\n\t}\n\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\t/*\n\t *\tWe have determined the INTEL FLASH configuration, so lets\n\t *\tgo ahead and probe for them now.\n\t */\n\n\t/* Set PAR to the maximum size */\n\tif (maxsize < (32 * 1024 * 1024))\n\t\tmaxsize = (32 * 1024 * 1024);\n\t*intel0par = SC520_PAR(intel0cs, intel0addr, maxsize);\n\n\t/* Turn other PAR off so the first probe doesn't find it */\n\t*intel1par = 0;\n\n\t/* Probe for the size of the first Intel flash */\n\tnettel_intel_map.size = maxsize;\n\tnettel_intel_map.phys = intel0addr;\n\tnettel_intel_map.virt = ioremap(intel0addr, maxsize);\n\tif (!nettel_intel_map.virt) {\n\t\tprintk(\"SNAPGEAR: failed to ioremap() ROMCS1\\n\");\n\t\trc = -EIO;\n\t\tgoto out_unmap2;\n\t}\n\tsimple_map_init(&nettel_intel_map);\n\n\tintel_mtd = do_map_probe(\"cfi_probe\", &nettel_intel_map);\n\tif (!intel_mtd) {\n\t\trc = -ENXIO;\n\t\tgoto out_unmap1;\n\t}\n\n\t/* Set PAR to the detected size */\n\tintel0size = intel_mtd->size;\n\t*intel0par = SC520_PAR(intel0cs, intel0addr, intel0size);\n\n\t/*\n\t *\tMap second Intel FLASH right after first. Set its size to the\n\t *\tsame maxsize used for the first Intel FLASH.\n\t */\n\tintel1addr = intel0addr + intel0size;\n\t*intel1par = SC520_PAR(intel1cs, intel1addr, maxsize);\n\t__asm__ (\"wbinvd\");\n\n\tmaxsize += intel0size;\n\n\t/* Delete the old map and probe again to do both chips */\n\tmap_destroy(intel_mtd);\n\tintel_mtd = NULL;\n\tiounmap(nettel_intel_map.virt);\n\n\tnettel_intel_map.size = maxsize;\n\tnettel_intel_map.virt = ioremap(intel0addr, maxsize);\n\tif (!nettel_intel_map.virt) {\n\t\tprintk(\"SNAPGEAR: failed to ioremap() ROMCS1/2\\n\");\n\t\trc = -EIO;\n\t\tgoto out_unmap2;\n\t}\n\n\tintel_mtd = do_map_probe(\"cfi_probe\", &nettel_intel_map);\n\tif (! intel_mtd) {\n\t\trc = -ENXIO;\n\t\tgoto out_unmap1;\n\t}\n\n\tintel1size = intel_mtd->size - intel0size;\n\tif (intel1size > 0) {\n\t\t*intel1par = SC520_PAR(intel1cs, intel1addr, intel1size);\n\t\t__asm__ (\"wbinvd\");\n\t} else {\n\t\t*intel1par = 0;\n\t}\n\n\tprintk(KERN_NOTICE \"SNAPGEAR: Intel flash device size = %lldKiB\\n\",\n\t       (unsigned long long)(intel_mtd->size >> 10));\n\n\tintel_mtd->owner = THIS_MODULE;\n\n\tnum_intel_partitions = ARRAY_SIZE(nettel_intel_partitions);\n\n\tif (intelboot) {\n\t\t/*\n\t\t *\tAdjust offset and size of last boot partition.\n\t\t *\tMust allow for BIOS region at end of FLASH.\n\t\t */\n\t\tnettel_intel_partitions[1].size = (intel0size + intel1size) -\n\t\t\t(1024*1024 + intel_mtd->erasesize);\n\t\tnettel_intel_partitions[3].size = intel0size + intel1size;\n\t\tnettel_intel_partitions[4].offset =\n\t\t\t(intel0size + intel1size) - intel_mtd->erasesize;\n\t\tnettel_intel_partitions[4].size = intel_mtd->erasesize;\n\t\tnettel_intel_partitions[5].offset =\n\t\t\tnettel_intel_partitions[4].offset;\n\t\tnettel_intel_partitions[5].size =\n\t\t\tnettel_intel_partitions[4].size;\n\t} else {\n\t\t/* No BIOS regions when AMD boot */\n\t\tnum_intel_partitions -= 2;\n\t}\n\trc = mtd_device_register(intel_mtd, nettel_intel_partitions,\n\t\t\t\t num_intel_partitions);\n\tif (rc)\n\t\tgoto out_map_destroy;\n#endif\n\n\tif (amd_mtd) {\n\t\trc = mtd_device_register(amd_mtd, nettel_amd_partitions,\n\t\t\t\t\t num_amd_partitions);\n\t\tif (rc)\n\t\t\tgoto out_mtd_unreg;\n\t}\n\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\tregister_reboot_notifier(&nettel_notifier_block);\n#endif\n\n\treturn rc;\n\nout_mtd_unreg:\n#ifdef CONFIG_MTD_CFI_INTELEXT\n\tmtd_device_unregister(intel_mtd);\nout_map_destroy:\n\tmap_destroy(intel_mtd);\nout_unmap1:\n\tiounmap(nettel_intel_map.virt);\n#endif\n\nout_unmap2:\n\tiounmap(nettel_mmcrp);\n\tiounmap(nettel_amd_map.virt);\n\n\treturn rc;\n}",
        "static int s2io_poll_inta(struct napi_struct *napi, int budget)\n{\n\tstruct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);\n\tint pkts_processed = 0;\n\tint ring_pkts_processed, i;": "static int s2io_poll_inta(struct napi_struct *napi, int budget)\n{\n\tstruct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);\n\tint pkts_processed = 0;\n\tint ring_pkts_processed, i;\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tint budget_org = budget;\n\tstruct config_param *config = &nic->config;\n\tstruct mac_info *mac_control = &nic->mac_control;\n\n\tif (unlikely(!is_s2io_card_up(nic)))\n\t\treturn 0;\n\n\tfor (i = 0; i < config->rx_ring_num; i++) {\n\t\tstruct ring_info *ring = &mac_control->rings[i];\n\t\tring_pkts_processed = rx_intr_handler(ring, budget);\n\t\ts2io_chk_rx_buffers(nic, ring);\n\t\tpkts_processed += ring_pkts_processed;\n\t\tbudget -= ring_pkts_processed;\n\t\tif (budget <= 0)\n\t\t\tbreak;\n\t}\n\tif (pkts_processed < budget_org) {\n\t\tnapi_complete_done(napi, pkts_processed);\n\t\t/* Re enable the Rx interrupts for the ring */\n\t\twriteq(0, &bar0->rx_traffic_mask);\n\t\treadl(&bar0->rx_traffic_mask);\n\t}\n\treturn pkts_processed;\n}",
        "static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)\n{\n\tstruct uart_port *port = (struct uart_port *)dev_id;\n\tstruct cdns_uart *cdns_uart = port->private_data;\n\tunsigned int data;": "static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)\n{\n\tstruct uart_port *port = (struct uart_port *)dev_id;\n\tstruct cdns_uart *cdns_uart = port->private_data;\n\tunsigned int data;\n\tunsigned int rxbs_status = 0;\n\tunsigned int status_mask;\n\tunsigned int framerrprocessed = 0;\n\tchar status = TTY_NORMAL;\n\tbool is_rxbs_support;\n\n\tis_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;\n\n\twhile ((readl(port->membase + CDNS_UART_SR) &\n\t\tCDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {\n\t\tif (is_rxbs_support)\n\t\t\trxbs_status = readl(port->membase + CDNS_UART_RXBS);\n\t\tdata = readl(port->membase + CDNS_UART_FIFO);\n\t\tport->icount.rx++;\n\t\t/*\n\t\t * There is no hardware break detection in Zynq, so we interpret\n\t\t * framing error with all-zeros data as a break sequence.\n\t\t * Most of the time, there's another non-zero byte at the\n\t\t * end of the sequence.\n\t\t */\n\t\tif (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {\n\t\t\tif (!data) {\n\t\t\t\tport->read_status_mask |= CDNS_UART_IXR_BRK;\n\t\t\t\tframerrprocessed = 1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\t\tif (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {\n\t\t\tport->icount.brk++;\n\t\t\tstatus = TTY_BREAK;\n\t\t\tif (uart_handle_break(port))\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tisrstatus &= port->read_status_mask;\n\t\tisrstatus &= ~port->ignore_status_mask;\n\t\tstatus_mask = port->read_status_mask;\n\t\tstatus_mask &= ~port->ignore_status_mask;\n\n\t\tif (data &&\n\t\t    (port->read_status_mask & CDNS_UART_IXR_BRK)) {\n\t\t\tport->read_status_mask &= ~CDNS_UART_IXR_BRK;\n\t\t\tport->icount.brk++;\n\t\t\tif (uart_handle_break(port))\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tif (uart_handle_sysrq_char(port, data))\n\t\t\tcontinue;\n\n\t\tif (is_rxbs_support) {\n\t\t\tif ((rxbs_status & CDNS_UART_RXBS_PARITY)\n\t\t\t    && (status_mask & CDNS_UART_IXR_PARITY)) {\n\t\t\t\tport->icount.parity++;\n\t\t\t\tstatus = TTY_PARITY;\n\t\t\t}\n\t\t\tif ((rxbs_status & CDNS_UART_RXBS_FRAMING)\n\t\t\t    && (status_mask & CDNS_UART_IXR_PARITY)) {\n\t\t\t\tport->icount.frame++;\n\t\t\t\tstatus = TTY_FRAME;\n\t\t\t}\n\t\t} else {\n\t\t\tif (isrstatus & CDNS_UART_IXR_PARITY) {\n\t\t\t\tport->icount.parity++;\n\t\t\t\tstatus = TTY_PARITY;\n\t\t\t}\n\t\t\tif ((isrstatus & CDNS_UART_IXR_FRAMING) &&\n\t\t\t    !framerrprocessed) {\n\t\t\t\tport->icount.frame++;\n\t\t\t\tstatus = TTY_FRAME;\n\t\t\t}\n\t\t}\n\t\tif (isrstatus & CDNS_UART_IXR_OVERRUN) {\n\t\t\tport->icount.overrun++;\n\t\t\ttty_insert_flip_char(&port->state->port, 0,\n\t\t\t\t\t     TTY_OVERRUN);\n\t\t}\n\t\ttty_insert_flip_char(&port->state->port, data, status);\n\t\tisrstatus = 0;\n\t}\n\n\ttty_flip_buffer_push(&port->state->port);\n}",
        "static int ca_get_slot_caps(struct dst_state *state, struct ca_caps *p_ca_caps, void __user *arg)\n{\n\tint i;\n\tu8 slot_cap[256];\n\tstatic u8 slot_command[8] = {0x07, 0x40, 0x02, 0x00, 0x02, 0x00, 0x00, 0xff};": "static int ca_get_slot_caps(struct dst_state *state, struct ca_caps *p_ca_caps, void __user *arg)\n{\n\tint i;\n\tu8 slot_cap[256];\n\tstatic u8 slot_command[8] = {0x07, 0x40, 0x02, 0x00, 0x02, 0x00, 0x00, 0xff};\n\n\tput_checksum(&slot_command[0], slot_command[0]);\n\tif ((dst_put_ci(state, slot_command, sizeof (slot_command), slot_cap, GET_REPLY)) < 0) {\n\t\tdprintk(verbose, DST_CA_ERROR, 1, \" -->dst_put_ci FAILED !\");\n\t\treturn -EIO;\n\t}\n\tdprintk(verbose, DST_CA_NOTICE, 1, \" -->dst_put_ci SUCCESS !\");\n\n\t/*\tWill implement the rest soon\t\t*/\n\n\tdprintk(verbose, DST_CA_INFO, 1, \" Slot cap = [%d]\", slot_cap[7]);\n\tdprintk(verbose, DST_CA_INFO, 0, \"===================================\\n\");\n\tfor (i = 0; i < slot_cap[0] + 1; i++)\n\t\tdprintk(verbose, DST_CA_INFO, 0, \" %d\", slot_cap[i]);\n\tdprintk(verbose, DST_CA_INFO, 0, \"\\n\");\n\n\tp_ca_caps->slot_num = 1;\n\tp_ca_caps->slot_type = 1;\n\tp_ca_caps->descr_num = slot_cap[7];\n\tp_ca_caps->descr_type = 1;\n\n\tif (copy_to_user(arg, p_ca_caps, sizeof (struct ca_caps)))\n\t\treturn -EFAULT;\n\n\treturn 0;\n}",
        "static int s390_cpumsf_samples(struct s390_cpumsf_queue *sfq, u64 *ts)\n{\n\tstruct s390_cpumsf *sf = sfq->sf;\n\tunsigned char *buf = sfq->buffer->use_data;\n\tsize_t len = sfq->buffer->use_size;": "static int s390_cpumsf_samples(struct s390_cpumsf_queue *sfq, u64 *ts)\n{\n\tstruct s390_cpumsf *sf = sfq->sf;\n\tunsigned char *buf = sfq->buffer->use_data;\n\tsize_t len = sfq->buffer->use_size;\n\tstruct hws_basic_entry *basic;\n\tunsigned short bsdes, dsdes;\n\tsize_t pos = 0;\n\tint err = 1;\n\tu64 aux_ts;\n\n\tif (!s390_cpumsf_validate(sf->machine_type, buf, len, &bsdes,\n\t\t\t\t  &dsdes)) {\n\t\t*ts = ~0ULL;\n\t\treturn -1;\n\t}\n\n\t/* Get trailer entry time stamp and check if entries in\n\t * this auxiliary page are ready for processing. If the\n\t * time stamp of the first entry is too high, whole buffer\n\t * can be skipped. In this case return time stamp.\n\t */\n\taux_ts = get_trailer_time(buf);\n\tif (!aux_ts) {\n\t\tpr_err(\"[%#08\" PRIx64 \"] Invalid AUX trailer entry TOD clock base\\n\",\n\t\t       (s64)sfq->buffer->data_offset);\n\t\taux_ts = ~0ULL;\n\t\tgoto out;\n\t}\n\tif (aux_ts > *ts) {\n\t\t*ts = aux_ts;\n\t\treturn 0;\n\t}\n\n\twhile (pos < len) {\n\t\t/* Handle Basic entry */\n\t\tbasic = (struct hws_basic_entry *)(buf + pos);\n\t\tif (s390_cpumsf_make_event(pos, basic, sfq))\n\t\t\tpos += bsdes;\n\t\telse {\n\t\t\terr = -EBADF;\n\t\t\tgoto out;\n\t\t}\n\n\t\tpos += dsdes;\t/* Skip diagnostic entry */\n\n\t\t/* Check for trailer entry */\n\t\tif (!s390_cpumsf_reached_trailer(bsdes + dsdes, pos)) {\n\t\t\tpos = (pos + S390_CPUMSF_PAGESZ)\n\t\t\t       & ~(S390_CPUMSF_PAGESZ - 1);\n\t\t\t/* Check existence of next page */\n\t\t\tif (pos >= len)\n\t\t\t\tbreak;\n\t\t\taux_ts = get_trailer_time(buf + pos);\n\t\t\tif (!aux_ts) {\n\t\t\t\taux_ts = ~0ULL;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tif (aux_ts > *ts) {\n\t\t\t\t*ts = aux_ts;\n\t\t\t\tsfq->buffer->use_data += pos;\n\t\t\t\tsfq->buffer->use_size -= pos;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\nout:\n\t*ts = aux_ts;\n\tsfq->buffer->use_size = 0;\n\tsfq->buffer->use_data = NULL;\n\treturn err;\t/* Buffer completely scanned or error */\n}",
        "static int hci_set_random_addr_sync(struct hci_dev *hdev, bdaddr_t *rpa)\n{\n\t/* If we're advertising or initiating an LE connection we can't\n\t * go ahead and change the random address at this time. This is\n\t * because the eventual initiator address used for the": "static int hci_set_random_addr_sync(struct hci_dev *hdev, bdaddr_t *rpa)\n{\n\t/* If we're advertising or initiating an LE connection we can't\n\t * go ahead and change the random address at this time. This is\n\t * because the eventual initiator address used for the\n\t * subsequently created connection will be undefined (some\n\t * controllers use the new address and others the one we had\n\t * when the operation started).\n\t *\n\t * In this kind of scenario skip the update and let the random\n\t * address be updated at the next cycle.\n\t */\n\tif (hci_dev_test_flag(hdev, HCI_LE_ADV) ||\n\t    hci_lookup_le_connect(hdev)) {\n\t\tbt_dev_dbg(hdev, \"Deferring random address update\");\n\t\thci_dev_set_flag(hdev, HCI_RPA_EXPIRED);\n\t\treturn 0;\n\t}\n\n\treturn __hci_cmd_sync_status(hdev, HCI_OP_LE_SET_RANDOM_ADDR,\n\t\t\t\t     6, rpa, HCI_CMD_TIMEOUT);\n}",
        "static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)\n{\n\tint rc;\n\n\tBNX2X_DEV_INFO(\"Uncommon unload Flow\\n\");": "static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)\n{\n\tint rc;\n\n\tBNX2X_DEV_INFO(\"Uncommon unload Flow\\n\");\n\n\t/* Test if previous unload process was already finished for this path */\n\tif (bnx2x_prev_is_path_marked(bp))\n\t\treturn bnx2x_prev_mcp_done(bp);\n\n\tBNX2X_DEV_INFO(\"Path is unmarked\\n\");\n\n\t/* Cannot proceed with FLR if UNDI is loaded, since FW does not match */\n\tif (bnx2x_prev_is_after_undi(bp))\n\t\tgoto out;\n\n\t/* If function has FLR capabilities, and existing FW version matches\n\t * the one required, then FLR will be sufficient to clean any residue\n\t * left by previous driver\n\t */\n\trc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);\n\n\tif (!rc) {\n\t\t/* fw version is good */\n\t\tBNX2X_DEV_INFO(\"FW version matches our own. Attempting FLR\\n\");\n\t\trc = bnx2x_do_flr(bp);\n\t}\n\n\tif (!rc) {\n\t\t/* FLR was performed */\n\t\tBNX2X_DEV_INFO(\"FLR successful\\n\");\n\t\treturn 0;\n\t}\n\n\tBNX2X_DEV_INFO(\"Could not FLR\\n\");\n\nout:\n\t/* Close the MCP request, return failure*/\n\trc = bnx2x_prev_mcp_done(bp);\n\tif (!rc)\n\t\trc = BNX2X_PREV_WAIT_NEEDED;\n\n\treturn rc;\n}",
        "static void _tcpm_pd_vbus_vsafe0v(struct tcpm_port *port)\n{\n\ttcpm_log_force(port, \"VBUS VSAFE0V\");\n\tport->vbus_vsafe0v = true;\n\tswitch (port->state) {": "static void _tcpm_pd_vbus_vsafe0v(struct tcpm_port *port)\n{\n\ttcpm_log_force(port, \"VBUS VSAFE0V\");\n\tport->vbus_vsafe0v = true;\n\tswitch (port->state) {\n\tcase SRC_HARD_RESET_VBUS_OFF:\n\t\t/*\n\t\t * After establishing the vSafe0V voltage condition on VBUS, the Source Shall wait\n\t\t * tSrcRecover before re-applying VCONN and restoring VBUS to vSafe5V.\n\t\t */\n\t\ttcpm_set_state(port, SRC_HARD_RESET_VBUS_ON, PD_T_SRC_RECOVER);\n\t\tbreak;\n\tcase SRC_ATTACH_WAIT:\n\t\tif (tcpm_port_is_source(port))\n\t\t\ttcpm_set_state(port, tcpm_try_snk(port) ? SNK_TRY : SRC_ATTACHED,\n\t\t\t\t       PD_T_CC_DEBOUNCE);\n\t\tbreak;\n\tcase SRC_STARTUP:\n\tcase SRC_SEND_CAPABILITIES:\n\tcase SRC_SEND_CAPABILITIES_TIMEOUT:\n\tcase SRC_NEGOTIATE_CAPABILITIES:\n\tcase SRC_TRANSITION_SUPPLY:\n\tcase SRC_READY:\n\tcase SRC_WAIT_NEW_CAPABILITIES:\n\t\tif (port->auto_vbus_discharge_enabled) {\n\t\t\tif (port->port_type == TYPEC_PORT_SRC)\n\t\t\t\ttcpm_set_state(port, SRC_UNATTACHED, 0);\n\t\t\telse\n\t\t\t\ttcpm_set_state(port, SNK_UNATTACHED, 0);\n\t\t}\n\t\tbreak;\n\tcase PR_SWAP_SNK_SRC_SINK_OFF:\n\tcase PR_SWAP_SNK_SRC_SOURCE_ON:\n\t\t/* Do nothing, vsafe0v is expected during transition */\n\t\tbreak;\n\tcase SNK_ATTACH_WAIT:\n\tcase SNK_DEBOUNCED:\n\t\t/*Do nothing, still waiting for VSAFE5V for connect */\n\t\tbreak;\n\tdefault:\n\t\tif (port->pwr_role == TYPEC_SINK && port->auto_vbus_discharge_enabled)\n\t\t\ttcpm_set_state(port, SNK_UNATTACHED, 0);\n\t\tbreak;\n\t}\n}",
        "static int sealing_thread_fn(void *arg)\n{\n\tint sig, r;\n\n\t/*": "static int sealing_thread_fn(void *arg)\n{\n\tint sig, r;\n\n\t/*\n\t * This thread first waits 200ms so any pending operation in the parent\n\t * is correctly started. After that, it tries to seal @global_mfd as\n\t * SEAL_WRITE. This _must_ fail as the parent thread has a read() into\n\t * that memory mapped object still ongoing.\n\t * We then wait one more second and try sealing again. This time it\n\t * must succeed as there shouldn't be anyone else pinning the pages.\n\t */\n\n\t/* wait 200ms for FUSE-request to be active */\n\tusleep(200000);\n\n\t/* unmount mapping before sealing to avoid i_mmap_writable failures */\n\tmunmap(global_p, mfd_def_size);\n\n\t/* Try sealing the global file; expect EBUSY or success. Current\n\t * kernels will never succeed, but in the future, kernels might\n\t * implement page-replacements or other fancy ways to avoid racing\n\t * writes. */\n\tr = mfd_busy_add_seals(global_mfd, F_SEAL_WRITE);\n\tif (r >= 0) {\n\t\tprintf(\"HURRAY! This kernel fixed GUP races!\\n\");\n\t} else {\n\t\t/* wait 1s more so the FUSE-request is done */\n\t\tsleep(1);\n\n\t\t/* try sealing the global file again */\n\t\tmfd_assert_add_seals(global_mfd, F_SEAL_WRITE);\n\t}\n\n\treturn 0;\n}",
        "static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;": "static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)\n{\n\tstruct spi_mem_op op;\n\tu8 *buf = nor->bouncebuf;\n\tint ret;\n\n\t/*\n\t * The register is 1-byte wide, but 1-byte transactions are not allowed\n\t * in 8D-8D-8D mode. Since there is no register at the next location,\n\t * just initialize the value to 0 and let the transaction go on.\n\t */\n\tbuf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;\n\tbuf[1] = 0;\n\top = (struct spi_mem_op)\n\t\tCYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf);\n\tret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Read flash ID to make sure the switch was successful. */\n\tret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);\n\tif (ret) {\n\t\tdev_dbg(nor->dev, \"error %d reading JEDEC ID after disabling 8D-8D-8D mode\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tif (memcmp(buf, nor->info->id, nor->info->id_len))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static int sock_map_link(struct bpf_map *map, struct sock *sk)\n{\n\tstruct sk_psock_progs *progs = sock_map_progs(map);\n\tstruct bpf_prog *stream_verdict = NULL;\n\tstruct bpf_prog *stream_parser = NULL;": "static int sock_map_link(struct bpf_map *map, struct sock *sk)\n{\n\tstruct sk_psock_progs *progs = sock_map_progs(map);\n\tstruct bpf_prog *stream_verdict = NULL;\n\tstruct bpf_prog *stream_parser = NULL;\n\tstruct bpf_prog *skb_verdict = NULL;\n\tstruct bpf_prog *msg_parser = NULL;\n\tstruct sk_psock *psock;\n\tint ret;\n\n\tstream_verdict = READ_ONCE(progs->stream_verdict);\n\tif (stream_verdict) {\n\t\tstream_verdict = bpf_prog_inc_not_zero(stream_verdict);\n\t\tif (IS_ERR(stream_verdict))\n\t\t\treturn PTR_ERR(stream_verdict);\n\t}\n\n\tstream_parser = READ_ONCE(progs->stream_parser);\n\tif (stream_parser) {\n\t\tstream_parser = bpf_prog_inc_not_zero(stream_parser);\n\t\tif (IS_ERR(stream_parser)) {\n\t\t\tret = PTR_ERR(stream_parser);\n\t\t\tgoto out_put_stream_verdict;\n\t\t}\n\t}\n\n\tmsg_parser = READ_ONCE(progs->msg_parser);\n\tif (msg_parser) {\n\t\tmsg_parser = bpf_prog_inc_not_zero(msg_parser);\n\t\tif (IS_ERR(msg_parser)) {\n\t\t\tret = PTR_ERR(msg_parser);\n\t\t\tgoto out_put_stream_parser;\n\t\t}\n\t}\n\n\tskb_verdict = READ_ONCE(progs->skb_verdict);\n\tif (skb_verdict) {\n\t\tskb_verdict = bpf_prog_inc_not_zero(skb_verdict);\n\t\tif (IS_ERR(skb_verdict)) {\n\t\t\tret = PTR_ERR(skb_verdict);\n\t\t\tgoto out_put_msg_parser;\n\t\t}\n\t}\n\n\tpsock = sock_map_psock_get_checked(sk);\n\tif (IS_ERR(psock)) {\n\t\tret = PTR_ERR(psock);\n\t\tgoto out_progs;\n\t}\n\n\tif (psock) {\n\t\tif ((msg_parser && READ_ONCE(psock->progs.msg_parser)) ||\n\t\t    (stream_parser  && READ_ONCE(psock->progs.stream_parser)) ||\n\t\t    (skb_verdict && READ_ONCE(psock->progs.skb_verdict)) ||\n\t\t    (skb_verdict && READ_ONCE(psock->progs.stream_verdict)) ||\n\t\t    (stream_verdict && READ_ONCE(psock->progs.skb_verdict)) ||\n\t\t    (stream_verdict && READ_ONCE(psock->progs.stream_verdict))) {\n\t\t\tsk_psock_put(sk, psock);\n\t\t\tret = -EBUSY;\n\t\t\tgoto out_progs;\n\t\t}\n\t} else {\n\t\tpsock = sk_psock_init(sk, map->numa_node);\n\t\tif (IS_ERR(psock)) {\n\t\t\tret = PTR_ERR(psock);\n\t\t\tgoto out_progs;\n\t\t}\n\t}\n\n\tif (msg_parser)\n\t\tpsock_set_prog(&psock->progs.msg_parser, msg_parser);\n\tif (stream_parser)\n\t\tpsock_set_prog(&psock->progs.stream_parser, stream_parser);\n\tif (stream_verdict)\n\t\tpsock_set_prog(&psock->progs.stream_verdict, stream_verdict);\n\tif (skb_verdict)\n\t\tpsock_set_prog(&psock->progs.skb_verdict, skb_verdict);\n\n\t/* msg_* and stream_* programs references tracked in psock after this\n\t * point. Reference dec and cleanup will occur through psock destructor\n\t */\n\tret = sock_map_init_proto(sk, psock);\n\tif (ret < 0) {\n\t\tsk_psock_put(sk, psock);\n\t\tgoto out;\n\t}\n\n\twrite_lock_bh(&sk->sk_callback_lock);\n\tif (stream_parser && stream_verdict && !psock->saved_data_ready) {\n\t\tret = sk_psock_init_strp(sk, psock);\n\t\tif (ret) {\n\t\t\twrite_unlock_bh(&sk->sk_callback_lock);\n\t\t\tsk_psock_put(sk, psock);\n\t\t\tgoto out;\n\t\t}\n\t\tsk_psock_start_strp(sk, psock);\n\t} else if (!stream_parser && stream_verdict && !psock->saved_data_ready) {\n\t\tsk_psock_start_verdict(sk,psock);\n\t} else if (!stream_verdict && skb_verdict && !psock->saved_data_ready) {\n\t\tsk_psock_start_verdict(sk, psock);\n\t}\n\twrite_unlock_bh(&sk->sk_callback_lock);\n\treturn 0;\nout_progs:\n\tif (skb_verdict)\n\t\tbpf_prog_put(skb_verdict);\nout_put_msg_parser:\n\tif (msg_parser)\n\t\tbpf_prog_put(msg_parser);\nout_put_stream_parser:\n\tif (stream_parser)\n\t\tbpf_prog_put(stream_parser);\nout_put_stream_verdict:\n\tif (stream_verdict)\n\t\tbpf_prog_put(stream_verdict);\nout:\n\treturn ret;\n}",
        "static void test_v3_new_redist_regions(void)\n{\n\tvoid *dummy = NULL;\n\tstruct vm_gic v;\n\tuint64_t addr;": "static void test_v3_new_redist_regions(void)\n{\n\tvoid *dummy = NULL;\n\tstruct vm_gic v;\n\tuint64_t addr;\n\tint ret;\n\n\tv = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS);\n\tsubtest_v3_redist_regions(&v);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,\n\t\t\t  KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);\n\n\tret = run_vcpu(v.vm, 3);\n\tTEST_ASSERT(ret == -ENXIO, \"running without sufficient number of rdists\");\n\tvm_gic_destroy(&v);\n\n\t/* step2 */\n\n\tv = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS);\n\tsubtest_v3_redist_regions(&v);\n\n\taddr = REDIST_REGION_ATTR_ADDR(1, 0x280000, 0, 2);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, &addr, true);\n\n\tret = run_vcpu(v.vm, 3);\n\tTEST_ASSERT(ret == -EBUSY, \"running without vgic explicit init\");\n\n\tvm_gic_destroy(&v);\n\n\t/* step 3 */\n\n\tv = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS);\n\tsubtest_v3_redist_regions(&v);\n\n\t_kvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, dummy, true);\n\tTEST_ASSERT(ret && errno == EFAULT,\n\t\t    \"register a third region allowing to cover the 4 vcpus\");\n\n\taddr = REDIST_REGION_ATTR_ADDR(1, 0x280000, 0, 2);\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,\n\t\t\t  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, &addr, true);\n\n\tkvm_device_access(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,\n\t\t\t  KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);\n\n\tret = run_vcpu(v.vm, 3);\n\tTEST_ASSERT(!ret, \"vcpu run\");\n\n\tvm_gic_destroy(&v);\n}",
        "static int handle_quectel_ec20(struct device *dev, int ifnum)\n{\n\tint altsetting = 0;\n\n\t/*": "static int handle_quectel_ec20(struct device *dev, int ifnum)\n{\n\tint altsetting = 0;\n\n\t/*\n\t * Quectel EC20 Mini PCIe LTE module layout:\n\t * 0: DM/DIAG (use libqcdm from ModemManager for communication)\n\t * 1: NMEA\n\t * 2: AT-capable modem port\n\t * 3: Modem interface\n\t * 4: NDIS\n\t */\n\tswitch (ifnum) {\n\tcase 0:\n\t\tdev_dbg(dev, \"Quectel EC20 DM/DIAG interface found\\n\");\n\t\tbreak;\n\tcase 1:\n\t\tdev_dbg(dev, \"Quectel EC20 NMEA GPS interface found\\n\");\n\t\tbreak;\n\tcase 2:\n\tcase 3:\n\t\tdev_dbg(dev, \"Quectel EC20 Modem port found\\n\");\n\t\tbreak;\n\tcase 4:\n\t\t/* Don't claim the QMI/net interface */\n\t\taltsetting = -1;\n\t\tbreak;\n\t}\n\n\treturn altsetting;\n}",
        "static int init_nic(struct s2io_nic *nic)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tstruct net_device *dev = nic->dev;\n\tregister u64 val64 = 0;": "static int init_nic(struct s2io_nic *nic)\n{\n\tstruct XENA_dev_config __iomem *bar0 = nic->bar0;\n\tstruct net_device *dev = nic->dev;\n\tregister u64 val64 = 0;\n\tvoid __iomem *add;\n\tu32 time;\n\tint i, j;\n\tint dtx_cnt = 0;\n\tunsigned long long mem_share;\n\tint mem_size;\n\tstruct config_param *config = &nic->config;\n\tstruct mac_info *mac_control = &nic->mac_control;\n\n\t/* to set the swapper controle on the card */\n\tif (s2io_set_swapper(nic)) {\n\t\tDBG_PRINT(ERR_DBG, \"ERROR: Setting Swapper failed\\n\");\n\t\treturn -EIO;\n\t}\n\n\t/*\n\t * Herc requires EOI to be removed from reset before XGXS, so..\n\t */\n\tif (nic->device_type & XFRAME_II_DEVICE) {\n\t\tval64 = 0xA500000000ULL;\n\t\twriteq(val64, &bar0->sw_reset);\n\t\tmsleep(500);\n\t\tval64 = readq(&bar0->sw_reset);\n\t}\n\n\t/* Remove XGXS from reset state */\n\tval64 = 0;\n\twriteq(val64, &bar0->sw_reset);\n\tmsleep(500);\n\tval64 = readq(&bar0->sw_reset);\n\n\t/* Ensure that it's safe to access registers by checking\n\t * RIC_RUNNING bit is reset. Check is valid only for XframeII.\n\t */\n\tif (nic->device_type == XFRAME_II_DEVICE) {\n\t\tfor (i = 0; i < 50; i++) {\n\t\t\tval64 = readq(&bar0->adapter_status);\n\t\t\tif (!(val64 & ADAPTER_STATUS_RIC_RUNNING))\n\t\t\t\tbreak;\n\t\t\tmsleep(10);\n\t\t}\n\t\tif (i == 50)\n\t\t\treturn -ENODEV;\n\t}\n\n\t/*  Enable Receiving broadcasts */\n\tadd = &bar0->mac_cfg;\n\tval64 = readq(&bar0->mac_cfg);\n\tval64 |= MAC_RMAC_BCAST_ENABLE;\n\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\twritel((u32)val64, add);\n\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\twritel((u32) (val64 >> 32), (add + 4));\n\n\t/* Read registers in all blocks */\n\tval64 = readq(&bar0->mac_int_mask);\n\tval64 = readq(&bar0->mc_int_mask);\n\tval64 = readq(&bar0->xgxs_int_mask);\n\n\t/*  Set MTU */\n\tval64 = dev->mtu;\n\twriteq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);\n\n\tif (nic->device_type & XFRAME_II_DEVICE) {\n\t\twhile (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {\n\t\t\tSPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],\n\t\t\t\t\t  &bar0->dtx_control, UF);\n\t\t\tif (dtx_cnt & 0x1)\n\t\t\t\tmsleep(1); /* Necessary!! */\n\t\t\tdtx_cnt++;\n\t\t}\n\t} else {\n\t\twhile (xena_dtx_cfg[dtx_cnt] != END_SIGN) {\n\t\t\tSPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],\n\t\t\t\t\t  &bar0->dtx_control, UF);\n\t\t\tval64 = readq(&bar0->dtx_control);\n\t\t\tdtx_cnt++;\n\t\t}\n\t}\n\n\t/*  Tx DMA Initialization */\n\tval64 = 0;\n\twriteq(val64, &bar0->tx_fifo_partition_0);\n\twriteq(val64, &bar0->tx_fifo_partition_1);\n\twriteq(val64, &bar0->tx_fifo_partition_2);\n\twriteq(val64, &bar0->tx_fifo_partition_3);\n\n\tfor (i = 0, j = 0; i < config->tx_fifo_num; i++) {\n\t\tstruct tx_fifo_config *tx_cfg = &config->tx_cfg[i];\n\n\t\tval64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |\n\t\t\tvBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);\n\n\t\tif (i == (config->tx_fifo_num - 1)) {\n\t\t\tif (i % 2 == 0)\n\t\t\t\ti++;\n\t\t}\n\n\t\tswitch (i) {\n\t\tcase 1:\n\t\t\twriteq(val64, &bar0->tx_fifo_partition_0);\n\t\t\tval64 = 0;\n\t\t\tj = 0;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\twriteq(val64, &bar0->tx_fifo_partition_1);\n\t\t\tval64 = 0;\n\t\t\tj = 0;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\twriteq(val64, &bar0->tx_fifo_partition_2);\n\t\t\tval64 = 0;\n\t\t\tj = 0;\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\twriteq(val64, &bar0->tx_fifo_partition_3);\n\t\t\tval64 = 0;\n\t\t\tj = 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tj++;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*\n\t * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug\n\t * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.\n\t */\n\tif ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))\n\t\twriteq(PCC_ENABLE_FOUR, &bar0->pcc_enable);\n\n\tval64 = readq(&bar0->tx_fifo_partition_0);\n\tDBG_PRINT(INIT_DBG, \"Fifo partition at: 0x%p is: 0x%llx\\n\",\n\t\t  &bar0->tx_fifo_partition_0, (unsigned long long)val64);\n\n\t/*\n\t * Initialization of Tx_PA_CONFIG register to ignore packet\n\t * integrity checking.\n\t */\n\tval64 = readq(&bar0->tx_pa_cfg);\n\tval64 |= TX_PA_CFG_IGNORE_FRM_ERR |\n\t\tTX_PA_CFG_IGNORE_SNAP_OUI |\n\t\tTX_PA_CFG_IGNORE_LLC_CTRL |\n\t\tTX_PA_CFG_IGNORE_L2_ERR;\n\twriteq(val64, &bar0->tx_pa_cfg);\n\n\t/* Rx DMA initialization. */\n\tval64 = 0;\n\tfor (i = 0; i < config->rx_ring_num; i++) {\n\t\tstruct rx_ring_config *rx_cfg = &config->rx_cfg[i];\n\n\t\tval64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);\n\t}\n\twriteq(val64, &bar0->rx_queue_priority);\n\n\t/*\n\t * Allocating equal share of memory to all the\n\t * configured Rings.\n\t */\n\tval64 = 0;\n\tif (nic->device_type & XFRAME_II_DEVICE)\n\t\tmem_size = 32;\n\telse\n\t\tmem_size = 64;\n\n\tfor (i = 0; i < config->rx_ring_num; i++) {\n\t\tswitch (i) {\n\t\tcase 0:\n\t\t\tmem_share = (mem_size / config->rx_ring_num +\n\t\t\t\t     mem_size % config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 1:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 2:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 3:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 4:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 5:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 6:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);\n\t\t\tcontinue;\n\t\tcase 7:\n\t\t\tmem_share = (mem_size / config->rx_ring_num);\n\t\t\tval64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);\n\t\t\tcontinue;\n\t\t}\n\t}\n\twriteq(val64, &bar0->rx_queue_cfg);\n\n\t/*\n\t * Filling Tx round robin registers\n\t * as per the number of FIFOs for equal scheduling priority\n\t */\n\tswitch (config->tx_fifo_num) {\n\tcase 1:\n\t\tval64 = 0x0;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 2:\n\t\tval64 = 0x0001000100010001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0001000100000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 3:\n\t\tval64 = 0x0001020001020001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\tval64 = 0x0200010200010200ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\tval64 = 0x0102000102000102ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\tval64 = 0x0001020001020001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0200010200000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 4:\n\t\tval64 = 0x0001020300010203ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0001020300000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 5:\n\t\tval64 = 0x0001020304000102ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\tval64 = 0x0304000102030400ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\tval64 = 0x0102030400010203ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\tval64 = 0x0400010203040001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0203040000000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 6:\n\t\tval64 = 0x0001020304050001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\tval64 = 0x0203040500010203ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\tval64 = 0x0405000102030405ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\tval64 = 0x0001020304050001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0203040500000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 7:\n\t\tval64 = 0x0001020304050600ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\tval64 = 0x0102030405060001ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\tval64 = 0x0203040506000102ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\tval64 = 0x0304050600010203ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0405060000000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\tcase 8:\n\t\tval64 = 0x0001020304050607ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_0);\n\t\twriteq(val64, &bar0->tx_w_round_robin_1);\n\t\twriteq(val64, &bar0->tx_w_round_robin_2);\n\t\twriteq(val64, &bar0->tx_w_round_robin_3);\n\t\tval64 = 0x0001020300000000ULL;\n\t\twriteq(val64, &bar0->tx_w_round_robin_4);\n\t\tbreak;\n\t}\n\n\t/* Enable all configured Tx FIFO partitions */\n\tval64 = readq(&bar0->tx_fifo_partition_0);\n\tval64 |= (TX_FIFO_PARTITION_EN);\n\twriteq(val64, &bar0->tx_fifo_partition_0);\n\n\t/* Filling the Rx round robin registers as per the\n\t * number of Rings and steering based on QoS with\n\t * equal priority.\n\t */\n\tswitch (config->rx_ring_num) {\n\tcase 1:\n\t\tval64 = 0x0;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080808080808080ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 2:\n\t\tval64 = 0x0001000100010001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0001000100000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080808040404040ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 3:\n\t\tval64 = 0x0001020001020001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\tval64 = 0x0200010200010200ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\tval64 = 0x0102000102000102ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\tval64 = 0x0001020001020001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0200010200000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080804040402020ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 4:\n\t\tval64 = 0x0001020300010203ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0001020300000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080404020201010ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 5:\n\t\tval64 = 0x0001020304000102ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\tval64 = 0x0304000102030400ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\tval64 = 0x0102030400010203ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\tval64 = 0x0400010203040001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0203040000000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080404020201008ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 6:\n\t\tval64 = 0x0001020304050001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\tval64 = 0x0203040500010203ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\tval64 = 0x0405000102030405ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\tval64 = 0x0001020304050001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0203040500000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080404020100804ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 7:\n\t\tval64 = 0x0001020304050600ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\tval64 = 0x0102030405060001ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\tval64 = 0x0203040506000102ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\tval64 = 0x0304050600010203ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0405060000000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8080402010080402ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\tcase 8:\n\t\tval64 = 0x0001020304050607ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_0);\n\t\twriteq(val64, &bar0->rx_w_round_robin_1);\n\t\twriteq(val64, &bar0->rx_w_round_robin_2);\n\t\twriteq(val64, &bar0->rx_w_round_robin_3);\n\t\tval64 = 0x0001020300000000ULL;\n\t\twriteq(val64, &bar0->rx_w_round_robin_4);\n\n\t\tval64 = 0x8040201008040201ULL;\n\t\twriteq(val64, &bar0->rts_qos_steering);\n\t\tbreak;\n\t}\n\n\t/* UDP Fix */\n\tval64 = 0;\n\tfor (i = 0; i < 8; i++)\n\t\twriteq(val64, &bar0->rts_frm_len_n[i]);\n\n\t/* Set the default rts frame length for the rings configured */\n\tval64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);\n\tfor (i = 0 ; i < config->rx_ring_num ; i++)\n\t\twriteq(val64, &bar0->rts_frm_len_n[i]);\n\n\t/* Set the frame length for the configured rings\n\t * desired by the user\n\t */\n\tfor (i = 0; i < config->rx_ring_num; i++) {\n\t\t/* If rts_frm_len[i] == 0 then it is assumed that user not\n\t\t * specified frame length steering.\n\t\t * If the user provides the frame length then program\n\t\t * the rts_frm_len register for those values or else\n\t\t * leave it as it is.\n\t\t */\n\t\tif (rts_frm_len[i] != 0) {\n\t\t\twriteq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),\n\t\t\t       &bar0->rts_frm_len_n[i]);\n\t\t}\n\t}\n\n\t/* Disable differentiated services steering logic */\n\tfor (i = 0; i < 64; i++) {\n\t\tif (rts_ds_steer(nic, i, 0) == FAILURE) {\n\t\t\tDBG_PRINT(ERR_DBG,\n\t\t\t\t  \"%s: rts_ds_steer failed on codepoint %d\\n\",\n\t\t\t\t  dev->name, i);\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\n\t/* Program statistics memory */\n\twriteq(mac_control->stats_mem_phy, &bar0->stat_addr);\n\n\tif (nic->device_type == XFRAME_II_DEVICE) {\n\t\tval64 = STAT_BC(0x320);\n\t\twriteq(val64, &bar0->stat_byte_cnt);\n\t}\n\n\t/*\n\t * Initializing the sampling rate for the device to calculate the\n\t * bandwidth utilization.\n\t */\n\tval64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |\n\t\tMAC_RX_LINK_UTIL_VAL(rmac_util_period);\n\twriteq(val64, &bar0->mac_link_util);\n\n\t/*\n\t * Initializing the Transmit and Receive Traffic Interrupt\n\t * Scheme.\n\t */\n\n\t/* Initialize TTI */\n\tif (SUCCESS != init_tti(nic, nic->last_link_state, true))\n\t\treturn -ENODEV;\n\n\t/* RTI Initialization */\n\tif (nic->device_type == XFRAME_II_DEVICE) {\n\t\t/*\n\t\t * Programmed to generate Apprx 500 Intrs per\n\t\t * second\n\t\t */\n\t\tint count = (nic->config.bus_speed * 125)/4;\n\t\tval64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);\n\t} else\n\t\tval64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);\n\tval64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |\n\t\tRTI_DATA1_MEM_RX_URNG_B(0x10) |\n\t\tRTI_DATA1_MEM_RX_URNG_C(0x30) |\n\t\tRTI_DATA1_MEM_RX_TIMER_AC_EN;\n\n\twriteq(val64, &bar0->rti_data1_mem);\n\n\tval64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |\n\t\tRTI_DATA2_MEM_RX_UFC_B(0x2) ;\n\tif (nic->config.intr_type == MSI_X)\n\t\tval64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |\n\t\t\t  RTI_DATA2_MEM_RX_UFC_D(0x40));\n\telse\n\t\tval64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |\n\t\t\t  RTI_DATA2_MEM_RX_UFC_D(0x80));\n\twriteq(val64, &bar0->rti_data2_mem);\n\n\tfor (i = 0; i < config->rx_ring_num; i++) {\n\t\tval64 = RTI_CMD_MEM_WE |\n\t\t\tRTI_CMD_MEM_STROBE_NEW_CMD |\n\t\t\tRTI_CMD_MEM_OFFSET(i);\n\t\twriteq(val64, &bar0->rti_command_mem);\n\n\t\t/*\n\t\t * Once the operation completes, the Strobe bit of the\n\t\t * command register will be reset. We poll for this\n\t\t * particular condition. We wait for a maximum of 500ms\n\t\t * for the operation to complete, if it's not complete\n\t\t * by then we return error.\n\t\t */\n\t\ttime = 0;\n\t\twhile (true) {\n\t\t\tval64 = readq(&bar0->rti_command_mem);\n\t\t\tif (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))\n\t\t\t\tbreak;\n\n\t\t\tif (time > 10) {\n\t\t\t\tDBG_PRINT(ERR_DBG, \"%s: RTI init failed\\n\",\n\t\t\t\t\t  dev->name);\n\t\t\t\treturn -ENODEV;\n\t\t\t}\n\t\t\ttime++;\n\t\t\tmsleep(50);\n\t\t}\n\t}\n\n\t/*\n\t * Initializing proper values as Pause threshold into all\n\t * the 8 Queues on Rx side.\n\t */\n\twriteq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);\n\twriteq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);\n\n\t/* Disable RMAC PAD STRIPPING */\n\tadd = &bar0->mac_cfg;\n\tval64 = readq(&bar0->mac_cfg);\n\tval64 &= ~(MAC_CFG_RMAC_STRIP_PAD);\n\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\twritel((u32) (val64), add);\n\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\twritel((u32) (val64 >> 32), (add + 4));\n\tval64 = readq(&bar0->mac_cfg);\n\n\t/* Enable FCS stripping by adapter */\n\tadd = &bar0->mac_cfg;\n\tval64 = readq(&bar0->mac_cfg);\n\tval64 |= MAC_CFG_RMAC_STRIP_FCS;\n\tif (nic->device_type == XFRAME_II_DEVICE)\n\t\twriteq(val64, &bar0->mac_cfg);\n\telse {\n\t\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\t\twritel((u32) (val64), add);\n\t\twriteq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);\n\t\twritel((u32) (val64 >> 32), (add + 4));\n\t}\n\n\t/*\n\t * Set the time value to be inserted in the pause frame\n\t * generated by xena.\n\t */\n\tval64 = readq(&bar0->rmac_pause_cfg);\n\tval64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));\n\tval64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);\n\twriteq(val64, &bar0->rmac_pause_cfg);\n\n\t/*\n\t * Set the Threshold Limit for Generating the pause frame\n\t * If the amount of data in any Queue exceeds ratio of\n\t * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256\n\t * pause frame is generated\n\t */\n\tval64 = 0;\n\tfor (i = 0; i < 4; i++) {\n\t\tval64 |= (((u64)0xFF00 |\n\t\t\t   nic->mac_control.mc_pause_threshold_q0q3)\n\t\t\t  << (i * 2 * 8));\n\t}\n\twriteq(val64, &bar0->mc_pause_thresh_q0q3);\n\n\tval64 = 0;\n\tfor (i = 0; i < 4; i++) {\n\t\tval64 |= (((u64)0xFF00 |\n\t\t\t   nic->mac_control.mc_pause_threshold_q4q7)\n\t\t\t  << (i * 2 * 8));\n\t}\n\twriteq(val64, &bar0->mc_pause_thresh_q4q7);\n\n\t/*\n\t * TxDMA will stop Read request if the number of read split has\n\t * exceeded the limit pointed by shared_splits\n\t */\n\tval64 = readq(&bar0->pic_control);\n\tval64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);\n\twriteq(val64, &bar0->pic_control);\n\n\tif (nic->config.bus_speed == 266) {\n\t\twriteq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);\n\t\twriteq(0x0, &bar0->read_retry_delay);\n\t\twriteq(0x0, &bar0->write_retry_delay);\n\t}\n\n\t/*\n\t * Programming the Herc to split every write transaction\n\t * that does not start on an ADB to reduce disconnects.\n\t */\n\tif (nic->device_type == XFRAME_II_DEVICE) {\n\t\tval64 = FAULT_BEHAVIOUR | EXT_REQ_EN |\n\t\t\tMISC_LINK_STABILITY_PRD(3);\n\t\twriteq(val64, &bar0->misc_control);\n\t\tval64 = readq(&bar0->pic_control2);\n\t\tval64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));\n\t\twriteq(val64, &bar0->pic_control2);\n\t}\n\tif (strstr(nic->product_name, \"CX4\")) {\n\t\tval64 = TMAC_AVG_IPG(0x17);\n\t\twriteq(val64, &bar0->tmac_avg_ipg);\n\t}\n\n\treturn SUCCESS;\n}",
        "static int dsa_realloc_skb(struct sk_buff *skb, struct net_device *dev)\n{\n\tint needed_headroom = dev->needed_headroom;\n\tint needed_tailroom = dev->needed_tailroom;\n": "static int dsa_realloc_skb(struct sk_buff *skb, struct net_device *dev)\n{\n\tint needed_headroom = dev->needed_headroom;\n\tint needed_tailroom = dev->needed_tailroom;\n\n\t/* For tail taggers, we need to pad short frames ourselves, to ensure\n\t * that the tail tag does not fail at its role of being at the end of\n\t * the packet, once the master interface pads the frame. Account for\n\t * that pad length here, and pad later.\n\t */\n\tif (unlikely(needed_tailroom && skb->len < ETH_ZLEN))\n\t\tneeded_tailroom += ETH_ZLEN - skb->len;\n\t/* skb_headroom() returns unsigned int... */\n\tneeded_headroom = max_t(int, needed_headroom - skb_headroom(skb), 0);\n\tneeded_tailroom = max_t(int, needed_tailroom - skb_tailroom(skb), 0);\n\n\tif (likely(!needed_headroom && !needed_tailroom && !skb_cloned(skb)))\n\t\t/* No reallocation needed, yay! */\n\t\treturn 0;\n\n\treturn pskb_expand_head(skb, needed_headroom, needed_tailroom,\n\t\t\t\tGFP_ATOMIC);\n}",
        "static void __attribute__((__flatten__)) guest_code(struct svm_test_data *svm)\n{\n\tunsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];\n\tstruct vmcb *vmcb = svm->vmcb;\n\tstruct hv_enlightenments *hve =": "static void __attribute__((__flatten__)) guest_code(struct svm_test_data *svm)\n{\n\tunsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];\n\tstruct vmcb *vmcb = svm->vmcb;\n\tstruct hv_enlightenments *hve =\n\t\t(struct hv_enlightenments *)vmcb->control.reserved_sw;\n\n\tGUEST_SYNC(1);\n\n\twrmsr(HV_X64_MSR_GUEST_OS_ID, (u64)0x8100 << 48);\n\n\tGUEST_ASSERT(svm->vmcb_gpa);\n\t/* Prepare for L2 execution. */\n\tgeneric_svm_setup(svm, l2_guest_code,\n\t\t\t  &l2_guest_stack[L2_GUEST_STACK_SIZE]);\n\n\tGUEST_SYNC(2);\n\trun_guest(vmcb, svm->vmcb_gpa);\n\tGUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_VMMCALL);\n\tGUEST_SYNC(4);\n\tvmcb->save.rip += 3;\n\n\t/* Intercept RDMSR 0xc0000100 */\n\tvmcb->control.intercept |= 1ULL << INTERCEPT_MSR_PROT;\n\tset_bit(2 * (MSR_FS_BASE & 0x1fff), svm->msr + 0x800);\n\trun_guest(vmcb, svm->vmcb_gpa);\n\tGUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_MSR);\n\tvmcb->save.rip += 2; /* rdmsr */\n\n\t/* Enable enlightened MSR bitmap */\n\thve->hv_enlightenments_control.msr_bitmap = 1;\n\trun_guest(vmcb, svm->vmcb_gpa);\n\tGUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_MSR);\n\tvmcb->save.rip += 2; /* rdmsr */\n\n\t/* Intercept RDMSR 0xc0000101 without telling KVM about it */\n\tset_bit(2 * (MSR_GS_BASE & 0x1fff), svm->msr + 0x800);\n\t/* Make sure HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP is set */\n\tvmcb->control.clean |= VMCB_HV_NESTED_ENLIGHTENMENTS;\n\trun_guest(vmcb, svm->vmcb_gpa);\n\t/* Make sure we don't see SVM_EXIT_MSR here so eMSR bitmap works */\n\tGUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_VMMCALL);\n\tvmcb->save.rip += 3; /* vmcall */\n\n\t/* Now tell KVM we've changed MSR-Bitmap */\n\tvmcb->control.clean &= ~VMCB_HV_NESTED_ENLIGHTENMENTS;\n\trun_guest(vmcb, svm->vmcb_gpa);\n\tGUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_MSR);\n\tvmcb->save.rip += 2; /* rdmsr */\n\n\trun_guest(vmcb, svm->vmcb_gpa);\n\tGUEST_ASSERT(vmcb->control.exit_code == SVM_EXIT_VMMCALL);\n\tGUEST_SYNC(6);\n\n\tGUEST_DONE();\n}",
        "static void __mace_set_address(struct net_device *dev, const void *addr)\n{\n    struct mace_data *mp = netdev_priv(dev);\n    volatile struct mace __iomem *mb = mp->mace;\n    const unsigned char *p = addr;": "static void __mace_set_address(struct net_device *dev, const void *addr)\n{\n    struct mace_data *mp = netdev_priv(dev);\n    volatile struct mace __iomem *mb = mp->mace;\n    const unsigned char *p = addr;\n    u8 macaddr[ETH_ALEN];\n    int i;\n\n    /* load up the hardware address */\n    if (mp->chipid == BROKEN_ADDRCHG_REV)\n\tout_8(&mb->iac, PHYADDR);\n    else {\n\tout_8(&mb->iac, ADDRCHG | PHYADDR);\n\twhile ((in_8(&mb->iac) & ADDRCHG) != 0)\n\t    ;\n    }\n    for (i = 0; i < 6; ++i)\n        out_8(&mb->padr, macaddr[i] = p[i]);\n\n    eth_hw_addr_set(dev, macaddr);\n\n    if (mp->chipid != BROKEN_ADDRCHG_REV)\n        out_8(&mb->iac, 0);\n}",
        "static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)\n{\n\tstruct v4l2_subdev *sd = &chip->sd;\n\n\t/* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */": "static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)\n{\n\tstruct v4l2_subdev *sd = &chip->sd;\n\n\t/* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */\n\t/* If auto-muting is disabled, we can hear a signal of degrading quality. */\n\tif (tda9874a_mode) {\n\t\tif(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */\n\t\t\ttda9874a_NCONR &= 0xfe; /* enable */\n\t\telse\n\t\t\ttda9874a_NCONR |= 0x01; /* disable */\n\t\tchip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);\n\t}\n\n\t/* Note: TDA9874A supports automatic FM dematrixing (FMMR register)\n\t * and has auto-select function for audio output (AOSR register).\n\t * Old TDA9874H doesn't support these features.\n\t * TDA9874A also has additional mono output pin (OUTM), which\n\t * on same (all?) tv-cards is not used, anyway (as well as MONOIN).\n\t */\n\tif(tda9874a_dic == 0x11) {\n\t\tint aosr = 0x80;\n\t\tint mdacosr = (tda9874a_mode) ? 0x82:0x80;\n\n\t\tswitch(mode) {\n\t\tcase V4L2_TUNER_MODE_MONO:\n\t\tcase V4L2_TUNER_MODE_STEREO:\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_LANG1:\n\t\t\taosr = 0x80; /* auto-select, dual A/A */\n\t\t\tmdacosr = (tda9874a_mode) ? 0x82:0x80;\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_LANG2:\n\t\t\taosr = 0xa0; /* auto-select, dual B/B */\n\t\t\tmdacosr = (tda9874a_mode) ? 0x83:0x81;\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_LANG1_LANG2:\n\t\t\taosr = 0x00; /* always route L to L and R to R */\n\t\t\tmdacosr = (tda9874a_mode) ? 0x82:0x80;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn;\n\t\t}\n\t\tchip_write(chip, TDA9874A_AOSR, aosr);\n\t\tchip_write(chip, TDA9874A_MDACOSR, mdacosr);\n\n\t\tv4l2_dbg(1, debug, sd,\n\t\t\t\"tda9874a_setaudmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\\n\",\n\t\t\tmode, aosr, mdacosr);\n\n\t} else { /* dic == 0x07 */\n\t\tint fmmr,aosr;\n\n\t\tswitch(mode) {\n\t\tcase V4L2_TUNER_MODE_MONO:\n\t\t\tfmmr = 0x00; /* mono */\n\t\t\taosr = 0x10; /* A/A */\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_STEREO:\n\t\t\tif(tda9874a_mode) {\n\t\t\t\tfmmr = 0x00;\n\t\t\t\taosr = 0x00; /* handled by NICAM auto-mute */\n\t\t\t} else {\n\t\t\t\tfmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */\n\t\t\t\taosr = 0x00;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_LANG1:\n\t\t\tfmmr = 0x02; /* dual */\n\t\t\taosr = 0x10; /* dual A/A */\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_LANG2:\n\t\t\tfmmr = 0x02; /* dual */\n\t\t\taosr = 0x20; /* dual B/B */\n\t\t\tbreak;\n\t\tcase V4L2_TUNER_MODE_LANG1_LANG2:\n\t\t\tfmmr = 0x02; /* dual */\n\t\t\taosr = 0x00; /* dual A/B */\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn;\n\t\t}\n\t\tchip_write(chip, TDA9874A_FMMR, fmmr);\n\t\tchip_write(chip, TDA9874A_AOSR, aosr);\n\n\t\tv4l2_dbg(1, debug, sd,\n\t\t\t\"tda9874a_setaudmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\\n\",\n\t\t\tmode, fmmr, aosr);\n\t}\n}",
        "static int bredr_inquiry(struct hci_request *req, unsigned long opt)\n{\n\tu8 length = opt;\n\tconst u8 giac[3] = { 0x33, 0x8b, 0x9e };\n\tconst u8 liac[3] = { 0x00, 0x8b, 0x9e };": "static int bredr_inquiry(struct hci_request *req, unsigned long opt)\n{\n\tu8 length = opt;\n\tconst u8 giac[3] = { 0x33, 0x8b, 0x9e };\n\tconst u8 liac[3] = { 0x00, 0x8b, 0x9e };\n\tstruct hci_cp_inquiry cp;\n\n\tif (test_bit(HCI_INQUIRY, &req->hdev->flags))\n\t\treturn 0;\n\n\tbt_dev_dbg(req->hdev, \"\");\n\n\thci_dev_lock(req->hdev);\n\thci_inquiry_cache_flush(req->hdev);\n\thci_dev_unlock(req->hdev);\n\n\tmemset(&cp, 0, sizeof(cp));\n\n\tif (req->hdev->discovery.limited)\n\t\tmemcpy(&cp.lap, liac, sizeof(cp.lap));\n\telse\n\t\tmemcpy(&cp.lap, giac, sizeof(cp.lap));\n\n\tcp.length = length;\n\n\thci_req_add(req, HCI_OP_INQUIRY, sizeof(cp), &cp);\n\n\treturn 0;\n}",
        "static inline void end_verification_log(unsigned int tid, unsigned nr_anamolies)\n{\n\tFILE *f = fp[tid];\n\tchar logfile[30];\n\tchar path[LOGDIR_NAME_SIZE + 30];": "static inline void end_verification_log(unsigned int tid, unsigned nr_anamolies)\n{\n\tFILE *f = fp[tid];\n\tchar logfile[30];\n\tchar path[LOGDIR_NAME_SIZE + 30];\n\tchar separator[] = \"/\";\n\n\tfclose(f);\n\n\tif (nr_anamolies == 0) {\n\t\tremove(path);\n\t\treturn;\n\t}\n\n\tsprintf(logfile, logfilename, tid);\n\tstrcpy(path, logdir);\n\tstrcat(path, separator);\n\tstrcat(path, logfile);\n\n\tprintf(\"Thread %02d chunk has %d corrupted words. For details check %s\\n\",\n\t\ttid, nr_anamolies, path);\n}",
        "static void sbefifo_collect_async_ffdc(struct sbefifo *sbefifo)\n{\n\tstruct device *dev = &sbefifo->fsi_dev->dev;\n        struct iov_iter ffdc_iter;\n        struct kvec ffdc_iov;": "static void sbefifo_collect_async_ffdc(struct sbefifo *sbefifo)\n{\n\tstruct device *dev = &sbefifo->fsi_dev->dev;\n        struct iov_iter ffdc_iter;\n        struct kvec ffdc_iov;\n\t__be32 *ffdc;\n\tsize_t ffdc_sz;\n\t__be32 cmd[2];\n\tint rc;\n\n\tsbefifo->async_ffdc = false;\n\tffdc = vmalloc(SBEFIFO_MAX_FFDC_SIZE);\n\tif (!ffdc) {\n\t\tdev_err(dev, \"Failed to allocate SBE FFDC buffer\\n\");\n\t\treturn;\n\t}\n        ffdc_iov.iov_base = ffdc;\n\tffdc_iov.iov_len = SBEFIFO_MAX_FFDC_SIZE;\n        iov_iter_kvec(&ffdc_iter, WRITE, &ffdc_iov, 1, SBEFIFO_MAX_FFDC_SIZE);\n\tcmd[0] = cpu_to_be32(2);\n\tcmd[1] = cpu_to_be32(SBEFIFO_CMD_GET_SBE_FFDC);\n\trc = sbefifo_do_command(sbefifo, cmd, 2, &ffdc_iter);\n\tif (rc != 0) {\n\t\tdev_err(dev, \"Error %d retrieving SBE FFDC\\n\", rc);\n\t\tgoto bail;\n\t}\n\tffdc_sz = SBEFIFO_MAX_FFDC_SIZE - iov_iter_count(&ffdc_iter);\n\tffdc_sz /= sizeof(__be32);\n\trc = sbefifo_parse_status(dev, SBEFIFO_CMD_GET_SBE_FFDC, ffdc,\n\t\t\t\t  ffdc_sz, &ffdc_sz);\n\tif (rc != 0) {\n\t\tdev_err(dev, \"Error %d decoding SBE FFDC\\n\", rc);\n\t\tgoto bail;\n\t}\n\tif (ffdc_sz > 0)\n\t\tsbefifo_dump_ffdc(dev, ffdc, ffdc_sz, true);\n bail:\n\tvfree(ffdc);\n\n}",
        "static void cfi_tell_features(struct cfi_pri_intelext *extp)\n{\n\tint i;\n\tprintk(\"  Extended Query version %c.%c\\n\", extp->MajorVersion, extp->MinorVersion);\n\tprintk(\"  Feature/Command Support:      %4.4X\\n\", extp->FeatureSupport);": "static void cfi_tell_features(struct cfi_pri_intelext *extp)\n{\n\tint i;\n\tprintk(\"  Extended Query version %c.%c\\n\", extp->MajorVersion, extp->MinorVersion);\n\tprintk(\"  Feature/Command Support:      %4.4X\\n\", extp->FeatureSupport);\n\tprintk(\"     - Chip Erase:              %s\\n\", extp->FeatureSupport&1?\"supported\":\"unsupported\");\n\tprintk(\"     - Suspend Erase:           %s\\n\", extp->FeatureSupport&2?\"supported\":\"unsupported\");\n\tprintk(\"     - Suspend Program:         %s\\n\", extp->FeatureSupport&4?\"supported\":\"unsupported\");\n\tprintk(\"     - Legacy Lock/Unlock:      %s\\n\", extp->FeatureSupport&8?\"supported\":\"unsupported\");\n\tprintk(\"     - Queued Erase:            %s\\n\", extp->FeatureSupport&16?\"supported\":\"unsupported\");\n\tprintk(\"     - Instant block lock:      %s\\n\", extp->FeatureSupport&32?\"supported\":\"unsupported\");\n\tprintk(\"     - Protection Bits:         %s\\n\", extp->FeatureSupport&64?\"supported\":\"unsupported\");\n\tprintk(\"     - Page-mode read:          %s\\n\", extp->FeatureSupport&128?\"supported\":\"unsupported\");\n\tprintk(\"     - Synchronous read:        %s\\n\", extp->FeatureSupport&256?\"supported\":\"unsupported\");\n\tprintk(\"     - Simultaneous operations: %s\\n\", extp->FeatureSupport&512?\"supported\":\"unsupported\");\n\tprintk(\"     - Extended Flash Array:    %s\\n\", extp->FeatureSupport&1024?\"supported\":\"unsupported\");\n\tfor (i=11; i<32; i++) {\n\t\tif (extp->FeatureSupport & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X:      supported\\n\", i);\n\t}\n\n\tprintk(\"  Supported functions after Suspend: %2.2X\\n\", extp->SuspendCmdSupport);\n\tprintk(\"     - Program after Erase Suspend: %s\\n\", extp->SuspendCmdSupport&1?\"supported\":\"unsupported\");\n\tfor (i=1; i<8; i++) {\n\t\tif (extp->SuspendCmdSupport & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X:               supported\\n\", i);\n\t}\n\n\tprintk(\"  Block Status Register Mask: %4.4X\\n\", extp->BlkStatusRegMask);\n\tprintk(\"     - Lock Bit Active:      %s\\n\", extp->BlkStatusRegMask&1?\"yes\":\"no\");\n\tprintk(\"     - Lock-Down Bit Active: %s\\n\", extp->BlkStatusRegMask&2?\"yes\":\"no\");\n\tfor (i=2; i<3; i++) {\n\t\tif (extp->BlkStatusRegMask & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X Active: yes\\n\",i);\n\t}\n\tprintk(\"     - EFA Lock Bit:         %s\\n\", extp->BlkStatusRegMask&16?\"yes\":\"no\");\n\tprintk(\"     - EFA Lock-Down Bit:    %s\\n\", extp->BlkStatusRegMask&32?\"yes\":\"no\");\n\tfor (i=6; i<16; i++) {\n\t\tif (extp->BlkStatusRegMask & (1<<i))\n\t\t\tprintk(\"     - Unknown Bit %X Active: yes\\n\",i);\n\t}\n\n\tprintk(\"  Vcc Logic Supply Optimum Program/Erase Voltage: %d.%d V\\n\",\n\t       extp->VccOptimal >> 4, extp->VccOptimal & 0xf);\n\tif (extp->VppOptimal)\n\t\tprintk(\"  Vpp Programming Supply Optimum Program/Erase Voltage: %d.%d V\\n\",\n\t\t       extp->VppOptimal >> 4, extp->VppOptimal & 0xf);\n}",
        "static void fwtty_emit_breaks(struct work_struct *work)\n{\n\tstruct fwtty_port *port = to_port(to_delayed_work(work), emit_breaks);\n\tstatic const char buf[16];\n\tunsigned long now = jiffies;": "static void fwtty_emit_breaks(struct work_struct *work)\n{\n\tstruct fwtty_port *port = to_port(to_delayed_work(work), emit_breaks);\n\tstatic const char buf[16];\n\tunsigned long now = jiffies;\n\tunsigned long elapsed = now - port->break_last;\n\tint n, t, c, brk = 0;\n\n\t/* generate breaks at the line rate (but at least 1) */\n\tn = (elapsed * port->cps) / HZ + 1;\n\tport->break_last = now;\n\n\tfwtty_dbg(port, \"sending %d brks\\n\", n);\n\n\twhile (n) {\n\t\tt = min(n, 16);\n\t\tc = tty_insert_flip_string_fixed_flag(&port->port, buf,\n\t\t\t\t\t\t      TTY_BREAK, t);\n\t\tn -= c;\n\t\tbrk += c;\n\t\tif (c < t)\n\t\t\tbreak;\n\t}\n\ttty_flip_buffer_push(&port->port);\n\n\tif (port->mstatus & (UART_LSR_BI << 24))\n\t\tschedule_delayed_work(&port->emit_breaks, FREQ_BREAKS);\n\tport->icount.brk += brk;\n}",
        "static int power_down_device(struct drxk_state *state)\n{\n\t/* Power down to requested mode */\n\t/* Backup some register settings */\n\t/* Set pins with possible pull-ups connected to them in input mode */": "static int power_down_device(struct drxk_state *state)\n{\n\t/* Power down to requested mode */\n\t/* Backup some register settings */\n\t/* Set pins with possible pull-ups connected to them in input mode */\n\t/* Analog power down */\n\t/* ADC power down */\n\t/* Power down device */\n\tint status;\n\n\tdprintk(1, \"\\n\");\n\tif (state->m_b_p_down_open_bridge) {\n\t\t/* Open I2C bridge before power down of DRXK */\n\t\tstatus = ConfigureI2CBridge(state, true);\n\t\tif (status < 0)\n\t\t\tgoto error;\n\t}\n\t/* driver 0.9.0 */\n\tstatus = dvbt_enable_ofdm_token_ring(state, false);\n\tif (status < 0)\n\t\tgoto error;\n\n\tstatus = write16(state, SIO_CC_PWD_MODE__A,\n\t\t\t SIO_CC_PWD_MODE_LEVEL_CLOCK);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);\n\tif (status < 0)\n\t\tgoto error;\n\tstate->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;\n\tstatus = hi_cfg_command(state);\nerror:\n\tif (status < 0)\n\t\tpr_err(\"Error %d on %s\\n\", status, __func__);\n\n\treturn status;\n}",
        "static int xdp_umem_reg(struct xdp_umem *umem, struct xdp_umem_reg *mr)\n{\n\tu32 npgs_rem, chunk_size = mr->chunk_size, headroom = mr->headroom;\n\tbool unaligned_chunks = mr->flags & XDP_UMEM_UNALIGNED_CHUNK_FLAG;\n\tu64 npgs, addr = mr->addr, size = mr->len;": "static int xdp_umem_reg(struct xdp_umem *umem, struct xdp_umem_reg *mr)\n{\n\tu32 npgs_rem, chunk_size = mr->chunk_size, headroom = mr->headroom;\n\tbool unaligned_chunks = mr->flags & XDP_UMEM_UNALIGNED_CHUNK_FLAG;\n\tu64 npgs, addr = mr->addr, size = mr->len;\n\tunsigned int chunks, chunks_rem;\n\tint err;\n\n\tif (chunk_size < XDP_UMEM_MIN_CHUNK_SIZE || chunk_size > PAGE_SIZE) {\n\t\t/* Strictly speaking we could support this, if:\n\t\t * - huge pages, or*\n\t\t * - using an IOMMU, or\n\t\t * - making sure the memory area is consecutive\n\t\t * but for now, we simply say \"computer says no\".\n\t\t */\n\t\treturn -EINVAL;\n\t}\n\n\tif (mr->flags & ~XDP_UMEM_UNALIGNED_CHUNK_FLAG)\n\t\treturn -EINVAL;\n\n\tif (!unaligned_chunks && !is_power_of_2(chunk_size))\n\t\treturn -EINVAL;\n\n\tif (!PAGE_ALIGNED(addr)) {\n\t\t/* Memory area has to be page size aligned. For\n\t\t * simplicity, this might change.\n\t\t */\n\t\treturn -EINVAL;\n\t}\n\n\tif ((addr + size) < addr)\n\t\treturn -EINVAL;\n\n\tnpgs = div_u64_rem(size, PAGE_SIZE, &npgs_rem);\n\tif (npgs_rem)\n\t\tnpgs++;\n\tif (npgs > U32_MAX)\n\t\treturn -EINVAL;\n\n\tchunks = (unsigned int)div_u64_rem(size, chunk_size, &chunks_rem);\n\tif (chunks == 0)\n\t\treturn -EINVAL;\n\n\tif (!unaligned_chunks && chunks_rem)\n\t\treturn -EINVAL;\n\n\tif (headroom >= chunk_size - XDP_PACKET_HEADROOM)\n\t\treturn -EINVAL;\n\n\tumem->size = size;\n\tumem->headroom = headroom;\n\tumem->chunk_size = chunk_size;\n\tumem->chunks = chunks;\n\tumem->npgs = (u32)npgs;\n\tumem->pgs = NULL;\n\tumem->user = NULL;\n\tumem->flags = mr->flags;\n\n\tINIT_LIST_HEAD(&umem->xsk_dma_list);\n\trefcount_set(&umem->users, 1);\n\n\terr = xdp_umem_account_pages(umem);\n\tif (err)\n\t\treturn err;\n\n\terr = xdp_umem_pin_pages(umem, (unsigned long)addr);\n\tif (err)\n\t\tgoto out_account;\n\n\terr = xdp_umem_addr_map(umem, umem->pgs, umem->npgs);\n\tif (err)\n\t\tgoto out_unpin;\n\n\treturn 0;\n\nout_unpin:\n\txdp_umem_unpin_pages(umem);\nout_account:\n\txdp_umem_unaccount_pages(umem);\n\treturn err;\n}",
        "static int test2_prpw_aligned_10327bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(start_addr[0] + 0x6000) & ~(ADI_BLKSZ - 1);": "static int test2_prpw_aligned_10327bytes(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(start_addr[0] + 0x6000) & ~(ADI_BLKSZ - 1);\n\tunsigned char version[TEST2_VERSION_SZ],\n\t\texpected_version[TEST2_VERSION_SZ];\n\tloff_t offset;\n\tint ret, i;\n\n\tfor (i = 0; i < TEST2_VERSION_SZ; i++) {\n\t\tversion[i] = random_version();\n\t\texpected_version[i] = version[i];\n\t}\n\n\toffset = paddr / ADI_BLKSZ;\n\n\tret = pwrite_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tret = pread_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tfor (i = 0; i < TEST2_VERSION_SZ; i++) {\n\t\tif (expected_version[i] != version[i]) {\n\t\t\tDEBUG_PRINT_L2(\n\t\t\t\t\"\\tExpected version %d but read version %d\\n\",\n\t\t\t\texpected_version, version[0]);\n\t\t\tTEST_STEP_FAILURE(-expected_version[i]);\n\t\t}\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static void test_lpm_map(int keysize)\n{\n\tLIBBPF_OPTS(bpf_map_create_opts, opts, .map_flags = BPF_F_NO_PREALLOC);\n\tvolatile size_t n_matches, n_matches_after_delete;\n\tsize_t i, j, n_nodes, n_lookups;": "static void test_lpm_map(int keysize)\n{\n\tLIBBPF_OPTS(bpf_map_create_opts, opts, .map_flags = BPF_F_NO_PREALLOC);\n\tvolatile size_t n_matches, n_matches_after_delete;\n\tsize_t i, j, n_nodes, n_lookups;\n\tstruct tlpm_node *t, *list = NULL;\n\tstruct bpf_lpm_trie_key *key;\n\tuint8_t *data, *value;\n\tint r, map;\n\n\t/* Compare behavior of tlpm vs. bpf-lpm. Create a randomized set of\n\t * prefixes and insert it into both tlpm and bpf-lpm. Then run some\n\t * randomized lookups and verify both maps return the same result.\n\t */\n\n\tn_matches = 0;\n\tn_matches_after_delete = 0;\n\tn_nodes = 1 << 8;\n\tn_lookups = 1 << 16;\n\n\tdata = alloca(keysize);\n\tmemset(data, 0, keysize);\n\n\tvalue = alloca(keysize + 1);\n\tmemset(value, 0, keysize + 1);\n\n\tkey = alloca(sizeof(*key) + keysize);\n\tmemset(key, 0, sizeof(*key) + keysize);\n\n\tmap = bpf_map_create(BPF_MAP_TYPE_LPM_TRIE, NULL,\n\t\t\t     sizeof(*key) + keysize,\n\t\t\t     keysize + 1,\n\t\t\t     4096,\n\t\t\t     &opts);\n\tassert(map >= 0);\n\n\tfor (i = 0; i < n_nodes; ++i) {\n\t\tfor (j = 0; j < keysize; ++j)\n\t\t\tvalue[j] = rand() & 0xff;\n\t\tvalue[keysize] = rand() % (8 * keysize + 1);\n\n\t\tlist = tlpm_add(list, value, value[keysize]);\n\n\t\tkey->prefixlen = value[keysize];\n\t\tmemcpy(key->data, value, keysize);\n\t\tr = bpf_map_update_elem(map, key, value, 0);\n\t\tassert(!r);\n\t}\n\n\tfor (i = 0; i < n_lookups; ++i) {\n\t\tfor (j = 0; j < keysize; ++j)\n\t\t\tdata[j] = rand() & 0xff;\n\n\t\tt = tlpm_match(list, data, 8 * keysize);\n\n\t\tkey->prefixlen = 8 * keysize;\n\t\tmemcpy(key->data, data, keysize);\n\t\tr = bpf_map_lookup_elem(map, key, value);\n\t\tassert(!r || errno == ENOENT);\n\t\tassert(!t == !!r);\n\n\t\tif (t) {\n\t\t\t++n_matches;\n\t\t\tassert(t->n_bits == value[keysize]);\n\t\t\tfor (j = 0; j < t->n_bits; ++j)\n\t\t\t\tassert((t->key[j / 8] & (1 << (7 - j % 8))) ==\n\t\t\t\t       (value[j / 8] & (1 << (7 - j % 8))));\n\t\t}\n\t}\n\n\t/* Remove the first half of the elements in the tlpm and the\n\t * corresponding nodes from the bpf-lpm.  Then run the same\n\t * large number of random lookups in both and make sure they match.\n\t * Note: we need to count the number of nodes actually inserted\n\t * since there may have been duplicates.\n\t */\n\tfor (i = 0, t = list; t; i++, t = t->next)\n\t\t;\n\tfor (j = 0; j < i / 2; ++j) {\n\t\tkey->prefixlen = list->n_bits;\n\t\tmemcpy(key->data, list->key, keysize);\n\t\tr = bpf_map_delete_elem(map, key);\n\t\tassert(!r);\n\t\tlist = tlpm_delete(list, list->key, list->n_bits);\n\t\tassert(list);\n\t}\n\tfor (i = 0; i < n_lookups; ++i) {\n\t\tfor (j = 0; j < keysize; ++j)\n\t\t\tdata[j] = rand() & 0xff;\n\n\t\tt = tlpm_match(list, data, 8 * keysize);\n\n\t\tkey->prefixlen = 8 * keysize;\n\t\tmemcpy(key->data, data, keysize);\n\t\tr = bpf_map_lookup_elem(map, key, value);\n\t\tassert(!r || errno == ENOENT);\n\t\tassert(!t == !!r);\n\n\t\tif (t) {\n\t\t\t++n_matches_after_delete;\n\t\t\tassert(t->n_bits == value[keysize]);\n\t\t\tfor (j = 0; j < t->n_bits; ++j)\n\t\t\t\tassert((t->key[j / 8] & (1 << (7 - j % 8))) ==\n\t\t\t\t       (value[j / 8] & (1 << (7 - j % 8))));\n\t\t}\n\t}\n\n\tclose(map);\n\ttlpm_clear(list);\n\n\t/* With 255 random nodes in the map, we are pretty likely to match\n\t * something on every lookup. For statistics, use this:\n\t *\n\t *     printf(\"          nodes: %zu\\n\"\n\t *            \"        lookups: %zu\\n\"\n\t *            \"        matches: %zu\\n\"\n\t *            \"matches(delete): %zu\\n\",\n\t *            n_nodes, n_lookups, n_matches, n_matches_after_delete);\n\t */\n}",
        "static int armpmu_event_init(struct perf_event *event)\n{\n\tstruct arm_pmu *armpmu = to_arm_pmu(event->pmu);\n\n\t/*": "static int armpmu_event_init(struct perf_event *event)\n{\n\tstruct arm_pmu *armpmu = to_arm_pmu(event->pmu);\n\n\t/*\n\t * Reject CPU-affine events for CPUs that are of a different class to\n\t * that which this PMU handles. Process-following events (where\n\t * event->cpu == -1) can be migrated between CPUs, and thus we have to\n\t * reject them later (in armpmu_add) if they're scheduled on a\n\t * different class of CPU.\n\t */\n\tif (event->cpu != -1 &&\n\t\t!cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))\n\t\treturn -ENOENT;\n\n\t/* does not support taken branch sampling */\n\tif (has_branch_stack(event))\n\t\treturn -EOPNOTSUPP;\n\n\tif (armpmu->map_event(event) == -ENOENT)\n\t\treturn -ENOENT;\n\n\treturn __hw_perf_event_init(event);\n}",
        "static void __debug_check_no_obj_freed(const void *address, unsigned long size)\n{\n\tunsigned long flags, oaddr, saddr, eaddr, paddr, chunks;\n\tconst struct debug_obj_descr *descr;\n\tenum debug_obj_state state;": "static void __debug_check_no_obj_freed(const void *address, unsigned long size)\n{\n\tunsigned long flags, oaddr, saddr, eaddr, paddr, chunks;\n\tconst struct debug_obj_descr *descr;\n\tenum debug_obj_state state;\n\tstruct debug_bucket *db;\n\tstruct hlist_node *tmp;\n\tstruct debug_obj *obj;\n\tint cnt, objs_checked = 0;\n\n\tsaddr = (unsigned long) address;\n\teaddr = saddr + size;\n\tpaddr = saddr & ODEBUG_CHUNK_MASK;\n\tchunks = ((eaddr - paddr) + (ODEBUG_CHUNK_SIZE - 1));\n\tchunks >>= ODEBUG_CHUNK_SHIFT;\n\n\tfor (;chunks > 0; chunks--, paddr += ODEBUG_CHUNK_SIZE) {\n\t\tdb = get_bucket(paddr);\n\nrepeat:\n\t\tcnt = 0;\n\t\traw_spin_lock_irqsave(&db->lock, flags);\n\t\thlist_for_each_entry_safe(obj, tmp, &db->list, node) {\n\t\t\tcnt++;\n\t\t\toaddr = (unsigned long) obj->object;\n\t\t\tif (oaddr < saddr || oaddr >= eaddr)\n\t\t\t\tcontinue;\n\n\t\t\tswitch (obj->state) {\n\t\t\tcase ODEBUG_STATE_ACTIVE:\n\t\t\t\tdescr = obj->descr;\n\t\t\t\tstate = obj->state;\n\t\t\t\traw_spin_unlock_irqrestore(&db->lock, flags);\n\t\t\t\tdebug_print_object(obj, \"free\");\n\t\t\t\tdebug_object_fixup(descr->fixup_free,\n\t\t\t\t\t\t   (void *) oaddr, state);\n\t\t\t\tgoto repeat;\n\t\t\tdefault:\n\t\t\t\thlist_del(&obj->node);\n\t\t\t\t__free_object(obj);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\traw_spin_unlock_irqrestore(&db->lock, flags);\n\n\t\tif (cnt > debug_objects_maxchain)\n\t\t\tdebug_objects_maxchain = cnt;\n\n\t\tobjs_checked += cnt;\n\t}\n\n\tif (objs_checked > debug_objects_maxchecked)\n\t\tdebug_objects_maxchecked = objs_checked;\n\n\t/* Schedule work to actually kmem_cache_free() objects */\n\tif (!READ_ONCE(obj_freeing) && READ_ONCE(obj_nr_tofree)) {\n\t\tWRITE_ONCE(obj_freeing, true);\n\t\tschedule_delayed_work(&debug_obj_work, ODEBUG_FREE_WORK_DELAY);\n\t}\n}",
        "static int run_dir(const char *d)\n{\n\tchar filename[PATH_MAX];\n\tchar debugfile[PATH_MAX];\n\tstruct build_id bid;": "static int run_dir(const char *d)\n{\n\tchar filename[PATH_MAX];\n\tchar debugfile[PATH_MAX];\n\tstruct build_id bid;\n\tchar debuglink[PATH_MAX];\n\tchar expect_build_id[] = {\n\t\t0x5a, 0x0f, 0xd8, 0x82, 0xb5, 0x30, 0x84, 0x22,\n\t\t0x4b, 0xa4, 0x7b, 0x62, 0x4c, 0x55, 0xa4, 0x69,\n\t};\n\tchar expect_debuglink[PATH_MAX] = \"pe-file.exe.debug\";\n\tstruct dso *dso;\n\tstruct symbol *sym;\n\tint ret;\n\n\tscnprintf(filename, PATH_MAX, \"%s/pe-file.exe\", d);\n\tret = filename__read_build_id(filename, &bid);\n\tTEST_ASSERT_VAL(\"Failed to read build_id\",\n\t\t\tret == sizeof(expect_build_id));\n\tTEST_ASSERT_VAL(\"Wrong build_id\", !memcmp(bid.data, expect_build_id,\n\t\t\t\t\t\t  sizeof(expect_build_id)));\n\n\tret = filename__read_debuglink(filename, debuglink, PATH_MAX);\n\tTEST_ASSERT_VAL(\"Failed to read debuglink\", ret == 0);\n\tTEST_ASSERT_VAL(\"Wrong debuglink\",\n\t\t\t!strcmp(debuglink, expect_debuglink));\n\n\tscnprintf(debugfile, PATH_MAX, \"%s/%s\", d, debuglink);\n\tret = filename__read_build_id(debugfile, &bid);\n\tTEST_ASSERT_VAL(\"Failed to read debug file build_id\",\n\t\t\tret == sizeof(expect_build_id));\n\tTEST_ASSERT_VAL(\"Wrong build_id\", !memcmp(bid.data, expect_build_id,\n\t\t\t\t\t\t  sizeof(expect_build_id)));\n\n\tdso = dso__new(filename);\n\tTEST_ASSERT_VAL(\"Failed to get dso\", dso);\n\n\tret = dso__load_bfd_symbols(dso, debugfile);\n\tTEST_ASSERT_VAL(\"Failed to load symbols\", ret == 0);\n\n\tdso__sort_by_name(dso);\n\tsym = dso__find_symbol_by_name(dso, \"main\");\n\tTEST_ASSERT_VAL(\"Failed to find main\", sym);\n\tdso__delete(dso);\n\n\treturn TEST_OK;\n}",
        "static int subskeleton_lib_subresult(struct bpf_object *obj)\n{\n\tstruct test_subskeleton_lib *lib = test_subskeleton_lib__open(obj);\n\tint result;\n": "static int subskeleton_lib_subresult(struct bpf_object *obj)\n{\n\tstruct test_subskeleton_lib *lib = test_subskeleton_lib__open(obj);\n\tint result;\n\n\tif (!ASSERT_OK_PTR(lib, \"open subskeleton\"))\n\t\treturn -EINVAL;\n\n\tresult = *lib->bss.libout1;\n\tASSERT_EQ(result, 1 + 2 + 3 + 4 + 5 + 6, \"lib subresult\");\n\n\tASSERT_OK_PTR(lib->progs.lib_perf_handler, \"lib_perf_handler\");\n\tASSERT_STREQ(bpf_program__name(lib->progs.lib_perf_handler),\n\t\t     \"lib_perf_handler\", \"program name\");\n\n\tASSERT_OK_PTR(lib->maps.map1, \"map1\");\n\tASSERT_STREQ(bpf_map__name(lib->maps.map1), \"map1\", \"map name\");\n\n\tASSERT_EQ(*lib->data.var5, 5, \"__weak var5\");\n\tASSERT_EQ(*lib->data.var6, 6, \"extern var6\");\n\tASSERT_TRUE(*lib->kconfig.CONFIG_BPF_SYSCALL, \"CONFIG_BPF_SYSCALL\");\n\n\ttest_subskeleton_lib__destroy(lib);\n\treturn result;\n}",
        "static void PXC200_muxsel(struct bttv *btv, unsigned int input)\n{\n\tint rc;\n\tlong mux;\n\tint bitmask;": "static void PXC200_muxsel(struct bttv *btv, unsigned int input)\n{\n\tint rc;\n\tlong mux;\n\tint bitmask;\n\tunsigned char buf[2];\n\n\t/* Read PIC config to determine if this is a PXC200F */\n\t/* PX_I2C_CMD_CFG*/\n\tbuf[0]=0;\n\tbuf[1]=0;\n\trc=bttv_I2CWrite(btv,(PX_I2C_PIC<<1),buf[0],buf[1],1);\n\tif (rc) {\n\t\tpr_debug(\"%d: PXC200_muxsel: pic cfg write failed:%d\\n\",\n\t\t\t btv->c.nr, rc);\n\t  /* not PXC ? do nothing */\n\t\treturn;\n\t}\n\n\trc=bttv_I2CRead(btv,(PX_I2C_PIC<<1),NULL);\n\tif (!(rc & PX_CFG_PXC200F)) {\n\t\tpr_debug(\"%d: PXC200_muxsel: not PXC200F rc:%d\\n\",\n\t\t\t btv->c.nr, rc);\n\t\treturn;\n\t}\n\n\n\t/* The multiplexer in the 200F is handled by the GPIO port */\n\t/* get correct mapping between inputs  */\n\t/*  mux = bttv_tvcards[btv->type].muxsel[input] & 3; */\n\t/* ** not needed!?   */\n\tmux = input;\n\n\t/* make sure output pins are enabled */\n\t/* bitmask=0x30f; */\n\tbitmask=0x302;\n\t/* check whether we have a PXC200A */\n\tif (btv->cardid == PX_PXC200A_CARDID)  {\n\t   bitmask ^= 0x180; /* use 7 and 9, not 8 and 9 */\n\t   bitmask |= 7<<4; /* the DAC */\n\t}\n\tbtwrite(bitmask, BT848_GPIO_OUT_EN);\n\n\tbitmask = btread(BT848_GPIO_DATA);\n\tif (btv->cardid == PX_PXC200A_CARDID)\n\t  bitmask = (bitmask & ~0x280) | ((mux & 2) << 8) | ((mux & 1) << 7);\n\telse /* older device */\n\t  bitmask = (bitmask & ~0x300) | ((mux & 3) << 8);\n\tbtwrite(bitmask,BT848_GPIO_DATA);\n\n\t/*\n\t * Was \"to be safe, set the bt848 to input 0\"\n\t * Actually, since it's ok at load time, better not messing\n\t * with these bits (on PXC200AF you need to set mux 2 here)\n\t *\n\t * needed because bttv-driver sets mux before calling this function\n\t */\n\tif (btv->cardid == PX_PXC200A_CARDID)\n\t  btaor(2<<5, ~BT848_IFORM_MUXSEL, BT848_IFORM);\n\telse /* older device */\n\t  btand(~BT848_IFORM_MUXSEL,BT848_IFORM);\n\n\tpr_debug(\"%d: setting input channel to:%d\\n\", btv->c.nr, (int)mux);\n}",
        "static void samsung_banks_node_get(struct device *dev, struct samsung_pinctrl_drv_data *d)\n{\n\tconst char *suffix = \"-gpio-bank\";\n\tstruct samsung_pin_bank *bank;\n\tstruct fwnode_handle *child;": "static void samsung_banks_node_get(struct device *dev, struct samsung_pinctrl_drv_data *d)\n{\n\tconst char *suffix = \"-gpio-bank\";\n\tstruct samsung_pin_bank *bank;\n\tstruct fwnode_handle *child;\n\t/* Pin bank names are up to 4 characters */\n\tchar node_name[20];\n\tunsigned int i;\n\tsize_t len;\n\n\tbank = d->pin_banks;\n\tfor (i = 0; i < d->nr_banks; ++i, ++bank) {\n\t\tstrscpy(node_name, bank->name, sizeof(node_name));\n\t\tlen = strlcat(node_name, suffix, sizeof(node_name));\n\t\tif (len >= sizeof(node_name)) {\n\t\t\tdev_err(dev, \"Too long pin bank name '%s', ignoring\\n\",\n\t\t\t\tbank->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\tfor_each_gpiochip_node(dev, child) {\n\t\t\tstruct device_node *np = to_of_node(child);\n\n\t\t\tif (of_node_name_eq(np, node_name))\n\t\t\t\tbreak;\n\t\t\tif (of_node_name_eq(np, bank->name))\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (child)\n\t\t\tbank->fwnode = child;\n\t\telse\n\t\t\tdev_warn(dev, \"Missing node for bank %s - invalid DTB\\n\",\n\t\t\t\t bank->name);\n\t\t/* child reference dropped in samsung_drop_banks_of_node() */\n\t}\n}",
        "static int nv_loopback_test(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tstruct sk_buff *tx_skb, *rx_skb;": "static int nv_loopback_test(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tstruct sk_buff *tx_skb, *rx_skb;\n\tdma_addr_t test_dma_addr;\n\tu32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);\n\tu32 flags;\n\tint len, i, pkt_len;\n\tu8 *pkt_data;\n\tu32 filter_flags = 0;\n\tu32 misc1_flags = 0;\n\tint ret = 1;\n\n\tif (netif_running(dev)) {\n\t\tnv_disable_irq(dev);\n\t\tfilter_flags = readl(base + NvRegPacketFilterFlags);\n\t\tmisc1_flags = readl(base + NvRegMisc1);\n\t} else {\n\t\tnv_txrx_reset(dev);\n\t}\n\n\t/* reinit driver view of the rx queue */\n\tset_bufsize(dev);\n\tnv_init_ring(dev);\n\n\t/* setup hardware for loopback */\n\twritel(NVREG_MISC1_FORCE, base + NvRegMisc1);\n\twritel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);\n\n\t/* reinit nic view of the rx queue */\n\twritel(np->rx_buf_sz, base + NvRegOffloadConfig);\n\tsetup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);\n\twritel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),\n\t\tbase + NvRegRingSizes);\n\tpci_push(base);\n\n\t/* restart rx engine */\n\tnv_start_rxtx(dev);\n\n\t/* setup packet for tx */\n\tpkt_len = ETH_DATA_LEN;\n\ttx_skb = netdev_alloc_skb(dev, pkt_len);\n\tif (!tx_skb) {\n\t\tret = 0;\n\t\tgoto out;\n\t}\n\ttest_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data,\n\t\t\t\t       skb_tailroom(tx_skb),\n\t\t\t\t       DMA_FROM_DEVICE);\n\tif (unlikely(dma_mapping_error(&np->pci_dev->dev,\n\t\t\t\t       test_dma_addr))) {\n\t\tdev_kfree_skb_any(tx_skb);\n\t\tgoto out;\n\t}\n\tpkt_data = skb_put(tx_skb, pkt_len);\n\tfor (i = 0; i < pkt_len; i++)\n\t\tpkt_data[i] = (u8)(i & 0xff);\n\n\tif (!nv_optimized(np)) {\n\t\tnp->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);\n\t\tnp->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);\n\t} else {\n\t\tnp->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));\n\t\tnp->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));\n\t\tnp->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);\n\t}\n\twritel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);\n\tpci_push(get_hwbase(dev));\n\n\tmsleep(500);\n\n\t/* check for rx of the packet */\n\tif (!nv_optimized(np)) {\n\t\tflags = le32_to_cpu(np->rx_ring.orig[0].flaglen);\n\t\tlen = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);\n\n\t} else {\n\t\tflags = le32_to_cpu(np->rx_ring.ex[0].flaglen);\n\t\tlen = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);\n\t}\n\n\tif (flags & NV_RX_AVAIL) {\n\t\tret = 0;\n\t} else if (np->desc_ver == DESC_VER_1) {\n\t\tif (flags & NV_RX_ERROR)\n\t\t\tret = 0;\n\t} else {\n\t\tif (flags & NV_RX2_ERROR)\n\t\t\tret = 0;\n\t}\n\n\tif (ret) {\n\t\tif (len != pkt_len) {\n\t\t\tret = 0;\n\t\t} else {\n\t\t\trx_skb = np->rx_skb[0].skb;\n\t\t\tfor (i = 0; i < pkt_len; i++) {\n\t\t\t\tif (rx_skb->data[i] != (u8)(i & 0xff)) {\n\t\t\t\t\tret = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tdma_unmap_single(&np->pci_dev->dev, test_dma_addr,\n\t\t\t (skb_end_pointer(tx_skb) - tx_skb->data),\n\t\t\t DMA_TO_DEVICE);\n\tdev_kfree_skb_any(tx_skb);\n out:\n\t/* stop engines */\n\tnv_stop_rxtx(dev);\n\tnv_txrx_reset(dev);\n\t/* drain rx queue */\n\tnv_drain_rxtx(dev);\n\n\tif (netif_running(dev)) {\n\t\twritel(misc1_flags, base + NvRegMisc1);\n\t\twritel(filter_flags, base + NvRegPacketFilterFlags);\n\t\tnv_enable_irq(dev);\n\t}\n\n\treturn ret;\n}",
        "static int active_cacheline_insert(struct dma_debug_entry *entry)\n{\n\tphys_addr_t cln = to_cacheline_number(entry);\n\tunsigned long flags;\n\tint rc;": "static int active_cacheline_insert(struct dma_debug_entry *entry)\n{\n\tphys_addr_t cln = to_cacheline_number(entry);\n\tunsigned long flags;\n\tint rc;\n\n\t/* If the device is not writing memory then we don't have any\n\t * concerns about the cpu consuming stale data.  This mitigates\n\t * legitimate usages of overlapping mappings.\n\t */\n\tif (entry->direction == DMA_TO_DEVICE)\n\t\treturn 0;\n\n\tspin_lock_irqsave(&radix_lock, flags);\n\trc = radix_tree_insert(&dma_active_cacheline, cln, entry);\n\tif (rc == -EEXIST)\n\t\tactive_cacheline_inc_overlap(cln);\n\tspin_unlock_irqrestore(&radix_lock, flags);\n\n\treturn rc;\n}",
        "static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo)\n{\n\tu8 j;\n\tu8 temp_stage;\n\tu32 numsc;": "static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo)\n{\n\tu8 j;\n\tu8 temp_stage;\n\tu32 numsc;\n\tu32 num_total;\n\tu8 stage_id;\n\n\tnumsc  = 0;\n\tnum_total = pRaInfo->TOTAL * PT_PENALTY[5];\n\tfor (j = 0; j <= 4; j++) {\n\t\tnumsc += pRaInfo->RTY[j] * PT_PENALTY[j];\n\t\tif (numsc > num_total)\n\t\t\tbreak;\n\t}\n\n\tj = j >> 1;\n\ttemp_stage = (pRaInfo->PTStage + 1) >> 1;\n\tif (temp_stage > j)\n\t\tstage_id = temp_stage - j;\n\telse\n\t\tstage_id = 0;\n\n\tpRaInfo->PTSmoothFactor = (pRaInfo->PTSmoothFactor >> 1) + (pRaInfo->PTSmoothFactor >> 2) + stage_id * 16 + 2;\n\tif (pRaInfo->PTSmoothFactor > 192)\n\t\tpRaInfo->PTSmoothFactor = 192;\n\tstage_id = pRaInfo->PTSmoothFactor >> 6;\n\ttemp_stage = stage_id * 2;\n\tif (temp_stage != 0)\n\t\ttemp_stage -= 1;\n\tif (pRaInfo->DROP > 3)\n\t\ttemp_stage = 0;\n\tpRaInfo->PTStage = temp_stage;\n}",
        "static bool rx_get_frame(struct slgt_info *info)\n{\n\tunsigned int start, end;\n\tunsigned short status;\n\tunsigned int framesize = 0;": "static bool rx_get_frame(struct slgt_info *info)\n{\n\tunsigned int start, end;\n\tunsigned short status;\n\tunsigned int framesize = 0;\n\tunsigned long flags;\n\tstruct tty_struct *tty = info->port.tty;\n\tunsigned char addr_field = 0xff;\n\tunsigned int crc_size = 0;\n\n\tswitch (info->params.crc_type & HDLC_CRC_MASK) {\n\tcase HDLC_CRC_16_CCITT: crc_size = 2; break;\n\tcase HDLC_CRC_32_CCITT: crc_size = 4; break;\n\t}\n\ncheck_again:\n\n\tframesize = 0;\n\taddr_field = 0xff;\n\tstart = end = info->rbuf_current;\n\n\tfor (;;) {\n\t\tif (!desc_complete(info->rbufs[end]))\n\t\t\tgoto cleanup;\n\n\t\tif (framesize == 0 && info->params.addr_filter != 0xff)\n\t\t\taddr_field = info->rbufs[end].buf[0];\n\n\t\tframesize += desc_count(info->rbufs[end]);\n\n\t\tif (desc_eof(info->rbufs[end]))\n\t\t\tbreak;\n\n\t\tif (++end == info->rbuf_count)\n\t\t\tend = 0;\n\n\t\tif (end == info->rbuf_current) {\n\t\t\tif (info->rx_enabled){\n\t\t\t\tspin_lock_irqsave(&info->lock,flags);\n\t\t\t\trx_start(info);\n\t\t\t\tspin_unlock_irqrestore(&info->lock,flags);\n\t\t\t}\n\t\t\tgoto cleanup;\n\t\t}\n\t}\n\n\t/* status\n\t *\n\t * 15      buffer complete\n\t * 14..06  reserved\n\t * 05..04  residue\n\t * 02      eof (end of frame)\n\t * 01      CRC error\n\t * 00      abort\n\t */\n\tstatus = desc_status(info->rbufs[end]);\n\n\t/* ignore CRC bit if not using CRC (bit is undefined) */\n\tif ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)\n\t\tstatus &= ~BIT1;\n\n\tif (framesize == 0 ||\n\t\t (addr_field != 0xff && addr_field != info->params.addr_filter)) {\n\t\tfree_rbufs(info, start, end);\n\t\tgoto check_again;\n\t}\n\n\tif (framesize < (2 + crc_size) || status & BIT0) {\n\t\tinfo->icount.rxshort++;\n\t\tframesize = 0;\n\t} else if (status & BIT1) {\n\t\tinfo->icount.rxcrc++;\n\t\tif (!(info->params.crc_type & HDLC_CRC_RETURN_EX))\n\t\t\tframesize = 0;\n\t}\n\n#if SYNCLINK_GENERIC_HDLC\n\tif (framesize == 0) {\n\t\tinfo->netdev->stats.rx_errors++;\n\t\tinfo->netdev->stats.rx_frame_errors++;\n\t}\n#endif\n\n\tDBGBH((\"%s rx frame status=%04X size=%d\\n\",\n\t\tinfo->device_name, status, framesize));\n\tDBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), \"rx\");\n\n\tif (framesize) {\n\t\tif (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {\n\t\t\tframesize -= crc_size;\n\t\t\tcrc_size = 0;\n\t\t}\n\n\t\tif (framesize > info->max_frame_size + crc_size)\n\t\t\tinfo->icount.rxlong++;\n\t\telse {\n\t\t\t/* copy dma buffer(s) to contiguous temp buffer */\n\t\t\tint copy_count = framesize;\n\t\t\tint i = start;\n\t\t\tunsigned char *p = info->tmp_rbuf;\n\t\t\tinfo->tmp_rbuf_count = framesize;\n\n\t\t\tinfo->icount.rxok++;\n\n\t\t\twhile(copy_count) {\n\t\t\t\tint partial_count = min_t(int, copy_count, info->rbuf_fill_level);\n\t\t\t\tmemcpy(p, info->rbufs[i].buf, partial_count);\n\t\t\t\tp += partial_count;\n\t\t\t\tcopy_count -= partial_count;\n\t\t\t\tif (++i == info->rbuf_count)\n\t\t\t\t\ti = 0;\n\t\t\t}\n\n\t\t\tif (info->params.crc_type & HDLC_CRC_RETURN_EX) {\n\t\t\t\t*p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;\n\t\t\t\tframesize++;\n\t\t\t}\n\n#if SYNCLINK_GENERIC_HDLC\n\t\t\tif (info->netcount)\n\t\t\t\thdlcdev_rx(info,info->tmp_rbuf, framesize);\n\t\t\telse\n#endif\n\t\t\t\tldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);\n\t\t}\n\t}\n\tfree_rbufs(info, start, end);\n\treturn true;\n\ncleanup:\n\treturn false;\n}",
        "static void setup_ast2500_cf_maps(struct fsi_master_acf *master)\n{\n\t/*\n\t * Note about byteswap setting: the bus is wired backwards,\n\t * so setting the byteswap bit actually makes the ColdFire": "static void setup_ast2500_cf_maps(struct fsi_master_acf *master)\n{\n\t/*\n\t * Note about byteswap setting: the bus is wired backwards,\n\t * so setting the byteswap bit actually makes the ColdFire\n\t * work \"normally\" for a BE processor, ie, put the MSB in\n\t * the lowest address byte.\n\t *\n\t * We thus need to set the bit for our main memory which\n\t * contains our program code. We create two mappings for\n\t * the register, one with each setting.\n\t *\n\t * Segments 2 and 3 has a \"swapped\" mapping (BE)\n\t * and 6 and 7 have a non-swapped mapping (LE) which allows\n\t * us to avoid byteswapping register accesses since the\n\t * registers are all LE.\n\t */\n\n\t/* Setup segment 0 to our memory region */\n\tregmap_write(master->scu, SCU_2500_COPRO_SEG0, master->cf_mem_addr |\n\t\t     SCU_2500_COPRO_SEG_SWAP);\n\n\t/* Segments 2 and 3 to sysregs with byteswap (for SRAM) */\n\tregmap_write(master->scu, SCU_2500_COPRO_SEG2, SYSREG_BASE |\n\t\t     SCU_2500_COPRO_SEG_SWAP);\n\tregmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 |\n\t\t     SCU_2500_COPRO_SEG_SWAP);\n\n\t/* And segment 6 and 7 to sysregs no byteswap */\n\tregmap_write(master->scu, SCU_2500_COPRO_SEG6, SYSREG_BASE);\n\tregmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000);\n\n\t/* Memory cachable, regs and SRAM not cachable */\n\tregmap_write(master->scu, SCU_2500_COPRO_CACHE_CTL,\n\t\t     SCU_2500_COPRO_SEG0_CACHE_EN | SCU_2500_COPRO_CACHE_EN);\n}",
        "static void ww_test_edeadlk_no_unlock(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_no_unlock(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\to2.ctx = &t2;\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\n\to2.ctx = NULL;\n\tmutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_);\n\tww_mutex_base_unlock(&o2.base);\n\n\tWWL(&o2, &t);\n}",
        "static void mptcp_crypto_test_basic(struct kunit *test)\n{\n\tchar hmac[32], hmac_hex[65];\n\tu32 nonce1, nonce2;\n\tu64 key1, key2;": "static void mptcp_crypto_test_basic(struct kunit *test)\n{\n\tchar hmac[32], hmac_hex[65];\n\tu32 nonce1, nonce2;\n\tu64 key1, key2;\n\tu8 msg[8];\n\tint i, j;\n\n\tfor (i = 0; i < ARRAY_SIZE(tests); ++i) {\n\t\t/* mptcp hmap will convert to be before computing the hmac */\n\t\tkey1 = be64_to_cpu(*((__be64 *)&tests[i].key[0]));\n\t\tkey2 = be64_to_cpu(*((__be64 *)&tests[i].key[8]));\n\t\tnonce1 = be32_to_cpu(*((__be32 *)&tests[i].msg[0]));\n\t\tnonce2 = be32_to_cpu(*((__be32 *)&tests[i].msg[4]));\n\n\t\tput_unaligned_be32(nonce1, &msg[0]);\n\t\tput_unaligned_be32(nonce2, &msg[4]);\n\n\t\tmptcp_crypto_hmac_sha(key1, key2, msg, 8, hmac);\n\t\tfor (j = 0; j < 32; ++j)\n\t\t\tsprintf(&hmac_hex[j << 1], \"%02x\", hmac[j] & 0xff);\n\t\thmac_hex[64] = 0;\n\n\t\tKUNIT_EXPECT_STREQ(test, &hmac_hex[0], tests[i].result);\n\t}\n}",
        "static void __rvu_mbox_handler(struct rvu_work *mwork, int type)\n{\n\tstruct rvu *rvu = mwork->rvu;\n\tint offset, err, id, devid;\n\tstruct otx2_mbox_dev *mdev;": "static void __rvu_mbox_handler(struct rvu_work *mwork, int type)\n{\n\tstruct rvu *rvu = mwork->rvu;\n\tint offset, err, id, devid;\n\tstruct otx2_mbox_dev *mdev;\n\tstruct mbox_hdr *req_hdr;\n\tstruct mbox_msghdr *msg;\n\tstruct mbox_wq_info *mw;\n\tstruct otx2_mbox *mbox;\n\n\tswitch (type) {\n\tcase TYPE_AFPF:\n\t\tmw = &rvu->afpf_wq_info;\n\t\tbreak;\n\tcase TYPE_AFVF:\n\t\tmw = &rvu->afvf_wq_info;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tdevid = mwork - mw->mbox_wrk;\n\tmbox = &mw->mbox;\n\tmdev = &mbox->dev[devid];\n\n\t/* Process received mbox messages */\n\treq_hdr = mdev->mbase + mbox->rx_start;\n\tif (mw->mbox_wrk[devid].num_msgs == 0)\n\t\treturn;\n\n\toffset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n\n\tfor (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {\n\t\tmsg = mdev->mbase + offset;\n\n\t\t/* Set which PF/VF sent this message based on mbox IRQ */\n\t\tswitch (type) {\n\t\tcase TYPE_AFPF:\n\t\t\tmsg->pcifunc &=\n\t\t\t\t~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);\n\t\t\tmsg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);\n\t\t\tbreak;\n\t\tcase TYPE_AFVF:\n\t\t\tmsg->pcifunc &=\n\t\t\t\t~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);\n\t\t\tmsg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;\n\t\t\tbreak;\n\t\t}\n\n\t\terr = rvu_process_mbox_msg(mbox, devid, msg);\n\t\tif (!err) {\n\t\t\toffset = mbox->rx_start + msg->next_msgoff;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (msg->pcifunc & RVU_PFVF_FUNC_MASK)\n\t\t\tdev_warn(rvu->dev, \"Error %d when processing message %s (0x%x) from PF%d:VF%d\\n\",\n\t\t\t\t err, otx2_mbox_id2name(msg->id),\n\t\t\t\t msg->id, rvu_get_pf(msg->pcifunc),\n\t\t\t\t (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);\n\t\telse\n\t\t\tdev_warn(rvu->dev, \"Error %d when processing message %s (0x%x) from PF%d\\n\",\n\t\t\t\t err, otx2_mbox_id2name(msg->id),\n\t\t\t\t msg->id, devid);\n\t}\n\tmw->mbox_wrk[devid].num_msgs = 0;\n\n\t/* Send mbox responses to VF/PF */\n\totx2_mbox_msg_send(mbox, devid);\n}",
        "static int up_to_host(struct mux_rx *r)\n{\n\tstruct mux_dev *mux_dev = r->mux_dev;\n\tstruct mux_pkt_header *mux_header;\n\tunsigned int start_flag;": "static int up_to_host(struct mux_rx *r)\n{\n\tstruct mux_dev *mux_dev = r->mux_dev;\n\tstruct mux_pkt_header *mux_header;\n\tunsigned int start_flag;\n\tunsigned int payload_size;\n\tunsigned short packet_type;\n\tint total_len;\n\tu32 packet_size_sum = r->offset;\n\tint index;\n\tint ret = TO_HOST_INVALID_PACKET;\n\tint len = r->len;\n\n\twhile (1) {\n\t\tmux_header = (struct mux_pkt_header *)(r->buf +\n\t\t\t\t\t\t       packet_size_sum);\n\t\tstart_flag = __le32_to_cpu(mux_header->start_flag);\n\t\tpayload_size = __le32_to_cpu(mux_header->payload_size);\n\t\tpacket_type = __le16_to_cpu(mux_header->packet_type);\n\n\t\tif (start_flag != START_FLAG) {\n\t\t\tpr_err(\"invalid START_FLAG %x\\n\", start_flag);\n\t\t\tbreak;\n\t\t}\n\n\t\ttotal_len = ALIGN(MUX_HEADER_SIZE + payload_size, 4);\n\n\t\tif (len - packet_size_sum < total_len) {\n\t\t\tpr_err(\"invalid payload : %d %d %04x\\n\",\n\t\t\t       payload_size, len, packet_type);\n\t\t\tbreak;\n\t\t}\n\n\t\tindex = packet_type_to_tty_index(packet_type);\n\t\tif (index < 0) {\n\t\t\tpr_err(\"invalid index %d\\n\", index);\n\t\t\tbreak;\n\t\t}\n\n\t\tret = r->callback(mux_header->data,\n\t\t\t\tpayload_size,\n\t\t\t\tindex,\n\t\t\t\tmux_dev->tty_dev,\n\t\t\t\tRECV_PACKET_PROCESS_CONTINUE\n\t\t\t\t);\n\t\tif (ret == TO_HOST_BUFFER_REQUEST_FAIL) {\n\t\t\tr->offset += packet_size_sum;\n\t\t\tbreak;\n\t\t}\n\n\t\tpacket_size_sum += total_len;\n\t\tif (len - packet_size_sum <= MUX_HEADER_SIZE + 2) {\n\t\t\tret = r->callback(NULL,\n\t\t\t\t\t0,\n\t\t\t\t\tindex,\n\t\t\t\t\tmux_dev->tty_dev,\n\t\t\t\t\tRECV_PACKET_PROCESS_COMPLETE\n\t\t\t\t\t);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}",
        "static inline u32 i40e_buildreg_itr(const int type, u16 itr)\n{\n\tu32 val;\n\n\t/* We don't bother with setting the CLEARPBA bit as the data sheet": "static inline u32 i40e_buildreg_itr(const int type, u16 itr)\n{\n\tu32 val;\n\n\t/* We don't bother with setting the CLEARPBA bit as the data sheet\n\t * points out doing so is \"meaningless since it was already\n\t * auto-cleared\". The auto-clearing happens when the interrupt is\n\t * asserted.\n\t *\n\t * Hardware errata 28 for also indicates that writing to a\n\t * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear\n\t * an event in the PBA anyway so we need to rely on the automask\n\t * to hold pending events for us until the interrupt is re-enabled\n\t *\n\t * The itr value is reported in microseconds, and the register\n\t * value is recorded in 2 microsecond units. For this reason we\n\t * only need to shift by the interval shift - 1 instead of the\n\t * full value.\n\t */\n\titr &= I40E_ITR_MASK;\n\n\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n\t      (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n\t      (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));\n\n\treturn val;\n}",
        "static int mlx5_create_ipsec_obj(struct mlx5e_ipsec_sa_entry *sa_entry)\n{\n\tstruct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs;\n\tstruct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);\n\tstruct aes_gcm_keymat *aes_gcm = &attrs->aes_gcm;": "static int mlx5_create_ipsec_obj(struct mlx5e_ipsec_sa_entry *sa_entry)\n{\n\tstruct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs;\n\tstruct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);\n\tstruct aes_gcm_keymat *aes_gcm = &attrs->aes_gcm;\n\tu32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];\n\tu32 in[MLX5_ST_SZ_DW(create_ipsec_obj_in)] = {};\n\tvoid *obj, *salt_p, *salt_iv_p;\n\tint err;\n\n\tobj = MLX5_ADDR_OF(create_ipsec_obj_in, in, ipsec_object);\n\n\t/* salt and seq_iv */\n\tsalt_p = MLX5_ADDR_OF(ipsec_obj, obj, salt);\n\tmemcpy(salt_p, &aes_gcm->salt, sizeof(aes_gcm->salt));\n\n\tMLX5_SET(ipsec_obj, obj, icv_length, MLX5_IPSEC_OBJECT_ICV_LEN_16B);\n\tsalt_iv_p = MLX5_ADDR_OF(ipsec_obj, obj, implicit_iv);\n\tmemcpy(salt_iv_p, &aes_gcm->seq_iv, sizeof(aes_gcm->seq_iv));\n\t/* esn */\n\tif (attrs->flags & MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED) {\n\t\tMLX5_SET(ipsec_obj, obj, esn_en, 1);\n\t\tMLX5_SET(ipsec_obj, obj, esn_msb, attrs->esn);\n\t\tif (attrs->flags & MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP)\n\t\t\tMLX5_SET(ipsec_obj, obj, esn_overlap, 1);\n\t}\n\n\tMLX5_SET(ipsec_obj, obj, dekn, sa_entry->enc_key_id);\n\n\t/* general object fields set */\n\tMLX5_SET(general_obj_in_cmd_hdr, in, opcode,\n\t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n\tMLX5_SET(general_obj_in_cmd_hdr, in, obj_type,\n\t\t MLX5_GENERAL_OBJECT_TYPES_IPSEC);\n\n\terr = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));\n\tif (!err)\n\t\tsa_entry->ipsec_obj_id =\n\t\t\tMLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n\n\treturn err;\n}",
        "static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)\n{\n\tunsigned long flags;\n\n\t/* In BT.656 mode the synchronization signals are generated by the CCDC": "static void ccdc_vd1_isr(struct isp_ccdc_device *ccdc)\n{\n\tunsigned long flags;\n\n\t/* In BT.656 mode the synchronization signals are generated by the CCDC\n\t * from the embedded sync codes. The VD0 and VD1 interrupts are thus\n\t * only triggered when the CCDC is enabled, unlike external sync mode\n\t * where the line counter runs even when the CCDC is stopped. We can't\n\t * disable the CCDC at VD1 time, as no VD0 interrupt would be generated\n\t * for a short frame, which would result in the CCDC being stopped and\n\t * no VD interrupt generated anymore. The CCDC is stopped from the VD0\n\t * interrupt handler instead for BT.656.\n\t */\n\tif (ccdc->bt656)\n\t\treturn;\n\n\tspin_lock_irqsave(&ccdc->lsc.req_lock, flags);\n\n\t/*\n\t * Depending on the CCDC pipeline state, CCDC stopping should be\n\t * handled differently. In SINGLESHOT we emulate an internal CCDC\n\t * stopping because the CCDC hw works only in continuous mode.\n\t * When CONTINUOUS pipeline state is used and the CCDC writes it's\n\t * data to memory the CCDC and LSC are stopped immediately but\n\t * without change the CCDC stopping state machine. The CCDC\n\t * stopping state machine should be used only when user request\n\t * for stopping is received (SINGLESHOT is an exception).\n\t */\n\tswitch (ccdc->state) {\n\tcase ISP_PIPELINE_STREAM_SINGLESHOT:\n\t\tccdc->stopping = CCDC_STOP_REQUEST;\n\t\tbreak;\n\n\tcase ISP_PIPELINE_STREAM_CONTINUOUS:\n\t\tif (ccdc->output & CCDC_OUTPUT_MEMORY) {\n\t\t\tif (ccdc->lsc.state != LSC_STATE_STOPPED)\n\t\t\t\t__ccdc_lsc_enable(ccdc, 0);\n\t\t\t__ccdc_enable(ccdc, 0);\n\t\t}\n\t\tbreak;\n\n\tcase ISP_PIPELINE_STREAM_STOPPED:\n\t\tbreak;\n\t}\n\n\tif (ccdc_handle_stopping(ccdc, CCDC_EVENT_VD1))\n\t\tgoto done;\n\n\tif (ccdc->lsc.request == NULL)\n\t\tgoto done;\n\n\t/*\n\t * LSC need to be reconfigured. Stop it here and on next LSC_DONE IRQ\n\t * do the appropriate changes in registers\n\t */\n\tif (ccdc->lsc.state == LSC_STATE_RUNNING) {\n\t\t__ccdc_lsc_enable(ccdc, 0);\n\t\tccdc->lsc.state = LSC_STATE_RECONFIG;\n\t\tgoto done;\n\t}\n\n\t/* LSC has been in STOPPED state, enable it */\n\tif (ccdc->lsc.state == LSC_STATE_STOPPED)\n\t\tccdc_lsc_enable(ccdc);\n\ndone:\n\tspin_unlock_irqrestore(&ccdc->lsc.req_lock, flags);\n}",
        "static int rio_mport_inbound_free(struct file *filp, void __user *arg)\n{\n\tstruct mport_cdev_priv *priv = filp->private_data;\n\tstruct mport_dev *md = priv->md;\n\tu64 handle;": "static int rio_mport_inbound_free(struct file *filp, void __user *arg)\n{\n\tstruct mport_cdev_priv *priv = filp->private_data;\n\tstruct mport_dev *md = priv->md;\n\tu64 handle;\n\tstruct rio_mport_mapping *map, *_map;\n\n\trmcd_debug(IBW, \"%s filp=%p\", dev_name(&priv->md->dev), filp);\n\n\tif (!md->mport->ops->unmap_inb)\n\t\treturn -EPROTONOSUPPORT;\n\n\tif (copy_from_user(&handle, arg, sizeof(handle)))\n\t\treturn -EFAULT;\n\n\tmutex_lock(&md->buf_mutex);\n\tlist_for_each_entry_safe(map, _map, &md->mappings, node) {\n\t\tif (map->dir == MAP_INBOUND && map->phys_addr == handle) {\n\t\t\tif (map->filp == filp) {\n\t\t\t\tmap->filp = NULL;\n\t\t\t\tkref_put(&map->ref, mport_release_mapping);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n\tmutex_unlock(&md->buf_mutex);\n\n\treturn 0;\n}",
        "static int bond_get_lowest_level_rcu(struct net_device *dev)\n{\n\tstruct net_device *ldev, *next, *now, *dev_stack[MAX_NEST_DEV + 1];\n\tstruct list_head *niter, *iter, *iter_stack[MAX_NEST_DEV + 1];\n\tint cur = 0, max = 0;": "static int bond_get_lowest_level_rcu(struct net_device *dev)\n{\n\tstruct net_device *ldev, *next, *now, *dev_stack[MAX_NEST_DEV + 1];\n\tstruct list_head *niter, *iter, *iter_stack[MAX_NEST_DEV + 1];\n\tint cur = 0, max = 0;\n\n\tnow = dev;\n\titer = &dev->adj_list.lower;\n\n\twhile (1) {\n\t\tnext = NULL;\n\t\twhile (1) {\n\t\t\tldev = netdev_next_lower_dev_rcu(now, &iter);\n\t\t\tif (!ldev)\n\t\t\t\tbreak;\n\n\t\t\tnext = ldev;\n\t\t\tniter = &ldev->adj_list.lower;\n\t\t\tdev_stack[cur] = now;\n\t\t\titer_stack[cur++] = iter;\n\t\t\tif (max <= cur)\n\t\t\t\tmax = cur;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!next) {\n\t\t\tif (!cur)\n\t\t\t\treturn max;\n\t\t\tnext = dev_stack[--cur];\n\t\t\tniter = iter_stack[cur];\n\t\t}\n\n\t\tnow = next;\n\t\titer = niter;\n\t}\n\n\treturn max;\n}",
        "static int t7xx_cldma_gpd_rx_collect(struct cldma_queue *queue, int budget)\n{\n\tstruct cldma_ctrl *md_ctrl = queue->md_ctrl;\n\tstruct t7xx_cldma_hw *hw_info;\n\tunsigned int pending_rx_int;": "static int t7xx_cldma_gpd_rx_collect(struct cldma_queue *queue, int budget)\n{\n\tstruct cldma_ctrl *md_ctrl = queue->md_ctrl;\n\tstruct t7xx_cldma_hw *hw_info;\n\tunsigned int pending_rx_int;\n\tbool over_budget = false;\n\tunsigned long flags;\n\tint ret;\n\n\thw_info = &md_ctrl->hw_info;\n\n\tdo {\n\t\tret = t7xx_cldma_gpd_rx_from_q(queue, budget, &over_budget);\n\t\tif (ret == -ENODATA)\n\t\t\treturn 0;\n\t\telse if (ret)\n\t\t\treturn ret;\n\n\t\tpending_rx_int = 0;\n\n\t\tspin_lock_irqsave(&md_ctrl->cldma_lock, flags);\n\t\tif (md_ctrl->rxq_active & BIT(queue->index)) {\n\t\t\tif (!t7xx_cldma_hw_queue_status(hw_info, queue->index, MTK_RX))\n\t\t\t\tt7xx_cldma_hw_resume_queue(hw_info, queue->index, MTK_RX);\n\n\t\t\tpending_rx_int = t7xx_cldma_hw_int_status(hw_info, BIT(queue->index),\n\t\t\t\t\t\t\t\t  MTK_RX);\n\t\t\tif (pending_rx_int) {\n\t\t\t\tt7xx_cldma_hw_rx_done(hw_info, pending_rx_int);\n\n\t\t\t\tif (over_budget) {\n\t\t\t\t\tspin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);\n\t\t\t\t\treturn -EAGAIN;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tspin_unlock_irqrestore(&md_ctrl->cldma_lock, flags);\n\t} while (pending_rx_int);\n\n\treturn 0;\n}",
        "static void tx_intr_handler(struct fifo_info *fifo_data)\n{\n\tstruct s2io_nic *nic = fifo_data->nic;\n\tstruct tx_curr_get_info get_info, put_info;\n\tstruct sk_buff *skb = NULL;": "static void tx_intr_handler(struct fifo_info *fifo_data)\n{\n\tstruct s2io_nic *nic = fifo_data->nic;\n\tstruct tx_curr_get_info get_info, put_info;\n\tstruct sk_buff *skb = NULL;\n\tstruct TxD *txdlp;\n\tint pkt_cnt = 0;\n\tunsigned long flags = 0;\n\tu8 err_mask;\n\tstruct stat_block *stats = nic->mac_control.stats_info;\n\tstruct swStat *swstats = &stats->sw_stat;\n\n\tif (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))\n\t\treturn;\n\n\tget_info = fifo_data->tx_curr_get_info;\n\tmemcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));\n\ttxdlp = fifo_data->list_info[get_info.offset].list_virt_addr;\n\twhile ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&\n\t       (get_info.offset != put_info.offset) &&\n\t       (txdlp->Host_Control)) {\n\t\t/* Check for TxD errors */\n\t\tif (txdlp->Control_1 & TXD_T_CODE) {\n\t\t\tunsigned long long err;\n\t\t\terr = txdlp->Control_1 & TXD_T_CODE;\n\t\t\tif (err & 0x1) {\n\t\t\t\tswstats->parity_err_cnt++;\n\t\t\t}\n\n\t\t\t/* update t_code statistics */\n\t\t\terr_mask = err >> 48;\n\t\t\tswitch (err_mask) {\n\t\t\tcase 2:\n\t\t\t\tswstats->tx_buf_abort_cnt++;\n\t\t\t\tbreak;\n\n\t\t\tcase 3:\n\t\t\t\tswstats->tx_desc_abort_cnt++;\n\t\t\t\tbreak;\n\n\t\t\tcase 7:\n\t\t\t\tswstats->tx_parity_err_cnt++;\n\t\t\t\tbreak;\n\n\t\t\tcase 10:\n\t\t\t\tswstats->tx_link_loss_cnt++;\n\t\t\t\tbreak;\n\n\t\t\tcase 15:\n\t\t\t\tswstats->tx_list_proc_err_cnt++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tskb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);\n\t\tif (skb == NULL) {\n\t\t\tspin_unlock_irqrestore(&fifo_data->tx_lock, flags);\n\t\t\tDBG_PRINT(ERR_DBG, \"%s: NULL skb in Tx Free Intr\\n\",\n\t\t\t\t  __func__);\n\t\t\treturn;\n\t\t}\n\t\tpkt_cnt++;\n\n\t\t/* Updating the statistics block */\n\t\tswstats->mem_freed += skb->truesize;\n\t\tdev_consume_skb_irq(skb);\n\n\t\tget_info.offset++;\n\t\tif (get_info.offset == get_info.fifo_len + 1)\n\t\t\tget_info.offset = 0;\n\t\ttxdlp = fifo_data->list_info[get_info.offset].list_virt_addr;\n\t\tfifo_data->tx_curr_get_info.offset = get_info.offset;\n\t}\n\n\ts2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);\n\n\tspin_unlock_irqrestore(&fifo_data->tx_lock, flags);\n}",
        "static int send_pcc_cmd(int pcc_ss_id, u16 cmd)\n{\n\tint ret = -EIO, i;\n\tstruct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];\n\tstruct acpi_pcct_shared_memory __iomem *generic_comm_base =": "static int send_pcc_cmd(int pcc_ss_id, u16 cmd)\n{\n\tint ret = -EIO, i;\n\tstruct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];\n\tstruct acpi_pcct_shared_memory __iomem *generic_comm_base =\n\t\tpcc_ss_data->pcc_comm_addr;\n\tunsigned int time_delta;\n\n\t/*\n\t * For CMD_WRITE we know for a fact the caller should have checked\n\t * the channel before writing to PCC space\n\t */\n\tif (cmd == CMD_READ) {\n\t\t/*\n\t\t * If there are pending cpc_writes, then we stole the channel\n\t\t * before write completion, so first send a WRITE command to\n\t\t * platform\n\t\t */\n\t\tif (pcc_ss_data->pending_pcc_write_cmd)\n\t\t\tsend_pcc_cmd(pcc_ss_id, CMD_WRITE);\n\n\t\tret = check_pcc_chan(pcc_ss_id, false);\n\t\tif (ret)\n\t\t\tgoto end;\n\t} else /* CMD_WRITE */\n\t\tpcc_ss_data->pending_pcc_write_cmd = FALSE;\n\n\t/*\n\t * Handle the Minimum Request Turnaround Time(MRTT)\n\t * \"The minimum amount of time that OSPM must wait after the completion\n\t * of a command before issuing the next command, in microseconds\"\n\t */\n\tif (pcc_ss_data->pcc_mrtt) {\n\t\ttime_delta = ktime_us_delta(ktime_get(),\n\t\t\t\t\t    pcc_ss_data->last_cmd_cmpl_time);\n\t\tif (pcc_ss_data->pcc_mrtt > time_delta)\n\t\t\tudelay(pcc_ss_data->pcc_mrtt - time_delta);\n\t}\n\n\t/*\n\t * Handle the non-zero Maximum Periodic Access Rate(MPAR)\n\t * \"The maximum number of periodic requests that the subspace channel can\n\t * support, reported in commands per minute. 0 indicates no limitation.\"\n\t *\n\t * This parameter should be ideally zero or large enough so that it can\n\t * handle maximum number of requests that all the cores in the system can\n\t * collectively generate. If it is not, we will follow the spec and just\n\t * not send the request to the platform after hitting the MPAR limit in\n\t * any 60s window\n\t */\n\tif (pcc_ss_data->pcc_mpar) {\n\t\tif (pcc_ss_data->mpar_count == 0) {\n\t\t\ttime_delta = ktime_ms_delta(ktime_get(),\n\t\t\t\t\t\t    pcc_ss_data->last_mpar_reset);\n\t\t\tif ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {\n\t\t\t\tpr_debug(\"PCC cmd for subspace %d not sent due to MPAR limit\",\n\t\t\t\t\t pcc_ss_id);\n\t\t\t\tret = -EIO;\n\t\t\t\tgoto end;\n\t\t\t}\n\t\t\tpcc_ss_data->last_mpar_reset = ktime_get();\n\t\t\tpcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;\n\t\t}\n\t\tpcc_ss_data->mpar_count--;\n\t}\n\n\t/* Write to the shared comm region. */\n\twritew_relaxed(cmd, &generic_comm_base->command);\n\n\t/* Flip CMD COMPLETE bit */\n\twritew_relaxed(0, &generic_comm_base->status);\n\n\tpcc_ss_data->platform_owns_pcc = true;\n\n\t/* Ring doorbell */\n\tret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);\n\tif (ret < 0) {\n\t\tpr_err(\"Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\\n\",\n\t\t       pcc_ss_id, cmd, ret);\n\t\tgoto end;\n\t}\n\n\t/* wait for completion and check for PCC error bit */\n\tret = check_pcc_chan(pcc_ss_id, true);\n\n\tif (pcc_ss_data->pcc_mrtt)\n\t\tpcc_ss_data->last_cmd_cmpl_time = ktime_get();\n\n\tif (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)\n\t\tmbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);\n\telse\n\t\tmbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);\n\nend:\n\tif (cmd == CMD_WRITE) {\n\t\tif (unlikely(ret)) {\n\t\t\tfor_each_possible_cpu(i) {\n\t\t\t\tstruct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);\n\n\t\t\t\tif (!desc)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)\n\t\t\t\t\tdesc->write_cmd_status = ret;\n\t\t\t}\n\t\t}\n\t\tpcc_ss_data->pcc_write_cnt++;\n\t\twake_up_all(&pcc_ss_data->pcc_write_wait_q);\n\t}\n\n\treturn ret;\n}",
        "static int allocate_vpe_l1_table(void)\n{\n\tvoid __iomem *vlpi_base = gic_data_rdist_vlpi_base();\n\tu64 val, gpsz, npg, pa;\n\tunsigned int psz = SZ_64K;": "static int allocate_vpe_l1_table(void)\n{\n\tvoid __iomem *vlpi_base = gic_data_rdist_vlpi_base();\n\tu64 val, gpsz, npg, pa;\n\tunsigned int psz = SZ_64K;\n\tunsigned int np, epp, esz;\n\tstruct page *page;\n\n\tif (!gic_rdists->has_rvpeid)\n\t\treturn 0;\n\n\t/*\n\t * if VPENDBASER.Valid is set, disable any previously programmed\n\t * VPE by setting PendingLast while clearing Valid. This has the\n\t * effect of making sure no doorbell will be generated and we can\n\t * then safely clear VPROPBASER.Valid.\n\t */\n\tif (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)\n\t\tgicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,\n\t\t\t\t      vlpi_base + GICR_VPENDBASER);\n\n\t/*\n\t * If we can inherit the configuration from another RD, let's do\n\t * so. Otherwise, we have to go through the allocation process. We\n\t * assume that all RDs have the exact same requirements, as\n\t * nothing will work otherwise.\n\t */\n\tval = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);\n\tif (val & GICR_VPROPBASER_4_1_VALID)\n\t\tgoto out;\n\n\tgic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);\n\tif (!gic_data_rdist()->vpe_table_mask)\n\t\treturn -ENOMEM;\n\n\tval = inherit_vpe_l1_table_from_its();\n\tif (val & GICR_VPROPBASER_4_1_VALID)\n\t\tgoto out;\n\n\t/* First probe the page size */\n\tval = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);\n\tgicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);\n\tval = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);\n\tgpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);\n\tesz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);\n\n\tswitch (gpsz) {\n\tdefault:\n\t\tgpsz = GIC_PAGE_SIZE_4K;\n\t\tfallthrough;\n\tcase GIC_PAGE_SIZE_4K:\n\t\tpsz = SZ_4K;\n\t\tbreak;\n\tcase GIC_PAGE_SIZE_16K:\n\t\tpsz = SZ_16K;\n\t\tbreak;\n\tcase GIC_PAGE_SIZE_64K:\n\t\tpsz = SZ_64K;\n\t\tbreak;\n\t}\n\n\t/*\n\t * Start populating the register from scratch, including RO fields\n\t * (which we want to print in debug cases...)\n\t */\n\tval = 0;\n\tval |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);\n\tval |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);\n\n\t/* How many entries per GIC page? */\n\tesz++;\n\tepp = psz / (esz * SZ_8);\n\n\t/*\n\t * If we need more than just a single L1 page, flag the table\n\t * as indirect and compute the number of required L1 pages.\n\t */\n\tif (epp < ITS_MAX_VPEID) {\n\t\tint nl2;\n\n\t\tval |= GICR_VPROPBASER_4_1_INDIRECT;\n\n\t\t/* Number of L2 pages required to cover the VPEID space */\n\t\tnl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);\n\n\t\t/* Number of L1 pages to point to the L2 pages */\n\t\tnpg = DIV_ROUND_UP(nl2 * SZ_8, psz);\n\t} else {\n\t\tnpg = 1;\n\t}\n\n\tval |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);\n\n\t/* Right, that's the number of CPU pages we need for L1 */\n\tnp = DIV_ROUND_UP(npg * psz, PAGE_SIZE);\n\n\tpr_debug(\"np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\\n\",\n\t\t np, npg, psz, epp, esz);\n\tpage = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));\n\tif (!page)\n\t\treturn -ENOMEM;\n\n\tgic_data_rdist()->vpe_l1_base = page_address(page);\n\tpa = virt_to_phys(page_address(page));\n\tWARN_ON(!IS_ALIGNED(pa, psz));\n\n\tval |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);\n\tval |= GICR_VPROPBASER_RaWb;\n\tval |= GICR_VPROPBASER_InnerShareable;\n\tval |= GICR_VPROPBASER_4_1_Z;\n\tval |= GICR_VPROPBASER_4_1_VALID;\n\nout:\n\tgicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);\n\tcpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);\n\n\tpr_debug(\"CPU%d: VPROPBASER = %llx %*pbl\\n\",\n\t\t smp_processor_id(), val,\n\t\t cpumask_pr_args(gic_data_rdist()->vpe_table_mask));\n\n\treturn 0;\n}",
        "static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)\n{\n\tstruct device_node *np = ctrl->dev->of_node;\n\tu8 off1[QCOM_SDW_MAX_PORTS];\n\tu8 off2[QCOM_SDW_MAX_PORTS];": "static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)\n{\n\tstruct device_node *np = ctrl->dev->of_node;\n\tu8 off1[QCOM_SDW_MAX_PORTS];\n\tu8 off2[QCOM_SDW_MAX_PORTS];\n\tu8 si[QCOM_SDW_MAX_PORTS];\n\tu8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };\n\tu8 hstart[QCOM_SDW_MAX_PORTS];\n\tu8 hstop[QCOM_SDW_MAX_PORTS];\n\tu8 word_length[QCOM_SDW_MAX_PORTS];\n\tu8 blk_group_count[QCOM_SDW_MAX_PORTS];\n\tu8 lane_control[QCOM_SDW_MAX_PORTS];\n\tint i, ret, nports, val;\n\n\tctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);\n\n\tctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);\n\tctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);\n\n\tret = of_property_read_u32(np, \"qcom,din-ports\", &val);\n\tif (ret)\n\t\treturn ret;\n\n\tif (val > ctrl->num_din_ports)\n\t\treturn -EINVAL;\n\n\tctrl->num_din_ports = val;\n\n\tret = of_property_read_u32(np, \"qcom,dout-ports\", &val);\n\tif (ret)\n\t\treturn ret;\n\n\tif (val > ctrl->num_dout_ports)\n\t\treturn -EINVAL;\n\n\tctrl->num_dout_ports = val;\n\n\tnports = ctrl->num_dout_ports + ctrl->num_din_ports;\n\t/* Valid port numbers are from 1-14, so mask out port 0 explicitly */\n\tset_bit(0, &ctrl->dout_port_mask);\n\tset_bit(0, &ctrl->din_port_mask);\n\n\tret = of_property_read_u8_array(np, \"qcom,ports-offset1\",\n\t\t\t\t\toff1, nports);\n\tif (ret)\n\t\treturn ret;\n\n\tret = of_property_read_u8_array(np, \"qcom,ports-offset2\",\n\t\t\t\t\toff2, nports);\n\tif (ret)\n\t\treturn ret;\n\n\tret = of_property_read_u8_array(np, \"qcom,ports-sinterval-low\",\n\t\t\t\t\tsi, nports);\n\tif (ret)\n\t\treturn ret;\n\n\tret = of_property_read_u8_array(np, \"qcom,ports-block-pack-mode\",\n\t\t\t\t\tbp_mode, nports);\n\tif (ret) {\n\t\tif (ctrl->version <= 0x01030000)\n\t\t\tmemset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);\n\t\telse\n\t\t\treturn ret;\n\t}\n\n\tmemset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);\n\tof_property_read_u8_array(np, \"qcom,ports-hstart\", hstart, nports);\n\n\tmemset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);\n\tof_property_read_u8_array(np, \"qcom,ports-hstop\", hstop, nports);\n\n\tmemset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);\n\tof_property_read_u8_array(np, \"qcom,ports-word-length\", word_length, nports);\n\n\tmemset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);\n\tof_property_read_u8_array(np, \"qcom,ports-block-group-count\", blk_group_count, nports);\n\n\tmemset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);\n\tof_property_read_u8_array(np, \"qcom,ports-lane-control\", lane_control, nports);\n\n\tfor (i = 0; i < nports; i++) {\n\t\t/* Valid port number range is from 1-14 */\n\t\tctrl->pconfig[i + 1].si = si[i];\n\t\tctrl->pconfig[i + 1].off1 = off1[i];\n\t\tctrl->pconfig[i + 1].off2 = off2[i];\n\t\tctrl->pconfig[i + 1].bp_mode = bp_mode[i];\n\t\tctrl->pconfig[i + 1].hstart = hstart[i];\n\t\tctrl->pconfig[i + 1].hstop = hstop[i];\n\t\tctrl->pconfig[i + 1].word_length = word_length[i];\n\t\tctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];\n\t\tctrl->pconfig[i + 1].lane_control = lane_control[i];\n\t}\n\n\treturn 0;\n}",
        "static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)\n{\n\tu32 *data;\n\tint i, ret;\n\tu32 xsr;": "static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)\n{\n\tu32 *data;\n\tint i, ret;\n\tu32 xsr;\n\tu32 size, max_size;\n\n\tdata = (u32 *)priv->msg;\n\n\timx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));\n\t*data++ = imx_mu_read(priv, priv->dcfg->xRR);\n\n\tif (priv->dcfg->type & IMX_MU_V2_S4) {\n\t\tsize = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;\n\t\tmax_size = sizeof(struct imx_s4_rpc_msg_max);\n\t} else {\n\t\tsize = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;\n\t\tmax_size = sizeof(struct imx_sc_rpc_msg_max);\n\t}\n\n\tif (size > max_size / 4) {\n\t\tdev_err(priv->dev, \"Maximal message size (%u bytes) exceeded on RX; got: %i bytes\\n\", max_size, size << 2);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 1; i < size; i++) {\n\t\tret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,\n\t\t\t\t\t xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,\n\t\t\t\t\t 5 * USEC_PER_SEC);\n\t\tif (ret) {\n\t\t\tdev_err(priv->dev, \"timeout read idx %d\\n\", i);\n\t\t\treturn ret;\n\t\t}\n\t\t*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);\n\t}\n\n\timx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);\n\tmbox_chan_received_data(cp->chan, (void *)priv->msg);\n\n\treturn 0;\n}",
        "static int keene_cmd_main(struct keene_device *radio, unsigned freq, bool play)\n{\n\tunsigned short freq_send = freq ? (freq - 76 * 16000) / 800 : 0;\n\tint ret;\n": "static int keene_cmd_main(struct keene_device *radio, unsigned freq, bool play)\n{\n\tunsigned short freq_send = freq ? (freq - 76 * 16000) / 800 : 0;\n\tint ret;\n\n\tradio->buffer[0] = 0x00;\n\tradio->buffer[1] = 0x50;\n\tradio->buffer[2] = (freq_send >> 8) & 0xff;\n\tradio->buffer[3] = freq_send & 0xff;\n\tradio->buffer[4] = radio->pa;\n\t/* If bit 4 is set, then tune to the frequency.\n\t   If bit 3 is set, then unmute; if bit 2 is set, then mute.\n\t   If bit 1 is set, then enter idle mode; if bit 0 is set,\n\t   then enter transmit mode.\n\t */\n\tradio->buffer[5] = (radio->muted ? 4 : 8) | (play ? 1 : 2) |\n\t\t\t\t\t\t\t(freq ? 0x10 : 0);\n\tradio->buffer[6] = 0x00;\n\tradio->buffer[7] = 0x00;\n\n\tret = usb_control_msg(radio->usbdev, usb_sndctrlpipe(radio->usbdev, 0),\n\t\t9, 0x21, 0x200, 2, radio->buffer, BUFFER_LENGTH, USB_TIMEOUT);\n\n\tif (ret < 0) {\n\t\tdev_warn(&radio->vdev.dev, \"%s failed (%d)\\n\", __func__, ret);\n\t\treturn ret;\n\t}\n\tif (freq)\n\t\tradio->curfreq = freq;\n\treturn 0;\n}",
        "static void cpu_fans_tick_combined(void)\n{\n\ts32 temp0, power0, temp1, power1, t_max = 0;\n\ts32 temp, power, intake, pump;\n\tstruct wf_control *pump0, *pump1;": "static void cpu_fans_tick_combined(void)\n{\n\ts32 temp0, power0, temp1, power1, t_max = 0;\n\ts32 temp, power, intake, pump;\n\tstruct wf_control *pump0, *pump1;\n\tstruct wf_cpu_pid_state *sp = &cpu_pid[0];\n\tint err, cpu;\n\n\tDBG_LOTS(\"* cpu fans_tick_combined()\\n\");\n\n\t/* Read current speed from cpu 0 */\n\twf_control_get(cpu_rear_fans[0], &sp->target);\n\n\tDBG_LOTS(\"  CPUs: cur_target = %d RPM\\n\", sp->target);\n\n\t/* Read values for both CPUs */\n\terr = read_one_cpu_vals(0, &temp0, &power0);\n\tif (err) {\n\t\tfailure_state |= FAILURE_SENSOR;\n\t\tcpu_max_all_fans();\n\t\treturn;\n\t}\n\terr = read_one_cpu_vals(1, &temp1, &power1);\n\tif (err) {\n\t\tfailure_state |= FAILURE_SENSOR;\n\t\tcpu_max_all_fans();\n\t\treturn;\n\t}\n\n\t/* Keep track of highest temp */\n\tt_max = max(t_max, max(temp0, temp1));\n\n\t/* Handle possible overtemps */\n\tif (cpu_check_overtemp(t_max))\n\t\treturn;\n\n\t/* Use the max temp & power of both */\n\ttemp = max(temp0, temp1);\n\tpower = max(power0, power1);\n\n\t/* Run PID */\n\twf_cpu_pid_run(sp, power, temp);\n\n\t/* Scale result for intake fan */\n\tintake = (sp->target * CPU_INTAKE_SCALE) >> 16;\n\n\t/* Same deal with pump speed */\n\tpump0 = cpu_pumps[0];\n\tpump1 = cpu_pumps[1];\n\tif (!pump0) {\n\t\tpump0 = pump1;\n\t\tpump1 = NULL;\n\t}\n\tpump = (sp->target * wf_control_get_max(pump0)) /\n\t\tcpu_mpu_data[0]->rmaxn_exhaust_fan;\n\n\tDBG_LOTS(\"  CPUs: target = %d RPM\\n\", sp->target);\n\tDBG_LOTS(\"  CPUs: intake = %d RPM\\n\", intake);\n\tDBG_LOTS(\"  CPUs: pump   = %d RPM\\n\", pump);\n\n\tfor (cpu = 0; cpu < nr_chips; cpu++) {\n\t\terr = wf_control_set(cpu_rear_fans[cpu], sp->target);\n\t\tif (err) {\n\t\t\tpr_warn(\"wf_pm72: Fan %s reports error %d\\n\",\n\t\t\t\tcpu_rear_fans[cpu]->name, err);\n\t\t\tfailure_state |= FAILURE_FAN;\n\t\t}\n\t\terr = wf_control_set(cpu_front_fans[cpu], intake);\n\t\tif (err) {\n\t\t\tpr_warn(\"wf_pm72: Fan %s reports error %d\\n\",\n\t\t\t\tcpu_front_fans[cpu]->name, err);\n\t\t\tfailure_state |= FAILURE_FAN;\n\t\t}\n\t\terr = 0;\n\t\tif (cpu_pumps[cpu])\n\t\t\terr = wf_control_set(cpu_pumps[cpu], pump);\n\t\tif (err) {\n\t\t\tpr_warn(\"wf_pm72: Pump %s reports error %d\\n\",\n\t\t\t\tcpu_pumps[cpu]->name, err);\n\t\t\tfailure_state |= FAILURE_FAN;\n\t\t}\n\t}\n}",
        "static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc)\n{\n\tu32 val;\n\n\t/* limit port speed to gen 1 */": "static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc)\n{\n\tu32 val;\n\n\t/* limit port speed to gen 1 */\n\tval = xudc_readl(xudc, SSPX_CORE_CNT56);\n\tval &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK);\n\tval |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260);\n\txudc_writel(xudc, val, SSPX_CORE_CNT56);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT57);\n\tval &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK);\n\tval |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6);\n\txudc_writel(xudc, val, SSPX_CORE_CNT57);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT65);\n\tval &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK);\n\tval |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0);\n\txudc_writel(xudc, val, SSPX_CORE_CNT66);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT66);\n\tval &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK);\n\tval |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0);\n\txudc_writel(xudc, val, SSPX_CORE_CNT66);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT67);\n\tval &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK);\n\tval |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0);\n\txudc_writel(xudc, val, SSPX_CORE_CNT67);\n\n\tval = xudc_readl(xudc, SSPX_CORE_CNT72);\n\tval &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK);\n\tval |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10);\n\txudc_writel(xudc, val, SSPX_CORE_CNT72);\n}",
        "static bool ipc_mux_lite_send_qlt(struct iosm_mux *ipc_mux)\n{\n\tstruct ipc_mem_lite_gen_tbl *qlt;\n\tstruct mux_session *session;\n\tbool qlt_updated = false;": "static bool ipc_mux_lite_send_qlt(struct iosm_mux *ipc_mux)\n{\n\tstruct ipc_mem_lite_gen_tbl *qlt;\n\tstruct mux_session *session;\n\tbool qlt_updated = false;\n\tint i;\n\tint qlt_size;\n\n\tif (!ipc_mux->initialized || ipc_mux->state != MUX_S_ACTIVE)\n\t\treturn qlt_updated;\n\n\tqlt_size = offsetof(struct ipc_mem_lite_gen_tbl, vfl) +\n\t\t   MUX_QUEUE_LEVEL * sizeof(struct mux_lite_vfl);\n\n\tfor (i = 0; i < IPC_MEM_MUX_IP_SESSION_ENTRIES; i++) {\n\t\tsession = &ipc_mux->session[i];\n\n\t\tif (!session->wwan || session->flow_ctl_mask)\n\t\t\tcontinue;\n\n\t\tif (ipc_mux_ul_skb_alloc(ipc_mux, &ipc_mux->ul_adb,\n\t\t\t\t\t MUX_SIG_QLTH)) {\n\t\t\tdev_err(ipc_mux->dev,\n\t\t\t\t\"no reserved mem to send QLT of if_id: %d\", i);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Prepare QLT */\n\t\tqlt = (struct ipc_mem_lite_gen_tbl *)(ipc_mux->ul_adb.qlth_skb)\n\t\t\t      ->data;\n\t\tqlt->signature = cpu_to_le32(MUX_SIG_QLTH);\n\t\tqlt->length = cpu_to_le16(qlt_size);\n\t\tqlt->if_id = i;\n\t\tqlt->vfl_length = MUX_QUEUE_LEVEL * sizeof(struct mux_lite_vfl);\n\t\tqlt->reserved[0] = 0;\n\t\tqlt->reserved[1] = 0;\n\n\t\tqlt->vfl.nr_of_bytes = cpu_to_le32(session->ul_list.qlen);\n\n\t\t/* Add QLT to the transfer list. */\n\t\tskb_queue_tail(&ipc_mux->channel->ul_list,\n\t\t\t       ipc_mux->ul_adb.qlth_skb);\n\n\t\tqlt_updated = true;\n\t\tipc_mux->ul_adb.qlth_skb = NULL;\n\t}\n\n\tif (qlt_updated)\n\t\t/* Updates the TDs with ul_list */\n\t\t(void)ipc_imem_ul_write_td(ipc_mux->imem);\n\n\treturn qlt_updated;\n}",
        "static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)\n{\n\tu8 *addrs = nc->op.addrs;\n\tunsigned int op = 0;\n\tu32 addr, val;": "static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)\n{\n\tu8 *addrs = nc->op.addrs;\n\tunsigned int op = 0;\n\tu32 addr, val;\n\tint i, ret;\n\n\tnc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;\n\n\tfor (i = 0; i < nc->op.ncmds; i++)\n\t\top |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);\n\n\tif (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)\n\t\tregmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);\n\n\top |= ATMEL_NFC_CSID(nc->op.cs) |\n\t      ATMEL_NFC_ACYCLE(nc->op.naddrs);\n\n\tif (nc->op.ncmds > 1)\n\t\top |= ATMEL_NFC_VCMD2;\n\n\taddr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |\n\t       (addrs[3] << 24);\n\n\tif (nc->op.data != ATMEL_NFC_NO_DATA) {\n\t\top |= ATMEL_NFC_DATAEN;\n\t\tnc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;\n\n\t\tif (nc->op.data == ATMEL_NFC_WRITE_DATA)\n\t\t\top |= ATMEL_NFC_NFCWR;\n\t}\n\n\t/* Clear all flags. */\n\tregmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);\n\n\t/* Send the command. */\n\tregmap_write(nc->io, op, addr);\n\n\tret = atmel_nfc_wait(nc, poll, 0);\n\tif (ret)\n\t\tdev_err(nc->base.dev,\n\t\t\t\"Failed to send NAND command (err = %d)!\",\n\t\t\tret);\n\n\t/* Reset the op state. */\n\tmemset(&nc->op, 0, sizeof(nc->op));\n\n\treturn ret;\n}",
        "static int ttusb_init_controller(struct ttusb *ttusb)\n{\n\tu8 b0[] = { 0xaa, ++ttusb->c, 0x15, 1, 0 };\n\tu8 b1[] = { 0xaa, ++ttusb->c, 0x15, 1, 1 };\n\tu8 b2[] = { 0xaa, ++ttusb->c, 0x32, 1, 0 };": "static int ttusb_init_controller(struct ttusb *ttusb)\n{\n\tu8 b0[] = { 0xaa, ++ttusb->c, 0x15, 1, 0 };\n\tu8 b1[] = { 0xaa, ++ttusb->c, 0x15, 1, 1 };\n\tu8 b2[] = { 0xaa, ++ttusb->c, 0x32, 1, 0 };\n\t/* i2c write read: 5 bytes, addr 0x10, 0x02 bytes write, 1 bytes read. */\n\tu8 b3[] =\n\t    { 0xaa, ++ttusb->c, 0x31, 5, 0x10, 0x02, 0x01, 0x00, 0x1e };\n\n\tu8 get_version[] = { 0xaa, ++ttusb->c, 0x17, 5, 0, 0, 0, 0, 0 };\n\tu8 get_dsp_version[0x20] =\n\t    { 0xaa, ++ttusb->c, 0x26, 28, 0, 0, 0, 0, 0 };\n\tint err;\n\n\t/* reset board */\n\tif ((err = ttusb_cmd(ttusb, b0, sizeof(b0), 0)))\n\t\treturn err;\n\n\t/* reset board (again?) */\n\tif ((err = ttusb_cmd(ttusb, b1, sizeof(b1), 0)))\n\t\treturn err;\n\n\tttusb_boot_dsp(ttusb);\n\n\t/* set i2c bit rate */\n\tif ((err = ttusb_cmd(ttusb, b2, sizeof(b2), 0)))\n\t\treturn err;\n\n\tif ((err = ttusb_cmd(ttusb, b3, sizeof(b3), 0)))\n\t\treturn err;\n\n\tif ((err = ttusb_cmd(ttusb, get_version,\n\t\t\t     sizeof(get_version), sizeof(get_version))))\n\t\treturn err;\n\n\tdprintk(\"stc-version: %c%c%c%c%c\\n\", get_version[4], get_version[5],\n\t\tget_version[6], get_version[7], get_version[8]);\n\n\tif (memcmp(get_version + 4, \"V 0.0\", 5) &&\n\t    memcmp(get_version + 4, \"V 1.1\", 5) &&\n\t    memcmp(get_version + 4, \"V 2.1\", 5) &&\n\t    memcmp(get_version + 4, \"V 2.2\", 5)) {\n\t\tpr_err(\"unknown STC version %c%c%c%c%c, please report!\\n\",\n\t\t       get_version[4], get_version[5],\n\t\t       get_version[6], get_version[7], get_version[8]);\n\t}\n\n\tttusb->revision = ((get_version[6] - '0') << 4) |\n\t\t\t   (get_version[8] - '0');\n\n\terr =\n\t    ttusb_cmd(ttusb, get_dsp_version,\n\t\t      sizeof(get_dsp_version), sizeof(get_dsp_version));\n\tif (err)\n\t\treturn err;\n\n\tpr_info(\"dsp-version: %c%c%c\\n\",\n\t       get_dsp_version[4], get_dsp_version[5], get_dsp_version[6]);\n\treturn 0;\n}",
        "static void dump_table(const struct nozomi *dc)\n{\n\tDBG3(\"signature: 0x%08X\", dc->config_table.signature);\n\tDBG3(\"version: 0x%04X\", dc->config_table.version);\n\tDBG3(\"product_information: 0x%04X\", \\": "static void dump_table(const struct nozomi *dc)\n{\n\tDBG3(\"signature: 0x%08X\", dc->config_table.signature);\n\tDBG3(\"version: 0x%04X\", dc->config_table.version);\n\tDBG3(\"product_information: 0x%04X\", \\\n\t\t\t\tdc->config_table.product_information);\n\tDBG3(\"toggle enabled: %d\", dc->config_table.toggle.enabled);\n\tDBG3(\"toggle up_mdm: %d\", dc->config_table.toggle.mdm_ul);\n\tDBG3(\"toggle dl_mdm: %d\", dc->config_table.toggle.mdm_dl);\n\tDBG3(\"toggle dl_dbg: %d\", dc->config_table.toggle.diag_dl);\n\n\tDBG3(\"dl_start: 0x%04X\", dc->config_table.dl_start);\n\tDBG3(\"dl_mdm_len0: 0x%04X, %d\", dc->config_table.dl_mdm_len1,\n\t   dc->config_table.dl_mdm_len1);\n\tDBG3(\"dl_mdm_len1: 0x%04X, %d\", dc->config_table.dl_mdm_len2,\n\t   dc->config_table.dl_mdm_len2);\n\tDBG3(\"dl_diag_len0: 0x%04X, %d\", dc->config_table.dl_diag_len1,\n\t   dc->config_table.dl_diag_len1);\n\tDBG3(\"dl_diag_len1: 0x%04X, %d\", dc->config_table.dl_diag_len2,\n\t   dc->config_table.dl_diag_len2);\n\tDBG3(\"dl_app1_len: 0x%04X, %d\", dc->config_table.dl_app1_len,\n\t   dc->config_table.dl_app1_len);\n\tDBG3(\"dl_app2_len: 0x%04X, %d\", dc->config_table.dl_app2_len,\n\t   dc->config_table.dl_app2_len);\n\tDBG3(\"dl_ctrl_len: 0x%04X, %d\", dc->config_table.dl_ctrl_len,\n\t   dc->config_table.dl_ctrl_len);\n\tDBG3(\"ul_start: 0x%04X, %d\", dc->config_table.ul_start,\n\t   dc->config_table.ul_start);\n\tDBG3(\"ul_mdm_len[0]: 0x%04X, %d\", dc->config_table.ul_mdm_len1,\n\t   dc->config_table.ul_mdm_len1);\n\tDBG3(\"ul_mdm_len[1]: 0x%04X, %d\", dc->config_table.ul_mdm_len2,\n\t   dc->config_table.ul_mdm_len2);\n\tDBG3(\"ul_diag_len: 0x%04X, %d\", dc->config_table.ul_diag_len,\n\t   dc->config_table.ul_diag_len);\n\tDBG3(\"ul_app1_len: 0x%04X, %d\", dc->config_table.ul_app1_len,\n\t   dc->config_table.ul_app1_len);\n\tDBG3(\"ul_app2_len: 0x%04X, %d\", dc->config_table.ul_app2_len,\n\t   dc->config_table.ul_app2_len);\n\tDBG3(\"ul_ctrl_len: 0x%04X, %d\", dc->config_table.ul_ctrl_len,\n\t   dc->config_table.ul_ctrl_len);\n}",
        "static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)\n{\n\tu32 val, bmcr, mac_mode, ptest = 0;\n\n\ttg3_phy_toggle_apd(tp, false);": "static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)\n{\n\tu32 val, bmcr, mac_mode, ptest = 0;\n\n\ttg3_phy_toggle_apd(tp, false);\n\ttg3_phy_toggle_automdix(tp, false);\n\n\tif (extlpbk && tg3_phy_set_extloopbk(tp))\n\t\treturn -EIO;\n\n\tbmcr = BMCR_FULLDPLX;\n\tswitch (speed) {\n\tcase SPEED_10:\n\t\tbreak;\n\tcase SPEED_100:\n\t\tbmcr |= BMCR_SPEED100;\n\t\tbreak;\n\tcase SPEED_1000:\n\tdefault:\n\t\tif (tp->phy_flags & TG3_PHYFLG_IS_FET) {\n\t\t\tspeed = SPEED_100;\n\t\t\tbmcr |= BMCR_SPEED100;\n\t\t} else {\n\t\t\tspeed = SPEED_1000;\n\t\t\tbmcr |= BMCR_SPEED1000;\n\t\t}\n\t}\n\n\tif (extlpbk) {\n\t\tif (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {\n\t\t\ttg3_readphy(tp, MII_CTRL1000, &val);\n\t\t\tval |= CTL1000_AS_MASTER |\n\t\t\t       CTL1000_ENABLE_MASTER;\n\t\t\ttg3_writephy(tp, MII_CTRL1000, val);\n\t\t} else {\n\t\t\tptest = MII_TG3_FET_PTEST_TRIM_SEL |\n\t\t\t\tMII_TG3_FET_PTEST_TRIM_2;\n\t\t\ttg3_writephy(tp, MII_TG3_FET_PTEST, ptest);\n\t\t}\n\t} else\n\t\tbmcr |= BMCR_LOOPBACK;\n\n\ttg3_writephy(tp, MII_BMCR, bmcr);\n\n\t/* The write needs to be flushed for the FETs */\n\tif (tp->phy_flags & TG3_PHYFLG_IS_FET)\n\t\ttg3_readphy(tp, MII_BMCR, &bmcr);\n\n\tudelay(40);\n\n\tif ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&\n\t    tg3_asic_rev(tp) == ASIC_REV_5785) {\n\t\ttg3_writephy(tp, MII_TG3_FET_PTEST, ptest |\n\t\t\t     MII_TG3_FET_PTEST_FRC_TX_LINK |\n\t\t\t     MII_TG3_FET_PTEST_FRC_TX_LOCK);\n\n\t\t/* The write needs to be flushed for the AC131 */\n\t\ttg3_readphy(tp, MII_TG3_FET_PTEST, &val);\n\t}\n\n\t/* Reset to prevent losing 1st rx packet intermittently */\n\tif ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&\n\t    tg3_flag(tp, 5780_CLASS)) {\n\t\ttw32_f(MAC_RX_MODE, RX_MODE_RESET);\n\t\tudelay(10);\n\t\ttw32_f(MAC_RX_MODE, tp->rx_mode);\n\t}\n\n\tmac_mode = tp->mac_mode &\n\t\t   ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);\n\tif (speed == SPEED_1000)\n\t\tmac_mode |= MAC_MODE_PORT_MODE_GMII;\n\telse\n\t\tmac_mode |= MAC_MODE_PORT_MODE_MII;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5700) {\n\t\tu32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;\n\n\t\tif (masked_phy_id == TG3_PHY_ID_BCM5401)\n\t\t\tmac_mode &= ~MAC_MODE_LINK_POLARITY;\n\t\telse if (masked_phy_id == TG3_PHY_ID_BCM5411)\n\t\t\tmac_mode |= MAC_MODE_LINK_POLARITY;\n\n\t\ttg3_writephy(tp, MII_TG3_EXT_CTRL,\n\t\t\t     MII_TG3_EXT_CTRL_LNK3_LED_MODE);\n\t}\n\n\ttw32(MAC_MODE, mac_mode);\n\tudelay(40);\n\n\treturn 0;\n}",
        "static int do_btf_read(struct bpf_iter_task_btf *skel)\n{\n\tstruct bpf_program *prog = skel->progs.dump_task_struct;\n\tstruct bpf_iter_task_btf__bss *bss = skel->bss;\n\tint iter_fd = -1, err;": "static int do_btf_read(struct bpf_iter_task_btf *skel)\n{\n\tstruct bpf_program *prog = skel->progs.dump_task_struct;\n\tstruct bpf_iter_task_btf__bss *bss = skel->bss;\n\tint iter_fd = -1, err;\n\tstruct bpf_link *link;\n\tchar *buf = taskbuf;\n\tint ret = 0;\n\n\tlink = bpf_program__attach_iter(prog, NULL);\n\tif (!ASSERT_OK_PTR(link, \"attach_iter\"))\n\t\treturn ret;\n\n\titer_fd = bpf_iter_create(bpf_link__fd(link));\n\tif (!ASSERT_GE(iter_fd, 0, \"create_iter\"))\n\t\tgoto free_link;\n\n\terr = read_fd_into_buffer(iter_fd, buf, TASKBUFSZ);\n\tif (bss->skip) {\n\t\tprintf(\"%s:SKIP:no __builtin_btf_type_id\\n\", __func__);\n\t\tret = 1;\n\t\ttest__skip();\n\t\tgoto free_link;\n\t}\n\n\tif (CHECK(err < 0, \"read\", \"read failed: %s\\n\", strerror(errno)))\n\t\tgoto free_link;\n\n\tASSERT_HAS_SUBSTR(taskbuf, \"(struct task_struct)\",\n\t      \"check for btf representation of task_struct in iter data\");\nfree_link:\n\tif (iter_fd > 0)\n\t\tclose(iter_fd);\n\tbpf_link__destroy(link);\n\treturn ret;\n}",
        "static int ptrace_check_attach(struct task_struct *child, bool ignore_state)\n{\n\tint ret = -ESRCH;\n\n\t/*": "static int ptrace_check_attach(struct task_struct *child, bool ignore_state)\n{\n\tint ret = -ESRCH;\n\n\t/*\n\t * We take the read lock around doing both checks to close a\n\t * possible race where someone else was tracing our child and\n\t * detached between these two checks.  After this locked check,\n\t * we are sure that this is our traced child and that can only\n\t * be changed by us so it's not changing right after this.\n\t */\n\tread_lock(&tasklist_lock);\n\tif (child->ptrace && child->parent == current) {\n\t\t/*\n\t\t * child->sighand can't be NULL, release_task()\n\t\t * does ptrace_unlink() before __exit_signal().\n\t\t */\n\t\tif (ignore_state || ptrace_freeze_traced(child))\n\t\t\tret = 0;\n\t}\n\tread_unlock(&tasklist_lock);\n\n\tif (!ret && !ignore_state &&\n\t    WARN_ON_ONCE(!wait_task_inactive(child, __TASK_TRACED)))\n\t\tret = -ESRCH;\n\n\treturn ret;\n}",
        "static void ccid2_hc_tx_packet_sent(struct sock *sk, unsigned int len)\n{\n\tstruct dccp_sock *dp = dccp_sk(sk);\n\tstruct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);\n\tconst u32 now = ccid2_jiffies32;": "static void ccid2_hc_tx_packet_sent(struct sock *sk, unsigned int len)\n{\n\tstruct dccp_sock *dp = dccp_sk(sk);\n\tstruct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);\n\tconst u32 now = ccid2_jiffies32;\n\tstruct ccid2_seq *next;\n\n\t/* slow-start after idle periods (RFC 2581, RFC 2861) */\n\tif (ccid2_do_cwv && !hc->tx_pipe &&\n\t    (s32)(now - hc->tx_lsndtime) >= hc->tx_rto)\n\t\tccid2_cwnd_restart(sk, now);\n\n\thc->tx_lsndtime = now;\n\thc->tx_pipe    += 1;\n\n\t/* see whether cwnd was fully used (RFC 2861), update expected window */\n\tif (ccid2_cwnd_network_limited(hc)) {\n\t\tccid2_update_used_window(hc, hc->tx_cwnd);\n\t\thc->tx_cwnd_used  = 0;\n\t\thc->tx_cwnd_stamp = now;\n\t} else {\n\t\tif (hc->tx_pipe > hc->tx_cwnd_used)\n\t\t\thc->tx_cwnd_used = hc->tx_pipe;\n\n\t\tccid2_update_used_window(hc, hc->tx_cwnd_used);\n\n\t\tif (ccid2_do_cwv && (s32)(now - hc->tx_cwnd_stamp) >= hc->tx_rto)\n\t\t\tccid2_cwnd_application_limited(sk, now);\n\t}\n\n\thc->tx_seqh->ccid2s_seq   = dp->dccps_gss;\n\thc->tx_seqh->ccid2s_acked = 0;\n\thc->tx_seqh->ccid2s_sent  = now;\n\n\tnext = hc->tx_seqh->ccid2s_next;\n\t/* check if we need to alloc more space */\n\tif (next == hc->tx_seqt) {\n\t\tif (ccid2_hc_tx_alloc_seq(hc)) {\n\t\t\tDCCP_CRIT(\"packet history - out of memory!\");\n\t\t\t/* FIXME: find a more graceful way to bail out */\n\t\t\treturn;\n\t\t}\n\t\tnext = hc->tx_seqh->ccid2s_next;\n\t\tBUG_ON(next == hc->tx_seqt);\n\t}\n\thc->tx_seqh = next;\n\n\tccid2_pr_debug(\"cwnd=%d pipe=%d\\n\", hc->tx_cwnd, hc->tx_pipe);\n\n\t/*\n\t * FIXME: The code below is broken and the variables have been removed\n\t * from the socket struct. The `ackloss' variable was always set to 0,\n\t * and with arsent there are several problems:\n\t *  (i) it doesn't just count the number of Acks, but all sent packets;\n\t *  (ii) it is expressed in # of packets, not # of windows, so the\n\t *  comparison below uses the wrong formula: Appendix A of RFC 4341\n\t *  comes up with the number K = cwnd / (R^2 - R) of consecutive windows\n\t *  of data with no lost or marked Ack packets. If arsent were the # of\n\t *  consecutive Acks received without loss, then Ack Ratio needs to be\n\t *  decreased by 1 when\n\t *\t      arsent >=  K * cwnd / R  =  cwnd^2 / (R^3 - R^2)\n\t *  where cwnd / R is the number of Acks received per window of data\n\t *  (cf. RFC 4341, App. A). The problems are that\n\t *  - arsent counts other packets as well;\n\t *  - the comparison uses a formula different from RFC 4341;\n\t *  - computing a cubic/quadratic equation each time is too complicated.\n\t *  Hence a different algorithm is needed.\n\t */\n#if 0\n\t/* Ack Ratio.  Need to maintain a concept of how many windows we sent */\n\thc->tx_arsent++;\n\t/* We had an ack loss in this window... */\n\tif (hc->tx_ackloss) {\n\t\tif (hc->tx_arsent >= hc->tx_cwnd) {\n\t\t\thc->tx_arsent  = 0;\n\t\t\thc->tx_ackloss = 0;\n\t\t}\n\t} else {\n\t\t/* No acks lost up to now... */\n\t\t/* decrease ack ratio if enough packets were sent */\n\t\tif (dp->dccps_l_ack_ratio > 1) {\n\t\t\t/* XXX don't calculate denominator each time */\n\t\t\tint denom = dp->dccps_l_ack_ratio * dp->dccps_l_ack_ratio -\n\t\t\t\t    dp->dccps_l_ack_ratio;\n\n\t\t\tdenom = hc->tx_cwnd * hc->tx_cwnd / denom;\n\n\t\t\tif (hc->tx_arsent >= denom) {\n\t\t\t\tccid2_change_l_ack_ratio(sk, dp->dccps_l_ack_ratio - 1);\n\t\t\t\thc->tx_arsent = 0;\n\t\t\t}\n\t\t} else {\n\t\t\t/* we can't increase ack ratio further [1] */\n\t\t\thc->tx_arsent = 0; /* or maybe set it to cwnd*/\n\t\t}\n\t}\n#endif\n\n\tsk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);\n\n#ifdef CONFIG_IP_DCCP_CCID2_DEBUG\n\tdo {\n\t\tstruct ccid2_seq *seqp = hc->tx_seqt;\n\n\t\twhile (seqp != hc->tx_seqh) {\n\t\t\tccid2_pr_debug(\"out seq=%llu acked=%d time=%u\\n\",\n\t\t\t\t       (unsigned long long)seqp->ccid2s_seq,\n\t\t\t\t       seqp->ccid2s_acked, seqp->ccid2s_sent);\n\t\t\tseqp = seqp->ccid2s_next;\n\t\t}\n\t} while (0);\n\tccid2_pr_debug(\"=========\\n\");\n#endif\n}",
        "static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tstruct cnic_eth_dev *ethdev = cp->ethdev;": "static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tstruct cnic_eth_dev *ethdev = cp->ethdev;\n\tu32 start_cid = ethdev->starting_cid;\n\tint i, j, n, ret, pages;\n\tstruct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;\n\n\tcp->max_cid_space = MAX_ISCSI_TBL_SZ;\n\tcp->iscsi_start_cid = start_cid;\n\tcp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;\n\n\tif (BNX2X_CHIP_IS_E2_PLUS(bp)) {\n\t\tcp->max_cid_space += dev->max_fcoe_conn;\n\t\tcp->fcoe_init_cid = ethdev->fcoe_init_cid;\n\t\tif (!cp->fcoe_init_cid)\n\t\t\tcp->fcoe_init_cid = 0x10;\n\t}\n\n\tcp->iscsi_tbl = kcalloc(MAX_ISCSI_TBL_SZ, sizeof(struct cnic_iscsi),\n\t\t\t\tGFP_KERNEL);\n\tif (!cp->iscsi_tbl)\n\t\tgoto error;\n\n\tcp->ctx_tbl = kcalloc(cp->max_cid_space, sizeof(struct cnic_context),\n\t\t\t      GFP_KERNEL);\n\tif (!cp->ctx_tbl)\n\t\tgoto error;\n\n\tfor (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {\n\t\tcp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];\n\t\tcp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;\n\t}\n\n\tfor (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)\n\t\tcp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;\n\n\tpages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /\n\t\tCNIC_PAGE_SIZE;\n\n\tret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);\n\tif (ret)\n\t\tgoto error;\n\n\tn = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;\n\tfor (i = 0, j = 0; i < cp->max_cid_space; i++) {\n\t\tlong off = CNIC_KWQ16_DATA_SIZE * (i % n);\n\n\t\tcp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;\n\t\tcp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +\n\t\t\t\t\t\t   off;\n\n\t\tif ((i % n) == (n - 1))\n\t\t\tj++;\n\t}\n\n\tret = cnic_alloc_kcq(dev, &cp->kcq1, false);\n\tif (ret)\n\t\tgoto error;\n\n\tif (CNIC_SUPPORTS_FCOE(bp)) {\n\t\tret = cnic_alloc_kcq(dev, &cp->kcq2, true);\n\t\tif (ret)\n\t\t\tgoto error;\n\t}\n\n\tpages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;\n\tret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);\n\tif (ret)\n\t\tgoto error;\n\n\tret = cnic_alloc_bnx2x_context(dev);\n\tif (ret)\n\t\tgoto error;\n\n\tif (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)\n\t\treturn 0;\n\n\tcp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;\n\n\tcp->l2_rx_ring_size = 15;\n\n\tret = cnic_alloc_uio_rings(dev, 4);\n\tif (ret)\n\t\tgoto error;\n\n\tret = cnic_init_uio(dev);\n\tif (ret)\n\t\tgoto error;\n\n\treturn 0;\n\nerror:\n\tcnic_free_resc(dev);\n\treturn -ENOMEM;\n}",
        "static int intel_component_dais_suspend(struct snd_soc_component *component)\n{\n\tstruct snd_soc_dai *dai;\n\n\t/*": "static int intel_component_dais_suspend(struct snd_soc_component *component)\n{\n\tstruct snd_soc_dai *dai;\n\n\t/*\n\t * In the corner case where a SUSPEND happens during a PAUSE, the ALSA core\n\t * does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.\n\t * Since the component suspend is called last, we can trap this corner case\n\t * and force the DAIs to release their resources.\n\t */\n\tfor_each_component_dais(component, dai) {\n\t\tstruct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);\n\t\tstruct sdw_intel *sdw = cdns_to_intel(cdns);\n\t\tstruct sdw_cdns_dma_data *dma;\n\t\tint stream;\n\t\tint ret;\n\n\t\tdma = dai->playback_dma_data;\n\t\tstream = SNDRV_PCM_STREAM_PLAYBACK;\n\t\tif (!dma) {\n\t\t\tdma = dai->capture_dma_data;\n\t\t\tstream = SNDRV_PCM_STREAM_CAPTURE;\n\t\t}\n\n\t\tif (!dma)\n\t\t\tcontinue;\n\n\t\tif (dma->suspended)\n\t\t\tcontinue;\n\n\t\tif (dma->paused) {\n\t\t\tdma->suspended = true;\n\n\t\t\tret = intel_free_stream(sdw, stream, dai, sdw->instance);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static bool smc_clc_msg_prop_valid(struct smc_clc_msg_proposal *pclc)\n{\n\tstruct smc_clc_msg_proposal_prefix *pclc_prfx;\n\tstruct smc_clc_smcd_v2_extension *smcd_v2_ext;\n\tstruct smc_clc_msg_hdr *hdr = &pclc->hdr;": "static bool smc_clc_msg_prop_valid(struct smc_clc_msg_proposal *pclc)\n{\n\tstruct smc_clc_msg_proposal_prefix *pclc_prfx;\n\tstruct smc_clc_smcd_v2_extension *smcd_v2_ext;\n\tstruct smc_clc_msg_hdr *hdr = &pclc->hdr;\n\tstruct smc_clc_v2_extension *v2_ext;\n\n\tv2_ext = smc_get_clc_v2_ext(pclc);\n\tpclc_prfx = smc_clc_proposal_get_prefix(pclc);\n\tif (hdr->version == SMC_V1) {\n\t\tif (hdr->typev1 == SMC_TYPE_N)\n\t\t\treturn false;\n\t\tif (ntohs(hdr->length) !=\n\t\t\tsizeof(*pclc) + ntohs(pclc->iparea_offset) +\n\t\t\tsizeof(*pclc_prfx) +\n\t\t\tpclc_prfx->ipv6_prefixes_cnt *\n\t\t\t\tsizeof(struct smc_clc_ipv6_prefix) +\n\t\t\tsizeof(struct smc_clc_msg_trail))\n\t\t\treturn false;\n\t} else {\n\t\tif (ntohs(hdr->length) !=\n\t\t\tsizeof(*pclc) +\n\t\t\tsizeof(struct smc_clc_msg_smcd) +\n\t\t\t(hdr->typev1 != SMC_TYPE_N ?\n\t\t\t\tsizeof(*pclc_prfx) +\n\t\t\t\tpclc_prfx->ipv6_prefixes_cnt *\n\t\t\t\tsizeof(struct smc_clc_ipv6_prefix) : 0) +\n\t\t\t(hdr->typev2 != SMC_TYPE_N ?\n\t\t\t\tsizeof(*v2_ext) +\n\t\t\t\tv2_ext->hdr.eid_cnt * SMC_MAX_EID_LEN : 0) +\n\t\t\t(smcd_indicated(hdr->typev2) ?\n\t\t\t\tsizeof(*smcd_v2_ext) + v2_ext->hdr.ism_gid_cnt *\n\t\t\t\t\tsizeof(struct smc_clc_smcd_gid_chid) :\n\t\t\t\t0) +\n\t\t\tsizeof(struct smc_clc_msg_trail))\n\t\t\treturn false;\n\t}\n\treturn true;\n}",
        "static void __init rcu_init_one(void)\n{\n\tstatic const char * const buf[] = RCU_NODE_NAME_INIT;\n\tstatic const char * const fqs[] = RCU_FQS_NAME_INIT;\n\tstatic struct lock_class_key rcu_node_class[RCU_NUM_LVLS];": "static void __init rcu_init_one(void)\n{\n\tstatic const char * const buf[] = RCU_NODE_NAME_INIT;\n\tstatic const char * const fqs[] = RCU_FQS_NAME_INIT;\n\tstatic struct lock_class_key rcu_node_class[RCU_NUM_LVLS];\n\tstatic struct lock_class_key rcu_fqs_class[RCU_NUM_LVLS];\n\n\tint levelspread[RCU_NUM_LVLS];\t\t/* kids/node in each level. */\n\tint cpustride = 1;\n\tint i;\n\tint j;\n\tstruct rcu_node *rnp;\n\n\tBUILD_BUG_ON(RCU_NUM_LVLS > ARRAY_SIZE(buf));  /* Fix buf[] init! */\n\n\t/* Silence gcc 4.8 false positive about array index out of range. */\n\tif (rcu_num_lvls <= 0 || rcu_num_lvls > RCU_NUM_LVLS)\n\t\tpanic(\"rcu_init_one: rcu_num_lvls out of range\");\n\n\t/* Initialize the level-tracking arrays. */\n\n\tfor (i = 1; i < rcu_num_lvls; i++)\n\t\trcu_state.level[i] =\n\t\t\trcu_state.level[i - 1] + num_rcu_lvl[i - 1];\n\trcu_init_levelspread(levelspread, num_rcu_lvl);\n\n\t/* Initialize the elements themselves, starting from the leaves. */\n\n\tfor (i = rcu_num_lvls - 1; i >= 0; i--) {\n\t\tcpustride *= levelspread[i];\n\t\trnp = rcu_state.level[i];\n\t\tfor (j = 0; j < num_rcu_lvl[i]; j++, rnp++) {\n\t\t\traw_spin_lock_init(&ACCESS_PRIVATE(rnp, lock));\n\t\t\tlockdep_set_class_and_name(&ACCESS_PRIVATE(rnp, lock),\n\t\t\t\t\t\t   &rcu_node_class[i], buf[i]);\n\t\t\traw_spin_lock_init(&rnp->fqslock);\n\t\t\tlockdep_set_class_and_name(&rnp->fqslock,\n\t\t\t\t\t\t   &rcu_fqs_class[i], fqs[i]);\n\t\t\trnp->gp_seq = rcu_state.gp_seq;\n\t\t\trnp->gp_seq_needed = rcu_state.gp_seq;\n\t\t\trnp->completedqs = rcu_state.gp_seq;\n\t\t\trnp->qsmask = 0;\n\t\t\trnp->qsmaskinit = 0;\n\t\t\trnp->grplo = j * cpustride;\n\t\t\trnp->grphi = (j + 1) * cpustride - 1;\n\t\t\tif (rnp->grphi >= nr_cpu_ids)\n\t\t\t\trnp->grphi = nr_cpu_ids - 1;\n\t\t\tif (i == 0) {\n\t\t\t\trnp->grpnum = 0;\n\t\t\t\trnp->grpmask = 0;\n\t\t\t\trnp->parent = NULL;\n\t\t\t} else {\n\t\t\t\trnp->grpnum = j % levelspread[i - 1];\n\t\t\t\trnp->grpmask = BIT(rnp->grpnum);\n\t\t\t\trnp->parent = rcu_state.level[i - 1] +\n\t\t\t\t\t      j / levelspread[i - 1];\n\t\t\t}\n\t\t\trnp->level = i;\n\t\t\tINIT_LIST_HEAD(&rnp->blkd_tasks);\n\t\t\trcu_init_one_nocb(rnp);\n\t\t\tinit_waitqueue_head(&rnp->exp_wq[0]);\n\t\t\tinit_waitqueue_head(&rnp->exp_wq[1]);\n\t\t\tinit_waitqueue_head(&rnp->exp_wq[2]);\n\t\t\tinit_waitqueue_head(&rnp->exp_wq[3]);\n\t\t\tspin_lock_init(&rnp->exp_lock);\n\t\t\tmutex_init(&rnp->boost_kthread_mutex);\n\t\t}\n\t}\n\n\tinit_swait_queue_head(&rcu_state.gp_wq);\n\tinit_swait_queue_head(&rcu_state.expedited_wq);\n\trnp = rcu_first_leaf_node();\n\tfor_each_possible_cpu(i) {\n\t\twhile (i > rnp->grphi)\n\t\t\trnp++;\n\t\tper_cpu_ptr(&rcu_data, i)->mynode = rnp;\n\t\trcu_boot_init_percpu_data(i);\n\t}\n}",
        "static void sh7760_i2c_mrecv(struct cami2c *id)\n{\n\tint len;\n\n\tid->flags |= IDF_RECV;": "static void sh7760_i2c_mrecv(struct cami2c *id)\n{\n\tint len;\n\n\tid->flags |= IDF_RECV;\n\n\t/* set the slave addr reg; otherwise rcv wont work! */\n\tOUT32(id, I2CSAR, 0xfe);\n\tOUT32(id, I2CMAR, (id->msg->addr << 1) | 1);\n\n\t/* adjust rx fifo trigger */\n\tif (id->msg->len >= FIFO_SIZE)\n\t\tlen = FIFO_SIZE - 1;\t/* trigger at fifo full */\n\telse\n\t\tlen = id->msg->len - 1;\t/* trigger before all received */\n\n\tOUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);\n\tOUT32(id, I2CFCR, FCR_TFRST | ((len & 0xF) << 4));\n\n\tOUT32(id, I2CMSR, 0);\n\tOUT32(id, I2CMCR, MCR_MIE | MCR_ESG);\n\tOUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);\n\tOUT32(id, I2CFIER, FIER_RXIE);\n}",
        "static int bt8xx_dst_init(struct dvb_frontend *fe)\n{\n\tstruct dst_state *state = fe->demodulator_priv;\n\n\tstatic u8 sat_tuna_188[] = { 0x09, 0x00, 0x03, 0xb6, 0x01, 0x00, 0x73, 0x21, 0x00, 0x00 };": "static int bt8xx_dst_init(struct dvb_frontend *fe)\n{\n\tstruct dst_state *state = fe->demodulator_priv;\n\n\tstatic u8 sat_tuna_188[] = { 0x09, 0x00, 0x03, 0xb6, 0x01, 0x00, 0x73, 0x21, 0x00, 0x00 };\n\tstatic u8 sat_tuna_204[] = { 0x00, 0x00, 0x03, 0xb6, 0x01, 0x55, 0xbd, 0x50, 0x00, 0x00 };\n\tstatic u8 ter_tuna_188[] = { 0x09, 0x00, 0x03, 0xb6, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00 };\n\tstatic u8 ter_tuna_204[] = { 0x00, 0x00, 0x03, 0xb6, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00 };\n\tstatic u8 cab_tuna_188[] = { 0x09, 0x00, 0x03, 0xb6, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00 };\n\tstatic u8 cab_tuna_204[] = { 0x00, 0x00, 0x03, 0xb6, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00 };\n\tstatic u8 atsc_tuner[] = { 0x00, 0x00, 0x03, 0xb6, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00 };\n\n\tstate->inversion = INVERSION_OFF;\n\tstate->voltage = SEC_VOLTAGE_13;\n\tstate->tone = SEC_TONE_OFF;\n\tstate->diseq_flags = 0;\n\tstate->k22 = 0x02;\n\tstate->bandwidth = 7000000;\n\tstate->cur_jiff = jiffies;\n\tif (state->dst_type == DST_TYPE_IS_SAT)\n\t\tmemcpy(state->tx_tuna, ((state->type_flags & DST_TYPE_HAS_VLF) ? sat_tuna_188 : sat_tuna_204), sizeof (sat_tuna_204));\n\telse if (state->dst_type == DST_TYPE_IS_TERR)\n\t\tmemcpy(state->tx_tuna, ((state->type_flags & DST_TYPE_HAS_VLF) ? ter_tuna_188 : ter_tuna_204), sizeof (ter_tuna_204));\n\telse if (state->dst_type == DST_TYPE_IS_CABLE)\n\t\tmemcpy(state->tx_tuna, ((state->type_flags & DST_TYPE_HAS_VLF) ? cab_tuna_188 : cab_tuna_204), sizeof (cab_tuna_204));\n\telse if (state->dst_type == DST_TYPE_IS_ATSC)\n\t\tmemcpy(state->tx_tuna, atsc_tuner, sizeof (atsc_tuner));\n\n\treturn 0;\n}",
        "static int irq_timings_next_event_index(int *buffer, size_t len, int period_max)\n{\n\tint period;\n\n\t/*": "static int irq_timings_next_event_index(int *buffer, size_t len, int period_max)\n{\n\tint period;\n\n\t/*\n\t * Move the beginning pointer to the end minus the max period x 3.\n\t * We are at the point we can begin searching the pattern\n\t */\n\tbuffer = &buffer[len - (period_max * 3)];\n\n\t/* Adjust the length to the maximum allowed period x 3 */\n\tlen = period_max * 3;\n\n\t/*\n\t * The buffer contains the suite of intervals, in a ilog2\n\t * basis, we are looking for a repetition. We point the\n\t * beginning of the search three times the length of the\n\t * period beginning at the end of the buffer. We do that for\n\t * each suffix.\n\t */\n\tfor (period = period_max; period >= PREDICTION_PERIOD_MIN; period--) {\n\n\t\t/*\n\t\t * The first comparison always succeed because the\n\t\t * suffix is deduced from the first n-period bytes of\n\t\t * the buffer and we compare the initial suffix with\n\t\t * itself, so we can skip the first iteration.\n\t\t */\n\t\tint idx = period;\n\t\tsize_t size = period;\n\n\t\t/*\n\t\t * We look if the suite with period 'i' repeat\n\t\t * itself. If it is truncated at the end, as it\n\t\t * repeats we can use the period to find out the next\n\t\t * element with the modulo.\n\t\t */\n\t\twhile (!memcmp(buffer, &buffer[idx], size * sizeof(int))) {\n\n\t\t\t/*\n\t\t\t * Move the index in a period basis\n\t\t\t */\n\t\t\tidx += size;\n\n\t\t\t/*\n\t\t\t * If this condition is reached, all previous\n\t\t\t * memcmp were successful, so the period is\n\t\t\t * found.\n\t\t\t */\n\t\t\tif (idx == len)\n\t\t\t\treturn buffer[len % period];\n\n\t\t\t/*\n\t\t\t * If the remaining elements to compare are\n\t\t\t * smaller than the period, readjust the size\n\t\t\t * of the comparison for the last iteration.\n\t\t\t */\n\t\t\tif (len - idx < period)\n\t\t\t\tsize = len - idx;\n\t\t}\n\t}\n\n\treturn -1;\n}",
        "static int venus_core_init(struct venus_core *core)\n{\n\tstruct venus_hfi_device *hdev = to_hfi_priv(core);\n\tstruct device *dev = core->dev;\n\tstruct hfi_sys_get_property_pkt version_pkt;": "static int venus_core_init(struct venus_core *core)\n{\n\tstruct venus_hfi_device *hdev = to_hfi_priv(core);\n\tstruct device *dev = core->dev;\n\tstruct hfi_sys_get_property_pkt version_pkt;\n\tstruct hfi_sys_init_pkt pkt;\n\tint ret;\n\n\tpkt_sys_init(&pkt, HFI_VIDEO_ARCH_OX);\n\n\tvenus_set_state(hdev, VENUS_STATE_INIT);\n\n\tret = venus_iface_cmdq_write(hdev, &pkt, false);\n\tif (ret)\n\t\treturn ret;\n\n\tpkt_sys_image_version(&version_pkt);\n\n\tret = venus_iface_cmdq_write(hdev, &version_pkt, false);\n\tif (ret)\n\t\tdev_warn(dev, \"failed to send image version pkt to fw\\n\");\n\n\tret = venus_sys_set_default_properties(hdev);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}",
        "static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)\n{\n\tunsigned int found_mask = 0;\n#define FOUND_MASK_MODEL\t0x00000001\n#define FOUND_MASK_BMODEL\t0x00000002": "static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)\n{\n\tunsigned int found_mask = 0;\n#define FOUND_MASK_MODEL\t0x00000001\n#define FOUND_MASK_BMODEL\t0x00000002\n#define FOUND_MASK_VERS\t\t0x00000004\n#define FOUND_MASK_MAC\t\t0x00000008\n#define FOUND_MASK_NMAC\t\t0x00000010\n#define FOUND_MASK_PHY\t\t0x00000020\n#define FOUND_MASK_ALL\t\t0x0000003f\n\n\tnetif_printk(np, probe, KERN_DEBUG, np->dev,\n\t\t     \"VPD_SCAN: start[%x] end[%x]\\n\", start, end);\n\twhile (start < end) {\n\t\tint len, err, prop_len;\n\t\tchar namebuf[64];\n\t\tu8 *prop_buf;\n\t\tint max_len;\n\n\t\tif (found_mask == FOUND_MASK_ALL) {\n\t\t\tniu_vpd_parse_version(np);\n\t\t\treturn 1;\n\t\t}\n\n\t\terr = niu_pci_eeprom_read(np, start + 2);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\tlen = err;\n\t\tstart += 3;\n\n\t\tprop_len = niu_pci_eeprom_read(np, start + 4);\n\t\tif (prop_len < 0)\n\t\t\treturn prop_len;\n\t\terr = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);\n\t\tif (err < 0)\n\t\t\treturn err;\n\n\t\tprop_buf = NULL;\n\t\tmax_len = 0;\n\t\tif (!strcmp(namebuf, \"model\")) {\n\t\t\tprop_buf = np->vpd.model;\n\t\t\tmax_len = NIU_VPD_MODEL_MAX;\n\t\t\tfound_mask |= FOUND_MASK_MODEL;\n\t\t} else if (!strcmp(namebuf, \"board-model\")) {\n\t\t\tprop_buf = np->vpd.board_model;\n\t\t\tmax_len = NIU_VPD_BD_MODEL_MAX;\n\t\t\tfound_mask |= FOUND_MASK_BMODEL;\n\t\t} else if (!strcmp(namebuf, \"version\")) {\n\t\t\tprop_buf = np->vpd.version;\n\t\t\tmax_len = NIU_VPD_VERSION_MAX;\n\t\t\tfound_mask |= FOUND_MASK_VERS;\n\t\t} else if (!strcmp(namebuf, \"local-mac-address\")) {\n\t\t\tprop_buf = np->vpd.local_mac;\n\t\t\tmax_len = ETH_ALEN;\n\t\t\tfound_mask |= FOUND_MASK_MAC;\n\t\t} else if (!strcmp(namebuf, \"num-mac-addresses\")) {\n\t\t\tprop_buf = &np->vpd.mac_num;\n\t\t\tmax_len = 1;\n\t\t\tfound_mask |= FOUND_MASK_NMAC;\n\t\t} else if (!strcmp(namebuf, \"phy-type\")) {\n\t\t\tprop_buf = np->vpd.phy_type;\n\t\t\tmax_len = NIU_VPD_PHY_TYPE_MAX;\n\t\t\tfound_mask |= FOUND_MASK_PHY;\n\t\t}\n\n\t\tif (max_len && prop_len > max_len) {\n\t\t\tdev_err(np->device, \"Property '%s' length (%d) is too long\\n\", namebuf, prop_len);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (prop_buf) {\n\t\t\tu32 off = start + 5 + err;\n\t\t\tint i;\n\n\t\t\tnetif_printk(np, probe, KERN_DEBUG, np->dev,\n\t\t\t\t     \"VPD_SCAN: Reading in property [%s] len[%d]\\n\",\n\t\t\t\t     namebuf, prop_len);\n\t\t\tfor (i = 0; i < prop_len; i++) {\n\t\t\t\terr =  niu_pci_eeprom_read(np, off + i);\n\t\t\t\tif (err < 0)\n\t\t\t\t\treturn err;\n\t\t\t\t*prop_buf++ = err;\n\t\t\t}\n\t\t}\n\n\t\tstart += len;\n\t}\n\n\treturn 0;\n}",
        "static int alloc_try_nid_bottom_up_cap_min_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_bottom_up_cap_min_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_1K;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM();\n\tmax_addr = memblock_end_of_DRAM() - SZ_256;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr,\n\t\t\t\t\t       NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == memblock_start_of_DRAM());\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static void *run_vcpu(void *_cpu_nr)\n{\n\tunsigned long cpu = (unsigned long)_cpu_nr;\n\tunsigned long failures = 0;\n\tstatic bool first_cpu_done;": "static void *run_vcpu(void *_cpu_nr)\n{\n\tunsigned long cpu = (unsigned long)_cpu_nr;\n\tunsigned long failures = 0;\n\tstatic bool first_cpu_done;\n\n\t/* The kernel is fine, but vm_vcpu_add_default() needs locking */\n\tpthread_spin_lock(&create_lock);\n\n\tvm_vcpu_add_default(vm, cpu, guest_code);\n\n\tif (!first_cpu_done) {\n\t\tfirst_cpu_done = true;\n\t\tvcpu_set_msr(vm, cpu, MSR_IA32_TSC, TEST_TSC_OFFSET);\n\t}\n\n\tpthread_spin_unlock(&create_lock);\n\n\tfor (;;) {\n\t\tvolatile struct kvm_run *run = vcpu_state(vm, cpu);\n                struct ucall uc;\n\n                vcpu_run(vm, cpu);\n                TEST_ASSERT(run->exit_reason == KVM_EXIT_IO,\n                            \"Got exit_reason other than KVM_EXIT_IO: %u (%s)\\n\",\n                            run->exit_reason,\n                            exit_reason_str(run->exit_reason));\n\n                switch (get_ucall(vm, cpu, &uc)) {\n                case UCALL_DONE:\n\t\t\tgoto out;\n\n                case UCALL_SYNC:\n\t\t\tprintf(\"Guest %ld sync %lx %lx %ld\\n\", cpu, uc.args[2], uc.args[3], uc.args[2] - uc.args[3]);\n\t\t\tfailures++;\n\t\t\tbreak;\n\n                default:\n                        TEST_FAIL(\"Unknown ucall %lu\", uc.cmd);\n\t\t}\n\t}\n out:\n\treturn (void *)failures;\n}",
        "static int read_partial_msg_data(struct ceph_connection *con)\n{\n\tstruct ceph_msg_data_cursor *cursor = &con->in_msg->cursor;\n\tbool do_datacrc = !ceph_test_opt(from_msgr(con->msgr), NOCRC);\n\tstruct page *page;": "static int read_partial_msg_data(struct ceph_connection *con)\n{\n\tstruct ceph_msg_data_cursor *cursor = &con->in_msg->cursor;\n\tbool do_datacrc = !ceph_test_opt(from_msgr(con->msgr), NOCRC);\n\tstruct page *page;\n\tsize_t page_offset;\n\tsize_t length;\n\tu32 crc = 0;\n\tint ret;\n\n\tif (do_datacrc)\n\t\tcrc = con->in_data_crc;\n\twhile (cursor->total_resid) {\n\t\tif (!cursor->resid) {\n\t\t\tceph_msg_data_advance(cursor, 0);\n\t\t\tcontinue;\n\t\t}\n\n\t\tpage = ceph_msg_data_next(cursor, &page_offset, &length, NULL);\n\t\tret = ceph_tcp_recvpage(con->sock, page, page_offset, length);\n\t\tif (ret <= 0) {\n\t\t\tif (do_datacrc)\n\t\t\t\tcon->in_data_crc = crc;\n\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (do_datacrc)\n\t\t\tcrc = ceph_crc32c_page(crc, page, page_offset, ret);\n\t\tceph_msg_data_advance(cursor, (size_t)ret);\n\t}\n\tif (do_datacrc)\n\t\tcon->in_data_crc = crc;\n\n\treturn 1;\t/* must return > 0 to indicate success */\n}",
        "static inline int get_cgroup_v1_idx(__u32 *cgrps, int size)\n{\n\tstruct task_struct *p = (void *)bpf_get_current_task();\n\tstruct cgroup *cgrp;\n\tregister int i = 0;": "static inline int get_cgroup_v1_idx(__u32 *cgrps, int size)\n{\n\tstruct task_struct *p = (void *)bpf_get_current_task();\n\tstruct cgroup *cgrp;\n\tregister int i = 0;\n\t__u32 *elem;\n\tint level;\n\tint cnt;\n\n\tcgrp = BPF_CORE_READ(p, cgroups, subsys[perf_event_cgrp_id], cgroup);\n\tlevel = BPF_CORE_READ(cgrp, level);\n\n\tfor (cnt = 0; i < MAX_LEVELS; i++) {\n\t\t__u64 cgrp_id;\n\n\t\tif (i > level)\n\t\t\tbreak;\n\n\t\t// convert cgroup-id to a map index\n\t\tcgrp_id = BPF_CORE_READ(cgrp, ancestor_ids[i]);\n\t\telem = bpf_map_lookup_elem(&cgrp_idx, &cgrp_id);\n\t\tif (!elem)\n\t\t\tcontinue;\n\n\t\tcgrps[cnt++] = *elem;\n\t\tif (cnt == size)\n\t\t\tbreak;\n\t}\n\n\treturn cnt;\n}",
        "static int nv_mgmt_get_version(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 data_ready = readl(base + NvRegTransmitterControl);": "static int nv_mgmt_get_version(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu8 __iomem *base = get_hwbase(dev);\n\tu32 data_ready = readl(base + NvRegTransmitterControl);\n\tu32 data_ready2 = 0;\n\tunsigned long start;\n\tint ready = 0;\n\n\twritel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);\n\twritel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);\n\tstart = jiffies;\n\twhile (time_before(jiffies, start + 5*HZ)) {\n\t\tdata_ready2 = readl(base + NvRegTransmitterControl);\n\t\tif ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {\n\t\t\tready = 1;\n\t\t\tbreak;\n\t\t}\n\t\tschedule_timeout_uninterruptible(1);\n\t}\n\n\tif (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))\n\t\treturn 0;\n\n\tnp->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;\n\n\treturn 1;\n}",
        "static int igc_tsn_enable_offload(struct igc_adapter *adapter)\n{\n\tstruct igc_hw *hw = &adapter->hw;\n\tu32 tqavctrl, baset_l, baset_h;\n\tu32 sec, nsec, cycle;": "static int igc_tsn_enable_offload(struct igc_adapter *adapter)\n{\n\tstruct igc_hw *hw = &adapter->hw;\n\tu32 tqavctrl, baset_l, baset_h;\n\tu32 sec, nsec, cycle;\n\tktime_t base_time, systim;\n\tint i;\n\n\tcycle = adapter->cycle_time;\n\tbase_time = adapter->base_time;\n\n\twr32(IGC_TSAUXC, 0);\n\twr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);\n\twr32(IGC_TXPBS, IGC_TXPBSIZE_TSN);\n\n\ttqavctrl = rd32(IGC_TQAVCTRL);\n\ttqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;\n\twr32(IGC_TQAVCTRL, tqavctrl);\n\n\twr32(IGC_QBVCYCLET_S, cycle);\n\twr32(IGC_QBVCYCLET, cycle);\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\tstruct igc_ring *ring = adapter->tx_ring[i];\n\t\tu32 txqctl = 0;\n\t\tu16 cbs_value;\n\t\tu32 tqavcc;\n\n\t\twr32(IGC_STQT(i), ring->start_time);\n\t\twr32(IGC_ENDQT(i), ring->end_time);\n\n\t\tif (adapter->base_time) {\n\t\t\t/* If we have a base_time we are in \"taprio\"\n\t\t\t * mode and we need to be strict about the\n\t\t\t * cycles: only transmit a packet if it can be\n\t\t\t * completed during that cycle.\n\t\t\t */\n\t\t\ttxqctl |= IGC_TXQCTL_STRICT_CYCLE |\n\t\t\t\tIGC_TXQCTL_STRICT_END;\n\t\t}\n\n\t\tif (ring->launchtime_enable)\n\t\t\ttxqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;\n\n\t\t/* Skip configuring CBS for Q2 and Q3 */\n\t\tif (i > 1)\n\t\t\tgoto skip_cbs;\n\n\t\tif (ring->cbs_enable) {\n\t\t\tif (i == 0)\n\t\t\t\ttxqctl |= IGC_TXQCTL_QAV_SEL_CBS0;\n\t\t\telse\n\t\t\t\ttxqctl |= IGC_TXQCTL_QAV_SEL_CBS1;\n\n\t\t\t/* According to i225 datasheet section 7.5.2.7, we\n\t\t\t * should set the 'idleSlope' field from TQAVCC\n\t\t\t * register following the equation:\n\t\t\t *\n\t\t\t * value = link-speed   0x7736 * BW * 0.2\n\t\t\t *         ---------- *  -----------------         (E1)\n\t\t\t *          100Mbps            2.5\n\t\t\t *\n\t\t\t * Note that 'link-speed' is in Mbps.\n\t\t\t *\n\t\t\t * 'BW' is the percentage bandwidth out of full\n\t\t\t * link speed which can be found with the\n\t\t\t * following equation. Note that idleSlope here\n\t\t\t * is the parameter from this function\n\t\t\t * which is in kbps.\n\t\t\t *\n\t\t\t *     BW =     idleSlope\n\t\t\t *          -----------------                      (E2)\n\t\t\t *          link-speed * 1000\n\t\t\t *\n\t\t\t * That said, we can come up with a generic\n\t\t\t * equation to calculate the value we should set\n\t\t\t * it TQAVCC register by replacing 'BW' in E1 by E2.\n\t\t\t * The resulting equation is:\n\t\t\t *\n\t\t\t * value = link-speed * 0x7736 * idleSlope * 0.2\n\t\t\t *         -------------------------------------   (E3)\n\t\t\t *             100 * 2.5 * link-speed * 1000\n\t\t\t *\n\t\t\t * 'link-speed' is present in both sides of the\n\t\t\t * fraction so it is canceled out. The final\n\t\t\t * equation is the following:\n\t\t\t *\n\t\t\t *     value = idleSlope * 61036\n\t\t\t *             -----------------                   (E4)\n\t\t\t *                  2500000\n\t\t\t *\n\t\t\t * NOTE: For i225, given the above, we can see\n\t\t\t *       that idleslope is represented in\n\t\t\t *       40.959433 kbps units by the value at\n\t\t\t *       the TQAVCC register (2.5Gbps / 61036),\n\t\t\t *       which reduces the granularity for\n\t\t\t *       idleslope increments.\n\t\t\t *\n\t\t\t * In i225 controller, the sendSlope and loCredit\n\t\t\t * parameters from CBS are not configurable\n\t\t\t * by software so we don't do any\n\t\t\t * 'controller configuration' in respect to\n\t\t\t * these parameters.\n\t\t\t */\n\t\t\tcbs_value = DIV_ROUND_UP_ULL(ring->idleslope\n\t\t\t\t\t\t     * 61036ULL, 2500000);\n\n\t\t\ttqavcc = rd32(IGC_TQAVCC(i));\n\t\t\ttqavcc &= ~IGC_TQAVCC_IDLESLOPE_MASK;\n\t\t\ttqavcc |= cbs_value | IGC_TQAVCC_KEEP_CREDITS;\n\t\t\twr32(IGC_TQAVCC(i), tqavcc);\n\n\t\t\twr32(IGC_TQAVHC(i),\n\t\t\t     0x80000000 + ring->hicredit * 0x7735);\n\t\t} else {\n\t\t\t/* Disable any CBS for the queue */\n\t\t\ttxqctl &= ~(IGC_TXQCTL_QAV_SEL_MASK);\n\n\t\t\t/* Set idleSlope to zero. */\n\t\t\ttqavcc = rd32(IGC_TQAVCC(i));\n\t\t\ttqavcc &= ~(IGC_TQAVCC_IDLESLOPE_MASK |\n\t\t\t\t    IGC_TQAVCC_KEEP_CREDITS);\n\t\t\twr32(IGC_TQAVCC(i), tqavcc);\n\n\t\t\t/* Set hiCredit to zero. */\n\t\t\twr32(IGC_TQAVHC(i), 0);\n\t\t}\nskip_cbs:\n\t\twr32(IGC_TXQCTL(i), txqctl);\n\t}\n\n\tnsec = rd32(IGC_SYSTIML);\n\tsec = rd32(IGC_SYSTIMH);\n\n\tsystim = ktime_set(sec, nsec);\n\n\tif (ktime_compare(systim, base_time) > 0) {\n\t\ts64 n;\n\n\t\tn = div64_s64(ktime_sub_ns(systim, base_time), cycle);\n\t\tbase_time = ktime_add_ns(base_time, (n + 1) * cycle);\n\t}\n\n\tbaset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);\n\n\twr32(IGC_BASET_H, baset_h);\n\twr32(IGC_BASET_L, baset_l);\n\n\treturn 0;\n}",
        "static int __bpf_fill_alu_reg_pairs(struct bpf_test *self, u8 op, bool alu32)\n{\n\tint len = 2 + 10 * 10 * 12;\n\tu64 dst, src, res, same;\n\tstruct bpf_insn *insns;": "static int __bpf_fill_alu_reg_pairs(struct bpf_test *self, u8 op, bool alu32)\n{\n\tint len = 2 + 10 * 10 * 12;\n\tu64 dst, src, res, same;\n\tstruct bpf_insn *insns;\n\tint rd, rs;\n\tint i = 0;\n\n\tinsns = kmalloc_array(len, sizeof(*insns), GFP_KERNEL);\n\tif (!insns)\n\t\treturn -ENOMEM;\n\n\t/* Operand and result values according to operation */\n\tif (alu32) {\n\t\tdst = 0x76543210U;\n\t\tsrc = 0x01234567U;\n\t} else {\n\t\tdst = 0x7edcba9876543210ULL;\n\t\tsrc = 0x0123456789abcdefULL;\n\t}\n\n\tif (op == BPF_LSH || op == BPF_RSH || op == BPF_ARSH)\n\t\tsrc &= 31;\n\n\t__bpf_alu_result(&res, dst, src, op);\n\t__bpf_alu_result(&same, src, src, op);\n\n\tif (alu32) {\n\t\tres = (u32)res;\n\t\tsame = (u32)same;\n\t}\n\n\t/* Check all combinations of operand registers */\n\tfor (rd = R0; rd <= R9; rd++) {\n\t\tfor (rs = R0; rs <= R9; rs++) {\n\t\t\tu64 val = rd == rs ? same : res;\n\n\t\t\ti += __bpf_ld_imm64(&insns[i], rd, dst);\n\t\t\ti += __bpf_ld_imm64(&insns[i], rs, src);\n\n\t\t\tif (alu32)\n\t\t\t\tinsns[i++] = BPF_ALU32_REG(op, rd, rs);\n\t\t\telse\n\t\t\t\tinsns[i++] = BPF_ALU64_REG(op, rd, rs);\n\n\t\t\tinsns[i++] = BPF_JMP32_IMM(BPF_JEQ, rd, val, 2);\n\t\t\tinsns[i++] = BPF_MOV64_IMM(R0, __LINE__);\n\t\t\tinsns[i++] = BPF_EXIT_INSN();\n\n\t\t\tinsns[i++] = BPF_ALU64_IMM(BPF_RSH, rd, 32);\n\t\t\tinsns[i++] = BPF_JMP32_IMM(BPF_JEQ, rd, val >> 32, 2);\n\t\t\tinsns[i++] = BPF_MOV64_IMM(R0, __LINE__);\n\t\t\tinsns[i++] = BPF_EXIT_INSN();\n\t\t}\n\t}\n\n\tinsns[i++] = BPF_MOV64_IMM(R0, 1);\n\tinsns[i++] = BPF_EXIT_INSN();\n\n\tself->u.ptr.insns = insns;\n\tself->u.ptr.len = len;\n\tBUG_ON(i != len);\n\n\treturn 0;\n}",
        "static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n": "static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)\n{\n\tstruct i2c_device_addr *dev_addr = NULL;\n\tint rc;\n\n\tstatic const u8 vsb_ffe_leak_gain_ram0[] = {\n\t\tDRXJ_16TO8(0x8),\t/* FFETRAINLKRATIO1  */\n\t\tDRXJ_16TO8(0x8),\t/* FFETRAINLKRATIO2  */\n\t\tDRXJ_16TO8(0x8),\t/* FFETRAINLKRATIO3  */\n\t\tDRXJ_16TO8(0xf),\t/* FFETRAINLKRATIO4  */\n\t\tDRXJ_16TO8(0xf),\t/* FFETRAINLKRATIO5  */\n\t\tDRXJ_16TO8(0xf),\t/* FFETRAINLKRATIO6  */\n\t\tDRXJ_16TO8(0xf),\t/* FFETRAINLKRATIO7  */\n\t\tDRXJ_16TO8(0xf),\t/* FFETRAINLKRATIO8  */\n\t\tDRXJ_16TO8(0xf),\t/* FFETRAINLKRATIO9  */\n\t\tDRXJ_16TO8(0x8),\t/* FFETRAINLKRATIO10  */\n\t\tDRXJ_16TO8(0x8),\t/* FFETRAINLKRATIO11 */\n\t\tDRXJ_16TO8(0x8),\t/* FFETRAINLKRATIO12 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1TRAINLKRATIO1 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1TRAINLKRATIO2 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1TRAINLKRATIO3 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1TRAINLKRATIO4 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1TRAINLKRATIO5 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1TRAINLKRATIO6 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1TRAINLKRATIO7 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1TRAINLKRATIO8 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1TRAINLKRATIO9 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1TRAINLKRATIO10 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1TRAINLKRATIO11 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1TRAINLKRATIO12 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1DATALKRATIO1 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1DATALKRATIO2 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1DATALKRATIO3 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1DATALKRATIO4 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1DATALKRATIO5 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1DATALKRATIO6 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1DATALKRATIO7 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1DATALKRATIO8 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA1DATALKRATIO9 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1DATALKRATIO10 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1DATALKRATIO11 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA1DATALKRATIO12 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2TRAINLKRATIO1 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2TRAINLKRATIO2 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2TRAINLKRATIO3 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2TRAINLKRATIO4 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2TRAINLKRATIO5 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2TRAINLKRATIO6 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2TRAINLKRATIO7 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2TRAINLKRATIO8 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2TRAINLKRATIO9 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2TRAINLKRATIO10 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2TRAINLKRATIO11 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2TRAINLKRATIO12 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2DATALKRATIO1 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2DATALKRATIO2 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2DATALKRATIO3 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2DATALKRATIO4 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2DATALKRATIO5 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2DATALKRATIO6 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2DATALKRATIO7 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2DATALKRATIO8 */\n\t\tDRXJ_16TO8(0x20),\t/* FFERCA2DATALKRATIO9 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2DATALKRATIO10 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2DATALKRATIO11 */\n\t\tDRXJ_16TO8(0x10),\t/* FFERCA2DATALKRATIO12 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1TRAINLKRATIO1 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1TRAINLKRATIO2 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1TRAINLKRATIO3 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1TRAINLKRATIO4 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1TRAINLKRATIO5 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1TRAINLKRATIO6 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1TRAINLKRATIO7 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1TRAINLKRATIO8 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1TRAINLKRATIO9 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1TRAINLKRATIO10 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1TRAINLKRATIO11 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1TRAINLKRATIO12 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1DATALKRATIO1 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1DATALKRATIO2 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1DATALKRATIO3 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1DATALKRATIO4 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1DATALKRATIO5 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1DATALKRATIO6 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1DATALKRATIO7 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1DATALKRATIO8 */\n\t\tDRXJ_16TO8(0x0e),\t/* FFEDDM1DATALKRATIO9 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1DATALKRATIO10 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1DATALKRATIO11 */\n\t\tDRXJ_16TO8(0x07),\t/* FFEDDM1DATALKRATIO12 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2TRAINLKRATIO1 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2TRAINLKRATIO2 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2TRAINLKRATIO3 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2TRAINLKRATIO4 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2TRAINLKRATIO5 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2TRAINLKRATIO6 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2TRAINLKRATIO7 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2TRAINLKRATIO8 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2TRAINLKRATIO9 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2TRAINLKRATIO10 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2TRAINLKRATIO11 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2TRAINLKRATIO12 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2DATALKRATIO1 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2DATALKRATIO2 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2DATALKRATIO3 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2DATALKRATIO4 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2DATALKRATIO5 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2DATALKRATIO6 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2DATALKRATIO7 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2DATALKRATIO8 */\n\t\tDRXJ_16TO8(0x0c),\t/* FFEDDM2DATALKRATIO9 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2DATALKRATIO10 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2DATALKRATIO11 */\n\t\tDRXJ_16TO8(0x06),\t/* FFEDDM2DATALKRATIO12 */\n\t\tDRXJ_16TO8(0x2020),\t/* FIRTRAINGAIN1 */\n\t\tDRXJ_16TO8(0x2020),\t/* FIRTRAINGAIN2 */\n\t\tDRXJ_16TO8(0x2020),\t/* FIRTRAINGAIN3 */\n\t\tDRXJ_16TO8(0x4040),\t/* FIRTRAINGAIN4 */\n\t\tDRXJ_16TO8(0x4040),\t/* FIRTRAINGAIN5 */\n\t\tDRXJ_16TO8(0x4040),\t/* FIRTRAINGAIN6 */\n\t\tDRXJ_16TO8(0x4040),\t/* FIRTRAINGAIN7 */\n\t\tDRXJ_16TO8(0x4040),\t/* FIRTRAINGAIN8 */\n\t\tDRXJ_16TO8(0x4040),\t/* FIRTRAINGAIN9 */\n\t\tDRXJ_16TO8(0x2020),\t/* FIRTRAINGAIN10 */\n\t\tDRXJ_16TO8(0x2020),\t/* FIRTRAINGAIN11 */\n\t\tDRXJ_16TO8(0x2020),\t/* FIRTRAINGAIN12 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA1GAIN1 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA1GAIN2 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA1GAIN3 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA1GAIN4 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA1GAIN5 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA1GAIN6 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA1GAIN7 */\n\t\tDRXJ_16TO8(0x1010)\t/* FIRRCA1GAIN8 */\n\t};\n\n\tstatic const u8 vsb_ffe_leak_gain_ram1[] = {\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA1GAIN9 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA1GAIN10 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA1GAIN11 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA1GAIN12 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA2GAIN1 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA2GAIN2 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA2GAIN3 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA2GAIN4 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA2GAIN5 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA2GAIN6 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA2GAIN7 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA2GAIN8 */\n\t\tDRXJ_16TO8(0x1010),\t/* FIRRCA2GAIN9 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA2GAIN10 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA2GAIN11 */\n\t\tDRXJ_16TO8(0x0808),\t/* FIRRCA2GAIN12 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM1GAIN1 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM1GAIN2 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM1GAIN3 */\n\t\tDRXJ_16TO8(0x0606),\t/* FIRDDM1GAIN4 */\n\t\tDRXJ_16TO8(0x0606),\t/* FIRDDM1GAIN5 */\n\t\tDRXJ_16TO8(0x0606),\t/* FIRDDM1GAIN6 */\n\t\tDRXJ_16TO8(0x0606),\t/* FIRDDM1GAIN7 */\n\t\tDRXJ_16TO8(0x0606),\t/* FIRDDM1GAIN8 */\n\t\tDRXJ_16TO8(0x0606),\t/* FIRDDM1GAIN9 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM1GAIN10 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM1GAIN11 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM1GAIN12 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM2GAIN1 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM2GAIN2 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM2GAIN3 */\n\t\tDRXJ_16TO8(0x0505),\t/* FIRDDM2GAIN4 */\n\t\tDRXJ_16TO8(0x0505),\t/* FIRDDM2GAIN5 */\n\t\tDRXJ_16TO8(0x0505),\t/* FIRDDM2GAIN6 */\n\t\tDRXJ_16TO8(0x0505),\t/* FIRDDM2GAIN7 */\n\t\tDRXJ_16TO8(0x0505),\t/* FIRDDM2GAIN8 */\n\t\tDRXJ_16TO8(0x0505),\t/* FIRDDM2GAIN9 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM2GAIN10 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM2GAIN11 */\n\t\tDRXJ_16TO8(0x0303),\t/* FIRDDM2GAIN12 */\n\t\tDRXJ_16TO8(0x001f),\t/* DFETRAINLKRATIO */\n\t\tDRXJ_16TO8(0x01ff),\t/* DFERCA1TRAINLKRATIO */\n\t\tDRXJ_16TO8(0x01ff),\t/* DFERCA1DATALKRATIO */\n\t\tDRXJ_16TO8(0x004f),\t/* DFERCA2TRAINLKRATIO */\n\t\tDRXJ_16TO8(0x004f),\t/* DFERCA2DATALKRATIO */\n\t\tDRXJ_16TO8(0x01ff),\t/* DFEDDM1TRAINLKRATIO */\n\t\tDRXJ_16TO8(0x01ff),\t/* DFEDDM1DATALKRATIO */\n\t\tDRXJ_16TO8(0x0352),\t/* DFEDDM2TRAINLKRATIO */\n\t\tDRXJ_16TO8(0x0352),\t/* DFEDDM2DATALKRATIO */\n\t\tDRXJ_16TO8(0x0000),\t/* DFETRAINGAIN */\n\t\tDRXJ_16TO8(0x2020),\t/* DFERCA1GAIN */\n\t\tDRXJ_16TO8(0x1010),\t/* DFERCA2GAIN */\n\t\tDRXJ_16TO8(0x1818),\t/* DFEDDM1GAIN */\n\t\tDRXJ_16TO8(0x1212)\t/* DFEDDM2GAIN */\n\t};\n\n\tdev_addr = demod->my_i2c_dev_addr;\n\trc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)\n{\n\tu32 rcba, bspr, updcr;\n\tvoid __iomem *rcba_mem;\n": "static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)\n{\n\tu32 rcba, bspr, updcr;\n\tvoid __iomem *rcba_mem;\n\n\t/*\n\t * Read the RCBA register from the LPC (D31:F0).  PCH root ports\n\t * are D28:F* and therefore get probed before LPC, thus we can't\n\t * use pci_get_slot()/pci_read_config_dword() here.\n\t */\n\tpci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),\n\t\t\t\t  INTEL_LPC_RCBA_REG, &rcba);\n\tif (!(rcba & INTEL_LPC_RCBA_ENABLE))\n\t\treturn -EINVAL;\n\n\trcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,\n\t\t\t\t   PAGE_ALIGN(INTEL_UPDCR_REG));\n\tif (!rcba_mem)\n\t\treturn -ENOMEM;\n\n\t/*\n\t * The BSPR can disallow peer cycles, but it's set by soft strap and\n\t * therefore read-only.  If both posted and non-posted peer cycles are\n\t * disallowed, we're ok.  If either are allowed, then we need to use\n\t * the UPDCR to disable peer decodes for each port.  This provides the\n\t * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF\n\t */\n\tbspr = readl(rcba_mem + INTEL_BSPR_REG);\n\tbspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;\n\tif (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {\n\t\tupdcr = readl(rcba_mem + INTEL_UPDCR_REG);\n\t\tif (updcr & INTEL_UPDCR_REG_MASK) {\n\t\t\tpci_info(dev, \"Disabling UPDCR peer decodes\\n\");\n\t\t\tupdcr &= ~INTEL_UPDCR_REG_MASK;\n\t\t\twritel(updcr, rcba_mem + INTEL_UPDCR_REG);\n\t\t}\n\t}\n\n\tiounmap(rcba_mem);\n\treturn 0;\n}",
        "static void pwc_frame_complete(struct pwc_device *pdev)\n{\n\tstruct pwc_frame_buf *fbuf = pdev->fill_buf;\n\n\t/* The ToUCam Fun CMOS sensor causes the firmware to send 2 or 3 bogus": "static void pwc_frame_complete(struct pwc_device *pdev)\n{\n\tstruct pwc_frame_buf *fbuf = pdev->fill_buf;\n\n\t/* The ToUCam Fun CMOS sensor causes the firmware to send 2 or 3 bogus\n\t   frames on the USB wire after an exposure change. This conditition is\n\t   however detected  in the cam and a bit is set in the header.\n\t   */\n\tif (pdev->type == 730) {\n\t\tunsigned char *ptr = (unsigned char *)fbuf->data;\n\n\t\tif (ptr[1] == 1 && ptr[0] & 0x10) {\n\t\t\tPWC_TRACE(\"Hyundai CMOS sensor bug. Dropping frame.\\n\");\n\t\t\tpdev->drop_frames += 2;\n\t\t}\n\t\tif ((ptr[0] ^ pdev->vmirror) & 0x01) {\n\t\t\tpwc_snapshot_button(pdev, ptr[0] & 0x01);\n\t\t}\n\t\tif ((ptr[0] ^ pdev->vmirror) & 0x02) {\n\t\t\tif (ptr[0] & 0x02)\n\t\t\t\tPWC_TRACE(\"Image is mirrored.\\n\");\n\t\t\telse\n\t\t\t\tPWC_TRACE(\"Image is normal.\\n\");\n\t\t}\n\t\tpdev->vmirror = ptr[0] & 0x03;\n\t\t/* Sometimes the trailer of the 730 is still sent as a 4 byte packet\n\t\t   after a short frame; this condition is filtered out specifically. A 4 byte\n\t\t   frame doesn't make sense anyway.\n\t\t   So we get either this sequence:\n\t\t   drop_bit set -> 4 byte frame -> short frame -> good frame\n\t\t   Or this one:\n\t\t   drop_bit set -> short frame -> good frame\n\t\t   So we drop either 3 or 2 frames in all!\n\t\t   */\n\t\tif (fbuf->filled == 4)\n\t\t\tpdev->drop_frames++;\n\t} else if (pdev->type == 740 || pdev->type == 720) {\n\t\tunsigned char *ptr = (unsigned char *)fbuf->data;\n\t\tif ((ptr[0] ^ pdev->vmirror) & 0x01) {\n\t\t\tpwc_snapshot_button(pdev, ptr[0] & 0x01);\n\t\t}\n\t\tpdev->vmirror = ptr[0] & 0x03;\n\t}\n\n\t/* In case we were instructed to drop the frame, do so silently. */\n\tif (pdev->drop_frames > 0) {\n\t\tpdev->drop_frames--;\n\t} else {\n\t\t/* Check for underflow first */\n\t\tif (fbuf->filled < pdev->frame_total_size) {\n\t\t\tPWC_DEBUG_FLOW(\"Frame buffer underflow (%d bytes); discarded.\\n\",\n\t\t\t\t       fbuf->filled);\n\t\t} else {\n\t\t\tfbuf->vb.field = V4L2_FIELD_NONE;\n\t\t\tfbuf->vb.sequence = pdev->vframe_count;\n\t\t\tvb2_buffer_done(&fbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);\n\t\t\tpdev->fill_buf = NULL;\n\t\t\tpdev->vsync = 0;\n\t\t}\n\t} /* !drop_frames */\n\tpdev->vframe_count++;\n}",
        "static void s2io_handle_errors(void *dev_id)\n{\n\tstruct net_device *dev = (struct net_device *)dev_id;\n\tstruct s2io_nic *sp = netdev_priv(dev);\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;": "static void s2io_handle_errors(void *dev_id)\n{\n\tstruct net_device *dev = (struct net_device *)dev_id;\n\tstruct s2io_nic *sp = netdev_priv(dev);\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;\n\tu64 temp64 = 0, val64 = 0;\n\tint i = 0;\n\n\tstruct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;\n\tstruct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;\n\n\tif (!is_s2io_card_up(sp))\n\t\treturn;\n\n\tif (pci_channel_offline(sp->pdev))\n\t\treturn;\n\n\tmemset(&sw_stat->ring_full_cnt, 0,\n\t       sizeof(sw_stat->ring_full_cnt));\n\n\t/* Handling the XPAK counters update */\n\tif (stats->xpak_timer_count < 72000) {\n\t\t/* waiting for an hour */\n\t\tstats->xpak_timer_count++;\n\t} else {\n\t\ts2io_updt_xpak_counter(dev);\n\t\t/* reset the count to zero */\n\t\tstats->xpak_timer_count = 0;\n\t}\n\n\t/* Handling link status change error Intr */\n\tif (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {\n\t\tval64 = readq(&bar0->mac_rmac_err_reg);\n\t\twriteq(val64, &bar0->mac_rmac_err_reg);\n\t\tif (val64 & RMAC_LINK_STATE_CHANGE_INT)\n\t\t\tschedule_work(&sp->set_link_task);\n\t}\n\n\t/* In case of a serious error, the device will be Reset. */\n\tif (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,\n\t\t\t\t  &sw_stat->serious_err_cnt))\n\t\tgoto reset;\n\n\t/* Check for data parity error */\n\tif (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,\n\t\t\t\t  &sw_stat->parity_err_cnt))\n\t\tgoto reset;\n\n\t/* Check for ring full counter */\n\tif (sp->device_type == XFRAME_II_DEVICE) {\n\t\tval64 = readq(&bar0->ring_bump_counter1);\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\ttemp64 = (val64 & vBIT(0xFFFF, (i*16), 16));\n\t\t\ttemp64 >>= 64 - ((i+1)*16);\n\t\t\tsw_stat->ring_full_cnt[i] += temp64;\n\t\t}\n\n\t\tval64 = readq(&bar0->ring_bump_counter2);\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\ttemp64 = (val64 & vBIT(0xFFFF, (i*16), 16));\n\t\t\ttemp64 >>= 64 - ((i+1)*16);\n\t\t\tsw_stat->ring_full_cnt[i+4] += temp64;\n\t\t}\n\t}\n\n\tval64 = readq(&bar0->txdma_int_status);\n\t/*check for pfc_err*/\n\tif (val64 & TXDMA_PFC_INT) {\n\t\tif (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |\n\t\t\t\t\t  PFC_MISC_0_ERR | PFC_MISC_1_ERR |\n\t\t\t\t\t  PFC_PCIX_ERR,\n\t\t\t\t\t  &bar0->pfc_err_reg,\n\t\t\t\t\t  &sw_stat->pfc_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,\n\t\t\t\t      &bar0->pfc_err_reg,\n\t\t\t\t      &sw_stat->pfc_err_cnt);\n\t}\n\n\t/*check for tda_err*/\n\tif (val64 & TXDMA_TDA_INT) {\n\t\tif (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |\n\t\t\t\t\t  TDA_SM0_ERR_ALARM |\n\t\t\t\t\t  TDA_SM1_ERR_ALARM,\n\t\t\t\t\t  &bar0->tda_err_reg,\n\t\t\t\t\t  &sw_stat->tda_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,\n\t\t\t\t      &bar0->tda_err_reg,\n\t\t\t\t      &sw_stat->tda_err_cnt);\n\t}\n\t/*check for pcc_err*/\n\tif (val64 & TXDMA_PCC_INT) {\n\t\tif (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |\n\t\t\t\t\t  PCC_N_SERR | PCC_6_COF_OV_ERR |\n\t\t\t\t\t  PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |\n\t\t\t\t\t  PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |\n\t\t\t\t\t  PCC_TXB_ECC_DB_ERR,\n\t\t\t\t\t  &bar0->pcc_err_reg,\n\t\t\t\t\t  &sw_stat->pcc_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,\n\t\t\t\t      &bar0->pcc_err_reg,\n\t\t\t\t      &sw_stat->pcc_err_cnt);\n\t}\n\n\t/*check for tti_err*/\n\tif (val64 & TXDMA_TTI_INT) {\n\t\tif (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,\n\t\t\t\t\t  &bar0->tti_err_reg,\n\t\t\t\t\t  &sw_stat->tti_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,\n\t\t\t\t      &bar0->tti_err_reg,\n\t\t\t\t      &sw_stat->tti_err_cnt);\n\t}\n\n\t/*check for lso_err*/\n\tif (val64 & TXDMA_LSO_INT) {\n\t\tif (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |\n\t\t\t\t\t  LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,\n\t\t\t\t\t  &bar0->lso_err_reg,\n\t\t\t\t\t  &sw_stat->lso_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,\n\t\t\t\t      &bar0->lso_err_reg,\n\t\t\t\t      &sw_stat->lso_err_cnt);\n\t}\n\n\t/*check for tpa_err*/\n\tif (val64 & TXDMA_TPA_INT) {\n\t\tif (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,\n\t\t\t\t\t  &bar0->tpa_err_reg,\n\t\t\t\t\t  &sw_stat->tpa_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,\n\t\t\t\t      &bar0->tpa_err_reg,\n\t\t\t\t      &sw_stat->tpa_err_cnt);\n\t}\n\n\t/*check for sm_err*/\n\tif (val64 & TXDMA_SM_INT) {\n\t\tif (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,\n\t\t\t\t\t  &bar0->sm_err_reg,\n\t\t\t\t\t  &sw_stat->sm_err_cnt))\n\t\t\tgoto reset;\n\t}\n\n\tval64 = readq(&bar0->mac_int_status);\n\tif (val64 & MAC_INT_STATUS_TMAC_INT) {\n\t\tif (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,\n\t\t\t\t\t  &bar0->mac_tmac_err_reg,\n\t\t\t\t\t  &sw_stat->mac_tmac_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |\n\t\t\t\t      TMAC_DESC_ECC_SG_ERR |\n\t\t\t\t      TMAC_DESC_ECC_DB_ERR,\n\t\t\t\t      &bar0->mac_tmac_err_reg,\n\t\t\t\t      &sw_stat->mac_tmac_err_cnt);\n\t}\n\n\tval64 = readq(&bar0->xgxs_int_status);\n\tif (val64 & XGXS_INT_STATUS_TXGXS) {\n\t\tif (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,\n\t\t\t\t\t  &bar0->xgxs_txgxs_err_reg,\n\t\t\t\t\t  &sw_stat->xgxs_txgxs_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,\n\t\t\t\t      &bar0->xgxs_txgxs_err_reg,\n\t\t\t\t      &sw_stat->xgxs_txgxs_err_cnt);\n\t}\n\n\tval64 = readq(&bar0->rxdma_int_status);\n\tif (val64 & RXDMA_INT_RC_INT_M) {\n\t\tif (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |\n\t\t\t\t\t  RC_FTC_ECC_DB_ERR |\n\t\t\t\t\t  RC_PRCn_SM_ERR_ALARM |\n\t\t\t\t\t  RC_FTC_SM_ERR_ALARM,\n\t\t\t\t\t  &bar0->rc_err_reg,\n\t\t\t\t\t  &sw_stat->rc_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |\n\t\t\t\t      RC_FTC_ECC_SG_ERR |\n\t\t\t\t      RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,\n\t\t\t\t      &sw_stat->rc_err_cnt);\n\t\tif (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |\n\t\t\t\t\t  PRC_PCI_AB_WR_Rn |\n\t\t\t\t\t  PRC_PCI_AB_F_WR_Rn,\n\t\t\t\t\t  &bar0->prc_pcix_err_reg,\n\t\t\t\t\t  &sw_stat->prc_pcix_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |\n\t\t\t\t      PRC_PCI_DP_WR_Rn |\n\t\t\t\t      PRC_PCI_DP_F_WR_Rn,\n\t\t\t\t      &bar0->prc_pcix_err_reg,\n\t\t\t\t      &sw_stat->prc_pcix_err_cnt);\n\t}\n\n\tif (val64 & RXDMA_INT_RPA_INT_M) {\n\t\tif (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,\n\t\t\t\t\t  &bar0->rpa_err_reg,\n\t\t\t\t\t  &sw_stat->rpa_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,\n\t\t\t\t      &bar0->rpa_err_reg,\n\t\t\t\t      &sw_stat->rpa_err_cnt);\n\t}\n\n\tif (val64 & RXDMA_INT_RDA_INT_M) {\n\t\tif (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |\n\t\t\t\t\t  RDA_FRM_ECC_DB_N_AERR |\n\t\t\t\t\t  RDA_SM1_ERR_ALARM |\n\t\t\t\t\t  RDA_SM0_ERR_ALARM |\n\t\t\t\t\t  RDA_RXD_ECC_DB_SERR,\n\t\t\t\t\t  &bar0->rda_err_reg,\n\t\t\t\t\t  &sw_stat->rda_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |\n\t\t\t\t      RDA_FRM_ECC_SG_ERR |\n\t\t\t\t      RDA_MISC_ERR |\n\t\t\t\t      RDA_PCIX_ERR,\n\t\t\t\t      &bar0->rda_err_reg,\n\t\t\t\t      &sw_stat->rda_err_cnt);\n\t}\n\n\tif (val64 & RXDMA_INT_RTI_INT_M) {\n\t\tif (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,\n\t\t\t\t\t  &bar0->rti_err_reg,\n\t\t\t\t\t  &sw_stat->rti_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,\n\t\t\t\t      &bar0->rti_err_reg,\n\t\t\t\t      &sw_stat->rti_err_cnt);\n\t}\n\n\tval64 = readq(&bar0->mac_int_status);\n\tif (val64 & MAC_INT_STATUS_RMAC_INT) {\n\t\tif (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,\n\t\t\t\t\t  &bar0->mac_rmac_err_reg,\n\t\t\t\t\t  &sw_stat->mac_rmac_err_cnt))\n\t\t\tgoto reset;\n\t\tdo_s2io_chk_alarm_bit(RMAC_UNUSED_INT |\n\t\t\t\t      RMAC_SINGLE_ECC_ERR |\n\t\t\t\t      RMAC_DOUBLE_ECC_ERR,\n\t\t\t\t      &bar0->mac_rmac_err_reg,\n\t\t\t\t      &sw_stat->mac_rmac_err_cnt);\n\t}\n\n\tval64 = readq(&bar0->xgxs_int_status);\n\tif (val64 & XGXS_INT_STATUS_RXGXS) {\n\t\tif (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,\n\t\t\t\t\t  &bar0->xgxs_rxgxs_err_reg,\n\t\t\t\t\t  &sw_stat->xgxs_rxgxs_err_cnt))\n\t\t\tgoto reset;\n\t}\n\n\tval64 = readq(&bar0->mc_int_status);\n\tif (val64 & MC_INT_STATUS_MC_INT) {\n\t\tif (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,\n\t\t\t\t\t  &bar0->mc_err_reg,\n\t\t\t\t\t  &sw_stat->mc_err_cnt))\n\t\t\tgoto reset;\n\n\t\t/* Handling Ecc errors */\n\t\tif (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {\n\t\t\twriteq(val64, &bar0->mc_err_reg);\n\t\t\tif (val64 & MC_ERR_REG_ECC_ALL_DBL) {\n\t\t\t\tsw_stat->double_ecc_errs++;\n\t\t\t\tif (sp->device_type != XFRAME_II_DEVICE) {\n\t\t\t\t\t/*\n\t\t\t\t\t * Reset XframeI only if critical error\n\t\t\t\t\t */\n\t\t\t\t\tif (val64 &\n\t\t\t\t\t    (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |\n\t\t\t\t\t     MC_ERR_REG_MIRI_ECC_DB_ERR_1))\n\t\t\t\t\t\tgoto reset;\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tsw_stat->single_ecc_errs++;\n\t\t}\n\t}\n\treturn;\n\nreset:\n\ts2io_stop_all_tx_queue(sp);\n\tschedule_work(&sp->rst_timer_task);\n\tsw_stat->soft_reset_cnt++;\n}",
        "static void __init test_bitfields_constants(struct kunit *context)\n{\n\t/*\n\t * NOTE\n\t * This whole function compiles (or at least should, if everything": "static void __init test_bitfields_constants(struct kunit *context)\n{\n\t/*\n\t * NOTE\n\t * This whole function compiles (or at least should, if everything\n\t * is going according to plan) to nothing after optimisation.\n\t */\n\n\tCHECK_ENC_GET(16,  1, 0x000f, 0x0001);\n\tCHECK_ENC_GET(16,  3, 0x00f0, 0x0030);\n\tCHECK_ENC_GET(16,  5, 0x0f00, 0x0500);\n\tCHECK_ENC_GET(16,  7, 0xf000, 0x7000);\n\tCHECK_ENC_GET(16, 14, 0x000f, 0x000e);\n\tCHECK_ENC_GET(16, 15, 0x00f0, 0x00f0);\n\n\tCHECK_ENC_GET_U(8,  1, 0x0f, 0x01);\n\tCHECK_ENC_GET_U(8,  3, 0xf0, 0x30);\n\tCHECK_ENC_GET_U(8, 14, 0x0f, 0x0e);\n\tCHECK_ENC_GET_U(8, 15, 0xf0, 0xf0);\n\n\tCHECK_ENC_GET(32,  1, 0x00000f00, 0x00000100);\n\tCHECK_ENC_GET(32,  3, 0x0000f000, 0x00003000);\n\tCHECK_ENC_GET(32,  5, 0x000f0000, 0x00050000);\n\tCHECK_ENC_GET(32,  7, 0x00f00000, 0x00700000);\n\tCHECK_ENC_GET(32, 14, 0x0f000000, 0x0e000000);\n\tCHECK_ENC_GET(32, 15, 0xf0000000, 0xf0000000);\n\n\tCHECK_ENC_GET(64,  1, 0x00000f0000000000ull, 0x0000010000000000ull);\n\tCHECK_ENC_GET(64,  3, 0x0000f00000000000ull, 0x0000300000000000ull);\n\tCHECK_ENC_GET(64,  5, 0x000f000000000000ull, 0x0005000000000000ull);\n\tCHECK_ENC_GET(64,  7, 0x00f0000000000000ull, 0x0070000000000000ull);\n\tCHECK_ENC_GET(64, 14, 0x0f00000000000000ull, 0x0e00000000000000ull);\n\tCHECK_ENC_GET(64, 15, 0xf000000000000000ull, 0xf000000000000000ull);\n}",
        "static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)\n{\n\tseq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |\n\t\t\t   SEQ_OPC_OPCODE(SPINOR_OP_EN4B));\n\tseq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |": "static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)\n{\n\tseq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |\n\t\t\t   SEQ_OPC_OPCODE(SPINOR_OP_EN4B));\n\tseq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |\n\t\t\t   SEQ_OPC_OPCODE(SPINOR_OP_WREN) |\n\t\t\t   SEQ_OPC_CSDEASSERT);\n\n\tseq->seq[0] = STFSM_INST_CMD2;\n\tseq->seq[1] = STFSM_INST_CMD1;\n\tseq->seq[2] = STFSM_INST_WAIT;\n\tseq->seq[3] = STFSM_INST_STOP;\n\n\tseq->seq_cfg = (SEQ_CFG_PADS_1 |\n\t\t\tSEQ_CFG_ERASE |\n\t\t\tSEQ_CFG_READNOTWRITE |\n\t\t\tSEQ_CFG_CSDEASSERT |\n\t\t\tSEQ_CFG_STARTSEQ);\n\n\treturn 0;\n}",
        "static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)\n{\n\tint reg, i, pos, status;\n\t/* link active 1, speed 3, bridge 0, contender 1, more packets 0 */\n\tu32 self_id = 0x8040c800;": "static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)\n{\n\tint reg, i, pos, status;\n\t/* link active 1, speed 3, bridge 0, contender 1, more packets 0 */\n\tu32 self_id = 0x8040c800;\n\n\treg = reg_read(ohci, OHCI1394_NodeID);\n\tif (!(reg & OHCI1394_NodeID_idValid)) {\n\t\tohci_notice(ohci,\n\t\t\t    \"node ID not valid, new bus reset in progress\\n\");\n\t\treturn -EBUSY;\n\t}\n\tself_id |= ((reg & 0x3f) << 24); /* phy ID */\n\n\treg = ohci_read_phy_reg(&ohci->card, 4);\n\tif (reg < 0)\n\t\treturn reg;\n\tself_id |= ((reg & 0x07) << 8); /* power class */\n\n\treg = ohci_read_phy_reg(&ohci->card, 1);\n\tif (reg < 0)\n\t\treturn reg;\n\tself_id |= ((reg & 0x3f) << 16); /* gap count */\n\n\tfor (i = 0; i < 3; i++) {\n\t\tstatus = get_status_for_port(ohci, i);\n\t\tif (status < 0)\n\t\t\treturn status;\n\t\tself_id |= ((status & 0x3) << (6 - (i * 2)));\n\t}\n\n\tself_id |= initiated_reset(ohci);\n\n\tpos = get_self_id_pos(ohci, self_id, self_id_count);\n\tif (pos >= 0) {\n\t\tmemmove(&(ohci->self_id_buffer[pos+1]),\n\t\t\t&(ohci->self_id_buffer[pos]),\n\t\t\t(self_id_count - pos) * sizeof(*ohci->self_id_buffer));\n\t\tohci->self_id_buffer[pos] = self_id;\n\t\tself_id_count++;\n\t}\n\treturn self_id_count;\n}",
        "static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tu16 rf_gain = 0;": "static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)\n{\n\tstruct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;\n\tint rc;\n\tu16 rf_gain = 0;\n\tu16 if_gain = 0;\n\tu16 if_agc_sns = 0;\n\tu16 if_agc_top = 0;\n\tu16 rf_agc_max = 0;\n\tu16 rf_agc_min = 0;\n\n\trc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\tif_gain &= IQM_AF_AGC_IF__M;\n\trc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);\n\tif (rc != 0) {\n\t\tpr_err(\"error %d\\n\", rc);\n\t\tgoto rw_error;\n\t}\n\trf_gain &= IQM_AF_AGC_RF__M;\n\n\tif_agc_sns = DRXJ_AGC_SNS;\n\tif_agc_top = DRXJ_AGC_TOP;\n\trf_agc_max = DRXJ_RFAGC_MAX;\n\trf_agc_min = DRXJ_RFAGC_MIN;\n\n\tif (if_gain > if_agc_top) {\n\t\tif (rf_gain > rf_agc_max)\n\t\t\t*sig_strength = 100;\n\t\telse if (rf_gain > rf_agc_min) {\n\t\t\tif (rf_agc_max == rf_agc_min) {\n\t\t\t\tpr_err(\"error: rf_agc_max == rf_agc_min\\n\");\n\t\t\t\treturn -EIO;\n\t\t\t}\n\t\t\t*sig_strength =\n\t\t\t75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -\n\t\t\t\t\t\t\t\trf_agc_min);\n\t\t} else\n\t\t\t*sig_strength = 75;\n\t} else if (if_gain > if_agc_sns) {\n\t\tif (if_agc_top == if_agc_sns) {\n\t\t\tpr_err(\"error: if_agc_top == if_agc_sns\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\t*sig_strength =\n\t\t20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);\n\t} else {\n\t\tif (!if_agc_sns) {\n\t\t\tpr_err(\"error: if_agc_sns is zero!\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\t*sig_strength = (20 * if_gain / if_agc_sns);\n\t}\n\n\tif (*sig_strength <= 7)\n\t\t*sig_strength = 0;\n\n\treturn 0;\nrw_error:\n\treturn rc;\n}",
        "static void hotkey_resume(void)\n{\n\ttpacpi_disable_brightness_delay();\n\n\tif (hotkey_status_set(true) < 0 ||": "static void hotkey_resume(void)\n{\n\ttpacpi_disable_brightness_delay();\n\n\tif (hotkey_status_set(true) < 0 ||\n\t    hotkey_mask_set(hotkey_acpi_mask) < 0)\n\t\tpr_err(\"error while attempting to reset the event firmware interface\\n\");\n\n\ttpacpi_send_radiosw_update();\n\ttpacpi_input_send_tabletsw();\n\thotkey_tablet_mode_notify_change();\n\thotkey_wakeup_reason_notify_change();\n\thotkey_wakeup_hotunplug_complete_notify_change();\n\thotkey_poll_setup_safe(false);\n\n\t/* restore previous mode of adapive keyboard of X1 Carbon */\n\tif (tp_features.has_adaptive_kbd) {\n\t\tif (!acpi_evalf(hkey_handle, NULL, \"STRW\", \"vd\",\n\t\t\t\t\tadaptive_keyboard_prev_mode)) {\n\t\t\tpr_err(\"Cannot set adaptive keyboard mode.\\n\");\n\t\t}\n\t}\n}",
        "static void do_test_info_raw(unsigned int test_num)\n{\n\tconst struct prog_info_raw_test *test = &info_raw_tests[test_num - 1];\n\tunsigned int raw_btf_size, linfo_str_off, linfo_size = 0;\n\tint btf_fd = -1, prog_fd = -1, err = 0;": "static void do_test_info_raw(unsigned int test_num)\n{\n\tconst struct prog_info_raw_test *test = &info_raw_tests[test_num - 1];\n\tunsigned int raw_btf_size, linfo_str_off, linfo_size = 0;\n\tint btf_fd = -1, prog_fd = -1, err = 0;\n\tvoid *raw_btf, *patched_linfo = NULL;\n\tconst char *ret_next_str;\n\tunion bpf_attr attr = {};\n\n\tif (!test__start_subtest(test->descr))\n\t\treturn;\n\n\traw_btf = btf_raw_create(&hdr_tmpl, test->raw_types,\n\t\t\t\t test->str_sec, test->str_sec_size,\n\t\t\t\t &raw_btf_size, &ret_next_str);\n\tif (!raw_btf)\n\t\treturn;\n\n\t*btf_log_buf = '\\0';\n\tbtf_fd = load_raw_btf(raw_btf, raw_btf_size);\n\tfree(raw_btf);\n\n\tif (CHECK(btf_fd < 0, \"invalid btf_fd errno:%d\", errno)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tif (*btf_log_buf && always_log)\n\t\tfprintf(stderr, \"\\n%s\", btf_log_buf);\n\t*btf_log_buf = '\\0';\n\n\tlinfo_str_off = ret_next_str - test->str_sec;\n\tpatched_linfo = patch_name_tbd(test->line_info,\n\t\t\t\t       test->str_sec, linfo_str_off,\n\t\t\t\t       test->str_sec_size, &linfo_size);\n\terr = libbpf_get_error(patched_linfo);\n\tif (err) {\n\t\tfprintf(stderr, \"error in creating raw bpf_line_info\");\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tattr.prog_type = test->prog_type;\n\tattr.insns = ptr_to_u64(test->insns);\n\tattr.insn_cnt = probe_prog_length(test->insns);\n\tattr.license = ptr_to_u64(\"GPL\");\n\tattr.prog_btf_fd = btf_fd;\n\tattr.func_info_rec_size = test->func_info_rec_size;\n\tattr.func_info_cnt = test->func_info_cnt;\n\tattr.func_info = ptr_to_u64(test->func_info);\n\tattr.log_buf = ptr_to_u64(btf_log_buf);\n\tattr.log_size = BTF_LOG_BUF_SIZE;\n\tattr.log_level = 1;\n\tif (linfo_size) {\n\t\tattr.line_info_rec_size = test->line_info_rec_size;\n\t\tattr.line_info = ptr_to_u64(patched_linfo);\n\t\tattr.line_info_cnt = linfo_size / attr.line_info_rec_size;\n\t}\n\n\tprog_fd = syscall(__NR_bpf, BPF_PROG_LOAD, &attr, sizeof(attr));\n\terr = ((prog_fd < 0) != test->expected_prog_load_failure);\n\tif (CHECK(err, \"prog_fd:%d expected_prog_load_failure:%u errno:%d\",\n\t\t  prog_fd, test->expected_prog_load_failure, errno) ||\n\t    CHECK(test->err_str && !strstr(btf_log_buf, test->err_str),\n\t\t  \"expected err_str:%s\", test->err_str)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tif (prog_fd < 0)\n\t\tgoto done;\n\n\terr = test_get_finfo(test, prog_fd);\n\tif (err)\n\t\tgoto done;\n\n\terr = test_get_linfo(test, patched_linfo,\n\t\t\t     attr.line_info_cnt - test->dead_code_cnt,\n\t\t\t     prog_fd);\n\tif (err)\n\t\tgoto done;\n\ndone:\n\tif (*btf_log_buf && (err || always_log))\n\t\tfprintf(stderr, \"\\n%s\", btf_log_buf);\n\n\tif (btf_fd >= 0)\n\t\tclose(btf_fd);\n\tif (prog_fd >= 0)\n\t\tclose(prog_fd);\n\n\tif (!libbpf_get_error(patched_linfo))\n\t\tfree(patched_linfo);\n}",
        "static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)\n{\n\t/*\n\t * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)\n\t * Not applicable for OMAP4.": "static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)\n{\n\t/*\n\t * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)\n\t * Not applicable for OMAP4.\n\t * Under certain rare conditions, RDR could be set again\n\t * when the bus is busy, then ignore the interrupt and\n\t * clear the interrupt.\n\t */\n\tif (stat & OMAP_I2C_STAT_RDR) {\n\t\t/* Step 1: If RDR is set, clear it */\n\t\tomap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);\n\n\t\t/* Step 2: */\n\t\tif (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)\n\t\t\t\t\t\t& OMAP_I2C_STAT_BB)) {\n\n\t\t\t/* Step 3: */\n\t\t\tif (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)\n\t\t\t\t\t\t& OMAP_I2C_STAT_RDR) {\n\t\t\t\tomap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);\n\t\t\t\tdev_dbg(omap->dev, \"RDR when bus is busy.\\n\");\n\t\t\t}\n\n\t\t}\n\t}\n}",
        "static void qcom_l3_cache__64bit_counter_start(struct perf_event *event)\n{\n\tstruct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);\n\tint idx = event->hw.idx;\n\tu32 evsel = get_event_type(event);": "static void qcom_l3_cache__64bit_counter_start(struct perf_event *event)\n{\n\tstruct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);\n\tint idx = event->hw.idx;\n\tu32 evsel = get_event_type(event);\n\tu32 gang;\n\n\t/* Set the odd counter to count the overflows of the even counter */\n\tgang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);\n\tgang |= GANG_EN(idx + 1);\n\twritel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG);\n\n\t/* Initialize the hardware counters and reset prev_count*/\n\tlocal64_set(&event->hw.prev_count, 0);\n\twritel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));\n\twritel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));\n\n\t/*\n\t * Set the event types, the upper half must use zero and the lower\n\t * half the actual event type\n\t */\n\twritel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1));\n\twritel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));\n\n\t/* Finally, enable the counters */\n\twritel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1));\n\twritel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET);\n\twritel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));\n\twritel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);\n}",
        "static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)\n{\n\tstruct tc358743_state *state = to_state(sd);\n\tstruct tc358743_platform_data *pdata = &state->pdata;\n": "static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)\n{\n\tstruct tc358743_state *state = to_state(sd);\n\tstruct tc358743_platform_data *pdata = &state->pdata;\n\n\t/* Default settings from REF_02, sheet \"Source HDMI\"\n\t * and custom settings as platform data */\n\ti2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);\n\ti2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |\n\t\t\tSET_FREQ_RANGE_MODE_CYCLES(1));\n\ti2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,\n\t\t\t(pdata->hdmi_phy_auto_reset_tmds_detected ?\n\t\t\t MASK_PHY_AUTO_RST2 : 0) |\n\t\t\t(pdata->hdmi_phy_auto_reset_tmds_in_range ?\n\t\t\t MASK_PHY_AUTO_RST3 : 0) |\n\t\t\t(pdata->hdmi_phy_auto_reset_tmds_valid ?\n\t\t\t MASK_PHY_AUTO_RST4 : 0));\n\ti2c_wr8(sd, PHY_BIAS, 0x40);\n\ti2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));\n\ti2c_wr8(sd, AVM_CTL, 45);\n\ti2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,\n\t\t\tpdata->hdmi_detection_delay << 4);\n\ti2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),\n\t\t\t(pdata->hdmi_phy_auto_reset_hsync_out_of_range ?\n\t\t\t MASK_H_PI_RST : 0) |\n\t\t\t(pdata->hdmi_phy_auto_reset_vsync_out_of_range ?\n\t\t\t MASK_V_PI_RST : 0));\n\ti2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);\n}",
        "static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tu64 *features = &mcam->rx_features;\n\tu64 tcp_udp_sctp;": "static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf)\n{\n\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n\tu64 *features = &mcam->rx_features;\n\tu64 tcp_udp_sctp;\n\tint hdr;\n\n\tif (is_npc_intf_tx(intf))\n\t\tfeatures = &mcam->tx_features;\n\n\tfor (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) {\n\t\tif (npc_check_field(rvu, blkaddr, hdr, intf))\n\t\t\t*features |= BIT_ULL(hdr);\n\t}\n\n\ttcp_udp_sctp = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) |\n\t\t       BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) |\n\t\t       BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP);\n\n\t/* for tcp/udp/sctp corresponding layer type should be in the key */\n\tif (*features & tcp_udp_sctp) {\n\t\tif (!npc_check_field(rvu, blkaddr, NPC_LD, intf))\n\t\t\t*features &= ~tcp_udp_sctp;\n\t\telse\n\t\t\t*features |= BIT_ULL(NPC_IPPROTO_TCP) |\n\t\t\t\t     BIT_ULL(NPC_IPPROTO_UDP) |\n\t\t\t\t     BIT_ULL(NPC_IPPROTO_SCTP);\n\t}\n\n\t/* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */\n\tif (npc_check_field(rvu, blkaddr, NPC_LD, intf)) {\n\t\t*features |= BIT_ULL(NPC_IPPROTO_AH);\n\t\t*features |= BIT_ULL(NPC_IPPROTO_ICMP);\n\t\t*features |= BIT_ULL(NPC_IPPROTO_ICMP6);\n\t}\n\n\t/* for ESP, check if corresponding layer type is present in the key */\n\tif (npc_check_field(rvu, blkaddr, NPC_LE, intf))\n\t\t*features |= BIT_ULL(NPC_IPPROTO_ESP);\n\n\t/* for vlan corresponding layer type should be in the key */\n\tif (*features & BIT_ULL(NPC_OUTER_VID))\n\t\tif (!npc_check_field(rvu, blkaddr, NPC_LB, intf))\n\t\t\t*features &= ~BIT_ULL(NPC_OUTER_VID);\n\n\t/* for vlan ethertypes corresponding layer type should be in the key */\n\tif (npc_check_field(rvu, blkaddr, NPC_LB, intf))\n\t\t*features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) |\n\t\t\t     BIT_ULL(NPC_VLAN_ETYPE_STAG);\n}",
        "static void ti_sci_setup_ops(struct ti_sci_info *info)\n{\n\tstruct ti_sci_ops *ops = &info->handle.ops;\n\tstruct ti_sci_core_ops *core_ops = &ops->core_ops;\n\tstruct ti_sci_dev_ops *dops = &ops->dev_ops;": "static void ti_sci_setup_ops(struct ti_sci_info *info)\n{\n\tstruct ti_sci_ops *ops = &info->handle.ops;\n\tstruct ti_sci_core_ops *core_ops = &ops->core_ops;\n\tstruct ti_sci_dev_ops *dops = &ops->dev_ops;\n\tstruct ti_sci_clk_ops *cops = &ops->clk_ops;\n\tstruct ti_sci_rm_core_ops *rm_core_ops = &ops->rm_core_ops;\n\tstruct ti_sci_rm_irq_ops *iops = &ops->rm_irq_ops;\n\tstruct ti_sci_rm_ringacc_ops *rops = &ops->rm_ring_ops;\n\tstruct ti_sci_rm_psil_ops *psilops = &ops->rm_psil_ops;\n\tstruct ti_sci_rm_udmap_ops *udmap_ops = &ops->rm_udmap_ops;\n\tstruct ti_sci_proc_ops *pops = &ops->proc_ops;\n\n\tcore_ops->reboot_device = ti_sci_cmd_core_reboot;\n\n\tdops->get_device = ti_sci_cmd_get_device;\n\tdops->get_device_exclusive = ti_sci_cmd_get_device_exclusive;\n\tdops->idle_device = ti_sci_cmd_idle_device;\n\tdops->idle_device_exclusive = ti_sci_cmd_idle_device_exclusive;\n\tdops->put_device = ti_sci_cmd_put_device;\n\n\tdops->is_valid = ti_sci_cmd_dev_is_valid;\n\tdops->get_context_loss_count = ti_sci_cmd_dev_get_clcnt;\n\tdops->is_idle = ti_sci_cmd_dev_is_idle;\n\tdops->is_stop = ti_sci_cmd_dev_is_stop;\n\tdops->is_on = ti_sci_cmd_dev_is_on;\n\tdops->is_transitioning = ti_sci_cmd_dev_is_trans;\n\tdops->set_device_resets = ti_sci_cmd_set_device_resets;\n\tdops->get_device_resets = ti_sci_cmd_get_device_resets;\n\n\tcops->get_clock = ti_sci_cmd_get_clock;\n\tcops->idle_clock = ti_sci_cmd_idle_clock;\n\tcops->put_clock = ti_sci_cmd_put_clock;\n\tcops->is_auto = ti_sci_cmd_clk_is_auto;\n\tcops->is_on = ti_sci_cmd_clk_is_on;\n\tcops->is_off = ti_sci_cmd_clk_is_off;\n\n\tcops->set_parent = ti_sci_cmd_clk_set_parent;\n\tcops->get_parent = ti_sci_cmd_clk_get_parent;\n\tcops->get_num_parents = ti_sci_cmd_clk_get_num_parents;\n\n\tcops->get_best_match_freq = ti_sci_cmd_clk_get_match_freq;\n\tcops->set_freq = ti_sci_cmd_clk_set_freq;\n\tcops->get_freq = ti_sci_cmd_clk_get_freq;\n\n\trm_core_ops->get_range = ti_sci_cmd_get_resource_range;\n\trm_core_ops->get_range_from_shost =\n\t\t\t\tti_sci_cmd_get_resource_range_from_shost;\n\n\tiops->set_irq = ti_sci_cmd_set_irq;\n\tiops->set_event_map = ti_sci_cmd_set_event_map;\n\tiops->free_irq = ti_sci_cmd_free_irq;\n\tiops->free_event_map = ti_sci_cmd_free_event_map;\n\n\trops->set_cfg = ti_sci_cmd_rm_ring_cfg;\n\n\tpsilops->pair = ti_sci_cmd_rm_psil_pair;\n\tpsilops->unpair = ti_sci_cmd_rm_psil_unpair;\n\n\tudmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;\n\tudmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;\n\tudmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;\n\n\tpops->request = ti_sci_cmd_proc_request;\n\tpops->release = ti_sci_cmd_proc_release;\n\tpops->handover = ti_sci_cmd_proc_handover;\n\tpops->set_config = ti_sci_cmd_proc_set_config;\n\tpops->set_control = ti_sci_cmd_proc_set_control;\n\tpops->get_status = ti_sci_cmd_proc_get_status;\n}",
        "static void kasan_global_oob_right(struct kunit *test)\n{\n\t/*\n\t * Deliberate out-of-bounds access. To prevent CONFIG_UBSAN_LOCAL_BOUNDS\n\t * from failing here and panicking the kernel, access the array via a": "static void kasan_global_oob_right(struct kunit *test)\n{\n\t/*\n\t * Deliberate out-of-bounds access. To prevent CONFIG_UBSAN_LOCAL_BOUNDS\n\t * from failing here and panicking the kernel, access the array via a\n\t * volatile pointer, which will prevent the compiler from being able to\n\t * determine the array bounds.\n\t *\n\t * This access uses a volatile pointer to char (char *volatile) rather\n\t * than the more conventional pointer to volatile char (volatile char *)\n\t * because we want to prevent the compiler from making inferences about\n\t * the pointer itself (i.e. its array bounds), not the data that it\n\t * refers to.\n\t */\n\tchar *volatile array = global_array;\n\tchar *p = &array[ARRAY_SIZE(global_array) + 3];\n\n\t/* Only generic mode instruments globals. */\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_GENERIC);\n\n\tKUNIT_EXPECT_KASAN_FAIL(test, *(volatile char *)p);\n}",
        "static void igb_update_ring_itr(struct igb_q_vector *q_vector)\n{\n\tint new_val = q_vector->itr_val;\n\tint avg_wire_size = 0;\n\tstruct igb_adapter *adapter = q_vector->adapter;": "static void igb_update_ring_itr(struct igb_q_vector *q_vector)\n{\n\tint new_val = q_vector->itr_val;\n\tint avg_wire_size = 0;\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tunsigned int packets;\n\n\t/* For non-gigabit speeds, just fix the interrupt rate at 4000\n\t * ints/sec - ITR timer value of 120 ticks.\n\t */\n\tif (adapter->link_speed != SPEED_1000) {\n\t\tnew_val = IGB_4K_ITR;\n\t\tgoto set_itr_val;\n\t}\n\n\tpackets = q_vector->rx.total_packets;\n\tif (packets)\n\t\tavg_wire_size = q_vector->rx.total_bytes / packets;\n\n\tpackets = q_vector->tx.total_packets;\n\tif (packets)\n\t\tavg_wire_size = max_t(u32, avg_wire_size,\n\t\t\t\t      q_vector->tx.total_bytes / packets);\n\n\t/* if avg_wire_size isn't set no work was done */\n\tif (!avg_wire_size)\n\t\tgoto clear_counts;\n\n\t/* Add 24 bytes to size to account for CRC, preamble, and gap */\n\tavg_wire_size += 24;\n\n\t/* Don't starve jumbo frames */\n\tavg_wire_size = min(avg_wire_size, 3000);\n\n\t/* Give a little boost to mid-size frames */\n\tif ((avg_wire_size > 300) && (avg_wire_size < 1200))\n\t\tnew_val = avg_wire_size / 3;\n\telse\n\t\tnew_val = avg_wire_size / 2;\n\n\t/* conservative mode (itr 3) eliminates the lowest_latency setting */\n\tif (new_val < IGB_20K_ITR &&\n\t    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||\n\t     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))\n\t\tnew_val = IGB_20K_ITR;\n\nset_itr_val:\n\tif (new_val != q_vector->itr_val) {\n\t\tq_vector->itr_val = new_val;\n\t\tq_vector->set_itr = 1;\n\t}\nclear_counts:\n\tq_vector->rx.total_bytes = 0;\n\tq_vector->rx.total_packets = 0;\n\tq_vector->tx.total_bytes = 0;\n\tq_vector->tx.total_packets = 0;\n}",
        "static unsigned int vdm_ready_timeout(u32 vdm_hdr)\n{\n\tunsigned int timeout;\n\tint cmd = PD_VDO_CMD(vdm_hdr);\n": "static unsigned int vdm_ready_timeout(u32 vdm_hdr)\n{\n\tunsigned int timeout;\n\tint cmd = PD_VDO_CMD(vdm_hdr);\n\n\t/* its not a structured VDM command */\n\tif (!PD_VDO_SVDM(vdm_hdr))\n\t\treturn PD_T_VDM_UNSTRUCTURED;\n\n\tswitch (PD_VDO_CMDT(vdm_hdr)) {\n\tcase CMDT_INIT:\n\t\tif (cmd == CMD_ENTER_MODE || cmd == CMD_EXIT_MODE)\n\t\t\ttimeout = PD_T_VDM_WAIT_MODE_E;\n\t\telse\n\t\t\ttimeout = PD_T_VDM_SNDR_RSP;\n\t\tbreak;\n\tdefault:\n\t\tif (cmd == CMD_ENTER_MODE || cmd == CMD_EXIT_MODE)\n\t\t\ttimeout = PD_T_VDM_E_MODE;\n\t\telse\n\t\t\ttimeout = PD_T_VDM_RCVR_RSP;\n\t\tbreak;\n\t}\n\treturn timeout;\n}",
        "static int __io_sq_thread(struct io_ring_ctx *ctx, bool cap_entries)\n{\n\tunsigned int to_submit;\n\tint ret = 0;\n": "static int __io_sq_thread(struct io_ring_ctx *ctx, bool cap_entries)\n{\n\tunsigned int to_submit;\n\tint ret = 0;\n\n\tto_submit = io_sqring_entries(ctx);\n\t/* if we're handling multiple rings, cap submit size for fairness */\n\tif (cap_entries && to_submit > IORING_SQPOLL_CAP_ENTRIES_VALUE)\n\t\tto_submit = IORING_SQPOLL_CAP_ENTRIES_VALUE;\n\n\tif (!wq_list_empty(&ctx->iopoll_list) || to_submit) {\n\t\tconst struct cred *creds = NULL;\n\n\t\tif (ctx->sq_creds != current_cred())\n\t\t\tcreds = override_creds(ctx->sq_creds);\n\n\t\tmutex_lock(&ctx->uring_lock);\n\t\tif (!wq_list_empty(&ctx->iopoll_list))\n\t\t\tio_do_iopoll(ctx, true);\n\n\t\t/*\n\t\t * Don't submit if refs are dying, good for io_uring_register(),\n\t\t * but also it is relied upon by io_ring_exit_work()\n\t\t */\n\t\tif (to_submit && likely(!percpu_ref_is_dying(&ctx->refs)) &&\n\t\t    !(ctx->flags & IORING_SETUP_R_DISABLED))\n\t\t\tret = io_submit_sqes(ctx, to_submit);\n\t\tmutex_unlock(&ctx->uring_lock);\n\n\t\tif (to_submit && wq_has_sleeper(&ctx->sqo_sq_wait))\n\t\t\twake_up(&ctx->sqo_sq_wait);\n\t\tif (creds)\n\t\t\trevert_creds(creds);\n\t}\n\n\treturn ret;\n}",
        "static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)\n{\n\tsigned int  i;\n\tu16 PPK[6];                          /* temporary key for mixing    */\n": "static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)\n{\n\tsigned int  i;\n\tu16 PPK[6];                          /* temporary key for mixing    */\n\n\t/* Note: all adds in the PPK[] equations below are mod 2**16         */\n\tfor (i = 0; i < 5; i++)\n\t\tPPK[i] = p1k[i];      /* first, copy P1K to PPK      */\n\n\tPPK[5]  =  p1k[4]+iv16;             /* next,  add in IV16          */\n\n\t/* Bijective non-linear mixing of the 96 bits of PPK[0..5]           */\n\tPPK[0] +=    _S_(PPK[5] ^ TK16(0));   /* Mix key in each \"round\"     */\n\tPPK[1] +=    _S_(PPK[0] ^ TK16(1));\n\tPPK[2] +=    _S_(PPK[1] ^ TK16(2));\n\tPPK[3] +=    _S_(PPK[2] ^ TK16(3));\n\tPPK[4] +=    _S_(PPK[3] ^ TK16(4));\n\tPPK[5] +=    _S_(PPK[4] ^ TK16(5));   /* Total # S-box lookups == 6  */\n\n\t/* Final sweep: bijective, \"linear\". Rotates kill LSB correlations   */\n\tPPK[0] +=  RotR1(PPK[5] ^ TK16(6));\n\tPPK[1] +=  RotR1(PPK[0] ^ TK16(7));   /* Use all of TK[] in Phase2   */\n\tPPK[2] +=  RotR1(PPK[1]);\n\tPPK[3] +=  RotR1(PPK[2]);\n\tPPK[4] +=  RotR1(PPK[3]);\n\tPPK[5] +=  RotR1(PPK[4]);\n\t/* Note: At this point, for a given key TK[0..15], the 96-bit output */\n\t/*       value PPK[0..5] is guaranteed to be unique, as a function   */\n\t/*       of the 96-bit \"input\" value   {TA, IV32, IV16}. That is, P1K  */\n\t/*       is now a keyed permutation of {TA, IV32, IV16}.               */\n\n\t/* Set RC4KEY[0..3], which includes \"cleartext\" portion of RC4 key   */\n\trc4key[0] = Hi8(iv16);                /* RC4KEY[0..2] is the WEP IV  */\n\trc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys  */\n\trc4key[2] = Lo8(iv16);\n\trc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);\n\n\n\t/* Copy 96 bits of PPK[0..5] to RC4KEY[4..15]  (little-endian)       */\n\tfor (i = 0; i < 6; i++) {\n\t\trc4key[4+2*i] = Lo8(PPK[i]);\n\t\trc4key[5+2*i] = Hi8(PPK[i]);\n\t}\n}",
        "static int mmcr0_cc56run(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n": "static int mmcr0_cc56run(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\n\t/* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\tSKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));\n\n\t /* Init the event for the sampling test */\n\tevent_init_sampling(&event, 0x500fa);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop(10000);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/* Verify that cc56run bit is set in MMCR0 */\n\tFAIL_IF(!get_mmcr0_cc56run(get_reg_value(intr_regs, \"MMCR0\"), 5));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static int rcu_torture_barrier_cbs(void *arg)\n{\n\tlong myid = (long)arg;\n\tbool lastphase = false;\n\tbool newphase;": "static int rcu_torture_barrier_cbs(void *arg)\n{\n\tlong myid = (long)arg;\n\tbool lastphase = false;\n\tbool newphase;\n\tstruct rcu_head rcu;\n\n\tinit_rcu_head_on_stack(&rcu);\n\tVERBOSE_TOROUT_STRING(\"rcu_torture_barrier_cbs task started\");\n\tset_user_nice(current, MAX_NICE);\n\tdo {\n\t\twait_event(barrier_cbs_wq[myid],\n\t\t\t   (newphase =\n\t\t\t    smp_load_acquire(&barrier_phase)) != lastphase ||\n\t\t\t   torture_must_stop());\n\t\tlastphase = newphase;\n\t\tif (torture_must_stop())\n\t\t\tbreak;\n\t\t/*\n\t\t * The above smp_load_acquire() ensures barrier_phase load\n\t\t * is ordered before the following ->call().\n\t\t */\n\t\tif (smp_call_function_single(myid, rcu_torture_barrier1cb,\n\t\t\t\t\t     &rcu, 1)) {\n\t\t\t// IPI failed, so use direct call from current CPU.\n\t\t\tcur_ops->call(&rcu, rcu_torture_barrier_cbf);\n\t\t}\n\t\tif (atomic_dec_and_test(&barrier_cbs_count))\n\t\t\twake_up(&barrier_wq);\n\t} while (!torture_must_stop());\n\tif (cur_ops->cb_barrier != NULL)\n\t\tcur_ops->cb_barrier();\n\tdestroy_rcu_head_on_stack(&rcu);\n\ttorture_kthread_stopping(\"rcu_torture_barrier_cbs\");\n\treturn 0;\n}",
        "static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)\n{\n\tu32 val;\n\n\t/*": "static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)\n{\n\tu32 val;\n\n\t/*\n\t * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->\n\t * Stop ISP(isp) ->wait for ISP isp off\n\t */\n\t/* stop and clear MI, MIPI, and ISP interrupts */\n\trkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC);\n\trkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);\n\n\trkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC);\n\trkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR);\n\n\trkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC);\n\trkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR);\n\tval = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);\n\trkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA),\n\t\t     RKISP1_CIF_MIPI_CTRL);\n\t/* stop ISP */\n\tval = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);\n\tval &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE |\n\t\t RKISP1_CIF_ISP_CTRL_ISP_ENABLE);\n\trkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);\n\n\tval = rkisp1_read(rkisp1,\tRKISP1_CIF_ISP_CTRL);\n\trkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD,\n\t\t     RKISP1_CIF_ISP_CTRL);\n\n\treadx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,\n\t\t\t   val, val & RKISP1_CIF_ISP_OFF, 20, 100);\n\trkisp1_write(rkisp1,\n\t\t     RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,\n\t\t     RKISP1_CIF_IRCL);\n\trkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);\n}",
        "static void iio_rescale_test_scale(struct kunit *test)\n{\n\tstruct rescale_tc_data *t = (struct rescale_tc_data *)test->param_value;\n\tchar *buff = kunit_kmalloc(test, PAGE_SIZE, GFP_KERNEL);\n\tstruct rescale rescale;": "static void iio_rescale_test_scale(struct kunit *test)\n{\n\tstruct rescale_tc_data *t = (struct rescale_tc_data *)test->param_value;\n\tchar *buff = kunit_kmalloc(test, PAGE_SIZE, GFP_KERNEL);\n\tstruct rescale rescale;\n\tint values[2];\n\tint rel_ppm;\n\tint ret;\n\n\trescale.numerator = t->numerator;\n\trescale.denominator = t->denominator;\n\trescale.offset = t->offset;\n\tvalues[0] = t->schan_val;\n\tvalues[1] = t->schan_val2;\n\n\tret = rescale_process_scale(&rescale, t->schan_scale_type,\n\t\t\t\t    &values[0], &values[1]);\n\n\tret = iio_format_value(buff, ret, 2, values);\n\tKUNIT_EXPECT_EQ(test, (int)strlen(buff), ret);\n\n\trel_ppm = iio_test_relative_error_ppm(buff, t->expected);\n\tKUNIT_EXPECT_GE_MSG(test, rel_ppm, 0, \"failed to compute ppm\\n\");\n\n\tKUNIT_EXPECT_EQ_MSG(test, rel_ppm, 0,\n\t\t\t    \"\\t    real=%s\"\n\t\t\t    \"\\texpected=%s\\n\",\n\t\t\t    buff, t->expected);\n}",
        "static int cas_phy_write(struct cas *cp, int reg, u16 val)\n{\n\tint limit = STOP_TRIES_PHY;\n\tu32 cmd;\n": "static int cas_phy_write(struct cas *cp, int reg, u16 val)\n{\n\tint limit = STOP_TRIES_PHY;\n\tu32 cmd;\n\n\tcmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;\n\tcmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);\n\tcmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);\n\tcmd |= MIF_FRAME_TURN_AROUND_MSB;\n\tcmd |= val & MIF_FRAME_DATA_MASK;\n\twritel(cmd, cp->regs + REG_MIF_FRAME);\n\n\t/* poll for completion */\n\twhile (limit-- > 0) {\n\t\tudelay(10);\n\t\tcmd = readl(cp->regs + REG_MIF_FRAME);\n\t\tif (cmd & MIF_FRAME_TURN_AROUND_LSB)\n\t\t\treturn 0;\n\t}\n\treturn -1;\n}",
        "static int alloc_try_nid_bottom_up_start_misaligned_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_bottom_up_start_misaligned_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_128;\n\tphys_addr_t misalign = SZ_2;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\tphys_addr_t rgn_end;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM() + misalign;\n\tmax_addr = min_addr + SZ_512;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr,\n\t\t\t\t\t       NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\trgn_end = rgn->base + rgn->size;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == min_addr + (SMP_CACHE_BYTES - misalign));\n\tassert(rgn_end < max_addr);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)\n{\n\tint core_dfx_regs_num =  ARRAY_SIZE(hzip_dump_dfx_regs);\n\tint com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs);\n\tstruct qm_debug *debug = &qm->debug;": "static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)\n{\n\tint core_dfx_regs_num =  ARRAY_SIZE(hzip_dump_dfx_regs);\n\tint com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs);\n\tstruct qm_debug *debug = &qm->debug;\n\tchar buf[HZIP_BUF_SIZE];\n\tvoid __iomem *base;\n\tint i, j, idx;\n\tu32 val;\n\n\tif (qm->fun_type == QM_HW_VF || !debug->last_words)\n\t\treturn;\n\n\tfor (i = 0; i < com_dfx_regs_num; i++) {\n\t\tval = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset);\n\t\tif (debug->last_words[i] != val)\n\t\t\tpci_info(qm->pdev, \"com_dfx: %s \\t= 0x%08x => 0x%08x\\n\",\n\t\t\t\thzip_com_dfx_regs[i].name, debug->last_words[i], val);\n\t}\n\n\tfor (i = 0; i < HZIP_CORE_NUM; i++) {\n\t\tif (i < HZIP_COMP_CORE_NUM)\n\t\t\tscnprintf(buf, sizeof(buf), \"Comp_core-%d\", i);\n\t\telse\n\t\t\tscnprintf(buf, sizeof(buf), \"Decomp_core-%d\",\n\t\t\t\t  i - HZIP_COMP_CORE_NUM);\n\t\tbase = qm->io_base + core_offsets[i];\n\n\t\tpci_info(qm->pdev, \"==>%s:\\n\", buf);\n\t\t/* dump last word for dfx regs during control resetting */\n\t\tfor (j = 0; j < core_dfx_regs_num; j++) {\n\t\t\tidx = com_dfx_regs_num + i * core_dfx_regs_num + j;\n\t\t\tval = readl_relaxed(base + hzip_dump_dfx_regs[j].offset);\n\t\t\tif (debug->last_words[idx] != val)\n\t\t\t\tpci_info(qm->pdev, \"%s \\t= 0x%08x => 0x%08x\\n\",\n\t\t\t\t\thzip_dump_dfx_regs[j].name, debug->last_words[idx], val);\n\t\t}\n\t}\n}",
        "static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)\n{\n\tstruct afex_stats afex_stats;\n\tu32 func = BP_ABS_FUNC(bp);\n\tu32 mf_config;": "static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)\n{\n\tstruct afex_stats afex_stats;\n\tu32 func = BP_ABS_FUNC(bp);\n\tu32 mf_config;\n\tu16 vlan_val;\n\tu32 vlan_prio;\n\tu16 vif_id;\n\tu8 allowed_prio;\n\tu8 vlan_mode;\n\tu32 addr_to_write, vifid, addrs, stats_type, i;\n\n\tif (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {\n\t\tvifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);\n\t\tDP(BNX2X_MSG_MCP,\n\t\t   \"afex: got MCP req LISTGET_REQ for vifid 0x%x\\n\", vifid);\n\t\tbnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);\n\t}\n\n\tif (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {\n\t\tvifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);\n\t\taddrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);\n\t\tDP(BNX2X_MSG_MCP,\n\t\t   \"afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\\n\",\n\t\t   vifid, addrs);\n\t\tbnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,\n\t\t\t\t\t       addrs);\n\t}\n\n\tif (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {\n\t\taddr_to_write = SHMEM2_RD(bp,\n\t\t\tafex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);\n\t\tstats_type = SHMEM2_RD(bp,\n\t\t\tafex_param1_to_driver[BP_FW_MB_IDX(bp)]);\n\n\t\tDP(BNX2X_MSG_MCP,\n\t\t   \"afex: got MCP req STATSGET_REQ, write to addr 0x%x\\n\",\n\t\t   addr_to_write);\n\n\t\tbnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);\n\n\t\t/* write response to scratchpad, for MCP */\n\t\tfor (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)\n\t\t\tREG_WR(bp, addr_to_write + i*sizeof(u32),\n\t\t\t       *(((u32 *)(&afex_stats))+i));\n\n\t\t/* send ack message to MCP */\n\t\tbnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);\n\t}\n\n\tif (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {\n\t\tmf_config = MF_CFG_RD(bp, func_mf_config[func].config);\n\t\tbp->mf_config[BP_VN(bp)] = mf_config;\n\t\tDP(BNX2X_MSG_MCP,\n\t\t   \"afex: got MCP req VIFSET_REQ, mf_config 0x%x\\n\",\n\t\t   mf_config);\n\n\t\t/* if VIF_SET is \"enabled\" */\n\t\tif (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {\n\t\t\t/* set rate limit directly to internal RAM */\n\t\t\tstruct cmng_init_input cmng_input;\n\t\t\tstruct rate_shaping_vars_per_vn m_rs_vn;\n\t\t\tsize_t size = sizeof(struct rate_shaping_vars_per_vn);\n\t\t\tu32 addr = BAR_XSTRORM_INTMEM +\n\t\t\t    XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));\n\n\t\t\tbp->mf_config[BP_VN(bp)] = mf_config;\n\n\t\t\tbnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);\n\t\t\tm_rs_vn.vn_counter.rate =\n\t\t\t\tcmng_input.vnic_max_rate[BP_VN(bp)];\n\t\t\tm_rs_vn.vn_counter.quota =\n\t\t\t\t(m_rs_vn.vn_counter.rate *\n\t\t\t\t RS_PERIODIC_TIMEOUT_USEC) / 8;\n\n\t\t\t__storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);\n\n\t\t\t/* read relevant values from mf_cfg struct in shmem */\n\t\t\tvif_id =\n\t\t\t\t(MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &\n\t\t\t\t FUNC_MF_CFG_E1HOV_TAG_MASK) >>\n\t\t\t\tFUNC_MF_CFG_E1HOV_TAG_SHIFT;\n\t\t\tvlan_val =\n\t\t\t\t(MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &\n\t\t\t\t FUNC_MF_CFG_AFEX_VLAN_MASK) >>\n\t\t\t\tFUNC_MF_CFG_AFEX_VLAN_SHIFT;\n\t\t\tvlan_prio = (mf_config &\n\t\t\t\t     FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>\n\t\t\t\t    FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;\n\t\t\tvlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);\n\t\t\tvlan_mode =\n\t\t\t\t(MF_CFG_RD(bp,\n\t\t\t\t\t   func_mf_config[func].afex_config) &\n\t\t\t\t FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>\n\t\t\t\tFUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;\n\t\t\tallowed_prio =\n\t\t\t\t(MF_CFG_RD(bp,\n\t\t\t\t\t   func_mf_config[func].afex_config) &\n\t\t\t\t FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>\n\t\t\t\tFUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;\n\n\t\t\t/* send ramrod to FW, return in case of failure */\n\t\t\tif (bnx2x_afex_func_update(bp, vif_id, vlan_val,\n\t\t\t\t\t\t   allowed_prio))\n\t\t\t\treturn;\n\n\t\t\tbp->afex_def_vlan_tag = vlan_val;\n\t\t\tbp->afex_vlan_mode = vlan_mode;\n\t\t} else {\n\t\t\t/* notify link down because BP->flags is disabled */\n\t\t\tbnx2x_link_report(bp);\n\n\t\t\t/* send INVALID VIF ramrod to FW */\n\t\t\tbnx2x_afex_func_update(bp, 0xFFFF, 0, 0);\n\n\t\t\t/* Reset the default afex VLAN */\n\t\t\tbp->afex_def_vlan_tag = -1;\n\t\t}\n\t}\n}",
        "static void perf_mmap_close(struct vm_area_struct *vma)\n{\n\tstruct perf_event *event = vma->vm_file->private_data;\n\tstruct perf_buffer *rb = ring_buffer_get(event);\n\tstruct user_struct *mmap_user = rb->mmap_user;": "static void perf_mmap_close(struct vm_area_struct *vma)\n{\n\tstruct perf_event *event = vma->vm_file->private_data;\n\tstruct perf_buffer *rb = ring_buffer_get(event);\n\tstruct user_struct *mmap_user = rb->mmap_user;\n\tint mmap_locked = rb->mmap_locked;\n\tunsigned long size = perf_data_size(rb);\n\tbool detach_rest = false;\n\n\tif (event->pmu->event_unmapped)\n\t\tevent->pmu->event_unmapped(event, vma->vm_mm);\n\n\t/*\n\t * rb->aux_mmap_count will always drop before rb->mmap_count and\n\t * event->mmap_count, so it is ok to use event->mmap_mutex to\n\t * serialize with perf_mmap here.\n\t */\n\tif (rb_has_aux(rb) && vma->vm_pgoff == rb->aux_pgoff &&\n\t    atomic_dec_and_mutex_lock(&rb->aux_mmap_count, &event->mmap_mutex)) {\n\t\t/*\n\t\t * Stop all AUX events that are writing to this buffer,\n\t\t * so that we can free its AUX pages and corresponding PMU\n\t\t * data. Note that after rb::aux_mmap_count dropped to zero,\n\t\t * they won't start any more (see perf_aux_output_begin()).\n\t\t */\n\t\tperf_pmu_output_stop(event);\n\n\t\t/* now it's safe to free the pages */\n\t\tatomic_long_sub(rb->aux_nr_pages - rb->aux_mmap_locked, &mmap_user->locked_vm);\n\t\tatomic64_sub(rb->aux_mmap_locked, &vma->vm_mm->pinned_vm);\n\n\t\t/* this has to be the last one */\n\t\trb_free_aux(rb);\n\t\tWARN_ON_ONCE(refcount_read(&rb->aux_refcount));\n\n\t\tmutex_unlock(&event->mmap_mutex);\n\t}\n\n\tif (atomic_dec_and_test(&rb->mmap_count))\n\t\tdetach_rest = true;\n\n\tif (!atomic_dec_and_mutex_lock(&event->mmap_count, &event->mmap_mutex))\n\t\tgoto out_put;\n\n\tring_buffer_attach(event, NULL);\n\tmutex_unlock(&event->mmap_mutex);\n\n\t/* If there's still other mmap()s of this buffer, we're done. */\n\tif (!detach_rest)\n\t\tgoto out_put;\n\n\t/*\n\t * No other mmap()s, detach from all other events that might redirect\n\t * into the now unreachable buffer. Somewhat complicated by the\n\t * fact that rb::event_lock otherwise nests inside mmap_mutex.\n\t */\nagain:\n\trcu_read_lock();\n\tlist_for_each_entry_rcu(event, &rb->event_list, rb_entry) {\n\t\tif (!atomic_long_inc_not_zero(&event->refcount)) {\n\t\t\t/*\n\t\t\t * This event is en-route to free_event() which will\n\t\t\t * detach it and remove it from the list.\n\t\t\t */\n\t\t\tcontinue;\n\t\t}\n\t\trcu_read_unlock();\n\n\t\tmutex_lock(&event->mmap_mutex);\n\t\t/*\n\t\t * Check we didn't race with perf_event_set_output() which can\n\t\t * swizzle the rb from under us while we were waiting to\n\t\t * acquire mmap_mutex.\n\t\t *\n\t\t * If we find a different rb; ignore this event, a next\n\t\t * iteration will no longer find it on the list. We have to\n\t\t * still restart the iteration to make sure we're not now\n\t\t * iterating the wrong list.\n\t\t */\n\t\tif (event->rb == rb)\n\t\t\tring_buffer_attach(event, NULL);\n\n\t\tmutex_unlock(&event->mmap_mutex);\n\t\tput_event(event);\n\n\t\t/*\n\t\t * Restart the iteration; either we're on the wrong list or\n\t\t * destroyed its integrity by doing a deletion.\n\t\t */\n\t\tgoto again;\n\t}\n\trcu_read_unlock();\n\n\t/*\n\t * It could be there's still a few 0-ref events on the list; they'll\n\t * get cleaned up by free_event() -- they'll also still have their\n\t * ref on the rb and will free it whenever they are done with it.\n\t *\n\t * Aside from that, this buffer is 'fully' detached and unmapped,\n\t * undo the VM accounting.\n\t */\n\n\tatomic_long_sub((size >> PAGE_SHIFT) + 1 - mmap_locked,\n\t\t\t&mmap_user->locked_vm);\n\tatomic64_sub(mmap_locked, &vma->vm_mm->pinned_vm);\n\tfree_uid(mmap_user);\n\nout_put:\n\tring_buffer_put(rb); /* could be last */\n}",
        "static void rcu_do_batch(struct rcu_data *rdp)\n{\n\tint div;\n\tbool __maybe_unused empty;\n\tunsigned long flags;": "static void rcu_do_batch(struct rcu_data *rdp)\n{\n\tint div;\n\tbool __maybe_unused empty;\n\tunsigned long flags;\n\tstruct rcu_head *rhp;\n\tstruct rcu_cblist rcl = RCU_CBLIST_INITIALIZER(rcl);\n\tlong bl, count = 0;\n\tlong pending, tlimit = 0;\n\n\t/* If no callbacks are ready, just return. */\n\tif (!rcu_segcblist_ready_cbs(&rdp->cblist)) {\n\t\ttrace_rcu_batch_start(rcu_state.name,\n\t\t\t\t      rcu_segcblist_n_cbs(&rdp->cblist), 0);\n\t\ttrace_rcu_batch_end(rcu_state.name, 0,\n\t\t\t\t    !rcu_segcblist_empty(&rdp->cblist),\n\t\t\t\t    need_resched(), is_idle_task(current),\n\t\t\t\t    rcu_is_callbacks_kthread());\n\t\treturn;\n\t}\n\n\t/*\n\t * Extract the list of ready callbacks, disabling IRQs to prevent\n\t * races with call_rcu() from interrupt handlers.  Leave the\n\t * callback counts, as rcu_barrier() needs to be conservative.\n\t */\n\trcu_nocb_lock_irqsave(rdp, flags);\n\tWARN_ON_ONCE(cpu_is_offline(smp_processor_id()));\n\tpending = rcu_segcblist_n_cbs(&rdp->cblist);\n\tdiv = READ_ONCE(rcu_divisor);\n\tdiv = div < 0 ? 7 : div > sizeof(long) * 8 - 2 ? sizeof(long) * 8 - 2 : div;\n\tbl = max(rdp->blimit, pending >> div);\n\tif (in_serving_softirq() && unlikely(bl > 100)) {\n\t\tlong rrn = READ_ONCE(rcu_resched_ns);\n\n\t\trrn = rrn < NSEC_PER_MSEC ? NSEC_PER_MSEC : rrn > NSEC_PER_SEC ? NSEC_PER_SEC : rrn;\n\t\ttlimit = local_clock() + rrn;\n\t}\n\ttrace_rcu_batch_start(rcu_state.name,\n\t\t\t      rcu_segcblist_n_cbs(&rdp->cblist), bl);\n\trcu_segcblist_extract_done_cbs(&rdp->cblist, &rcl);\n\tif (rcu_rdp_is_offloaded(rdp))\n\t\trdp->qlen_last_fqs_check = rcu_segcblist_n_cbs(&rdp->cblist);\n\n\ttrace_rcu_segcb_stats(&rdp->cblist, TPS(\"SegCbDequeued\"));\n\trcu_nocb_unlock_irqrestore(rdp, flags);\n\n\t/* Invoke callbacks. */\n\ttick_dep_set_task(current, TICK_DEP_BIT_RCU);\n\trhp = rcu_cblist_dequeue(&rcl);\n\n\tfor (; rhp; rhp = rcu_cblist_dequeue(&rcl)) {\n\t\trcu_callback_t f;\n\n\t\tcount++;\n\t\tdebug_rcu_head_unqueue(rhp);\n\n\t\trcu_lock_acquire(&rcu_callback_map);\n\t\ttrace_rcu_invoke_callback(rcu_state.name, rhp);\n\n\t\tf = rhp->func;\n\t\tWRITE_ONCE(rhp->func, (rcu_callback_t)0L);\n\t\tf(rhp);\n\n\t\trcu_lock_release(&rcu_callback_map);\n\n\t\t/*\n\t\t * Stop only if limit reached and CPU has something to do.\n\t\t */\n\t\tif (in_serving_softirq()) {\n\t\t\tif (count >= bl && (need_resched() || !is_idle_task(current)))\n\t\t\t\tbreak;\n\t\t\t/*\n\t\t\t * Make sure we don't spend too much time here and deprive other\n\t\t\t * softirq vectors of CPU cycles.\n\t\t\t */\n\t\t\tif (unlikely(tlimit)) {\n\t\t\t\t/* only call local_clock() every 32 callbacks */\n\t\t\t\tif (likely((count & 31) || local_clock() < tlimit))\n\t\t\t\t\tcontinue;\n\t\t\t\t/* Exceeded the time limit, so leave. */\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\tlocal_bh_enable();\n\t\t\tlockdep_assert_irqs_enabled();\n\t\t\tcond_resched_tasks_rcu_qs();\n\t\t\tlockdep_assert_irqs_enabled();\n\t\t\tlocal_bh_disable();\n\t\t}\n\t}\n\n\trcu_nocb_lock_irqsave(rdp, flags);\n\trdp->n_cbs_invoked += count;\n\ttrace_rcu_batch_end(rcu_state.name, count, !!rcl.head, need_resched(),\n\t\t\t    is_idle_task(current), rcu_is_callbacks_kthread());\n\n\t/* Update counts and requeue any remaining callbacks. */\n\trcu_segcblist_insert_done_cbs(&rdp->cblist, &rcl);\n\trcu_segcblist_add_len(&rdp->cblist, -count);\n\n\t/* Reinstate batch limit if we have worked down the excess. */\n\tcount = rcu_segcblist_n_cbs(&rdp->cblist);\n\tif (rdp->blimit >= DEFAULT_MAX_RCU_BLIMIT && count <= qlowmark)\n\t\trdp->blimit = blimit;\n\n\t/* Reset ->qlen_last_fqs_check trigger if enough CBs have drained. */\n\tif (count == 0 && rdp->qlen_last_fqs_check != 0) {\n\t\trdp->qlen_last_fqs_check = 0;\n\t\trdp->n_force_qs_snap = READ_ONCE(rcu_state.n_force_qs);\n\t} else if (count < rdp->qlen_last_fqs_check - qhimark)\n\t\trdp->qlen_last_fqs_check = count;\n\n\t/*\n\t * The following usually indicates a double call_rcu().  To track\n\t * this down, try building with CONFIG_DEBUG_OBJECTS_RCU_HEAD=y.\n\t */\n\tempty = rcu_segcblist_empty(&rdp->cblist);\n\tWARN_ON_ONCE(count == 0 && !empty);\n\tWARN_ON_ONCE(!IS_ENABLED(CONFIG_RCU_NOCB_CPU) &&\n\t\t     count != 0 && empty);\n\tWARN_ON_ONCE(count == 0 && rcu_segcblist_n_segment_cbs(&rdp->cblist) != 0);\n\tWARN_ON_ONCE(!empty && rcu_segcblist_n_segment_cbs(&rdp->cblist) == 0);\n\n\trcu_nocb_unlock_irqrestore(rdp, flags);\n\n\ttick_dep_clear_task(current, TICK_DEP_BIT_RCU);\n}",
        "static void revoke_at_queue_data(struct ceph_connection *con)\n{\n\tint boundary;\n\tint resid;\n": "static void revoke_at_queue_data(struct ceph_connection *con)\n{\n\tint boundary;\n\tint resid;\n\n\tWARN_ON(!data_len(con->out_msg));\n\tWARN_ON(!iov_iter_is_kvec(&con->v2.out_iter));\n\tresid = iov_iter_count(&con->v2.out_iter);\n\n\tboundary = front_len(con->out_msg) + middle_len(con->out_msg);\n\tif (resid > boundary) {\n\t\tresid -= boundary;\n\t\tWARN_ON(resid > MESSAGE_HEAD_PLAIN_LEN);\n\t\tdout(\"%s con %p was sending head\\n\", __func__, con);\n\t\tif (front_len(con->out_msg))\n\t\t\tprepare_zero_front(con, front_len(con->out_msg));\n\t\tif (middle_len(con->out_msg))\n\t\t\tprepare_zero_middle(con, middle_len(con->out_msg));\n\t\tprepare_zero_data(con);\n\t\tWARN_ON(iov_iter_count(&con->v2.out_iter) != resid);\n\t\tcon->v2.out_state = OUT_S_QUEUE_ZEROS;\n\t\treturn;\n\t}\n\n\tboundary = middle_len(con->out_msg);\n\tif (resid > boundary) {\n\t\tresid -= boundary;\n\t\tdout(\"%s con %p was sending front\\n\", __func__, con);\n\t\tprepare_zero_front(con, resid);\n\t\tif (middle_len(con->out_msg))\n\t\t\tprepare_zero_middle(con, middle_len(con->out_msg));\n\t\tprepare_zero_data(con);\n\t\tqueue_zeros(con);\n\t\treturn;\n\t}\n\n\tWARN_ON(!resid);\n\tdout(\"%s con %p was sending middle\\n\", __func__, con);\n\tprepare_zero_middle(con, resid);\n\tprepare_zero_data(con);\n\tqueue_zeros(con);\n}",
        "static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)\n{\n\tu64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;\n\tu32 status;\n\tu32 can_write;": "static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)\n{\n\tu64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;\n\tu32 status;\n\tu32 can_write;\n\n\tdev_dbg(priv->dev, \"Trying to write %.8x to idx %d\\n\", val, idx);\n\n\tdo {\n\t\tstatus = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);\n\t\tcan_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);\n\t} while (!can_write && time_is_after_jiffies64(timeout_time));\n\n\tif (!can_write) {\n\t\tdev_err(priv->dev, \"timeout trying to write %.8x at %d(%.8x)\\n\",\n\t\t\tval, idx, status);\n\t\treturn -ETIME;\n\t}\n\n\timx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);\n\n\treturn 0;\n}",
        "static void do_test_dedup(unsigned int test_num)\n{\n\tstruct btf_dedup_test *test = &dedup_tests[test_num - 1];\n\t__u32 test_nr_types, expect_nr_types, test_btf_size, expect_btf_size;\n\tconst struct btf_header *test_hdr, *expect_hdr;": "static void do_test_dedup(unsigned int test_num)\n{\n\tstruct btf_dedup_test *test = &dedup_tests[test_num - 1];\n\t__u32 test_nr_types, expect_nr_types, test_btf_size, expect_btf_size;\n\tconst struct btf_header *test_hdr, *expect_hdr;\n\tstruct btf *test_btf = NULL, *expect_btf = NULL;\n\tconst void *test_btf_data, *expect_btf_data;\n\tconst char *ret_test_next_str, *ret_expect_next_str;\n\tconst char *test_strs, *expect_strs;\n\tconst char *test_str_cur;\n\tconst char *expect_str_cur, *expect_str_end;\n\tunsigned int raw_btf_size;\n\tvoid *raw_btf;\n\tint err = 0, i;\n\n\tif (!test__start_subtest(test->descr))\n\t\treturn;\n\n\traw_btf = btf_raw_create(&hdr_tmpl, test->input.raw_types,\n\t\t\t\t test->input.str_sec, test->input.str_sec_size,\n\t\t\t\t &raw_btf_size, &ret_test_next_str);\n\tif (!raw_btf)\n\t\treturn;\n\n\ttest_btf = btf__new((__u8 *)raw_btf, raw_btf_size);\n\terr = libbpf_get_error(test_btf);\n\tfree(raw_btf);\n\tif (CHECK(err, \"invalid test_btf errno:%d\", err)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\traw_btf = btf_raw_create(&hdr_tmpl, test->expect.raw_types,\n\t\t\t\t test->expect.str_sec,\n\t\t\t\t test->expect.str_sec_size,\n\t\t\t\t &raw_btf_size, &ret_expect_next_str);\n\tif (!raw_btf)\n\t\treturn;\n\texpect_btf = btf__new((__u8 *)raw_btf, raw_btf_size);\n\terr = libbpf_get_error(expect_btf);\n\tfree(raw_btf);\n\tif (CHECK(err, \"invalid expect_btf errno:%d\", err)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\ttest->opts.sz = sizeof(test->opts);\n\terr = btf__dedup(test_btf, &test->opts);\n\tif (CHECK(err, \"btf_dedup failed errno:%d\", err)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\ttest_btf_data = btf__raw_data(test_btf, &test_btf_size);\n\texpect_btf_data = btf__raw_data(expect_btf, &expect_btf_size);\n\tif (CHECK(test_btf_size != expect_btf_size,\n\t\t  \"test_btf_size:%u != expect_btf_size:%u\",\n\t\t  test_btf_size, expect_btf_size)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\ttest_hdr = test_btf_data;\n\ttest_strs = test_btf_data + sizeof(*test_hdr) + test_hdr->str_off;\n\texpect_hdr = expect_btf_data;\n\texpect_strs = expect_btf_data + sizeof(*test_hdr) + expect_hdr->str_off;\n\tif (CHECK(test_hdr->str_len != expect_hdr->str_len,\n\t\t  \"test_hdr->str_len:%u != expect_hdr->str_len:%u\",\n\t\t  test_hdr->str_len, expect_hdr->str_len)) {\n\t\tfprintf(stderr, \"\\ntest strings:\\n\");\n\t\tdump_btf_strings(test_strs, test_hdr->str_len);\n\t\tfprintf(stderr, \"\\nexpected strings:\\n\");\n\t\tdump_btf_strings(expect_strs, expect_hdr->str_len);\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\texpect_str_cur = expect_strs;\n\texpect_str_end = expect_strs + expect_hdr->str_len;\n\twhile (expect_str_cur < expect_str_end) {\n\t\tsize_t test_len, expect_len;\n\t\tint off;\n\n\t\toff = btf__find_str(test_btf, expect_str_cur);\n\t\tif (CHECK(off < 0, \"exp str '%s' not found: %d\\n\", expect_str_cur, off)) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t\ttest_str_cur = btf__str_by_offset(test_btf, off);\n\n\t\ttest_len = strlen(test_str_cur);\n\t\texpect_len = strlen(expect_str_cur);\n\t\tif (CHECK(test_len != expect_len,\n\t\t\t  \"test_len:%zu != expect_len:%zu \"\n\t\t\t  \"(test_str:%s, expect_str:%s)\",\n\t\t\t  test_len, expect_len, test_str_cur, expect_str_cur)) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t\tif (CHECK(strcmp(test_str_cur, expect_str_cur),\n\t\t\t  \"test_str:%s != expect_str:%s\",\n\t\t\t  test_str_cur, expect_str_cur)) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t\texpect_str_cur += expect_len + 1;\n\t}\n\n\ttest_nr_types = btf__type_cnt(test_btf);\n\texpect_nr_types = btf__type_cnt(expect_btf);\n\tif (CHECK(test_nr_types != expect_nr_types,\n\t\t  \"test_nr_types:%u != expect_nr_types:%u\",\n\t\t  test_nr_types, expect_nr_types)) {\n\t\terr = -1;\n\t\tgoto done;\n\t}\n\n\tfor (i = 1; i < test_nr_types; i++) {\n\t\tconst struct btf_type *test_type, *expect_type;\n\t\tint test_size, expect_size;\n\n\t\ttest_type = btf__type_by_id(test_btf, i);\n\t\texpect_type = btf__type_by_id(expect_btf, i);\n\t\ttest_size = btf_type_size(test_type);\n\t\texpect_size = btf_type_size(expect_type);\n\n\t\tif (CHECK(test_size != expect_size,\n\t\t\t  \"type #%d: test_size:%d != expect_size:%u\",\n\t\t\t  i, test_size, expect_size)) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t\tif (CHECK(btf_kind(test_type) != btf_kind(expect_type),\n\t\t\t  \"type %d kind: exp %d != got %u\\n\",\n\t\t\t  i, btf_kind(expect_type), btf_kind(test_type))) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t\tif (CHECK(test_type->info != expect_type->info,\n\t\t\t  \"type %d info: exp %d != got %u\\n\",\n\t\t\t  i, expect_type->info, test_type->info)) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t\tif (CHECK(test_type->size != expect_type->size,\n\t\t\t  \"type %d size/type: exp %d != got %u\\n\",\n\t\t\t  i, expect_type->size, test_type->size)) {\n\t\t\terr = -1;\n\t\t\tgoto done;\n\t\t}\n\t}\n\ndone:\n\tbtf__free(test_btf);\n\tbtf__free(expect_btf);\n}",
        "static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)\n{\n\tstruct bnxt_coal_cap *coal_cap = &bp->coal_cap;\n\tstruct hwrm_ring_aggint_qcaps_output *resp;\n\tstruct hwrm_ring_aggint_qcaps_input *req;": "static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)\n{\n\tstruct bnxt_coal_cap *coal_cap = &bp->coal_cap;\n\tstruct hwrm_ring_aggint_qcaps_output *resp;\n\tstruct hwrm_ring_aggint_qcaps_input *req;\n\tint rc;\n\n\tcoal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;\n\tcoal_cap->num_cmpl_dma_aggr_max = 63;\n\tcoal_cap->num_cmpl_dma_aggr_during_int_max = 63;\n\tcoal_cap->cmpl_aggr_dma_tmr_max = 65535;\n\tcoal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;\n\tcoal_cap->int_lat_tmr_min_max = 65535;\n\tcoal_cap->int_lat_tmr_max_max = 65535;\n\tcoal_cap->num_cmpl_aggr_int_max = 65535;\n\tcoal_cap->timer_units = 80;\n\n\tif (bp->hwrm_spec_code < 0x10902)\n\t\treturn;\n\n\tif (hwrm_req_init(bp, req, HWRM_RING_AGGINT_QCAPS))\n\t\treturn;\n\n\tresp = hwrm_req_hold(bp, req);\n\trc = hwrm_req_send_silent(bp, req);\n\tif (!rc) {\n\t\tcoal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);\n\t\tcoal_cap->nq_params = le32_to_cpu(resp->nq_params);\n\t\tcoal_cap->num_cmpl_dma_aggr_max =\n\t\t\tle16_to_cpu(resp->num_cmpl_dma_aggr_max);\n\t\tcoal_cap->num_cmpl_dma_aggr_during_int_max =\n\t\t\tle16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);\n\t\tcoal_cap->cmpl_aggr_dma_tmr_max =\n\t\t\tle16_to_cpu(resp->cmpl_aggr_dma_tmr_max);\n\t\tcoal_cap->cmpl_aggr_dma_tmr_during_int_max =\n\t\t\tle16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);\n\t\tcoal_cap->int_lat_tmr_min_max =\n\t\t\tle16_to_cpu(resp->int_lat_tmr_min_max);\n\t\tcoal_cap->int_lat_tmr_max_max =\n\t\t\tle16_to_cpu(resp->int_lat_tmr_max_max);\n\t\tcoal_cap->num_cmpl_aggr_int_max =\n\t\t\tle16_to_cpu(resp->num_cmpl_aggr_int_max);\n\t\tcoal_cap->timer_units = le16_to_cpu(resp->timer_units);\n\t}\n\thwrm_req_drop(bp, req);\n}",
        "static int migrate_degrades_locality(struct task_struct *p, struct lb_env *env)\n{\n\tstruct numa_group *numa_group = rcu_dereference(p->numa_group);\n\tunsigned long src_weight, dst_weight;\n\tint src_nid, dst_nid, dist;": "static int migrate_degrades_locality(struct task_struct *p, struct lb_env *env)\n{\n\tstruct numa_group *numa_group = rcu_dereference(p->numa_group);\n\tunsigned long src_weight, dst_weight;\n\tint src_nid, dst_nid, dist;\n\n\tif (!static_branch_likely(&sched_numa_balancing))\n\t\treturn -1;\n\n\tif (!p->numa_faults || !(env->sd->flags & SD_NUMA))\n\t\treturn -1;\n\n\tsrc_nid = cpu_to_node(env->src_cpu);\n\tdst_nid = cpu_to_node(env->dst_cpu);\n\n\tif (src_nid == dst_nid)\n\t\treturn -1;\n\n\t/* Migrating away from the preferred node is always bad. */\n\tif (src_nid == p->numa_preferred_nid) {\n\t\tif (env->src_rq->nr_running > env->src_rq->nr_preferred_running)\n\t\t\treturn 1;\n\t\telse\n\t\t\treturn -1;\n\t}\n\n\t/* Encourage migration to the preferred node. */\n\tif (dst_nid == p->numa_preferred_nid)\n\t\treturn 0;\n\n\t/* Leaving a core idle is often worse than degrading locality. */\n\tif (env->idle == CPU_IDLE)\n\t\treturn -1;\n\n\tdist = node_distance(src_nid, dst_nid);\n\tif (numa_group) {\n\t\tsrc_weight = group_weight(p, src_nid, dist);\n\t\tdst_weight = group_weight(p, dst_nid, dist);\n\t} else {\n\t\tsrc_weight = task_weight(p, src_nid, dist);\n\t\tdst_weight = task_weight(p, dst_nid, dist);\n\t}\n\n\treturn dst_weight < src_weight;\n}",
        "static int __init i40e_init_module(void)\n{\n\tpr_info(\"%s: %s\\n\", i40e_driver_name, i40e_driver_string);\n\tpr_info(\"%s: %s\\n\", i40e_driver_name, i40e_copyright);\n": "static int __init i40e_init_module(void)\n{\n\tpr_info(\"%s: %s\\n\", i40e_driver_name, i40e_driver_string);\n\tpr_info(\"%s: %s\\n\", i40e_driver_name, i40e_copyright);\n\n\t/* There is no need to throttle the number of active tasks because\n\t * each device limits its own task using a state bit for scheduling\n\t * the service task, and the device tasks do not interfere with each\n\t * other, so we don't set a max task limit. We must set WQ_MEM_RECLAIM\n\t * since we need to be able to guarantee forward progress even under\n\t * memory pressure.\n\t */\n\ti40e_wq = alloc_workqueue(\"%s\", WQ_MEM_RECLAIM, 0, i40e_driver_name);\n\tif (!i40e_wq) {\n\t\tpr_err(\"%s: Failed to create workqueue\\n\", i40e_driver_name);\n\t\treturn -ENOMEM;\n\t}\n\n\ti40e_dbg_init();\n\treturn pci_register_driver(&i40e_driver);\n}",
        "static int ov490_initialize(struct rdacm21_device *dev)\n{\n\tu8 pid, ver, val;\n\tunsigned int i;\n\tint ret;": "static int ov490_initialize(struct rdacm21_device *dev)\n{\n\tu8 pid, ver, val;\n\tunsigned int i;\n\tint ret;\n\n\tov10640_power_up(dev);\n\n\t/*\n\t * Read OV490 Id to test communications. Give it up to 40msec to\n\t * exit from reset.\n\t */\n\tfor (i = 0; i < OV490_PID_TIMEOUT; ++i) {\n\t\tret = ov490_read_reg(dev, OV490_PID, &pid);\n\t\tif (ret == 0)\n\t\t\tbreak;\n\t\tusleep_range(1000, 2000);\n\t}\n\tif (i == OV490_PID_TIMEOUT) {\n\t\tdev_err(dev->dev, \"OV490 PID read failed (%d)\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tret = ov490_read_reg(dev, OV490_VER, &ver);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tif (OV490_ID(pid, ver) != OV490_ID_VAL) {\n\t\tdev_err(dev->dev, \"OV490 ID mismatch (0x%04x)\\n\",\n\t\t\tOV490_ID(pid, ver));\n\t\treturn -ENODEV;\n\t}\n\n\t/* Wait for firmware boot by reading streamon status. */\n\tfor (i = 0; i < OV490_OUTPUT_EN_TIMEOUT; ++i) {\n\t\tov490_read_reg(dev, OV490_ODS_CTRL, &val);\n\t\tif (val == OV490_ODS_CTRL_FRAME_OUTPUT_EN)\n\t\t\tbreak;\n\t\tusleep_range(1000, 2000);\n\t}\n\tif (i == OV490_OUTPUT_EN_TIMEOUT) {\n\t\tdev_err(dev->dev, \"Timeout waiting for firmware boot\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tret = ov10640_check_id(dev);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Program OV490 with register-value table. */\n\tfor (i = 0; i < ARRAY_SIZE(ov490_regs_wizard); ++i) {\n\t\tret = ov490_write(dev, ov490_regs_wizard[i].reg,\n\t\t\t\t  ov490_regs_wizard[i].val);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev->dev,\n\t\t\t\t\"%s: register %u (0x%04x) write failed (%d)\\n\",\n\t\t\t\t__func__, i, ov490_regs_wizard[i].reg, ret);\n\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tusleep_range(100, 150);\n\t}\n\n\t/*\n\t * The ISP is programmed with the content of a serial flash memory.\n\t * Read the firmware configuration to reflect it through the V4L2 APIs.\n\t */\n\tov490_read_reg(dev, OV490_ISP_HSIZE_HIGH, &val);\n\tdev->fmt.width = (val & 0xf) << 8;\n\tov490_read_reg(dev, OV490_ISP_HSIZE_LOW, &val);\n\tdev->fmt.width |= (val & 0xff);\n\n\tov490_read_reg(dev, OV490_ISP_VSIZE_HIGH, &val);\n\tdev->fmt.height = (val & 0xf) << 8;\n\tov490_read_reg(dev, OV490_ISP_VSIZE_LOW, &val);\n\tdev->fmt.height |= val & 0xff;\n\n\t/* Set bus width to 12 bits with [0:11] ordering. */\n\tov490_write_reg(dev, OV490_DVP_CTRL3, 0x10);\n\n\tdev_info(dev->dev, \"Identified RDACM21 camera module\\n\");\n\n\treturn 0;\n}",
        "static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)\n{\n\tu16 p_cfr_left_edge  = 0, p_cfr_right_edge = 0;\n\tu16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ;\n\tu16 max_constellation = DQPSK;": "static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)\n{\n\tu16 p_cfr_left_edge  = 0, p_cfr_right_edge = 0;\n\tu16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ;\n\tu16 max_constellation = DQPSK;\n\tint init_prbs;\n\tstruct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;\n\n\tif (autosearching)\n\t\tc->isdbt_partial_reception = 1;\n\n\t/* P_mode */\n\tdib8000_write_word(state, 10, (seq << 4));\n\n\t/* init mode */\n\tstate->mode = fft_to_mode(state);\n\n\t/* set guard */\n\ttmp = dib8000_read_word(state, 1);\n\tdib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));\n\n\tdib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));\n\n\t/* signal optimization parameter */\n\tif (c->isdbt_partial_reception) {\n\t\tstate->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];\n\t\tfor (i = 1; i < 3; i++)\n\t\t\tnbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;\n\t\tfor (i = 0; i < nbseg_diff; i++)\n\t\t\tstate->seg_diff_mask |= 1 << permu_seg[i+1];\n\t} else {\n\t\tfor (i = 0; i < 3; i++)\n\t\t\tnbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;\n\t\tfor (i = 0; i < nbseg_diff; i++)\n\t\t\tstate->seg_diff_mask |= 1 << permu_seg[i];\n\t}\n\n\tif (state->seg_diff_mask)\n\t\tdib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);\n\telse\n\t\tdib8000_write_word(state, 268, (2 << 9) | 39); /*init value */\n\n\tfor (i = 0; i < 3; i++)\n\t\tmax_constellation = dib8000_set_layer(state, i, max_constellation);\n\tif (autosearching == 0) {\n\t\tstate->layer_b_nb_seg = c->layer[1].segment_count;\n\t\tstate->layer_c_nb_seg = c->layer[2].segment_count;\n\t}\n\n\t/* WRITE: Mode & Diff mask */\n\tdib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);\n\n\tstate->differential_constellation = (state->seg_diff_mask != 0);\n\n\t/* channel estimation fine configuration */\n\tana_gain = dib8000_adp_fine_tune(state, max_constellation);\n\n\t/* update ana_gain depending on max constellation */\n\tdib8000_update_ana_gain(state, ana_gain);\n\n\t/* ---- ANA_FE ---- */\n\tif (c->isdbt_partial_reception) /* 3-segments */\n\t\tdib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);\n\telse\n\t\tdib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */\n\n\t/* TSB or ISDBT ? apply it now */\n\tif (c->isdbt_sb_mode) {\n\t\tdib8000_set_sb_channel(state);\n\t\tinit_prbs = dib8000_get_init_prbs(state,\n\t\t\t\t\t\t  c->isdbt_sb_subchannel);\n\t} else {\n\t\tdib8000_set_13seg_channel(state);\n\t\tinit_prbs = 0xfff;\n\t}\n\n\t/* SMALL */\n\tdib8000_small_fine_tune(state);\n\n\tdib8000_set_subchannel_prbs(state, init_prbs);\n\n\t/* ---- CHAN_BLK ---- */\n\tfor (i = 0; i < 13; i++) {\n\t\tif ((((~state->seg_diff_mask) >> i) & 1) == 1) {\n\t\t\tp_cfr_left_edge  += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));\n\t\t\tp_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));\n\t\t}\n\t}\n\tdib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */\n\tdib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */\n\t/* \"P_cspu_left_edge\" & \"P_cspu_right_edge\" not used => do not care */\n\n\tdib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */\n\tdib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */\n\tdib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */\n\n\tif (!autosearching)\n\t\tdib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */\n\telse\n\t\tdib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */\n\n\tdib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */\n\tdib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */\n\n\tdib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */\n\n\t/* ---- TMCC ---- */\n\tfor (i = 0; i < 3; i++)\n\t\ttmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ;\n\n\t/* Quantif of \"P_tmcc_dec_thres_?k\" is (0, 5+mode, 9); */\n\t/* Threshold is set at 1/4 of max power. */\n\ttmcc_pow *= (1 << (9-2));\n\tdib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */\n\tdib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */\n\tdib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */\n\t/*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */\n\n\t/* ---- PHA3 ---- */\n\tif (state->isdbt_cfg_loaded == 0)\n\t\tdib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */\n\n\tstate->isdbt_cfg_loaded = 0;\n}",
        "static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)\n{\n\tunsigned int ep;\n\tunsigned int addr;\n\tint timeout;": "static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)\n{\n\tunsigned int ep;\n\tunsigned int addr;\n\tint timeout;\n\n\tu32 val;\n\tu32 *txfsz = hsotg->params.g_tx_fifo_size;\n\n\t/* Reset fifo map if not correctly cleared during previous session */\n\tWARN_ON(hsotg->fifo_map);\n\thsotg->fifo_map = 0;\n\n\t/* set RX/NPTX FIFO sizes */\n\tdwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);\n\tdwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<\n\t\t    FIFOSIZE_STARTADDR_SHIFT) |\n\t\t    (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),\n\t\t    GNPTXFSIZ);\n\n\t/*\n\t * arange all the rest of the TX FIFOs, as some versions of this\n\t * block have overlapping default addresses. This also ensures\n\t * that if the settings have been changed, then they are set to\n\t * known values.\n\t */\n\n\t/* start at the end of the GNPTXFSIZ, rounded up */\n\taddr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;\n\n\t/*\n\t * Configure fifos sizes from provided configuration and assign\n\t * them to endpoints dynamically according to maxpacket size value of\n\t * given endpoint.\n\t */\n\tfor (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {\n\t\tif (!txfsz[ep])\n\t\t\tcontinue;\n\t\tval = addr;\n\t\tval |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;\n\t\tWARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,\n\t\t\t  \"insufficient fifo memory\");\n\t\taddr += txfsz[ep];\n\n\t\tdwc2_writel(hsotg, val, DPTXFSIZN(ep));\n\t\tval = dwc2_readl(hsotg, DPTXFSIZN(ep));\n\t}\n\n\tdwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |\n\t\t    addr << GDFIFOCFG_EPINFOBASE_SHIFT,\n\t\t    GDFIFOCFG);\n\t/*\n\t * according to p428 of the design guide, we need to ensure that\n\t * all fifos are flushed before continuing\n\t */\n\n\tdwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |\n\t       GRSTCTL_RXFFLSH, GRSTCTL);\n\n\t/* wait until the fifos are both flushed */\n\ttimeout = 100;\n\twhile (1) {\n\t\tval = dwc2_readl(hsotg, GRSTCTL);\n\n\t\tif ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)\n\t\t\tbreak;\n\n\t\tif (--timeout == 0) {\n\t\t\tdev_err(hsotg->dev,\n\t\t\t\t\"%s: timeout flushing fifos (GRSTCTL=%08x)\\n\",\n\t\t\t\t__func__, val);\n\t\t\tbreak;\n\t\t}\n\n\t\tudelay(1);\n\t}\n\n\tdev_dbg(hsotg->dev, \"FIFOs reset, timeout at %d\\n\", timeout);\n}",
        "static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)\n{\n\tint i;\n\n\tfor (i = 0; i < bus->slv_rd_ind; i++)": "static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)\n{\n\tint i;\n\n\tfor (i = 0; i < bus->slv_rd_ind; i++)\n\t\ti2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,\n\t\t\t\t&bus->slv_rd_buf[i]);\n\t/*\n\t * once we send bytes up, need to reset the counter of the wr buf\n\t * got data from master (new offset in device), ignore wr fifo:\n\t */\n\tif (bus->slv_rd_ind) {\n\t\tbus->slv_wr_size = 0;\n\t\tbus->slv_wr_ind = 0;\n\t}\n\n\tbus->slv_rd_ind = 0;\n\tbus->slv_rd_size = bus->adap.quirks->max_read_len;\n\n\tnpcm_i2c_clear_fifo_int(bus);\n\tnpcm_i2c_clear_rx_fifo(bus);\n}",
        "static int create_packet(void *data, size_t length)\n{\n\tstruct packet_data *newpacket;\n\tint ordernum = 0;\n\tint retval = 0;": "static int create_packet(void *data, size_t length)\n{\n\tstruct packet_data *newpacket;\n\tint ordernum = 0;\n\tint retval = 0;\n\tunsigned int packet_array_size = 0;\n\tvoid **invalid_addr_packet_array = NULL;\n\tvoid *packet_data_temp_buf = NULL;\n\tunsigned int idx = 0;\n\n\tpr_debug(\"entry\\n\");\n\n\tif (!rbu_data.packetsize) {\n\t\tpr_debug(\"packetsize not specified\\n\");\n\t\tretval = -EINVAL;\n\t\tgoto out_noalloc;\n\t}\n\n\tspin_unlock(&rbu_data.lock);\n\n\tnewpacket = kzalloc(sizeof (struct packet_data), GFP_KERNEL);\n\n\tif (!newpacket) {\n\t\tpr_warn(\"failed to allocate new packet\\n\");\n\t\tretval = -ENOMEM;\n\t\tspin_lock(&rbu_data.lock);\n\t\tgoto out_noalloc;\n\t}\n\n\tordernum = get_order(length);\n\n\t/*\n\t * BIOS errata mean we cannot allocate packets below 1MB or they will\n\t * be overwritten by BIOS.\n\t *\n\t * array to temporarily hold packets\n\t * that are below the allocation floor\n\t *\n\t * NOTE: very simplistic because we only need the floor to be at 1MB\n\t *       due to BIOS errata. This shouldn't be used for higher floors\n\t *       or you will run out of mem trying to allocate the array.\n\t */\n\tpacket_array_size = max_t(unsigned int, allocation_floor / rbu_data.packetsize, 1);\n\tinvalid_addr_packet_array = kcalloc(packet_array_size, sizeof(void *),\n\t\t\t\t\t\tGFP_KERNEL);\n\n\tif (!invalid_addr_packet_array) {\n\t\tpr_warn(\"failed to allocate invalid_addr_packet_array\\n\");\n\t\tretval = -ENOMEM;\n\t\tspin_lock(&rbu_data.lock);\n\t\tgoto out_alloc_packet;\n\t}\n\n\twhile (!packet_data_temp_buf) {\n\t\tpacket_data_temp_buf = (unsigned char *)\n\t\t\t__get_free_pages(GFP_KERNEL, ordernum);\n\t\tif (!packet_data_temp_buf) {\n\t\t\tpr_warn(\"failed to allocate new packet\\n\");\n\t\t\tretval = -ENOMEM;\n\t\t\tspin_lock(&rbu_data.lock);\n\t\t\tgoto out_alloc_packet_array;\n\t\t}\n\n\t\tif ((unsigned long)virt_to_phys(packet_data_temp_buf)\n\t\t\t\t< allocation_floor) {\n\t\t\tpr_debug(\"packet 0x%lx below floor at 0x%lx\\n\",\n\t\t\t\t\t(unsigned long)virt_to_phys(\n\t\t\t\t\t\tpacket_data_temp_buf),\n\t\t\t\t\tallocation_floor);\n\t\t\tinvalid_addr_packet_array[idx++] = packet_data_temp_buf;\n\t\t\tpacket_data_temp_buf = NULL;\n\t\t}\n\t}\n\t/*\n\t * set to uncachable or it may never get written back before reboot\n\t */\n\tset_memory_uc((unsigned long)packet_data_temp_buf, 1 << ordernum);\n\n\tspin_lock(&rbu_data.lock);\n\n\tnewpacket->data = packet_data_temp_buf;\n\n\tpr_debug(\"newpacket at physical addr %lx\\n\",\n\t\t(unsigned long)virt_to_phys(newpacket->data));\n\n\t/* packets may not have fixed size */\n\tnewpacket->length = length;\n\tnewpacket->ordernum = ordernum;\n\t++rbu_data.num_packets;\n\n\t/* initialize the newly created packet headers */\n\tINIT_LIST_HEAD(&newpacket->list);\n\tlist_add_tail(&newpacket->list, &packet_data_head.list);\n\n\tmemcpy(newpacket->data, data, length);\n\n\tpr_debug(\"exit\\n\");\n\nout_alloc_packet_array:\n\t/* always free packet array */\n\twhile (idx--) {\n\t\tpr_debug(\"freeing unused packet below floor 0x%lx\\n\",\n\t\t\t(unsigned long)virt_to_phys(invalid_addr_packet_array[idx]));\n\t\tfree_pages((unsigned long)invalid_addr_packet_array[idx], ordernum);\n\t}\n\tkfree(invalid_addr_packet_array);\n\nout_alloc_packet:\n\t/* if error, free data */\n\tif (retval)\n\t\tkfree(newpacket);\n\nout_noalloc:\n\treturn retval;\n}",
        "static void io_rsrc_file_put(struct io_ring_ctx *ctx, struct io_rsrc_put *prsrc)\n{\n\tstruct file *file = prsrc->file;\n#if defined(CONFIG_UNIX)\n\tstruct sock *sock = ctx->ring_sock->sk;": "static void io_rsrc_file_put(struct io_ring_ctx *ctx, struct io_rsrc_put *prsrc)\n{\n\tstruct file *file = prsrc->file;\n#if defined(CONFIG_UNIX)\n\tstruct sock *sock = ctx->ring_sock->sk;\n\tstruct sk_buff_head list, *head = &sock->sk_receive_queue;\n\tstruct sk_buff *skb;\n\tint i;\n\n\tif (!io_file_need_scm(file)) {\n\t\tfput(file);\n\t\treturn;\n\t}\n\n\t__skb_queue_head_init(&list);\n\n\t/*\n\t * Find the skb that holds this file in its SCM_RIGHTS. When found,\n\t * remove this entry and rearrange the file array.\n\t */\n\tskb = skb_dequeue(head);\n\twhile (skb) {\n\t\tstruct scm_fp_list *fp;\n\n\t\tfp = UNIXCB(skb).fp;\n\t\tfor (i = 0; i < fp->count; i++) {\n\t\t\tint left;\n\n\t\t\tif (fp->fp[i] != file)\n\t\t\t\tcontinue;\n\n\t\t\tunix_notinflight(fp->user, fp->fp[i]);\n\t\t\tleft = fp->count - 1 - i;\n\t\t\tif (left) {\n\t\t\t\tmemmove(&fp->fp[i], &fp->fp[i + 1],\n\t\t\t\t\t\tleft * sizeof(struct file *));\n\t\t\t}\n\t\t\tfp->count--;\n\t\t\tif (!fp->count) {\n\t\t\t\tkfree_skb(skb);\n\t\t\t\tskb = NULL;\n\t\t\t} else {\n\t\t\t\t__skb_queue_tail(&list, skb);\n\t\t\t}\n\t\t\tfput(file);\n\t\t\tfile = NULL;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!file)\n\t\t\tbreak;\n\n\t\t__skb_queue_tail(&list, skb);\n\n\t\tskb = skb_dequeue(head);\n\t}\n\n\tif (skb_peek(&list)) {\n\t\tspin_lock_irq(&head->lock);\n\t\twhile ((skb = __skb_dequeue(&list)) != NULL)\n\t\t\t__skb_queue_tail(head, skb);\n\t\tspin_unlock_irq(&head->lock);\n\t}\n#else\n\tfput(file);\n#endif\n}",
        "static const struct NTFS_DE *hdr_find_split(const struct INDEX_HDR *hdr)\n{\n\tsize_t o;\n\tconst struct NTFS_DE *e = hdr_first_de(hdr);\n\tu32 used_2 = le32_to_cpu(hdr->used) >> 1;": "static const struct NTFS_DE *hdr_find_split(const struct INDEX_HDR *hdr)\n{\n\tsize_t o;\n\tconst struct NTFS_DE *e = hdr_first_de(hdr);\n\tu32 used_2 = le32_to_cpu(hdr->used) >> 1;\n\tu16 esize;\n\n\tif (!e || de_is_last(e))\n\t\treturn NULL;\n\n\tesize = le16_to_cpu(e->size);\n\tfor (o = le32_to_cpu(hdr->de_off) + esize; o < used_2; o += esize) {\n\t\tconst struct NTFS_DE *p = e;\n\n\t\te = Add2Ptr(hdr, o);\n\n\t\t/* We must not return END entry. */\n\t\tif (de_is_last(e))\n\t\t\treturn p;\n\n\t\tesize = le16_to_cpu(e->size);\n\t}\n\n\treturn e;\n}",
        "static void add_ext_adv_data_complete(struct hci_dev *hdev, void *data, int err)\n{\n\tstruct mgmt_pending_cmd *cmd = data;\n\tstruct mgmt_cp_add_ext_adv_data *cp = cmd->param;\n\tstruct mgmt_rp_add_advertising rp;": "static void add_ext_adv_data_complete(struct hci_dev *hdev, void *data, int err)\n{\n\tstruct mgmt_pending_cmd *cmd = data;\n\tstruct mgmt_cp_add_ext_adv_data *cp = cmd->param;\n\tstruct mgmt_rp_add_advertising rp;\n\n\tadd_adv_complete(hdev, cmd->sk, cp->instance, err);\n\n\tmemset(&rp, 0, sizeof(rp));\n\n\trp.instance = cp->instance;\n\n\tif (err)\n\t\tmgmt_cmd_status(cmd->sk, cmd->index, cmd->opcode,\n\t\t\t\tmgmt_status(err));\n\telse\n\t\tmgmt_cmd_complete(cmd->sk, cmd->index, cmd->opcode,\n\t\t\t\t  mgmt_status(err), &rp, sizeof(rp));\n\n\tmgmt_pending_free(cmd);\n}",
        "static int cp2102n_gpioconf_init(struct usb_serial *serial)\n{\n\tstruct cp210x_serial_private *priv = usb_get_serial_data(serial);\n\tconst u16 config_size = 0x02a6;\n\tu8 gpio_rst_latch;": "static int cp2102n_gpioconf_init(struct usb_serial *serial)\n{\n\tstruct cp210x_serial_private *priv = usb_get_serial_data(serial);\n\tconst u16 config_size = 0x02a6;\n\tu8 gpio_rst_latch;\n\tu8 config_version;\n\tu8 gpio_pushpull;\n\tu8 *config_buf;\n\tu8 gpio_latch;\n\tu8 gpio_ctrl;\n\tint result;\n\tu8 i;\n\n\t/*\n\t * Retrieve device configuration from the device.\n\t * The array received contains all customization settings done at the\n\t * factory/manufacturer. Format of the array is documented at the\n\t * time of writing at:\n\t * https://www.silabs.com/community/interface/knowledge-base.entry.html/2017/03/31/cp2102n_setconfig-xsfa\n\t */\n\tconfig_buf = kmalloc(config_size, GFP_KERNEL);\n\tif (!config_buf)\n\t\treturn -ENOMEM;\n\n\tresult = cp210x_read_vendor_block(serial,\n\t\t\t\t\t  REQTYPE_DEVICE_TO_HOST,\n\t\t\t\t\t  CP210X_READ_2NCONFIG,\n\t\t\t\t\t  config_buf,\n\t\t\t\t\t  config_size);\n\tif (result < 0) {\n\t\tkfree(config_buf);\n\t\treturn result;\n\t}\n\n\tconfig_version = config_buf[CP210X_2NCONFIG_CONFIG_VERSION_IDX];\n\tgpio_pushpull = config_buf[CP210X_2NCONFIG_GPIO_MODE_IDX];\n\tgpio_ctrl = config_buf[CP210X_2NCONFIG_GPIO_CONTROL_IDX];\n\tgpio_rst_latch = config_buf[CP210X_2NCONFIG_GPIO_RSTLATCH_IDX];\n\n\tkfree(config_buf);\n\n\t/* Make sure this is a config format we understand. */\n\tif (config_version != 0x01)\n\t\treturn -ENOTSUPP;\n\n\tpriv->gc.ngpio = 4;\n\n\t/*\n\t * Get default pin states after reset. Needed so we can determine\n\t * the direction of an open-drain pin.\n\t */\n\tgpio_latch = (gpio_rst_latch >> 3) & 0x0f;\n\n\t/* 0 indicates open-drain mode, 1 is push-pull */\n\tpriv->gpio_pushpull = (gpio_pushpull >> 3) & 0x0f;\n\n\t/* 0 indicates GPIO mode, 1 is alternate function */\n\tif (priv->partnum == CP210X_PARTNUM_CP2102N_QFN20) {\n\t\t/* QFN20 is special... */\n\t\tif (gpio_ctrl & CP2102N_QFN20_GPIO0_CLK_MODE)   /* GPIO 0 */\n\t\t\tpriv->gpio_altfunc |= BIT(0);\n\t\tif (gpio_ctrl & CP2102N_QFN20_GPIO1_RS485_MODE) /* GPIO 1 */\n\t\t\tpriv->gpio_altfunc |= BIT(1);\n\t\tif (gpio_ctrl & CP2102N_QFN20_GPIO2_TXLED_MODE) /* GPIO 2 */\n\t\t\tpriv->gpio_altfunc |= BIT(2);\n\t\tif (gpio_ctrl & CP2102N_QFN20_GPIO3_RXLED_MODE) /* GPIO 3 */\n\t\t\tpriv->gpio_altfunc |= BIT(3);\n\t} else {\n\t\tpriv->gpio_altfunc = (gpio_ctrl >> 2) & 0x0f;\n\t}\n\n\tif (priv->partnum == CP210X_PARTNUM_CP2102N_QFN28) {\n\t\t/*\n\t\t * For the QFN28 package, GPIO4-6 are controlled by\n\t\t * the low three bits of the mode/latch fields.\n\t\t * Contrary to the document linked above, the bits for\n\t\t * the SUSPEND pins are elsewhere.  No alternate\n\t\t * function is available for these pins.\n\t\t */\n\t\tpriv->gc.ngpio = 7;\n\t\tgpio_latch |= (gpio_rst_latch & 7) << 4;\n\t\tpriv->gpio_pushpull |= (gpio_pushpull & 7) << 4;\n\t}\n\n\t/*\n\t * The CP2102N does not strictly has input and output pin modes,\n\t * it only knows open-drain and push-pull modes which is set at\n\t * factory. An open-drain pin can function both as an\n\t * input or an output. We emulate input mode for open-drain pins\n\t * by making sure they are not driven low, and we do not allow\n\t * push-pull pins to be set as an input.\n\t */\n\tfor (i = 0; i < priv->gc.ngpio; ++i) {\n\t\t/*\n\t\t * Set direction to \"input\" iff pin is open-drain and reset\n\t\t * value is 1.\n\t\t */\n\t\tif (!(priv->gpio_pushpull & BIT(i)) && (gpio_latch & BIT(i)))\n\t\t\tpriv->gpio_input |= BIT(i);\n\t}\n\n\treturn 0;\n}",
        "static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8168e_2[] = {\n\t\t{ 0x09, 0x0000,\t0x0080 },\n\t\t{ 0x19, 0x0000,\t0x0224 },": "static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)\n{\n\tstatic const struct ephy_info e_info_8168e_2[] = {\n\t\t{ 0x09, 0x0000,\t0x0080 },\n\t\t{ 0x19, 0x0000,\t0x0224 },\n\t\t{ 0x00, 0x0000,\t0x0004 },\n\t\t{ 0x0c, 0x3df0,\t0x0200 },\n\t};\n\n\trtl_set_def_aspm_entry_latency(tp);\n\n\trtl_ephy_init(tp, e_info_8168e_2);\n\n\trtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);\n\trtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);\n\trtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);\n\trtl_eri_set_bits(tp, 0x1d0, BIT(1));\n\trtl_reset_packet_filter(tp);\n\trtl_eri_set_bits(tp, 0x1b0, BIT(4));\n\trtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);\n\trtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);\n\n\trtl_disable_clock_request(tp);\n\n\tRTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);\n\n\trtl8168_config_eee_mac(tp);\n\n\tRTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);\n\tRTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);\n\tRTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);\n\n\trtl_hw_aspm_clkreq_enable(tp, true);\n}",
        "static void smcr_link_down(struct smc_link *lnk)\n{\n\tstruct smc_link_group *lgr = lnk->lgr;\n\tstruct smc_link *to_lnk;\n\tint del_link_id;": "static void smcr_link_down(struct smc_link *lnk)\n{\n\tstruct smc_link_group *lgr = lnk->lgr;\n\tstruct smc_link *to_lnk;\n\tint del_link_id;\n\n\tif (!lgr || lnk->state == SMC_LNK_UNUSED || list_empty(&lgr->list))\n\t\treturn;\n\n\tto_lnk = smc_switch_conns(lgr, lnk, true);\n\tif (!to_lnk) { /* no backup link available */\n\t\tsmcr_link_clear(lnk, true);\n\t\treturn;\n\t}\n\tsmcr_lgr_set_type(lgr, SMC_LGR_SINGLE);\n\tdel_link_id = lnk->link_id;\n\n\tif (lgr->role == SMC_SERV) {\n\t\t/* trigger local delete link processing */\n\t\tsmc_llc_srv_delete_link_local(to_lnk, del_link_id);\n\t} else {\n\t\tif (lgr->llc_flow_lcl.type != SMC_LLC_FLOW_NONE) {\n\t\t\t/* another llc task is ongoing */\n\t\t\tmutex_unlock(&lgr->llc_conf_mutex);\n\t\t\twait_event_timeout(lgr->llc_flow_waiter,\n\t\t\t\t(list_empty(&lgr->list) ||\n\t\t\t\t lgr->llc_flow_lcl.type == SMC_LLC_FLOW_NONE),\n\t\t\t\tSMC_LLC_WAIT_TIME);\n\t\t\tmutex_lock(&lgr->llc_conf_mutex);\n\t\t}\n\t\tif (!list_empty(&lgr->list)) {\n\t\t\tsmc_llc_send_delete_link(to_lnk, del_link_id,\n\t\t\t\t\t\t SMC_LLC_REQ, true,\n\t\t\t\t\t\t SMC_LLC_DEL_LOST_PATH);\n\t\t\tsmcr_link_clear(lnk, true);\n\t\t}\n\t\twake_up(&lgr->llc_flow_waiter);\t/* wake up next waiter */\n\t}\n}",
        "static int alloc_from_top_down_no_space_above_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n": "static int alloc_from_top_down_no_space_above_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\n\tphys_addr_t r1_size = SZ_64;\n\tphys_addr_t r2_size = SZ_2;\n\tphys_addr_t total_size = r1_size + r2_size;\n\tphys_addr_t min_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2;\n\n\t/* No space above this address */\n\tmemblock_reserve(min_addr, r2_size);\n\n\tallocated_ptr = memblock_alloc_from(r1_size, SMP_CACHE_BYTES, min_addr);\n\n\tassert(allocated_ptr);\n\tassert(rgn->base == min_addr - r1_size);\n\tassert(rgn->size == total_size);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static void vmalloc_helpers_tags(struct kunit *test)\n{\n\tvoid *ptr;\n\n\t/* This test is intended for tag-based modes. */": "static void vmalloc_helpers_tags(struct kunit *test)\n{\n\tvoid *ptr;\n\n\t/* This test is intended for tag-based modes. */\n\tKASAN_TEST_NEEDS_CONFIG_OFF(test, CONFIG_KASAN_GENERIC);\n\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_VMALLOC);\n\n\tptr = vmalloc(PAGE_SIZE);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);\n\n\t/* Check that the returned pointer is tagged. */\n\tKUNIT_EXPECT_GE(test, (u8)get_tag(ptr), (u8)KASAN_TAG_MIN);\n\tKUNIT_EXPECT_LT(test, (u8)get_tag(ptr), (u8)KASAN_TAG_KERNEL);\n\n\t/* Make sure exported vmalloc helpers handle tagged pointers. */\n\tKUNIT_ASSERT_TRUE(test, is_vmalloc_addr(ptr));\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, vmalloc_to_page(ptr));\n\n#if !IS_MODULE(CONFIG_KASAN_KUNIT_TEST)\n\t{\n\t\tint rv;\n\n\t\t/* Make sure vmalloc'ed memory permissions can be changed. */\n\t\trv = set_memory_ro((unsigned long)ptr, 1);\n\t\tKUNIT_ASSERT_GE(test, rv, 0);\n\t\trv = set_memory_rw((unsigned long)ptr, 1);\n\t\tKUNIT_ASSERT_GE(test, rv, 0);\n\t}\n#endif\n\n\tvfree(ptr);\n}",
        "static int dcdbas_probe(struct platform_device *dev)\n{\n\tint error;\n\n\thost_control_action = HC_ACTION_NONE;": "static int dcdbas_probe(struct platform_device *dev)\n{\n\tint error;\n\n\thost_control_action = HC_ACTION_NONE;\n\thost_control_smi_type = HC_SMITYPE_NONE;\n\n\tdcdbas_pdev = dev;\n\n\t/* Check if ACPI WSMT table specifies protected SMI buffer address */\n\terror = dcdbas_check_wsmt();\n\tif (error < 0)\n\t\treturn error;\n\n\t/*\n\t * BIOS SMI calls require buffer addresses be in 32-bit address space.\n\t * This is done by setting the DMA mask below.\n\t */\n\terror = dma_set_coherent_mask(&dcdbas_pdev->dev, DMA_BIT_MASK(32));\n\tif (error)\n\t\treturn error;\n\n\terror = sysfs_create_group(&dev->dev.kobj, &dcdbas_attr_group);\n\tif (error)\n\t\treturn error;\n\n\tregister_reboot_notifier(&dcdbas_reboot_nb);\n\n\tdev_info(&dev->dev, \"%s (version %s)\\n\",\n\t\t DRIVER_DESCRIPTION, DRIVER_VERSION);\n\n\treturn 0;\n}",
        "static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)\n{\n\tu32 omsg_int;\n\tstruct rio_mport *mport = &priv->mport;\n\tvoid *dev_id = NULL;": "static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)\n{\n\tu32 omsg_int;\n\tstruct rio_mport *mport = &priv->mport;\n\tvoid *dev_id = NULL;\n\tu32 tx_slot = 0xffffffff;\n\tint do_callback = 0;\n\n\tspin_lock(&priv->omsg_ring[ch].lock);\n\n\tomsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch));\n\n\tif (omsg_int & TSI721_OBDMAC_INT_ST_FULL)\n\t\ttsi_info(&priv->pdev->dev,\n\t\t\t\"OB MBOX%d: Status FIFO is full\", ch);\n\n\tif (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) {\n\t\tu32 srd_ptr;\n\t\tu64 *sts_ptr, last_ptr = 0, prev_ptr = 0;\n\t\tint i, j;\n\n\t\t/*\n\t\t * Find last successfully processed descriptor\n\t\t */\n\n\t\t/* Check and clear descriptor status FIFO entries */\n\t\tsrd_ptr = priv->omsg_ring[ch].sts_rdptr;\n\t\tsts_ptr = priv->omsg_ring[ch].sts_base;\n\t\tj = srd_ptr * 8;\n\t\twhile (sts_ptr[j]) {\n\t\t\tfor (i = 0; i < 8 && sts_ptr[j]; i++, j++) {\n\t\t\t\tprev_ptr = last_ptr;\n\t\t\t\tlast_ptr = le64_to_cpu(sts_ptr[j]);\n\t\t\t\tsts_ptr[j] = 0;\n\t\t\t}\n\n\t\t\t++srd_ptr;\n\t\t\tsrd_ptr %= priv->omsg_ring[ch].sts_size;\n\t\t\tj = srd_ptr * 8;\n\t\t}\n\n\t\tif (last_ptr == 0)\n\t\t\tgoto no_sts_update;\n\n\t\tpriv->omsg_ring[ch].sts_rdptr = srd_ptr;\n\t\tiowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));\n\n\t\tif (!mport->outb_msg[ch].mcback)\n\t\t\tgoto no_sts_update;\n\n\t\t/* Inform upper layer about transfer completion */\n\n\t\ttx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/\n\t\t\t\t\t\tsizeof(struct tsi721_omsg_desc);\n\n\t\t/*\n\t\t * Check if this is a Link Descriptor (LD).\n\t\t * If yes, ignore LD and use descriptor processed\n\t\t * before LD.\n\t\t */\n\t\tif (tx_slot == priv->omsg_ring[ch].size) {\n\t\t\tif (prev_ptr)\n\t\t\t\ttx_slot = (prev_ptr -\n\t\t\t\t\t(u64)priv->omsg_ring[ch].omd_phys)/\n\t\t\t\t\t\tsizeof(struct tsi721_omsg_desc);\n\t\t\telse\n\t\t\t\tgoto no_sts_update;\n\t\t}\n\n\t\tif (tx_slot >= priv->omsg_ring[ch].size)\n\t\t\ttsi_debug(OMSG, &priv->pdev->dev,\n\t\t\t\t  \"OB_MSG tx_slot=%x > size=%x\",\n\t\t\t\t  tx_slot, priv->omsg_ring[ch].size);\n\t\tWARN_ON(tx_slot >= priv->omsg_ring[ch].size);\n\n\t\t/* Move slot index to the next message to be sent */\n\t\t++tx_slot;\n\t\tif (tx_slot == priv->omsg_ring[ch].size)\n\t\t\ttx_slot = 0;\n\n\t\tdev_id = priv->omsg_ring[ch].dev_id;\n\t\tdo_callback = 1;\n\t}\n\nno_sts_update:\n\n\tif (omsg_int & TSI721_OBDMAC_INT_ERROR) {\n\t\t/*\n\t\t* Outbound message operation aborted due to error,\n\t\t* reinitialize OB MSG channel\n\t\t*/\n\n\t\ttsi_debug(OMSG, &priv->pdev->dev, \"OB MSG ABORT ch_stat=%x\",\n\t\t\t  ioread32(priv->regs + TSI721_OBDMAC_STS(ch)));\n\n\t\tiowrite32(TSI721_OBDMAC_INT_ERROR,\n\t\t\t\tpriv->regs + TSI721_OBDMAC_INT(ch));\n\t\tiowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT,\n\t\t\t\tpriv->regs + TSI721_OBDMAC_CTL(ch));\n\t\tioread32(priv->regs + TSI721_OBDMAC_CTL(ch));\n\n\t\t/* Inform upper level to clear all pending tx slots */\n\t\tdev_id = priv->omsg_ring[ch].dev_id;\n\t\ttx_slot = priv->omsg_ring[ch].tx_slot;\n\t\tdo_callback = 1;\n\n\t\t/* Synch tx_slot tracking */\n\t\tiowrite32(priv->omsg_ring[ch].tx_slot,\n\t\t\tpriv->regs + TSI721_OBDMAC_DRDCNT(ch));\n\t\tioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch));\n\t\tpriv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot;\n\t\tpriv->omsg_ring[ch].sts_rdptr = 0;\n\t}\n\n\t/* Clear channel interrupts */\n\tiowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));\n\n\tif (!(priv->flags & TSI721_USING_MSIX)) {\n\t\tu32 ch_inte;\n\n\t\t/* Re-enable channel interrupts */\n\t\tch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);\n\t\tch_inte |= TSI721_INT_OMSG_CHAN(ch);\n\t\tiowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);\n\t}\n\n\tspin_unlock(&priv->omsg_ring[ch].lock);\n\n\tif (mport->outb_msg[ch].mcback && do_callback)\n\t\tmport->outb_msg[ch].mcback(mport, dev_id, ch, tx_slot);\n}",
        "static void txc_apply_defaults(struct ef4_nic *efx)\n{\n\tint mctrl;\n\n\t/* Turn amplitude down and preemphasis off on the host side": "static void txc_apply_defaults(struct ef4_nic *efx)\n{\n\tint mctrl;\n\n\t/* Turn amplitude down and preemphasis off on the host side\n\t * (PHY<->MAC) as this is believed less likely to upset Falcon\n\t * and no adverse effects have been noted. It probably also\n\t * saves a picowatt or two */\n\n\t/* Turn off preemphasis */\n\tef4_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, TXC_ATXPRE_NONE);\n\tef4_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, TXC_ATXPRE_NONE);\n\n\t/* Turn down the amplitude */\n\tef4_mdio_write(efx, MDIO_MMD_PHYXS,\n\t\t       TXC_ALRGS_ATXAMP0, TXC_ATXAMP_0820_BOTH);\n\tef4_mdio_write(efx, MDIO_MMD_PHYXS,\n\t\t       TXC_ALRGS_ATXAMP1, TXC_ATXAMP_0820_BOTH);\n\n\t/* Set the line side amplitude and preemphasis to the databook\n\t * defaults as an erratum causes them to be 0 on at least some\n\t * PHY rev.s */\n\tef4_mdio_write(efx, MDIO_MMD_PMAPMD,\n\t\t       TXC_ALRGS_ATXPRE0, TXC_ATXPRE_DEFAULT);\n\tef4_mdio_write(efx, MDIO_MMD_PMAPMD,\n\t\t       TXC_ALRGS_ATXPRE1, TXC_ATXPRE_DEFAULT);\n\tef4_mdio_write(efx, MDIO_MMD_PMAPMD,\n\t\t       TXC_ALRGS_ATXAMP0, TXC_ATXAMP_DEFAULT);\n\tef4_mdio_write(efx, MDIO_MMD_PMAPMD,\n\t\t       TXC_ALRGS_ATXAMP1, TXC_ATXAMP_DEFAULT);\n\n\t/* Set up the LEDs  */\n\tmctrl = ef4_mdio_read(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL);\n\n\t/* Set the Green and Red LEDs to their default modes */\n\tmctrl &= ~((1 << TXC_MCTL_TXLED_LBN) | (1 << TXC_MCTL_RXLED_LBN));\n\tef4_mdio_write(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL, mctrl);\n\n\t/* Databook recommends doing this after configuration changes */\n\ttxc_reset_logic(efx);\n\n\tfalcon_board(efx)->type->init_phy(efx);\n}",
        "static int intel_bxtwc_pmic_get_raw_temp(struct regmap *regmap, int reg)\n{\n\tunsigned int val, adc_val, reg_val;\n\tu8 temp_l, temp_h, cursrc;\n\tunsigned long rlsb;": "static int intel_bxtwc_pmic_get_raw_temp(struct regmap *regmap, int reg)\n{\n\tunsigned int val, adc_val, reg_val;\n\tu8 temp_l, temp_h, cursrc;\n\tunsigned long rlsb;\n\tstatic const unsigned long rlsb_array[] = {\n\t\t0, 260420, 130210, 65100, 32550, 16280,\n\t\t8140, 4070, 2030, 0, 260420, 130210 };\n\n\tif (regmap_read(regmap, reg, &val))\n\t\treturn -EIO;\n\ttemp_l = (u8) val;\n\n\tif (regmap_read(regmap, (reg - 1), &val))\n\t\treturn -EIO;\n\ttemp_h = (u8) val;\n\n\treg_val = temp_l | WHISKEY_COVE_ADC_HIGH_BIT(temp_h);\n\tcursrc = WHISKEY_COVE_ADC_CURSRC(temp_h);\n\trlsb = rlsb_array[cursrc];\n\tadc_val = reg_val * rlsb / 1000;\n\n\treturn adc_val;\n}",
        "static void batadv_iv_ogm_schedule_buff(struct batadv_hard_iface *hard_iface)\n{\n\tstruct batadv_priv *bat_priv = netdev_priv(hard_iface->soft_iface);\n\tunsigned char **ogm_buff = &hard_iface->bat_iv.ogm_buff;\n\tstruct batadv_ogm_packet *batadv_ogm_packet;": "static void batadv_iv_ogm_schedule_buff(struct batadv_hard_iface *hard_iface)\n{\n\tstruct batadv_priv *bat_priv = netdev_priv(hard_iface->soft_iface);\n\tunsigned char **ogm_buff = &hard_iface->bat_iv.ogm_buff;\n\tstruct batadv_ogm_packet *batadv_ogm_packet;\n\tstruct batadv_hard_iface *primary_if, *tmp_hard_iface;\n\tint *ogm_buff_len = &hard_iface->bat_iv.ogm_buff_len;\n\tu32 seqno;\n\tu16 tvlv_len = 0;\n\tunsigned long send_time;\n\n\tlockdep_assert_held(&hard_iface->bat_iv.ogm_buff_mutex);\n\n\t/* interface already disabled by batadv_iv_ogm_iface_disable */\n\tif (!*ogm_buff)\n\t\treturn;\n\n\t/* the interface gets activated here to avoid race conditions between\n\t * the moment of activating the interface in\n\t * hardif_activate_interface() where the originator mac is set and\n\t * outdated packets (especially uninitialized mac addresses) in the\n\t * packet queue\n\t */\n\tif (hard_iface->if_status == BATADV_IF_TO_BE_ACTIVATED)\n\t\thard_iface->if_status = BATADV_IF_ACTIVE;\n\n\tprimary_if = batadv_primary_if_get_selected(bat_priv);\n\n\tif (hard_iface == primary_if) {\n\t\t/* tt changes have to be committed before the tvlv data is\n\t\t * appended as it may alter the tt tvlv container\n\t\t */\n\t\tbatadv_tt_local_commit_changes(bat_priv);\n\t\ttvlv_len = batadv_tvlv_container_ogm_append(bat_priv, ogm_buff,\n\t\t\t\t\t\t\t    ogm_buff_len,\n\t\t\t\t\t\t\t    BATADV_OGM_HLEN);\n\t}\n\n\tbatadv_ogm_packet = (struct batadv_ogm_packet *)(*ogm_buff);\n\tbatadv_ogm_packet->tvlv_len = htons(tvlv_len);\n\n\t/* change sequence number to network order */\n\tseqno = (u32)atomic_read(&hard_iface->bat_iv.ogm_seqno);\n\tbatadv_ogm_packet->seqno = htonl(seqno);\n\tatomic_inc(&hard_iface->bat_iv.ogm_seqno);\n\n\tbatadv_iv_ogm_slide_own_bcast_window(hard_iface);\n\n\tsend_time = batadv_iv_ogm_emit_send_time(bat_priv);\n\n\tif (hard_iface != primary_if) {\n\t\t/* OGMs from secondary interfaces are only scheduled on their\n\t\t * respective interfaces.\n\t\t */\n\t\tbatadv_iv_ogm_queue_add(bat_priv, *ogm_buff, *ogm_buff_len,\n\t\t\t\t\thard_iface, hard_iface, 1, send_time);\n\t\tgoto out;\n\t}\n\n\t/* OGMs from primary interfaces are scheduled on all\n\t * interfaces.\n\t */\n\trcu_read_lock();\n\tlist_for_each_entry_rcu(tmp_hard_iface, &batadv_hardif_list, list) {\n\t\tif (tmp_hard_iface->soft_iface != hard_iface->soft_iface)\n\t\t\tcontinue;\n\n\t\tif (!kref_get_unless_zero(&tmp_hard_iface->refcount))\n\t\t\tcontinue;\n\n\t\tbatadv_iv_ogm_queue_add(bat_priv, *ogm_buff,\n\t\t\t\t\t*ogm_buff_len, hard_iface,\n\t\t\t\t\ttmp_hard_iface, 1, send_time);\n\n\t\tbatadv_hardif_put(tmp_hard_iface);\n\t}\n\trcu_read_unlock();\n\nout:\n\tbatadv_hardif_put(primary_if);\n}",
        "static int anfc_select_target(struct nand_chip *chip, int target)\n{\n\tstruct anand *anand = to_anand(chip);\n\tstruct arasan_nfc *nfc = to_anfc(chip->controller);\n\tunsigned int nfc_cs_idx = anfc_relative_to_absolute_cs(anand, target);": "static int anfc_select_target(struct nand_chip *chip, int target)\n{\n\tstruct anand *anand = to_anand(chip);\n\tstruct arasan_nfc *nfc = to_anfc(chip->controller);\n\tunsigned int nfc_cs_idx = anfc_relative_to_absolute_cs(anand, target);\n\tint ret;\n\n\tanfc_assert_cs(nfc, nfc_cs_idx);\n\n\t/* Update the controller timings and the potential ECC configuration */\n\twritel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);\n\twritel_relaxed(anand->timings, nfc->base + TIMING_REG);\n\n\t/* Update clock frequency */\n\tif (nfc->cur_clk != anand->clk) {\n\t\tclk_disable_unprepare(nfc->controller_clk);\n\t\tret = clk_set_rate(nfc->controller_clk, anand->clk);\n\t\tif (ret) {\n\t\t\tdev_err(nfc->dev, \"Failed to change clock rate\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tret = clk_prepare_enable(nfc->controller_clk);\n\t\tif (ret) {\n\t\t\tdev_err(nfc->dev,\n\t\t\t\t\"Failed to re-enable the controller clock\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tnfc->cur_clk = anand->clk;\n\t}\n\n\treturn 0;\n}",
        "static int suspend_test_thread(void *arg)\n{\n\tint cpu = (long)arg;\n\tint i, nb_suspend = 0, nb_shallow_sleep = 0, nb_err = 0;\n\tstruct cpuidle_device *dev;": "static int suspend_test_thread(void *arg)\n{\n\tint cpu = (long)arg;\n\tint i, nb_suspend = 0, nb_shallow_sleep = 0, nb_err = 0;\n\tstruct cpuidle_device *dev;\n\tstruct cpuidle_driver *drv;\n\t/* No need for an actual callback, we just want to wake up the CPU. */\n\tstruct timer_list wakeup_timer;\n\n\t/* Wait for the main thread to give the start signal. */\n\twait_for_completion(&suspend_threads_started);\n\n\t/* Set maximum priority to preempt all other threads on this CPU. */\n\tsched_set_fifo(current);\n\n\tdev = this_cpu_read(cpuidle_devices);\n\tdrv = cpuidle_get_cpu_driver(dev);\n\n\tpr_info(\"CPU %d entering suspend cycles, states 1 through %d\\n\",\n\t\tcpu, drv->state_count - 1);\n\n\ttimer_setup_on_stack(&wakeup_timer, dummy_callback, 0);\n\tfor (i = 0; i < NUM_SUSPEND_CYCLE; ++i) {\n\t\tint index;\n\t\t/*\n\t\t * Test all possible states, except 0 (which is usually WFI and\n\t\t * doesn't use PSCI).\n\t\t */\n\t\tfor (index = 1; index < drv->state_count; ++index) {\n\t\t\tint ret;\n\t\t\tstruct cpuidle_state *state = &drv->states[index];\n\n\t\t\t/*\n\t\t\t * Set the timer to wake this CPU up in some time (which\n\t\t\t * should be largely sufficient for entering suspend).\n\t\t\t * If the local tick is disabled when entering suspend,\n\t\t\t * suspend_cpu() takes care of switching to a broadcast\n\t\t\t * tick, so the timer will still wake us up.\n\t\t\t */\n\t\t\tmod_timer(&wakeup_timer, jiffies +\n\t\t\t\t  usecs_to_jiffies(state->target_residency));\n\n\t\t\t/* IRQs must be disabled during suspend operations. */\n\t\t\tlocal_irq_disable();\n\n\t\t\tret = suspend_cpu(dev, drv, index);\n\n\t\t\t/*\n\t\t\t * We have woken up. Re-enable IRQs to handle any\n\t\t\t * pending interrupt, do not wait until the end of the\n\t\t\t * loop.\n\t\t\t */\n\t\t\tlocal_irq_enable();\n\n\t\t\tif (ret == index) {\n\t\t\t\t++nb_suspend;\n\t\t\t} else if (ret >= 0) {\n\t\t\t\t/* We did not enter the expected state. */\n\t\t\t\t++nb_shallow_sleep;\n\t\t\t} else {\n\t\t\t\tpr_err(\"Failed to suspend CPU %d: error %d \"\n\t\t\t\t       \"(requested state %d, cycle %d)\\n\",\n\t\t\t\t       cpu, ret, index, i);\n\t\t\t\t++nb_err;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\n\t * Disable the timer to make sure that the timer will not trigger\n\t * later.\n\t */\n\tdel_timer(&wakeup_timer);\n\tdestroy_timer_on_stack(&wakeup_timer);\n\n\tif (atomic_dec_return_relaxed(&nb_active_threads) == 0)\n\t\tcomplete(&suspend_threads_done);\n\n\tfor (;;) {\n\t\t/* Needs to be set first to avoid missing a wakeup. */\n\t\tset_current_state(TASK_INTERRUPTIBLE);\n\t\tif (kthread_should_park())\n\t\t\tbreak;\n\t\tschedule();\n\t}\n\n\tpr_info(\"CPU %d suspend test results: success %d, shallow states %d, errors %d\\n\",\n\t\tcpu, nb_suspend, nb_shallow_sleep, nb_err);\n\n\tkthread_parkme();\n\n\treturn nb_err;\n}",
        "static void hw_failure_emergency_poweroff_func(struct work_struct *work)\n{\n\tprintk_prefer_direct_enter();\n\n\t/*": "static void hw_failure_emergency_poweroff_func(struct work_struct *work)\n{\n\tprintk_prefer_direct_enter();\n\n\t/*\n\t * We have reached here after the emergency shutdown waiting period has\n\t * expired. This means orderly_poweroff has not been able to shut off\n\t * the system for some reason.\n\t *\n\t * Try to shut down the system immediately using kernel_power_off\n\t * if populated\n\t */\n\tpr_emerg(\"Hardware protection timed-out. Trying forced poweroff\\n\");\n\tkernel_power_off();\n\n\t/*\n\t * Worst of the worst case trigger emergency restart\n\t */\n\tpr_emerg(\"Hardware protection shutdown failed. Trying emergency restart\\n\");\n\temergency_restart();\n\n\tprintk_prefer_direct_exit();\n}",
        "static int pfkey_process(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr)\n{\n\tvoid *ext_hdrs[SADB_EXT_MAX];\n\tint err;\n": "static int pfkey_process(struct sock *sk, struct sk_buff *skb, const struct sadb_msg *hdr)\n{\n\tvoid *ext_hdrs[SADB_EXT_MAX];\n\tint err;\n\n\t/* Non-zero return value of pfkey_broadcast() does not always signal\n\t * an error and even on an actual error we may still want to process\n\t * the message so rather ignore the return value.\n\t */\n\tpfkey_broadcast(skb_clone(skb, GFP_KERNEL), GFP_KERNEL,\n\t\t\tBROADCAST_PROMISC_ONLY, NULL, sock_net(sk));\n\n\tmemset(ext_hdrs, 0, sizeof(ext_hdrs));\n\terr = parse_exthdrs(skb, hdr, ext_hdrs);\n\tif (!err) {\n\t\terr = -EOPNOTSUPP;\n\t\tif (pfkey_funcs[hdr->sadb_msg_type])\n\t\t\terr = pfkey_funcs[hdr->sadb_msg_type](sk, skb, hdr, ext_hdrs);\n\t}\n\treturn err;\n}",
        "static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tstruct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;": "static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct bnx2x *bp = netdev_priv(dev->netdev);\n\tstruct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;\n\tint hq_bds, pages;\n\tu32 pfid = bp->pfid;\n\n\tcp->num_iscsi_tasks = req1->num_tasks_per_conn;\n\tcp->num_ccells = req1->num_ccells_per_conn;\n\tcp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *\n\t\t\t      cp->num_iscsi_tasks;\n\tcp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *\n\t\t\tBNX2X_ISCSI_R2TQE_SIZE;\n\tcp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;\n\tpages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;\n\thq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);\n\tcp->num_cqs = req1->num_cqs;\n\n\tif (!dev->max_iscsi_conn)\n\t\treturn 0;\n\n\t/* init Tstorm RAM */\n\tCNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),\n\t\t  req1->rq_num_wqes);\n\tCNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),\n\t\t  CNIC_PAGE_SIZE);\n\tCNIC_WR8(dev, BAR_TSTRORM_INTMEM +\n\t\t TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);\n\tCNIC_WR16(dev, BAR_TSTRORM_INTMEM +\n\t\t  TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),\n\t\t  req1->num_tasks_per_conn);\n\n\t/* init Ustorm RAM */\n\tCNIC_WR16(dev, BAR_USTRORM_INTMEM +\n\t\t  USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),\n\t\t  req1->rq_buffer_size);\n\tCNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),\n\t\t  CNIC_PAGE_SIZE);\n\tCNIC_WR8(dev, BAR_USTRORM_INTMEM +\n\t\t USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);\n\tCNIC_WR16(dev, BAR_USTRORM_INTMEM +\n\t\t  USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),\n\t\t  req1->num_tasks_per_conn);\n\tCNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),\n\t\t  req1->rq_num_wqes);\n\tCNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),\n\t\t  req1->cq_num_wqes);\n\tCNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),\n\t\t  cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);\n\n\t/* init Xstorm RAM */\n\tCNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),\n\t\t  CNIC_PAGE_SIZE);\n\tCNIC_WR8(dev, BAR_XSTRORM_INTMEM +\n\t\t XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);\n\tCNIC_WR16(dev, BAR_XSTRORM_INTMEM +\n\t\t  XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),\n\t\t  req1->num_tasks_per_conn);\n\tCNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),\n\t\t  hq_bds);\n\tCNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),\n\t\t  req1->num_tasks_per_conn);\n\tCNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),\n\t\t  cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);\n\n\t/* init Cstorm RAM */\n\tCNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),\n\t\t  CNIC_PAGE_SIZE);\n\tCNIC_WR8(dev, BAR_CSTRORM_INTMEM +\n\t\t CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);\n\tCNIC_WR16(dev, BAR_CSTRORM_INTMEM +\n\t\t  CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),\n\t\t  req1->num_tasks_per_conn);\n\tCNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),\n\t\t  req1->cq_num_wqes);\n\tCNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),\n\t\t  hq_bds);\n\n\tcnic_bnx2x_set_tcp_options(dev,\n\t\t\treq1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,\n\t\t\treq1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);\n\n\treturn 0;\n}",
        "static int cadence_nand_read_bbm(struct nand_chip *chip, int page, u8 *buf)\n{\n\tint status;\n\tstruct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);\n\tstruct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);": "static int cadence_nand_read_bbm(struct nand_chip *chip, int page, u8 *buf)\n{\n\tint status;\n\tstruct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);\n\tstruct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);\n\tstruct mtd_info *mtd = nand_to_mtd(chip);\n\n\tcadence_nand_prepare_data_size(chip, TT_BBM);\n\n\tcadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);\n\n\t/*\n\t * Read only bad block marker from offset\n\t * defined by a memory manufacturer.\n\t */\n\tstatus = cadence_nand_cdma_transfer(cdns_ctrl,\n\t\t\t\t\t    cdns_chip->cs[chip->cur_cs],\n\t\t\t\t\t    page, cdns_ctrl->buf, NULL,\n\t\t\t\t\t    mtd->oobsize,\n\t\t\t\t\t    0, DMA_FROM_DEVICE, false);\n\tif (status) {\n\t\tdev_err(cdns_ctrl->dev, \"read BBM failed\\n\");\n\t\treturn -EIO;\n\t}\n\n\tmemcpy(buf + cdns_chip->bbm_offs, cdns_ctrl->buf, cdns_chip->bbm_len);\n\n\treturn 0;\n}",
        "static void wq_netinfo(struct work_struct *wq_obj)\n{\n\tstruct most_dev *mdev = to_mdev_from_work(wq_obj);\n\tstruct usb_device *usb_device = mdev->usb_device;\n\tstruct device *dev = &usb_device->dev;": "static void wq_netinfo(struct work_struct *wq_obj)\n{\n\tstruct most_dev *mdev = to_mdev_from_work(wq_obj);\n\tstruct usb_device *usb_device = mdev->usb_device;\n\tstruct device *dev = &usb_device->dev;\n\tu16 hi, mi, lo, link;\n\tu8 hw_addr[6];\n\n\tif (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_HI, &hi)) {\n\t\tdev_err(dev, \"Vendor request 'hw_addr_hi' failed\\n\");\n\t\treturn;\n\t}\n\n\tif (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_MI, &mi)) {\n\t\tdev_err(dev, \"Vendor request 'hw_addr_mid' failed\\n\");\n\t\treturn;\n\t}\n\n\tif (drci_rd_reg(usb_device, DRCI_REG_HW_ADDR_LO, &lo)) {\n\t\tdev_err(dev, \"Vendor request 'hw_addr_low' failed\\n\");\n\t\treturn;\n\t}\n\n\tif (drci_rd_reg(usb_device, DRCI_REG_NI_STATE, &link)) {\n\t\tdev_err(dev, \"Vendor request 'link status' failed\\n\");\n\t\treturn;\n\t}\n\n\thw_addr[0] = hi >> 8;\n\thw_addr[1] = hi;\n\thw_addr[2] = mi >> 8;\n\thw_addr[3] = mi;\n\thw_addr[4] = lo >> 8;\n\thw_addr[5] = lo;\n\n\tif (mdev->on_netinfo)\n\t\tmdev->on_netinfo(&mdev->iface, link, hw_addr);\n}",
        "static int mse102x_rx_cmd_spi(struct mse102x_net *mse, u8 *rxb)\n{\n\tstruct mse102x_net_spi *mses = to_mse102x_spi(mse);\n\tstruct spi_transfer *xfer = &mses->spi_xfer;\n\tstruct spi_message *msg = &mses->spi_msg;": "static int mse102x_rx_cmd_spi(struct mse102x_net *mse, u8 *rxb)\n{\n\tstruct mse102x_net_spi *mses = to_mse102x_spi(mse);\n\tstruct spi_transfer *xfer = &mses->spi_xfer;\n\tstruct spi_message *msg = &mses->spi_msg;\n\t__be16 *txb = (__be16 *)mse->txd;\n\t__be16 *cmd = (__be16 *)mse->rxd;\n\tu8 *trx = mse->rxd;\n\tint ret;\n\n\ttxb[0] = 0;\n\ttxb[1] = 0;\n\n\txfer->tx_buf = txb;\n\txfer->rx_buf = trx;\n\txfer->len = DET_CMD_LEN;\n\n\tret = spi_sync(mses->spidev, msg);\n\tif (ret < 0) {\n\t\tnetdev_err(mse->ndev, \"%s: spi_sync() failed: %d\\n\",\n\t\t\t   __func__, ret);\n\t\tmse->stats.xfer_err++;\n\t} else if (*cmd != cpu_to_be16(DET_CMD)) {\n\t\tnet_dbg_ratelimited(\"%s: Unexpected response (0x%04x)\\n\",\n\t\t\t\t    __func__, *cmd);\n\t\tmse->stats.invalid_cmd++;\n\t\tret = -EIO;\n\t} else {\n\t\tmemcpy(rxb, trx + 2, 2);\n\t}\n\n\treturn ret;\n}",
        "static inline void ftm_irq_acknowledge(struct ftm_rtc *rtc)\n{\n\tunsigned int timeout = 100;\n\n\t/*": "static inline void ftm_irq_acknowledge(struct ftm_rtc *rtc)\n{\n\tunsigned int timeout = 100;\n\n\t/*\n\t *Fix errata A-007728 for flextimer\n\t *\tIf the FTM counter reaches the FTM_MOD value between\n\t *\tthe reading of the TOF bit and the writing of 0 to\n\t *\tthe TOF bit, the process of clearing the TOF bit\n\t *\tdoes not work as expected when FTMx_CONF[NUMTOF] != 0\n\t *\tand the current TOF count is less than FTMx_CONF[NUMTOF].\n\t *\tIf the above condition is met, the TOF bit remains set.\n\t *\tIf the TOF interrupt is enabled (FTMx_SC[TOIE] = 1),the\n\t *\tTOF interrupt also remains asserted.\n\t *\n\t *\tAbove is the errata discription\n\t *\n\t *\tIn one word: software clearing TOF bit not works when\n\t *\tFTMx_CONF[NUMTOF] was seted as nonzero and FTM counter\n\t *\treaches the FTM_MOD value.\n\t *\n\t *\tThe workaround is clearing TOF bit until it works\n\t *\t(FTM counter doesn't always reache the FTM_MOD anyway),\n\t *\twhich may cost some cycles.\n\t */\n\twhile ((FTM_SC_TOF & rtc_readl(rtc, FTM_SC)) && timeout--)\n\t\trtc_writel(rtc, FTM_SC, rtc_readl(rtc, FTM_SC) & (~FTM_SC_TOF));\n}",
        "static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)\n{\n\tunsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */\n\tunsigned long flags;\n\tint n_pending;": "static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)\n{\n\tunsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */\n\tunsigned long flags;\n\tint n_pending;\n\tint i;\n\n\tspin_lock_irqsave (&hmidi->lock, flags);\n\tn_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);\n\tif (n_pending > 0) {\n\t\tif (hmidi->input) {\n\t\t\tif (n_pending > (int)sizeof (buf))\n\t\t\t\tn_pending = sizeof (buf);\n\t\t\tfor (i = 0; i < n_pending; ++i)\n\t\t\t\tbuf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);\n\t\t\tif (n_pending)\n\t\t\t\tsnd_rawmidi_receive (hmidi->input, buf, n_pending);\n\t\t} else {\n\t\t\t/* flush the MIDI input FIFO */\n\t\t\twhile (--n_pending)\n\t\t\t\tsnd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);\n\t\t}\n\t}\n\thmidi->pending = 0;\n\tif (hmidi->id)\n\t\thmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;\n\telse\n\t\thmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;\n\thdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);\n\tspin_unlock_irqrestore (&hmidi->lock, flags);\n\treturn snd_hdsp_midi_output_write (hmidi);\n}",
        "static void wnd_remove_free_ext(struct wnd_bitmap *wnd, size_t bit, size_t len)\n{\n\tstruct rb_node *n, *n3;\n\tstruct e_node *e, *e3;\n\tsize_t end_in = bit + len;": "static void wnd_remove_free_ext(struct wnd_bitmap *wnd, size_t bit, size_t len)\n{\n\tstruct rb_node *n, *n3;\n\tstruct e_node *e, *e3;\n\tsize_t end_in = bit + len;\n\tsize_t end3, end, new_key, new_len, max_new_len;\n\n\t/* Try to find extent before 'bit'. */\n\tn = rb_lookup(&wnd->start_tree, bit);\n\n\tif (!n)\n\t\treturn;\n\n\te = rb_entry(n, struct e_node, start.node);\n\tend = e->start.key + e->count.key;\n\n\tnew_key = new_len = 0;\n\tlen = e->count.key;\n\n\t/* Range [bit,end_in) must be inside 'e' or outside 'e' and 'n'. */\n\tif (e->start.key > bit)\n\t\t;\n\telse if (end_in <= end) {\n\t\t/* Range [bit,end_in) inside 'e'. */\n\t\tnew_key = end_in;\n\t\tnew_len = end - end_in;\n\t\tlen = bit - e->start.key;\n\t} else if (bit > end) {\n\t\tbool bmax = false;\n\n\t\tn3 = rb_next(n);\n\n\t\twhile (n3) {\n\t\t\te3 = rb_entry(n3, struct e_node, start.node);\n\t\t\tif (e3->start.key >= end_in)\n\t\t\t\tbreak;\n\n\t\t\tif (e3->count.key == wnd->extent_max)\n\t\t\t\tbmax = true;\n\n\t\t\tend3 = e3->start.key + e3->count.key;\n\t\t\tif (end3 > end_in) {\n\t\t\t\te3->start.key = end_in;\n\t\t\t\trb_erase(&e3->count.node, &wnd->count_tree);\n\t\t\t\te3->count.key = end3 - end_in;\n\t\t\t\trb_insert_count(&wnd->count_tree, e3);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tn3 = rb_next(n3);\n\t\t\trb_erase(&e3->start.node, &wnd->start_tree);\n\t\t\trb_erase(&e3->count.node, &wnd->count_tree);\n\t\t\twnd->count -= 1;\n\t\t\tkmem_cache_free(ntfs_enode_cachep, e3);\n\t\t}\n\t\tif (!bmax)\n\t\t\treturn;\n\t\tn3 = rb_first(&wnd->count_tree);\n\t\twnd->extent_max =\n\t\t\tn3 ? rb_entry(n3, struct e_node, count.node)->count.key\n\t\t\t   : 0;\n\t\treturn;\n\t}\n\n\tif (e->count.key != wnd->extent_max) {\n\t\t;\n\t} else if (rb_prev(&e->count.node)) {\n\t\t;\n\t} else {\n\t\tn3 = rb_next(&e->count.node);\n\t\tmax_new_len = max(len, new_len);\n\t\tif (!n3) {\n\t\t\twnd->extent_max = max_new_len;\n\t\t} else {\n\t\t\te3 = rb_entry(n3, struct e_node, count.node);\n\t\t\twnd->extent_max = max(e3->count.key, max_new_len);\n\t\t}\n\t}\n\n\tif (!len) {\n\t\tif (new_len) {\n\t\t\te->start.key = new_key;\n\t\t\trb_erase(&e->count.node, &wnd->count_tree);\n\t\t\te->count.key = new_len;\n\t\t\trb_insert_count(&wnd->count_tree, e);\n\t\t} else {\n\t\t\trb_erase(&e->start.node, &wnd->start_tree);\n\t\t\trb_erase(&e->count.node, &wnd->count_tree);\n\t\t\twnd->count -= 1;\n\t\t\tkmem_cache_free(ntfs_enode_cachep, e);\n\t\t}\n\t\tgoto out;\n\t}\n\trb_erase(&e->count.node, &wnd->count_tree);\n\te->count.key = len;\n\trb_insert_count(&wnd->count_tree, e);\n\n\tif (!new_len)\n\t\tgoto out;\n\n\tif (wnd->count >= NTFS_MAX_WND_EXTENTS) {\n\t\twnd->uptodated = -1;\n\n\t\t/* Get minimal extent. */\n\t\te = rb_entry(rb_last(&wnd->count_tree), struct e_node,\n\t\t\t     count.node);\n\t\tif (e->count.key > new_len)\n\t\t\tgoto out;\n\n\t\t/* Replace minimum. */\n\t\trb_erase(&e->start.node, &wnd->start_tree);\n\t\trb_erase(&e->count.node, &wnd->count_tree);\n\t\twnd->count -= 1;\n\t} else {\n\t\te = kmem_cache_alloc(ntfs_enode_cachep, GFP_ATOMIC);\n\t\tif (!e)\n\t\t\twnd->uptodated = -1;\n\t}\n\n\tif (e) {\n\t\te->start.key = new_key;\n\t\te->count.key = new_len;\n\t\trb_insert_start(&wnd->start_tree, e);\n\t\trb_insert_count(&wnd->count_tree, e);\n\t\twnd->count += 1;\n\t}\n\nout:\n\tif (!wnd->count && 1 != wnd->uptodated)\n\t\twnd_rescan(wnd);\n}",
        "static int ice_pf_reset(struct ice_hw *hw)\n{\n\tu32 cnt, reg;\n\n\t/* If at function entry a global reset was already in progress, i.e.": "static int ice_pf_reset(struct ice_hw *hw)\n{\n\tu32 cnt, reg;\n\n\t/* If at function entry a global reset was already in progress, i.e.\n\t * state is not 'device active' or any of the reset done bits are not\n\t * set in GLNVM_ULD, there is no need for a PF Reset; poll until the\n\t * global reset is done.\n\t */\n\tif ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||\n\t    (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {\n\t\t/* poll on global reset currently in progress until done */\n\t\tif (ice_check_reset(hw))\n\t\t\treturn -EIO;\n\n\t\treturn 0;\n\t}\n\n\t/* Reset the PF */\n\treg = rd32(hw, PFGEN_CTRL);\n\n\twr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));\n\n\t/* Wait for the PFR to complete. The wait time is the global config lock\n\t * timeout plus the PFR timeout which will account for a possible reset\n\t * that is occurring during a download package operation.\n\t */\n\tfor (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +\n\t     ICE_PF_RESET_WAIT_COUNT; cnt++) {\n\t\treg = rd32(hw, PFGEN_CTRL);\n\t\tif (!(reg & PFGEN_CTRL_PFSWR_M))\n\t\t\tbreak;\n\n\t\tmdelay(1);\n\t}\n\n\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n\t\tice_debug(hw, ICE_DBG_INIT, \"PF reset polling failed to complete.\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}",
        "static void hist_unreg_all(struct trace_event_file *file)\n{\n\tstruct event_trigger_data *test, *n;\n\tstruct hist_trigger_data *hist_data;\n\tstruct synth_event *se;": "static void hist_unreg_all(struct trace_event_file *file)\n{\n\tstruct event_trigger_data *test, *n;\n\tstruct hist_trigger_data *hist_data;\n\tstruct synth_event *se;\n\tconst char *se_name;\n\n\tlockdep_assert_held(&event_mutex);\n\n\tif (hist_file_check_refs(file))\n\t\treturn;\n\n\tlist_for_each_entry_safe(test, n, &file->triggers, list) {\n\t\tif (test->cmd_ops->trigger_type == ETT_EVENT_HIST) {\n\t\t\thist_data = test->private_data;\n\t\t\tlist_del_rcu(&test->list);\n\t\t\ttrace_event_trigger_enable_disable(file, 0);\n\n\t\t\tse_name = trace_event_name(file->event_call);\n\t\t\tse = find_synth_event(se_name);\n\t\t\tif (se)\n\t\t\t\tse->ref--;\n\n\t\t\tupdate_cond_flag(file);\n\t\t\tif (hist_data->enable_timestamps)\n\t\t\t\ttracing_set_filter_buffering(file->tr, false);\n\t\t\tif (test->ops->free)\n\t\t\t\ttest->ops->free(test);\n\t\t}\n\t}\n}",
        "static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)\n{\n\tu16 mode_reg, bp_index;\n\tu32 length, i, num;\n\t__le16 *data;": "static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)\n{\n\tu16 mode_reg, bp_index;\n\tu32 length, i, num;\n\t__le16 *data;\n\n\trtl_reset_ocp_base(tp);\n\n\tmode_reg = __le16_to_cpu(phy->mode_reg);\n\tsram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));\n\tsram_write(tp, __le16_to_cpu(phy->ba_reg),\n\t\t   __le16_to_cpu(phy->ba_data));\n\n\tlength = __le32_to_cpu(phy->blk_hdr.length);\n\tlength -= __le16_to_cpu(phy->fw_offset);\n\tnum = length / 2;\n\tdata = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));\n\n\tocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));\n\tfor (i = 0; i < num; i++)\n\t\tocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));\n\n\tsram_write(tp, __le16_to_cpu(phy->patch_en_addr),\n\t\t   __le16_to_cpu(phy->patch_en_value));\n\n\tbp_index = __le16_to_cpu(phy->bp_start);\n\tnum = __le16_to_cpu(phy->bp_num);\n\tfor (i = 0; i < num; i++) {\n\t\tsram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));\n\t\tbp_index += 2;\n\t}\n\n\tsram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));\n\n\tdev_dbg(&tp->intf->dev, \"successfully applied %s\\n\", phy->info);\n}",
        "static int check_child_file_mapping(int mem_type, int mode, int mapping)\n{\n\tchar *ptr, *map_ptr;\n\tint run, fd, map_size, result = KSFT_PASS;\n\tint total = ARRAY_SIZE(sizes);": "static int check_child_file_mapping(int mem_type, int mode, int mapping)\n{\n\tchar *ptr, *map_ptr;\n\tint run, fd, map_size, result = KSFT_PASS;\n\tint total = ARRAY_SIZE(sizes);\n\n\tmte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG);\n\tfor (run = 0; run < total; run++) {\n\t\tfd = create_temp_file();\n\t\tif (fd == -1)\n\t\t\treturn KSFT_FAIL;\n\n\t\tmap_size = sizes[run] + OVERFLOW + UNDERFLOW;\n\t\tmap_ptr = (char *)mte_allocate_file_memory(map_size, mem_type, mapping, false, fd);\n\t\tif (check_allocated_memory(map_ptr, map_size, mem_type, false) != KSFT_PASS) {\n\t\t\tclose(fd);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tptr = map_ptr + UNDERFLOW;\n\t\tmte_initialize_current_context(mode, (uintptr_t)ptr, sizes[run]);\n\t\t/* Only mte enabled memory will allow tag insertion */\n\t\tptr = mte_insert_tags((void *)ptr, sizes[run]);\n\t\tif (!ptr || cur_mte_cxt.fault_valid == true) {\n\t\t\tksft_print_msg(\"FAIL: Insert tags on file based memory\\n\");\n\t\t\tmunmap((void *)map_ptr, map_size);\n\t\t\tclose(fd);\n\t\t\treturn KSFT_FAIL;\n\t\t}\n\t\tresult = check_child_tag_inheritance(ptr, sizes[run], mode);\n\t\tmte_clear_tags((void *)ptr, sizes[run]);\n\t\tmunmap((void *)map_ptr, map_size);\n\t\tclose(fd);\n\t\tif (result != KSFT_PASS)\n\t\t\treturn KSFT_FAIL;\n\t}\n\treturn KSFT_PASS;\n}",
        "static void task_non_contending(struct task_struct *p)\n{\n\tstruct sched_dl_entity *dl_se = &p->dl;\n\tstruct hrtimer *timer = &dl_se->inactive_timer;\n\tstruct dl_rq *dl_rq = dl_rq_of_se(dl_se);": "static void task_non_contending(struct task_struct *p)\n{\n\tstruct sched_dl_entity *dl_se = &p->dl;\n\tstruct hrtimer *timer = &dl_se->inactive_timer;\n\tstruct dl_rq *dl_rq = dl_rq_of_se(dl_se);\n\tstruct rq *rq = rq_of_dl_rq(dl_rq);\n\ts64 zerolag_time;\n\n\t/*\n\t * If this is a non-deadline task that has been boosted,\n\t * do nothing\n\t */\n\tif (dl_se->dl_runtime == 0)\n\t\treturn;\n\n\tif (dl_entity_is_special(dl_se))\n\t\treturn;\n\n\tWARN_ON(dl_se->dl_non_contending);\n\n\tzerolag_time = dl_se->deadline -\n\t\t div64_long((dl_se->runtime * dl_se->dl_period),\n\t\t\tdl_se->dl_runtime);\n\n\t/*\n\t * Using relative times instead of the absolute \"0-lag time\"\n\t * allows to simplify the code\n\t */\n\tzerolag_time -= rq_clock(rq);\n\n\t/*\n\t * If the \"0-lag time\" already passed, decrease the active\n\t * utilization now, instead of starting a timer\n\t */\n\tif ((zerolag_time < 0) || hrtimer_active(&dl_se->inactive_timer)) {\n\t\tif (dl_task(p))\n\t\t\tsub_running_bw(dl_se, dl_rq);\n\t\tif (!dl_task(p) || READ_ONCE(p->__state) == TASK_DEAD) {\n\t\t\tstruct dl_bw *dl_b = dl_bw_of(task_cpu(p));\n\n\t\t\tif (READ_ONCE(p->__state) == TASK_DEAD)\n\t\t\t\tsub_rq_bw(&p->dl, &rq->dl);\n\t\t\traw_spin_lock(&dl_b->lock);\n\t\t\t__dl_sub(dl_b, p->dl.dl_bw, dl_bw_cpus(task_cpu(p)));\n\t\t\t__dl_clear_params(p);\n\t\t\traw_spin_unlock(&dl_b->lock);\n\t\t}\n\n\t\treturn;\n\t}\n\n\tdl_se->dl_non_contending = 1;\n\tget_task_struct(p);\n\thrtimer_start(timer, ns_to_ktime(zerolag_time), HRTIMER_MODE_REL_HARD);\n}",
        "static void sugov_work(struct kthread_work *work)\n{\n\tstruct sugov_policy *sg_policy = container_of(work, struct sugov_policy, work);\n\tunsigned int freq;\n\tunsigned long flags;": "static void sugov_work(struct kthread_work *work)\n{\n\tstruct sugov_policy *sg_policy = container_of(work, struct sugov_policy, work);\n\tunsigned int freq;\n\tunsigned long flags;\n\n\t/*\n\t * Hold sg_policy->update_lock shortly to handle the case where:\n\t * in case sg_policy->next_freq is read here, and then updated by\n\t * sugov_deferred_update() just before work_in_progress is set to false\n\t * here, we may miss queueing the new update.\n\t *\n\t * Note: If a work was queued after the update_lock is released,\n\t * sugov_work() will just be called again by kthread_work code; and the\n\t * request will be proceed before the sugov thread sleeps.\n\t */\n\traw_spin_lock_irqsave(&sg_policy->update_lock, flags);\n\tfreq = sg_policy->next_freq;\n\tsg_policy->work_in_progress = false;\n\traw_spin_unlock_irqrestore(&sg_policy->update_lock, flags);\n\n\tmutex_lock(&sg_policy->work_lock);\n\t__cpufreq_driver_target(sg_policy->policy, freq, CPUFREQ_RELATION_L);\n\tmutex_unlock(&sg_policy->work_lock);\n}",
        "static void smc_close_passive_abort_received(struct smc_sock *smc)\n{\n\tstruct smc_cdc_conn_state_flags *txflags =\n\t\t&smc->conn.local_tx_ctrl.conn_state_flags;\n\tstruct sock *sk = &smc->sk;": "static void smc_close_passive_abort_received(struct smc_sock *smc)\n{\n\tstruct smc_cdc_conn_state_flags *txflags =\n\t\t&smc->conn.local_tx_ctrl.conn_state_flags;\n\tstruct sock *sk = &smc->sk;\n\n\tswitch (sk->sk_state) {\n\tcase SMC_INIT:\n\tcase SMC_ACTIVE:\n\tcase SMC_APPCLOSEWAIT1:\n\t\tsk->sk_state = SMC_PROCESSABORT;\n\t\tsock_put(sk); /* passive closing */\n\t\tbreak;\n\tcase SMC_APPFINCLOSEWAIT:\n\t\tsk->sk_state = SMC_PROCESSABORT;\n\t\tbreak;\n\tcase SMC_PEERCLOSEWAIT1:\n\tcase SMC_PEERCLOSEWAIT2:\n\t\tif (txflags->peer_done_writing &&\n\t\t    !smc_close_sent_any_close(&smc->conn))\n\t\t\t/* just shutdown, but not yet closed locally */\n\t\t\tsk->sk_state = SMC_PROCESSABORT;\n\t\telse\n\t\t\tsk->sk_state = SMC_CLOSED;\n\t\tsock_put(sk); /* passive closing */\n\t\tbreak;\n\tcase SMC_APPCLOSEWAIT2:\n\tcase SMC_PEERFINCLOSEWAIT:\n\t\tsk->sk_state = SMC_CLOSED;\n\t\tsock_put(sk); /* passive closing */\n\t\tbreak;\n\tcase SMC_PEERABORTWAIT:\n\t\tsk->sk_state = SMC_CLOSED;\n\t\tbreak;\n\tcase SMC_PROCESSABORT:\n\t/* nothing to do, add tracing in future patch */\n\t\tbreak;\n\t}\n}",
        "static void __dump_page(struct page *page)\n{\n\tstruct folio *folio = page_folio(page);\n\tstruct page *head = &folio->page;\n\tstruct address_space *mapping;": "static void __dump_page(struct page *page)\n{\n\tstruct folio *folio = page_folio(page);\n\tstruct page *head = &folio->page;\n\tstruct address_space *mapping;\n\tbool compound = PageCompound(page);\n\t/*\n\t * Accessing the pageblock without the zone lock. It could change to\n\t * \"isolate\" again in the meantime, but since we are just dumping the\n\t * state for debugging, it should be fine to accept a bit of\n\t * inaccuracy here due to racing.\n\t */\n\tbool page_cma = is_migrate_cma_page(page);\n\tint mapcount;\n\tchar *type = \"\";\n\n\tif (page < head || (page >= head + MAX_ORDER_NR_PAGES)) {\n\t\t/*\n\t\t * Corrupt page, so we cannot call page_mapping. Instead, do a\n\t\t * safe subset of the steps that page_mapping() does. Caution:\n\t\t * this will be misleading for tail pages, PageSwapCache pages,\n\t\t * and potentially other situations. (See the page_mapping()\n\t\t * implementation for what's missing here.)\n\t\t */\n\t\tunsigned long tmp = (unsigned long)page->mapping;\n\n\t\tif (tmp & PAGE_MAPPING_ANON)\n\t\t\tmapping = NULL;\n\t\telse\n\t\t\tmapping = (void *)(tmp & ~PAGE_MAPPING_FLAGS);\n\t\thead = page;\n\t\tfolio = (struct folio *)page;\n\t\tcompound = false;\n\t} else {\n\t\tmapping = page_mapping(page);\n\t}\n\n\t/*\n\t * Avoid VM_BUG_ON() in page_mapcount().\n\t * page->_mapcount space in struct page is used by sl[aou]b pages to\n\t * encode own info.\n\t */\n\tmapcount = PageSlab(head) ? 0 : page_mapcount(page);\n\n\tpr_warn(\"page:%p refcount:%d mapcount:%d mapping:%p index:%#lx pfn:%#lx\\n\",\n\t\t\tpage, page_ref_count(head), mapcount, mapping,\n\t\t\tpage_to_pgoff(page), page_to_pfn(page));\n\tif (compound) {\n\t\tpr_warn(\"head:%p order:%u compound_mapcount:%d compound_pincount:%d\\n\",\n\t\t\t\thead, compound_order(head),\n\t\t\t\tfolio_entire_mapcount(folio),\n\t\t\t\thead_compound_pincount(head));\n\t}\n\n#ifdef CONFIG_MEMCG\n\tif (head->memcg_data)\n\t\tpr_warn(\"memcg:%lx\\n\", head->memcg_data);\n#endif\n\tif (PageKsm(page))\n\t\ttype = \"ksm \";\n\telse if (PageAnon(page))\n\t\ttype = \"anon \";\n\telse if (mapping)\n\t\tdump_mapping(mapping);\n\tBUILD_BUG_ON(ARRAY_SIZE(pageflag_names) != __NR_PAGEFLAGS + 1);\n\n\tpr_warn(\"%sflags: %pGp%s\\n\", type, &head->flags,\n\t\tpage_cma ? \" CMA\" : \"\");\n\tprint_hex_dump(KERN_WARNING, \"raw: \", DUMP_PREFIX_NONE, 32,\n\t\t\tsizeof(unsigned long), page,\n\t\t\tsizeof(struct page), false);\n\tif (head != page)\n\t\tprint_hex_dump(KERN_WARNING, \"head: \", DUMP_PREFIX_NONE, 32,\n\t\t\tsizeof(unsigned long), head,\n\t\t\tsizeof(struct page), false);\n}",
        "static int tlmi_simple_call(const char *guid, const char *arg)\n{\n\tconst struct acpi_buffer input = { strlen(arg), (char *)arg };\n\tstruct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };\n\tacpi_status status;": "static int tlmi_simple_call(const char *guid, const char *arg)\n{\n\tconst struct acpi_buffer input = { strlen(arg), (char *)arg };\n\tstruct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };\n\tacpi_status status;\n\tint i, err;\n\n\t/*\n\t * Duplicated call required to match BIOS workaround for behavior\n\t * seen when WMI accessed via scripting on other OS.\n\t */\n\tfor (i = 0; i < 2; i++) {\n\t\t/* (re)initialize output buffer to default state */\n\t\toutput.length = ACPI_ALLOCATE_BUFFER;\n\t\toutput.pointer = NULL;\n\n\t\tstatus = wmi_evaluate_method(guid, 0, 0, &input, &output);\n\t\tif (ACPI_FAILURE(status)) {\n\t\t\tkfree(output.pointer);\n\t\t\treturn -EIO;\n\t\t}\n\t\terr = tlmi_extract_error(&output);\n\t\tkfree(output.pointer);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\treturn 0;\n}",
        "static void enable_video_mode(struct _adapter *padapter, int cbw40_value)\n{\n\t/*   bit 8:\n\t *   1 -> enable video mode to 96B AP\n\t *   0 -> disable video mode to 96B AP": "static void enable_video_mode(struct _adapter *padapter, int cbw40_value)\n{\n\t/*   bit 8:\n\t *   1 -> enable video mode to 96B AP\n\t *   0 -> disable video mode to 96B AP\n\t *   bit 9:\n\t *   1 -> enable 40MHz mode\n\t *   0 -> disable 40MHz mode\n\t *   bit 10:\n\t *   1 -> enable STBC\n\t *   0 -> disable STBC\n\t */\n\tu32  intcmd = 0xf4000500;   /* enable bit8, bit10*/\n\n\tif (cbw40_value) {\n\t\t/* if the driver supports the 40M bandwidth,\n\t\t * we can enable the bit 9.\n\t\t */\n\t\tintcmd |= 0x200;\n\t}\n\tr8712_fw_cmd(padapter, intcmd);\n}",
        "static inline void uclamp_rq_inc(struct rq *rq, struct task_struct *p)\n{\n\tenum uclamp_id clamp_id;\n\n\t/*": "static inline void uclamp_rq_inc(struct rq *rq, struct task_struct *p)\n{\n\tenum uclamp_id clamp_id;\n\n\t/*\n\t * Avoid any overhead until uclamp is actually used by the userspace.\n\t *\n\t * The condition is constructed such that a NOP is generated when\n\t * sched_uclamp_used is disabled.\n\t */\n\tif (!static_branch_unlikely(&sched_uclamp_used))\n\t\treturn;\n\n\tif (unlikely(!p->sched_class->uclamp_enabled))\n\t\treturn;\n\n\tfor_each_clamp_id(clamp_id)\n\t\tuclamp_rq_inc_id(rq, p, clamp_id);\n\n\t/* Reset clamp idle holding when there is one RUNNABLE task */\n\tif (rq->uclamp_flags & UCLAMP_FLAG_IDLE)\n\t\trq->uclamp_flags &= ~UCLAMP_FLAG_IDLE;\n}",
        "static int lpddr2_nvm_pfow_present(struct map_info *map)\n{\n\tmap_word pfow_val[4];\n\tunsigned int found = 1;\n": "static int lpddr2_nvm_pfow_present(struct map_info *map)\n{\n\tmap_word pfow_val[4];\n\tunsigned int found = 1;\n\n\tmutex_lock(&lpdd2_nvm_mutex);\n\n\tow_enable(map);\n\n\t/* Load string from array */\n\tpfow_val[0] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_P));\n\tpfow_val[1] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_F));\n\tpfow_val[2] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_O));\n\tpfow_val[3] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_W));\n\n\t/* Verify the string loaded vs expected */\n\tif (!map_word_equal(map, build_map_word('P'), pfow_val[0]))\n\t\tfound = 0;\n\tif (!map_word_equal(map, build_map_word('F'), pfow_val[1]))\n\t\tfound = 0;\n\tif (!map_word_equal(map, build_map_word('O'), pfow_val[2]))\n\t\tfound = 0;\n\tif (!map_word_equal(map, build_map_word('W'), pfow_val[3]))\n\t\tfound = 0;\n\n\tow_disable(map);\n\n\tmutex_unlock(&lpdd2_nvm_mutex);\n\n\treturn found;\n}",
        "static void __reset_isolation_suitable(struct zone *zone)\n{\n\tunsigned long migrate_pfn = zone->zone_start_pfn;\n\tunsigned long free_pfn = zone_end_pfn(zone) - 1;\n\tunsigned long reset_migrate = free_pfn;": "static void __reset_isolation_suitable(struct zone *zone)\n{\n\tunsigned long migrate_pfn = zone->zone_start_pfn;\n\tunsigned long free_pfn = zone_end_pfn(zone) - 1;\n\tunsigned long reset_migrate = free_pfn;\n\tunsigned long reset_free = migrate_pfn;\n\tbool source_set = false;\n\tbool free_set = false;\n\n\tif (!zone->compact_blockskip_flush)\n\t\treturn;\n\n\tzone->compact_blockskip_flush = false;\n\n\t/*\n\t * Walk the zone and update pageblock skip information. Source looks\n\t * for PageLRU while target looks for PageBuddy. When the scanner\n\t * is found, both PageBuddy and PageLRU are checked as the pageblock\n\t * is suitable as both source and target.\n\t */\n\tfor (; migrate_pfn < free_pfn; migrate_pfn += pageblock_nr_pages,\n\t\t\t\t\tfree_pfn -= pageblock_nr_pages) {\n\t\tcond_resched();\n\n\t\t/* Update the migrate PFN */\n\t\tif (__reset_isolation_pfn(zone, migrate_pfn, true, source_set) &&\n\t\t    migrate_pfn < reset_migrate) {\n\t\t\tsource_set = true;\n\t\t\treset_migrate = migrate_pfn;\n\t\t\tzone->compact_init_migrate_pfn = reset_migrate;\n\t\t\tzone->compact_cached_migrate_pfn[0] = reset_migrate;\n\t\t\tzone->compact_cached_migrate_pfn[1] = reset_migrate;\n\t\t}\n\n\t\t/* Update the free PFN */\n\t\tif (__reset_isolation_pfn(zone, free_pfn, free_set, true) &&\n\t\t    free_pfn > reset_free) {\n\t\t\tfree_set = true;\n\t\t\treset_free = free_pfn;\n\t\t\tzone->compact_init_free_pfn = reset_free;\n\t\t\tzone->compact_cached_free_pfn = reset_free;\n\t\t}\n\t}\n\n\t/* Leave no distance if no suitable block was reset */\n\tif (reset_migrate >= reset_free) {\n\t\tzone->compact_cached_migrate_pfn[0] = migrate_pfn;\n\t\tzone->compact_cached_migrate_pfn[1] = migrate_pfn;\n\t\tzone->compact_cached_free_pfn = free_pfn;\n\t}\n}",
        "static int do_skeleton(int argc, char **argv)\n{\n\tchar header_guard[MAX_OBJ_NAME_LEN + sizeof(\"__SKEL_H__\")];\n\tsize_t map_cnt = 0, prog_cnt = 0, file_sz, mmap_sz;\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, opts);": "static int do_skeleton(int argc, char **argv)\n{\n\tchar header_guard[MAX_OBJ_NAME_LEN + sizeof(\"__SKEL_H__\")];\n\tsize_t map_cnt = 0, prog_cnt = 0, file_sz, mmap_sz;\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, opts);\n\tchar obj_name[MAX_OBJ_NAME_LEN] = \"\", *obj_data;\n\tstruct bpf_object *obj = NULL;\n\tconst char *file;\n\tchar ident[256];\n\tstruct bpf_program *prog;\n\tint fd, err = -1;\n\tstruct bpf_map *map;\n\tstruct btf *btf;\n\tstruct stat st;\n\n\tif (!REQ_ARGS(1)) {\n\t\tusage();\n\t\treturn -1;\n\t}\n\tfile = GET_ARG();\n\n\twhile (argc) {\n\t\tif (!REQ_ARGS(2))\n\t\t\treturn -1;\n\n\t\tif (is_prefix(*argv, \"name\")) {\n\t\t\tNEXT_ARG();\n\n\t\t\tif (obj_name[0] != '\\0') {\n\t\t\t\tp_err(\"object name already specified\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tstrncpy(obj_name, *argv, MAX_OBJ_NAME_LEN - 1);\n\t\t\tobj_name[MAX_OBJ_NAME_LEN - 1] = '\\0';\n\t\t} else {\n\t\t\tp_err(\"unknown arg %s\", *argv);\n\t\t\treturn -1;\n\t\t}\n\n\t\tNEXT_ARG();\n\t}\n\n\tif (argc) {\n\t\tp_err(\"extra unknown arguments\");\n\t\treturn -1;\n\t}\n\n\tif (stat(file, &st)) {\n\t\tp_err(\"failed to stat() %s: %s\", file, strerror(errno));\n\t\treturn -1;\n\t}\n\tfile_sz = st.st_size;\n\tmmap_sz = roundup(file_sz, sysconf(_SC_PAGE_SIZE));\n\tfd = open(file, O_RDONLY);\n\tif (fd < 0) {\n\t\tp_err(\"failed to open() %s: %s\", file, strerror(errno));\n\t\treturn -1;\n\t}\n\tobj_data = mmap(NULL, mmap_sz, PROT_READ, MAP_PRIVATE, fd, 0);\n\tif (obj_data == MAP_FAILED) {\n\t\tobj_data = NULL;\n\t\tp_err(\"failed to mmap() %s: %s\", file, strerror(errno));\n\t\tgoto out;\n\t}\n\tif (obj_name[0] == '\\0')\n\t\tget_obj_name(obj_name, file);\n\topts.object_name = obj_name;\n\tif (verifier_logs)\n\t\t/* log_level1 + log_level2 + stats, but not stable UAPI */\n\t\topts.kernel_log_level = 1 + 2 + 4;\n\tobj = bpf_object__open_mem(obj_data, file_sz, &opts);\n\terr = libbpf_get_error(obj);\n\tif (err) {\n\t\tchar err_buf[256];\n\n\t\tlibbpf_strerror(err, err_buf, sizeof(err_buf));\n\t\tp_err(\"failed to open BPF object file: %s\", err_buf);\n\t\tobj = NULL;\n\t\tgoto out;\n\t}\n\n\tbpf_object__for_each_map(map, obj) {\n\t\tif (!get_map_ident(map, ident, sizeof(ident))) {\n\t\t\tp_err(\"ignoring unrecognized internal map '%s'...\",\n\t\t\t      bpf_map__name(map));\n\t\t\tcontinue;\n\t\t}\n\t\tmap_cnt++;\n\t}\n\tbpf_object__for_each_program(prog, obj) {\n\t\tprog_cnt++;\n\t}\n\n\tget_header_guard(header_guard, obj_name, \"SKEL_H\");\n\tif (use_loader) {\n\t\tcodegen(\"\\\n\t\t\\n\\\n\t\t/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */   \\n\\\n\t\t/* THIS FILE IS AUTOGENERATED BY BPFTOOL! */\t\t    \\n\\\n\t\t#ifndef %2$s\t\t\t\t\t\t    \\n\\\n\t\t#define %2$s\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#include <bpf/skel_internal.h>\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstruct %1$s {\t\t\t\t\t\t    \\n\\\n\t\t\tstruct bpf_loader_ctx ctx;\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name, header_guard\n\t\t);\n\t} else {\n\t\tcodegen(\"\\\n\t\t\\n\\\n\t\t/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */   \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t/* THIS FILE IS AUTOGENERATED BY BPFTOOL! */\t\t    \\n\\\n\t\t#ifndef %2$s\t\t\t\t\t\t    \\n\\\n\t\t#define %2$s\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#include <errno.h>\t\t\t\t\t    \\n\\\n\t\t#include <stdlib.h>\t\t\t\t\t    \\n\\\n\t\t#include <bpf/libbpf.h>\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstruct %1$s {\t\t\t\t\t\t    \\n\\\n\t\t\tstruct bpf_object_skeleton *skeleton;\t\t    \\n\\\n\t\t\tstruct bpf_object *obj;\t\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name, header_guard\n\t\t);\n\t}\n\n\tif (map_cnt) {\n\t\tprintf(\"\\tstruct {\\n\");\n\t\tbpf_object__for_each_map(map, obj) {\n\t\t\tif (!get_map_ident(map, ident, sizeof(ident)))\n\t\t\t\tcontinue;\n\t\t\tif (use_loader)\n\t\t\t\tprintf(\"\\t\\tstruct bpf_map_desc %s;\\n\", ident);\n\t\t\telse\n\t\t\t\tprintf(\"\\t\\tstruct bpf_map *%s;\\n\", ident);\n\t\t}\n\t\tprintf(\"\\t} maps;\\n\");\n\t}\n\n\tif (prog_cnt) {\n\t\tprintf(\"\\tstruct {\\n\");\n\t\tbpf_object__for_each_program(prog, obj) {\n\t\t\tif (use_loader)\n\t\t\t\tprintf(\"\\t\\tstruct bpf_prog_desc %s;\\n\",\n\t\t\t\t       bpf_program__name(prog));\n\t\t\telse\n\t\t\t\tprintf(\"\\t\\tstruct bpf_program *%s;\\n\",\n\t\t\t\t       bpf_program__name(prog));\n\t\t}\n\t\tprintf(\"\\t} progs;\\n\");\n\t\tprintf(\"\\tstruct {\\n\");\n\t\tbpf_object__for_each_program(prog, obj) {\n\t\t\tif (use_loader)\n\t\t\t\tprintf(\"\\t\\tint %s_fd;\\n\",\n\t\t\t\t       bpf_program__name(prog));\n\t\t\telse\n\t\t\t\tprintf(\"\\t\\tstruct bpf_link *%s;\\n\",\n\t\t\t\t       bpf_program__name(prog));\n\t\t}\n\t\tprintf(\"\\t} links;\\n\");\n\t}\n\n\tbtf = bpf_object__btf(obj);\n\tif (btf) {\n\t\terr = codegen_datasecs(obj, obj_name);\n\t\tif (err)\n\t\t\tgoto out;\n\t}\n\tif (use_loader) {\n\t\terr = gen_trace(obj, obj_name, header_guard);\n\t\tgoto out;\n\t}\n\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#ifdef __cplusplus\t\t\t\t\t    \\n\\\n\t\t\tstatic inline struct %1$s *open(const struct bpf_object_open_opts *opts = nullptr);\\n\\\n\t\t\tstatic inline struct %1$s *open_and_load();\t    \\n\\\n\t\t\tstatic inline int load(struct %1$s *skel);\t    \\n\\\n\t\t\tstatic inline int attach(struct %1$s *skel);\t    \\n\\\n\t\t\tstatic inline void detach(struct %1$s *skel);\t    \\n\\\n\t\t\tstatic inline void destroy(struct %1$s *skel);\t    \\n\\\n\t\t\tstatic inline const void *elf_bytes(size_t *sz);    \\n\\\n\t\t#endif /* __cplusplus */\t\t\t\t    \\n\\\n\t\t};\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic void\t\t\t\t\t\t    \\n\\\n\t\t%1$s__destroy(struct %1$s *obj)\t\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\tif (!obj)\t\t\t\t\t    \\n\\\n\t\t\t\treturn;\t\t\t\t\t    \\n\\\n\t\t\tif (obj->skeleton)\t\t\t\t    \\n\\\n\t\t\t\tbpf_object__destroy_skeleton(obj->skeleton);\\n\\\n\t\t\tfree(obj);\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline int\t\t\t\t\t    \\n\\\n\t\t%1$s__create_skeleton(struct %1$s *obj);\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline struct %1$s *\t\t\t\t    \\n\\\n\t\t%1$s__open_opts(const struct bpf_object_open_opts *opts)    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\tstruct %1$s *obj;\t\t\t\t    \\n\\\n\t\t\tint err;\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\tobj = (struct %1$s *)calloc(1, sizeof(*obj));\t    \\n\\\n\t\t\tif (!obj) {\t\t\t\t\t    \\n\\\n\t\t\t\terrno = ENOMEM;\t\t\t\t    \\n\\\n\t\t\t\treturn NULL;\t\t\t\t    \\n\\\n\t\t\t}\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\terr = %1$s__create_skeleton(obj);\t\t    \\n\\\n\t\t\tif (err)\t\t\t\t\t    \\n\\\n\t\t\t\tgoto err_out;\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\terr = bpf_object__open_skeleton(obj->skeleton, opts);\\n\\\n\t\t\tif (err)\t\t\t\t\t    \\n\\\n\t\t\t\tgoto err_out;\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\treturn obj;\t\t\t\t\t    \\n\\\n\t\terr_out:\t\t\t\t\t\t    \\n\\\n\t\t\t%1$s__destroy(obj);\t\t\t\t    \\n\\\n\t\t\terrno = -err;\t\t\t\t\t    \\n\\\n\t\t\treturn NULL;\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline struct %1$s *\t\t\t\t    \\n\\\n\t\t%1$s__open(void)\t\t\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\treturn %1$s__open_opts(NULL);\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline int\t\t\t\t\t    \\n\\\n\t\t%1$s__load(struct %1$s *obj)\t\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\treturn bpf_object__load_skeleton(obj->skeleton);    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline struct %1$s *\t\t\t\t    \\n\\\n\t\t%1$s__open_and_load(void)\t\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\tstruct %1$s *obj;\t\t\t\t    \\n\\\n\t\t\tint err;\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\tobj = %1$s__open();\t\t\t\t    \\n\\\n\t\t\tif (!obj)\t\t\t\t\t    \\n\\\n\t\t\t\treturn NULL;\t\t\t\t    \\n\\\n\t\t\terr = %1$s__load(obj);\t\t\t\t    \\n\\\n\t\t\tif (err) {\t\t\t\t\t    \\n\\\n\t\t\t\t%1$s__destroy(obj);\t\t\t    \\n\\\n\t\t\t\terrno = -err;\t\t\t\t    \\n\\\n\t\t\t\treturn NULL;\t\t\t\t    \\n\\\n\t\t\t}\t\t\t\t\t\t    \\n\\\n\t\t\treturn obj;\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline int\t\t\t\t\t    \\n\\\n\t\t%1$s__attach(struct %1$s *obj)\t\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\treturn bpf_object__attach_skeleton(obj->skeleton);  \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline void\t\t\t\t\t    \\n\\\n\t\t%1$s__detach(struct %1$s *obj)\t\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\treturn bpf_object__detach_skeleton(obj->skeleton);  \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name\n\t);\n\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline const void *%1$s__elf_bytes(size_t *sz);\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline int\t\t\t\t\t    \\n\\\n\t\t%1$s__create_skeleton(struct %1$s *obj)\t\t\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\tstruct bpf_object_skeleton *s;\t\t\t    \\n\\\n\t\t\tint err;\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\ts = (struct bpf_object_skeleton *)calloc(1, sizeof(*s));\\n\\\n\t\t\tif (!s)\t{\t\t\t\t\t    \\n\\\n\t\t\t\terr = -ENOMEM;\t\t\t\t    \\n\\\n\t\t\t\tgoto err;\t\t\t\t    \\n\\\n\t\t\t}\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\ts->sz = sizeof(*s);\t\t\t\t    \\n\\\n\t\t\ts->name = \\\"%1$s\\\";\t\t\t\t    \\n\\\n\t\t\ts->obj = &obj->obj;\t\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name\n\t);\n\n\tcodegen_maps_skeleton(obj, map_cnt, true /*mmaped*/);\n\tcodegen_progs_skeleton(obj, prog_cnt, true /*populate_links*/);\n\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\ts->data = (void *)%2$s__elf_bytes(&s->data_sz);\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\tobj->skeleton = s;\t\t\t\t    \\n\\\n\t\t\treturn 0;\t\t\t\t\t    \\n\\\n\t\terr:\t\t\t\t\t\t\t    \\n\\\n\t\t\tbpf_object__destroy_skeleton(s);\t\t    \\n\\\n\t\t\treturn err;\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\tstatic inline const void *%2$s__elf_bytes(size_t *sz)\t    \\n\\\n\t\t{\t\t\t\t\t\t\t    \\n\\\n\t\t\t*sz = %1$d;\t\t\t\t\t    \\n\\\n\t\t\treturn (const void *)\\\"\\\\\t\t\t    \\n\\\n\t\t\"\n\t\t, file_sz, obj_name);\n\n\t/* embed contents of BPF object file */\n\tprint_hex(obj_data, file_sz);\n\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\\\";\t\t\t\t\t\t\t    \\n\\\n\t\t}\t\t\t\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#ifdef __cplusplus\t\t\t\t\t    \\n\\\n\t\tstruct %1$s *%1$s::open(const struct bpf_object_open_opts *opts) { return %1$s__open_opts(opts); }\\n\\\n\t\tstruct %1$s *%1$s::open_and_load() { return %1$s__open_and_load(); }\t\\n\\\n\t\tint %1$s::load(struct %1$s *skel) { return %1$s__load(skel); }\t\t\\n\\\n\t\tint %1$s::attach(struct %1$s *skel) { return %1$s__attach(skel); }\t\\n\\\n\t\tvoid %1$s::detach(struct %1$s *skel) { %1$s__detach(skel); }\t\t\\n\\\n\t\tvoid %1$s::destroy(struct %1$s *skel) { %1$s__destroy(skel); }\t\t\\n\\\n\t\tconst void *%1$s::elf_bytes(size_t *sz) { return %1$s__elf_bytes(sz); } \\n\\\n\t\t#endif /* __cplusplus */\t\t\t\t    \\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t\",\n\t\tobj_name);\n\n\tcodegen_asserts(obj, obj_name);\n\n\tcodegen(\"\\\n\t\t\\n\\\n\t\t\t\t\t\t\t\t\t    \\n\\\n\t\t#endif /* %1$s */\t\t\t\t\t    \\n\\\n\t\t\",\n\t\theader_guard);\n\terr = 0;\nout:\n\tbpf_object__close(obj);\n\tif (obj_data)\n\t\tmunmap(obj_data, mmap_sz);\n\tclose(fd);\n\treturn err;\n}",
        "static void print_lock_class_header(struct lock_class *class, int depth)\n{\n\tint bit;\n\n\tprintk(\"%*s->\", depth, \"\");": "static void print_lock_class_header(struct lock_class *class, int depth)\n{\n\tint bit;\n\n\tprintk(\"%*s->\", depth, \"\");\n\tprint_lock_name(class);\n#ifdef CONFIG_DEBUG_LOCKDEP\n\tprintk(KERN_CONT \" ops: %lu\", debug_class_ops_read(class));\n#endif\n\tprintk(KERN_CONT \" {\\n\");\n\n\tfor (bit = 0; bit < LOCK_TRACE_STATES; bit++) {\n\t\tif (class->usage_mask & (1 << bit)) {\n\t\t\tint len = depth;\n\n\t\t\tlen += printk(\"%*s   %s\", depth, \"\", usage_str[bit]);\n\t\t\tlen += printk(KERN_CONT \" at:\\n\");\n\t\t\tprint_lock_trace(class->usage_traces[bit], len);\n\t\t}\n\t}\n\tprintk(\"%*s }\\n\", depth, \"\");\n\n\tprintk(\"%*s ... key      at: [<%px>] %pS\\n\",\n\t\tdepth, \"\", class->key, class->key);\n}",
        "static void nfdicf_init(void)\n{\n\tFILE *file;\n\tunsigned int unichar;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */": "static void nfdicf_init(void)\n{\n\tFILE *file;\n\tunsigned int unichar;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */\n\tchar status;\n\tchar *s;\n\tunsigned int *um;\n\tint i;\n\tint count;\n\tint ret;\n\n\tif (verbose > 0)\n\t\tprintf(\"Parsing %s\\n\", fold_name);\n\tfile = fopen(fold_name, \"r\");\n\tif (!file)\n\t\topen_fail(fold_name, errno);\n\n\tcount = 0;\n\twhile (fgets(line, LINESIZE, file)) {\n\t\tret = sscanf(line, \"%X; %c; %[^;];\", &unichar, &status, buf0);\n\t\tif (ret != 3)\n\t\t\tcontinue;\n\t\tif (!utf32valid(unichar))\n\t\t\tline_fail(fold_name, line);\n\t\t/* Use the C+F casefold. */\n\t\tif (status != 'C' && status != 'F')\n\t\t\tcontinue;\n\t\ts = buf0;\n\t\tif (*s == '<')\n\t\t\twhile (*s++ != ' ')\n\t\t\t\t;\n\t\ti = 0;\n\t\twhile (*s) {\n\t\t\tmapping[i] = strtoul(s, &s, 16);\n\t\t\tif (!utf32valid(mapping[i]))\n\t\t\t\tline_fail(fold_name, line);\n\t\t\ti++;\n\t\t}\n\t\tmapping[i++] = 0;\n\n\t\tum = malloc(i * sizeof(unsigned int));\n\t\tmemcpy(um, mapping, i * sizeof(unsigned int));\n\t\tunicode_data[unichar].utf32nfdicf = um;\n\n\t\tif (verbose > 1)\n\t\t\tprint_utf32nfdicf(unichar);\n\t\tcount++;\n\t}\n\tfclose(file);\n\tif (verbose > 0)\n\t\tprintf(\"Found %d entries\\n\", count);\n\tif (count == 0)\n\t\tfile_fail(fold_name);\n}",
        "static void subflow_data_ready(struct sock *sk)\n{\n\tstruct mptcp_subflow_context *subflow = mptcp_subflow_ctx(sk);\n\tu16 state = 1 << inet_sk_state_load(sk);\n\tstruct sock *parent = subflow->conn;": "static void subflow_data_ready(struct sock *sk)\n{\n\tstruct mptcp_subflow_context *subflow = mptcp_subflow_ctx(sk);\n\tu16 state = 1 << inet_sk_state_load(sk);\n\tstruct sock *parent = subflow->conn;\n\tstruct mptcp_sock *msk;\n\n\tmsk = mptcp_sk(parent);\n\tif (state & TCPF_LISTEN) {\n\t\t/* MPJ subflow are removed from accept queue before reaching here,\n\t\t * avoid stray wakeups\n\t\t */\n\t\tif (reqsk_queue_empty(&inet_csk(sk)->icsk_accept_queue))\n\t\t\treturn;\n\n\t\tparent->sk_data_ready(parent);\n\t\treturn;\n\t}\n\n\tWARN_ON_ONCE(!__mptcp_check_fallback(msk) && !subflow->mp_capable &&\n\t\t     !subflow->mp_join && !(state & TCPF_CLOSE));\n\n\tif (mptcp_subflow_data_available(sk))\n\t\tmptcp_data_ready(parent, sk);\n\telse if (unlikely(sk->sk_err))\n\t\tsubflow_error_report(sk);\n}",
        "static int nv_alloc_rx_optimized(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tstruct ring_desc_ex *less_rx;\n": "static int nv_alloc_rx_optimized(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tstruct ring_desc_ex *less_rx;\n\n\tless_rx = np->get_rx.ex;\n\tif (less_rx-- == np->rx_ring.ex)\n\t\tless_rx = np->last_rx.ex;\n\n\twhile (np->put_rx.ex != less_rx) {\n\t\tstruct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);\n\t\tif (likely(skb)) {\n\t\t\tnp->put_rx_ctx->skb = skb;\n\t\t\tnp->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,\n\t\t\t\t\t\t\t     skb->data,\n\t\t\t\t\t\t\t     skb_tailroom(skb),\n\t\t\t\t\t\t\t     DMA_FROM_DEVICE);\n\t\t\tif (unlikely(dma_mapping_error(&np->pci_dev->dev,\n\t\t\t\t\t\t       np->put_rx_ctx->dma))) {\n\t\t\t\tkfree_skb(skb);\n\t\t\t\tgoto packet_dropped;\n\t\t\t}\n\t\t\tnp->put_rx_ctx->dma_len = skb_tailroom(skb);\n\t\t\tnp->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));\n\t\t\tnp->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));\n\t\t\twmb();\n\t\t\tnp->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);\n\t\t\tif (unlikely(np->put_rx.ex++ == np->last_rx.ex))\n\t\t\t\tnp->put_rx.ex = np->rx_ring.ex;\n\t\t\tif (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))\n\t\t\t\tnp->put_rx_ctx = np->rx_skb;\n\t\t} else {\npacket_dropped:\n\t\t\tu64_stats_update_begin(&np->swstats_rx_syncp);\n\t\t\tnv_txrx_stats_inc(stat_rx_dropped);\n\t\t\tu64_stats_update_end(&np->swstats_rx_syncp);\n\t\t\treturn 1;\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)\n{\n\tint err, i, z, gpr, tmp, playback, capture;\n\tu32 ptr;\n\tstruct snd_emu10k1_fx8010_code *icode;": "static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)\n{\n\tint err, i, z, gpr, tmp, playback, capture;\n\tu32 ptr;\n\tstruct snd_emu10k1_fx8010_code *icode;\n\tstruct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;\n\tstruct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;\n\tu32 *gpr_map;\n\n\terr = -ENOMEM;\n\ticode = kzalloc(sizeof(*icode), GFP_KERNEL);\n\tif (!icode)\n\t\treturn err;\n\n\ticode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512,\n\t\t\t\t sizeof(u_int32_t), GFP_KERNEL);\n\tif (!icode->gpr_map)\n\t\tgoto __err_gpr;\n\n\tcontrols = kcalloc(SND_EMU10K1_GPR_CONTROLS,\n\t\t\t   sizeof(struct snd_emu10k1_fx8010_control_gpr),\n\t\t\t   GFP_KERNEL);\n\tif (!controls)\n\t\tgoto __err_ctrls;\n\n\tipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);\n\tif (!ipcm)\n\t\tgoto __err_ipcm;\n\n\tgpr_map = icode->gpr_map;\n\n\ticode->tram_data_map = icode->gpr_map + 256;\n\ticode->tram_addr_map = icode->tram_data_map + 160;\n\ticode->code = icode->tram_addr_map + 160;\n\t\n\t/* clear free GPRs */\n\tfor (i = 0; i < 256; i++)\n\t\tset_bit(i, icode->gpr_valid);\n\n\t/* clear TRAM data & address lines */\n\tfor (i = 0; i < 160; i++)\n\t\tset_bit(i, icode->tram_valid);\n\n\tstrcpy(icode->name, \"SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela\");\n\tptr = 0; i = 0;\n\t/* we have 12 inputs */\n\tplayback = SND_EMU10K1_INPUTS;\n\t/* we have 6 playback channels and tone control doubles */\n\tcapture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);\n\tgpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;\n\ttmp = 0x88;\t/* we need 4 temporary GPR */\n\t/* from 0x8c to 0xff is the area for tone control */\n\n\t/* stop FX processor */\n\tsnd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);\n\n\t/*\n\t *  Process FX Buses\n\t */\n\tOP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000);\t/* S/PDIF left */\n\tOP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000);\t/* S/PDIF right */\n\tOP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);\n\tOP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);\n\n\t/* Raw S/PDIF PCM */\n\tipcm->substream = 0;\n\tipcm->channels = 2;\n\tipcm->tram_start = 0;\n\tipcm->buffer_size = (64 * 1024) / 2;\n\tipcm->gpr_size = gpr++;\n\tipcm->gpr_ptr = gpr++;\n\tipcm->gpr_count = gpr++;\n\tipcm->gpr_tmpcount = gpr++;\n\tipcm->gpr_trigger = gpr++;\n\tipcm->gpr_running = gpr++;\n\tipcm->etram[0] = 0;\n\tipcm->etram[1] = 1;\n\n\tgpr_map[gpr + 0] = 0xfffff000;\n\tgpr_map[gpr + 1] = 0xffff0000;\n\tgpr_map[gpr + 2] = 0x70000000;\n\tgpr_map[gpr + 3] = 0x00000007;\n\tgpr_map[gpr + 4] = 0x001f << 11;\n\tgpr_map[gpr + 5] = 0x001c << 11;\n\tgpr_map[gpr + 6] = (0x22  - 0x01) - 1;\t/* skip at 01 to 22 */\n\tgpr_map[gpr + 7] = (0x22  - 0x06) - 1;\t/* skip at 06 to 22 */\n\tgpr_map[gpr + 8] = 0x2000000 + (2<<11);\n\tgpr_map[gpr + 9] = 0x4000000 + (2<<11);\n\tgpr_map[gpr + 10] = 1<<11;\n\tgpr_map[gpr + 11] = (0x24 - 0x0a) - 1;\t/* skip at 0a to 24 */\n\tgpr_map[gpr + 12] = 0;\n\n\t/* if the trigger flag is not set, skip */\n\t/* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);\n\t/* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));\n\t/* if the running flag is set, we're running */\n\t/* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);\n\t/* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);\n\t/* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */\n\t/* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);\n\t/* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));\n\t/* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));\n\t/* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);\n\n\t/* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);\n\t/* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);\n\t/* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));\n\t/* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);\n\n\t/* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);\n\t/* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);\n\t/* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));\n\t/* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);\n\t/* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));\n\n\t/* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);\n\t/* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);\n\t/* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));\n\t/* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);\n\t/* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));\n\n\t/* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);\n\t/* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));\n\t/* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);\n\t/* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);\n\t/* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);\n\t\n\t/* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);\n\t/* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);\n\t/* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);\n\t/* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);\n\t/* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);\n\n\t/* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);\n\t/* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);\n\n\t/* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);\n\t/* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);\n\n\t/* 24: */\n\tgpr += 13;\n\n\t/* Wave Playback Volume */\n\tfor (z = 0; z < 2; z++)\n\t\tVOLUME(icode, &ptr, playback + z, z, gpr + z);\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Wave Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* Wave Surround Playback Volume */\n\tfor (z = 0; z < 2; z++)\n\t\tVOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Wave Surround Playback Volume\", gpr, 0);\n\tgpr += 2;\n\t\n\t/* Wave Center/LFE Playback Volume */\n\tOP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);\n\tOP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);\n\tVOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);\n\tsnd_emu10k1_init_mono_control(controls + i++, \"Wave Center Playback Volume\", gpr++, 0);\n\tVOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);\n\tsnd_emu10k1_init_mono_control(controls + i++, \"Wave LFE Playback Volume\", gpr++, 0);\n\n\t/* Wave Capture Volume + Switch */\n\tfor (z = 0; z < 2; z++) {\n\t\tSWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);\n\t\tVOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t}\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Wave Capture Volume\", gpr, 0);\n\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Wave Capture Switch\", gpr + 2, 0);\n\tgpr += 4;\n\n\t/* Synth Playback Volume */\n\tfor (z = 0; z < 2; z++)\n\t\tVOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Synth Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* Synth Capture Volume + Switch */\n\tfor (z = 0; z < 2; z++) {\n\t\tSWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);\n\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t}\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Synth Capture Volume\", gpr, 0);\n\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Synth Capture Switch\", gpr + 2, 0);\n\tgpr += 4;\n\n\t/* Surround Digital Playback Volume (renamed later without Digital) */\n\tfor (z = 0; z < 2; z++)\n\t\tVOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Surround Digital Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* Surround Capture Volume + Switch */\n\tfor (z = 0; z < 2; z++) {\n\t\tSWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);\n\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t}\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Surround Capture Volume\", gpr, 0);\n\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Surround Capture Switch\", gpr + 2, 0);\n\tgpr += 4;\n\n\t/* Center Playback Volume (renamed later without Digital) */\n\tVOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);\n\tsnd_emu10k1_init_mono_control(controls + i++, \"Center Digital Playback Volume\", gpr++, 100);\n\n\t/* LFE Playback Volume + Switch (renamed later without Digital) */\n\tVOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);\n\tsnd_emu10k1_init_mono_control(controls + i++, \"LFE Digital Playback Volume\", gpr++, 100);\n\n\t/* Front Playback Volume */\n\tfor (z = 0; z < 2; z++)\n\t\tVOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Front Playback Volume\", gpr, 100);\n\tgpr += 2;\n\n\t/* Front Capture Volume + Switch */\n\tfor (z = 0; z < 2; z++) {\n\t\tSWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);\n\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t}\n\tsnd_emu10k1_init_stereo_control(controls + i++, \"Front Capture Volume\", gpr, 0);\n\tsnd_emu10k1_init_mono_onoff_control(controls + i++, \"Front Capture Switch\", gpr + 2, 0);\n\tgpr += 3;\n\n\t/*\n\t *  Process inputs\n\t */\n\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {\n\t\t/* AC'97 Playback Volume */\n\t\tVOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;\n\t\tVOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"AC97 Playback Volume\", gpr-2, 0);\n\t\t/* AC'97 Capture Volume */\n\t\tVOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;\n\t\tVOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"AC97 Capture Volume\", gpr-2, 100);\n\t}\n\t\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {\n\t\t/* IEC958 TTL Playback Volume */\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tVOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"TTL \",PLAYBACK,VOLUME), gpr, 0);\n\t\tgpr += 2;\n\t\n\t\t/* IEC958 TTL Capture Volume + Switch */\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);\n\t\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"TTL \",CAPTURE,VOLUME), gpr, 0);\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"TTL \",CAPTURE,SWITCH), gpr + 2, 0);\n\t\tgpr += 4;\n\t}\n\t\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {\n\t\t/* Zoom Video Playback Volume */\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tVOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Zoom Video Playback Volume\", gpr, 0);\n\t\tgpr += 2;\n\t\n\t\t/* Zoom Video Capture Volume + Switch */\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);\n\t\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Zoom Video Capture Volume\", gpr, 0);\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Zoom Video Capture Switch\", gpr + 2, 0);\n\t\tgpr += 4;\n\t}\n\t\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {\n\t\t/* IEC958 Optical Playback Volume */\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tVOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"LiveDrive \",PLAYBACK,VOLUME), gpr, 0);\n\t\tgpr += 2;\n\t\n\t\t/* IEC958 Optical Capture Volume */\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);\n\t\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"LiveDrive \",CAPTURE,VOLUME), gpr, 0);\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"LiveDrive \",CAPTURE,SWITCH), gpr + 2, 0);\n\t\tgpr += 4;\n\t}\n\t\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {\n\t\t/* Line LiveDrive Playback Volume */\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tVOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Line LiveDrive Playback Volume\", gpr, 0);\n\t\tgpr += 2;\n\t\n\t\t/* Line LiveDrive Capture Volume + Switch */\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);\n\t\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Line LiveDrive Capture Volume\", gpr, 0);\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Line LiveDrive Capture Switch\", gpr + 2, 0);\n\t\tgpr += 4;\n\t}\n\t\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {\n\t\t/* IEC958 Coax Playback Volume */\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tVOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"Coaxial \",PLAYBACK,VOLUME), gpr, 0);\n\t\tgpr += 2;\n\t\n\t\t/* IEC958 Coax Capture Volume + Switch */\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);\n\t\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"Coaxial \",CAPTURE,VOLUME), gpr, 0);\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"Coaxial \",CAPTURE,SWITCH), gpr + 2, 0);\n\t\tgpr += 4;\n\t}\n\t\n\tif (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {\n\t\t/* Line LiveDrive Playback Volume */\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tVOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Line2 LiveDrive Playback Volume\", gpr, 0);\n\t\tcontrols[i-1].id.index = 1;\n\t\tgpr += 2;\n\t\n\t\t/* Line LiveDrive Capture Volume */\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);\n\t\t\tVOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);\n\t\t}\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Line2 LiveDrive Capture Volume\", gpr, 0);\n\t\tcontrols[i-1].id.index = 1;\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Line2 LiveDrive Capture Switch\", gpr + 2, 0);\n\t\tcontrols[i-1].id.index = 1;\n\t\tgpr += 4;\n\t}\n\n\t/*\n\t *  Process tone control\n\t */\n\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */\n\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */\n\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */\n\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */\n\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */\n\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */\n\n\tctl = &controls[i + 0];\n\tctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;\n\tstrcpy(ctl->id.name, \"Tone Control - Bass\");\n\tctl->vcount = 2;\n\tctl->count = 10;\n\tctl->min = 0;\n\tctl->max = 40;\n\tctl->value[0] = ctl->value[1] = 20;\n\tctl->tlv = snd_emu10k1_bass_treble_db_scale;\n\tctl->translation = EMU10K1_GPR_TRANSLATION_BASS;\n\tctl = &controls[i + 1];\n\tctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;\n\tstrcpy(ctl->id.name, \"Tone Control - Treble\");\n\tctl->vcount = 2;\n\tctl->count = 10;\n\tctl->min = 0;\n\tctl->max = 40;\n\tctl->value[0] = ctl->value[1] = 20;\n\tctl->tlv = snd_emu10k1_bass_treble_db_scale;\n\tctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;\n\n#define BASS_GPR\t0x8c\n#define TREBLE_GPR\t0x96\n\n\tfor (z = 0; z < 5; z++) {\n\t\tint j;\n\t\tfor (j = 0; j < 2; j++) {\n\t\t\tcontrols[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;\n\t\t\tcontrols[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;\n\t\t}\n\t}\n\tfor (z = 0; z < 3; z++) {\t\t/* front/rear/center-lfe */\n\t\tint j, k, l, d;\n\t\tfor (j = 0; j < 2; j++) {\t/* left/right */\n\t\t\tk = 0xa0 + (z * 8) + (j * 4);\n\t\t\tl = 0xd0 + (z * 8) + (j * 4);\n\t\t\td = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;\n\n\t\t\tOP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));\n\t\t\tOP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));\n\t\t\tOP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));\n\t\t\tOP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));\n\t\t\tOP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));\n\t\t\tOP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);\n\n\t\t\tOP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));\n\t\t\tOP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));\n\t\t\tOP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));\n\t\t\tOP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));\n\t\t\tOP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));\n\t\t\tOP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);\n\n\t\t\tOP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);\n\n\t\t\tif (z == 2)\t/* center */\n\t\t\t\tbreak;\n\t\t}\n\t}\n\ti += 2;\n\n#undef BASS_GPR\n#undef TREBLE_GPR\n\n\tfor (z = 0; z < 6; z++) {\n\t\tSWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);\n\t\tSWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);\n\t\tSWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);\n\t\tOP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);\n\t}\n\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, \"Tone Control - Switch\", gpr, 0);\n\tgpr += 2;\n\n\t/*\n\t *  Process outputs\n\t */\n\tif (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {\n\t\t/* AC'97 Playback Volume */\n\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);\n\t}\n\n\tif (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {\n\t\t/* IEC958 Optical Raw Playback Switch */\n\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);\n\t\t\tSWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);\n\t\t\tSWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);\n\t\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);\n#ifdef EMU10K1_CAPTURE_DIGITAL_OUT\n\t \t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);\n#endif\n\t\t}\n\n\t\tsnd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958(\"Optical Raw \",PLAYBACK,SWITCH), gpr, 0);\n\t\tgpr += 2;\n\t}\n\n\tif (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {\n\t\t/* Headphone Playback Volume */\n\n\t\tfor (z = 0; z < 2; z++) {\n\t\t\tSWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);\n\t\t\tSWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);\n\t\t\tSWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);\n\t\t\tOP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);\n\t\t\tVOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);\n\t\t}\n\n\t\tsnd_emu10k1_init_stereo_control(controls + i++, \"Headphone Playback Volume\", gpr + 0, 0);\n\t\tcontrols[i-1].id.index = 1;\t/* AC'97 can have also Headphone control */\n\t\tsnd_emu10k1_init_mono_onoff_control(controls + i++, \"Headphone Center Playback Switch\", gpr + 2, 0);\n\t\tcontrols[i-1].id.index = 1;\n\t\tsnd_emu10k1_init_mono_onoff_control(controls + i++, \"Headphone LFE Playback Switch\", gpr + 3, 0);\n\t\tcontrols[i-1].id.index = 1;\n\n\t\tgpr += 4;\n\t}\n\t\n\tif (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);\n\n\tif (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))\n\t\tfor (z = 0; z < 2; z++)\n\t\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);\n\n\tif (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {\n#ifndef EMU10K1_CENTER_LFE_FROM_FRONT\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);\n#else\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);\n#endif\n\t}\n\n\tif (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {\n#ifndef EMU10K1_CENTER_LFE_FROM_FRONT\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);\n#else\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);\n#endif\n\t}\n\t\n#ifndef EMU10K1_CAPTURE_DIGITAL_OUT\n\tfor (z = 0; z < 2; z++)\n \t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);\n#endif\n\t\n\tif (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))\n\t\tOP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);\n\n\t/* EFX capture - capture the 16 EXTINS */\n\tif (emu->card_capabilities->sblive51) {\n\t\t/* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER\n\t\t * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.\n\t\t *\n\t\t * Since only 14 of the 16 EXTINs are used, this is not a big problem.  \n\t\t * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture \n\t\t * 0 and 3, then the rest of the EXTINs to the corresponding FX capture \n\t\t * channel.  Multitrack recorders will still see the center/lfe output signal \n\t\t * on the second and third channels.\n\t\t */\n\t\tOP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));\n\t\tOP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));\n\t\tOP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));\n\t\tOP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));\n\t\tfor (z = 4; z < 14; z++)\n\t\t\tOP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));\n\t} else {\n\t\tfor (z = 0; z < 16; z++)\n\t\t\tOP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));\n\t}\n\t    \n\n\tif (gpr > tmp) {\n\t\tsnd_BUG();\n\t\terr = -EIO;\n\t\tgoto __err;\n\t}\n\tif (i > SND_EMU10K1_GPR_CONTROLS) {\n\t\tsnd_BUG();\n\t\terr = -EIO;\n\t\tgoto __err;\n\t}\n\t\n\t/* clear remaining instruction memory */\n\twhile (ptr < 0x200)\n\t\tOP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);\n\n\terr = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size);\n\tif (err < 0)\n\t\tgoto __err;\n\ticode->gpr_add_control_count = i;\n\ticode->gpr_add_controls = controls;\n\temu->support_tlv = 1; /* support TLV */\n\terr = snd_emu10k1_icode_poke(emu, icode, true);\n\temu->support_tlv = 0; /* clear again */\n\tif (err >= 0)\n\t\terr = snd_emu10k1_ipcm_poke(emu, ipcm);\n__err:\n\tkfree(ipcm);\n__err_ipcm:\n\tkfree(controls);\n__err_ctrls:\n\tkfree(icode->gpr_map);\n__err_gpr:\n\tkfree(icode);\n\treturn err;\n}",
        "static void gdb_cmd_break(struct kgdb_state *ks)\n{\n\t/*\n\t * Since GDB-5.3, it's been drafted that '0' is a software\n\t * breakpoint, '1' is a hardware breakpoint, so let's do that.": "static void gdb_cmd_break(struct kgdb_state *ks)\n{\n\t/*\n\t * Since GDB-5.3, it's been drafted that '0' is a software\n\t * breakpoint, '1' is a hardware breakpoint, so let's do that.\n\t */\n\tchar *bpt_type = &remcom_in_buffer[1];\n\tchar *ptr = &remcom_in_buffer[2];\n\tunsigned long addr;\n\tunsigned long length;\n\tint error = 0;\n\n\tif (arch_kgdb_ops.set_hw_breakpoint && *bpt_type >= '1') {\n\t\t/* Unsupported */\n\t\tif (*bpt_type > '4')\n\t\t\treturn;\n\t} else {\n\t\tif (*bpt_type != '0' && *bpt_type != '1')\n\t\t\t/* Unsupported. */\n\t\t\treturn;\n\t}\n\n\t/*\n\t * Test if this is a hardware breakpoint, and\n\t * if we support it:\n\t */\n\tif (*bpt_type == '1' && !(arch_kgdb_ops.flags & KGDB_HW_BREAKPOINT))\n\t\t/* Unsupported. */\n\t\treturn;\n\n\tif (*(ptr++) != ',') {\n\t\terror_packet(remcom_out_buffer, -EINVAL);\n\t\treturn;\n\t}\n\tif (!kgdb_hex2long(&ptr, &addr)) {\n\t\terror_packet(remcom_out_buffer, -EINVAL);\n\t\treturn;\n\t}\n\tif (*(ptr++) != ',' ||\n\t\t!kgdb_hex2long(&ptr, &length)) {\n\t\terror_packet(remcom_out_buffer, -EINVAL);\n\t\treturn;\n\t}\n\n\tif (remcom_in_buffer[0] == 'Z' && *bpt_type == '0')\n\t\terror = dbg_set_sw_break(addr);\n\telse if (remcom_in_buffer[0] == 'z' && *bpt_type == '0')\n\t\terror = dbg_remove_sw_break(addr);\n\telse if (remcom_in_buffer[0] == 'Z')\n\t\terror = arch_kgdb_ops.set_hw_breakpoint(addr,\n\t\t\t(int)length, *bpt_type - '0');\n\telse if (remcom_in_buffer[0] == 'z')\n\t\terror = arch_kgdb_ops.remove_hw_breakpoint(addr,\n\t\t\t(int) length, *bpt_type - '0');\n\n\tif (error == 0)\n\t\tstrcpy(remcom_out_buffer, \"OK\");\n\telse\n\t\terror_packet(remcom_out_buffer, error);\n}",
        "static int virtio_mem_fake_offline(unsigned long pfn, unsigned long nr_pages)\n{\n\tconst bool is_movable = page_zonenum(pfn_to_page(pfn)) ==\n\t\t\t\tZONE_MOVABLE;\n\tint rc, retry_count;": "static int virtio_mem_fake_offline(unsigned long pfn, unsigned long nr_pages)\n{\n\tconst bool is_movable = page_zonenum(pfn_to_page(pfn)) ==\n\t\t\t\tZONE_MOVABLE;\n\tint rc, retry_count;\n\n\t/*\n\t * TODO: We want an alloc_contig_range() mode that tries to allocate\n\t * harder (e.g., dealing with temporarily pinned pages, PCP), especially\n\t * with ZONE_MOVABLE. So for now, retry a couple of times with\n\t * ZONE_MOVABLE before giving up - because that zone is supposed to give\n\t * some guarantees.\n\t */\n\tfor (retry_count = 0; retry_count < 5; retry_count++) {\n\t\trc = alloc_contig_range(pfn, pfn + nr_pages, MIGRATE_MOVABLE,\n\t\t\t\t\tGFP_KERNEL);\n\t\tif (rc == -ENOMEM)\n\t\t\t/* whoops, out of memory */\n\t\t\treturn rc;\n\t\telse if (rc && !is_movable)\n\t\t\tbreak;\n\t\telse if (rc)\n\t\t\tcontinue;\n\n\t\tvirtio_mem_set_fake_offline(pfn, nr_pages, true);\n\t\tadjust_managed_page_count(pfn_to_page(pfn), -nr_pages);\n\t\treturn 0;\n\t}\n\n\treturn -EBUSY;\n}",
        "static void kasan_strings(struct kunit *test)\n{\n\tchar *ptr;\n\tsize_t size = 24;\n": "static void kasan_strings(struct kunit *test)\n{\n\tchar *ptr;\n\tsize_t size = 24;\n\n\t/*\n\t * str* functions are not instrumented with CONFIG_AMD_MEM_ENCRYPT.\n\t * See https://bugzilla.kernel.org/show_bug.cgi?id=206337 for details.\n\t */\n\tKASAN_TEST_NEEDS_CONFIG_OFF(test, CONFIG_AMD_MEM_ENCRYPT);\n\n\tptr = kmalloc(size, GFP_KERNEL | __GFP_ZERO);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);\n\n\tkfree(ptr);\n\n\t/*\n\t * Try to cause only 1 invalid access (less spam in dmesg).\n\t * For that we need ptr to point to zeroed byte.\n\t * Skip metadata that could be stored in freed object so ptr\n\t * will likely point to zeroed byte.\n\t */\n\tptr += 16;\n\tKUNIT_EXPECT_KASAN_FAIL(test, kasan_ptr_result = strchr(ptr, '1'));\n\n\tKUNIT_EXPECT_KASAN_FAIL(test, kasan_ptr_result = strrchr(ptr, '1'));\n\n\tKUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result = strcmp(ptr, \"2\"));\n\n\tKUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result = strncmp(ptr, \"2\", 1));\n\n\tKUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result = strlen(ptr));\n\n\tKUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result = strnlen(ptr, 1));\n}",
        "static enum hrtimer_restart bcm_rx_timeout_handler(struct hrtimer *hrtimer)\n{\n\tstruct bcm_op *op = container_of(hrtimer, struct bcm_op, timer);\n\tstruct bcm_msg_head msg_head;\n": "static enum hrtimer_restart bcm_rx_timeout_handler(struct hrtimer *hrtimer)\n{\n\tstruct bcm_op *op = container_of(hrtimer, struct bcm_op, timer);\n\tstruct bcm_msg_head msg_head;\n\n\t/* if user wants to be informed, when cyclic CAN-Messages come back */\n\tif ((op->flags & RX_ANNOUNCE_RESUME) && op->last_frames) {\n\t\t/* clear received CAN frames to indicate 'nothing received' */\n\t\tmemset(op->last_frames, 0, op->nframes * op->cfsiz);\n\t}\n\n\t/* create notification to user */\n\tmemset(&msg_head, 0, sizeof(msg_head));\n\tmsg_head.opcode  = RX_TIMEOUT;\n\tmsg_head.flags   = op->flags;\n\tmsg_head.count   = op->count;\n\tmsg_head.ival1   = op->ival1;\n\tmsg_head.ival2   = op->ival2;\n\tmsg_head.can_id  = op->can_id;\n\tmsg_head.nframes = 0;\n\n\tbcm_send_to_user(op, &msg_head, NULL, 0);\n\n\treturn HRTIMER_NORESTART;\n}",
        "static void ipa_table_validate_build(void)\n{\n\t/* Filter and route tables contain DMA addresses that refer\n\t * to filter or route rules.  But the size of a table entry\n\t * is 64 bits regardless of what the size of an AP DMA address": "static void ipa_table_validate_build(void)\n{\n\t/* Filter and route tables contain DMA addresses that refer\n\t * to filter or route rules.  But the size of a table entry\n\t * is 64 bits regardless of what the size of an AP DMA address\n\t * is.  A fixed constant defines the size of an entry, and\n\t * code in ipa_table_init() uses a pointer to __le64 to\n\t * initialize tables.\n\t */\n\tBUILD_BUG_ON(sizeof(dma_addr_t) > sizeof(__le64));\n\n\t/* A \"zero rule\" is used to represent no filtering or no routing.\n\t * It is a 64-bit block of zeroed memory.  Code in ipa_table_init()\n\t * assumes that it can be written using a pointer to __le64.\n\t */\n\tBUILD_BUG_ON(IPA_ZERO_RULE_SIZE != sizeof(__le64));\n\n\t/* Impose a practical limit on the number of routes */\n\tBUILD_BUG_ON(IPA_ROUTE_COUNT_MAX > 32);\n\t/* The modem must be allotted at least one route table entry */\n\tBUILD_BUG_ON(!IPA_ROUTE_MODEM_COUNT);\n\t/* But it can't have more than what is available */\n\tBUILD_BUG_ON(IPA_ROUTE_MODEM_COUNT > IPA_ROUTE_COUNT_MAX);\n\n}",
        "static int tc358743_log_status(struct v4l2_subdev *sd)\n{\n\tstruct tc358743_state *state = to_state(sd);\n\tstruct v4l2_dv_timings timings;\n\tuint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);": "static int tc358743_log_status(struct v4l2_subdev *sd)\n{\n\tstruct tc358743_state *state = to_state(sd);\n\tstruct v4l2_dv_timings timings;\n\tuint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);\n\tuint16_t sysctl = i2c_rd16(sd, SYSCTL);\n\tu8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);\n\tconst int deep_color_mode[4] = { 8, 10, 12, 16 };\n\tstatic const char * const input_color_space[] = {\n\t\t\"RGB\", \"YCbCr 601\", \"opRGB\", \"YCbCr 709\", \"NA (4)\",\n\t\t\"xvYCC 601\", \"NA(6)\", \"xvYCC 709\", \"NA(8)\", \"sYCC601\",\n\t\t\"NA(10)\", \"NA(11)\", \"NA(12)\", \"opYCC 601\"};\n\n\tv4l2_info(sd, \"-----Chip status-----\\n\");\n\tv4l2_info(sd, \"Chip ID: 0x%02x\\n\",\n\t\t\t(i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);\n\tv4l2_info(sd, \"Chip revision: 0x%02x\\n\",\n\t\t\ti2c_rd16(sd, CHIPID) & MASK_REVID);\n\tv4l2_info(sd, \"Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\\n\",\n\t\t\t!!(sysctl & MASK_IRRST),\n\t\t\t!!(sysctl & MASK_CECRST),\n\t\t\t!!(sysctl & MASK_CTXRST),\n\t\t\t!!(sysctl & MASK_HDMIRST));\n\tv4l2_info(sd, \"Sleep mode: %s\\n\", sysctl & MASK_SLEEP ? \"on\" : \"off\");\n\tv4l2_info(sd, \"Cable detected (+5V power): %s\\n\",\n\t\t\thdmi_sys_status & MASK_S_DDC5V ? \"yes\" : \"no\");\n\tv4l2_info(sd, \"DDC lines enabled: %s\\n\",\n\t\t\t(i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?\n\t\t\t\"yes\" : \"no\");\n\tv4l2_info(sd, \"Hotplug enabled: %s\\n\",\n\t\t\t(i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?\n\t\t\t\"yes\" : \"no\");\n\tv4l2_info(sd, \"CEC enabled: %s\\n\",\n\t\t\t(i2c_rd16(sd, CECEN) & MASK_CECEN) ?  \"yes\" : \"no\");\n\tv4l2_info(sd, \"-----Signal status-----\\n\");\n\tv4l2_info(sd, \"TMDS signal detected: %s\\n\",\n\t\t\thdmi_sys_status & MASK_S_TMDS ? \"yes\" : \"no\");\n\tv4l2_info(sd, \"Stable sync signal: %s\\n\",\n\t\t\thdmi_sys_status & MASK_S_SYNC ? \"yes\" : \"no\");\n\tv4l2_info(sd, \"PHY PLL locked: %s\\n\",\n\t\t\thdmi_sys_status & MASK_S_PHY_PLL ? \"yes\" : \"no\");\n\tv4l2_info(sd, \"PHY DE detected: %s\\n\",\n\t\t\thdmi_sys_status & MASK_S_PHY_SCDT ? \"yes\" : \"no\");\n\n\tif (tc358743_get_detected_timings(sd, &timings)) {\n\t\tv4l2_info(sd, \"No video detected\\n\");\n\t} else {\n\t\tv4l2_print_dv_timings(sd->name, \"Detected format: \", &timings,\n\t\t\t\ttrue);\n\t}\n\tv4l2_print_dv_timings(sd->name, \"Configured format: \", &state->timings,\n\t\t\ttrue);\n\n\tv4l2_info(sd, \"-----CSI-TX status-----\\n\");\n\tv4l2_info(sd, \"Lanes needed: %d\\n\",\n\t\t\ttc358743_num_csi_lanes_needed(sd));\n\tv4l2_info(sd, \"Lanes in use: %d\\n\",\n\t\t\tstate->csi_lanes_in_use);\n\tv4l2_info(sd, \"Waiting for particular sync signal: %s\\n\",\n\t\t\t(i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?\n\t\t\t\"yes\" : \"no\");\n\tv4l2_info(sd, \"Transmit mode: %s\\n\",\n\t\t\t(i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?\n\t\t\t\"yes\" : \"no\");\n\tv4l2_info(sd, \"Receive mode: %s\\n\",\n\t\t\t(i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?\n\t\t\t\"yes\" : \"no\");\n\tv4l2_info(sd, \"Stopped: %s\\n\",\n\t\t\t(i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?\n\t\t\t\"yes\" : \"no\");\n\tv4l2_info(sd, \"Color space: %s\\n\",\n\t\t\tstate->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?\n\t\t\t\"YCbCr 422 16-bit\" :\n\t\t\tstate->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?\n\t\t\t\"RGB 888 24-bit\" : \"Unsupported\");\n\n\tv4l2_info(sd, \"-----%s status-----\\n\", is_hdmi(sd) ? \"HDMI\" : \"DVI-D\");\n\tv4l2_info(sd, \"HDCP encrypted content: %s\\n\",\n\t\t\thdmi_sys_status & MASK_S_HDCP ? \"yes\" : \"no\");\n\tv4l2_info(sd, \"Input color space: %s %s range\\n\",\n\t\t\tinput_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],\n\t\t\t(vi_status3 & MASK_LIMITED) ? \"limited\" : \"full\");\n\tif (!is_hdmi(sd))\n\t\treturn 0;\n\tv4l2_info(sd, \"AV Mute: %s\\n\", hdmi_sys_status & MASK_S_AVMUTE ? \"on\" :\n\t\t\t\"off\");\n\tv4l2_info(sd, \"Deep color mode: %d-bits per channel\\n\",\n\t\t\tdeep_color_mode[(i2c_rd8(sd, VI_STATUS1) &\n\t\t\t\tMASK_S_DEEPCOLOR) >> 2]);\n\tprint_avi_infoframe(sd);\n\n\treturn 0;\n}",
        "static int tsl2772_chip_on(struct iio_dev *indio_dev)\n{\n\tstruct tsl2772_chip *chip = iio_priv(indio_dev);\n\tint ret, i, als_count, als_time_us;\n\tu8 *dev_reg, reg_val;": "static int tsl2772_chip_on(struct iio_dev *indio_dev)\n{\n\tstruct tsl2772_chip *chip = iio_priv(indio_dev);\n\tint ret, i, als_count, als_time_us;\n\tu8 *dev_reg, reg_val;\n\n\t/* Non calculated parameters */\n\tchip->tsl2772_config[TSL2772_ALS_TIME] = chip->settings.als_time;\n\tchip->tsl2772_config[TSL2772_PRX_TIME] = chip->settings.prox_time;\n\tchip->tsl2772_config[TSL2772_WAIT_TIME] = chip->settings.wait_time;\n\tchip->tsl2772_config[TSL2772_ALS_PRX_CONFIG] =\n\t\tchip->settings.als_prox_config;\n\n\tchip->tsl2772_config[TSL2772_ALS_MINTHRESHLO] =\n\t\t(chip->settings.als_thresh_low) & 0xFF;\n\tchip->tsl2772_config[TSL2772_ALS_MINTHRESHHI] =\n\t\t(chip->settings.als_thresh_low >> 8) & 0xFF;\n\tchip->tsl2772_config[TSL2772_ALS_MAXTHRESHLO] =\n\t\t(chip->settings.als_thresh_high) & 0xFF;\n\tchip->tsl2772_config[TSL2772_ALS_MAXTHRESHHI] =\n\t\t(chip->settings.als_thresh_high >> 8) & 0xFF;\n\tchip->tsl2772_config[TSL2772_PERSISTENCE] =\n\t\t(chip->settings.prox_persistence & 0xFF) << 4 |\n\t\t(chip->settings.als_persistence & 0xFF);\n\n\tchip->tsl2772_config[TSL2772_PRX_COUNT] =\n\t\t\tchip->settings.prox_pulse_count;\n\tchip->tsl2772_config[TSL2772_PRX_MINTHRESHLO] =\n\t\t\t(chip->settings.prox_thres_low) & 0xFF;\n\tchip->tsl2772_config[TSL2772_PRX_MINTHRESHHI] =\n\t\t\t(chip->settings.prox_thres_low >> 8) & 0xFF;\n\tchip->tsl2772_config[TSL2772_PRX_MAXTHRESHLO] =\n\t\t\t(chip->settings.prox_thres_high) & 0xFF;\n\tchip->tsl2772_config[TSL2772_PRX_MAXTHRESHHI] =\n\t\t\t(chip->settings.prox_thres_high >> 8) & 0xFF;\n\n\t/* and make sure we're not already on */\n\tif (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {\n\t\t/* if forcing a register update - turn off, then on */\n\t\tdev_info(&chip->client->dev, \"device is already enabled\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Set the gain based on tsl2772_settings struct */\n\tchip->tsl2772_config[TSL2772_GAIN] =\n\t\t(chip->settings.als_gain & 0xFF) |\n\t\t((chip->settings.prox_gain & 0xFF) << 2) |\n\t\t(chip->settings.prox_diode << 4) |\n\t\t(chip->settings.prox_power << 6);\n\n\t/* set chip time scaling and saturation */\n\tals_count = 256 - chip->settings.als_time;\n\tals_time_us = als_count * tsl2772_int_time_avail[chip->id][3];\n\tchip->als_saturation = als_count * 768; /* 75% of full scale */\n\tchip->als_gain_time_scale = als_time_us *\n\t\ttsl2772_als_gain[chip->settings.als_gain];\n\n\t/*\n\t * TSL2772 Specific power-on / adc enable sequence\n\t * Power on the device 1st.\n\t */\n\tret = tsl2772_write_control_reg(chip, TSL2772_CNTL_PWR_ON);\n\tif (ret < 0)\n\t\treturn ret;\n\n\t/*\n\t * Use the following shadow copy for our delay before enabling ADC.\n\t * Write all the registers.\n\t */\n\tfor (i = 0, dev_reg = chip->tsl2772_config;\n\t\t\ti < TSL2772_MAX_CONFIG_REG; i++) {\n\t\tint reg = TSL2772_CMD_REG + i;\n\n\t\tret = i2c_smbus_write_byte_data(chip->client, reg,\n\t\t\t\t\t\t*dev_reg++);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&chip->client->dev,\n\t\t\t\t\"%s: failed to write to register %x: %d\\n\",\n\t\t\t\t__func__, reg, ret);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\t/* Power-on settling time */\n\tusleep_range(3000, 3500);\n\n\treg_val = TSL2772_CNTL_PWR_ON | TSL2772_CNTL_ADC_ENBL |\n\t\t  TSL2772_CNTL_PROX_DET_ENBL;\n\tif (chip->settings.als_interrupt_en)\n\t\treg_val |= TSL2772_CNTL_ALS_INT_ENBL;\n\tif (chip->settings.prox_interrupt_en)\n\t\treg_val |= TSL2772_CNTL_PROX_INT_ENBL;\n\n\tret = tsl2772_write_control_reg(chip, reg_val);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tret = i2c_smbus_write_byte(chip->client,\n\t\t\t\t   TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |\n\t\t\t\t   TSL2772_CMD_PROXALS_INT_CLR);\n\tif (ret < 0) {\n\t\tdev_err(&chip->client->dev,\n\t\t\t\"%s: failed to clear interrupt status: %d\\n\",\n\t\t\t__func__, ret);\n\t\treturn ret;\n\t}\n\n\tchip->tsl2772_chip_status = TSL2772_CHIP_WORKING;\n\n\treturn ret;\n}",
        "static void program_capture_engine(struct saa7146_dev *dev, int planar)\n{\n\tstruct saa7146_vv *vv = dev->vv_data;\n\tint count = 0;\n": "static void program_capture_engine(struct saa7146_dev *dev, int planar)\n{\n\tstruct saa7146_vv *vv = dev->vv_data;\n\tint count = 0;\n\n\tunsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;\n\tunsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;\n\n\t/* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/\n\tWRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait);\n\tWRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait);\n\n\t/* set rps register 0 */\n\tWRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));\n\tWRITE_RPS0(MASK_27 | MASK_11);\n\n\t/* turn on video-dma1 */\n\tWRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));\n\tWRITE_RPS0(MASK_06 | MASK_22);\t\t\t/* => mask */\n\tWRITE_RPS0(MASK_06 | MASK_22);\t\t\t/* => values */\n\tif( 0 != planar ) {\n\t\t/* turn on video-dma2 */\n\t\tWRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));\n\t\tWRITE_RPS0(MASK_05 | MASK_21);\t\t\t/* => mask */\n\t\tWRITE_RPS0(MASK_05 | MASK_21);\t\t\t/* => values */\n\n\t\t/* turn on video-dma3 */\n\t\tWRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));\n\t\tWRITE_RPS0(MASK_04 | MASK_20);\t\t\t/* => mask */\n\t\tWRITE_RPS0(MASK_04 | MASK_20);\t\t\t/* => values */\n\t}\n\n\t/* wait for o_fid_a/b / e_fid_a/b toggle */\n\tif ( vv->last_field == V4L2_FIELD_INTERLACED ) {\n\t\tWRITE_RPS0(CMD_PAUSE | o_wait);\n\t\tWRITE_RPS0(CMD_PAUSE | e_wait);\n\t} else if ( vv->last_field == V4L2_FIELD_TOP ) {\n\t\tWRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));\n\t\tWRITE_RPS0(CMD_PAUSE | o_wait);\n\t} else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {\n\t\tWRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));\n\t\tWRITE_RPS0(CMD_PAUSE | e_wait);\n\t}\n\n\t/* turn off video-dma1 */\n\tWRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));\n\tWRITE_RPS0(MASK_22 | MASK_06);\t\t\t/* => mask */\n\tWRITE_RPS0(MASK_22);\t\t\t\t/* => values */\n\tif( 0 != planar ) {\n\t\t/* turn off video-dma2 */\n\t\tWRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));\n\t\tWRITE_RPS0(MASK_05 | MASK_21);\t\t\t/* => mask */\n\t\tWRITE_RPS0(MASK_21);\t\t\t\t/* => values */\n\n\t\t/* turn off video-dma3 */\n\t\tWRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));\n\t\tWRITE_RPS0(MASK_04 | MASK_20);\t\t\t/* => mask */\n\t\tWRITE_RPS0(MASK_20);\t\t\t\t/* => values */\n\t}\n\n\t/* generate interrupt */\n\tWRITE_RPS0(CMD_INTERRUPT);\n\n\t/* stop */\n\tWRITE_RPS0(CMD_STOP);\n}",
        "static void test_tailcall_bpf2bpf_4(bool noise)\n{\n\tint err, map_fd, prog_fd, main_fd, data_fd, i;\n\tstruct tailcall_bpf2bpf4__bss val;\n\tstruct bpf_map *prog_array, *data_map;": "static void test_tailcall_bpf2bpf_4(bool noise)\n{\n\tint err, map_fd, prog_fd, main_fd, data_fd, i;\n\tstruct tailcall_bpf2bpf4__bss val;\n\tstruct bpf_map *prog_array, *data_map;\n\tstruct bpf_program *prog;\n\tstruct bpf_object *obj;\n\tchar prog_name[32];\n\tLIBBPF_OPTS(bpf_test_run_opts, topts,\n\t\t.data_in = &pkt_v4,\n\t\t.data_size_in = sizeof(pkt_v4),\n\t\t.repeat = 1,\n\t);\n\n\terr = bpf_prog_test_load(\"tailcall_bpf2bpf4.o\", BPF_PROG_TYPE_SCHED_CLS,\n\t\t\t    &obj, &prog_fd);\n\tif (CHECK_FAIL(err))\n\t\treturn;\n\n\tprog = bpf_object__find_program_by_name(obj, \"entry\");\n\tif (CHECK_FAIL(!prog))\n\t\tgoto out;\n\n\tmain_fd = bpf_program__fd(prog);\n\tif (CHECK_FAIL(main_fd < 0))\n\t\tgoto out;\n\n\tprog_array = bpf_object__find_map_by_name(obj, \"jmp_table\");\n\tif (CHECK_FAIL(!prog_array))\n\t\tgoto out;\n\n\tmap_fd = bpf_map__fd(prog_array);\n\tif (CHECK_FAIL(map_fd < 0))\n\t\tgoto out;\n\n\tfor (i = 0; i < bpf_map__max_entries(prog_array); i++) {\n\t\tsnprintf(prog_name, sizeof(prog_name), \"classifier_%d\", i);\n\n\t\tprog = bpf_object__find_program_by_name(obj, prog_name);\n\t\tif (CHECK_FAIL(!prog))\n\t\t\tgoto out;\n\n\t\tprog_fd = bpf_program__fd(prog);\n\t\tif (CHECK_FAIL(prog_fd < 0))\n\t\t\tgoto out;\n\n\t\terr = bpf_map_update_elem(map_fd, &i, &prog_fd, BPF_ANY);\n\t\tif (CHECK_FAIL(err))\n\t\t\tgoto out;\n\t}\n\n\tdata_map = bpf_object__find_map_by_name(obj, \"tailcall.bss\");\n\tif (CHECK_FAIL(!data_map || !bpf_map__is_internal(data_map)))\n\t\treturn;\n\n\tdata_fd = bpf_map__fd(data_map);\n\tif (CHECK_FAIL(map_fd < 0))\n\t\treturn;\n\n\ti = 0;\n\tval.noise = noise;\n\tval.count = 0;\n\terr = bpf_map_update_elem(data_fd, &i, &val, BPF_ANY);\n\tif (CHECK_FAIL(err))\n\t\tgoto out;\n\n\terr = bpf_prog_test_run_opts(main_fd, &topts);\n\tASSERT_OK(err, \"tailcall\");\n\tASSERT_EQ(topts.retval, sizeof(pkt_v4) * 3, \"tailcall retval\");\n\n\ti = 0;\n\terr = bpf_map_lookup_elem(data_fd, &i, &val);\n\tASSERT_OK(err, \"tailcall count\");\n\tASSERT_EQ(val.count, 31, \"tailcall count\");\n\nout:\n\tbpf_object__close(obj);\n}",
        "static int io_timeout_remove(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_timeout_rem *tr = &req->timeout_rem;\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tint ret;": "static int io_timeout_remove(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_timeout_rem *tr = &req->timeout_rem;\n\tstruct io_ring_ctx *ctx = req->ctx;\n\tint ret;\n\n\tif (!(req->timeout_rem.flags & IORING_TIMEOUT_UPDATE)) {\n\t\tstruct io_cancel_data cd = { .data = tr->addr, };\n\n\t\tspin_lock(&ctx->completion_lock);\n\t\tret = io_timeout_cancel(ctx, &cd);\n\t\tspin_unlock(&ctx->completion_lock);\n\t} else {\n\t\tenum hrtimer_mode mode = io_translate_timeout_mode(tr->flags);\n\n\t\tspin_lock_irq(&ctx->timeout_lock);\n\t\tif (tr->ltimeout)\n\t\t\tret = io_linked_timeout_update(ctx, tr->addr, &tr->ts, mode);\n\t\telse\n\t\t\tret = io_timeout_update(ctx, tr->addr, &tr->ts, mode);\n\t\tspin_unlock_irq(&ctx->timeout_lock);\n\t}\n\n\tif (ret < 0)\n\t\treq_set_fail(req);\n\tio_req_complete_post(req, ret, 0);\n\treturn 0;\n}",
        "static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)\n{\n\tif (dev->cpu_id == AMD_CPU_ID_PCO) {\n\t\tdev_warn_once(dev->dev, \"SMU debugging info not supported on this platform\\n\");\n\t\treturn -EINVAL;": "static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)\n{\n\tif (dev->cpu_id == AMD_CPU_ID_PCO) {\n\t\tdev_warn_once(dev->dev, \"SMU debugging info not supported on this platform\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Get Active devices list from SMU */\n\tif (!dev->active_ips)\n\t\tamd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);\n\n\t/* Get dram address */\n\tif (!dev->smu_virt_addr) {\n\t\tu32 phys_addr_low, phys_addr_hi;\n\t\tu64 smu_phys_addr;\n\n\t\tamd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);\n\t\tamd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);\n\t\tsmu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);\n\n\t\tdev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,\n\t\t\t\t\t\t  sizeof(struct smu_metrics));\n\t\tif (!dev->smu_virt_addr)\n\t\t\treturn -ENOMEM;\n\t}\n\n\t/* Start the logging */\n\tamd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);\n\tamd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);\n\n\treturn 0;\n}",
        "static void llc_shdlc_rcv_rej(struct llc_shdlc *shdlc, int y_nr)\n{\n\tstruct sk_buff *skb;\n\n\tpr_debug(\"remote asks retransmission from frame %d\\n\", y_nr);": "static void llc_shdlc_rcv_rej(struct llc_shdlc *shdlc, int y_nr)\n{\n\tstruct sk_buff *skb;\n\n\tpr_debug(\"remote asks retransmission from frame %d\\n\", y_nr);\n\n\tif (llc_shdlc_x_lteq_y_lt_z(shdlc->dnr, y_nr, shdlc->ns)) {\n\t\tif (shdlc->t2_active) {\n\t\t\tdel_timer_sync(&shdlc->t2_timer);\n\t\t\tshdlc->t2_active = false;\n\t\t\tpr_debug(\"Stopped T2(retransmit)\\n\");\n\t\t}\n\n\t\tif (shdlc->dnr != y_nr) {\n\t\t\twhile ((shdlc->dnr = ((shdlc->dnr + 1) % 8)) != y_nr) {\n\t\t\t\tskb = skb_dequeue(&shdlc->ack_pending_q);\n\t\t\t\tkfree_skb(skb);\n\t\t\t}\n\t\t}\n\n\t\tllc_shdlc_requeue_ack_pending(shdlc);\n\t}\n}",
        "static int alloc_try_nid_bottom_up_narrow_range_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_bottom_up_narrow_range_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t size = SZ_256;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmin_addr = memblock_start_of_DRAM() + SZ_512;\n\tmax_addr = min_addr + SMP_CACHE_BYTES;\n\n\tallocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr,\n\t\t\t\t\t       NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == size);\n\tassert(rgn->base == memblock_start_of_DRAM());\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == size);\n\n\treturn 0;\n}",
        "static int hpre_show_last_regs_init(struct hisi_qm *qm)\n{\n\tint cluster_dfx_regs_num =  ARRAY_SIZE(hpre_cluster_dfx_regs);\n\tint com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);\n\tu8 clusters_num = hpre_cluster_num(qm);": "static int hpre_show_last_regs_init(struct hisi_qm *qm)\n{\n\tint cluster_dfx_regs_num =  ARRAY_SIZE(hpre_cluster_dfx_regs);\n\tint com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);\n\tu8 clusters_num = hpre_cluster_num(qm);\n\tstruct qm_debug *debug = &qm->debug;\n\tvoid __iomem *io_base;\n\tint i, j, idx;\n\n\tdebug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +\n\t\t\tcom_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);\n\tif (!debug->last_words)\n\t\treturn -ENOMEM;\n\n\tfor (i = 0; i < com_dfx_regs_num; i++)\n\t\tdebug->last_words[i] = readl_relaxed(qm->io_base +\n\t\t\t\t\t\thpre_com_dfx_regs[i].offset);\n\n\tfor (i = 0; i < clusters_num; i++) {\n\t\tio_base = qm->io_base + hpre_cluster_offsets[i];\n\t\tfor (j = 0; j < cluster_dfx_regs_num; j++) {\n\t\t\tidx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;\n\t\t\tdebug->last_words[idx] = readl_relaxed(\n\t\t\t\tio_base + hpre_cluster_dfx_regs[j].offset);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static inline void ti_abb_clear_txdone(const struct ti_abb *abb)\n{\n\twritel(abb->txdone_mask, abb->int_base);\n};\n": "static inline void ti_abb_clear_txdone(const struct ti_abb *abb)\n{\n\twritel(abb->txdone_mask, abb->int_base);\n};\n\n/**\n * ti_abb_wait_tranx() - waits for ABB tranxdone event\n * @dev:\tdevice\n * @abb:\tpointer to the abb instance\n *\n * Return: 0 on success or -ETIMEDOUT if the event is not cleared on time.\n */\nstatic int ti_abb_wait_txdone(struct device *dev, struct ti_abb *abb)\n{\n\tint timeout = 0;\n\tbool status;\n\n\twhile (timeout++ <= abb->settling_time) {\n\t\tstatus = ti_abb_check_txdone(abb);\n\t\tif (status)\n\t\t\treturn 0;\n\n\t\tudelay(1);\n\t}\n\n\tdev_warn_ratelimited(dev, \"%s:TRANXDONE timeout(%duS) int=0x%08x\\n\",\n\t\t\t     __func__, timeout, readl(abb->int_base));\n\treturn -ETIMEDOUT;\n}",
        "static bool send_waiting_write(struct sock *sk, u64 room_needed)\n{\n#if defined(VSOCK_OPTIMIZATION_WAITING_NOTIFY)\n\tstruct vsock_sock *vsk;\n\tstruct vmci_transport_waiting_info waiting_info;": "static bool send_waiting_write(struct sock *sk, u64 room_needed)\n{\n#if defined(VSOCK_OPTIMIZATION_WAITING_NOTIFY)\n\tstruct vsock_sock *vsk;\n\tstruct vmci_transport_waiting_info waiting_info;\n\tu64 tail;\n\tu64 head;\n\tu64 room_left;\n\tbool ret;\n\n\tvsk = vsock_sk(sk);\n\n\tif (PKT_FIELD(vsk, sent_waiting_write))\n\t\treturn true;\n\n\tvmci_qpair_get_produce_indexes(vmci_trans(vsk)->qpair, &tail, &head);\n\troom_left = vmci_trans(vsk)->produce_size - tail;\n\tif (room_needed + 1 >= room_left) {\n\t\t/* Wraps around to current generation. */\n\t\twaiting_info.offset = room_needed + 1 - room_left;\n\t\twaiting_info.generation = PKT_FIELD(vsk, produce_q_generation);\n\t} else {\n\t\twaiting_info.offset = tail + room_needed + 1;\n\t\twaiting_info.generation =\n\t\t    PKT_FIELD(vsk, produce_q_generation) - 1;\n\t}\n\n\tret = vmci_transport_send_waiting_write(sk, &waiting_info) > 0;\n\tif (ret)\n\t\tPKT_FIELD(vsk, sent_waiting_write) = true;\n\n\treturn ret;\n#else\n\treturn true;\n#endif\n}",
        "static struct tls_rec *tls_get_rec(struct sock *sk)\n{\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tstruct tls_sw_context_tx *ctx = tls_sw_ctx_tx(tls_ctx);": "static struct tls_rec *tls_get_rec(struct sock *sk)\n{\n\tstruct tls_context *tls_ctx = tls_get_ctx(sk);\n\tstruct tls_prot_info *prot = &tls_ctx->prot_info;\n\tstruct tls_sw_context_tx *ctx = tls_sw_ctx_tx(tls_ctx);\n\tstruct sk_msg *msg_pl, *msg_en;\n\tstruct tls_rec *rec;\n\tint mem_size;\n\n\tmem_size = sizeof(struct tls_rec) + crypto_aead_reqsize(ctx->aead_send);\n\n\trec = kzalloc(mem_size, sk->sk_allocation);\n\tif (!rec)\n\t\treturn NULL;\n\n\tmsg_pl = &rec->msg_plaintext;\n\tmsg_en = &rec->msg_encrypted;\n\n\tsk_msg_init(msg_pl);\n\tsk_msg_init(msg_en);\n\n\tsg_init_table(rec->sg_aead_in, 2);\n\tsg_set_buf(&rec->sg_aead_in[0], rec->aad_space, prot->aad_size);\n\tsg_unmark_end(&rec->sg_aead_in[1]);\n\n\tsg_init_table(rec->sg_aead_out, 2);\n\tsg_set_buf(&rec->sg_aead_out[0], rec->aad_space, prot->aad_size);\n\tsg_unmark_end(&rec->sg_aead_out[1]);\n\n\treturn rec;\n}",
        "static int __two_after_loss(struct tfrc_rx_hist *h, struct sk_buff *skb, u32 n3)\n{\n\tu64 s0 = tfrc_rx_hist_loss_prev(h)->tfrchrx_seqno,\n\t    s1 = tfrc_rx_hist_entry(h, 1)->tfrchrx_seqno,\n\t    s2 = tfrc_rx_hist_entry(h, 2)->tfrchrx_seqno,": "static int __two_after_loss(struct tfrc_rx_hist *h, struct sk_buff *skb, u32 n3)\n{\n\tu64 s0 = tfrc_rx_hist_loss_prev(h)->tfrchrx_seqno,\n\t    s1 = tfrc_rx_hist_entry(h, 1)->tfrchrx_seqno,\n\t    s2 = tfrc_rx_hist_entry(h, 2)->tfrchrx_seqno,\n\t    s3 = DCCP_SKB_CB(skb)->dccpd_seq;\n\n\tif (likely(dccp_delta_seqno(s2, s3) > 0)) {\t/* S2  <  S3 */\n\t\th->loss_count = 3;\n\t\ttfrc_rx_hist_entry_from_skb(tfrc_rx_hist_entry(h, 3), skb, n3);\n\t\treturn 1;\n\t}\n\n\t/* S3  <  S2 */\n\n\tif (dccp_delta_seqno(s1, s3) > 0) {\t\t/* S1  <  S3  <  S2 */\n\t\t/*\n\t\t * Reorder history to insert S3 between S1 and S2\n\t\t */\n\t\ttfrc_rx_hist_swap(h, 2, 3);\n\t\ttfrc_rx_hist_entry_from_skb(tfrc_rx_hist_entry(h, 2), skb, n3);\n\t\th->loss_count = 3;\n\t\treturn 1;\n\t}\n\n\t/* S0  <  S3  <  S1 */\n\n\tif (dccp_loss_free(s0, s3, n3)) {\n\t\tu64 n1 = tfrc_rx_hist_entry(h, 1)->tfrchrx_ndp;\n\n\t\tif (dccp_loss_free(s3, s1, n1)) {\n\t\t\t/* hole between S0 and S1 filled by S3 */\n\t\t\tu64 n2 = tfrc_rx_hist_entry(h, 2)->tfrchrx_ndp;\n\n\t\t\tif (dccp_loss_free(s1, s2, n2)) {\n\t\t\t\t/* entire hole filled by S0, S3, S1, S2 */\n\t\t\t\th->loss_start = tfrc_rx_hist_index(h, 2);\n\t\t\t\th->loss_count = 0;\n\t\t\t} else {\n\t\t\t\t/* gap remains between S1 and S2 */\n\t\t\t\th->loss_start = tfrc_rx_hist_index(h, 1);\n\t\t\t\th->loss_count = 1;\n\t\t\t}\n\n\t\t} else /* gap exists between S3 and S1, loss_count stays at 2 */\n\t\t\ttfrc_rx_hist_entry_from_skb(tfrc_rx_hist_loss_prev(h), skb, n3);\n\n\t\treturn 0;\n\t}\n\n\t/*\n\t * The remaining case:  S0  <  S3  <  S1  <  S2;  gap between S0 and S3\n\t * Reorder history to insert S3 between S0 and S1.\n\t */\n\ttfrc_rx_hist_swap(h, 0, 3);\n\th->loss_start = tfrc_rx_hist_index(h, 3);\n\ttfrc_rx_hist_entry_from_skb(tfrc_rx_hist_entry(h, 1), skb, n3);\n\th->loss_count = 3;\n\n\treturn 1;\n}",
        "static int test_set_debugreg(pid_t child_pid)\n{\n\tunsigned long wp_addr = (unsigned long)&glvar;\n\tchar *name = \"PTRACE_SET_DEBUGREG\";\n\tint len;": "static int test_set_debugreg(pid_t child_pid)\n{\n\tunsigned long wp_addr = (unsigned long)&glvar;\n\tchar *name = \"PTRACE_SET_DEBUGREG\";\n\tint len;\n\n\t/* PTRACE_SET_DEBUGREG, WO test*/\n\twp_addr &= ~0x7UL;\n\twp_addr |= (1UL << DABR_WRITE_SHIFT);\n\twp_addr |= (1UL << DABR_TRANSLATION_SHIFT);\n\tfor (len = 1; len <= sizeof(glvar); len <<= 1) {\n\t\tptrace_set_debugreg(child_pid, wp_addr);\n\t\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\t\tcheck_success(child_pid, name, \"WO\", wp_addr, len);\n\t}\n\n\t/* PTRACE_SET_DEBUGREG, RO test */\n\twp_addr &= ~0x7UL;\n\twp_addr |= (1UL << DABR_READ_SHIFT);\n\twp_addr |= (1UL << DABR_TRANSLATION_SHIFT);\n\tfor (len = 1; len <= sizeof(glvar); len <<= 1) {\n\t\tptrace_set_debugreg(child_pid, wp_addr);\n\t\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\t\tcheck_success(child_pid, name, \"RO\", wp_addr, len);\n\t}\n\n\t/* PTRACE_SET_DEBUGREG, RW test */\n\twp_addr &= ~0x7UL;\n\twp_addr |= (1Ul << DABR_READ_SHIFT);\n\twp_addr |= (1UL << DABR_WRITE_SHIFT);\n\twp_addr |= (1UL << DABR_TRANSLATION_SHIFT);\n\tfor (len = 1; len <= sizeof(glvar); len <<= 1) {\n\t\tptrace_set_debugreg(child_pid, wp_addr);\n\t\tptrace(PTRACE_CONT, child_pid, NULL, 0);\n\t\tcheck_success(child_pid, name, \"RW\", wp_addr, len);\n\t}\n\n\tptrace_set_debugreg(child_pid, 0);\n\treturn 0;\n}",
        "static void rt711_sdca_btn_check_handler(struct work_struct *work)\n{\n\tstruct rt711_sdca_priv *rt711 =\n\t\tcontainer_of(work, struct rt711_sdca_priv, jack_btn_check_work.work);\n\tint btn_type = 0, ret, idx;": "static void rt711_sdca_btn_check_handler(struct work_struct *work)\n{\n\tstruct rt711_sdca_priv *rt711 =\n\t\tcontainer_of(work, struct rt711_sdca_priv, jack_btn_check_work.work);\n\tint btn_type = 0, ret, idx;\n\tunsigned int det_mode, offset, val;\n\tunsigned char buf[3];\n\n\tret = regmap_read(rt711->regmap,\n\t\tSDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_DETECTED_MODE, 0),\n\t\t&det_mode);\n\tif (ret < 0)\n\t\tgoto io_error;\n\n\t/* pin attached */\n\tif (det_mode) {\n\t\t/* read UMP message offset */\n\t\tret = regmap_read(rt711->regmap,\n\t\t\tSDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0),\n\t\t\t&offset);\n\t\tif (ret < 0)\n\t\t\tgoto io_error;\n\n\t\tfor (idx = 0; idx < sizeof(buf); idx++) {\n\t\t\tret = regmap_read(rt711->regmap,\n\t\t\t\tRT711_BUF_ADDR_HID1 + offset + idx, &val);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto io_error;\n\t\t\tbuf[idx] = val & 0xff;\n\t\t}\n\n\t\tif (buf[0] == 0x11) {\n\t\t\tswitch (buf[1] & 0xf0) {\n\t\t\tcase 0x10:\n\t\t\t\tbtn_type |= SND_JACK_BTN_2;\n\t\t\t\tbreak;\n\t\t\tcase 0x20:\n\t\t\t\tbtn_type |= SND_JACK_BTN_3;\n\t\t\t\tbreak;\n\t\t\tcase 0x40:\n\t\t\t\tbtn_type |= SND_JACK_BTN_0;\n\t\t\t\tbreak;\n\t\t\tcase 0x80:\n\t\t\t\tbtn_type |= SND_JACK_BTN_1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tswitch (buf[2]) {\n\t\t\tcase 0x01:\n\t\t\tcase 0x10:\n\t\t\t\tbtn_type |= SND_JACK_BTN_2;\n\t\t\t\tbreak;\n\t\t\tcase 0x02:\n\t\t\tcase 0x20:\n\t\t\t\tbtn_type |= SND_JACK_BTN_3;\n\t\t\t\tbreak;\n\t\t\tcase 0x04:\n\t\t\tcase 0x40:\n\t\t\t\tbtn_type |= SND_JACK_BTN_0;\n\t\t\t\tbreak;\n\t\t\tcase 0x08:\n\t\t\tcase 0x80:\n\t\t\t\tbtn_type |= SND_JACK_BTN_1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t} else\n\t\trt711->jack_type = 0;\n\n\tdev_dbg(&rt711->slave->dev, \"%s, btn_type=0x%x\\n\",\t__func__, btn_type);\n\tsnd_soc_jack_report(rt711->hs_jack, rt711->jack_type | btn_type,\n\t\t\tSND_JACK_HEADSET |\n\t\t\tSND_JACK_BTN_0 | SND_JACK_BTN_1 |\n\t\t\tSND_JACK_BTN_2 | SND_JACK_BTN_3);\n\n\tif (btn_type) {\n\t\t/* button released */\n\t\tsnd_soc_jack_report(rt711->hs_jack, rt711->jack_type,\n\t\t\tSND_JACK_HEADSET |\n\t\t\tSND_JACK_BTN_0 | SND_JACK_BTN_1 |\n\t\t\tSND_JACK_BTN_2 | SND_JACK_BTN_3);\n\n\t\tmod_delayed_work(system_power_efficient_wq,\n\t\t\t&rt711->jack_btn_check_work, msecs_to_jiffies(200));\n\t}\n\n\treturn;\n\nio_error:\n\tpr_err_ratelimited(\"IO error in %s, ret %d\\n\", __func__, ret);\n}",
        "static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)\n{\n\tu32 room, entries, sts;\n\tunsigned int len;\n\tu8 *buf;": "static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)\n{\n\tu32 room, entries, sts;\n\tunsigned int len;\n\tu8 *buf;\n\n\t/*\n\t * At initial stage we just pre-fill the Tx FIFO in with no rush,\n\t * since native CS hasn't been enabled yet and the automatic data\n\t * transmission won't start til we do that.\n\t */\n\tlen = min(dws->fifo_len, dws->tx_len);\n\tbuf = dws->tx;\n\twhile (len--)\n\t\tdw_write_io_reg(dws, DW_SPI_DR, *buf++);\n\n\t/*\n\t * After setting any bit in the SER register the transmission will\n\t * start automatically. We have to keep up with that procedure\n\t * otherwise the CS de-assertion will happen whereupon the memory\n\t * operation will be pre-terminated.\n\t */\n\tlen = dws->tx_len - ((void *)buf - dws->tx);\n\tdw_spi_set_cs(spi, false);\n\twhile (len) {\n\t\tentries = readl_relaxed(dws->regs + DW_SPI_TXFLR);\n\t\tif (!entries) {\n\t\t\tdev_err(&dws->master->dev, \"CS de-assertion on Tx\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\troom = min(dws->fifo_len - entries, len);\n\t\tfor (; room; --room, --len)\n\t\t\tdw_write_io_reg(dws, DW_SPI_DR, *buf++);\n\t}\n\n\t/*\n\t * Data fetching will start automatically if the EEPROM-read mode is\n\t * activated. We have to keep up with the incoming data pace to\n\t * prevent the Rx FIFO overflow causing the inbound data loss.\n\t */\n\tlen = dws->rx_len;\n\tbuf = dws->rx;\n\twhile (len) {\n\t\tentries = readl_relaxed(dws->regs + DW_SPI_RXFLR);\n\t\tif (!entries) {\n\t\t\tsts = readl_relaxed(dws->regs + DW_SPI_RISR);\n\t\t\tif (sts & DW_SPI_INT_RXOI) {\n\t\t\t\tdev_err(&dws->master->dev, \"FIFO overflow on Rx\\n\");\n\t\t\t\treturn -EIO;\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t\tentries = min(entries, len);\n\t\tfor (; entries; --entries, --len)\n\t\t\t*buf++ = dw_read_io_reg(dws, DW_SPI_DR);\n\t}\n\n\treturn 0;\n}",
        "static void ftrace_syscall_enter(void *data, struct pt_regs *regs, long id)\n{\n\tstruct trace_array *tr = data;\n\tstruct trace_event_file *trace_file;\n\tstruct syscall_trace_enter *entry;": "static void ftrace_syscall_enter(void *data, struct pt_regs *regs, long id)\n{\n\tstruct trace_array *tr = data;\n\tstruct trace_event_file *trace_file;\n\tstruct syscall_trace_enter *entry;\n\tstruct syscall_metadata *sys_data;\n\tstruct trace_event_buffer fbuffer;\n\tunsigned long args[6];\n\tint syscall_nr;\n\tint size;\n\n\tsyscall_nr = trace_get_syscall_nr(current, regs);\n\tif (syscall_nr < 0 || syscall_nr >= NR_syscalls)\n\t\treturn;\n\n\t/* Here we're inside tp handler's rcu_read_lock_sched (__DO_TRACE) */\n\ttrace_file = rcu_dereference_sched(tr->enter_syscall_files[syscall_nr]);\n\tif (!trace_file)\n\t\treturn;\n\n\tif (trace_trigger_soft_disabled(trace_file))\n\t\treturn;\n\n\tsys_data = syscall_nr_to_meta(syscall_nr);\n\tif (!sys_data)\n\t\treturn;\n\n\tsize = sizeof(*entry) + sizeof(unsigned long) * sys_data->nb_args;\n\n\tentry = trace_event_buffer_reserve(&fbuffer, trace_file, size);\n\tif (!entry)\n\t\treturn;\n\n\tentry = ring_buffer_event_data(fbuffer.event);\n\tentry->nr = syscall_nr;\n\tsyscall_get_arguments(current, regs, args);\n\tmemcpy(entry->args, args, sizeof(unsigned long) * sys_data->nb_args);\n\n\ttrace_event_buffer_commit(&fbuffer);\n}",
        "static inline bool allow_direct_printing(void)\n{\n\t/*\n\t * Checking kthread availability is a possible race because the\n\t * kthread printers can become permanently disabled during runtime.": "static inline bool allow_direct_printing(void)\n{\n\t/*\n\t * Checking kthread availability is a possible race because the\n\t * kthread printers can become permanently disabled during runtime.\n\t * However, doing that requires holding the console_lock, so any\n\t * pending messages will be direct printed by console_unlock().\n\t */\n\tif (!printk_kthreads_available)\n\t\treturn true;\n\n\t/*\n\t * Prefer direct printing when the system is in a problematic state.\n\t * The context that sets this state will always see the updated value.\n\t * The other contexts do not care. Anyway, direct printing is just a\n\t * best effort. The direct output is only possible when console_lock\n\t * is not already taken and no kthread printers are actively printing.\n\t */\n\treturn (system_state > SYSTEM_RUNNING ||\n\t\toops_in_progress ||\n\t\tatomic_read(&printk_prefer_direct));\n}",
        "static int adv7842_sdp_log_status(struct v4l2_subdev *sd)\n{\n\t/* SDP (Standard definition processor) block */\n\tu8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;\n": "static int adv7842_sdp_log_status(struct v4l2_subdev *sd)\n{\n\t/* SDP (Standard definition processor) block */\n\tu8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;\n\n\tv4l2_info(sd, \"Chip powered %s\\n\", no_power(sd) ? \"off\" : \"on\");\n\tv4l2_info(sd, \"Prim-mode = 0x%x, video std = 0x%x\\n\",\n\t\t  io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);\n\n\tv4l2_info(sd, \"SDP: free run: %s\\n\",\n\t\t(sdp_read(sd, 0x56) & 0x01) ? \"on\" : \"off\");\n\tv4l2_info(sd, \"SDP: %s\\n\", sdp_signal_detected ?\n\t\t\"valid SD/PR signal detected\" : \"invalid/no signal\");\n\tif (sdp_signal_detected) {\n\t\tstatic const char * const sdp_std_txt[] = {\n\t\t\t\"NTSC-M/J\",\n\t\t\t\"1?\",\n\t\t\t\"NTSC-443\",\n\t\t\t\"60HzSECAM\",\n\t\t\t\"PAL-M\",\n\t\t\t\"5?\",\n\t\t\t\"PAL-60\",\n\t\t\t\"7?\", \"8?\", \"9?\", \"a?\", \"b?\",\n\t\t\t\"PAL-CombN\",\n\t\t\t\"d?\",\n\t\t\t\"PAL-BGHID\",\n\t\t\t\"SECAM\"\n\t\t};\n\t\tv4l2_info(sd, \"SDP: standard %s\\n\",\n\t\t\tsdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);\n\t\tv4l2_info(sd, \"SDP: %s\\n\",\n\t\t\t(sdp_read(sd, 0x59) & 0x08) ? \"50Hz\" : \"60Hz\");\n\t\tv4l2_info(sd, \"SDP: %s\\n\",\n\t\t\t(sdp_read(sd, 0x57) & 0x08) ? \"Interlaced\" : \"Progressive\");\n\t\tv4l2_info(sd, \"SDP: deinterlacer %s\\n\",\n\t\t\t(sdp_read(sd, 0x12) & 0x08) ? \"enabled\" : \"disabled\");\n\t\tv4l2_info(sd, \"SDP: csc %s mode\\n\",\n\t\t\t(sdp_io_read(sd, 0xe0) & 0x40) ? \"auto\" : \"manual\");\n\t}\n\treturn 0;\n}",
        "static void freezer_fork(struct task_struct *task)\n{\n\tstruct freezer *freezer;\n\n\t/*": "static void freezer_fork(struct task_struct *task)\n{\n\tstruct freezer *freezer;\n\n\t/*\n\t * The root cgroup is non-freezable, so we can skip locking the\n\t * freezer.  This is safe regardless of race with task migration.\n\t * If we didn't race or won, skipping is obviously the right thing\n\t * to do.  If we lost and root is the new cgroup, noop is still the\n\t * right thing to do.\n\t */\n\tif (task_css_is_root(task, freezer_cgrp_id))\n\t\treturn;\n\n\tmutex_lock(&freezer_mutex);\n\trcu_read_lock();\n\n\tfreezer = task_freezer(task);\n\tif (freezer->state & CGROUP_FREEZING)\n\t\tfreeze_task(task);\n\n\trcu_read_unlock();\n\tmutex_unlock(&freezer_mutex);\n}",
        "static int alloc_try_nid_max_reserved_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_max_reserved_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t r1_size = SZ_64;\n\tphys_addr_t r2_size = SZ_128;\n\tphys_addr_t total_size = r1_size + r2_size;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\n\tsetup_memblock();\n\n\tmax_addr = memblock_end_of_DRAM() - r1_size;\n\tmin_addr = max_addr - r2_size;\n\n\tmemblock_reserve(max_addr, r1_size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r2_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == total_size);\n\tassert(rgn->base == min_addr);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static void register_pid_events(struct trace_array *tr)\n{\n\t/*\n\t * Register a probe that is called before all other probes\n\t * to set ignore_pid if next or prev do not match.": "static void register_pid_events(struct trace_array *tr)\n{\n\t/*\n\t * Register a probe that is called before all other probes\n\t * to set ignore_pid if next or prev do not match.\n\t * Register a probe this is called after all other probes\n\t * to only keep ignore_pid set if next pid matches.\n\t */\n\tregister_trace_prio_sched_switch(event_filter_pid_sched_switch_probe_pre,\n\t\t\t\t\t tr, INT_MAX);\n\tregister_trace_prio_sched_switch(event_filter_pid_sched_switch_probe_post,\n\t\t\t\t\t tr, 0);\n\n\tregister_trace_prio_sched_wakeup(event_filter_pid_sched_wakeup_probe_pre,\n\t\t\t\t\t tr, INT_MAX);\n\tregister_trace_prio_sched_wakeup(event_filter_pid_sched_wakeup_probe_post,\n\t\t\t\t\t tr, 0);\n\n\tregister_trace_prio_sched_wakeup_new(event_filter_pid_sched_wakeup_probe_pre,\n\t\t\t\t\t     tr, INT_MAX);\n\tregister_trace_prio_sched_wakeup_new(event_filter_pid_sched_wakeup_probe_post,\n\t\t\t\t\t     tr, 0);\n\n\tregister_trace_prio_sched_waking(event_filter_pid_sched_wakeup_probe_pre,\n\t\t\t\t\t tr, INT_MAX);\n\tregister_trace_prio_sched_waking(event_filter_pid_sched_wakeup_probe_post,\n\t\t\t\t\t tr, 0);\n}",
        "static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)\n{\n\tunsigned int reg;\n\n\tcs42l42->hs_type = CS42L42_PLUG_INVALID;": "static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)\n{\n\tunsigned int reg;\n\n\tcs42l42->hs_type = CS42L42_PLUG_INVALID;\n\n\t/*\n\t * DETECT_MODE must always be 0 with ADC and HP both off otherwise the\n\t * FILT+ supply will not charge properly.\n\t */\n\tregmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,\n\t\t\t   CS42L42_DETECT_MODE_MASK, 0);\n\n\t/* Latch analog controls to VP power domain */\n\tregmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,\n\t\t\tCS42L42_LATCH_TO_VP_MASK |\n\t\t\tCS42L42_EVENT_STAT_SEL_MASK |\n\t\t\tCS42L42_HS_DET_LEVEL_MASK,\n\t\t\t(1 << CS42L42_LATCH_TO_VP_SHIFT) |\n\t\t\t(0 << CS42L42_EVENT_STAT_SEL_SHIFT) |\n\t\t\t(cs42l42->bias_thresholds[0] <<\n\t\t\tCS42L42_HS_DET_LEVEL_SHIFT));\n\n\t/* Remove ground noise-suppression clamps */\n\tregmap_update_bits(cs42l42->regmap,\n\t\t\tCS42L42_HS_CLAMP_DISABLE,\n\t\t\tCS42L42_HS_CLAMP_DISABLE_MASK,\n\t\t\t(1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));\n\n\t/* Enable the tip sense circuit */\n\tregmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,\n\t\t\t   CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);\n\n\tregmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,\n\t\t\tCS42L42_TIP_SENSE_CTRL_MASK |\n\t\t\tCS42L42_TIP_SENSE_INV_MASK |\n\t\t\tCS42L42_TIP_SENSE_DEBOUNCE_MASK,\n\t\t\t(3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |\n\t\t\t(!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |\n\t\t\t(2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));\n\n\t/* Save the initial status of the tip sense */\n\tregmap_read(cs42l42->regmap,\n\t\t\t  CS42L42_TSRS_PLUG_STATUS,\n\t\t\t  &reg);\n\tcs42l42->plug_state = (((char) reg) &\n\t\t      (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>\n\t\t      CS42L42_TS_PLUG_SHIFT;\n}",
        "static void otx2_pfaf_mbox_up_handler(struct work_struct *work)\n{\n\tstruct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);\n\tstruct otx2_mbox *mbox = &af_mbox->mbox_up;\n\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];": "static void otx2_pfaf_mbox_up_handler(struct work_struct *work)\n{\n\tstruct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);\n\tstruct otx2_mbox *mbox = &af_mbox->mbox_up;\n\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n\tstruct otx2_nic *pf = af_mbox->pfvf;\n\tint offset, id, devid = 0;\n\tstruct mbox_hdr *rsp_hdr;\n\tstruct mbox_msghdr *msg;\n\n\trsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);\n\n\toffset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);\n\n\tfor (id = 0; id < af_mbox->up_num_msgs; id++) {\n\t\tmsg = (struct mbox_msghdr *)(mdev->mbase + offset);\n\n\t\tdevid = msg->pcifunc & RVU_PFVF_FUNC_MASK;\n\t\t/* Skip processing VF's messages */\n\t\tif (!devid)\n\t\t\totx2_process_mbox_msg_up(pf, msg);\n\t\toffset = mbox->rx_start + msg->next_msgoff;\n\t}\n\tif (devid) {\n\t\totx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,\n\t\t\t\t\t  MBOX_DIR_PFVF_UP, devid - 1,\n\t\t\t\t\t  af_mbox->up_num_msgs);\n\t\treturn;\n\t}\n\n\totx2_mbox_msg_send(mbox, 0);\n}",
        "static int __bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)\n{\n\tu32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);\n\tu32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;\n\tstruct coredump_segment_record *seg_record = NULL;": "static int __bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)\n{\n\tu32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);\n\tu32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;\n\tstruct coredump_segment_record *seg_record = NULL;\n\tstruct bnxt_coredump_segment_hdr seg_hdr;\n\tstruct bnxt_coredump coredump = {NULL};\n\ttime64_t start_time;\n\tu16 start_utc;\n\tint rc = 0, i;\n\n\tif (buf)\n\t\tbuf_len = *dump_len;\n\n\tstart_time = ktime_get_real_seconds();\n\tstart_utc = sys_tz.tz_minuteswest * 60;\n\tseg_hdr_len = sizeof(seg_hdr);\n\n\t/* First segment should be hwrm_ver_get response */\n\t*dump_len = seg_hdr_len + ver_get_resp_len;\n\tif (buf) {\n\t\tbnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,\n\t\t\t\t\t   0, 0, 0);\n\t\tmemcpy(buf + offset, &seg_hdr, seg_hdr_len);\n\t\toffset += seg_hdr_len;\n\t\tmemcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);\n\t\toffset += ver_get_resp_len;\n\t}\n\n\trc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);\n\tif (rc) {\n\t\tnetdev_err(bp->dev, \"Failed to get coredump segment list\\n\");\n\t\tgoto err;\n\t}\n\n\t*dump_len += seg_hdr_len * coredump.total_segs;\n\n\tseg_record = (struct coredump_segment_record *)coredump.data;\n\tseg_record_len = sizeof(*seg_record);\n\n\tfor (i = 0; i < coredump.total_segs; i++) {\n\t\tu16 comp_id = le16_to_cpu(seg_record->component_id);\n\t\tu16 seg_id = le16_to_cpu(seg_record->segment_id);\n\t\tu32 duration = 0, seg_len = 0;\n\t\tunsigned long start, end;\n\n\t\tif (buf && ((offset + seg_hdr_len) >\n\t\t\t    BNXT_COREDUMP_BUF_LEN(buf_len))) {\n\t\t\trc = -ENOBUFS;\n\t\t\tgoto err;\n\t\t}\n\n\t\tstart = jiffies;\n\n\t\trc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);\n\t\tif (rc) {\n\t\t\tnetdev_err(bp->dev,\n\t\t\t\t   \"Failed to initiate coredump for seg = %d\\n\",\n\t\t\t\t   seg_record->segment_id);\n\t\t\tgoto next_seg;\n\t\t}\n\n\t\t/* Write segment data into the buffer */\n\t\trc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,\n\t\t\t\t\t\t     &seg_len, buf, buf_len,\n\t\t\t\t\t\t     offset + seg_hdr_len);\n\t\tif (rc && rc == -ENOBUFS)\n\t\t\tgoto err;\n\t\telse if (rc)\n\t\t\tnetdev_err(bp->dev,\n\t\t\t\t   \"Failed to retrieve coredump for seg = %d\\n\",\n\t\t\t\t   seg_record->segment_id);\n\nnext_seg:\n\t\tend = jiffies;\n\t\tduration = jiffies_to_msecs(end - start);\n\t\tbnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,\n\t\t\t\t\t   rc, duration, 0);\n\n\t\tif (buf) {\n\t\t\t/* Write segment header into the buffer */\n\t\t\tmemcpy(buf + offset, &seg_hdr, seg_hdr_len);\n\t\t\toffset += seg_hdr_len + seg_len;\n\t\t}\n\n\t\t*dump_len += seg_len;\n\t\tseg_record =\n\t\t\t(struct coredump_segment_record *)((u8 *)seg_record +\n\t\t\t\t\t\t\t   seg_record_len);\n\t}\n\nerr:\n\tif (buf)\n\t\tbnxt_fill_coredump_record(bp, buf + offset, start_time,\n\t\t\t\t\t  start_utc, coredump.total_segs + 1,\n\t\t\t\t\t  rc);\n\tkfree(coredump.data);\n\t*dump_len += sizeof(struct bnxt_coredump_record);\n\tif (rc == -ENOBUFS)\n\t\tnetdev_err(bp->dev, \"Firmware returned large coredump buffer\\n\");\n\treturn rc;\n}",
        "static void setbrightness(struct gspca_dev *gspca_dev, s32 val)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tu8 sign_reg = 7;  /* This reg and the next one used on CIF cams. */\n\tu8 value_reg = 8; /* VGA cams seem to use regs 0x0b and 0x0c */": "static void setbrightness(struct gspca_dev *gspca_dev, s32 val)\n{\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\tu8 sign_reg = 7;  /* This reg and the next one used on CIF cams. */\n\tu8 value_reg = 8; /* VGA cams seem to use regs 0x0b and 0x0c */\n\tstatic const u8 quick_clix_table[] =\n\t/*\t  0  1  2   3  4  5  6  7  8  9  10  11  12  13  14  15 */\n\t\t{ 0, 4, 8, 12, 1, 2, 3, 5, 6, 9,  7, 10, 13, 11, 14, 15};\n\tif (sd->cam_type == CAM_TYPE_VGA) {\n\t\tsign_reg += 4;\n\t\tvalue_reg += 4;\n\t}\n\n\t/* Note register 7 is also seen as 0x8x or 0xCx in some dumps */\n\tif (val > 0) {\n\t\tsensor_write1(gspca_dev, sign_reg, 0x00);\n\t} else {\n\t\tsensor_write1(gspca_dev, sign_reg, 0x01);\n\t\tval = 257 - val;\n\t}\n\t/* Use lookup table for funky Argus QuickClix brightness */\n\tif (sd->do_lcd_stop)\n\t\tval = quick_clix_table[val];\n\n\tsensor_write1(gspca_dev, value_reg, val);\n}",
        "static void catpt_dsp_process_response(struct catpt_dev *cdev, u32 header)\n{\n\tunion catpt_notify_msg msg = CATPT_MSG(header);\n\tstruct catpt_ipc *ipc = &cdev->ipc;\n": "static void catpt_dsp_process_response(struct catpt_dev *cdev, u32 header)\n{\n\tunion catpt_notify_msg msg = CATPT_MSG(header);\n\tstruct catpt_ipc *ipc = &cdev->ipc;\n\n\tif (msg.fw_ready) {\n\t\tstruct catpt_fw_ready config;\n\t\t/* to fit 32b header original address is shifted right by 3 */\n\t\tu32 off = msg.mailbox_address << 3;\n\n\t\tmemcpy_fromio(&config, cdev->lpe_ba + off, sizeof(config));\n\t\ttrace_catpt_ipc_payload((u8 *)&config, sizeof(config));\n\n\t\tcatpt_ipc_arm(ipc, &config);\n\t\tcomplete(&cdev->fw_ready);\n\t\treturn;\n\t}\n\n\tswitch (msg.global_msg_type) {\n\tcase CATPT_GLB_REQUEST_CORE_DUMP:\n\t\tdev_err(cdev->dev, \"ADSP device coredump received\\n\");\n\t\tipc->ready = false;\n\t\tcatpt_coredump(cdev);\n\t\t/* TODO: attempt recovery */\n\t\tbreak;\n\n\tcase CATPT_GLB_STREAM_MESSAGE:\n\t\tswitch (msg.stream_msg_type) {\n\t\tcase CATPT_STRM_NOTIFICATION:\n\t\t\tcatpt_dsp_notify_stream(cdev, msg);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tcatpt_dsp_copy_rx(cdev, header);\n\t\t\t/* signal completion of delayed reply */\n\t\t\tcomplete(&ipc->busy_completion);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tdev_warn(cdev->dev, \"unknown response: %d received\\n\",\n\t\t\t msg.global_msg_type);\n\t\tbreak;\n\t}\n}",
        "static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers)\n{\n\tunsigned int buffer;\n\n\t/*": "static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers)\n{\n\tunsigned int buffer;\n\n\t/*\n\t * Sanity check: when preparing a buffer the queue lock is released for\n\t * a short while (see __buf_prepare for the details), which would allow\n\t * a race with a reqbufs which can call this function. Removing the\n\t * buffers from underneath __buf_prepare is obviously a bad idea, so we\n\t * check if any of the buffers is in the state PREPARING, and if so we\n\t * just return -EAGAIN.\n\t */\n\tfor (buffer = q->num_buffers - buffers; buffer < q->num_buffers;\n\t     ++buffer) {\n\t\tif (q->bufs[buffer] == NULL)\n\t\t\tcontinue;\n\t\tif (q->bufs[buffer]->state == VB2_BUF_STATE_PREPARING) {\n\t\t\tdprintk(q, 1, \"preparing buffers, cannot free\\n\");\n\t\t\treturn -EAGAIN;\n\t\t}\n\t}\n\n\t/* Call driver-provided cleanup function for each buffer, if provided */\n\tfor (buffer = q->num_buffers - buffers; buffer < q->num_buffers;\n\t     ++buffer) {\n\t\tstruct vb2_buffer *vb = q->bufs[buffer];\n\n\t\tif (vb && vb->planes[0].mem_priv)\n\t\t\tcall_void_vb_qop(vb, buf_cleanup, vb);\n\t}\n\n\t/* Release video buffer memory */\n\t__vb2_free_mem(q, buffers);\n\n#ifdef CONFIG_VIDEO_ADV_DEBUG\n\t/*\n\t * Check that all the calls were balances during the life-time of this\n\t * queue. If not (or if the debug level is 1 or up), then dump the\n\t * counters to the kernel log.\n\t */\n\tif (q->num_buffers) {\n\t\tbool unbalanced = q->cnt_start_streaming != q->cnt_stop_streaming ||\n\t\t\t\t  q->cnt_wait_prepare != q->cnt_wait_finish;\n\n\t\tif (unbalanced || debug) {\n\t\t\tpr_info(\"counters for queue %p:%s\\n\", q,\n\t\t\t\tunbalanced ? \" UNBALANCED!\" : \"\");\n\t\t\tpr_info(\"     setup: %u start_streaming: %u stop_streaming: %u\\n\",\n\t\t\t\tq->cnt_queue_setup, q->cnt_start_streaming,\n\t\t\t\tq->cnt_stop_streaming);\n\t\t\tpr_info(\"     wait_prepare: %u wait_finish: %u\\n\",\n\t\t\t\tq->cnt_wait_prepare, q->cnt_wait_finish);\n\t\t}\n\t\tq->cnt_queue_setup = 0;\n\t\tq->cnt_wait_prepare = 0;\n\t\tq->cnt_wait_finish = 0;\n\t\tq->cnt_start_streaming = 0;\n\t\tq->cnt_stop_streaming = 0;\n\t}\n\tfor (buffer = 0; buffer < q->num_buffers; ++buffer) {\n\t\tstruct vb2_buffer *vb = q->bufs[buffer];\n\t\tbool unbalanced = vb->cnt_mem_alloc != vb->cnt_mem_put ||\n\t\t\t\t  vb->cnt_mem_prepare != vb->cnt_mem_finish ||\n\t\t\t\t  vb->cnt_mem_get_userptr != vb->cnt_mem_put_userptr ||\n\t\t\t\t  vb->cnt_mem_attach_dmabuf != vb->cnt_mem_detach_dmabuf ||\n\t\t\t\t  vb->cnt_mem_map_dmabuf != vb->cnt_mem_unmap_dmabuf ||\n\t\t\t\t  vb->cnt_buf_queue != vb->cnt_buf_done ||\n\t\t\t\t  vb->cnt_buf_prepare != vb->cnt_buf_finish ||\n\t\t\t\t  vb->cnt_buf_init != vb->cnt_buf_cleanup;\n\n\t\tif (unbalanced || debug) {\n\t\t\tpr_info(\"   counters for queue %p, buffer %d:%s\\n\",\n\t\t\t\tq, buffer, unbalanced ? \" UNBALANCED!\" : \"\");\n\t\t\tpr_info(\"     buf_init: %u buf_cleanup: %u buf_prepare: %u buf_finish: %u\\n\",\n\t\t\t\tvb->cnt_buf_init, vb->cnt_buf_cleanup,\n\t\t\t\tvb->cnt_buf_prepare, vb->cnt_buf_finish);\n\t\t\tpr_info(\"     buf_out_validate: %u buf_queue: %u buf_done: %u buf_request_complete: %u\\n\",\n\t\t\t\tvb->cnt_buf_out_validate, vb->cnt_buf_queue,\n\t\t\t\tvb->cnt_buf_done, vb->cnt_buf_request_complete);\n\t\t\tpr_info(\"     alloc: %u put: %u prepare: %u finish: %u mmap: %u\\n\",\n\t\t\t\tvb->cnt_mem_alloc, vb->cnt_mem_put,\n\t\t\t\tvb->cnt_mem_prepare, vb->cnt_mem_finish,\n\t\t\t\tvb->cnt_mem_mmap);\n\t\t\tpr_info(\"     get_userptr: %u put_userptr: %u\\n\",\n\t\t\t\tvb->cnt_mem_get_userptr, vb->cnt_mem_put_userptr);\n\t\t\tpr_info(\"     attach_dmabuf: %u detach_dmabuf: %u map_dmabuf: %u unmap_dmabuf: %u\\n\",\n\t\t\t\tvb->cnt_mem_attach_dmabuf, vb->cnt_mem_detach_dmabuf,\n\t\t\t\tvb->cnt_mem_map_dmabuf, vb->cnt_mem_unmap_dmabuf);\n\t\t\tpr_info(\"     get_dmabuf: %u num_users: %u vaddr: %u cookie: %u\\n\",\n\t\t\t\tvb->cnt_mem_get_dmabuf,\n\t\t\t\tvb->cnt_mem_num_users,\n\t\t\t\tvb->cnt_mem_vaddr,\n\t\t\t\tvb->cnt_mem_cookie);\n\t\t}\n\t}\n#endif\n\n\t/* Free videobuf buffers */\n\tfor (buffer = q->num_buffers - buffers; buffer < q->num_buffers;\n\t     ++buffer) {\n\t\tkfree(q->bufs[buffer]);\n\t\tq->bufs[buffer] = NULL;\n\t}\n\n\tq->num_buffers -= buffers;\n\tif (!q->num_buffers) {\n\t\tq->memory = VB2_MEMORY_UNKNOWN;\n\t\tINIT_LIST_HEAD(&q->queued_list);\n\t}\n\treturn 0;\n}",
        "static void force_qs_rnp(int (*f)(struct rcu_data *rdp))\n{\n\tint cpu;\n\tunsigned long flags;\n\tunsigned long mask;": "static void force_qs_rnp(int (*f)(struct rcu_data *rdp))\n{\n\tint cpu;\n\tunsigned long flags;\n\tunsigned long mask;\n\tstruct rcu_data *rdp;\n\tstruct rcu_node *rnp;\n\n\trcu_state.cbovld = rcu_state.cbovldnext;\n\trcu_state.cbovldnext = false;\n\trcu_for_each_leaf_node(rnp) {\n\t\tcond_resched_tasks_rcu_qs();\n\t\tmask = 0;\n\t\traw_spin_lock_irqsave_rcu_node(rnp, flags);\n\t\trcu_state.cbovldnext |= !!rnp->cbovldmask;\n\t\tif (rnp->qsmask == 0) {\n\t\t\tif (rcu_preempt_blocked_readers_cgp(rnp)) {\n\t\t\t\t/*\n\t\t\t\t * No point in scanning bits because they\n\t\t\t\t * are all zero.  But we might need to\n\t\t\t\t * priority-boost blocked readers.\n\t\t\t\t */\n\t\t\t\trcu_initiate_boost(rnp, flags);\n\t\t\t\t/* rcu_initiate_boost() releases rnp->lock */\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\traw_spin_unlock_irqrestore_rcu_node(rnp, flags);\n\t\t\tcontinue;\n\t\t}\n\t\tfor_each_leaf_node_cpu_mask(rnp, cpu, rnp->qsmask) {\n\t\t\trdp = per_cpu_ptr(&rcu_data, cpu);\n\t\t\tif (f(rdp)) {\n\t\t\t\tmask |= rdp->grpmask;\n\t\t\t\trcu_disable_urgency_upon_qs(rdp);\n\t\t\t}\n\t\t}\n\t\tif (mask != 0) {\n\t\t\t/* Idle/offline CPUs, report (releases rnp->lock). */\n\t\t\trcu_report_qs_rnp(mask, rnp, rnp->gp_seq, flags);\n\t\t} else {\n\t\t\t/* Nothing to do here, so just drop the lock. */\n\t\t\traw_spin_unlock_irqrestore_rcu_node(rnp, flags);\n\t\t}\n\t}\n}",
        "static int cht_int33fe_add_nodes(struct cht_int33fe_data *data)\n{\n\tconst struct software_node *mux_ref_node;\n\tint ret;\n": "static int cht_int33fe_add_nodes(struct cht_int33fe_data *data)\n{\n\tconst struct software_node *mux_ref_node;\n\tint ret;\n\n\t/*\n\t * There is no ACPI device node for the USB role mux, so we need to wait\n\t * until the mux driver has created software node for the mux device.\n\t * It means we depend on the mux driver. This function will return\n\t * -EPROBE_DEFER until the mux device is registered.\n\t */\n\tmux_ref_node = software_node_find_by_name(NULL, \"intel-xhci-usb-sw\");\n\tif (!mux_ref_node)\n\t\treturn -EPROBE_DEFER;\n\n\t/*\n\t * Update node used in \"usb-role-switch\" property. Note that we\n\t * rely on software_node_register_nodes() to use the original\n\t * instance of properties instead of copying them.\n\t */\n\tfusb302_mux_refs[0].node = mux_ref_node;\n\n\tret = software_node_register_node_group(node_group);\n\tif (ret)\n\t\treturn ret;\n\n\t/* The devices that are not created in this driver need extra steps. */\n\n\t/*\n\t * The DP connector does have ACPI device node. In this case we can just\n\t * find that ACPI node and assign our node as the secondary node to it.\n\t */\n\tret = cht_int33fe_setup_dp(data);\n\tif (ret)\n\t\tgoto err_remove_nodes;\n\n\treturn 0;\n\nerr_remove_nodes:\n\tcht_int33fe_remove_nodes(data);\n\n\treturn ret;\n}",
        "static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)\n{\n\tu32 link_s1, lp_an_page_low, an_cntl_1;\n\ts32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\tixgbe_link_speed speed;": "static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)\n{\n\tu32 link_s1, lp_an_page_low, an_cntl_1;\n\ts32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\t/* AN should have completed when the cable was plugged in.\n\t * Look for reasons to bail out.  Bail out if:\n\t * - FC autoneg is disabled, or if\n\t * - link is not up.\n\t */\n\tif (hw->fc.disable_fc_autoneg) {\n\t\thw_err(hw, \"Flow control autoneg is disabled\");\n\t\tgoto out;\n\t}\n\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\tif (!link_up) {\n\t\thw_err(hw, \"The link is down\");\n\t\tgoto out;\n\t}\n\n\t/* Check at auto-negotiation has completed */\n\tstatus = hw->mac.ops.read_iosf_sb_reg(hw,\n\t\t\t\t\tIXGBE_KRM_LINK_S1(hw->bus.lan_id),\n\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);\n\n\tif (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {\n\t\thw_dbg(hw, \"Auto-Negotiation did not complete\\n\");\n\t\tstatus = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\t\tgoto out;\n\t}\n\n\t/* Read the 10g AN autoc and LP ability registers and resolve\n\t * local flow control settings accordingly\n\t */\n\tstatus = hw->mac.ops.read_iosf_sb_reg(hw,\n\t\t\t\tIXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);\n\n\tif (status) {\n\t\thw_dbg(hw, \"Auto-Negotiation did not complete\\n\");\n\t\tgoto out;\n\t}\n\n\tstatus = hw->mac.ops.read_iosf_sb_reg(hw,\n\t\t\t\tIXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);\n\n\tif (status) {\n\t\thw_dbg(hw, \"Auto-Negotiation did not complete\\n\");\n\t\tgoto out;\n\t}\n\n\tstatus = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,\n\t\t\t\t    IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,\n\t\t\t\t    IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,\n\t\t\t\t    IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,\n\t\t\t\t    IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);\n\nout:\n\tif (!status) {\n\t\thw->fc.fc_was_autonegged = true;\n\t} else {\n\t\thw->fc.fc_was_autonegged = false;\n\t\thw->fc.current_mode = hw->fc.requested_mode;\n\t}\n}",
        "static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)\n{\n\tu32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;\n\tacpi_handle handle = ACPI_HANDLE(i2c_dev->dev);\n\tstruct i2c_timings *t = &i2c_dev->timings;": "static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)\n{\n\tu32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;\n\tacpi_handle handle = ACPI_HANDLE(i2c_dev->dev);\n\tstruct i2c_timings *t = &i2c_dev->timings;\n\tint err;\n\n\t/*\n\t * The reset shouldn't ever fail in practice. The failure will be a\n\t * sign of a severe problem that needs to be resolved. Still we don't\n\t * want to fail the initialization completely because this may break\n\t * kernel boot up since voltage regulators use I2C. Hence, we will\n\t * emit a noisy warning on error, which won't stay unnoticed and\n\t * won't hose machine entirely.\n\t */\n\tif (handle)\n\t\terr = acpi_evaluate_object(handle, \"_RST\", NULL, NULL);\n\telse\n\t\terr = reset_control_reset(i2c_dev->rst);\n\n\tWARN_ON_ONCE(err);\n\n\tif (i2c_dev->is_dvc)\n\t\ttegra_dvc_init(i2c_dev);\n\n\tval = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |\n\t      FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);\n\n\tif (i2c_dev->hw->has_multi_master_mode)\n\t\tval |= I2C_CNFG_MULTI_MASTER_MODE;\n\n\ti2c_writel(i2c_dev, val, I2C_CNFG);\n\ti2c_writel(i2c_dev, 0, I2C_INT_MASK);\n\n\tif (i2c_dev->is_vi)\n\t\ttegra_i2c_vi_init(i2c_dev);\n\n\tswitch (t->bus_freq_hz) {\n\tcase I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:\n\tdefault:\n\t\ttlow = i2c_dev->hw->tlow_fast_fastplus_mode;\n\t\tthigh = i2c_dev->hw->thigh_fast_fastplus_mode;\n\t\ttsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;\n\n\t\tif (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)\n\t\t\tnon_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;\n\t\telse\n\t\t\tnon_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;\n\t\tbreak;\n\n\tcase 0 ... I2C_MAX_STANDARD_MODE_FREQ:\n\t\ttlow = i2c_dev->hw->tlow_std_mode;\n\t\tthigh = i2c_dev->hw->thigh_std_mode;\n\t\ttsu_thd = i2c_dev->hw->setup_hold_time_std_mode;\n\t\tnon_hs_mode = i2c_dev->hw->clk_divisor_std_mode;\n\t\tbreak;\n\t}\n\n\t/* make sure clock divisor programmed correctly */\n\tclk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,\n\t\t\t\t i2c_dev->hw->clk_divisor_hs_mode) |\n\t\t      FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);\n\ti2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);\n\n\tif (i2c_dev->hw->has_interface_timing_reg) {\n\t\tval = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |\n\t\t      FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);\n\t\ti2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);\n\t}\n\n\t/*\n\t * Configure setup and hold times only when tsu_thd is non-zero.\n\t * Otherwise, preserve the chip default values.\n\t */\n\tif (i2c_dev->hw->has_interface_timing_reg && tsu_thd)\n\t\ti2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);\n\n\tclk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);\n\n\terr = clk_set_rate(i2c_dev->div_clk,\n\t\t\t   t->bus_freq_hz * clk_multiplier);\n\tif (err) {\n\t\tdev_err(i2c_dev->dev, \"failed to set div-clk rate: %d\\n\", err);\n\t\treturn err;\n\t}\n\n\tif (!i2c_dev->is_dvc && !i2c_dev->is_vi) {\n\t\tu32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);\n\n\t\tsl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;\n\t\ti2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);\n\t\ti2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);\n\t\ti2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);\n\t}\n\n\terr = tegra_i2c_flush_fifos(i2c_dev);\n\tif (err)\n\t\treturn err;\n\n\tif (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)\n\t\ti2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);\n\n\terr = tegra_i2c_wait_for_config_load(i2c_dev);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}",
        "static int skl_int3472_tps68470_calc_type(struct acpi_device *adev)\n{\n\tstruct int3472_cldb cldb = { 0 };\n\tint ret;\n": "static int skl_int3472_tps68470_calc_type(struct acpi_device *adev)\n{\n\tstruct int3472_cldb cldb = { 0 };\n\tint ret;\n\n\t/*\n\t * A CLDB buffer that exists, but which does not match our expectations\n\t * should trigger an error so we don't blindly continue.\n\t */\n\tret = skl_int3472_fill_cldb(adev, &cldb);\n\tif (ret && ret != -ENODEV)\n\t\treturn ret;\n\n\tif (ret)\n\t\treturn DESIGNED_FOR_CHROMEOS;\n\n\tif (cldb.control_logic_type != 2)\n\t\treturn -EINVAL;\n\n\treturn DESIGNED_FOR_WINDOWS;\n}",
        "static void test_syscalls_with_x32(int msb)\n{\n\t/*\n\t * Syscalls 512-547 are \"x32\" syscalls.  They are\n\t * intended to be called with the x32 (0x40000000) bit": "static void test_syscalls_with_x32(int msb)\n{\n\t/*\n\t * Syscalls 512-547 are \"x32\" syscalls.  They are\n\t * intended to be called with the x32 (0x40000000) bit\n\t * set.  Calling them without the x32 bit set is\n\t * nonsense and should not work.\n\t */\n\trun(\"Checking x32 syscalls as 64 bit\\n\");\n\tcheck_for(msb, 512, 547, -ENOSYS);\n\n\trun(\"Checking some common syscalls as x32\\n\");\n\tcheck_zero(msb, SYS_READ   | X32_BIT);\n\tcheck_zero(msb, SYS_WRITE  | X32_BIT);\n\n\trun(\"Checking some x32 syscalls as x32\\n\");\n\tcheck_zero(msb, X32_READV  | X32_BIT);\n\tcheck_zero(msb, X32_WRITEV | X32_BIT);\n\n\trun(\"Checking some 64-bit syscalls as x32\\n\");\n\tcheck_enosys(msb, X64_IOCTL  | X32_BIT);\n\tcheck_enosys(msb, X64_READV  | X32_BIT);\n\tcheck_enosys(msb, X64_WRITEV | X32_BIT);\n}",
        "static void *display_thread(void *arg)\n{\n\tstruct pollfd stdin_poll = { .fd = 0, .events = POLLIN };\n\tstruct termios save;\n\tstruct perf_top *top = arg;": "static void *display_thread(void *arg)\n{\n\tstruct pollfd stdin_poll = { .fd = 0, .events = POLLIN };\n\tstruct termios save;\n\tstruct perf_top *top = arg;\n\tint delay_msecs, c;\n\n\t/* In order to read symbols from other namespaces perf to  needs to call\n\t * setns(2).  This isn't permitted if the struct_fs has multiple users.\n\t * unshare(2) the fs so that we may continue to setns into namespaces\n\t * that we're observing.\n\t */\n\tunshare(CLONE_FS);\n\n\tprctl(PR_SET_NAME, \"perf-top-UI\", 0, 0, 0);\n\n\tdisplay_setup_sig();\n\tpthread__unblock_sigwinch();\nrepeat:\n\tdelay_msecs = top->delay_secs * MSEC_PER_SEC;\n\tset_term_quiet_input(&save);\n\t/* trash return*/\n\tclearerr(stdin);\n\tif (poll(&stdin_poll, 1, 0) > 0)\n\t\tgetc(stdin);\n\n\twhile (!done) {\n\t\tperf_top__print_sym_table(top);\n\t\t/*\n\t\t * Either timeout expired or we got an EINTR due to SIGWINCH,\n\t\t * refresh screen in both cases.\n\t\t */\n\t\tswitch (poll(&stdin_poll, 1, delay_msecs)) {\n\t\tcase 0:\n\t\t\tcontinue;\n\t\tcase -1:\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\t\t\t__fallthrough;\n\t\tdefault:\n\t\t\tc = getc(stdin);\n\t\t\ttcsetattr(0, TCSAFLUSH, &save);\n\n\t\t\tif (perf_top__handle_keypress(top, c))\n\t\t\t\tgoto repeat;\n\t\t\tstop_top();\n\t\t}\n\t}\n\n\ttcsetattr(0, TCSAFLUSH, &save);\n\treturn NULL;\n}",
        "static void kmalloc_memmove_negative_size(struct kunit *test)\n{\n\tchar *ptr;\n\tsize_t size = 64;\n\tsize_t invalid_size = -2;": "static void kmalloc_memmove_negative_size(struct kunit *test)\n{\n\tchar *ptr;\n\tsize_t size = 64;\n\tsize_t invalid_size = -2;\n\n\t/*\n\t * Hardware tag-based mode doesn't check memmove for negative size.\n\t * As a result, this test introduces a side-effect memory corruption,\n\t * which can result in a crash.\n\t */\n\tKASAN_TEST_NEEDS_CONFIG_OFF(test, CONFIG_KASAN_HW_TAGS);\n\n\tptr = kmalloc(size, GFP_KERNEL);\n\tKUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);\n\n\tmemset((char *)ptr, 0, 64);\n\tOPTIMIZER_HIDE_VAR(ptr);\n\tOPTIMIZER_HIDE_VAR(invalid_size);\n\tKUNIT_EXPECT_KASAN_FAIL(test,\n\t\tmemmove((char *)ptr, (char *)ptr + 4, invalid_size));\n\tkfree(ptr);\n}",
        "static void guest_code(struct test_args *args)\n{\n\tuint32_t i, nr_irqs = args->nr_irqs;\n\tbool level_sensitive = args->level_sensitive;\n\tstruct kvm_inject_desc *f, *inject_fns;": "static void guest_code(struct test_args *args)\n{\n\tuint32_t i, nr_irqs = args->nr_irqs;\n\tbool level_sensitive = args->level_sensitive;\n\tstruct kvm_inject_desc *f, *inject_fns;\n\n\tgic_init(GIC_V3, 1, dist, redist);\n\n\tfor (i = 0; i < nr_irqs; i++)\n\t\tgic_irq_enable(i);\n\n\tfor (i = MIN_SPI; i < nr_irqs; i++)\n\t\tgic_irq_set_config(i, !level_sensitive);\n\n\tgic_set_eoi_split(args->eoi_split);\n\n\treset_priorities(args);\n\tgic_set_priority_mask(CPU_PRIO_MASK);\n\n\tinject_fns  = level_sensitive ? inject_level_fns\n\t\t\t\t      : inject_edge_fns;\n\n\tlocal_irq_enable();\n\n\t/* Start the tests. */\n\tfor_each_supported_inject_fn(args, inject_fns, f) {\n\t\ttest_injection(args, f);\n\t\ttest_preemption(args, f);\n\t\ttest_injection_failure(args, f);\n\t}\n\n\t/*\n\t * Restore the active state of IRQs. This would happen when live\n\t * migrating IRQs in the middle of being handled.\n\t */\n\tfor_each_supported_activate_fn(args, set_active_fns, f)\n\t\ttest_restore_active(args, f);\n\n\tGUEST_DONE();\n}",
        "static int add_root_nvdimm_bridge(struct device *match, void *data)\n{\n\tstruct cxl_decoder *cxld;\n\tstruct cxl_port *root_port = data;\n\tstruct cxl_nvdimm_bridge *cxl_nvb;": "static int add_root_nvdimm_bridge(struct device *match, void *data)\n{\n\tstruct cxl_decoder *cxld;\n\tstruct cxl_port *root_port = data;\n\tstruct cxl_nvdimm_bridge *cxl_nvb;\n\tstruct device *host = root_port->dev.parent;\n\n\tif (!is_root_decoder(match))\n\t\treturn 0;\n\n\tcxld = to_cxl_decoder(match);\n\tif (!(cxld->flags & CXL_DECODER_F_PMEM))\n\t\treturn 0;\n\n\tcxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);\n\tif (IS_ERR(cxl_nvb)) {\n\t\tdev_dbg(host, \"failed to register pmem\\n\");\n\t\treturn PTR_ERR(cxl_nvb);\n\t}\n\tdev_dbg(host, \"%s: add: %s\\n\", dev_name(&root_port->dev),\n\t\tdev_name(&cxl_nvb->dev));\n\treturn 1;\n}",
        "static int fexit_test(struct fexit_test_lskel *fexit_skel)\n{\n\tint err, prog_fd, i;\n\tint link_fd;\n\t__u64 *result;": "static int fexit_test(struct fexit_test_lskel *fexit_skel)\n{\n\tint err, prog_fd, i;\n\tint link_fd;\n\t__u64 *result;\n\tLIBBPF_OPTS(bpf_test_run_opts, topts);\n\n\terr = fexit_test_lskel__attach(fexit_skel);\n\tif (!ASSERT_OK(err, \"fexit_attach\"))\n\t\treturn err;\n\n\t/* Check that already linked program can't be attached again. */\n\tlink_fd = fexit_test_lskel__test1__attach(fexit_skel);\n\tif (!ASSERT_LT(link_fd, 0, \"fexit_attach_link\"))\n\t\treturn -1;\n\n\tprog_fd = fexit_skel->progs.test1.prog_fd;\n\terr = bpf_prog_test_run_opts(prog_fd, &topts);\n\tASSERT_OK(err, \"test_run\");\n\tASSERT_EQ(topts.retval, 0, \"test_run\");\n\n\tresult = (__u64 *)fexit_skel->bss;\n\tfor (i = 0; i < sizeof(*fexit_skel->bss) / sizeof(__u64); i++) {\n\t\tif (!ASSERT_EQ(result[i], 1, \"fexit_result\"))\n\t\t\treturn -1;\n\t}\n\n\tfexit_test_lskel__detach(fexit_skel);\n\n\t/* zero results for re-attach test */\n\tmemset(fexit_skel->bss, 0, sizeof(*fexit_skel->bss));\n\treturn 0;\n}",
        "static int init_pci_top_obj(struct uv_pci_top_obj *top_obj, char *line)\n{\n\tchar *start;\n\tchar type[11], location[14], ppb_addr[15];\n\tint str_cnt, ret;": "static int init_pci_top_obj(struct uv_pci_top_obj *top_obj, char *line)\n{\n\tchar *start;\n\tchar type[11], location[14], ppb_addr[15];\n\tint str_cnt, ret;\n\tunsigned int tmp_match[2];\n\n\t// Minimum line length\n\tif (strlen(line) < 36)\n\t\treturn -EINVAL;\n\n\t//Line must match format \"pcibus %4x:%2x\" to be valid\n\tstr_cnt = sscanf(line, \"pcibus %4x:%2x\", &tmp_match[0], &tmp_match[1]);\n\tif (str_cnt < 2)\n\t\treturn -EINVAL;\n\n\t/* Connect pcibus to segment:bus number with '_'\n\t * to concatenate name tokens.\n\t * pcibus 0000:00 ... -> pcibus_0000:00 ...\n\t */\n\tline[6] = '_';\n\n\t/* Null terminate after the concatencated name tokens\n\t * to produce kobj name string.\n\t */\n\tline[14] = '\\0';\n\n\t// Use start to index after name tokens string for remainder of line info.\n\tstart = &line[15];\n\n\ttop_obj->iio_stack = -1;\n\ttop_obj->slot = -1;\n\n\t/* r001i01b00h0 BASE IO (IIO Stack 0)\n\t * r001i01b00h1 PCIe IO (IIO Stack 1)\n\t * r001i01b03h1 PCIe SLOT\n\t * r001i01b00h0 NODE IO\n\t * r001i01b00h0 Riser\n\t * (IIO Stack #) may not be present.\n\t */\n\tif (start[0] == 'r') {\n\t\tstr_cnt = sscanf(start, \"%13s %10[^(] %*s %*s %d)\",\n\t\t\t\tlocation, type, &top_obj->iio_stack);\n\t\tif (str_cnt < 2)\n\t\t\treturn -EINVAL;\n\t\ttop_obj->type = kstrdup(type, GFP_KERNEL);\n\t\tif (!top_obj->type)\n\t\t\treturn -ENOMEM;\n\t\ttop_obj->location = kstrdup(location, GFP_KERNEL);\n\t\tif (!top_obj->location) {\n\t\t\tkfree(top_obj->type);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\t/* PPB at 0000:80:00.00 (slot 3)\n\t * (slot #) may not be present.\n\t */\n\telse if (start[0] == 'P') {\n\t\tstr_cnt = sscanf(start, \"%10s %*s %14s %*s %d)\",\n\t\t\t\ttype, ppb_addr, &top_obj->slot);\n\t\tif (str_cnt < 2)\n\t\t\treturn -EINVAL;\n\t\ttop_obj->type = kstrdup(type, GFP_KERNEL);\n\t\tif (!top_obj->type)\n\t\t\treturn -ENOMEM;\n\t\ttop_obj->ppb_addr = kstrdup(ppb_addr, GFP_KERNEL);\n\t\tif (!top_obj->ppb_addr) {\n\t\t\tkfree(top_obj->type);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t} else\n\t\treturn -EINVAL;\n\n\ttop_obj->kobj.kset = uv_pcibus_kset;\n\n\tret = kobject_init_and_add(&top_obj->kobj, &uv_pci_top_attr_type, NULL, \"%s\", line);\n\tif (ret)\n\t\tgoto err_add_sysfs;\n\n\tif (top_obj->type) {\n\t\tret = sysfs_create_file(&top_obj->kobj, &uv_pci_type_attribute.attr);\n\t\tif (ret)\n\t\t\tgoto err_add_sysfs;\n\t}\n\tif (top_obj->location) {\n\t\tret = sysfs_create_file(&top_obj->kobj, &uv_pci_location_attribute.attr);\n\t\tif (ret)\n\t\t\tgoto err_add_sysfs;\n\t}\n\tif (top_obj->iio_stack >= 0) {\n\t\tret = sysfs_create_file(&top_obj->kobj, &uv_pci_iio_stack_attribute.attr);\n\t\tif (ret)\n\t\t\tgoto err_add_sysfs;\n\t}\n\tif (top_obj->ppb_addr) {\n\t\tret = sysfs_create_file(&top_obj->kobj, &uv_pci_ppb_addr_attribute.attr);\n\t\tif (ret)\n\t\t\tgoto err_add_sysfs;\n\t}\n\tif (top_obj->slot >= 0) {\n\t\tret = sysfs_create_file(&top_obj->kobj, &uv_pci_slot_attribute.attr);\n\t\tif (ret)\n\t\t\tgoto err_add_sysfs;\n\t}\n\n\tkobject_uevent(&top_obj->kobj, KOBJ_ADD);\n\treturn 0;\n\nerr_add_sysfs:\n\tkobject_put(&top_obj->kobj);\n\treturn ret;\n}",
        "static int sba_proc_info(struct seq_file *m, void *p)\n{\n\tstruct sba_device *sba_dev = sba_list;\n\tstruct ioc *ioc = &sba_dev->ioc[0];\t/* FIXME: Multi-IOC support! */\n\tint total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */": "static int sba_proc_info(struct seq_file *m, void *p)\n{\n\tstruct sba_device *sba_dev = sba_list;\n\tstruct ioc *ioc = &sba_dev->ioc[0];\t/* FIXME: Multi-IOC support! */\n\tint total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */\n#ifdef SBA_COLLECT_STATS\n\tunsigned long avg = 0, min, max;\n#endif\n\tint i;\n\n\tseq_printf(m, \"%s rev %d.%d\\n\",\n\t\t   sba_dev->name,\n\t\t   (sba_dev->hw_rev & 0x7) + 1,\n\t\t   (sba_dev->hw_rev & 0x18) >> 3);\n\tseq_printf(m, \"IO PDIR size    : %d bytes (%d entries)\\n\",\n\t\t   (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */\n\t\t   total_pages);\n\n\tseq_printf(m, \"Resource bitmap : %d bytes (%d pages)\\n\",\n\t\t   ioc->res_size, ioc->res_size << 3);   /* 8 bits per byte */\n\n\tseq_printf(m, \"LMMIO_BASE/MASK/ROUTE %08x %08x %08x\\n\",\n\t\t   READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),\n\t\t   READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),\n\t\t   READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));\n\n\tfor (i=0; i<4; i++)\n\t\tseq_printf(m, \"DIR%d_BASE/MASK/ROUTE %08x %08x %08x\\n\",\n\t\t\t   i,\n\t\t\t   READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE  + i*0x18),\n\t\t\t   READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK  + i*0x18),\n\t\t\t   READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));\n\n#ifdef SBA_COLLECT_STATS\n\tseq_printf(m, \"IO PDIR entries : %ld free  %ld used (%d%%)\\n\",\n\t\t   total_pages - ioc->used_pages, ioc->used_pages,\n\t\t   (int)(ioc->used_pages * 100 / total_pages));\n\n\tmin = max = ioc->avg_search[0];\n\tfor (i = 0; i < SBA_SEARCH_SAMPLE; i++) {\n\t\tavg += ioc->avg_search[i];\n\t\tif (ioc->avg_search[i] > max) max = ioc->avg_search[i];\n\t\tif (ioc->avg_search[i] < min) min = ioc->avg_search[i];\n\t}\n\tavg /= SBA_SEARCH_SAMPLE;\n\tseq_printf(m, \"  Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\\n\",\n\t\t   min, avg, max);\n\n\tseq_printf(m, \"pci_map_single(): %12ld calls  %12ld pages (avg %d/1000)\\n\",\n\t\t   ioc->msingle_calls, ioc->msingle_pages,\n\t\t   (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));\n\n\t/* KLUGE - unmap_sg calls unmap_single for each mapped page */\n\tmin = ioc->usingle_calls;\n\tmax = ioc->usingle_pages - ioc->usg_pages;\n\tseq_printf(m, \"pci_unmap_single: %12ld calls  %12ld pages (avg %d/1000)\\n\",\n\t\t   min, max, (int)((max * 1000)/min));\n\n\tseq_printf(m, \"pci_map_sg()    : %12ld calls  %12ld pages (avg %d/1000)\\n\",\n\t\t   ioc->msg_calls, ioc->msg_pages,\n\t\t   (int)((ioc->msg_pages * 1000)/ioc->msg_calls));\n\n\tseq_printf(m, \"pci_unmap_sg()  : %12ld calls  %12ld pages (avg %d/1000)\\n\",\n\t\t   ioc->usg_calls, ioc->usg_pages,\n\t\t   (int)((ioc->usg_pages * 1000)/ioc->usg_calls));\n#endif\n\n\treturn 0;\n}",
        "static int __init fwserial_init(void)\n{\n\tint err, num_loops = !!(create_loop_dev);\n\n\t/* XXX: placeholder for a \"firewire\" debugfs node */": "static int __init fwserial_init(void)\n{\n\tint err, num_loops = !!(create_loop_dev);\n\n\t/* XXX: placeholder for a \"firewire\" debugfs node */\n\tfwserial_debugfs = debugfs_create_dir(KBUILD_MODNAME, NULL);\n\n\t/* num_ttys/num_ports must not be set above the static alloc avail */\n\tif (num_ttys + num_loops > MAX_CARD_PORTS)\n\t\tnum_ttys = MAX_CARD_PORTS - num_loops;\n\n\tnum_ports = num_ttys + num_loops;\n\n\tfwtty_driver = tty_alloc_driver(MAX_TOTAL_PORTS, TTY_DRIVER_REAL_RAW\n\t\t\t\t\t| TTY_DRIVER_DYNAMIC_DEV);\n\tif (IS_ERR(fwtty_driver)) {\n\t\terr = PTR_ERR(fwtty_driver);\n\t\tgoto remove_debugfs;\n\t}\n\n\tfwtty_driver->driver_name\t= KBUILD_MODNAME;\n\tfwtty_driver->name\t\t= tty_dev_name;\n\tfwtty_driver->major\t\t= 0;\n\tfwtty_driver->minor_start\t= 0;\n\tfwtty_driver->type\t\t= TTY_DRIVER_TYPE_SERIAL;\n\tfwtty_driver->subtype\t\t= SERIAL_TYPE_NORMAL;\n\tfwtty_driver->init_termios\t    = tty_std_termios;\n\tfwtty_driver->init_termios.c_cflag  |= CLOCAL;\n\ttty_set_operations(fwtty_driver, &fwtty_ops);\n\n\terr = tty_register_driver(fwtty_driver);\n\tif (err) {\n\t\tpr_err(\"register tty driver failed (%d)\\n\", err);\n\t\tgoto put_tty;\n\t}\n\n\tif (create_loop_dev) {\n\t\tfwloop_driver = tty_alloc_driver(MAX_TOTAL_PORTS / num_ports,\n\t\t\t\t\t\t TTY_DRIVER_REAL_RAW\n\t\t\t\t\t\t | TTY_DRIVER_DYNAMIC_DEV);\n\t\tif (IS_ERR(fwloop_driver)) {\n\t\t\terr = PTR_ERR(fwloop_driver);\n\t\t\tgoto unregister_driver;\n\t\t}\n\n\t\tfwloop_driver->driver_name\t= KBUILD_MODNAME \"_loop\";\n\t\tfwloop_driver->name\t\t= loop_dev_name;\n\t\tfwloop_driver->major\t\t= 0;\n\t\tfwloop_driver->minor_start\t= 0;\n\t\tfwloop_driver->type\t\t= TTY_DRIVER_TYPE_SERIAL;\n\t\tfwloop_driver->subtype\t\t= SERIAL_TYPE_NORMAL;\n\t\tfwloop_driver->init_termios\t    = tty_std_termios;\n\t\tfwloop_driver->init_termios.c_cflag  |= CLOCAL;\n\t\ttty_set_operations(fwloop_driver, &fwloop_ops);\n\n\t\terr = tty_register_driver(fwloop_driver);\n\t\tif (err) {\n\t\t\tpr_err(\"register loop driver failed (%d)\\n\", err);\n\t\t\tgoto put_loop;\n\t\t}\n\t}\n\n\tfwtty_txn_cache = kmem_cache_create(\"fwtty_txn_cache\",\n\t\t\t\t\t    sizeof(struct fwtty_transaction),\n\t\t\t\t\t    0, 0, NULL);\n\tif (!fwtty_txn_cache) {\n\t\terr = -ENOMEM;\n\t\tgoto unregister_loop;\n\t}\n\n\t/*\n\t * Ideally, this address handler would be registered per local node\n\t * (rather than the same handler for all local nodes). However,\n\t * since the firewire core requires the config rom descriptor *before*\n\t * the local unit device(s) are created, a single management handler\n\t * must suffice for all local serial units.\n\t */\n\tfwserial_mgmt_addr_handler.length = sizeof(struct fwserial_mgmt_pkt);\n\tfwserial_mgmt_addr_handler.address_callback = fwserial_mgmt_handler;\n\n\terr = fw_core_add_address_handler(&fwserial_mgmt_addr_handler,\n\t\t\t\t\t  &fwserial_mgmt_addr_region);\n\tif (err) {\n\t\tpr_err(\"add management handler failed (%d)\\n\", err);\n\t\tgoto destroy_cache;\n\t}\n\n\tfwserial_unit_directory_data.unit_addr_offset =\n\t\tFW_UNIT_ADDRESS(fwserial_mgmt_addr_handler.offset);\n\terr = fw_core_add_descriptor(&fwserial_unit_directory);\n\tif (err) {\n\t\tpr_err(\"add unit descriptor failed (%d)\\n\", err);\n\t\tgoto remove_handler;\n\t}\n\n\terr = driver_register(&fwserial_driver.driver);\n\tif (err) {\n\t\tpr_err(\"register fwserial driver failed (%d)\\n\", err);\n\t\tgoto remove_descriptor;\n\t}\n\n\treturn 0;\n\nremove_descriptor:\n\tfw_core_remove_descriptor(&fwserial_unit_directory);\nremove_handler:\n\tfw_core_remove_address_handler(&fwserial_mgmt_addr_handler);\ndestroy_cache:\n\tkmem_cache_destroy(fwtty_txn_cache);\nunregister_loop:\n\tif (create_loop_dev)\n\t\ttty_unregister_driver(fwloop_driver);\nput_loop:\n\tif (create_loop_dev)\n\t\ttty_driver_kref_put(fwloop_driver);\nunregister_driver:\n\ttty_unregister_driver(fwtty_driver);\nput_tty:\n\ttty_driver_kref_put(fwtty_driver);\nremove_debugfs:\n\tdebugfs_remove_recursive(fwserial_debugfs);\n\n\treturn err;\n}",
        "static void set_pool_mode(struct pool *pool, enum pool_mode new_mode)\n{\n\tstruct pool_c *pt = pool->ti->private;\n\tbool needs_check = dm_pool_metadata_needs_check(pool->pmd);\n\tenum pool_mode old_mode = get_pool_mode(pool);": "static void set_pool_mode(struct pool *pool, enum pool_mode new_mode)\n{\n\tstruct pool_c *pt = pool->ti->private;\n\tbool needs_check = dm_pool_metadata_needs_check(pool->pmd);\n\tenum pool_mode old_mode = get_pool_mode(pool);\n\tunsigned long no_space_timeout = READ_ONCE(no_space_timeout_secs) * HZ;\n\n\t/*\n\t * Never allow the pool to transition to PM_WRITE mode if user\n\t * intervention is required to verify metadata and data consistency.\n\t */\n\tif (new_mode == PM_WRITE && needs_check) {\n\t\tDMERR(\"%s: unable to switch pool to write mode until repaired.\",\n\t\t      dm_device_name(pool->pool_md));\n\t\tif (old_mode != new_mode)\n\t\t\tnew_mode = old_mode;\n\t\telse\n\t\t\tnew_mode = PM_READ_ONLY;\n\t}\n\t/*\n\t * If we were in PM_FAIL mode, rollback of metadata failed.  We're\n\t * not going to recover without a thin_repair.\tSo we never let the\n\t * pool move out of the old mode.\n\t */\n\tif (old_mode == PM_FAIL)\n\t\tnew_mode = old_mode;\n\n\tswitch (new_mode) {\n\tcase PM_FAIL:\n\t\tdm_pool_metadata_read_only(pool->pmd);\n\t\tpool->process_bio = process_bio_fail;\n\t\tpool->process_discard = process_bio_fail;\n\t\tpool->process_cell = process_cell_fail;\n\t\tpool->process_discard_cell = process_cell_fail;\n\t\tpool->process_prepared_mapping = process_prepared_mapping_fail;\n\t\tpool->process_prepared_discard = process_prepared_discard_fail;\n\n\t\terror_retry_list(pool);\n\t\tbreak;\n\n\tcase PM_OUT_OF_METADATA_SPACE:\n\tcase PM_READ_ONLY:\n\t\tdm_pool_metadata_read_only(pool->pmd);\n\t\tpool->process_bio = process_bio_read_only;\n\t\tpool->process_discard = process_bio_success;\n\t\tpool->process_cell = process_cell_read_only;\n\t\tpool->process_discard_cell = process_cell_success;\n\t\tpool->process_prepared_mapping = process_prepared_mapping_fail;\n\t\tpool->process_prepared_discard = process_prepared_discard_success;\n\n\t\terror_retry_list(pool);\n\t\tbreak;\n\n\tcase PM_OUT_OF_DATA_SPACE:\n\t\t/*\n\t\t * Ideally we'd never hit this state; the low water mark\n\t\t * would trigger userland to extend the pool before we\n\t\t * completely run out of data space.  However, many small\n\t\t * IOs to unprovisioned space can consume data space at an\n\t\t * alarming rate.  Adjust your low water mark if you're\n\t\t * frequently seeing this mode.\n\t\t */\n\t\tpool->out_of_data_space = true;\n\t\tpool->process_bio = process_bio_read_only;\n\t\tpool->process_discard = process_discard_bio;\n\t\tpool->process_cell = process_cell_read_only;\n\t\tpool->process_prepared_mapping = process_prepared_mapping;\n\t\tset_discard_callbacks(pool);\n\n\t\tif (!pool->pf.error_if_no_space && no_space_timeout)\n\t\t\tqueue_delayed_work(pool->wq, &pool->no_space_timeout, no_space_timeout);\n\t\tbreak;\n\n\tcase PM_WRITE:\n\t\tif (old_mode == PM_OUT_OF_DATA_SPACE)\n\t\t\tcancel_delayed_work_sync(&pool->no_space_timeout);\n\t\tpool->out_of_data_space = false;\n\t\tpool->pf.error_if_no_space = pt->requested_pf.error_if_no_space;\n\t\tdm_pool_metadata_read_write(pool->pmd);\n\t\tpool->process_bio = process_bio;\n\t\tpool->process_discard = process_discard_bio;\n\t\tpool->process_cell = process_cell;\n\t\tpool->process_prepared_mapping = process_prepared_mapping;\n\t\tset_discard_callbacks(pool);\n\t\tbreak;\n\t}\n\n\tpool->pf.mode = new_mode;\n\t/*\n\t * The pool mode may have changed, sync it so bind_control_target()\n\t * doesn't cause an unexpected mode transition on resume.\n\t */\n\tpt->adjusted_pf.mode = new_mode;\n\n\tif (old_mode != new_mode)\n\t\tnotify_of_pool_mode_change(pool);\n}",
        "static int avs_modext_create(struct avs_dev *adev, struct avs_path_module *mod)\n{\n\tstruct avs_tplg_module *t = mod->template;\n\tstruct avs_tplg_modcfg_ext *tcfg = t->cfg_ext;\n\tstruct avs_modcfg_ext *cfg;": "static int avs_modext_create(struct avs_dev *adev, struct avs_path_module *mod)\n{\n\tstruct avs_tplg_module *t = mod->template;\n\tstruct avs_tplg_modcfg_ext *tcfg = t->cfg_ext;\n\tstruct avs_modcfg_ext *cfg;\n\tsize_t cfg_size, num_pins;\n\tint ret, i;\n\n\tnum_pins = tcfg->generic.num_input_pins + tcfg->generic.num_output_pins;\n\tcfg_size = sizeof(*cfg) + sizeof(*cfg->pin_fmts) * num_pins;\n\n\tcfg = kzalloc(cfg_size, GFP_KERNEL);\n\tif (!cfg)\n\t\treturn -ENOMEM;\n\n\tcfg->base.cpc = t->cfg_base->cpc;\n\tcfg->base.ibs = t->cfg_base->ibs;\n\tcfg->base.obs = t->cfg_base->obs;\n\tcfg->base.is_pages = t->cfg_base->is_pages;\n\tcfg->base.audio_fmt = *t->in_fmt;\n\tcfg->num_input_pins = tcfg->generic.num_input_pins;\n\tcfg->num_output_pins = tcfg->generic.num_output_pins;\n\n\t/* configure pin formats */\n\tfor (i = 0; i < num_pins; i++) {\n\t\tstruct avs_tplg_pin_format *tpin = &tcfg->generic.pin_fmts[i];\n\t\tstruct avs_pin_format *pin = &cfg->pin_fmts[i];\n\n\t\tpin->pin_index = tpin->pin_index;\n\t\tpin->iobs = tpin->iobs;\n\t\tpin->audio_fmt = *tpin->fmt;\n\t}\n\n\tret = avs_dsp_init_module(adev, mod->module_id, mod->owner->instance_id,\n\t\t\t\t  t->core_id, t->domain, cfg, cfg_size,\n\t\t\t\t  &mod->instance_id);\n\tkfree(cfg);\n\treturn ret;\n}",
        "static void detach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se)\n{\n\tdequeue_load_avg(cfs_rq, se);\n\tsub_positive(&cfs_rq->avg.util_avg, se->avg.util_avg);\n\tsub_positive(&cfs_rq->avg.util_sum, se->avg.util_sum);": "static void detach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se)\n{\n\tdequeue_load_avg(cfs_rq, se);\n\tsub_positive(&cfs_rq->avg.util_avg, se->avg.util_avg);\n\tsub_positive(&cfs_rq->avg.util_sum, se->avg.util_sum);\n\t/* See update_cfs_rq_load_avg() */\n\tcfs_rq->avg.util_sum = max_t(u32, cfs_rq->avg.util_sum,\n\t\t\t\t\t  cfs_rq->avg.util_avg * PELT_MIN_DIVIDER);\n\n\tsub_positive(&cfs_rq->avg.runnable_avg, se->avg.runnable_avg);\n\tsub_positive(&cfs_rq->avg.runnable_sum, se->avg.runnable_sum);\n\t/* See update_cfs_rq_load_avg() */\n\tcfs_rq->avg.runnable_sum = max_t(u32, cfs_rq->avg.runnable_sum,\n\t\t\t\t\t      cfs_rq->avg.runnable_avg * PELT_MIN_DIVIDER);\n\n\tadd_tg_cfs_propagate(cfs_rq, -se->avg.load_sum);\n\n\tcfs_rq_util_change(cfs_rq, 0);\n\n\ttrace_pelt_cfs_tp(cfs_rq);\n}",
        "static void l2cap_conf_rfc_get(struct l2cap_chan *chan, void *rsp, int len)\n{\n\tint type, olen;\n\tunsigned long val;\n\t/* Use sane default values in case a misbehaving remote device": "static void l2cap_conf_rfc_get(struct l2cap_chan *chan, void *rsp, int len)\n{\n\tint type, olen;\n\tunsigned long val;\n\t/* Use sane default values in case a misbehaving remote device\n\t * did not send an RFC or extended window size option.\n\t */\n\tu16 txwin_ext = chan->ack_win;\n\tstruct l2cap_conf_rfc rfc = {\n\t\t.mode = chan->mode,\n\t\t.retrans_timeout = cpu_to_le16(L2CAP_DEFAULT_RETRANS_TO),\n\t\t.monitor_timeout = cpu_to_le16(L2CAP_DEFAULT_MONITOR_TO),\n\t\t.max_pdu_size = cpu_to_le16(chan->imtu),\n\t\t.txwin_size = min_t(u16, chan->ack_win, L2CAP_DEFAULT_TX_WINDOW),\n\t};\n\n\tBT_DBG(\"chan %p, rsp %p, len %d\", chan, rsp, len);\n\n\tif ((chan->mode != L2CAP_MODE_ERTM) && (chan->mode != L2CAP_MODE_STREAMING))\n\t\treturn;\n\n\twhile (len >= L2CAP_CONF_OPT_SIZE) {\n\t\tlen -= l2cap_get_conf_opt(&rsp, &type, &olen, &val);\n\t\tif (len < 0)\n\t\t\tbreak;\n\n\t\tswitch (type) {\n\t\tcase L2CAP_CONF_RFC:\n\t\t\tif (olen != sizeof(rfc))\n\t\t\t\tbreak;\n\t\t\tmemcpy(&rfc, (void *)val, olen);\n\t\t\tbreak;\n\t\tcase L2CAP_CONF_EWS:\n\t\t\tif (olen != 2)\n\t\t\t\tbreak;\n\t\t\ttxwin_ext = val;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tswitch (rfc.mode) {\n\tcase L2CAP_MODE_ERTM:\n\t\tchan->retrans_timeout = le16_to_cpu(rfc.retrans_timeout);\n\t\tchan->monitor_timeout = le16_to_cpu(rfc.monitor_timeout);\n\t\tchan->mps = le16_to_cpu(rfc.max_pdu_size);\n\t\tif (test_bit(FLAG_EXT_CTRL, &chan->flags))\n\t\t\tchan->ack_win = min_t(u16, chan->ack_win, txwin_ext);\n\t\telse\n\t\t\tchan->ack_win = min_t(u16, chan->ack_win,\n\t\t\t\t\t      rfc.txwin_size);\n\t\tbreak;\n\tcase L2CAP_MODE_STREAMING:\n\t\tchan->mps    = le16_to_cpu(rfc.max_pdu_size);\n\t}\n}",
        "static int __init fan_init(struct ibm_init_struct *iibm)\n{\n\tunsigned long quirks;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_FAN,": "static int __init fan_init(struct ibm_init_struct *iibm)\n{\n\tunsigned long quirks;\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_FAN,\n\t\t\t\"initializing fan subdriver\\n\");\n\n\tmutex_init(&fan_mutex);\n\tfan_status_access_mode = TPACPI_FAN_NONE;\n\tfan_control_access_mode = TPACPI_FAN_WR_NONE;\n\tfan_control_commands = 0;\n\tfan_watchdog_maxinterval = 0;\n\ttp_features.fan_ctrl_status_undef = 0;\n\ttp_features.second_fan = 0;\n\ttp_features.second_fan_ctl = 0;\n\tfan_control_desired_level = 7;\n\n\tif (tpacpi_is_ibm()) {\n\t\tTPACPI_ACPIHANDLE_INIT(fans);\n\t\tTPACPI_ACPIHANDLE_INIT(gfan);\n\t\tTPACPI_ACPIHANDLE_INIT(sfan);\n\t}\n\n\tquirks = tpacpi_check_quirks(fan_quirk_table,\n\t\t\t\t     ARRAY_SIZE(fan_quirk_table));\n\n\tif (quirks & TPACPI_FAN_NOFAN) {\n\t\tpr_info(\"No integrated ThinkPad fan available\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tif (gfan_handle) {\n\t\t/* 570, 600e/x, 770e, 770x */\n\t\tfan_status_access_mode = TPACPI_FAN_RD_ACPI_GFAN;\n\t} else {\n\t\t/* all other ThinkPads: note that even old-style\n\t\t * ThinkPad ECs supports the fan control register */\n\t\tif (likely(acpi_ec_read(fan_status_offset,\n\t\t\t\t\t&fan_control_initial_status))) {\n\t\t\tint res;\n\t\t\tunsigned int speed;\n\n\t\t\tfan_status_access_mode = TPACPI_FAN_RD_TPEC;\n\t\t\tif (quirks & TPACPI_FAN_Q1)\n\t\t\t\tfan_quirk1_setup();\n\t\t\t/* Try and probe the 2nd fan */\n\t\t\ttp_features.second_fan = 1; /* needed for get_speed to work */\n\t\t\tres = fan2_get_speed(&speed);\n\t\t\tif (res >= 0) {\n\t\t\t\t/* It responded - so let's assume it's there */\n\t\t\t\ttp_features.second_fan = 1;\n\t\t\t\ttp_features.second_fan_ctl = 1;\n\t\t\t\tpr_info(\"secondary fan control detected & enabled\\n\");\n\t\t\t} else {\n\t\t\t\t/* Fan not auto-detected */\n\t\t\t\ttp_features.second_fan = 0;\n\t\t\t\tif (quirks & TPACPI_FAN_2FAN) {\n\t\t\t\t\ttp_features.second_fan = 1;\n\t\t\t\t\tpr_info(\"secondary fan support enabled\\n\");\n\t\t\t\t}\n\t\t\t\tif (quirks & TPACPI_FAN_2CTL) {\n\t\t\t\t\ttp_features.second_fan = 1;\n\t\t\t\t\ttp_features.second_fan_ctl = 1;\n\t\t\t\t\tpr_info(\"secondary fan control enabled\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tpr_err(\"ThinkPad ACPI EC access misbehaving, fan status and control unavailable\\n\");\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\n\tif (sfan_handle) {\n\t\t/* 570, 770x-JL */\n\t\tfan_control_access_mode = TPACPI_FAN_WR_ACPI_SFAN;\n\t\tfan_control_commands |=\n\t\t    TPACPI_FAN_CMD_LEVEL | TPACPI_FAN_CMD_ENABLE;\n\t} else {\n\t\tif (!gfan_handle) {\n\t\t\t/* gfan without sfan means no fan control */\n\t\t\t/* all other models implement TP EC 0x2f control */\n\n\t\t\tif (fans_handle) {\n\t\t\t\t/* X31, X40, X41 */\n\t\t\t\tfan_control_access_mode =\n\t\t\t\t    TPACPI_FAN_WR_ACPI_FANS;\n\t\t\t\tfan_control_commands |=\n\t\t\t\t    TPACPI_FAN_CMD_SPEED |\n\t\t\t\t    TPACPI_FAN_CMD_LEVEL |\n\t\t\t\t    TPACPI_FAN_CMD_ENABLE;\n\t\t\t} else {\n\t\t\t\tfan_control_access_mode = TPACPI_FAN_WR_TPEC;\n\t\t\t\tfan_control_commands |=\n\t\t\t\t    TPACPI_FAN_CMD_LEVEL |\n\t\t\t\t    TPACPI_FAN_CMD_ENABLE;\n\t\t\t}\n\t\t}\n\t}\n\n\tvdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_FAN,\n\t\t\"fan is %s, modes %d, %d\\n\",\n\t\tstr_supported(fan_status_access_mode != TPACPI_FAN_NONE ||\n\t\t  fan_control_access_mode != TPACPI_FAN_WR_NONE),\n\t\tfan_status_access_mode, fan_control_access_mode);\n\n\t/* fan control master switch */\n\tif (!fan_control_allowed) {\n\t\tfan_control_access_mode = TPACPI_FAN_WR_NONE;\n\t\tfan_control_commands = 0;\n\t\tdbg_printk(TPACPI_DBG_INIT | TPACPI_DBG_FAN,\n\t\t\t   \"fan control features disabled by parameter\\n\");\n\t}\n\n\t/* update fan_control_desired_level */\n\tif (fan_status_access_mode != TPACPI_FAN_NONE)\n\t\tfan_get_status_safe(NULL);\n\n\tif (fan_status_access_mode == TPACPI_FAN_NONE &&\n\t    fan_control_access_mode == TPACPI_FAN_WR_NONE)\n\t\treturn -ENODEV;\n\n\treturn 0;\n}",
        "static int pfuze_power_off_prepare(struct sys_off_data *data)\n{\n\tstruct pfuze_chip *syspm_pfuze_chip = data->cb_data;\n\n\tdev_info(syspm_pfuze_chip->dev, \"Configure standby mode for power off\");": "static int pfuze_power_off_prepare(struct sys_off_data *data)\n{\n\tstruct pfuze_chip *syspm_pfuze_chip = data->cb_data;\n\n\tdev_info(syspm_pfuze_chip->dev, \"Configure standby mode for power off\");\n\n\t/* Switch from default mode: APS/APS to APS/Off */\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,\n\t\t\t   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,\n\t\t\t   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,\n\t\t\t   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,\n\t\t\t   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,\n\t\t\t   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,\n\t\t\t   PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);\n\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,\n\t\t\t   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,\n\t\t\t   PFUZE100_VGENxSTBY);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,\n\t\t\t   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,\n\t\t\t   PFUZE100_VGENxSTBY);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,\n\t\t\t   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,\n\t\t\t   PFUZE100_VGENxSTBY);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,\n\t\t\t   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,\n\t\t\t   PFUZE100_VGENxSTBY);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,\n\t\t\t   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,\n\t\t\t   PFUZE100_VGENxSTBY);\n\tregmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,\n\t\t\t   PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,\n\t\t\t   PFUZE100_VGENxSTBY);\n\n\treturn NOTIFY_DONE;\n}",
        "static void ptrace_set_get_data(pid_t child, unsigned int vl)\n{\n\tvoid *write_buf;\n\tvoid *read_buf = NULL;\n\tstruct user_za_header *write_za;": "static void ptrace_set_get_data(pid_t child, unsigned int vl)\n{\n\tvoid *write_buf;\n\tvoid *read_buf = NULL;\n\tstruct user_za_header *write_za;\n\tstruct user_za_header *read_za;\n\tsize_t read_za_size = 0;\n\tunsigned int vq = sve_vq_from_vl(vl);\n\tint ret;\n\tsize_t data_size;\n\n\tdata_size = ZA_PT_SIZE(vq);\n\twrite_buf = malloc(data_size);\n\tif (!write_buf) {\n\t\tksft_test_result_fail(\"Error allocating %d byte buffer for VL %u\\n\",\n\t\t\t\t      data_size, vl);\n\t\treturn;\n\t}\n\twrite_za = write_buf;\n\n\t/* Set up some data and write it out */\n\tmemset(write_za, 0, data_size);\n\twrite_za->size = data_size;\n\twrite_za->vl = vl;\n\n\tfill_buf(write_buf + ZA_PT_ZA_OFFSET, ZA_PT_ZA_SIZE(vq));\n\n\tret = set_za(child, write_za);\n\tif (ret != 0) {\n\t\tksft_test_result_fail(\"Failed to set VL %u data\\n\", vl);\n\t\tgoto out;\n\t}\n\n\t/* Read the data back */\n\tif (!get_za(child, (void **)&read_buf, &read_za_size)) {\n\t\tksft_test_result_fail(\"Failed to read VL %u data\\n\", vl);\n\t\tgoto out;\n\t}\n\tread_za = read_buf;\n\n\t/* We might read more data if there's extensions we don't know */\n\tif (read_za->size < write_za->size) {\n\t\tksft_test_result_fail(\"VL %u wrote %d bytes, only read %d\\n\",\n\t\t\t\t      vl, write_za->size, read_za->size);\n\t\tgoto out_read;\n\t}\n\n\tksft_test_result(memcmp(write_buf + ZA_PT_ZA_OFFSET,\n\t\t\t\tread_buf + ZA_PT_ZA_OFFSET,\n\t\t\t\tZA_PT_ZA_SIZE(vq)) == 0,\n\t\t\t \"Data match for VL %u\\n\", vl);\n\nout_read:\n\tfree(read_buf);\nout:\n\tfree(write_buf);\n}",
        "static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)\n{\n\tu16 val, cnt, cnt1 ;\n\n\tbnx2x_cl45_read(bp, phy,": "static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)\n{\n\tu16 val, cnt, cnt1 ;\n\n\tbnx2x_cl45_read(bp, phy,\n\t\t\tMDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_8073_CHIP_REV, &val);\n\n\tif (val > 0) {\n\t\t/* No need to workaround in 8073 A1 */\n\t\treturn 0;\n\t}\n\t/* XAUI workaround in 8073 A0: */\n\n\t/* After loading the boot ROM and restarting Autoneg, poll\n\t * Dev1, Reg $C820:\n\t */\n\n\tfor (cnt = 0; cnt < 1000; cnt++) {\n\t\tbnx2x_cl45_read(bp, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8073_SPEED_LINK_STATUS,\n\t\t\t\t&val);\n\t\t  /* If bit [14] = 0 or bit [13] = 0, continue on with\n\t\t   * system initialization (XAUI work-around not required, as\n\t\t   * these bits indicate 2.5G or 1G link up).\n\t\t   */\n\t\tif (!(val & (1<<14)) || !(val & (1<<13))) {\n\t\t\tDP(NETIF_MSG_LINK, \"XAUI work-around not required\\n\");\n\t\t\treturn 0;\n\t\t} else if (!(val & (1<<15))) {\n\t\t\tDP(NETIF_MSG_LINK, \"bit 15 went off\\n\");\n\t\t\t/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's\n\t\t\t * MSB (bit15) goes to 1 (indicating that the XAUI\n\t\t\t * workaround has completed), then continue on with\n\t\t\t * system initialization.\n\t\t\t */\n\t\t\tfor (cnt1 = 0; cnt1 < 1000; cnt1++) {\n\t\t\t\tbnx2x_cl45_read(bp, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_8073_XAUI_WA, &val);\n\t\t\t\tif (val & (1<<15)) {\n\t\t\t\t\tDP(NETIF_MSG_LINK,\n\t\t\t\t\t  \"XAUI workaround has completed\\n\");\n\t\t\t\t\treturn 0;\n\t\t\t\t}\n\t\t\t\tusleep_range(3000, 6000);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tusleep_range(3000, 6000);\n\t}\n\tDP(NETIF_MSG_LINK, \"Warning: XAUI work-around timeout !!!\\n\");\n\treturn -EINVAL;\n}",
        "static int dr_prepare_qp_to_rts(struct mlx5dr_domain *dmn)\n{\n\tstruct mlx5dr_qp *dr_qp = dmn->send_ring->qp;\n\tstruct dr_qp_rts_attr rts_attr = {};\n\tstruct dr_qp_rtr_attr rtr_attr = {};": "static int dr_prepare_qp_to_rts(struct mlx5dr_domain *dmn)\n{\n\tstruct mlx5dr_qp *dr_qp = dmn->send_ring->qp;\n\tstruct dr_qp_rts_attr rts_attr = {};\n\tstruct dr_qp_rtr_attr rtr_attr = {};\n\tenum ib_mtu mtu = IB_MTU_1024;\n\tu16 gid_index = 0;\n\tint port = 1;\n\tint ret;\n\n\t/* Init */\n\tret = dr_modify_qp_rst2init(dmn->mdev, dr_qp, port);\n\tif (ret) {\n\t\tmlx5dr_err(dmn, \"Failed modify QP rst2init\\n\");\n\t\treturn ret;\n\t}\n\n\t/* RTR */\n\trtr_attr.mtu\t\t= mtu;\n\trtr_attr.qp_num\t\t= dr_qp->qpn;\n\trtr_attr.min_rnr_timer\t= 12;\n\trtr_attr.port_num\t= port;\n\trtr_attr.udp_src_port\t= dmn->info.caps.roce_min_src_udp;\n\n\t/* If QP creation with force loopback is allowed, then there\n\t * is no need for GID index when creating the QP.\n\t * Otherwise we query GID attributes and use GID index.\n\t */\n\trtr_attr.fl = dr_send_allow_fl(&dmn->info.caps);\n\tif (!rtr_attr.fl) {\n\t\tret = mlx5dr_cmd_query_gid(dmn->mdev, port, gid_index,\n\t\t\t\t\t   &rtr_attr.dgid_attr);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\trtr_attr.sgid_index = gid_index;\n\t}\n\n\tret = dr_cmd_modify_qp_init2rtr(dmn->mdev, dr_qp, &rtr_attr);\n\tif (ret) {\n\t\tmlx5dr_err(dmn, \"Failed modify QP init2rtr\\n\");\n\t\treturn ret;\n\t}\n\n\t/* RTS */\n\trts_attr.timeout\t= 14;\n\trts_attr.retry_cnt\t= 7;\n\trts_attr.rnr_retry\t= 7;\n\n\tret = dr_cmd_modify_qp_rtr2rts(dmn->mdev, dr_qp, &rts_attr);\n\tif (ret) {\n\t\tmlx5dr_err(dmn, \"Failed modify QP rtr2rts\\n\");\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}",
        "static void cgroup_destroy_root(struct cgroup_root *root)\n{\n\tstruct cgroup *cgrp = &root->cgrp;\n\tstruct cgrp_cset_link *link, *tmp_link;\n": "static void cgroup_destroy_root(struct cgroup_root *root)\n{\n\tstruct cgroup *cgrp = &root->cgrp;\n\tstruct cgrp_cset_link *link, *tmp_link;\n\n\ttrace_cgroup_destroy_root(root);\n\n\tcgroup_lock_and_drain_offline(&cgrp_dfl_root.cgrp);\n\n\tBUG_ON(atomic_read(&root->nr_cgrps));\n\tBUG_ON(!list_empty(&cgrp->self.children));\n\n\t/* Rebind all subsystems back to the default hierarchy */\n\tWARN_ON(rebind_subsystems(&cgrp_dfl_root, root->subsys_mask));\n\n\t/*\n\t * Release all the links from cset_links to this hierarchy's\n\t * root cgroup\n\t */\n\tspin_lock_irq(&css_set_lock);\n\n\tlist_for_each_entry_safe(link, tmp_link, &cgrp->cset_links, cset_link) {\n\t\tlist_del(&link->cset_link);\n\t\tlist_del(&link->cgrp_link);\n\t\tkfree(link);\n\t}\n\n\tspin_unlock_irq(&css_set_lock);\n\n\tif (!list_empty(&root->root_list)) {\n\t\tlist_del(&root->root_list);\n\t\tcgroup_root_count--;\n\t}\n\n\tcgroup_exit_root_id(root);\n\n\tmutex_unlock(&cgroup_mutex);\n\n\tcgroup_rstat_exit(cgrp);\n\tkernfs_destroy_root(root->kf_root);\n\tcgroup_free_root(root);\n}",
        "static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct net_device *dev = adapter->netdev;\n\tint link, tc, kb, marker;": "static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct net_device *dev = adapter->netdev;\n\tint link, tc, kb, marker;\n\tu32 dv_id, rx_pba;\n\n\t/* Calculate max LAN frame size */\n\ttc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;\n\n#ifdef IXGBE_FCOE\n\t/* FCoE traffic class uses FCOE jumbo frames */\n\tif ((dev->features & NETIF_F_FCOE_MTU) &&\n\t    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&\n\t    (pb == ixgbe_fcoe_get_tc(adapter)))\n\t\ttc = IXGBE_FCOE_JUMBO_FRAME_SIZE;\n#endif\n\n\t/* Calculate delay value for device */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\tcase ixgbe_mac_x550em_a:\n\t\tdv_id = IXGBE_DV_X540(link, tc);\n\t\tbreak;\n\tdefault:\n\t\tdv_id = IXGBE_DV(link, tc);\n\t\tbreak;\n\t}\n\n\t/* Loopback switch introduces additional latency */\n\tif (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)\n\t\tdv_id += IXGBE_B2BT(tc);\n\n\t/* Delay value is calculated in bit times convert to KB */\n\tkb = IXGBE_BT2KB(dv_id);\n\trx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;\n\n\tmarker = rx_pba - kb;\n\n\t/* It is possible that the packet buffer is not large enough\n\t * to provide required headroom. In this case throw an error\n\t * to user and a do the best we can.\n\t */\n\tif (marker < 0) {\n\t\te_warn(drv, \"Packet Buffer(%i) can not provide enough\"\n\t\t\t    \"headroom to support flow control.\"\n\t\t\t    \"Decrease MTU or number of traffic classes\\n\", pb);\n\t\tmarker = tc + 1;\n\t}\n\n\treturn marker;\n}",
        "static void test_sockmap_copy(enum bpf_map_type map_type)\n{\n\tDECLARE_LIBBPF_OPTS(bpf_iter_attach_opts, opts);\n\tint err, len, src_fd, iter_fd, duration = 0;\n\tunion bpf_iter_link_info linfo = {};": "static void test_sockmap_copy(enum bpf_map_type map_type)\n{\n\tDECLARE_LIBBPF_OPTS(bpf_iter_attach_opts, opts);\n\tint err, len, src_fd, iter_fd, duration = 0;\n\tunion bpf_iter_link_info linfo = {};\n\t__u32 i, num_sockets, num_elems;\n\tstruct bpf_iter_sockmap *skel;\n\t__s64 *sock_fd = NULL;\n\tstruct bpf_link *link;\n\tstruct bpf_map *src;\n\tchar buf[64];\n\n\tskel = bpf_iter_sockmap__open_and_load();\n\tif (CHECK(!skel, \"bpf_iter_sockmap__open_and_load\", \"skeleton open_and_load failed\\n\"))\n\t\treturn;\n\n\tif (map_type == BPF_MAP_TYPE_SOCKMAP) {\n\t\tsrc = skel->maps.sockmap;\n\t\tnum_elems = bpf_map__max_entries(src);\n\t\tnum_sockets = num_elems - 1;\n\t} else {\n\t\tsrc = skel->maps.sockhash;\n\t\tnum_elems = bpf_map__max_entries(src) - 1;\n\t\tnum_sockets = num_elems;\n\t}\n\n\tsock_fd = calloc(num_sockets, sizeof(*sock_fd));\n\tif (CHECK(!sock_fd, \"calloc(sock_fd)\", \"failed to allocate\\n\"))\n\t\tgoto out;\n\n\tfor (i = 0; i < num_sockets; i++)\n\t\tsock_fd[i] = -1;\n\n\tsrc_fd = bpf_map__fd(src);\n\n\tfor (i = 0; i < num_sockets; i++) {\n\t\tsock_fd[i] = connected_socket_v4();\n\t\tif (CHECK(sock_fd[i] == -1, \"connected_socket_v4\", \"cannot connect\\n\"))\n\t\t\tgoto out;\n\n\t\terr = bpf_map_update_elem(src_fd, &i, &sock_fd[i], BPF_NOEXIST);\n\t\tif (CHECK(err, \"map_update\", \"failed: %s\\n\", strerror(errno)))\n\t\t\tgoto out;\n\t}\n\n\tlinfo.map.map_fd = src_fd;\n\topts.link_info = &linfo;\n\topts.link_info_len = sizeof(linfo);\n\tlink = bpf_program__attach_iter(skel->progs.copy, &opts);\n\tif (!ASSERT_OK_PTR(link, \"attach_iter\"))\n\t\tgoto out;\n\n\titer_fd = bpf_iter_create(bpf_link__fd(link));\n\tif (CHECK(iter_fd < 0, \"create_iter\", \"create_iter failed\\n\"))\n\t\tgoto free_link;\n\n\t/* do some tests */\n\twhile ((len = read(iter_fd, buf, sizeof(buf))) > 0)\n\t\t;\n\tif (CHECK(len < 0, \"read\", \"failed: %s\\n\", strerror(errno)))\n\t\tgoto close_iter;\n\n\t/* test results */\n\tif (CHECK(skel->bss->elems != num_elems, \"elems\", \"got %u expected %u\\n\",\n\t\t  skel->bss->elems, num_elems))\n\t\tgoto close_iter;\n\n\tif (CHECK(skel->bss->socks != num_sockets, \"socks\", \"got %u expected %u\\n\",\n\t\t  skel->bss->socks, num_sockets))\n\t\tgoto close_iter;\n\n\tcompare_cookies(src, skel->maps.dst);\n\nclose_iter:\n\tclose(iter_fd);\nfree_link:\n\tbpf_link__destroy(link);\nout:\n\tfor (i = 0; sock_fd && i < num_sockets; i++)\n\t\tif (sock_fd[i] >= 0)\n\t\t\tclose(sock_fd[i]);\n\tif (sock_fd)\n\t\tfree(sock_fd);\n\tbpf_iter_sockmap__destroy(skel);\n}",
        "static int kcryptd_io_read(struct dm_crypt_io *io, gfp_t gfp)\n{\n\tstruct crypt_config *cc = io->cc;\n\tstruct bio *clone;\n": "static int kcryptd_io_read(struct dm_crypt_io *io, gfp_t gfp)\n{\n\tstruct crypt_config *cc = io->cc;\n\tstruct bio *clone;\n\n\t/*\n\t * We need the original biovec array in order to decrypt the whole bio\n\t * data *afterwards* -- thanks to immutable biovecs we don't need to\n\t * worry about the block layer modifying the biovec array; so leverage\n\t * bio_alloc_clone().\n\t */\n\tclone = bio_alloc_clone(cc->dev->bdev, io->base_bio, gfp, &cc->bs);\n\tif (!clone)\n\t\treturn 1;\n\tclone->bi_private = io;\n\tclone->bi_end_io = crypt_endio;\n\n\tcrypt_inc_pending(io);\n\n\tclone->bi_iter.bi_sector = cc->start + io->sector;\n\n\tif (dm_crypt_integrity_io_alloc(io, clone)) {\n\t\tcrypt_dec_pending(io);\n\t\tbio_put(clone);\n\t\treturn 1;\n\t}\n\n\tdm_submit_bio_remap(io->base_bio, clone);\n\treturn 0;\n}",
        "static void imgu_css_hw_enable_irq(struct imgu_css *css)\n{\n\tvoid __iomem *const base = css->base;\n\tu32 val, i;\n": "static void imgu_css_hw_enable_irq(struct imgu_css *css)\n{\n\tvoid __iomem *const base = css->base;\n\tu32 val, i;\n\n\t/* Set up interrupts */\n\n\t/*\n\t * Enable IRQ on the SP which signals that SP goes to idle\n\t * (aka ready state) and set trigger to pulse\n\t */\n\tval = readl(base + IMGU_REG_SP_CTRL(0)) | IMGU_CTRL_IRQ_READY;\n\twritel(val, base + IMGU_REG_SP_CTRL(0));\n\twritel(val | IMGU_CTRL_IRQ_CLEAR, base + IMGU_REG_SP_CTRL(0));\n\n\t/* Enable IRQs from the IMGU wrapper */\n\twritel(IMGU_REG_INT_CSS_IRQ, base + IMGU_REG_INT_ENABLE);\n\t/* Clear */\n\twritel(IMGU_REG_INT_CSS_IRQ, base + IMGU_REG_INT_STATUS);\n\n\t/* Enable IRQs from main IRQ controller */\n\twritel(~0, base + IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(IMGU_IRQCTRL_MAIN));\n\twritel(0, base + IMGU_REG_IRQCTRL_MASK(IMGU_IRQCTRL_MAIN));\n\twritel(IMGU_IRQCTRL_IRQ_MASK,\n\t       base + IMGU_REG_IRQCTRL_EDGE(IMGU_IRQCTRL_MAIN));\n\twritel(IMGU_IRQCTRL_IRQ_MASK,\n\t       base + IMGU_REG_IRQCTRL_ENABLE(IMGU_IRQCTRL_MAIN));\n\twritel(IMGU_IRQCTRL_IRQ_MASK,\n\t       base + IMGU_REG_IRQCTRL_CLEAR(IMGU_IRQCTRL_MAIN));\n\twritel(IMGU_IRQCTRL_IRQ_MASK,\n\t       base + IMGU_REG_IRQCTRL_MASK(IMGU_IRQCTRL_MAIN));\n\t/* Wait for write complete */\n\treadl(base + IMGU_REG_IRQCTRL_ENABLE(IMGU_IRQCTRL_MAIN));\n\n\t/* Enable IRQs from SP0 and SP1 controllers */\n\tfor (i = IMGU_IRQCTRL_SP0; i <= IMGU_IRQCTRL_SP1; i++) {\n\t\twritel(~0, base + IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(i));\n\t\twritel(0, base + IMGU_REG_IRQCTRL_MASK(i));\n\t\twritel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_EDGE(i));\n\t\twritel(IMGU_IRQCTRL_IRQ_MASK,\n\t\t       base + IMGU_REG_IRQCTRL_ENABLE(i));\n\t\twritel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_CLEAR(i));\n\t\twritel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_MASK(i));\n\t\t/* Wait for write complete */\n\t\treadl(base + IMGU_REG_IRQCTRL_ENABLE(i));\n\t}\n}",
        "static bool cachefiles_invalidate_cookie(struct fscache_cookie *cookie)\n{\n\tstruct cachefiles_object *object = cookie->cache_priv;\n\tstruct file *new_file, *old_file;\n\tbool old_tmpfile;": "static bool cachefiles_invalidate_cookie(struct fscache_cookie *cookie)\n{\n\tstruct cachefiles_object *object = cookie->cache_priv;\n\tstruct file *new_file, *old_file;\n\tbool old_tmpfile;\n\n\t_enter(\"o=%x,[%llu]\", object->debug_id, object->cookie->object_size);\n\n\told_tmpfile = test_bit(CACHEFILES_OBJECT_USING_TMPFILE, &object->flags);\n\n\tif (!object->file) {\n\t\tfscache_resume_after_invalidation(cookie);\n\t\t_leave(\" = t [light]\");\n\t\treturn true;\n\t}\n\n\tnew_file = cachefiles_create_tmpfile(object);\n\tif (IS_ERR(new_file))\n\t\tgoto failed;\n\n\t/* Substitute the VFS target */\n\t_debug(\"sub\");\n\tspin_lock(&object->lock);\n\n\told_file = object->file;\n\tobject->file = new_file;\n\tobject->content_info = CACHEFILES_CONTENT_NO_DATA;\n\tset_bit(CACHEFILES_OBJECT_USING_TMPFILE, &object->flags);\n\tset_bit(FSCACHE_COOKIE_NEEDS_UPDATE, &object->cookie->flags);\n\n\tspin_unlock(&object->lock);\n\t_debug(\"subbed\");\n\n\t/* Allow I/O to take place again */\n\tfscache_resume_after_invalidation(cookie);\n\n\tif (old_file) {\n\t\tif (!old_tmpfile) {\n\t\t\tstruct cachefiles_volume *volume = object->volume;\n\t\t\tstruct dentry *fan = volume->fanout[(u8)cookie->key_hash];\n\n\t\t\tinode_lock_nested(d_inode(fan), I_MUTEX_PARENT);\n\t\t\tcachefiles_bury_object(volume->cache, object, fan,\n\t\t\t\t\t       old_file->f_path.dentry,\n\t\t\t\t\t       FSCACHE_OBJECT_INVALIDATED);\n\t\t}\n\t\tfput(old_file);\n\t}\n\n\t_leave(\" = t\");\n\treturn true;\n\nfailed:\n\t_leave(\" = f\");\n\treturn false;\n}",
        "static inline void calculate_imbalance(struct lb_env *env, struct sd_lb_stats *sds)\n{\n\tstruct sg_lb_stats *local, *busiest;\n\n\tlocal = &sds->local_stat;": "static inline void calculate_imbalance(struct lb_env *env, struct sd_lb_stats *sds)\n{\n\tstruct sg_lb_stats *local, *busiest;\n\n\tlocal = &sds->local_stat;\n\tbusiest = &sds->busiest_stat;\n\n\tif (busiest->group_type == group_misfit_task) {\n\t\t/* Set imbalance to allow misfit tasks to be balanced. */\n\t\tenv->migration_type = migrate_misfit;\n\t\tenv->imbalance = 1;\n\t\treturn;\n\t}\n\n\tif (busiest->group_type == group_asym_packing) {\n\t\t/*\n\t\t * In case of asym capacity, we will try to migrate all load to\n\t\t * the preferred CPU.\n\t\t */\n\t\tenv->migration_type = migrate_task;\n\t\tenv->imbalance = busiest->sum_h_nr_running;\n\t\treturn;\n\t}\n\n\tif (busiest->group_type == group_imbalanced) {\n\t\t/*\n\t\t * In the group_imb case we cannot rely on group-wide averages\n\t\t * to ensure CPU-load equilibrium, try to move any task to fix\n\t\t * the imbalance. The next load balance will take care of\n\t\t * balancing back the system.\n\t\t */\n\t\tenv->migration_type = migrate_task;\n\t\tenv->imbalance = 1;\n\t\treturn;\n\t}\n\n\t/*\n\t * Try to use spare capacity of local group without overloading it or\n\t * emptying busiest.\n\t */\n\tif (local->group_type == group_has_spare) {\n\t\tif ((busiest->group_type > group_fully_busy) &&\n\t\t    !(env->sd->flags & SD_SHARE_PKG_RESOURCES)) {\n\t\t\t/*\n\t\t\t * If busiest is overloaded, try to fill spare\n\t\t\t * capacity. This might end up creating spare capacity\n\t\t\t * in busiest or busiest still being overloaded but\n\t\t\t * there is no simple way to directly compute the\n\t\t\t * amount of load to migrate in order to balance the\n\t\t\t * system.\n\t\t\t */\n\t\t\tenv->migration_type = migrate_util;\n\t\t\tenv->imbalance = max(local->group_capacity, local->group_util) -\n\t\t\t\t\t local->group_util;\n\n\t\t\t/*\n\t\t\t * In some cases, the group's utilization is max or even\n\t\t\t * higher than capacity because of migrations but the\n\t\t\t * local CPU is (newly) idle. There is at least one\n\t\t\t * waiting task in this overloaded busiest group. Let's\n\t\t\t * try to pull it.\n\t\t\t */\n\t\t\tif (env->idle != CPU_NOT_IDLE && env->imbalance == 0) {\n\t\t\t\tenv->migration_type = migrate_task;\n\t\t\t\tenv->imbalance = 1;\n\t\t\t}\n\n\t\t\treturn;\n\t\t}\n\n\t\tif (busiest->group_weight == 1 || sds->prefer_sibling) {\n\t\t\tunsigned int nr_diff = busiest->sum_nr_running;\n\t\t\t/*\n\t\t\t * When prefer sibling, evenly spread running tasks on\n\t\t\t * groups.\n\t\t\t */\n\t\t\tenv->migration_type = migrate_task;\n\t\t\tlsub_positive(&nr_diff, local->sum_nr_running);\n\t\t\tenv->imbalance = nr_diff >> 1;\n\t\t} else {\n\n\t\t\t/*\n\t\t\t * If there is no overload, we just want to even the number of\n\t\t\t * idle cpus.\n\t\t\t */\n\t\t\tenv->migration_type = migrate_task;\n\t\t\tenv->imbalance = max_t(long, 0, (local->idle_cpus -\n\t\t\t\t\t\t busiest->idle_cpus) >> 1);\n\t\t}\n\n\t\t/* Consider allowing a small imbalance between NUMA groups */\n\t\tif (env->sd->flags & SD_NUMA) {\n\t\t\tenv->imbalance = adjust_numa_imbalance(env->imbalance,\n\t\t\t\tlocal->sum_nr_running + 1, env->sd->imb_numa_nr);\n\t\t}\n\n\t\treturn;\n\t}\n\n\t/*\n\t * Local is fully busy but has to take more load to relieve the\n\t * busiest group\n\t */\n\tif (local->group_type < group_overloaded) {\n\t\t/*\n\t\t * Local will become overloaded so the avg_load metrics are\n\t\t * finally needed.\n\t\t */\n\n\t\tlocal->avg_load = (local->group_load * SCHED_CAPACITY_SCALE) /\n\t\t\t\t  local->group_capacity;\n\n\t\t/*\n\t\t * If the local group is more loaded than the selected\n\t\t * busiest group don't try to pull any tasks.\n\t\t */\n\t\tif (local->avg_load >= busiest->avg_load) {\n\t\t\tenv->imbalance = 0;\n\t\t\treturn;\n\t\t}\n\n\t\tsds->avg_load = (sds->total_load * SCHED_CAPACITY_SCALE) /\n\t\t\t\tsds->total_capacity;\n\t}\n\n\t/*\n\t * Both group are or will become overloaded and we're trying to get all\n\t * the CPUs to the average_load, so we don't want to push ourselves\n\t * above the average load, nor do we wish to reduce the max loaded CPU\n\t * below the average load. At the same time, we also don't want to\n\t * reduce the group load below the group capacity. Thus we look for\n\t * the minimum possible imbalance.\n\t */\n\tenv->migration_type = migrate_load;\n\tenv->imbalance = min(\n\t\t(busiest->avg_load - sds->avg_load) * busiest->group_capacity,\n\t\t(sds->avg_load - local->avg_load) * local->group_capacity\n\t) / SCHED_CAPACITY_SCALE;\n}",
        "static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)\n{\n\tint ret = 0, herc;\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;\n\tu64 val64 = readq(&bar0->adapter_status);": "static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)\n{\n\tint ret = 0, herc;\n\tstruct XENA_dev_config __iomem *bar0 = sp->bar0;\n\tu64 val64 = readq(&bar0->adapter_status);\n\n\therc = (sp->device_type == XFRAME_II_DEVICE);\n\n\tif (flag == false) {\n\t\tif ((!herc && (sp->pdev->revision >= 4)) || herc) {\n\t\t\tif (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))\n\t\t\t\tret = 1;\n\t\t} else {\n\t\t\tif (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))\n\t\t\t\tret = 1;\n\t\t}\n\t} else {\n\t\tif ((!herc && (sp->pdev->revision >= 4)) || herc) {\n\t\t\tif (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==\n\t\t\t     ADAPTER_STATUS_RMAC_PCC_IDLE))\n\t\t\t\tret = 1;\n\t\t} else {\n\t\t\tif (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==\n\t\t\t     ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))\n\t\t\t\tret = 1;\n\t\t}\n\t}\n\n\treturn ret;\n}",
        "static int calculate_device_limits(struct dm_integrity_c *ic)\n{\n\t__u64 initial_sectors;\n\n\tcalculate_journal_section_size(ic);": "static int calculate_device_limits(struct dm_integrity_c *ic)\n{\n\t__u64 initial_sectors;\n\n\tcalculate_journal_section_size(ic);\n\tinitial_sectors = SB_SECTORS + (__u64)ic->journal_section_sectors * ic->journal_sections;\n\tif (initial_sectors + METADATA_PADDING_SECTORS >= ic->meta_device_sectors || initial_sectors > UINT_MAX)\n\t\treturn -EINVAL;\n\tic->initial_sectors = initial_sectors;\n\n\tif (!ic->meta_dev) {\n\t\tsector_t last_sector, last_area, last_offset;\n\n\t\t/* we have to maintain excessive padding for compatibility with existing volumes */\n\t\t__u64 metadata_run_padding =\n\t\t\tic->sb->flags & cpu_to_le32(SB_FLAG_FIXED_PADDING) ?\n\t\t\t(__u64)(METADATA_PADDING_SECTORS << SECTOR_SHIFT) :\n\t\t\t(__u64)(1 << SECTOR_SHIFT << METADATA_PADDING_SECTORS);\n\n\t\tic->metadata_run = round_up((__u64)ic->tag_size << (ic->sb->log2_interleave_sectors - ic->sb->log2_sectors_per_block),\n\t\t\t\t\t    metadata_run_padding) >> SECTOR_SHIFT;\n\t\tif (!(ic->metadata_run & (ic->metadata_run - 1)))\n\t\t\tic->log2_metadata_run = __ffs(ic->metadata_run);\n\t\telse\n\t\t\tic->log2_metadata_run = -1;\n\n\t\tget_area_and_offset(ic, ic->provided_data_sectors - 1, &last_area, &last_offset);\n\t\tlast_sector = get_data_sector(ic, last_area, last_offset);\n\t\tif (last_sector < ic->start || last_sector >= ic->meta_device_sectors)\n\t\t\treturn -EINVAL;\n\t} else {\n\t\t__u64 meta_size = (ic->provided_data_sectors >> ic->sb->log2_sectors_per_block) * ic->tag_size;\n\t\tmeta_size = (meta_size + ((1U << (ic->log2_buffer_sectors + SECTOR_SHIFT)) - 1))\n\t\t\t\t>> (ic->log2_buffer_sectors + SECTOR_SHIFT);\n\t\tmeta_size <<= ic->log2_buffer_sectors;\n\t\tif (ic->initial_sectors + meta_size < ic->initial_sectors ||\n\t\t    ic->initial_sectors + meta_size > ic->meta_device_sectors)\n\t\t\treturn -EINVAL;\n\t\tic->metadata_run = 1;\n\t\tic->log2_metadata_run = 0;\n\t}\n\n\treturn 0;\n}",
        "static int vivid_thread_touch_cap(void *data)\n{\n\tstruct vivid_dev *dev = data;\n\tu64 numerators_since_start;\n\tu64 buffers_since_start;": "static int vivid_thread_touch_cap(void *data)\n{\n\tstruct vivid_dev *dev = data;\n\tu64 numerators_since_start;\n\tu64 buffers_since_start;\n\tu64 next_jiffies_since_start;\n\tunsigned long jiffies_since_start;\n\tunsigned long cur_jiffies;\n\tunsigned int wait_jiffies;\n\tunsigned int numerator;\n\tunsigned int denominator;\n\tint dropped_bufs;\n\n\tdprintk(dev, 1, \"Touch Capture Thread Start\\n\");\n\n\tset_freezable();\n\n\t/* Resets frame counters */\n\tdev->touch_cap_seq_offset = 0;\n\tdev->touch_cap_seq_count = 0;\n\tdev->touch_cap_seq_resync = false;\n\tdev->jiffies_touch_cap = jiffies;\n\tif (dev->time_wrap)\n\t\tdev->time_wrap_offset = dev->time_wrap - ktime_get_ns();\n\telse\n\t\tdev->time_wrap_offset = 0;\n\n\tfor (;;) {\n\t\ttry_to_freeze();\n\t\tif (kthread_should_stop())\n\t\t\tbreak;\n\n\t\tif (!mutex_trylock(&dev->mutex)) {\n\t\t\tschedule();\n\t\t\tcontinue;\n\t\t}\n\t\tcur_jiffies = jiffies;\n\t\tif (dev->touch_cap_seq_resync) {\n\t\t\tdev->jiffies_touch_cap = cur_jiffies;\n\t\t\tdev->touch_cap_seq_offset = dev->touch_cap_seq_count + 1;\n\t\t\tdev->touch_cap_seq_count = 0;\n\t\t\tdev->cap_seq_resync = false;\n\t\t}\n\t\tdenominator = dev->timeperframe_tch_cap.denominator;\n\t\tnumerator = dev->timeperframe_tch_cap.numerator;\n\n\t\t/* Calculate the number of jiffies since we started streaming */\n\t\tjiffies_since_start = cur_jiffies - dev->jiffies_touch_cap;\n\t\t/* Get the number of buffers streamed since the start */\n\t\tbuffers_since_start = (u64)jiffies_since_start * denominator +\n\t\t\t\t      (HZ * numerator) / 2;\n\t\tdo_div(buffers_since_start, HZ * numerator);\n\n\t\t/*\n\t\t * After more than 0xf0000000 (rounded down to a multiple of\n\t\t * 'jiffies-per-day' to ease jiffies_to_msecs calculation)\n\t\t * jiffies have passed since we started streaming reset the\n\t\t * counters and keep track of the sequence offset.\n\t\t */\n\t\tif (jiffies_since_start > JIFFIES_RESYNC) {\n\t\t\tdev->jiffies_touch_cap = cur_jiffies;\n\t\t\tdev->cap_seq_offset = buffers_since_start;\n\t\t\tbuffers_since_start = 0;\n\t\t}\n\t\tdropped_bufs = buffers_since_start + dev->touch_cap_seq_offset - dev->touch_cap_seq_count;\n\t\tdev->touch_cap_seq_count = buffers_since_start + dev->touch_cap_seq_offset;\n\t\tdev->touch_cap_with_seq_wrap_count =\n\t\t\tdev->touch_cap_seq_count - dev->touch_cap_seq_start;\n\n\t\tvivid_thread_tch_cap_tick(dev, dropped_bufs);\n\n\t\t/*\n\t\t * Calculate the number of 'numerators' streamed\n\t\t * since we started, including the current buffer.\n\t\t */\n\t\tnumerators_since_start = ++buffers_since_start * numerator;\n\n\t\t/* And the number of jiffies since we started */\n\t\tjiffies_since_start = jiffies - dev->jiffies_touch_cap;\n\n\t\tmutex_unlock(&dev->mutex);\n\n\t\t/*\n\t\t * Calculate when that next buffer is supposed to start\n\t\t * in jiffies since we started streaming.\n\t\t */\n\t\tnext_jiffies_since_start = numerators_since_start * HZ +\n\t\t\t\t\t   denominator / 2;\n\t\tdo_div(next_jiffies_since_start, denominator);\n\t\t/* If it is in the past, then just schedule asap */\n\t\tif (next_jiffies_since_start < jiffies_since_start)\n\t\t\tnext_jiffies_since_start = jiffies_since_start;\n\n\t\twait_jiffies = next_jiffies_since_start - jiffies_since_start;\n\t\twhile (time_is_after_jiffies(cur_jiffies + wait_jiffies) &&\n\t\t       !kthread_should_stop())\n\t\t\tschedule();\n\t}\n\tdprintk(dev, 1, \"Touch Capture Thread End\\n\");\n\treturn 0;\n}",
        "static void mtk_smi_larb_config_port_gen2_general(struct device *dev)\n{\n\tstruct mtk_smi_larb *larb = dev_get_drvdata(dev);\n\tu32 reg, flags_general = larb->larb_gen->flags_general;\n\tconst u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;": "static void mtk_smi_larb_config_port_gen2_general(struct device *dev)\n{\n\tstruct mtk_smi_larb *larb = dev_get_drvdata(dev);\n\tu32 reg, flags_general = larb->larb_gen->flags_general;\n\tconst u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;\n\tint i;\n\n\tif (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)\n\t\treturn;\n\n\tif (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {\n\t\treg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);\n\t\treg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;\n\t\treg |= SMI_LARB_THRT_RD_NU_LMT;\n\t\twritel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);\n\t}\n\n\tif (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))\n\t\twritel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);\n\n\tfor (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)\n\t\twritel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));\n\n\tfor_each_set_bit(i, (unsigned long *)larb->mmu, 32) {\n\t\treg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));\n\t\treg |= F_MMU_EN;\n\t\treg |= BANK_SEL(larb->bank[i]);\n\t\twritel(reg, larb->base + SMI_LARB_NONSEC_CON(i));\n\t}\n}",
        "static void update_color_buffer(struct vc_data *vc, const u16 *ic, int len)\n{\n\tint i, bi, hi;\n\tint vc_num = vc->vc_num;\n": "static void update_color_buffer(struct vc_data *vc, const u16 *ic, int len)\n{\n\tint i, bi, hi;\n\tint vc_num = vc->vc_num;\n\n\tbi = (vc->vc_attr & 0x70) >> 4;\n\thi = speakup_console[vc_num]->ht.highsize[bi];\n\n\ti = 0;\n\tif (speakup_console[vc_num]->ht.highsize[bi] == 0) {\n\t\tspeakup_console[vc_num]->ht.rpos[bi] = vc->vc_pos;\n\t\tspeakup_console[vc_num]->ht.rx[bi] = vc->state.x;\n\t\tspeakup_console[vc_num]->ht.ry[bi] = vc->state.y;\n\t}\n\twhile ((hi < COLOR_BUFFER_SIZE) && (i < len)) {\n\t\tif (ic[i] > 32) {\n\t\t\tspeakup_console[vc_num]->ht.highbuf[bi][hi] = ic[i];\n\t\t\thi++;\n\t\t} else if ((ic[i] == 32) && (hi != 0)) {\n\t\t\tif (speakup_console[vc_num]->ht.highbuf[bi][hi - 1] !=\n\t\t\t    32) {\n\t\t\t\tspeakup_console[vc_num]->ht.highbuf[bi][hi] =\n\t\t\t\t    ic[i];\n\t\t\t\thi++;\n\t\t\t}\n\t\t}\n\t\ti++;\n\t}\n\tspeakup_console[vc_num]->ht.highsize[bi] = hi;\n}",
        "static int ipc_pcie_resources_request(struct iosm_pcie *ipc_pcie)\n{\n\tstruct pci_dev *pci = ipc_pcie->pci;\n\tu32 cap = 0;\n\tu32 ret;": "static int ipc_pcie_resources_request(struct iosm_pcie *ipc_pcie)\n{\n\tstruct pci_dev *pci = ipc_pcie->pci;\n\tu32 cap = 0;\n\tu32 ret;\n\n\t/* Reserved PCI I/O and memory resources.\n\t * Mark all PCI regions associated with PCI device pci as\n\t * being reserved by owner IOSM_IPC.\n\t */\n\tret = pci_request_regions(pci, \"IOSM_IPC\");\n\tif (ret) {\n\t\tdev_err(ipc_pcie->dev, \"failed pci request regions\");\n\t\tgoto pci_request_region_fail;\n\t}\n\n\t/* Reserve the doorbell IPC REGS memory resources.\n\t * Remap the memory into CPU space. Arrange for the physical address\n\t * (BAR) to be visible from this driver.\n\t * pci_ioremap_bar() ensures that the memory is marked uncachable.\n\t */\n\tipc_pcie->ipc_regs = pci_ioremap_bar(pci, ipc_pcie->ipc_regs_bar_nr);\n\n\tif (!ipc_pcie->ipc_regs) {\n\t\tdev_err(ipc_pcie->dev, \"IPC REGS ioremap error\");\n\t\tret = -EBUSY;\n\t\tgoto ipc_regs_remap_fail;\n\t}\n\n\t/* Reserve the MMIO scratchpad memory resources.\n\t * Remap the memory into CPU space. Arrange for the physical address\n\t * (BAR) to be visible from this driver.\n\t * pci_ioremap_bar() ensures that the memory is marked uncachable.\n\t */\n\tipc_pcie->scratchpad =\n\t\tpci_ioremap_bar(pci, ipc_pcie->scratchpad_bar_nr);\n\n\tif (!ipc_pcie->scratchpad) {\n\t\tdev_err(ipc_pcie->dev, \"doorbell scratchpad ioremap error\");\n\t\tret = -EBUSY;\n\t\tgoto scratch_remap_fail;\n\t}\n\n\t/* Install the irq handler triggered by CP. */\n\tret = ipc_acquire_irq(ipc_pcie);\n\tif (ret) {\n\t\tdev_err(ipc_pcie->dev, \"acquiring MSI irq failed!\");\n\t\tgoto irq_acquire_fail;\n\t}\n\n\t/* Enable bus-mastering for the IOSM IPC device. */\n\tpci_set_master(pci);\n\n\t/* Enable LTR if possible\n\t * This is needed for L1.2!\n\t */\n\tpcie_capability_read_dword(ipc_pcie->pci, PCI_EXP_DEVCAP2, &cap);\n\tif (cap & PCI_EXP_DEVCAP2_LTR)\n\t\tpcie_capability_set_word(ipc_pcie->pci, PCI_EXP_DEVCTL2,\n\t\t\t\t\t PCI_EXP_DEVCTL2_LTR_EN);\n\n\tdev_dbg(ipc_pcie->dev, \"link between AP and CP is fully on\");\n\n\treturn ret;\n\nirq_acquire_fail:\n\tiounmap(ipc_pcie->scratchpad);\nscratch_remap_fail:\n\tiounmap(ipc_pcie->ipc_regs);\nipc_regs_remap_fail:\n\tpci_release_regions(pci);\npci_request_region_fail:\n\treturn ret;\n}",
        "static int rpmsg_probe(struct virtio_device *vdev)\n{\n\tvq_callback_t *vq_cbs[] = { rpmsg_recv_done, rpmsg_xmit_done };\n\tstatic const char * const names[] = { \"input\", \"output\" };\n\tstruct virtqueue *vqs[2];": "static int rpmsg_probe(struct virtio_device *vdev)\n{\n\tvq_callback_t *vq_cbs[] = { rpmsg_recv_done, rpmsg_xmit_done };\n\tstatic const char * const names[] = { \"input\", \"output\" };\n\tstruct virtqueue *vqs[2];\n\tstruct virtproc_info *vrp;\n\tstruct virtio_rpmsg_channel *vch = NULL;\n\tstruct rpmsg_device *rpdev_ns, *rpdev_ctrl;\n\tvoid *bufs_va;\n\tint err = 0, i;\n\tsize_t total_buf_space;\n\tbool notify;\n\n\tvrp = kzalloc(sizeof(*vrp), GFP_KERNEL);\n\tif (!vrp)\n\t\treturn -ENOMEM;\n\n\tvrp->vdev = vdev;\n\n\tidr_init(&vrp->endpoints);\n\tmutex_init(&vrp->endpoints_lock);\n\tmutex_init(&vrp->tx_lock);\n\tinit_waitqueue_head(&vrp->sendq);\n\n\t/* We expect two virtqueues, rx and tx (and in this order) */\n\terr = virtio_find_vqs(vdev, 2, vqs, vq_cbs, names, NULL);\n\tif (err)\n\t\tgoto free_vrp;\n\n\tvrp->rvq = vqs[0];\n\tvrp->svq = vqs[1];\n\n\t/* we expect symmetric tx/rx vrings */\n\tWARN_ON(virtqueue_get_vring_size(vrp->rvq) !=\n\t\tvirtqueue_get_vring_size(vrp->svq));\n\n\t/* we need less buffers if vrings are small */\n\tif (virtqueue_get_vring_size(vrp->rvq) < MAX_RPMSG_NUM_BUFS / 2)\n\t\tvrp->num_bufs = virtqueue_get_vring_size(vrp->rvq) * 2;\n\telse\n\t\tvrp->num_bufs = MAX_RPMSG_NUM_BUFS;\n\n\tvrp->buf_size = MAX_RPMSG_BUF_SIZE;\n\n\ttotal_buf_space = vrp->num_bufs * vrp->buf_size;\n\n\t/* allocate coherent memory for the buffers */\n\tbufs_va = dma_alloc_coherent(vdev->dev.parent,\n\t\t\t\t     total_buf_space, &vrp->bufs_dma,\n\t\t\t\t     GFP_KERNEL);\n\tif (!bufs_va) {\n\t\terr = -ENOMEM;\n\t\tgoto vqs_del;\n\t}\n\n\tdev_dbg(&vdev->dev, \"buffers: va %pK, dma %pad\\n\",\n\t\tbufs_va, &vrp->bufs_dma);\n\n\t/* half of the buffers is dedicated for RX */\n\tvrp->rbufs = bufs_va;\n\n\t/* and half is dedicated for TX */\n\tvrp->sbufs = bufs_va + total_buf_space / 2;\n\n\t/* set up the receive buffers */\n\tfor (i = 0; i < vrp->num_bufs / 2; i++) {\n\t\tstruct scatterlist sg;\n\t\tvoid *cpu_addr = vrp->rbufs + i * vrp->buf_size;\n\n\t\trpmsg_sg_init(&sg, cpu_addr, vrp->buf_size);\n\n\t\terr = virtqueue_add_inbuf(vrp->rvq, &sg, 1, cpu_addr,\n\t\t\t\t\t  GFP_KERNEL);\n\t\tWARN_ON(err); /* sanity check; this can't really happen */\n\t}\n\n\t/* suppress \"tx-complete\" interrupts */\n\tvirtqueue_disable_cb(vrp->svq);\n\n\tvdev->priv = vrp;\n\n\trpdev_ctrl = rpmsg_virtio_add_ctrl_dev(vdev);\n\tif (IS_ERR(rpdev_ctrl)) {\n\t\terr = PTR_ERR(rpdev_ctrl);\n\t\tgoto free_coherent;\n\t}\n\n\t/* if supported by the remote processor, enable the name service */\n\tif (virtio_has_feature(vdev, VIRTIO_RPMSG_F_NS)) {\n\t\tvch = kzalloc(sizeof(*vch), GFP_KERNEL);\n\t\tif (!vch) {\n\t\t\terr = -ENOMEM;\n\t\t\tgoto free_ctrldev;\n\t\t}\n\n\t\t/* Link the channel to our vrp */\n\t\tvch->vrp = vrp;\n\n\t\t/* Assign public information to the rpmsg_device */\n\t\trpdev_ns = &vch->rpdev;\n\t\trpdev_ns->ops = &virtio_rpmsg_ops;\n\t\trpdev_ns->little_endian = virtio_is_little_endian(vrp->vdev);\n\n\t\trpdev_ns->dev.parent = &vrp->vdev->dev;\n\t\trpdev_ns->dev.release = virtio_rpmsg_release_device;\n\n\t\terr = rpmsg_ns_register_device(rpdev_ns);\n\t\tif (err)\n\t\t\t/* vch will be free in virtio_rpmsg_release_device() */\n\t\t\tgoto free_ctrldev;\n\t}\n\n\t/*\n\t * Prepare to kick but don't notify yet - we can't do this before\n\t * device is ready.\n\t */\n\tnotify = virtqueue_kick_prepare(vrp->rvq);\n\n\t/* From this point on, we can notify and get callbacks. */\n\tvirtio_device_ready(vdev);\n\n\t/* tell the remote processor it can start sending messages */\n\t/*\n\t * this might be concurrent with callbacks, but we are only\n\t * doing notify, not a full kick here, so that's ok.\n\t */\n\tif (notify)\n\t\tvirtqueue_notify(vrp->rvq);\n\n\tdev_info(&vdev->dev, \"rpmsg host is online\\n\");\n\n\treturn 0;\n\nfree_ctrldev:\n\trpmsg_virtio_del_ctrl_dev(rpdev_ctrl);\nfree_coherent:\n\tdma_free_coherent(vdev->dev.parent, total_buf_space,\n\t\t\t  bufs_va, vrp->bufs_dma);\nvqs_del:\n\tvdev->config->del_vqs(vrp->vdev);\nfree_vrp:\n\tkfree(vrp);\n\treturn err;\n}",
        "static int tsi721_enable_msix(struct tsi721_device *priv)\n{\n\tstruct msix_entry entries[TSI721_VECT_MAX];\n\tint err;\n\tint i;": "static int tsi721_enable_msix(struct tsi721_device *priv)\n{\n\tstruct msix_entry entries[TSI721_VECT_MAX];\n\tint err;\n\tint i;\n\n\tentries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);\n\tentries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;\n\n\t/*\n\t * Initialize MSI-X entries for Messaging Engine:\n\t * this driver supports four RIO mailboxes (inbound and outbound)\n\t * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore\n\t * offset +4 is added to IB MBOX number.\n\t */\n\tfor (i = 0; i < RIO_MAX_MBOX; i++) {\n\t\tentries[TSI721_VECT_IMB0_RCV + i].entry =\n\t\t\t\t\tTSI721_MSIX_IMSG_DQ_RCV(i + 4);\n\t\tentries[TSI721_VECT_IMB0_INT + i].entry =\n\t\t\t\t\tTSI721_MSIX_IMSG_INT(i + 4);\n\t\tentries[TSI721_VECT_OMB0_DONE + i].entry =\n\t\t\t\t\tTSI721_MSIX_OMSG_DONE(i);\n\t\tentries[TSI721_VECT_OMB0_INT + i].entry =\n\t\t\t\t\tTSI721_MSIX_OMSG_INT(i);\n\t}\n\n#ifdef CONFIG_RAPIDIO_DMA_ENGINE\n\t/*\n\t * Initialize MSI-X entries for Block DMA Engine:\n\t * this driver supports XXX DMA channels\n\t * (one is reserved for SRIO maintenance transactions)\n\t */\n\tfor (i = 0; i < TSI721_DMA_CHNUM; i++) {\n\t\tentries[TSI721_VECT_DMA0_DONE + i].entry =\n\t\t\t\t\tTSI721_MSIX_DMACH_DONE(i);\n\t\tentries[TSI721_VECT_DMA0_INT + i].entry =\n\t\t\t\t\tTSI721_MSIX_DMACH_INT(i);\n\t}\n#endif /* CONFIG_RAPIDIO_DMA_ENGINE */\n\n\terr = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries));\n\tif (err) {\n\t\ttsi_err(&priv->pdev->dev,\n\t\t\t\"Failed to enable MSI-X (err=%d)\", err);\n\t\treturn err;\n\t}\n\n\t/*\n\t * Copy MSI-X vector information into tsi721 private structure\n\t */\n\tpriv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;\n\tsnprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,\n\t\t DRV_NAME \"-idb@pci:%s\", pci_name(priv->pdev));\n\tpriv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;\n\tsnprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,\n\t\t DRV_NAME \"-pwrx@pci:%s\", pci_name(priv->pdev));\n\n\tfor (i = 0; i < RIO_MAX_MBOX; i++) {\n\t\tpriv->msix[TSI721_VECT_IMB0_RCV + i].vector =\n\t\t\t\tentries[TSI721_VECT_IMB0_RCV + i].vector;\n\t\tsnprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,\n\t\t\t IRQ_DEVICE_NAME_MAX, DRV_NAME \"-imbr%d@pci:%s\",\n\t\t\t i, pci_name(priv->pdev));\n\n\t\tpriv->msix[TSI721_VECT_IMB0_INT + i].vector =\n\t\t\t\tentries[TSI721_VECT_IMB0_INT + i].vector;\n\t\tsnprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,\n\t\t\t IRQ_DEVICE_NAME_MAX, DRV_NAME \"-imbi%d@pci:%s\",\n\t\t\t i, pci_name(priv->pdev));\n\n\t\tpriv->msix[TSI721_VECT_OMB0_DONE + i].vector =\n\t\t\t\tentries[TSI721_VECT_OMB0_DONE + i].vector;\n\t\tsnprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,\n\t\t\t IRQ_DEVICE_NAME_MAX, DRV_NAME \"-ombd%d@pci:%s\",\n\t\t\t i, pci_name(priv->pdev));\n\n\t\tpriv->msix[TSI721_VECT_OMB0_INT + i].vector =\n\t\t\t\tentries[TSI721_VECT_OMB0_INT + i].vector;\n\t\tsnprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,\n\t\t\t IRQ_DEVICE_NAME_MAX, DRV_NAME \"-ombi%d@pci:%s\",\n\t\t\t i, pci_name(priv->pdev));\n\t}\n\n#ifdef CONFIG_RAPIDIO_DMA_ENGINE\n\tfor (i = 0; i < TSI721_DMA_CHNUM; i++) {\n\t\tpriv->msix[TSI721_VECT_DMA0_DONE + i].vector =\n\t\t\t\tentries[TSI721_VECT_DMA0_DONE + i].vector;\n\t\tsnprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,\n\t\t\t IRQ_DEVICE_NAME_MAX, DRV_NAME \"-dmad%d@pci:%s\",\n\t\t\t i, pci_name(priv->pdev));\n\n\t\tpriv->msix[TSI721_VECT_DMA0_INT + i].vector =\n\t\t\t\tentries[TSI721_VECT_DMA0_INT + i].vector;\n\t\tsnprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,\n\t\t\t IRQ_DEVICE_NAME_MAX, DRV_NAME \"-dmai%d@pci:%s\",\n\t\t\t i, pci_name(priv->pdev));\n\t}\n#endif /* CONFIG_RAPIDIO_DMA_ENGINE */\n\n\treturn 0;\n}",
        "static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)\n{\n\tu32 len;\n\tu8 *data;\n": "static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)\n{\n\tu32 len;\n\tu8 *data;\n\n\trtl_reset_ocp_base(tp);\n\n\tif (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {\n\t\tdev_dbg(&tp->intf->dev, \"PHY firmware has been the newest\\n\");\n\t\treturn;\n\t}\n\n\tlen = __le32_to_cpu(phy->blk_hdr.length);\n\tlen -= __le16_to_cpu(phy->fw_offset);\n\tdata = (u8 *)phy + __le16_to_cpu(phy->fw_offset);\n\n\tif (rtl_phy_patch_request(tp, true, wait))\n\t\treturn;\n\n\twhile (len) {\n\t\tu32 ocp_data, size;\n\t\tint i;\n\n\t\tif (len < 2048)\n\t\t\tsize = len;\n\t\telse\n\t\t\tsize = 2048;\n\n\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);\n\t\tocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;\n\t\tocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);\n\n\t\tgeneric_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);\n\n\t\tdata += size;\n\t\tlen -= size;\n\n\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);\n\t\tocp_data |= POL_GPHY_PATCH;\n\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);\n\n\t\tfor (i = 0; i < 1000; i++) {\n\t\t\tif (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (i == 1000) {\n\t\t\tdev_err(&tp->intf->dev, \"ram code speedup mode timeout\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\trtl_reset_ocp_base(tp);\n\n\trtl_phy_patch_request(tp, false, wait);\n\n\tif (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))\n\t\tdev_dbg(&tp->intf->dev, \"successfully applied %s\\n\", phy->info);\n\telse\n\t\tdev_err(&tp->intf->dev, \"ram code speedup mode fail\\n\");\n}",
        "static int pppoatm_may_send(struct pppoatm_vcc *pvcc, int size)\n{\n\t/*\n\t * It's not clear that we need to bother with using atm_may_send()\n\t * to check we don't exceed sk->sk_sndbuf. If userspace sets a": "static int pppoatm_may_send(struct pppoatm_vcc *pvcc, int size)\n{\n\t/*\n\t * It's not clear that we need to bother with using atm_may_send()\n\t * to check we don't exceed sk->sk_sndbuf. If userspace sets a\n\t * value of sk_sndbuf which is lower than the MTU, we're going to\n\t * block for ever. But the code always did that before we introduced\n\t * the packet count limit, so...\n\t */\n\tif (atm_may_send(pvcc->atmvcc, size) &&\n\t    atomic_inc_not_zero(&pvcc->inflight))\n\t\treturn 1;\n\n\t/*\n\t * We use test_and_set_bit() rather than set_bit() here because\n\t * we need to ensure there's a memory barrier after it. The bit\n\t * *must* be set before we do the atomic_inc() on pvcc->inflight.\n\t * There's no smp_mb__after_set_bit(), so it's this or abuse\n\t * smp_mb__after_atomic().\n\t */\n\ttest_and_set_bit(BLOCKED, &pvcc->blocked);\n\n\t/*\n\t * We may have raced with pppoatm_pop(). If it ran for the\n\t * last packet in the queue, *just* before we set the BLOCKED\n\t * bit, then it might never run again and the channel could\n\t * remain permanently blocked. Cope with that race by checking\n\t * *again*. If it did run in that window, we'll have space on\n\t * the queue now and can return success. It's harmless to leave\n\t * the BLOCKED flag set, since it's only used as a trigger to\n\t * run the wakeup tasklet. Another wakeup will never hurt.\n\t * If pppoatm_pop() is running but hasn't got as far as making\n\t * space on the queue yet, then it hasn't checked the BLOCKED\n\t * flag yet either, so we're safe in that case too. It'll issue\n\t * an \"immediate\" wakeup... where \"immediate\" actually involves\n\t * taking the PPP channel's ->downl lock, which is held by the\n\t * code path that calls pppoatm_send(), and is thus going to\n\t * wait for us to finish.\n\t */\n\tif (atm_may_send(pvcc->atmvcc, size) &&\n\t    atomic_inc_not_zero(&pvcc->inflight))\n\t\treturn 1;\n\n\treturn 0;\n}",
        "static void cops_load (struct net_device *dev)\n{\n        struct ifreq ifr;\n        struct ltfirmware *ltf= (struct ltfirmware *)&ifr.ifr_ifru;\n        struct cops_local *lp = netdev_priv(dev);": "static void cops_load (struct net_device *dev)\n{\n        struct ifreq ifr;\n        struct ltfirmware *ltf= (struct ltfirmware *)&ifr.ifr_ifru;\n        struct cops_local *lp = netdev_priv(dev);\n        int ioaddr=dev->base_addr;\n\tint length, i = 0;\n\n        strcpy(ifr.ifr_name,\"lt0\");\n\n        /* Get card's firmware code and do some checks on it. */\n#ifdef CONFIG_COPS_DAYNA        \n        if(lp->board==DAYNA)\n        {\n                ltf->length=sizeof(ffdrv_code);\n                ltf->data=ffdrv_code;\n        }\n        else\n#endif        \n#ifdef CONFIG_COPS_TANGENT\n        if(lp->board==TANGENT)\n        {\n                ltf->length=sizeof(ltdrv_code);\n                ltf->data=ltdrv_code;\n        }\n        else\n#endif\n\t{\n\t\tprintk(KERN_INFO \"%s; unsupported board type.\\n\", dev->name);\n\t\treturn;\n\t}\n\t\n        /* Check to make sure firmware is correct length. */\n        if(lp->board==DAYNA && ltf->length!=5983)\n        {\n                printk(KERN_WARNING \"%s: Firmware is not length of FFDRV.BIN.\\n\", dev->name);\n                return;\n        }\n        if(lp->board==TANGENT && ltf->length!=2501)\n        {\n                printk(KERN_WARNING \"%s: Firmware is not length of DRVCODE.BIN.\\n\", dev->name);\n                return;\n        }\n\n        if(lp->board==DAYNA)\n        {\n                /*\n                 *      We must wait for a status response\n                 *      with the DAYNA board.\n                 */\n                while(++i<65536)\n                {\n                       if((inb(ioaddr+DAYNA_CARD_STATUS)&3)==1)\n                                break;\n                }\n\n                if(i==65536)\n                        return;\n        }\n\n        /*\n         *      Upload the firmware and kick. Byte-by-byte works nicely here.\n         */\n\ti=0;\n        length = ltf->length;\n        while(length--)\n        {\n                outb(ltf->data[i], ioaddr);\n                i++;\n        }\n\n\tif(cops_debug > 1)\n\t\tprintk(\"%s: Uploaded firmware - %d bytes of %d bytes.\\n\", \n\t\t\tdev->name, i, ltf->length);\n\n        if(lp->board==DAYNA) \t/* Tell Dayna to run the firmware code. */\n                outb(1, ioaddr+DAYNA_INT_CARD);\n\telse\t\t\t/* Tell Tang to run the firmware code. */\n\t\tinb(ioaddr);\n\n        if(lp->board==TANGENT)\n        {\n                tangent_wait_reset(ioaddr);\n                inb(ioaddr);\t/* Clear initial ready signal. */\n        }\n}",
        "static int load_capture_binaries(struct ia_css_pipe *pipe)\n{\n\tint err = 0;\n\tbool must_be_raw;\n": "static int load_capture_binaries(struct ia_css_pipe *pipe)\n{\n\tint err = 0;\n\tbool must_be_raw;\n\n\tIA_CSS_ENTER_PRIVATE(\"\");\n\tassert(pipe);\n\tassert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE ||\n\t       pipe->mode == IA_CSS_PIPE_ID_COPY);\n\n\tif (pipe->pipe_settings.capture.primary_binary[0].info) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(0);\n\t\treturn 0;\n\t}\n\n\t/* in primary, advanced,low light or bayer,\n\t\t\t\t\t\tthe input format must be raw */\n\tmust_be_raw =\n\t    pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED ||\n\t    pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER ||\n\t    pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT;\n\terr = ia_css_util_check_input(&pipe->stream->config, must_be_raw, false);\n\tif (err) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\treturn err;\n\t}\n\tif (copy_on_sp(pipe) &&\n\t    pipe->stream->config.input_config.format == ATOMISP_INPUT_FORMAT_BINARY_8) {\n\t\tia_css_frame_info_init(\n\t\t    &pipe->output_info[0],\n\t\t    JPEG_BYTES,\n\t\t    1,\n\t\t    IA_CSS_FRAME_FORMAT_BINARY_8,\n\t\t    0);\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(0);\n\t\treturn 0;\n\t}\n\n\tswitch (pipe->config.default_capture_config.mode) {\n\tcase IA_CSS_CAPTURE_MODE_RAW:\n\t\terr = load_copy_binaries(pipe);\n#if defined(ISP2401)\n\t\tif (!err)\n\t\t\tpipe->pipe_settings.capture.copy_binary.online = pipe->stream->config.online;\n#endif\n\t\tbreak;\n\tcase IA_CSS_CAPTURE_MODE_BAYER:\n\t\terr = load_bayer_isp_binaries(pipe);\n\t\tbreak;\n\tcase IA_CSS_CAPTURE_MODE_PRIMARY:\n\t\terr = load_primary_binaries(pipe);\n\t\tbreak;\n\tcase IA_CSS_CAPTURE_MODE_ADVANCED:\n\t\terr = load_advanced_binaries(pipe);\n\t\tbreak;\n\tcase IA_CSS_CAPTURE_MODE_LOW_LIGHT:\n\t\terr = load_low_light_binaries(pipe);\n\t\tbreak;\n\t}\n\tif (err) {\n\t\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\t\treturn err;\n\t}\n\n\tIA_CSS_LEAVE_ERR_PRIVATE(err);\n\treturn err;\n}",
        "static void bfq_update_rate_reset(struct bfq_data *bfqd, struct request *rq)\n{\n\tu32 rate, weight, divisor;\n\n\t/*": "static void bfq_update_rate_reset(struct bfq_data *bfqd, struct request *rq)\n{\n\tu32 rate, weight, divisor;\n\n\t/*\n\t * For the convergence property to hold (see comments on\n\t * bfq_update_peak_rate()) and for the assessment to be\n\t * reliable, a minimum number of samples must be present, and\n\t * a minimum amount of time must have elapsed. If not so, do\n\t * not compute new rate. Just reset parameters, to get ready\n\t * for a new evaluation attempt.\n\t */\n\tif (bfqd->peak_rate_samples < BFQ_RATE_MIN_SAMPLES ||\n\t    bfqd->delta_from_first < BFQ_RATE_MIN_INTERVAL)\n\t\tgoto reset_computation;\n\n\t/*\n\t * If a new request completion has occurred after last\n\t * dispatch, then, to approximate the rate at which requests\n\t * have been served by the device, it is more precise to\n\t * extend the observation interval to the last completion.\n\t */\n\tbfqd->delta_from_first =\n\t\tmax_t(u64, bfqd->delta_from_first,\n\t\t      bfqd->last_completion - bfqd->first_dispatch);\n\n\t/*\n\t * Rate computed in sects/usec, and not sects/nsec, for\n\t * precision issues.\n\t */\n\trate = div64_ul(bfqd->tot_sectors_dispatched<<BFQ_RATE_SHIFT,\n\t\t\tdiv_u64(bfqd->delta_from_first, NSEC_PER_USEC));\n\n\t/*\n\t * Peak rate not updated if:\n\t * - the percentage of sequential dispatches is below 3/4 of the\n\t *   total, and rate is below the current estimated peak rate\n\t * - rate is unreasonably high (> 20M sectors/sec)\n\t */\n\tif ((bfqd->sequential_samples < (3 * bfqd->peak_rate_samples)>>2 &&\n\t     rate <= bfqd->peak_rate) ||\n\t\trate > 20<<BFQ_RATE_SHIFT)\n\t\tgoto reset_computation;\n\n\t/*\n\t * We have to update the peak rate, at last! To this purpose,\n\t * we use a low-pass filter. We compute the smoothing constant\n\t * of the filter as a function of the 'weight' of the new\n\t * measured rate.\n\t *\n\t * As can be seen in next formulas, we define this weight as a\n\t * quantity proportional to how sequential the workload is,\n\t * and to how long the observation time interval is.\n\t *\n\t * The weight runs from 0 to 8. The maximum value of the\n\t * weight, 8, yields the minimum value for the smoothing\n\t * constant. At this minimum value for the smoothing constant,\n\t * the measured rate contributes for half of the next value of\n\t * the estimated peak rate.\n\t *\n\t * So, the first step is to compute the weight as a function\n\t * of how sequential the workload is. Note that the weight\n\t * cannot reach 9, because bfqd->sequential_samples cannot\n\t * become equal to bfqd->peak_rate_samples, which, in its\n\t * turn, holds true because bfqd->sequential_samples is not\n\t * incremented for the first sample.\n\t */\n\tweight = (9 * bfqd->sequential_samples) / bfqd->peak_rate_samples;\n\n\t/*\n\t * Second step: further refine the weight as a function of the\n\t * duration of the observation interval.\n\t */\n\tweight = min_t(u32, 8,\n\t\t       div_u64(weight * bfqd->delta_from_first,\n\t\t\t       BFQ_RATE_REF_INTERVAL));\n\n\t/*\n\t * Divisor ranging from 10, for minimum weight, to 2, for\n\t * maximum weight.\n\t */\n\tdivisor = 10 - weight;\n\n\t/*\n\t * Finally, update peak rate:\n\t *\n\t * peak_rate = peak_rate * (divisor-1) / divisor  +  rate / divisor\n\t */\n\tbfqd->peak_rate *= divisor-1;\n\tbfqd->peak_rate /= divisor;\n\trate /= divisor; /* smoothing constant alpha = 1/divisor */\n\n\tbfqd->peak_rate += rate;\n\n\t/*\n\t * For a very slow device, bfqd->peak_rate can reach 0 (see\n\t * the minimum representable values reported in the comments\n\t * on BFQ_RATE_SHIFT). Push to 1 if this happens, to avoid\n\t * divisions by zero where bfqd->peak_rate is used as a\n\t * divisor.\n\t */\n\tbfqd->peak_rate = max_t(u32, 1, bfqd->peak_rate);\n\n\tupdate_thr_responsiveness_params(bfqd);\n\nreset_computation:\n\tbfq_reset_rate_computation(bfqd, rq);\n}",
        "static void bad_core_relo(size_t log_buf_size, enum trunc_type trunc_type)\n{\n\tchar log_buf[8 * 1024];\n\tstruct test_log_fixup* skel;\n\tint err;": "static void bad_core_relo(size_t log_buf_size, enum trunc_type trunc_type)\n{\n\tchar log_buf[8 * 1024];\n\tstruct test_log_fixup* skel;\n\tint err;\n\n\tskel = test_log_fixup__open();\n\tif (!ASSERT_OK_PTR(skel, \"skel_open\"))\n\t\treturn;\n\n\tbpf_program__set_autoload(skel->progs.bad_relo, true);\n\tmemset(log_buf, 0, sizeof(log_buf));\n\tbpf_program__set_log_buf(skel->progs.bad_relo, log_buf, log_buf_size ?: sizeof(log_buf));\n\n\terr = test_log_fixup__load(skel);\n\tif (!ASSERT_ERR(err, \"load_fail\"))\n\t\tgoto cleanup;\n\n\tASSERT_HAS_SUBSTR(log_buf,\n\t\t\t  \"0: <invalid CO-RE relocation>\\n\"\n\t\t\t  \"failed to resolve CO-RE relocation <byte_sz> \",\n\t\t\t  \"log_buf_part1\");\n\n\tswitch (trunc_type) {\n\tcase TRUNC_NONE:\n\t\tASSERT_HAS_SUBSTR(log_buf,\n\t\t\t\t  \"struct task_struct___bad.fake_field (0:1 @ offset 4)\\n\",\n\t\t\t\t  \"log_buf_part2\");\n\t\tASSERT_HAS_SUBSTR(log_buf,\n\t\t\t\t  \"max_states_per_insn 0 total_states 0 peak_states 0 mark_read 0\\n\",\n\t\t\t\t  \"log_buf_end\");\n\t\tbreak;\n\tcase TRUNC_PARTIAL:\n\t\t/* we should get full libbpf message patch */\n\t\tASSERT_HAS_SUBSTR(log_buf,\n\t\t\t\t  \"struct task_struct___bad.fake_field (0:1 @ offset 4)\\n\",\n\t\t\t\t  \"log_buf_part2\");\n\t\t/* we shouldn't get full end of BPF verifier log */\n\t\tASSERT_NULL(strstr(log_buf, \"max_states_per_insn 0 total_states 0 peak_states 0 mark_read 0\\n\"),\n\t\t\t    \"log_buf_end\");\n\t\tbreak;\n\tcase TRUNC_FULL:\n\t\t/* we shouldn't get second part of libbpf message patch */\n\t\tASSERT_NULL(strstr(log_buf, \"struct task_struct___bad.fake_field (0:1 @ offset 4)\\n\"),\n\t\t\t    \"log_buf_part2\");\n\t\t/* we shouldn't get full end of BPF verifier log */\n\t\tASSERT_NULL(strstr(log_buf, \"max_states_per_insn 0 total_states 0 peak_states 0 mark_read 0\\n\"),\n\t\t\t    \"log_buf_end\");\n\t\tbreak;\n\t}\n\n\tif (env.verbosity > VERBOSE_NONE)\n\t\tprintf(\"LOG:   \\n=================\\n%s=================\\n\", log_buf);\ncleanup:\n\ttest_log_fixup__destroy(skel);\n}",
        "static int jent_measure_jitter(struct rand_data *ec)\n{\n\t__u64 time = 0;\n\t__u64 current_delta = 0;\n\tint stuck;": "static int jent_measure_jitter(struct rand_data *ec)\n{\n\t__u64 time = 0;\n\t__u64 current_delta = 0;\n\tint stuck;\n\n\t/* Invoke one noise source before time measurement to add variations */\n\tjent_memaccess(ec, 0);\n\n\t/*\n\t * Get time stamp and calculate time delta to previous\n\t * invocation to measure the timing variations\n\t */\n\tjent_get_nstime(&time);\n\tcurrent_delta = jent_delta(ec->prev_time, time);\n\tec->prev_time = time;\n\n\t/* Check whether we have a stuck measurement. */\n\tstuck = jent_stuck(ec, current_delta);\n\n\t/* Now call the next noise sources which also injects the data */\n\tjent_lfsr_time(ec, current_delta, 0, stuck);\n\n\treturn stuck;\n}",
        "static struct key_vector *tnode_new(t_key key, int pos, int bits)\n{\n\tunsigned int shift = pos + bits;\n\tstruct key_vector *tn;\n\tstruct tnode *tnode;": "static struct key_vector *tnode_new(t_key key, int pos, int bits)\n{\n\tunsigned int shift = pos + bits;\n\tstruct key_vector *tn;\n\tstruct tnode *tnode;\n\n\t/* verify bits and pos their msb bits clear and values are valid */\n\tBUG_ON(!bits || (shift > KEYLENGTH));\n\n\ttnode = tnode_alloc(bits);\n\tif (!tnode)\n\t\treturn NULL;\n\n\tpr_debug(\"AT %p s=%zu %zu\\n\", tnode, TNODE_SIZE(0),\n\t\t sizeof(struct key_vector *) << bits);\n\n\tif (bits == KEYLENGTH)\n\t\ttnode->full_children = 1;\n\telse\n\t\ttnode->empty_children = 1ul << bits;\n\n\ttn = tnode->kv;\n\ttn->key = (shift < KEYLENGTH) ? (key >> shift) << shift : 0;\n\ttn->pos = pos;\n\ttn->bits = bits;\n\ttn->slen = pos;\n\n\treturn tn;\n}",
        "static void two_out_pipe(struct adapter *adapter, bool wifi_cfg)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);\n\n\tif (wifi_cfg) { /* WMM */": "static void two_out_pipe(struct adapter *adapter, bool wifi_cfg)\n{\n\tstruct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);\n\n\tif (wifi_cfg) { /* WMM */\n\t\t/* BK, BE, VI, VO, BCN,\tCMD, MGT, HIGH, HCCA */\n\t\t/*  0,  1,  0,  1,   0,   0,   0,    0,    0}; */\n\t\t/* 0:H, 1:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\n\t} else {/* typical setting */\n\t\t/* BK, BE, VI, VO, BCN,\tCMD, MGT, HIGH, HCCA */\n\t\t/*  1,\t1,  0,  0,   0,   0,   0,    0,    0}; */\n\t\t/* 0:H, 1:L */\n\n\t\tpdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */\n\t\tpdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */\n\t\tpdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */\n\t\tpdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */\n\n\t\tpdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */\n\t\tpdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */\n\t\tpdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */\n\t\tpdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */\n\t}\n}",
        "static int nvsw_sn2201_config_init(struct nvsw_sn2201 *nvsw_sn2201, void *regmap)\n{\n\tstruct device *dev = nvsw_sn2201->dev;\n\tint err;\n": "static int nvsw_sn2201_config_init(struct nvsw_sn2201 *nvsw_sn2201, void *regmap)\n{\n\tstruct device *dev = nvsw_sn2201->dev;\n\tint err;\n\n\tnvsw_sn2201->io_data = &nvsw_sn2201_regs_io;\n\tnvsw_sn2201->led_data = &nvsw_sn2201_led;\n\tnvsw_sn2201->wd_data = &nvsw_sn2201_wd;\n\tnvsw_sn2201->hotplug_data = &nvsw_sn2201_hotplug;\n\n\t/* Register IO access driver. */\n\tif (nvsw_sn2201->io_data) {\n\t\tnvsw_sn2201->io_data->regmap = regmap;\n\t\tnvsw_sn2201->io_regs =\n\t\tplatform_device_register_resndata(dev, \"mlxreg-io\", PLATFORM_DEVID_NONE, NULL, 0,\n\t\t\t\t\t\t  nvsw_sn2201->io_data,\n\t\t\t\t\t\t  sizeof(*nvsw_sn2201->io_data));\n\t\tif (IS_ERR(nvsw_sn2201->io_regs)) {\n\t\t\terr = PTR_ERR(nvsw_sn2201->io_regs);\n\t\t\tgoto fail_register_io;\n\t\t}\n\t}\n\n\t/* Register LED driver. */\n\tif (nvsw_sn2201->led_data) {\n\t\tnvsw_sn2201->led_data->regmap = regmap;\n\t\tnvsw_sn2201->led =\n\t\tplatform_device_register_resndata(dev, \"leds-mlxreg\", PLATFORM_DEVID_NONE, NULL, 0,\n\t\t\t\t\t\t  nvsw_sn2201->led_data,\n\t\t\t\t\t\t  sizeof(*nvsw_sn2201->led_data));\n\t\tif (IS_ERR(nvsw_sn2201->led)) {\n\t\t\terr = PTR_ERR(nvsw_sn2201->led);\n\t\t\tgoto fail_register_led;\n\t\t}\n\t}\n\n\t/* Register WD driver. */\n\tif (nvsw_sn2201->wd_data) {\n\t\tnvsw_sn2201->wd_data->regmap = regmap;\n\t\tnvsw_sn2201->wd =\n\t\tplatform_device_register_resndata(dev, \"mlx-wdt\", PLATFORM_DEVID_NONE, NULL, 0,\n\t\t\t\t\t\t  nvsw_sn2201->wd_data,\n\t\t\t\t\t\t  sizeof(*nvsw_sn2201->wd_data));\n\t\tif (IS_ERR(nvsw_sn2201->wd)) {\n\t\t\terr = PTR_ERR(nvsw_sn2201->wd);\n\t\t\tgoto fail_register_wd;\n\t\t}\n\t}\n\n\t/* Register hotplug driver. */\n\tif (nvsw_sn2201->hotplug_data) {\n\t\tnvsw_sn2201->hotplug_data->regmap = regmap;\n\t\tnvsw_sn2201->pdev_hotplug =\n\t\tplatform_device_register_resndata(dev, \"mlxreg-hotplug\", PLATFORM_DEVID_NONE,\n\t\t\t\t\t\t  nvsw_sn2201_cpld_res,\n\t\t\t\t\t\t  ARRAY_SIZE(nvsw_sn2201_cpld_res),\n\t\t\t\t\t\t  nvsw_sn2201->hotplug_data,\n\t\t\t\t\t\t  sizeof(*nvsw_sn2201->hotplug_data));\n\t\tif (IS_ERR(nvsw_sn2201->pdev_hotplug)) {\n\t\t\terr = PTR_ERR(nvsw_sn2201->pdev_hotplug);\n\t\t\tgoto fail_register_hotplug;\n\t\t}\n\t}\n\n\treturn nvsw_sn2201_config_post_init(nvsw_sn2201);\n\nfail_register_hotplug:\n\tif (nvsw_sn2201->wd)\n\t\tplatform_device_unregister(nvsw_sn2201->wd);\nfail_register_wd:\n\tif (nvsw_sn2201->led)\n\t\tplatform_device_unregister(nvsw_sn2201->led);\nfail_register_led:\n\tif (nvsw_sn2201->io_regs)\n\t\tplatform_device_unregister(nvsw_sn2201->io_regs);\nfail_register_io:\n\n\treturn err;\n}",
        "static void vmalloc_percpu(struct kunit *test)\n{\n\tchar __percpu *ptr;\n\tint cpu;\n": "static void vmalloc_percpu(struct kunit *test)\n{\n\tchar __percpu *ptr;\n\tint cpu;\n\n\t/*\n\t * This test is specifically crafted for the software tag-based mode,\n\t * the only tag-based mode that poisons percpu mappings.\n\t */\n\tKASAN_TEST_NEEDS_CONFIG_ON(test, CONFIG_KASAN_SW_TAGS);\n\n\tptr = __alloc_percpu(PAGE_SIZE, PAGE_SIZE);\n\n\tfor_each_possible_cpu(cpu) {\n\t\tchar *c_ptr = per_cpu_ptr(ptr, cpu);\n\n\t\tKUNIT_EXPECT_GE(test, (u8)get_tag(c_ptr), (u8)KASAN_TAG_MIN);\n\t\tKUNIT_EXPECT_LT(test, (u8)get_tag(c_ptr), (u8)KASAN_TAG_KERNEL);\n\n\t\t/* Make sure that in-bounds accesses don't crash the kernel. */\n\t\t*c_ptr = 0;\n\t}\n\n\tfree_percpu(ptr);\n}",
        "static void slimpro_i2c_pcc_rx_cb(struct mbox_client *cl, void *msg)\n{\n\tstruct slimpro_i2c_dev *ctx = to_slimpro_i2c_dev(cl);\n\tstruct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;\n": "static void slimpro_i2c_pcc_rx_cb(struct mbox_client *cl, void *msg)\n{\n\tstruct slimpro_i2c_dev *ctx = to_slimpro_i2c_dev(cl);\n\tstruct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;\n\n\t/* Check if platform sends interrupt */\n\tif (!xgene_word_tst_and_clr(&generic_comm_base->status,\n\t\t\t\t    PCC_STS_SCI_DOORBELL))\n\t\treturn;\n\n\tif (xgene_word_tst_and_clr(&generic_comm_base->status,\n\t\t\t\t   PCC_STS_CMD_COMPLETE)) {\n\t\tmsg = generic_comm_base + 1;\n\n\t\t/* Response message msg[1] contains the return value. */\n\t\tif (ctx->resp_msg)\n\t\t\t*ctx->resp_msg = ((u32 *)msg)[1];\n\n\t\tcomplete(&ctx->rd_complete);\n\t}\n}",
        "static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value)\n{\n\tstruct i2c_client *c = v4l2_get_subdevdata(sd);\n\tint err;\n\t/* set for direct mode */": "static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value)\n{\n\tstruct i2c_client *c = v4l2_get_subdevdata(sd);\n\tint err;\n\t/* set for direct mode */\n\terr = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850);\n\tif (value >= 1) {\n\t\t/* enable H flip - ctx A */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x01);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x01);\n\t\t/* ctx B */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x01);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x01);\n\n\t\terr += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE,\n\t\t\t\t\tMISENSOR_VFLIP_MASK, MISENSOR_FLIP_EN);\n\t} else {\n\t\t/* disable H flip - ctx A */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x00);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x00);\n\t\t/* ctx B */\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x00);\n\t\terr += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x00);\n\n\t\terr += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE,\n\t\t\t\t\tMISENSOR_VFLIP_MASK, MISENSOR_FLIP_DIS);\n\t}\n\n\terr += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06);\n\tudelay(10);\n\n\treturn !!err;\n}",
        "static bool shuffle_freelist(struct kmem_cache *cachep, struct slab *slab)\n{\n\tunsigned int objfreelist = 0, i, rand, count = cachep->num;\n\tunion freelist_init_state state;\n\tbool precomputed;": "static bool shuffle_freelist(struct kmem_cache *cachep, struct slab *slab)\n{\n\tunsigned int objfreelist = 0, i, rand, count = cachep->num;\n\tunion freelist_init_state state;\n\tbool precomputed;\n\n\tif (count < 2)\n\t\treturn false;\n\n\tprecomputed = freelist_state_initialize(&state, cachep, count);\n\n\t/* Take a random entry as the objfreelist */\n\tif (OBJFREELIST_SLAB(cachep)) {\n\t\tif (!precomputed)\n\t\t\tobjfreelist = count - 1;\n\t\telse\n\t\t\tobjfreelist = next_random_slot(&state);\n\t\tslab->freelist = index_to_obj(cachep, slab, objfreelist) +\n\t\t\t\t\t\tobj_offset(cachep);\n\t\tcount--;\n\t}\n\n\t/*\n\t * On early boot, generate the list dynamically.\n\t * Later use a pre-computed list for speed.\n\t */\n\tif (!precomputed) {\n\t\tfor (i = 0; i < count; i++)\n\t\t\tset_free_obj(slab, i, i);\n\n\t\t/* Fisher-Yates shuffle */\n\t\tfor (i = count - 1; i > 0; i--) {\n\t\t\trand = prandom_u32_state(&state.rnd_state);\n\t\t\trand %= (i + 1);\n\t\t\tswap_free_obj(slab, i, rand);\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < count; i++)\n\t\t\tset_free_obj(slab, i, next_random_slot(&state));\n\t}\n\n\tif (OBJFREELIST_SLAB(cachep))\n\t\tset_free_obj(slab, cachep->num - 1, objfreelist);\n\n\treturn true;\n}",
        "static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)\n{\n\tu32 val;\n\n\t/*Set Debug Registers*/": "static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)\n{\n\tu32 val;\n\n\t/*Set Debug Registers*/\n\tval = DEBUG_STATUS_CFG_STATUS0(1) |\n\t      DEBUG_STATUS_CFG_STATUS0(7);\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG);\n\n\t/* BUS_WM_INPUT_IF_ADDR_SYNC_FRAME_HEADER */\n\twritel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER);\n\n\t/* no clock gating at bus input */\n\tval = WM_CGC_OVERRIDE_ALL;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);\n\n\twritel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);\n\n\t/* if addr_no_sync has default value then config the addr no sync reg */\n\tval = WM_ADDR_NO_SYNC_DEFAULT_VAL;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC);\n\n\twritel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));\n\n\tval = WM_BUFFER_DEFAULT_WIDTH;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm));\n\n\tval = 0;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm));\n\n\tval = 0;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); // XXX 1 for PLAIN8?\n\n\t/* Configure stride for RDIs */\n\tval = WM_STRIDE_DEFAULT_STRIDE;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm));\n\n\t/* Enable WM */\n\tval = 1 << WM_CFG_EN |\n\t      MODE_MIPI_RAW << WM_CFG_MODE;\n\twritel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm));\n}",
        "static void cfi_tell_features(struct cfi_pri_amdstd *extp)\n{\n\tconst char* erase_suspend[3] = {\n\t\t\"Not supported\", \"Read only\", \"Read/write\"\n\t};": "static void cfi_tell_features(struct cfi_pri_amdstd *extp)\n{\n\tconst char* erase_suspend[3] = {\n\t\t\"Not supported\", \"Read only\", \"Read/write\"\n\t};\n\tconst char* top_bottom[6] = {\n\t\t\"No WP\", \"8x8KiB sectors at top & bottom, no WP\",\n\t\t\"Bottom boot\", \"Top boot\",\n\t\t\"Uniform, Bottom WP\", \"Uniform, Top WP\"\n\t};\n\n\tprintk(\"  Silicon revision: %d\\n\", extp->SiliconRevision >> 1);\n\tprintk(\"  Address sensitive unlock: %s\\n\",\n\t       (extp->SiliconRevision & 1) ? \"Not required\" : \"Required\");\n\n\tif (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))\n\t\tprintk(\"  Erase Suspend: %s\\n\", erase_suspend[extp->EraseSuspend]);\n\telse\n\t\tprintk(\"  Erase Suspend: Unknown value %d\\n\", extp->EraseSuspend);\n\n\tif (extp->BlkProt == 0)\n\t\tprintk(\"  Block protection: Not supported\\n\");\n\telse\n\t\tprintk(\"  Block protection: %d sectors per group\\n\", extp->BlkProt);\n\n\n\tprintk(\"  Temporary block unprotect: %s\\n\",\n\t       extp->TmpBlkUnprotect ? \"Supported\" : \"Not supported\");\n\tprintk(\"  Block protect/unprotect scheme: %d\\n\", extp->BlkProtUnprot);\n\tprintk(\"  Number of simultaneous operations: %d\\n\", extp->SimultaneousOps);\n\tprintk(\"  Burst mode: %s\\n\",\n\t       extp->BurstMode ? \"Supported\" : \"Not supported\");\n\tif (extp->PageMode == 0)\n\t\tprintk(\"  Page mode: Not supported\\n\");\n\telse\n\t\tprintk(\"  Page mode: %d word page\\n\", extp->PageMode << 2);\n\n\tprintk(\"  Vpp Supply Minimum Program/Erase Voltage: %d.%d V\\n\",\n\t       extp->VppMin >> 4, extp->VppMin & 0xf);\n\tprintk(\"  Vpp Supply Maximum Program/Erase Voltage: %d.%d V\\n\",\n\t       extp->VppMax >> 4, extp->VppMax & 0xf);\n\n\tif (extp->TopBottom < ARRAY_SIZE(top_bottom))\n\t\tprintk(\"  Top/Bottom Boot Block: %s\\n\", top_bottom[extp->TopBottom]);\n\telse\n\t\tprintk(\"  Top/Bottom Boot Block: Unknown value %d\\n\", extp->TopBottom);\n}",
        "static void process_softint(struct anybuss_host *cd)\n{\n\tstruct anybuss_client *client = cd->client;\n\tstatic const u8 zero;\n\tint ret;": "static void process_softint(struct anybuss_host *cd)\n{\n\tstruct anybuss_client *client = cd->client;\n\tstatic const u8 zero;\n\tint ret;\n\tunsigned int ind_ap, ev;\n\tstruct ab_task *t;\n\n\tif (!cd->power_on)\n\t\treturn;\n\tif (cd->softint_pending)\n\t\treturn;\n\tregmap_read(cd->regmap, REG_IND_AP, &ind_ap);\n\tif (!((atomic_read(&cd->ind_ab) ^ ind_ap) & IND_AX_EVNT))\n\t\treturn;\n\t/* process software interrupt */\n\tregmap_read(cd->regmap, REG_EVENT_CAUSE, &ev);\n\tif (ev & EVENT_CAUSE_FBON) {\n\t\tif (client->on_online_changed)\n\t\t\tclient->on_online_changed(client, true);\n\t\tdev_dbg(cd->dev, \"Fieldbus ON\");\n\t}\n\tif (ev & EVENT_CAUSE_FBOF) {\n\t\tif (client->on_online_changed)\n\t\t\tclient->on_online_changed(client, false);\n\t\tdev_dbg(cd->dev, \"Fieldbus OFF\");\n\t}\n\tif (ev & EVENT_CAUSE_DC) {\n\t\tif (client->on_area_updated)\n\t\t\tclient->on_area_updated(client);\n\t\tdev_dbg(cd->dev, \"Fieldbus data changed\");\n\t}\n\t/*\n\t * reset the event cause bits.\n\t * this must be done while owning the fbctrl area, so we'll\n\t * enqueue a task to do that.\n\t */\n\tt = create_area_writer(cd->qcache, IND_AX_FBCTRL,\n\t\t\t       REG_EVENT_CAUSE, &zero, sizeof(zero));\n\tif (!t) {\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\tt->done_fn = softint_ack;\n\tret = ab_task_enqueue(t, cd->powerq, &cd->qlock, &cd->wq);\n\tab_task_put(t);\n\tcd->softint_pending = true;\nout:\n\tWARN_ON(ret);\n\tif (ret)\n\t\tsoftint_ack(cd);\n}",
        "static int __test_uncore_pmu_event_aliases(struct perf_pmu_test_pmu *test_pmu)\n{\n\tint alias_count = 0, to_match_count = 0, matched_count = 0;\n\tstruct perf_pmu_test_event const **table;\n\tstruct perf_pmu *pmu = &test_pmu->pmu;": "static int __test_uncore_pmu_event_aliases(struct perf_pmu_test_pmu *test_pmu)\n{\n\tint alias_count = 0, to_match_count = 0, matched_count = 0;\n\tstruct perf_pmu_test_event const **table;\n\tstruct perf_pmu *pmu = &test_pmu->pmu;\n\tconst char *pmu_name = pmu->name;\n\tstruct perf_pmu_alias *a, *tmp, *alias;\n\tconst struct pmu_events_map *map;\n\tLIST_HEAD(aliases);\n\tint res = 0;\n\n\tmap = __test_pmu_get_events_map();\n\tif (!map)\n\t\treturn -1;\n\tpmu_add_cpu_aliases_map(&aliases, pmu, map);\n\tpmu_add_sys_aliases(&aliases, pmu);\n\n\t/* Count how many aliases we generated */\n\tlist_for_each_entry(alias, &aliases, list)\n\t\talias_count++;\n\n\t/* Count how many aliases we expect from the known table */\n\tfor (table = &test_pmu->aliases[0]; *table; table++)\n\t\tto_match_count++;\n\n\tif (alias_count != to_match_count) {\n\t\tpr_debug(\"testing aliases uncore PMU %s: mismatch expected aliases (%d) vs found (%d)\\n\",\n\t\t\t pmu_name, to_match_count, alias_count);\n\t\tres = -1;\n\t\tgoto out;\n\t}\n\n\tlist_for_each_entry(alias, &aliases, list) {\n\t\tbool matched = false;\n\n\t\tfor (table = &test_pmu->aliases[0]; *table; table++) {\n\t\t\tstruct perf_pmu_test_event const *test_event = *table;\n\t\t\tstruct pmu_event const *event = &test_event->event;\n\n\t\t\tif (!strcmp(event->name, alias->name)) {\n\t\t\t\tif (compare_alias_to_test_event(alias,\n\t\t\t\t\t\t\ttest_event,\n\t\t\t\t\t\t\tpmu_name)) {\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tmatched = true;\n\t\t\t\tmatched_count++;\n\t\t\t}\n\t\t}\n\n\t\tif (matched == false) {\n\t\t\tpr_debug(\"testing aliases uncore PMU %s: could not match alias %s\\n\",\n\t\t\t\t pmu_name, alias->name);\n\t\t\tres = -1;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (alias_count != matched_count) {\n\t\tpr_debug(\"testing aliases uncore PMU %s: mismatch found aliases (%d) vs matched (%d)\\n\",\n\t\t\t pmu_name, matched_count, alias_count);\n\t\tres = -1;\n\t}\n\nout:\n\tlist_for_each_entry_safe(a, tmp, &aliases, list) {\n\t\tlist_del(&a->list);\n\t\tperf_pmu_free_alias(a);\n\t}\n\treturn res;\n}",
        "static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct qcom_osm_l3_icc_provider *qp;\n\tstruct icc_provider *provider;\n\tconst struct qcom_osm_l3_node *qn;": "static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct qcom_osm_l3_icc_provider *qp;\n\tstruct icc_provider *provider;\n\tconst struct qcom_osm_l3_node *qn;\n\tstruct icc_node *n;\n\tunsigned int index;\n\tu32 agg_peak = 0;\n\tu32 agg_avg = 0;\n\tu64 rate;\n\n\tqn = src->data;\n\tprovider = src->provider;\n\tqp = to_osm_l3_provider(provider);\n\n\tlist_for_each_entry(n, &provider->nodes, node_list)\n\t\tprovider->aggregate(n, 0, n->avg_bw, n->peak_bw,\n\t\t\t\t    &agg_avg, &agg_peak);\n\n\trate = max(agg_avg, agg_peak);\n\trate = icc_units_to_bps(rate);\n\tdo_div(rate, qn->buswidth);\n\n\tfor (index = 0; index < qp->max_state - 1; index++) {\n\t\tif (qp->lut_tables[index] >= rate)\n\t\t\tbreak;\n\t}\n\n\twritel_relaxed(index, qp->base + qp->reg_perf_state);\n\n\treturn 0;\n}",
        "static int inquiry(struct scsi_cmnd *srb, struct rtsx_chip *chip)\n{\n\tunsigned int lun = SCSI_LUN(srb);\n\tchar *inquiry_default = (char *)\"Generic-xD/SD/M.S.      1.00 \";\n\tchar *inquiry_sdms =    (char *)\"Generic-SD/MemoryStick  1.00 \";": "static int inquiry(struct scsi_cmnd *srb, struct rtsx_chip *chip)\n{\n\tunsigned int lun = SCSI_LUN(srb);\n\tchar *inquiry_default = (char *)\"Generic-xD/SD/M.S.      1.00 \";\n\tchar *inquiry_sdms =    (char *)\"Generic-SD/MemoryStick  1.00 \";\n\tchar *inquiry_sd =      (char *)\"Generic-SD/MMC          1.00 \";\n\tchar *inquiry_ms =      (char *)\"Generic-MemoryStick     1.00 \";\n\tchar *inquiry_string;\n\tunsigned char sendbytes;\n\tunsigned char *buf;\n\tu8 card = get_lun_card(chip, lun);\n\tbool pro_formatter_flag = false;\n\tunsigned char inquiry_buf[] = {\n\t\tQULIFIRE | DRCT_ACCESS_DEV,\n\t\tRMB_DISC | 0x0D,\n\t\t0x00,\n\t\t0x01,\n\t\t0x1f,\n\t\t0x02,\n\t\t0,\n\t\tREL_ADR | WBUS_32 | WBUS_16 | SYNC | LINKED | CMD_QUE | SFT_RE,\n\t};\n\n\tif (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {\n\t\tif (chip->lun2card[lun] == SD_CARD)\n\t\t\tinquiry_string = inquiry_sd;\n\t\telse\n\t\t\tinquiry_string = inquiry_ms;\n\n\t} else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {\n\t\tinquiry_string = inquiry_sdms;\n\t} else {\n\t\tinquiry_string = inquiry_default;\n\t}\n\n\tbuf = vmalloc(scsi_bufflen(srb));\n\tif (!buf)\n\t\treturn TRANSPORT_ERROR;\n\n#ifdef SUPPORT_MAGIC_GATE\n\tif (chip->mspro_formatter_enable &&\n\t    (chip->lun2card[lun] & MS_CARD))\n#else\n\tif (chip->mspro_formatter_enable)\n#endif\n\t\tif (!card || card == MS_CARD)\n\t\t\tpro_formatter_flag = true;\n\n\tif (pro_formatter_flag) {\n\t\tif (scsi_bufflen(srb) < 56)\n\t\t\tsendbytes = (unsigned char)(scsi_bufflen(srb));\n\t\telse\n\t\t\tsendbytes = 56;\n\n\t} else {\n\t\tif (scsi_bufflen(srb) < 36)\n\t\t\tsendbytes = (unsigned char)(scsi_bufflen(srb));\n\t\telse\n\t\t\tsendbytes = 36;\n\t}\n\n\tif (sendbytes > 8) {\n\t\tmemcpy(buf, inquiry_buf, 8);\n\t\tstrncpy(buf + 8, inquiry_string, sendbytes - 8);\n\t\tif (pro_formatter_flag) {\n\t\t\t/* Additional Length */\n\t\t\tbuf[4] = 0x33;\n\t\t}\n\t} else {\n\t\tmemcpy(buf, inquiry_buf, sendbytes);\n\t}\n\n\tif (pro_formatter_flag) {\n\t\tif (sendbytes > 36)\n\t\t\tmemcpy(buf + 36, formatter_inquiry_str, sendbytes - 36);\n\t}\n\n\tscsi_set_resid(srb, 0);\n\n\trtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);\n\tvfree(buf);\n\n\treturn TRANSPORT_GOOD;\n}",
        "static void dib8000_small_fine_tune(struct dib8000_state *state)\n{\n\tu16 i;\n\tconst s16 *ncoeff;\n\tstruct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;": "static void dib8000_small_fine_tune(struct dib8000_state *state)\n{\n\tu16 i;\n\tconst s16 *ncoeff;\n\tstruct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;\n\n\tdib8000_write_word(state, 352, state->seg_diff_mask);\n\tdib8000_write_word(state, 353, state->seg_mask);\n\n\t/* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */\n\tdib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);\n\n\tif (c->isdbt_sb_mode) {\n\t\t/* ---- SMALL ---- */\n\t\tswitch (c->transmission_mode) {\n\t\tcase TRANSMISSION_MODE_2K:\n\t\t\t\tif (c->isdbt_partial_reception == 0) { /* 1-seg */\n\t\t\t\t\tif (c->layer[0].modulation == DQPSK) /* DQPSK */\n\t\t\t\t\t\tncoeff = coeff_2k_sb_1seg_dqpsk;\n\t\t\t\t\telse /* QPSK or QAM */\n\t\t\t\t\t\tncoeff = coeff_2k_sb_1seg;\n\t\t\t\t} else { /* 3-segments */\n\t\t\t\t\tif (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */\n\t\t\t\t\t\tif (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;\n\t\t\t\t\t\telse /* QPSK or QAM on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_2k_sb_3seg_0dqpsk;\n\t\t\t\t\t} else { /* QPSK or QAM on central segment */\n\t\t\t\t\t\tif (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_2k_sb_3seg_1dqpsk;\n\t\t\t\t\t\telse /* QPSK or QAM on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_2k_sb_3seg;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\tcase TRANSMISSION_MODE_4K:\n\t\t\t\tif (c->isdbt_partial_reception == 0) { /* 1-seg */\n\t\t\t\t\tif (c->layer[0].modulation == DQPSK) /* DQPSK */\n\t\t\t\t\t\tncoeff = coeff_4k_sb_1seg_dqpsk;\n\t\t\t\t\telse /* QPSK or QAM */\n\t\t\t\t\t\tncoeff = coeff_4k_sb_1seg;\n\t\t\t\t} else { /* 3-segments */\n\t\t\t\t\tif (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */\n\t\t\t\t\t\tif (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;\n\t\t\t\t\t\telse /* QPSK or QAM on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_4k_sb_3seg_0dqpsk;\n\t\t\t\t\t} else { /* QPSK or QAM on central segment */\n\t\t\t\t\t\tif (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_4k_sb_3seg_1dqpsk;\n\t\t\t\t\t\telse /* QPSK or QAM on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_4k_sb_3seg;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\tcase TRANSMISSION_MODE_AUTO:\n\t\tcase TRANSMISSION_MODE_8K:\n\t\tdefault:\n\t\t\t\tif (c->isdbt_partial_reception == 0) { /* 1-seg */\n\t\t\t\t\tif (c->layer[0].modulation == DQPSK) /* DQPSK */\n\t\t\t\t\t\tncoeff = coeff_8k_sb_1seg_dqpsk;\n\t\t\t\t\telse /* QPSK or QAM */\n\t\t\t\t\t\tncoeff = coeff_8k_sb_1seg;\n\t\t\t\t} else { /* 3-segments */\n\t\t\t\t\tif (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */\n\t\t\t\t\t\tif (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;\n\t\t\t\t\t\telse /* QPSK or QAM on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_8k_sb_3seg_0dqpsk;\n\t\t\t\t\t} else { /* QPSK or QAM on central segment */\n\t\t\t\t\t\tif (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_8k_sb_3seg_1dqpsk;\n\t\t\t\t\t\telse /* QPSK or QAM on external segments */\n\t\t\t\t\t\t\tncoeff = coeff_8k_sb_3seg;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t}\n\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tdib8000_write_word(state, 343 + i, ncoeff[i]);\n\t}\n}",
        "static void snd_soc_tplg_test_load_empty_tplg_bad_abi(struct kunit *test)\n{\n\tstruct kunit_soc_component *kunit_comp;\n\tstruct tplg_tmpl_001 *data;\n\tint size;": "static void snd_soc_tplg_test_load_empty_tplg_bad_abi(struct kunit *test)\n{\n\tstruct kunit_soc_component *kunit_comp;\n\tstruct tplg_tmpl_001 *data;\n\tint size;\n\tint ret;\n\n\t/* prepare */\n\tkunit_comp = kunit_kzalloc(test, sizeof(*kunit_comp), GFP_KERNEL);\n\tKUNIT_EXPECT_NOT_ERR_OR_NULL(test, kunit_comp);\n\tkunit_comp->kunit = test;\n\tkunit_comp->expect = -EINVAL; /* expect failure */\n\n\tsize = sizeof(tplg_tmpl_empty);\n\tdata = kunit_kzalloc(kunit_comp->kunit, size, GFP_KERNEL);\n\tKUNIT_EXPECT_NOT_ERR_OR_NULL(kunit_comp->kunit, data);\n\n\tmemcpy(data, &tplg_tmpl_empty, sizeof(tplg_tmpl_empty));\n\t/*\n\t * override abi\n\t * any value != accepted range is wrong\n\t */\n\tdata->header.abi = cpu_to_le32(SND_SOC_TPLG_ABI_VERSION + 1);\n\n\tkunit_comp->fw.data = (u8 *)data;\n\tkunit_comp->fw.size = size;\n\n\tkunit_comp->card.dev = test_dev,\n\tkunit_comp->card.name = \"kunit-card\",\n\tkunit_comp->card.owner = THIS_MODULE,\n\tkunit_comp->card.dai_link = kunit_dai_links,\n\tkunit_comp->card.num_links = ARRAY_SIZE(kunit_dai_links),\n\tkunit_comp->card.fully_routed = true,\n\n\t/* run test */\n\tret = snd_soc_register_card(&kunit_comp->card);\n\tif (ret != 0 && ret != -EPROBE_DEFER)\n\t\tKUNIT_FAIL(test, \"Failed to register card\");\n\n\tret = snd_soc_component_initialize(&kunit_comp->comp, &test_component, test_dev);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\tret = snd_soc_add_component(&kunit_comp->comp, NULL, 0);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\t/* cleanup */\n\tret = snd_soc_unregister_card(&kunit_comp->card);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\tsnd_soc_unregister_component(test_dev);\n}",
        "static void srcu_flip(struct srcu_struct *ssp)\n{\n\t/*\n\t * Ensure that if this updater saw a given reader's increment\n\t * from __srcu_read_lock(), that reader was using an old value": "static void srcu_flip(struct srcu_struct *ssp)\n{\n\t/*\n\t * Ensure that if this updater saw a given reader's increment\n\t * from __srcu_read_lock(), that reader was using an old value\n\t * of ->srcu_idx.  Also ensure that if a given reader sees the\n\t * new value of ->srcu_idx, this updater's earlier scans cannot\n\t * have seen that reader's increments (which is OK, because this\n\t * grace period need not wait on that reader).\n\t */\n\tsmp_mb(); /* E */  /* Pairs with B and C. */\n\n\tWRITE_ONCE(ssp->srcu_idx, ssp->srcu_idx + 1);\n\n\t/*\n\t * Ensure that if the updater misses an __srcu_read_unlock()\n\t * increment, that task's next __srcu_read_lock() will see the\n\t * above counter update.  Note that both this memory barrier\n\t * and the one in srcu_readers_active_idx_check() provide the\n\t * guarantee for __srcu_read_lock().\n\t */\n\tsmp_mb(); /* D */  /* Pairs with C. */\n}",
        "static int cgx_print_dmac_flt(struct seq_file *s, int lmac_id)\n{\n\tstruct pci_dev *pdev = NULL;\n\tvoid *cgxd = s->private;\n\tchar *bcast, *mcast;": "static int cgx_print_dmac_flt(struct seq_file *s, int lmac_id)\n{\n\tstruct pci_dev *pdev = NULL;\n\tvoid *cgxd = s->private;\n\tchar *bcast, *mcast;\n\tu16 index, domain;\n\tu8 dmac[ETH_ALEN];\n\tstruct rvu *rvu;\n\tu64 cfg, mac;\n\tint pf;\n\n\trvu = pci_get_drvdata(pci_get_device(PCI_VENDOR_ID_CAVIUM,\n\t\t\t\t\t     PCI_DEVID_OCTEONTX2_RVU_AF, NULL));\n\tif (!rvu)\n\t\treturn -ENODEV;\n\n\tpf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);\n\tdomain = 2;\n\n\tpdev = pci_get_domain_bus_and_slot(domain, pf + 1, 0);\n\tif (!pdev)\n\t\treturn 0;\n\n\tcfg = cgx_read_dmac_ctrl(cgxd, lmac_id);\n\tbcast = cfg & CGX_DMAC_BCAST_MODE ? \"ACCEPT\" : \"REJECT\";\n\tmcast = cfg & CGX_DMAC_MCAST_MODE ? \"ACCEPT\" : \"REJECT\";\n\n\tseq_puts(s,\n\t\t \"PCI dev       RVUPF   BROADCAST  MULTICAST  FILTER-MODE\\n\");\n\tseq_printf(s, \"%s  PF%d  %9s  %9s\",\n\t\t   dev_name(&pdev->dev), pf, bcast, mcast);\n\tif (cfg & CGX_DMAC_CAM_ACCEPT)\n\t\tseq_printf(s, \"%12s\\n\\n\", \"UNICAST\");\n\telse\n\t\tseq_printf(s, \"%16s\\n\\n\", \"PROMISCUOUS\");\n\n\tseq_puts(s, \"\\nDMAC-INDEX  ADDRESS\\n\");\n\n\tfor (index = 0 ; index < 32 ; index++) {\n\t\tcfg = cgx_read_dmac_entry(cgxd, index);\n\t\t/* Display enabled dmac entries associated with current lmac */\n\t\tif (lmac_id == FIELD_GET(CGX_DMAC_CAM_ENTRY_LMACID, cfg) &&\n\t\t    FIELD_GET(CGX_DMAC_CAM_ADDR_ENABLE, cfg)) {\n\t\t\tmac = FIELD_GET(CGX_RX_DMAC_ADR_MASK, cfg);\n\t\t\tu64_to_ether_addr(mac, dmac);\n\t\t\tseq_printf(s, \"%7d     %pM\\n\", index, dmac);\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static void ad1986_update_jacks(struct snd_ac97 *ac97)\n{\n\tunsigned short misc_val = 0;\n\tunsigned short ser_val;\n": "static void ad1986_update_jacks(struct snd_ac97 *ac97)\n{\n\tunsigned short misc_val = 0;\n\tunsigned short ser_val;\n\n\t/* disable SURROUND and CENTER/LFE if not surround mode */\n\tif (!is_surround_on(ac97))\n\t\tmisc_val |= AC97_AD1986_SODIS;\n\tif (!is_clfe_on(ac97))\n\t\tmisc_val |= AC97_AD1986_CLDIS;\n\n\t/* select line input (default=LINE_IN, SURROUND or MIC_1/2) */\n\tif (is_shared_linein(ac97))\n\t\tmisc_val |= AC97_AD1986_LISEL_SURR;\n\telse if (ac97->spec.ad18xx.swap_mic_linein != 0)\n\t\tmisc_val |= AC97_AD1986_LISEL_MIC;\n\tsnd_ac97_update_bits(ac97, AC97_AD_MISC,\n\t\t\t     AC97_AD1986_SODIS | AC97_AD1986_CLDIS |\n\t\t\t     AC97_AD1986_LISEL_MASK,\n\t\t\t     misc_val);\n\n\t/* select microphone input (MIC_1/2, Center/LFE or LINE_IN) */\n\tif (is_shared_micin(ac97))\n\t\tser_val = AC97_AD1986_OMS_C;\n\telse if (ac97->spec.ad18xx.swap_mic_linein != 0)\n\t\tser_val = AC97_AD1986_OMS_L;\n\telse\n\t\tser_val = AC97_AD1986_OMS_M;\n\tsnd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG,\n\t\t\t     AC97_AD1986_OMS_MASK,\n\t\t\t     ser_val);\n}",
        "static int hdsp_get_iobox_version (struct hdsp *hdsp)\n{\n\tif ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {\n\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);": "static int hdsp_get_iobox_version (struct hdsp *hdsp)\n{\n\tif ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {\n\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);\n\t\thdsp_write(hdsp, HDSP_fifoData, 0);\n\n\t\tif (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {\n\t\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);\n\t\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);\n\t\t}\n\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);\n\t\thdsp_write (hdsp, HDSP_fifoData, 0);\n\t\tif (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)\n\t\t\tgoto set_multi;\n\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);\n\t\thdsp_write(hdsp, HDSP_fifoData, 0);\n\t\tif (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {\n\t\t\thdsp->io_type = Digiface;\n\t\t\tdev_info(hdsp->card->dev, \"Digiface found\\n\");\n\t\t\treturn 0;\n\t\t}\n\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);\n\t\thdsp_write(hdsp, HDSP_fifoData, 0);\n\t\tif (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)\n\t\t\tgoto set_multi;\n\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);\n\t\thdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);\n\t\thdsp_write(hdsp, HDSP_fifoData, 0);\n\t\tif (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)\n\t\t\tgoto set_multi;\n\n\t\thdsp->io_type = RPM;\n\t\tdev_info(hdsp->card->dev, \"RPM found\\n\");\n\t\treturn 0;\n\t} else {\n\t\t/* firmware was already loaded, get iobox type */\n\t\tif (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)\n\t\t\thdsp->io_type = RPM;\n\t\telse if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)\n\t\t\thdsp->io_type = Multiface;\n\t\telse\n\t\t\thdsp->io_type = Digiface;\n\t}\n\treturn 0;\n\nset_multi:\n\thdsp->io_type = Multiface;\n\tdev_info(hdsp->card->dev, \"Multiface found\\n\");\n\treturn 0;\n}",
        "static void test_tc_redirect_peer(struct netns_setup_result *setup_result)\n{\n\tstruct nstoken *nstoken;\n\tstruct test_tc_peer *skel;\n\tint err;": "static void test_tc_redirect_peer(struct netns_setup_result *setup_result)\n{\n\tstruct nstoken *nstoken;\n\tstruct test_tc_peer *skel;\n\tint err;\n\n\tnstoken = open_netns(NS_FWD);\n\tif (!ASSERT_OK_PTR(nstoken, \"setns fwd\"))\n\t\treturn;\n\n\tskel = test_tc_peer__open();\n\tif (!ASSERT_OK_PTR(skel, \"test_tc_peer__open\"))\n\t\tgoto done;\n\n\tskel->rodata->IFINDEX_SRC = setup_result->ifindex_veth_src_fwd;\n\tskel->rodata->IFINDEX_DST = setup_result->ifindex_veth_dst_fwd;\n\n\terr = test_tc_peer__load(skel);\n\tif (!ASSERT_OK(err, \"test_tc_peer__load\"))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_src, SRC_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" SRC_PROG_PIN_FILE))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_chk, CHK_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" CHK_PROG_PIN_FILE))\n\t\tgoto done;\n\n\terr = bpf_program__pin(skel->progs.tc_dst, DST_PROG_PIN_FILE);\n\tif (!ASSERT_OK(err, \"pin \" DST_PROG_PIN_FILE))\n\t\tgoto done;\n\n\tif (netns_load_bpf())\n\t\tgoto done;\n\n\tif (!ASSERT_OK(set_forwarding(false), \"disable forwarding\"))\n\t\tgoto done;\n\n\ttest_connectivity();\n\ndone:\n\tif (skel)\n\t\ttest_tc_peer__destroy(skel);\n\tclose_netns(nstoken);\n}",
        "static int mpcs_consumer_thread(void)\n{\n\tint fence, merged, tmp, valid, it, i;\n\tint *producer_timelines = test_data_mpsc.producer_timelines;\n\tint consumer_timeline = test_data_mpsc.consumer_timeline;": "static int mpcs_consumer_thread(void)\n{\n\tint fence, merged, tmp, valid, it, i;\n\tint *producer_timelines = test_data_mpsc.producer_timelines;\n\tint consumer_timeline = test_data_mpsc.consumer_timeline;\n\tint iterations = test_data_mpsc.iterations;\n\tint n = test_data_mpsc.threads;\n\n\tfor (it = 1; it <= iterations; it++) {\n\t\tfence = sw_sync_fence_create(producer_timelines[0], \"name\", it);\n\t\tfor (i = 1; i < n; i++) {\n\t\t\ttmp = sw_sync_fence_create(producer_timelines[i],\n\t\t\t\t\t\t   \"name\", it);\n\t\t\tmerged = sync_merge(\"name\", tmp, fence);\n\t\t\tsw_sync_fence_destroy(tmp);\n\t\t\tsw_sync_fence_destroy(fence);\n\t\t\tfence = merged;\n\t\t}\n\n\t\tvalid = sw_sync_fence_is_valid(fence);\n\t\tASSERT(valid, \"Failure merging fences\\n\");\n\n\t\t/*\n\t\t * Make sure we see an increment from every producer thread.\n\t\t * Vary the means by which we wait.\n\t\t */\n\t\tif (iterations % 8 != 0) {\n\t\t\tASSERT(sync_wait(fence, -1) > 0,\n\t\t\t       \"Producers did not increment as expected\\n\");\n\t\t} else {\n\t\t\tASSERT(busy_wait_on_fence(fence) == 0,\n\t\t\t       \"Producers did not increment as expected\\n\");\n\t\t}\n\n\t\tASSERT(test_data_mpsc.counter == n * it,\n\t\t       \"Counter value mismatch!\\n\");\n\n\t\t/* Release the producer threads */\n\t\tASSERT(sw_sync_timeline_inc(consumer_timeline, 1) == 0,\n\t\t       \"Failure releasing producer threads\\n\");\n\n\t\tsw_sync_fence_destroy(fence);\n\t}\n\n\treturn 0;\n}",
        "static void *do_printloop(void *arg)\n{\n\tconst size_t bufspace = PRINT_BUFFER_SIZE;\n\tchar *buffer;\n\tlong *rseed = (long *) arg;": "static void *do_printloop(void *arg)\n{\n\tconst size_t bufspace = PRINT_BUFFER_SIZE;\n\tchar *buffer;\n\tlong *rseed = (long *) arg;\n\tstruct drand48_data drandbuf;\n\tlong slept = 0;\n\tstruct entry req;\n\tint prob = 0;\n\tstruct timespec timestamp;\n\tstruct short_msg resize_msg;\n\n\tprint_priority();\n\n\tif (srand48_r(*rseed, &drandbuf) != 0) {\n\t\twarn(\"srand48_r() failed!\\n\");\n\t\tcleanup_exit(EXIT_FAILURE);\n\t}\n\n\tbuffer = malloc_or_die(bufspace);\n\n\twhile (true) {\n\t\treq = queue_wait_for_entry(&printqueue);\n\t\tclock_gettime_or_die(CLOCK_MONOTONIC, &timestamp);\n\t\tmutex_lock(&printstate.mutex);\n\t\tif (prev_req_won_race(&req)) {\n\t\t\tprintstate_mark_req_completed(&req);\n\t\t\tmutex_unlock(&printstate.mutex);\n\t\t\tif (verbose_lostevent())\n\t\t\t\tprint_lostmessage(&timestamp, buffer, bufspace,\n\t\t\t\t\t\t  &req, \"print loop\");\n\t\t\tcontinue;\n\t\t}\n\t\tmutex_unlock(&printstate.mutex);\n\n\t\t/*\n\t\t * Toss a coin to decide if we want to sleep before printing\n\t\t * out the backtrace. The reason for this is that opening\n\t\t * /sys/kernel/debug/tracing/trace will cause a blackout of\n\t\t * hundreds of ms, where no latencies will be noted by the\n\t\t * latency tracer. Thus by randomly sleeping we try to avoid\n\t\t * missing traces systematically due to this. With this option\n\t\t * we will sometimes get the first latency, some other times\n\t\t * some of the later ones, in case of closely spaced traces.\n\t\t */\n\t\tif (trace_enable && use_random_sleep) {\n\t\t\tslept = 0;\n\t\t\tprob = table_get_probability(&req, &resize_msg);\n\t\t\tif (!toss_coin(&drandbuf, prob))\n\t\t\t\tslept = go_to_sleep(&req);\n\t\t\tif (slept >= 0) {\n\t\t\t\t/* A print is ongoing */\n\t\t\t\tprintstate_cnt_inc();\n\t\t\t\t/*\n\t\t\t\t * We will do the printout below so we have to\n\t\t\t\t * mark it as completed while we still have the\n\t\t\t\t * mutex.\n\t\t\t\t */\n\t\t\t\tmutex_lock(&printstate.mutex);\n\t\t\t\tprintstate_mark_req_completed(&req);\n\t\t\t\tmutex_unlock(&printstate.mutex);\n\t\t\t}\n\t\t}\n\t\tif (trace_enable) {\n\t\t\t/*\n\t\t\t * slept < 0  means that we detected another\n\t\t\t * notification in go_to_sleep() above\n\t\t\t */\n\t\t\tif (slept >= 0)\n\t\t\t\t/*\n\t\t\t\t * N.B. printstate_cnt_dec(); will be called\n\t\t\t\t * inside print_tracefile()\n\t\t\t\t */\n\t\t\t\tprint_tracefile(&resize_msg, &timestamp, buffer,\n\t\t\t\t\t\tbufspace, slept, &req);\n\t\t\telse\n\t\t\t\tprint_skipmessage(&resize_msg, &timestamp,\n\t\t\t\t\t\t  buffer, bufspace, &req, true);\n\t\t} else {\n\t\t\tprint_skipmessage(&resize_msg, &timestamp, buffer,\n\t\t\t\t\t  bufspace, &req, false);\n\t\t}\n\t}\n\treturn NULL;\n}",
        "static inline bool boost_watermark(struct zone *zone)\n{\n\tunsigned long max_boost;\n\n\tif (!watermark_boost_factor)": "static inline bool boost_watermark(struct zone *zone)\n{\n\tunsigned long max_boost;\n\n\tif (!watermark_boost_factor)\n\t\treturn false;\n\t/*\n\t * Don't bother in zones that are unlikely to produce results.\n\t * On small machines, including kdump capture kernels running\n\t * in a small area, boosting the watermark can cause an out of\n\t * memory situation immediately.\n\t */\n\tif ((pageblock_nr_pages * 4) > zone_managed_pages(zone))\n\t\treturn false;\n\n\tmax_boost = mult_frac(zone->_watermark[WMARK_HIGH],\n\t\t\twatermark_boost_factor, 10000);\n\n\t/*\n\t * high watermark may be uninitialised if fragmentation occurs\n\t * very early in boot so do not boost. We do not fall\n\t * through and boost by pageblock_nr_pages as failing\n\t * allocations that early means that reclaim is not going\n\t * to help and it may even be impossible to reclaim the\n\t * boosted watermark resulting in a hang.\n\t */\n\tif (!max_boost)\n\t\treturn false;\n\n\tmax_boost = max(pageblock_nr_pages, max_boost);\n\n\tzone->watermark_boost = min(zone->watermark_boost + pageblock_nr_pages,\n\t\tmax_boost);\n\n\treturn true;\n}",
        "static int __init lenovo_yoga_tab2_830_1050_init_display(void)\n{\n\tstruct gpio_desc *gpiod;\n\tint ret;\n": "static int __init lenovo_yoga_tab2_830_1050_init_display(void)\n{\n\tstruct gpio_desc *gpiod;\n\tint ret;\n\n\t/* Use PMIC GPIO 10 bootstrap pin to differentiate 830 vs 1050 */\n\tret = x86_android_tablet_get_gpiod(\"gpio_crystalcove\", 10, &gpiod);\n\tif (ret)\n\t\treturn ret;\n\n\tret = gpiod_get_value_cansleep(gpiod);\n\tif (ret) {\n\t\tpr_info(\"detected Lenovo Yoga Tablet 2 1050F/L\\n\");\n\t\tlenovo_yoga_tab2_830_1050_info.i2c_client_count =\n\t\t\tARRAY_SIZE(lenovo_yoga_tab2_830_1050_i2c_clients) - 1;\n\t} else {\n\t\tpr_info(\"detected Lenovo Yoga Tablet 2 830F/L\\n\");\n\t\tlenovo_yoga_tab2_830_1050_rmi_pdata.sensor_pdata.axis_align.swap_axes = true;\n\t\tlenovo_yoga_tab2_830_1050_rmi_pdata.sensor_pdata.axis_align.flip_y = true;\n\t\tlenovo_yoga_tab2_830_1050_info.i2c_client_count =\n\t\t\tARRAY_SIZE(lenovo_yoga_tab2_830_1050_i2c_clients);\n\t}\n\n\treturn 0;\n}",
        "static void compat_exit_robust_list(struct task_struct *curr)\n{\n\tstruct compat_robust_list_head __user *head = curr->compat_robust_list;\n\tstruct robust_list __user *entry, *next_entry, *pending;\n\tunsigned int limit = ROBUST_LIST_LIMIT, pi, pip;": "static void compat_exit_robust_list(struct task_struct *curr)\n{\n\tstruct compat_robust_list_head __user *head = curr->compat_robust_list;\n\tstruct robust_list __user *entry, *next_entry, *pending;\n\tunsigned int limit = ROBUST_LIST_LIMIT, pi, pip;\n\tunsigned int next_pi;\n\tcompat_uptr_t uentry, next_uentry, upending;\n\tcompat_long_t futex_offset;\n\tint rc;\n\n\t/*\n\t * Fetch the list head (which was registered earlier, via\n\t * sys_set_robust_list()):\n\t */\n\tif (compat_fetch_robust_entry(&uentry, &entry, &head->list.next, &pi))\n\t\treturn;\n\t/*\n\t * Fetch the relative futex offset:\n\t */\n\tif (get_user(futex_offset, &head->futex_offset))\n\t\treturn;\n\t/*\n\t * Fetch any possibly pending lock-add first, and handle it\n\t * if it exists:\n\t */\n\tif (compat_fetch_robust_entry(&upending, &pending,\n\t\t\t       &head->list_op_pending, &pip))\n\t\treturn;\n\n\tnext_entry = NULL;\t/* avoid warning with gcc */\n\twhile (entry != (struct robust_list __user *) &head->list) {\n\t\t/*\n\t\t * Fetch the next entry in the list before calling\n\t\t * handle_futex_death:\n\t\t */\n\t\trc = compat_fetch_robust_entry(&next_uentry, &next_entry,\n\t\t\t(compat_uptr_t __user *)&entry->next, &next_pi);\n\t\t/*\n\t\t * A pending lock might already be on the list, so\n\t\t * dont process it twice:\n\t\t */\n\t\tif (entry != pending) {\n\t\t\tvoid __user *uaddr = futex_uaddr(entry, futex_offset);\n\n\t\t\tif (handle_futex_death(uaddr, curr, pi,\n\t\t\t\t\t       HANDLE_DEATH_LIST))\n\t\t\t\treturn;\n\t\t}\n\t\tif (rc)\n\t\t\treturn;\n\t\tuentry = next_uentry;\n\t\tentry = next_entry;\n\t\tpi = next_pi;\n\t\t/*\n\t\t * Avoid excessively long or circular lists:\n\t\t */\n\t\tif (!--limit)\n\t\t\tbreak;\n\n\t\tcond_resched();\n\t}\n\tif (pending) {\n\t\tvoid __user *uaddr = futex_uaddr(pending, futex_offset);\n\n\t\thandle_futex_death(uaddr, curr, pip, HANDLE_DEATH_PENDING);\n\t}\n}",
        "static void usage(void)\n{\n\tsize_t i, j;\n\n\tprintf(": "static void usage(void)\n{\n\tsize_t i, j;\n\n\tprintf(\n\"page-types [options]\\n\"\n\"            -r|--raw                   Raw mode, for kernel developers\\n\"\n\"            -d|--describe flags        Describe flags\\n\"\n\"            -a|--addr    addr-spec     Walk a range of pages\\n\"\n\"            -b|--bits    bits-spec     Walk pages with specified bits\\n\"\n\"            -c|--cgroup  path|@inode   Walk pages within memory cgroup\\n\"\n\"            -p|--pid     pid           Walk process address space\\n\"\n\"            -f|--file    filename      Walk file address space\\n\"\n\"            -i|--mark-idle             Mark pages idle\\n\"\n\"            -l|--list                  Show page details in ranges\\n\"\n\"            -L|--list-each             Show page details one by one\\n\"\n\"            -C|--list-cgroup           Show cgroup inode for pages\\n\"\n\"            -M|--list-mapcnt           Show page map count\\n\"\n\"            -N|--no-summary            Don't show summary info\\n\"\n\"            -X|--hwpoison              hwpoison pages\\n\"\n\"            -x|--unpoison              unpoison pages\\n\"\n\"            -F|--kpageflags filename   kpageflags file to parse\\n\"\n\"            -h|--help                  Show this usage message\\n\"\n\"flags:\\n\"\n\"            0x10                       bitfield format, e.g.\\n\"\n\"            anon                       bit-name, e.g.\\n\"\n\"            0x10,anon                  comma-separated list, e.g.\\n\"\n\"addr-spec:\\n\"\n\"            N                          one page at offset N (unit: pages)\\n\"\n\"            N+M                        pages range from N to N+M-1\\n\"\n\"            N,M                        pages range from N to M-1\\n\"\n\"            N,                         pages range from N to end\\n\"\n\"            ,M                         pages range from 0 to M-1\\n\"\n\"bits-spec:\\n\"\n\"            bit1,bit2                  (flags & (bit1|bit2)) != 0\\n\"\n\"            bit1,bit2=bit1             (flags & (bit1|bit2)) == bit1\\n\"\n\"            bit1,~bit2                 (flags & (bit1|bit2)) == bit1\\n\"\n\"            =bit1,bit2                 flags == (bit1|bit2)\\n\"\n\"bit-names:\\n\"\n\t);\n\n\tfor (i = 0, j = 0; i < ARRAY_SIZE(page_flag_names); i++) {\n\t\tif (!page_flag_names[i])\n\t\t\tcontinue;\n\t\tprintf(\"%16s%s\", page_flag_names[i] + 2,\n\t\t\t\t page_flag_type(1ULL << i));\n\t\tif (++j > 3) {\n\t\t\tj = 0;\n\t\t\tputchar('\\n');\n\t\t}\n\t}\n\tprintf(\"\\n                                   \"\n\t\t\"(r) raw mode bits  (o) overloaded bits\\n\");\n}",
        "static int rx_enable(struct slgt_info *info, int enable)\n{\n \tunsigned long flags;\n\tunsigned int rbuf_fill_level;\n\tDBGINFO((\"%s rx_enable(%08x)\\n\", info->device_name, enable));": "static int rx_enable(struct slgt_info *info, int enable)\n{\n \tunsigned long flags;\n\tunsigned int rbuf_fill_level;\n\tDBGINFO((\"%s rx_enable(%08x)\\n\", info->device_name, enable));\n\tspin_lock_irqsave(&info->lock,flags);\n\t/*\n\t * enable[31..16] = receive DMA buffer fill level\n\t * 0 = noop (leave fill level unchanged)\n\t * fill level must be multiple of 4 and <= buffer size\n\t */\n\trbuf_fill_level = ((unsigned int)enable) >> 16;\n\tif (rbuf_fill_level) {\n\t\tif ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {\n\t\t\tspin_unlock_irqrestore(&info->lock, flags);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tinfo->rbuf_fill_level = rbuf_fill_level;\n\t\tif (rbuf_fill_level < 128)\n\t\t\tinfo->rx_pio = 1; /* PIO mode */\n\t\telse\n\t\t\tinfo->rx_pio = 0; /* DMA mode */\n\t\trx_stop(info); /* restart receiver to use new fill level */\n\t}\n\n\t/*\n\t * enable[1..0] = receiver enable command\n\t * 0 = disable\n\t * 1 = enable\n\t * 2 = enable or force hunt mode if already enabled\n\t */\n\tenable &= 3;\n\tif (enable) {\n\t\tif (!info->rx_enabled)\n\t\t\trx_start(info);\n\t\telse if (enable == 2) {\n\t\t\t/* force hunt mode (write 1 to RCR[3]) */\n\t\t\twr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);\n\t\t}\n\t} else {\n\t\tif (info->rx_enabled)\n\t\t\trx_stop(info);\n\t}\n\tspin_unlock_irqrestore(&info->lock,flags);\n\treturn 0;\n}",
        "static int pmc_usb_send_command(struct intel_scu_ipc_dev *ipc, u8 *msg, u32 len)\n{\n\tu8 response[4];\n\tu8 status_res;\n\tint ret;": "static int pmc_usb_send_command(struct intel_scu_ipc_dev *ipc, u8 *msg, u32 len)\n{\n\tu8 response[4];\n\tu8 status_res;\n\tint ret;\n\n\t/*\n\t * Error bit will always be 0 with the USBC command.\n\t * Status can be checked from the response message if the\n\t * function intel_scu_ipc_dev_command succeeds.\n\t */\n\tret = intel_scu_ipc_dev_command(ipc, PMC_USBC_CMD, 0, msg,\n\t\t\t\t\tlen, response, sizeof(response));\n\n\tif (ret)\n\t\treturn ret;\n\n\tstatus_res = (msg[0] & 0xf) < PMC_USB_SAFE_MODE ?\n\t\t     response[2] : response[1];\n\n\tif (status_res & PMC_USB_RESP_STATUS_FAILURE) {\n\t\tif (status_res & PMC_USB_RESP_STATUS_FATAL)\n\t\t\treturn -EIO;\n\n\t\treturn -EBUSY;\n\t}\n\n\treturn 0;\n}",
        "static int alloc_from_top_down_min_addr_cap_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n": "static int alloc_from_top_down_min_addr_cap_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\n\tphys_addr_t r1_size = SZ_64;\n\tphys_addr_t min_addr;\n\tphys_addr_t start_addr;\n\n\tsetup_memblock();\n\n\tstart_addr = (phys_addr_t)memblock_start_of_DRAM();\n\tmin_addr = start_addr - SMP_CACHE_BYTES * 3;\n\n\tmemblock_reserve(start_addr + r1_size, MEM_SIZE - r1_size);\n\n\tallocated_ptr = memblock_alloc_from(r1_size, SMP_CACHE_BYTES, min_addr);\n\n\tassert(allocated_ptr);\n\tassert(rgn->base == start_addr);\n\tassert(rgn->size == MEM_SIZE);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == MEM_SIZE);\n\n\treturn 0;\n}",
        "static void perf_iterate_sb_cpu(perf_iterate_f output, void *data)\n{\n\tstruct pmu_event_list *pel = this_cpu_ptr(&pmu_sb_events);\n\tstruct perf_event *event;\n": "static void perf_iterate_sb_cpu(perf_iterate_f output, void *data)\n{\n\tstruct pmu_event_list *pel = this_cpu_ptr(&pmu_sb_events);\n\tstruct perf_event *event;\n\n\tlist_for_each_entry_rcu(event, &pel->list, sb_list) {\n\t\t/*\n\t\t * Skip events that are not fully formed yet; ensure that\n\t\t * if we observe event->ctx, both event and ctx will be\n\t\t * complete enough. See perf_install_in_context().\n\t\t */\n\t\tif (!smp_load_acquire(&event->ctx))\n\t\t\tcontinue;\n\n\t\tif (event->state < PERF_EVENT_STATE_INACTIVE)\n\t\t\tcontinue;\n\t\tif (!event_filter_match(event))\n\t\t\tcontinue;\n\t\toutput(event, data);\n\t}\n}",
        "static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)\n{\n\tu8 adr = state->demod_address, mm[6], len;\n\n\tif (state->single_master)": "static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)\n{\n\tu8 adr = state->demod_address, mm[6], len;\n\n\tif (state->single_master)\n\t\tflags |= 0xC0;\n\tif (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {\n\t\tmm[0] = (((reg << 1) & 0xFF) | 0x01);\n\t\tmm[1] = ((reg >> 16) & 0xFF);\n\t\tmm[2] = ((reg >> 24) & 0xFF) | flags;\n\t\tmm[3] = ((reg >> 7) & 0xFF);\n\t\tlen = 4;\n\t} else {\n\t\tmm[0] = ((reg << 1) & 0xFF);\n\t\tmm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));\n\t\tlen = 2;\n\t}\n\tmm[len] = data & 0xff;\n\tmm[len + 1] = (data >> 8) & 0xff;\n\n\tdprintk(2, \"(0x%08x, 0x%04x, 0x%02x)\\n\", reg, data, flags);\n\treturn i2c_write(state, adr, mm, len + 2);\n}",
        "static int t7xx_dpmaif_start(struct dpmaif_ctrl *dpmaif_ctrl)\n{\n\tstruct dpmaif_hw_info *hw_info = &dpmaif_ctrl->hw_info;\n\tstruct dpmaif_hw_params hw_init_para;\n\tstruct dpmaif_rx_queue *rxq;": "static int t7xx_dpmaif_start(struct dpmaif_ctrl *dpmaif_ctrl)\n{\n\tstruct dpmaif_hw_info *hw_info = &dpmaif_ctrl->hw_info;\n\tstruct dpmaif_hw_params hw_init_para;\n\tstruct dpmaif_rx_queue *rxq;\n\tstruct dpmaif_tx_queue *txq;\n\tunsigned int buf_cnt;\n\tint i, ret = 0;\n\n\tif (dpmaif_ctrl->state == DPMAIF_STATE_PWRON)\n\t\treturn -EFAULT;\n\n\tmemset(&hw_init_para, 0, sizeof(hw_init_para));\n\n\tfor (i = 0; i < DPMAIF_RXQ_NUM; i++) {\n\t\trxq = &dpmaif_ctrl->rxq[i];\n\t\trxq->que_started = true;\n\t\trxq->index = i;\n\t\trxq->budget = rxq->bat_req->bat_size_cnt - 1;\n\n\t\thw_init_para.pkt_bat_base_addr[i] = rxq->bat_req->bat_bus_addr;\n\t\thw_init_para.pkt_bat_size_cnt[i] = rxq->bat_req->bat_size_cnt;\n\t\thw_init_para.pit_base_addr[i] = rxq->pit_bus_addr;\n\t\thw_init_para.pit_size_cnt[i] = rxq->pit_size_cnt;\n\t\thw_init_para.frg_bat_base_addr[i] = rxq->bat_frag->bat_bus_addr;\n\t\thw_init_para.frg_bat_size_cnt[i] = rxq->bat_frag->bat_size_cnt;\n\t}\n\n\tbitmap_zero(dpmaif_ctrl->bat_req.bat_bitmap, dpmaif_ctrl->bat_req.bat_size_cnt);\n\tbuf_cnt = dpmaif_ctrl->bat_req.bat_size_cnt - 1;\n\tret = t7xx_dpmaif_rx_buf_alloc(dpmaif_ctrl, &dpmaif_ctrl->bat_req, 0, buf_cnt, true);\n\tif (ret) {\n\t\tdev_err(dpmaif_ctrl->dev, \"Failed to allocate RX buffer: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tbuf_cnt = dpmaif_ctrl->bat_frag.bat_size_cnt - 1;\n\tret = t7xx_dpmaif_rx_frag_alloc(dpmaif_ctrl, &dpmaif_ctrl->bat_frag, buf_cnt, true);\n\tif (ret) {\n\t\tdev_err(dpmaif_ctrl->dev, \"Failed to allocate frag RX buffer: %d\\n\", ret);\n\t\tgoto err_free_normal_bat;\n\t}\n\n\tfor (i = 0; i < DPMAIF_TXQ_NUM; i++) {\n\t\ttxq = &dpmaif_ctrl->txq[i];\n\t\ttxq->que_started = true;\n\n\t\thw_init_para.drb_base_addr[i] = txq->drb_bus_addr;\n\t\thw_init_para.drb_size_cnt[i] = txq->drb_size_cnt;\n\t}\n\n\tret = t7xx_dpmaif_hw_init(hw_info, &hw_init_para);\n\tif (ret) {\n\t\tdev_err(dpmaif_ctrl->dev, \"Failed to initialize DPMAIF HW: %d\\n\", ret);\n\t\tgoto err_free_frag_bat;\n\t}\n\n\tret = t7xx_dpmaif_dl_snd_hw_bat_cnt(hw_info, rxq->bat_req->bat_size_cnt - 1);\n\tif (ret)\n\t\tgoto err_free_frag_bat;\n\n\tret = t7xx_dpmaif_dl_snd_hw_frg_cnt(hw_info, rxq->bat_frag->bat_size_cnt - 1);\n\tif (ret)\n\t\tgoto err_free_frag_bat;\n\n\tt7xx_dpmaif_ul_clr_all_intr(hw_info);\n\tt7xx_dpmaif_dl_clr_all_intr(hw_info);\n\tdpmaif_ctrl->state = DPMAIF_STATE_PWRON;\n\tt7xx_dpmaif_enable_irq(dpmaif_ctrl);\n\twake_up(&dpmaif_ctrl->tx_wq);\n\treturn 0;\n\nerr_free_frag_bat:\n\tt7xx_dpmaif_bat_free(rxq->dpmaif_ctrl, rxq->bat_frag);\n\nerr_free_normal_bat:\n\tt7xx_dpmaif_bat_free(rxq->dpmaif_ctrl, rxq->bat_req);\n\n\treturn ret;\n}",
        "static int arm_cmn_event_add(struct perf_event *event, int flags)\n{\n\tstruct arm_cmn *cmn = to_cmn(event->pmu);\n\tstruct arm_cmn_hw_event *hw = to_cmn_hw(event);\n\tstruct arm_cmn_dtc *dtc = &cmn->dtc[0];": "static int arm_cmn_event_add(struct perf_event *event, int flags)\n{\n\tstruct arm_cmn *cmn = to_cmn(event->pmu);\n\tstruct arm_cmn_hw_event *hw = to_cmn_hw(event);\n\tstruct arm_cmn_dtc *dtc = &cmn->dtc[0];\n\tstruct arm_cmn_node *dn;\n\tenum cmn_node_type type = CMN_EVENT_TYPE(event);\n\tunsigned int i, dtc_idx, input_sel;\n\n\tif (type == CMN_TYPE_DTC) {\n\t\ti = 0;\n\t\twhile (cmn->dtc[i].cycles)\n\t\t\tif (++i == cmn->num_dtcs)\n\t\t\t\treturn -ENOSPC;\n\n\t\tcmn->dtc[i].cycles = event;\n\t\thw->dtc_idx = CMN_DT_NUM_COUNTERS;\n\t\thw->dtcs_used = 1U << i;\n\n\t\tif (flags & PERF_EF_START)\n\t\t\tarm_cmn_event_start(event, 0);\n\t\treturn 0;\n\t}\n\n\t/* Grab a free global counter first... */\n\tdtc_idx = 0;\n\twhile (dtc->counters[dtc_idx])\n\t\tif (++dtc_idx == CMN_DT_NUM_COUNTERS)\n\t\t\treturn -ENOSPC;\n\n\thw->dtc_idx = dtc_idx;\n\n\t/* ...then the local counters to feed it. */\n\tfor_each_hw_dn(hw, dn, i) {\n\t\tstruct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;\n\t\tunsigned int dtm_idx, shift;\n\t\tu64 reg;\n\n\t\tdtm_idx = 0;\n\t\twhile (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))\n\t\t\tif (++dtm_idx == CMN_DTM_NUM_COUNTERS)\n\t\t\t\tgoto free_dtms;\n\n\t\tif (type == CMN_TYPE_XP) {\n\t\t\tinput_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;\n\t\t} else if (type == CMN_TYPE_WP) {\n\t\t\tint tmp, wp_idx = arm_cmn_wp_idx(event);\n\t\t\tu32 cfg = arm_cmn_wp_config(event);\n\n\t\t\tif (dtm->wp_event[wp_idx] >= 0)\n\t\t\t\tgoto free_dtms;\n\n\t\t\ttmp = dtm->wp_event[wp_idx ^ 1];\n\t\t\tif (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=\n\t\t\t\t\tCMN_EVENT_WP_COMBINE(dtc->counters[tmp]))\n\t\t\t\tgoto free_dtms;\n\n\t\t\tinput_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;\n\t\t\tdtm->wp_event[wp_idx] = dtc_idx;\n\t\t\twritel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));\n\t\t} else {\n\t\t\tstruct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);\n\n\t\t\tif (cmn->multi_dtm)\n\t\t\t\tnid.port %= 2;\n\n\t\t\tinput_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +\n\t\t\t\t    (nid.port << 4) + (nid.dev << 2);\n\n\t\t\tif (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))\n\t\t\t\tgoto free_dtms;\n\t\t}\n\n\t\tarm_cmn_set_index(hw->dtm_idx, i, dtm_idx);\n\n\t\tdtm->input_sel[dtm_idx] = input_sel;\n\t\tshift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);\n\t\tdtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);\n\t\tdtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;\n\t\tdtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);\n\t\treg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;\n\t\twriteq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);\n\t}\n\n\t/* Go go go! */\n\tarm_cmn_init_counter(event);\n\n\tif (flags & PERF_EF_START)\n\t\tarm_cmn_event_start(event, 0);\n\n\treturn 0;\n\nfree_dtms:\n\tarm_cmn_event_clear(cmn, event, i);\n\treturn -ENOSPC;\n}",
        "static void sky2_rx_start(struct sky2_port *sky2)\n{\n\tstruct sky2_hw *hw = sky2->hw;\n\tstruct rx_ring_info *re;\n\tunsigned rxq = rxqaddr[sky2->port];": "static void sky2_rx_start(struct sky2_port *sky2)\n{\n\tstruct sky2_hw *hw = sky2->hw;\n\tstruct rx_ring_info *re;\n\tunsigned rxq = rxqaddr[sky2->port];\n\tunsigned i, thresh;\n\n\tsky2->rx_put = sky2->rx_next = 0;\n\tsky2_qset(hw, rxq);\n\n\t/* On PCI express lowering the watermark gives better performance */\n\tif (pci_is_pcie(hw->pdev))\n\t\tsky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);\n\n\t/* These chips have no ram buffer?\n\t * MAC Rx RAM Read is controlled by hardware\n\t */\n\tif (hw->chip_id == CHIP_ID_YUKON_EC_U &&\n\t    hw->chip_rev > CHIP_REV_YU_EC_U_A0)\n\t\tsky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);\n\n\tsky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);\n\n\tif (!(hw->flags & SKY2_HW_NEW_LE))\n\t\trx_set_checksum(sky2);\n\n\tif (!(hw->flags & SKY2_HW_RSS_BROKEN))\n\t\trx_set_rss(sky2->netdev, sky2->netdev->features);\n\n\t/* submit Rx ring */\n\tfor (i = 0; i < sky2->rx_pending; i++) {\n\t\tre = sky2->rx_ring + i;\n\t\tsky2_rx_submit(sky2, re);\n\t}\n\n\t/*\n\t * The receiver hangs if it receives frames larger than the\n\t * packet buffer. As a workaround, truncate oversize frames, but\n\t * the register is limited to 9 bits, so if you do frames > 2052\n\t * you better get the MTU right!\n\t */\n\tthresh = sky2_get_rx_threshold(sky2);\n\tif (thresh > 0x1ff)\n\t\tsky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);\n\telse {\n\t\tsky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);\n\t\tsky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);\n\t}\n\n\t/* Tell chip about available buffers */\n\tsky2_rx_update(sky2, rxq);\n\n\tif (hw->chip_id == CHIP_ID_YUKON_EX ||\n\t    hw->chip_id == CHIP_ID_YUKON_SUPR) {\n\t\t/*\n\t\t * Disable flushing of non ASF packets;\n\t\t * must be done after initializing the BMUs;\n\t\t * drivers without ASF support should do this too, otherwise\n\t\t * it may happen that they cannot run on ASF devices;\n\t\t * remember that the MAC FIFO isn't reset during initialization.\n\t\t */\n\t\tsky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);\n\t}\n\n\tif (hw->chip_id >= CHIP_ID_YUKON_SUPR) {\n\t\t/* Enable RX Home Address & Routing Header checksum fix */\n\t\tsky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),\n\t\t\t     RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);\n\n\t\t/* Enable TX Home Address & Routing Header checksum fix */\n\t\tsky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),\n\t\t\t     TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);\n\t}\n}",
        "static void test_memcache_alloc_bulk(struct kunit *test)\n{\n\tconst size_t size = 32;\n\tbool pass = false;\n\tunsigned long timeout;": "static void test_memcache_alloc_bulk(struct kunit *test)\n{\n\tconst size_t size = 32;\n\tbool pass = false;\n\tunsigned long timeout;\n\n\tsetup_test_cache(test, size, 0, NULL);\n\tKUNIT_EXPECT_TRUE(test, test_cache); /* Want memcache. */\n\t/*\n\t * 100x the sample interval should be more than enough to ensure we get\n\t * a KFENCE allocation eventually.\n\t */\n\ttimeout = jiffies + msecs_to_jiffies(100 * kfence_sample_interval);\n\tdo {\n\t\tvoid *objects[100];\n\t\tint i, num = kmem_cache_alloc_bulk(test_cache, GFP_ATOMIC, ARRAY_SIZE(objects),\n\t\t\t\t\t\t   objects);\n\t\tif (!num)\n\t\t\tcontinue;\n\t\tfor (i = 0; i < ARRAY_SIZE(objects); i++) {\n\t\t\tif (is_kfence_address(objects[i])) {\n\t\t\t\tpass = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tkmem_cache_free_bulk(test_cache, num, objects);\n\t\t/*\n\t\t * kmem_cache_alloc_bulk() disables interrupts, and calling it\n\t\t * in a tight loop may not give KFENCE a chance to switch the\n\t\t * static branch. Call cond_resched() to let KFENCE chime in.\n\t\t */\n\t\tcond_resched();\n\t} while (!pass && time_before(jiffies, timeout));\n\n\tKUNIT_EXPECT_TRUE(test, pass);\n\tKUNIT_EXPECT_FALSE(test, report_available());\n}",
        "static void cas_init_rx_dma(struct cas *cp)\n{\n\tu64 desc_dma = cp->block_dvma;\n\tu32 val;\n\tint i, size;": "static void cas_init_rx_dma(struct cas *cp)\n{\n\tu64 desc_dma = cp->block_dvma;\n\tu32 val;\n\tint i, size;\n\n\t/* rx free descriptors */\n\tval = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);\n\tval |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));\n\tval |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));\n\tif ((N_RX_DESC_RINGS > 1) &&\n\t    (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */\n\t\tval |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));\n\twritel(val, cp->regs + REG_RX_CFG);\n\n\tval = (unsigned long) cp->init_rxds[0] -\n\t\t(unsigned long) cp->init_block;\n\twritel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);\n\twritel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);\n\twritel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);\n\n\tif (cp->cas_flags & CAS_FLAG_REG_PLUS) {\n\t\t/* rx desc 2 is for IPSEC packets. however,\n\t\t * we don't it that for that purpose.\n\t\t */\n\t\tval = (unsigned long) cp->init_rxds[1] -\n\t\t\t(unsigned long) cp->init_block;\n\t\twritel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);\n\t\twritel((desc_dma + val) & 0xffffffff, cp->regs +\n\t\t       REG_PLUS_RX_DB1_LOW);\n\t\twritel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +\n\t\t       REG_PLUS_RX_KICK1);\n\t}\n\n\t/* rx completion registers */\n\tval = (unsigned long) cp->init_rxcs[0] -\n\t\t(unsigned long) cp->init_block;\n\twritel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);\n\twritel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);\n\n\tif (cp->cas_flags & CAS_FLAG_REG_PLUS) {\n\t\t/* rx comp 2-4 */\n\t\tfor (i = 1; i < MAX_RX_COMP_RINGS; i++) {\n\t\t\tval = (unsigned long) cp->init_rxcs[i] -\n\t\t\t\t(unsigned long) cp->init_block;\n\t\t\twritel((desc_dma + val) >> 32, cp->regs +\n\t\t\t       REG_PLUS_RX_CBN_HI(i));\n\t\t\twritel((desc_dma + val) & 0xffffffff, cp->regs +\n\t\t\t       REG_PLUS_RX_CBN_LOW(i));\n\t\t}\n\t}\n\n\t/* read selective clear regs to prevent spurious interrupts\n\t * on reset because complete == kick.\n\t * selective clear set up to prevent interrupts on resets\n\t */\n\treadl(cp->regs + REG_INTR_STATUS_ALIAS);\n\twritel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);\n\n\t/* set up pause thresholds */\n\tval  = CAS_BASE(RX_PAUSE_THRESH_OFF,\n\t\t\tcp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);\n\tval |= CAS_BASE(RX_PAUSE_THRESH_ON,\n\t\t\tcp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);\n\twritel(val, cp->regs + REG_RX_PAUSE_THRESH);\n\n\t/* zero out dma reassembly buffers */\n\tfor (i = 0; i < 64; i++) {\n\t\twritel(i, cp->regs + REG_RX_TABLE_ADDR);\n\t\twritel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);\n\t\twritel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);\n\t\twritel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);\n\t}\n\n\t/* make sure address register is 0 for normal operation */\n\twritel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);\n\twritel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);\n\n\t/* interrupt mitigation */\n#ifdef USE_RX_BLANK\n\tval = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);\n\tval |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);\n\twritel(val, cp->regs + REG_RX_BLANK);\n#else\n\twritel(0x0, cp->regs + REG_RX_BLANK);\n#endif\n\n\t/* interrupt generation as a function of low water marks for\n\t * free desc and completion entries. these are used to trigger\n\t * housekeeping for rx descs. we don't use the free interrupt\n\t * as it's not very useful\n\t */\n\t/* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */\n\tval = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);\n\twritel(val, cp->regs + REG_RX_AE_THRESH);\n\tif (cp->cas_flags & CAS_FLAG_REG_PLUS) {\n\t\tval = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));\n\t\twritel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);\n\t}\n\n\t/* Random early detect registers. useful for congestion avoidance.\n\t * this should be tunable.\n\t */\n\twritel(0x0, cp->regs + REG_RX_RED);\n\n\t/* receive page sizes. default == 2K (0x800) */\n\tval = 0;\n\tif (cp->page_size == 0x1000)\n\t\tval = 0x1;\n\telse if (cp->page_size == 0x2000)\n\t\tval = 0x2;\n\telse if (cp->page_size == 0x4000)\n\t\tval = 0x3;\n\n\t/* round mtu + offset. constrain to page size. */\n\tsize = cp->dev->mtu + 64;\n\tif (size > cp->page_size)\n\t\tsize = cp->page_size;\n\n\tif (size <= 0x400)\n\t\ti = 0x0;\n\telse if (size <= 0x800)\n\t\ti = 0x1;\n\telse if (size <= 0x1000)\n\t\ti = 0x2;\n\telse\n\t\ti = 0x3;\n\n\tcp->mtu_stride = 1 << (i + 10);\n\tval  = CAS_BASE(RX_PAGE_SIZE, val);\n\tval |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);\n\tval |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));\n\tval |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);\n\twritel(val, cp->regs + REG_RX_PAGE_SIZE);\n\n\t/* enable the header parser if desired */\n\tif (&CAS_HP_FIRMWARE[0] == &cas_prog_null[0])\n\t\treturn;\n\n\tval = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);\n\tval |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;\n\tval |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);\n\twritel(val, cp->regs + REG_HP_CFG);\n}",
        "static int find_energy_efficient_cpu(struct task_struct *p, int prev_cpu)\n{\n\tunsigned long prev_delta = ULONG_MAX, best_delta = ULONG_MAX;\n\tstruct root_domain *rd = cpu_rq(smp_processor_id())->rd;\n\tint cpu, best_energy_cpu = prev_cpu, target = -1;": "static int find_energy_efficient_cpu(struct task_struct *p, int prev_cpu)\n{\n\tunsigned long prev_delta = ULONG_MAX, best_delta = ULONG_MAX;\n\tstruct root_domain *rd = cpu_rq(smp_processor_id())->rd;\n\tint cpu, best_energy_cpu = prev_cpu, target = -1;\n\tunsigned long cpu_cap, util, base_energy = 0;\n\tstruct sched_domain *sd;\n\tstruct perf_domain *pd;\n\n\trcu_read_lock();\n\tpd = rcu_dereference(rd->pd);\n\tif (!pd || READ_ONCE(rd->overutilized))\n\t\tgoto unlock;\n\n\t/*\n\t * Energy-aware wake-up happens on the lowest sched_domain starting\n\t * from sd_asym_cpucapacity spanning over this_cpu and prev_cpu.\n\t */\n\tsd = rcu_dereference(*this_cpu_ptr(&sd_asym_cpucapacity));\n\twhile (sd && !cpumask_test_cpu(prev_cpu, sched_domain_span(sd)))\n\t\tsd = sd->parent;\n\tif (!sd)\n\t\tgoto unlock;\n\n\ttarget = prev_cpu;\n\n\tsync_entity_load_avg(&p->se);\n\tif (!task_util_est(p))\n\t\tgoto unlock;\n\n\tfor (; pd; pd = pd->next) {\n\t\tunsigned long cur_delta, spare_cap, max_spare_cap = 0;\n\t\tbool compute_prev_delta = false;\n\t\tunsigned long base_energy_pd;\n\t\tint max_spare_cap_cpu = -1;\n\n\t\tfor_each_cpu_and(cpu, perf_domain_span(pd), sched_domain_span(sd)) {\n\t\t\tif (!cpumask_test_cpu(cpu, p->cpus_ptr))\n\t\t\t\tcontinue;\n\n\t\t\tutil = cpu_util_next(cpu, p, cpu);\n\t\t\tcpu_cap = capacity_of(cpu);\n\t\t\tspare_cap = cpu_cap;\n\t\t\tlsub_positive(&spare_cap, util);\n\n\t\t\t/*\n\t\t\t * Skip CPUs that cannot satisfy the capacity request.\n\t\t\t * IOW, placing the task there would make the CPU\n\t\t\t * overutilized. Take uclamp into account to see how\n\t\t\t * much capacity we can get out of the CPU; this is\n\t\t\t * aligned with sched_cpu_util().\n\t\t\t */\n\t\t\tutil = uclamp_rq_util_with(cpu_rq(cpu), util, p);\n\t\t\tif (!fits_capacity(util, cpu_cap))\n\t\t\t\tcontinue;\n\n\t\t\tif (cpu == prev_cpu) {\n\t\t\t\t/* Always use prev_cpu as a candidate. */\n\t\t\t\tcompute_prev_delta = true;\n\t\t\t} else if (spare_cap > max_spare_cap) {\n\t\t\t\t/*\n\t\t\t\t * Find the CPU with the maximum spare capacity\n\t\t\t\t * in the performance domain.\n\t\t\t\t */\n\t\t\t\tmax_spare_cap = spare_cap;\n\t\t\t\tmax_spare_cap_cpu = cpu;\n\t\t\t}\n\t\t}\n\n\t\tif (max_spare_cap_cpu < 0 && !compute_prev_delta)\n\t\t\tcontinue;\n\n\t\t/* Compute the 'base' energy of the pd, without @p */\n\t\tbase_energy_pd = compute_energy(p, -1, pd);\n\t\tbase_energy += base_energy_pd;\n\n\t\t/* Evaluate the energy impact of using prev_cpu. */\n\t\tif (compute_prev_delta) {\n\t\t\tprev_delta = compute_energy(p, prev_cpu, pd);\n\t\t\tif (prev_delta < base_energy_pd)\n\t\t\t\tgoto unlock;\n\t\t\tprev_delta -= base_energy_pd;\n\t\t\tbest_delta = min(best_delta, prev_delta);\n\t\t}\n\n\t\t/* Evaluate the energy impact of using max_spare_cap_cpu. */\n\t\tif (max_spare_cap_cpu >= 0) {\n\t\t\tcur_delta = compute_energy(p, max_spare_cap_cpu, pd);\n\t\t\tif (cur_delta < base_energy_pd)\n\t\t\t\tgoto unlock;\n\t\t\tcur_delta -= base_energy_pd;\n\t\t\tif (cur_delta < best_delta) {\n\t\t\t\tbest_delta = cur_delta;\n\t\t\t\tbest_energy_cpu = max_spare_cap_cpu;\n\t\t\t}\n\t\t}\n\t}\n\trcu_read_unlock();\n\n\t/*\n\t * Pick the best CPU if prev_cpu cannot be used, or if it saves at\n\t * least 6% of the energy used by prev_cpu.\n\t */\n\tif ((prev_delta == ULONG_MAX) ||\n\t    (prev_delta - best_delta) > ((prev_delta + base_energy) >> 4))\n\t\ttarget = best_energy_cpu;\n\n\treturn target;\n\nunlock:\n\trcu_read_unlock();\n\n\treturn target;\n}",
        "static void output_headers(struct perf_session *session, struct convert_json *c)\n{\n\tstruct stat st;\n\tstruct perf_header *header = &session->header;\n\tint ret;": "static void output_headers(struct perf_session *session, struct convert_json *c)\n{\n\tstruct stat st;\n\tstruct perf_header *header = &session->header;\n\tint ret;\n\tint fd = perf_data__fd(session->data);\n\tint i;\n\tFILE *out = c->out;\n\n\toutput_json_key_format(out, false, 2, \"header-version\", \"%u\", header->version);\n\n\tret = fstat(fd, &st);\n\tif (ret >= 0) {\n\t\ttime_t stctime = st.st_mtime;\n\t\tchar buf[256];\n\n\t\tstrftime(buf, sizeof(buf), \"%FT%TZ\", gmtime(&stctime));\n\t\toutput_json_key_string(out, true, 2, \"captured-on\", buf);\n\t} else {\n\t\tpr_debug(\"Failed to get mtime of source file, not writing captured-on\");\n\t}\n\n\toutput_json_key_format(out, true, 2, \"data-offset\", \"%\" PRIu64, header->data_offset);\n\toutput_json_key_format(out, true, 2, \"data-size\", \"%\" PRIu64, header->data_size);\n\toutput_json_key_format(out, true, 2, \"feat-offset\", \"%\" PRIu64, header->feat_offset);\n\n\toutput_json_key_string(out, true, 2, \"hostname\", header->env.hostname);\n\toutput_json_key_string(out, true, 2, \"os-release\", header->env.os_release);\n\toutput_json_key_string(out, true, 2, \"arch\", header->env.arch);\n\n\toutput_json_key_string(out, true, 2, \"cpu-desc\", header->env.cpu_desc);\n\toutput_json_key_string(out, true, 2, \"cpuid\", header->env.cpuid);\n\toutput_json_key_format(out, true, 2, \"nrcpus-online\", \"%u\", header->env.nr_cpus_online);\n\toutput_json_key_format(out, true, 2, \"nrcpus-avail\", \"%u\", header->env.nr_cpus_avail);\n\n\tif (header->env.clock.enabled) {\n\t\toutput_json_key_format(out, true, 2, \"clockid\",\n\t\t\t\t\"%u\", header->env.clock.clockid);\n\t\toutput_json_key_format(out, true, 2, \"clock-time\",\n\t\t\t\t\"%\" PRIu64, header->env.clock.clockid_ns);\n\t\toutput_json_key_format(out, true, 2, \"real-time\",\n\t\t\t\t\"%\" PRIu64, header->env.clock.tod_ns);\n\t}\n\n\toutput_json_key_string(out, true, 2, \"perf-version\", header->env.version);\n\n\toutput_json_key_format(out, true, 2, \"cmdline\", \"[\");\n\tfor (i = 0; i < header->env.nr_cmdline; i++) {\n\t\toutput_json_delimiters(out, i != 0, 3);\n\t\toutput_json_string(c->out, header->env.cmdline_argv[i]);\n\t}\n\toutput_json_format(out, false, 2, \"]\");\n}",
        "static int compat_do_replace(struct net *net, sockptr_t arg, unsigned int len)\n{\n\tint ret, i, countersize, size64;\n\tstruct ebt_table_info *newinfo;\n\tstruct ebt_replace tmp;": "static int compat_do_replace(struct net *net, sockptr_t arg, unsigned int len)\n{\n\tint ret, i, countersize, size64;\n\tstruct ebt_table_info *newinfo;\n\tstruct ebt_replace tmp;\n\tstruct ebt_entries_buf_state state;\n\tvoid *entries_tmp;\n\n\tret = compat_copy_ebt_replace_from_user(&tmp, arg, len);\n\tif (ret) {\n\t\t/* try real handler in case userland supplied needed padding */\n\t\tif (ret == -EINVAL && do_replace(net, arg, len) == 0)\n\t\t\tret = 0;\n\t\treturn ret;\n\t}\n\n\tcountersize = COUNTER_OFFSET(tmp.nentries) * nr_cpu_ids;\n\tnewinfo = vmalloc(sizeof(*newinfo) + countersize);\n\tif (!newinfo)\n\t\treturn -ENOMEM;\n\n\tif (countersize)\n\t\tmemset(newinfo->counters, 0, countersize);\n\n\tmemset(&state, 0, sizeof(state));\n\n\tnewinfo->entries = vmalloc(tmp.entries_size);\n\tif (!newinfo->entries) {\n\t\tret = -ENOMEM;\n\t\tgoto free_newinfo;\n\t}\n\tif (copy_from_user(\n\t   newinfo->entries, tmp.entries, tmp.entries_size) != 0) {\n\t\tret = -EFAULT;\n\t\tgoto free_entries;\n\t}\n\n\tentries_tmp = newinfo->entries;\n\n\txt_compat_lock(NFPROTO_BRIDGE);\n\n\tret = ebt_compat_init_offsets(tmp.nentries);\n\tif (ret < 0)\n\t\tgoto out_unlock;\n\n\tret = compat_copy_entries(entries_tmp, tmp.entries_size, &state);\n\tif (ret < 0)\n\t\tgoto out_unlock;\n\n\tpr_debug(\"tmp.entries_size %d, kern off %d, user off %d delta %d\\n\",\n\t\ttmp.entries_size, state.buf_kern_offset, state.buf_user_offset,\n\t\txt_compat_calc_jump(NFPROTO_BRIDGE, tmp.entries_size));\n\n\tsize64 = ret;\n\tnewinfo->entries = vmalloc(size64);\n\tif (!newinfo->entries) {\n\t\tvfree(entries_tmp);\n\t\tret = -ENOMEM;\n\t\tgoto out_unlock;\n\t}\n\n\tmemset(&state, 0, sizeof(state));\n\tstate.buf_kern_start = newinfo->entries;\n\tstate.buf_kern_len = size64;\n\n\tret = compat_copy_entries(entries_tmp, tmp.entries_size, &state);\n\tif (WARN_ON(ret < 0)) {\n\t\tvfree(entries_tmp);\n\t\tgoto out_unlock;\n\t}\n\n\tvfree(entries_tmp);\n\ttmp.entries_size = size64;\n\n\tfor (i = 0; i < NF_BR_NUMHOOKS; i++) {\n\t\tchar __user *usrptr;\n\t\tif (tmp.hook_entry[i]) {\n\t\t\tunsigned int delta;\n\t\t\tusrptr = (char __user *) tmp.hook_entry[i];\n\t\t\tdelta = usrptr - tmp.entries;\n\t\t\tusrptr += xt_compat_calc_jump(NFPROTO_BRIDGE, delta);\n\t\t\ttmp.hook_entry[i] = (struct ebt_entries __user *)usrptr;\n\t\t}\n\t}\n\n\txt_compat_flush_offsets(NFPROTO_BRIDGE);\n\txt_compat_unlock(NFPROTO_BRIDGE);\n\n\tret = do_replace_finish(net, &tmp, newinfo);\n\tif (ret == 0)\n\t\treturn ret;\nfree_entries:\n\tvfree(newinfo->entries);\nfree_newinfo:\n\tvfree(newinfo);\n\treturn ret;\nout_unlock:\n\txt_compat_flush_offsets(NFPROTO_BRIDGE);\n\txt_compat_unlock(NFPROTO_BRIDGE);\n\tgoto free_entries;\n}",
        "static void alc_headset_mode_default(struct hda_codec *codec)\n{\n\tstatic const struct coef_fw coef0225[] = {\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x30<<10),\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x31<<10),": "static void alc_headset_mode_default(struct hda_codec *codec)\n{\n\tstatic const struct coef_fw coef0225[] = {\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x30<<10),\n\t\tUPDATE_COEF(0x45, 0x3f<<10, 0x31<<10),\n\t\tUPDATE_COEF(0x49, 3<<8, 0<<8),\n\t\tUPDATE_COEF(0x4a, 3<<4, 3<<4),\n\t\tUPDATE_COEF(0x63, 3<<14, 0),\n\t\tUPDATE_COEF(0x67, 0xf000, 0x3000),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0255[] = {\n\t\tWRITE_COEF(0x45, 0xc089),\n\t\tWRITE_COEF(0x45, 0xc489),\n\t\tWRITE_COEFEX(0x57, 0x03, 0x8ea6),\n\t\tWRITE_COEF(0x49, 0x0049),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0256[] = {\n\t\tWRITE_COEF(0x45, 0xc489),\n\t\tWRITE_COEFEX(0x57, 0x03, 0x0da3),\n\t\tWRITE_COEF(0x49, 0x0049),\n\t\tUPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/\n\t\tWRITE_COEF(0x06, 0x6100),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0233[] = {\n\t\tWRITE_COEF(0x06, 0x2100),\n\t\tWRITE_COEF(0x32, 0x4ea3),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0288[] = {\n\t\tUPDATE_COEF(0x4f, 0xfcc0, 0xc400), /* Set to TRS type */\n\t\tUPDATE_COEF(0x50, 0x2000, 0x2000),\n\t\tUPDATE_COEF(0x56, 0x0006, 0x0006),\n\t\tUPDATE_COEF(0x66, 0x0008, 0),\n\t\tUPDATE_COEF(0x67, 0x2000, 0),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0292[] = {\n\t\tWRITE_COEF(0x76, 0x000e),\n\t\tWRITE_COEF(0x6c, 0x2400),\n\t\tWRITE_COEF(0x6b, 0xc429),\n\t\tWRITE_COEF(0x18, 0x7308),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0293[] = {\n\t\tUPDATE_COEF(0x4a, 0x000f, 0x000e), /* Combo Jack auto detect */\n\t\tWRITE_COEF(0x45, 0xC429), /* Set to TRS type */\n\t\tUPDATE_COEF(0x1a, 1<<3, 0), /* Combo JD gating without LINE1-VREFO */\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0688[] = {\n\t\tWRITE_COEF(0x11, 0x0041),\n\t\tWRITE_COEF(0x15, 0x0d40),\n\t\tWRITE_COEF(0xb7, 0x802b),\n\t\t{}\n\t};\n\tstatic const struct coef_fw coef0274[] = {\n\t\tWRITE_COEF(0x45, 0x4289),\n\t\tUPDATE_COEF(0x4a, 0x0010, 0x0010),\n\t\tUPDATE_COEF(0x6b, 0x0f00, 0),\n\t\tUPDATE_COEF(0x49, 0x0300, 0x0300),\n\t\t{}\n\t};\n\n\tswitch (codec->core.vendor_id) {\n\tcase 0x10ec0215:\n\tcase 0x10ec0225:\n\tcase 0x10ec0285:\n\tcase 0x10ec0295:\n\tcase 0x10ec0289:\n\tcase 0x10ec0299:\n\t\talc_process_coef_fw(codec, alc225_pre_hsmode);\n\t\talc_process_coef_fw(codec, coef0225);\n\t\tbreak;\n\tcase 0x10ec0255:\n\t\talc_process_coef_fw(codec, coef0255);\n\t\tbreak;\n\tcase 0x10ec0230:\n\tcase 0x10ec0236:\n\tcase 0x10ec0256:\n\t\talc_write_coef_idx(codec, 0x1b, 0x0e4b);\n\t\talc_write_coef_idx(codec, 0x45, 0xc089);\n\t\tmsleep(50);\n\t\talc_process_coef_fw(codec, coef0256);\n\t\tbreak;\n\tcase 0x10ec0234:\n\tcase 0x10ec0274:\n\tcase 0x10ec0294:\n\t\talc_process_coef_fw(codec, coef0274);\n\t\tbreak;\n\tcase 0x10ec0233:\n\tcase 0x10ec0283:\n\t\talc_process_coef_fw(codec, coef0233);\n\t\tbreak;\n\tcase 0x10ec0286:\n\tcase 0x10ec0288:\n\tcase 0x10ec0298:\n\t\talc_process_coef_fw(codec, coef0288);\n\t\tbreak;\n\tcase 0x10ec0292:\n\t\talc_process_coef_fw(codec, coef0292);\n\t\tbreak;\n\tcase 0x10ec0293:\n\t\talc_process_coef_fw(codec, coef0293);\n\t\tbreak;\n\tcase 0x10ec0668:\n\t\talc_process_coef_fw(codec, coef0688);\n\t\tbreak;\n\tcase 0x10ec0867:\n\t\talc_update_coefex_idx(codec, 0x57, 0x5, 1<<14, 0);\n\t\tbreak;\n\t}\n\tcodec_dbg(codec, \"Headset jack set to headphone (default) mode.\\n\");\n}",
        "static int kmb_ocs_aead_dma_prepare(struct aead_request *req, u32 *src_dll_size)\n{\n\tstruct ocs_aes_tctx *tctx = crypto_aead_ctx(crypto_aead_reqtfm(req));\n\tconst int tag_size = crypto_aead_authsize(crypto_aead_reqtfm(req));\n\tstruct ocs_aes_rctx *rctx = aead_request_ctx(req);": "static int kmb_ocs_aead_dma_prepare(struct aead_request *req, u32 *src_dll_size)\n{\n\tstruct ocs_aes_tctx *tctx = crypto_aead_ctx(crypto_aead_reqtfm(req));\n\tconst int tag_size = crypto_aead_authsize(crypto_aead_reqtfm(req));\n\tstruct ocs_aes_rctx *rctx = aead_request_ctx(req);\n\tu32 in_size;\t/* The length of the data to be mapped by src_dll. */\n\tu32 out_size;\t/* The length of the data to be mapped by dst_dll. */\n\tu32 dst_size;\t/* The length of the data in dst_sg. */\n\tint rc;\n\n\t/* Get number of entries in input data SG list. */\n\trctx->src_nents = sg_nents_for_len(req->src,\n\t\t\t\t\t   req->assoclen + req->cryptlen);\n\tif (rctx->src_nents < 0)\n\t\treturn -EBADMSG;\n\n\tif (rctx->instruction == OCS_DECRYPT) {\n\t\t/*\n\t\t * For decrypt:\n\t\t * - src sg list is:\t\tAAD|CT|tag\n\t\t * - dst sg list expects:\tAAD|PT\n\t\t *\n\t\t * in_size == len(CT); out_size == len(PT)\n\t\t */\n\n\t\t/* req->cryptlen includes both CT and tag. */\n\t\tin_size = req->cryptlen - tag_size;\n\n\t\t/* out_size = PT size == CT size */\n\t\tout_size = in_size;\n\n\t\t/* len(dst_sg) == len(AAD) + len(PT) */\n\t\tdst_size = req->assoclen + out_size;\n\n\t\t/*\n\t\t * Copy tag from source SG list to 'in_tag' buffer.\n\t\t *\n\t\t * Note: this needs to be done here, before DMA mapping src_sg.\n\t\t */\n\t\tsg_pcopy_to_buffer(req->src, rctx->src_nents, rctx->in_tag,\n\t\t\t\t   tag_size, req->assoclen + in_size);\n\n\t} else { /* OCS_ENCRYPT */\n\t\t/*\n\t\t * For encrypt:\n\t\t *\tsrc sg list is:\t\tAAD|PT\n\t\t *\tdst sg list expects:\tAAD|CT|tag\n\t\t */\n\t\t/* in_size == len(PT) */\n\t\tin_size = req->cryptlen;\n\n\t\t/*\n\t\t * In CCM mode the OCS engine appends the tag to the ciphertext,\n\t\t * but in GCM mode the tag must be read from the tag registers\n\t\t * and appended manually below\n\t\t */\n\t\tout_size = (rctx->mode == OCS_MODE_CCM) ? in_size + tag_size :\n\t\t\t\t\t\t\t  in_size;\n\t\t/* len(dst_sg) == len(AAD) + len(CT) + len(tag) */\n\t\tdst_size = req->assoclen + in_size + tag_size;\n\t}\n\t*src_dll_size = in_size;\n\n\t/* Get number of entries in output data SG list. */\n\trctx->dst_nents = sg_nents_for_len(req->dst, dst_size);\n\tif (rctx->dst_nents < 0)\n\t\treturn -EBADMSG;\n\n\trctx->in_place = (req->src == req->dst) ? 1 : 0;\n\n\t/* Map destination; use bidirectional mapping for in-place case. */\n\trctx->dst_dma_count = dma_map_sg(tctx->aes_dev->dev, req->dst,\n\t\t\t\t\t rctx->dst_nents,\n\t\t\t\t\t rctx->in_place ? DMA_BIDIRECTIONAL :\n\t\t\t\t\t\t\t  DMA_FROM_DEVICE);\n\tif (rctx->dst_dma_count == 0 && rctx->dst_nents != 0) {\n\t\tdev_err(tctx->aes_dev->dev, \"Failed to map destination sg\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Create AAD DST list: maps dst[0:AAD_SIZE-1]. */\n\trc = ocs_create_linked_list_from_sg(tctx->aes_dev, req->dst,\n\t\t\t\t\t    rctx->dst_dma_count,\n\t\t\t\t\t    &rctx->aad_dst_dll, req->assoclen,\n\t\t\t\t\t    0);\n\tif (rc)\n\t\treturn rc;\n\n\t/* Create DST list: maps dst[AAD_SIZE:out_size] */\n\trc = ocs_create_linked_list_from_sg(tctx->aes_dev, req->dst,\n\t\t\t\t\t    rctx->dst_dma_count, &rctx->dst_dll,\n\t\t\t\t\t    out_size, req->assoclen);\n\tif (rc)\n\t\treturn rc;\n\n\tif (rctx->in_place) {\n\t\t/* If this is not CCM encrypt, we are done. */\n\t\tif (!(rctx->mode == OCS_MODE_CCM &&\n\t\t      rctx->instruction == OCS_ENCRYPT)) {\n\t\t\t/*\n\t\t\t * SRC and DST are the same, so re-use the same DMA\n\t\t\t * addresses (to avoid allocating new DMA lists\n\t\t\t * identical to the dst ones).\n\t\t\t */\n\t\t\trctx->src_dll.dma_addr = rctx->dst_dll.dma_addr;\n\t\t\trctx->aad_src_dll.dma_addr = rctx->aad_dst_dll.dma_addr;\n\n\t\t\treturn 0;\n\t\t}\n\t\t/*\n\t\t * For CCM encrypt the input and output linked lists contain\n\t\t * different amounts of data, so, we need to create different\n\t\t * SRC and AAD SRC lists, even for the in-place case.\n\t\t */\n\t\trc = ocs_create_linked_list_from_sg(tctx->aes_dev, req->dst,\n\t\t\t\t\t\t    rctx->dst_dma_count,\n\t\t\t\t\t\t    &rctx->aad_src_dll,\n\t\t\t\t\t\t    req->assoclen, 0);\n\t\tif (rc)\n\t\t\treturn rc;\n\t\trc = ocs_create_linked_list_from_sg(tctx->aes_dev, req->dst,\n\t\t\t\t\t\t    rctx->dst_dma_count,\n\t\t\t\t\t\t    &rctx->src_dll, in_size,\n\t\t\t\t\t\t    req->assoclen);\n\t\tif (rc)\n\t\t\treturn rc;\n\n\t\treturn 0;\n\t}\n\t/* Not in-place case. */\n\n\t/* Map source SG. */\n\trctx->src_dma_count = dma_map_sg(tctx->aes_dev->dev, req->src,\n\t\t\t\t\t rctx->src_nents, DMA_TO_DEVICE);\n\tif (rctx->src_dma_count == 0 && rctx->src_nents != 0) {\n\t\tdev_err(tctx->aes_dev->dev, \"Failed to map source sg\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Create AAD SRC list. */\n\trc = ocs_create_linked_list_from_sg(tctx->aes_dev, req->src,\n\t\t\t\t\t    rctx->src_dma_count,\n\t\t\t\t\t    &rctx->aad_src_dll,\n\t\t\t\t\t    req->assoclen, 0);\n\tif (rc)\n\t\treturn rc;\n\n\t/* Create SRC list. */\n\trc = ocs_create_linked_list_from_sg(tctx->aes_dev, req->src,\n\t\t\t\t\t    rctx->src_dma_count,\n\t\t\t\t\t    &rctx->src_dll, in_size,\n\t\t\t\t\t    req->assoclen);\n\tif (rc)\n\t\treturn rc;\n\n\tif (req->assoclen == 0)\n\t\treturn 0;\n\n\t/* Copy AAD from src sg to dst sg using OCS DMA. */\n\trc = ocs_aes_bypass_op(tctx->aes_dev, rctx->aad_dst_dll.dma_addr,\n\t\t\t       rctx->aad_src_dll.dma_addr, req->cryptlen);\n\tif (rc)\n\t\tdev_err(tctx->aes_dev->dev,\n\t\t\t\"Failed to copy source AAD to destination AAD\\n\");\n\n\treturn rc;\n}",
        "static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int on, tmp, channel_cfg;\n\tint num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;": "static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)\n{\n\tstruct ca0132_spec *spec = codec->spec;\n\tunsigned int on, tmp, channel_cfg;\n\tint num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;\n\tint err = 0;\n\tint idx = nid - EFFECT_START_NID;\n\n\tif ((idx < 0) || (idx >= num_fx))\n\t\treturn 0; /* no changed */\n\n\t/* for out effect, qualify with PE */\n\tif ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {\n\t\t/* if PE if off, turn off out effects. */\n\t\tif (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])\n\t\t\tval = 0;\n\t\tif (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {\n\t\t\tchannel_cfg = spec->channel_cfg_val;\n\t\t\tif (channel_cfg != SPEAKER_CHANNELS_2_0 &&\n\t\t\t\t\tchannel_cfg != SPEAKER_CHANNELS_4_0)\n\t\t\t\tval = 0;\n\t\t}\n\t}\n\n\t/* for in effect, qualify with CrystalVoice */\n\tif ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {\n\t\t/* if CrystalVoice if off, turn off in effects. */\n\t\tif (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])\n\t\t\tval = 0;\n\n\t\t/* Voice Focus applies to 2-ch Mic, Digital Mic */\n\t\tif ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))\n\t\t\tval = 0;\n\n\t\t/* If Voice Focus on SBZ, set to two channel. */\n\t\tif ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)\n\t\t\t\t&& (spec->cur_mic_type != REAR_LINE_IN)) {\n\t\t\tif (spec->effects_switch[CRYSTAL_VOICE -\n\t\t\t\t\t\t EFFECT_START_NID]) {\n\n\t\t\t\tif (spec->effects_switch[VOICE_FOCUS -\n\t\t\t\t\t\t\t EFFECT_START_NID]) {\n\t\t\t\t\ttmp = FLOAT_TWO;\n\t\t\t\t\tval = 1;\n\t\t\t\t} else\n\t\t\t\t\ttmp = FLOAT_ONE;\n\n\t\t\t\tdspio_set_uint_param(codec, 0x80, 0x00, tmp);\n\t\t\t}\n\t\t}\n\t\t/*\n\t\t * For SBZ noise reduction, there's an extra command\n\t\t * to module ID 0x47. No clue why.\n\t\t */\n\t\tif ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)\n\t\t\t\t&& (spec->cur_mic_type != REAR_LINE_IN)) {\n\t\t\tif (spec->effects_switch[CRYSTAL_VOICE -\n\t\t\t\t\t\t EFFECT_START_NID]) {\n\t\t\t\tif (spec->effects_switch[NOISE_REDUCTION -\n\t\t\t\t\t\t\t EFFECT_START_NID])\n\t\t\t\t\ttmp = FLOAT_ONE;\n\t\t\t\telse\n\t\t\t\t\ttmp = FLOAT_ZERO;\n\t\t\t} else\n\t\t\t\ttmp = FLOAT_ZERO;\n\n\t\t\tdspio_set_uint_param(codec, 0x47, 0x00, tmp);\n\t\t}\n\n\t\t/* If rear line in disable effects. */\n\t\tif (ca0132_use_alt_functions(spec) &&\n\t\t\t\tspec->in_enum_val == REAR_LINE_IN)\n\t\t\tval = 0;\n\t}\n\n\tcodec_dbg(codec, \"ca0132_effect_set: nid=0x%x, val=%ld\\n\",\n\t\t    nid, val);\n\n\ton = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;\n\terr = dspio_set_uint_param(codec, ca0132_effects[idx].mid,\n\t\t\t\t   ca0132_effects[idx].reqs[0], on);\n\n\tif (err < 0)\n\t\treturn 0; /* no changed */\n\n\treturn 1;\n}",
        "static int __tipc_nl_node_set_key(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct nlattr *attrs[TIPC_NLA_NODE_MAX + 1];\n\tstruct net *net = sock_net(skb->sk);\n\tstruct tipc_crypto *tx = tipc_net(net)->crypto_tx, *c = tx;": "static int __tipc_nl_node_set_key(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct nlattr *attrs[TIPC_NLA_NODE_MAX + 1];\n\tstruct net *net = sock_net(skb->sk);\n\tstruct tipc_crypto *tx = tipc_net(net)->crypto_tx, *c = tx;\n\tstruct tipc_node *n = NULL;\n\tstruct tipc_aead_key *ukey;\n\tbool rekeying = true, master_key = false;\n\tu8 *id, *own_id, mode;\n\tu32 intv = 0;\n\tint rc = 0;\n\n\tif (!info->attrs[TIPC_NLA_NODE])\n\t\treturn -EINVAL;\n\n\trc = nla_parse_nested(attrs, TIPC_NLA_NODE_MAX,\n\t\t\t      info->attrs[TIPC_NLA_NODE],\n\t\t\t      tipc_nl_node_policy, info->extack);\n\tif (rc)\n\t\treturn rc;\n\n\town_id = tipc_own_id(net);\n\tif (!own_id) {\n\t\tGENL_SET_ERR_MSG(info, \"not found own node identity (set id?)\");\n\t\treturn -EPERM;\n\t}\n\n\trc = tipc_nl_retrieve_rekeying(attrs, &intv);\n\tif (rc == -ENODATA)\n\t\trekeying = false;\n\n\trc = tipc_nl_retrieve_key(attrs, &ukey);\n\tif (rc == -ENODATA && rekeying)\n\t\tgoto rekeying;\n\telse if (rc)\n\t\treturn rc;\n\n\trc = tipc_aead_key_validate(ukey, info);\n\tif (rc)\n\t\treturn rc;\n\n\trc = tipc_nl_retrieve_nodeid(attrs, &id);\n\tswitch (rc) {\n\tcase -ENODATA:\n\t\tmode = CLUSTER_KEY;\n\t\tmaster_key = !!(attrs[TIPC_NLA_NODE_KEY_MASTER]);\n\t\tbreak;\n\tcase 0:\n\t\tmode = PER_NODE_KEY;\n\t\tif (memcmp(id, own_id, NODE_ID_LEN)) {\n\t\t\tn = tipc_node_find_by_id(net, id) ?:\n\t\t\t\ttipc_node_create(net, 0, id, 0xffffu, 0, true);\n\t\t\tif (unlikely(!n))\n\t\t\t\treturn -ENOMEM;\n\t\t\tc = n->crypto_rx;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\treturn rc;\n\t}\n\n\t/* Initiate the TX/RX key */\n\trc = tipc_crypto_key_init(c, ukey, mode, master_key);\n\tif (n)\n\t\ttipc_node_put(n);\n\n\tif (unlikely(rc < 0)) {\n\t\tGENL_SET_ERR_MSG(info, \"unable to initiate or attach new key\");\n\t\treturn rc;\n\t} else if (c == tx) {\n\t\t/* Distribute TX key but not master one */\n\t\tif (!master_key && tipc_crypto_key_distr(tx, rc, NULL))\n\t\t\tGENL_SET_ERR_MSG(info, \"failed to replicate new key\");\nrekeying:\n\t\t/* Schedule TX rekeying if needed */\n\t\ttipc_crypto_rekeying_sched(tx, rekeying, intv);\n\t}\n\n\treturn 0;\n}",
        "static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)\n{\n\tstruct attn_route attn, *group_mask;\n\tint port = BP_PORT(bp);\n\tint index;": "static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)\n{\n\tstruct attn_route attn, *group_mask;\n\tint port = BP_PORT(bp);\n\tint index;\n\tu32 reg_addr;\n\tu32 val;\n\tu32 aeu_mask;\n\tbool global = false;\n\n\t/* need to take HW lock because MCP or other port might also\n\t   try to handle this event */\n\tbnx2x_acquire_alr(bp);\n\n\tif (bnx2x_chk_parity_attn(bp, &global, true)) {\n#ifndef BNX2X_STOP_ON_ERROR\n\t\tbp->recovery_state = BNX2X_RECOVERY_INIT;\n\t\tschedule_delayed_work(&bp->sp_rtnl_task, 0);\n\t\t/* Disable HW interrupts */\n\t\tbnx2x_int_disable(bp);\n\t\t/* In case of parity errors don't handle attentions so that\n\t\t * other function would \"see\" parity errors.\n\t\t */\n#else\n\t\tbnx2x_panic();\n#endif\n\t\tbnx2x_release_alr(bp);\n\t\treturn;\n\t}\n\n\tattn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);\n\tattn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);\n\tattn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);\n\tattn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);\n\tif (!CHIP_IS_E1x(bp))\n\t\tattn.sig[4] =\n\t\t      REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);\n\telse\n\t\tattn.sig[4] = 0;\n\n\tDP(NETIF_MSG_HW, \"attn: %08x %08x %08x %08x %08x\\n\",\n\t   attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);\n\n\tfor (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {\n\t\tif (deasserted & (1 << index)) {\n\t\t\tgroup_mask = &bp->attn_group[index];\n\n\t\t\tDP(NETIF_MSG_HW, \"group[%d]: %08x %08x %08x %08x %08x\\n\",\n\t\t\t   index,\n\t\t\t   group_mask->sig[0], group_mask->sig[1],\n\t\t\t   group_mask->sig[2], group_mask->sig[3],\n\t\t\t   group_mask->sig[4]);\n\n\t\t\tbnx2x_attn_int_deasserted4(bp,\n\t\t\t\t\tattn.sig[4] & group_mask->sig[4]);\n\t\t\tbnx2x_attn_int_deasserted3(bp,\n\t\t\t\t\tattn.sig[3] & group_mask->sig[3]);\n\t\t\tbnx2x_attn_int_deasserted1(bp,\n\t\t\t\t\tattn.sig[1] & group_mask->sig[1]);\n\t\t\tbnx2x_attn_int_deasserted2(bp,\n\t\t\t\t\tattn.sig[2] & group_mask->sig[2]);\n\t\t\tbnx2x_attn_int_deasserted0(bp,\n\t\t\t\t\tattn.sig[0] & group_mask->sig[0]);\n\t\t}\n\t}\n\n\tbnx2x_release_alr(bp);\n\n\tif (bp->common.int_block == INT_BLOCK_HC)\n\t\treg_addr = (HC_REG_COMMAND_REG + port*32 +\n\t\t\t    COMMAND_REG_ATTN_BITS_CLR);\n\telse\n\t\treg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);\n\n\tval = ~deasserted;\n\tDP(NETIF_MSG_HW, \"about to mask 0x%08x at %s addr 0x%x\\n\", val,\n\t   (bp->common.int_block == INT_BLOCK_HC) ? \"HC\" : \"IGU\", reg_addr);\n\tREG_WR(bp, reg_addr, val);\n\n\tif (~bp->attn_state & deasserted)\n\t\tBNX2X_ERR(\"IGU ERROR\\n\");\n\n\treg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :\n\t\t\t  MISC_REG_AEU_MASK_ATTN_FUNC_0;\n\n\tbnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);\n\taeu_mask = REG_RD(bp, reg_addr);\n\n\tDP(NETIF_MSG_HW, \"aeu_mask %x  newly deasserted %x\\n\",\n\t   aeu_mask, deasserted);\n\taeu_mask |= (deasserted & 0x3ff);\n\tDP(NETIF_MSG_HW, \"new mask %x\\n\", aeu_mask);\n\n\tREG_WR(bp, reg_addr, aeu_mask);\n\tbnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);\n\n\tDP(NETIF_MSG_HW, \"attn_state %x\\n\", bp->attn_state);\n\tbp->attn_state &= ~deasserted;\n\tDP(NETIF_MSG_HW, \"new state %x\\n\", bp->attn_state);\n}",
        "static int ispif_set_stream(struct v4l2_subdev *sd, int enable)\n{\n\tstruct ispif_line *line = v4l2_get_subdevdata(sd);\n\tstruct ispif_device *ispif = line->ispif;\n\tstruct camss *camss = ispif->camss;": "static int ispif_set_stream(struct v4l2_subdev *sd, int enable)\n{\n\tstruct ispif_line *line = v4l2_get_subdevdata(sd);\n\tstruct ispif_device *ispif = line->ispif;\n\tstruct camss *camss = ispif->camss;\n\tenum ispif_intf intf = line->interface;\n\tu8 csid = line->csid_id;\n\tu8 vfe = line->vfe_id;\n\tu8 vc = 0; /* Virtual Channel 0 */\n\tu8 cid = vc * 4; /* id of Virtual Channel and Data Type set */\n\tint ret;\n\n\tif (enable) {\n\t\tif (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))\n\t\t\treturn -ENOLINK;\n\n\t\t/* Config */\n\n\t\tmutex_lock(&ispif->config_lock);\n\t\tispif_select_clk_mux(ispif, intf, csid, vfe, 1);\n\n\t\tret = ispif_validate_intf_status(ispif, intf, vfe);\n\t\tif (ret < 0) {\n\t\t\tmutex_unlock(&ispif->config_lock);\n\t\t\treturn ret;\n\t\t}\n\n\t\tispif_select_csid(ispif, intf, csid, vfe, 1);\n\t\tispif_select_cid(ispif, intf, cid, vfe, 1);\n\t\tispif_config_irq(ispif, intf, vfe, 1);\n\t\tif (camss->version == CAMSS_8x96 ||\n\t\t    camss->version == CAMSS_660)\n\t\t\tispif_config_pack(ispif,\n\t\t\t\t\t  line->fmt[MSM_ISPIF_PAD_SINK].code,\n\t\t\t\t\t  intf, cid, vfe, 1);\n\t\tispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,\n\t\t\t\t   intf, vfe, vc);\n\t} else {\n\t\tmutex_lock(&ispif->config_lock);\n\t\tispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,\n\t\t\t\t   intf, vfe, vc);\n\t\tmutex_unlock(&ispif->config_lock);\n\n\t\tret = ispif_wait_for_stop(ispif, intf, vfe);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tmutex_lock(&ispif->config_lock);\n\t\tif (camss->version == CAMSS_8x96 ||\n\t\t    camss->version == CAMSS_660)\n\t\t\tispif_config_pack(ispif,\n\t\t\t\t\t  line->fmt[MSM_ISPIF_PAD_SINK].code,\n\t\t\t\t\t  intf, cid, vfe, 0);\n\t\tispif_config_irq(ispif, intf, vfe, 0);\n\t\tispif_select_cid(ispif, intf, cid, vfe, 0);\n\t\tispif_select_csid(ispif, intf, csid, vfe, 0);\n\t\tispif_select_clk_mux(ispif, intf, csid, vfe, 0);\n\t}\n\n\tmutex_unlock(&ispif->config_lock);\n\n\treturn 0;\n}",
        "static int ice_set_dvm(struct ice_hw *hw)\n{\n\tstruct ice_aqc_set_vlan_mode params = { 0 };\n\tint status;\n": "static int ice_set_dvm(struct ice_hw *hw)\n{\n\tstruct ice_aqc_set_vlan_mode params = { 0 };\n\tint status;\n\n\tparams.l2tag_prio_tagging = ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG;\n\tparams.rdma_packet = ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING;\n\tparams.mng_vlan_prot_id = ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER;\n\n\tstatus = ice_aq_set_vlan_mode(hw, &params);\n\tif (status) {\n\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to set double VLAN mode parameters, status %d\\n\",\n\t\t\t  status);\n\t\treturn status;\n\t}\n\n\tstatus = ice_dvm_update_dflt_recipes(hw);\n\tif (status) {\n\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to update default recipes for double VLAN mode, status %d\\n\",\n\t\t\t  status);\n\t\treturn status;\n\t}\n\n\tstatus = ice_aq_set_port_params(hw->port_info, true, NULL);\n\tif (status) {\n\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to set port in double VLAN mode, status %d\\n\",\n\t\t\t  status);\n\t\treturn status;\n\t}\n\n\tstatus = ice_set_dvm_boost_entries(hw);\n\tif (status) {\n\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to set boost TCAM entries for double VLAN mode, status %d\\n\",\n\t\t\t  status);\n\t\treturn status;\n\t}\n\n\treturn 0;\n}",
        "static int rvu_dbg_rvu_pf_cgx_map_display(struct seq_file *filp, void *unused)\n{\n\tstruct rvu *rvu = filp->private;\n\tstruct pci_dev *pdev = NULL;\n\tstruct mac_ops *mac_ops;": "static int rvu_dbg_rvu_pf_cgx_map_display(struct seq_file *filp, void *unused)\n{\n\tstruct rvu *rvu = filp->private;\n\tstruct pci_dev *pdev = NULL;\n\tstruct mac_ops *mac_ops;\n\tchar cgx[10], lmac[10];\n\tstruct rvu_pfvf *pfvf;\n\tint pf, domain, blkid;\n\tu8 cgx_id, lmac_id;\n\tu16 pcifunc;\n\n\tdomain = 2;\n\tmac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));\n\t/* There can be no CGX devices at all */\n\tif (!mac_ops)\n\t\treturn 0;\n\tseq_printf(filp, \"PCI dev\\t\\tRVU PF Func\\tNIX block\\t%s\\tLMAC\\n\",\n\t\t   mac_ops->name);\n\tfor (pf = 0; pf < rvu->hw->total_pfs; pf++) {\n\t\tif (!is_pf_cgxmapped(rvu, pf))\n\t\t\tcontinue;\n\n\t\tpdev =  pci_get_domain_bus_and_slot(domain, pf + 1, 0);\n\t\tif (!pdev)\n\t\t\tcontinue;\n\n\t\tcgx[0] = 0;\n\t\tlmac[0] = 0;\n\t\tpcifunc = pf << 10;\n\t\tpfvf = rvu_get_pfvf(rvu, pcifunc);\n\n\t\tif (pfvf->nix_blkaddr == BLKADDR_NIX0)\n\t\t\tblkid = 0;\n\t\telse\n\t\t\tblkid = 1;\n\n\t\trvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id,\n\t\t\t\t    &lmac_id);\n\t\tsprintf(cgx, \"%s%d\", mac_ops->name, cgx_id);\n\t\tsprintf(lmac, \"LMAC%d\", lmac_id);\n\t\tseq_printf(filp, \"%s\\t0x%x\\t\\tNIX%d\\t\\t%s\\t%s\\n\",\n\t\t\t   dev_name(&pdev->dev), pcifunc, blkid, cgx, lmac);\n\t}\n\treturn 0;\n}",
        "static enum retry_state ecache_work_evict_list(struct nf_conntrack_net *cnet)\n{\n\tunsigned long stop = jiffies + ECACHE_MAX_JIFFIES;\n\tstruct hlist_nulls_head evicted_list;\n\tenum retry_state ret = STATE_DONE;": "static enum retry_state ecache_work_evict_list(struct nf_conntrack_net *cnet)\n{\n\tunsigned long stop = jiffies + ECACHE_MAX_JIFFIES;\n\tstruct hlist_nulls_head evicted_list;\n\tenum retry_state ret = STATE_DONE;\n\tstruct nf_conntrack_tuple_hash *h;\n\tstruct hlist_nulls_node *n;\n\tunsigned int sent;\n\n\tINIT_HLIST_NULLS_HEAD(&evicted_list, DYING_NULLS_VAL);\n\nnext:\n\tsent = 0;\n\tspin_lock_bh(&cnet->ecache.dying_lock);\n\n\thlist_nulls_for_each_entry_safe(h, n, &cnet->ecache.dying_list, hnnode) {\n\t\tstruct nf_conn *ct = nf_ct_tuplehash_to_ctrack(h);\n\n\t\t/* The worker owns all entries, ct remains valid until nf_ct_put\n\t\t * in the loop below.\n\t\t */\n\t\tif (nf_conntrack_event(IPCT_DESTROY, ct)) {\n\t\t\tret = STATE_CONGESTED;\n\t\t\tbreak;\n\t\t}\n\n\t\thlist_nulls_del_rcu(&ct->tuplehash[IP_CT_DIR_ORIGINAL].hnnode);\n\t\thlist_nulls_add_head(&ct->tuplehash[IP_CT_DIR_REPLY].hnnode, &evicted_list);\n\n\t\tif (time_after(stop, jiffies)) {\n\t\t\tret = STATE_RESTART;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (sent++ > 16) {\n\t\t\tspin_unlock_bh(&cnet->ecache.dying_lock);\n\t\t\tcond_resched();\n\t\t\tgoto next;\n\t\t}\n\t}\n\n\tspin_unlock_bh(&cnet->ecache.dying_lock);\n\n\thlist_nulls_for_each_entry_safe(h, n, &evicted_list, hnnode) {\n\t\tstruct nf_conn *ct = nf_ct_tuplehash_to_ctrack(h);\n\n\t\thlist_nulls_del_rcu(&ct->tuplehash[IP_CT_DIR_REPLY].hnnode);\n\t\tnf_ct_put(ct);\n\n\t\tcond_resched();\n\t}\n\n\treturn ret;\n}",
        "static void *worker_testapp_validate_rx(void *arg)\n{\n\tstruct test_spec *test = (struct test_spec *)arg;\n\tstruct ifobject *ifobject = test->ifobj_rx;\n\tstruct pollfd fds = { };": "static void *worker_testapp_validate_rx(void *arg)\n{\n\tstruct test_spec *test = (struct test_spec *)arg;\n\tstruct ifobject *ifobject = test->ifobj_rx;\n\tstruct pollfd fds = { };\n\tint err;\n\n\tif (test->current_step == 1)\n\t\tthread_common_ops(test, ifobject);\n\n\txsk_populate_fill_ring(ifobject->umem, ifobject->pkt_stream);\n\n\tfds.fd = xsk_socket__fd(ifobject->xsk->xsk);\n\tfds.events = POLLIN;\n\n\tpthread_barrier_wait(&barr);\n\n\terr = receive_pkts(ifobject, &fds);\n\n\tif (!err && ifobject->validation_func)\n\t\terr = ifobject->validation_func(ifobject);\n\tif (err) {\n\t\treport_failure(test);\n\t\tpthread_mutex_lock(&pacing_mutex);\n\t\tpthread_cond_signal(&pacing_cond);\n\t\tpthread_mutex_unlock(&pacing_mutex);\n\t}\n\n\tif (test->total_steps == test->current_step || err)\n\t\ttestapp_cleanup_xsk_res(ifobject);\n\tpthread_exit(NULL);\n}",
        "static int fun_enter_xdp(struct net_device *dev, struct bpf_prog *prog)\n{\n\tstruct funeth_priv *fp = netdev_priv(dev);\n\tunsigned int i, nqs = num_online_cpus();\n\tstruct funeth_txq **xdpqs;": "static int fun_enter_xdp(struct net_device *dev, struct bpf_prog *prog)\n{\n\tstruct funeth_priv *fp = netdev_priv(dev);\n\tunsigned int i, nqs = num_online_cpus();\n\tstruct funeth_txq **xdpqs;\n\tstruct funeth_rxq **rxqs;\n\tint err;\n\n\txdpqs = alloc_xdpqs(dev, nqs, fp->sq_depth, 0, FUN_QSTATE_INIT_FULL);\n\tif (IS_ERR(xdpqs))\n\t\treturn PTR_ERR(xdpqs);\n\n\trxqs = rtnl_dereference(fp->rxqs);\n\tfor (i = 0; i < dev->real_num_rx_queues; i++) {\n\t\terr = fun_rxq_set_bpf(rxqs[i], prog);\n\t\tif (err)\n\t\t\tgoto out;\n\t}\n\n\tfp->num_xdpqs = nqs;\n\trcu_assign_pointer(fp->xdpqs, xdpqs);\n\treturn 0;\nout:\n\twhile (i--)\n\t\tfun_rxq_set_bpf(rxqs[i], NULL);\n\n\tfree_xdpqs(xdpqs, nqs, 0, FUN_QSTATE_DESTROYED);\n\treturn err;\n}",
        "static int prp_registered(struct v4l2_subdev *sd)\n{\n\tstruct prp_priv *priv = sd_to_priv(sd);\n\tstruct imx_ic_priv *ic_priv = priv->ic_priv;\n\tint i, ret;": "static int prp_registered(struct v4l2_subdev *sd)\n{\n\tstruct prp_priv *priv = sd_to_priv(sd);\n\tstruct imx_ic_priv *ic_priv = priv->ic_priv;\n\tint i, ret;\n\tu32 code;\n\n\t/* set a default mbus format  */\n\timx_media_enum_ipu_formats(&code, 0, PIXFMT_SEL_YUV);\n\n\tfor (i = 0; i < PRPENCVF_NUM_PADS; i++) {\n\t\tret = imx_media_init_mbus_fmt(&priv->format_mbus[i],\n\t\t\t\t\t      IMX_MEDIA_DEF_PIX_WIDTH,\n\t\t\t\t\t      IMX_MEDIA_DEF_PIX_HEIGHT, code,\n\t\t\t\t\t      V4L2_FIELD_NONE, &priv->cc[i]);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\t/* init default frame interval */\n\tpriv->frame_interval.numerator = 1;\n\tpriv->frame_interval.denominator = 30;\n\n\tpriv->vdev = imx_media_capture_device_init(ic_priv->ipu_dev,\n\t\t\t\t\t\t   &ic_priv->sd,\n\t\t\t\t\t\t   PRPENCVF_SRC_PAD, true);\n\tif (IS_ERR(priv->vdev))\n\t\treturn PTR_ERR(priv->vdev);\n\n\tret = imx_media_capture_device_register(priv->vdev, 0);\n\tif (ret)\n\t\tgoto remove_vdev;\n\n\tret = prp_init_controls(priv);\n\tif (ret)\n\t\tgoto unreg_vdev;\n\n\treturn 0;\n\nunreg_vdev:\n\timx_media_capture_device_unregister(priv->vdev);\nremove_vdev:\n\timx_media_capture_device_remove(priv->vdev);\n\treturn ret;\n}",
        "static int sccnxp_set_baud(struct uart_port *port, int baud)\n{\n\tstruct sccnxp_port *s = dev_get_drvdata(port->dev);\n\tint div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;\n\tstruct sccnxp_chip *chip = s->chip;": "static int sccnxp_set_baud(struct uart_port *port, int baud)\n{\n\tstruct sccnxp_port *s = dev_get_drvdata(port->dev);\n\tint div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;\n\tstruct sccnxp_chip *chip = s->chip;\n\tu8 i, acr = 0, csr = 0, mr0 = 0;\n\n\t/* Find divisor to load to the timer preset registers */\n\tdiv_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);\n\tif ((div_std >= 2) && (div_std <= 0xffff)) {\n\t\tbestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);\n\t\tsccnxp_update_best_err(baud, bestbaud, &besterr);\n\t\tcsr = CSR_TIMER_MODE;\n\t\tsccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);\n\t\tsccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);\n\t\t/* Issue start timer/counter command */\n\t\tsccnxp_port_read(port, SCCNXP_START_COUNTER_REG);\n\t}\n\n\t/* Find best baud from table */\n\tfor (i = 0; baud_std[i].baud && besterr; i++) {\n\t\tif (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))\n\t\t\tcontinue;\n\t\tdiv_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);\n\t\ttmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);\n\t\tif (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {\n\t\t\tacr = baud_std[i].acr;\n\t\t\tcsr = baud_std[i].csr;\n\t\t\tmr0 = baud_std[i].mr0;\n\t\t\tbestbaud = tmp_baud;\n\t\t}\n\t}\n\n\tif (chip->flags & SCCNXP_HAVE_MR0) {\n\t\t/* Enable FIFO, set half level for TX */\n\t\tmr0 |= MR0_FIFO | MR0_TXLVL;\n\t\t/* Update MR0 */\n\t\tsccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);\n\t\tsccnxp_port_write(port, SCCNXP_MR_REG, mr0);\n\t}\n\n\tsccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);\n\tsccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);\n\n\tif (baud != bestbaud)\n\t\tdev_dbg(port->dev, \"Baudrate desired: %i, calculated: %i\\n\",\n\t\t\tbaud, bestbaud);\n\n\treturn bestbaud;\n}",
        "static void ioc3_start(struct ioc3_private *ip)\n{\n\tstruct ioc3_ethregs *regs = ip->regs;\n\tunsigned long ring;\n": "static void ioc3_start(struct ioc3_private *ip)\n{\n\tstruct ioc3_ethregs *regs = ip->regs;\n\tunsigned long ring;\n\n\t/* Now the rx ring base, consume & produce registers.  */\n\tring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC);\n\twritel(ring >> 32, &regs->erbr_h);\n\twritel(ring & 0xffffffff, &regs->erbr_l);\n\twritel(ip->rx_ci << 3, &regs->ercir);\n\twritel((ip->rx_pi << 3) | ERPIR_ARM, &regs->erpir);\n\n\tring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC);\n\n\tip->txqlen = 0;\t\t\t\t\t/* nothing queued  */\n\n\t/* Now the tx ring base, consume & produce registers.  */\n\twritel(ring >> 32, &regs->etbr_h);\n\twritel(ring & 0xffffffff, &regs->etbr_l);\n\twritel(ip->tx_pi << 7, &regs->etpir);\n\twritel(ip->tx_ci << 7, &regs->etcir);\n\treadl(&regs->etcir);\t\t\t\t/* Flush */\n\n\tip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |\n\t\t    EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;\n\twritel(ip->emcr, &regs->emcr);\n\twritel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |\n\t       EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |\n\t       EISR_TXEXPLICIT | EISR_TXMEMERR, &regs->eier);\n\treadl(&regs->eier);\n}",
        "static void usage(void)\n{\n\tif (is_clx_n_platform()) {\n\t\tfprintf(stderr, \"\\nThere is limited support of Intel Speed Select features on this platform.\\n\");\n\t\tfprintf(stderr, \"Everything is pre-configured using BIOS options, this tool can't enable any feature in the hardware.\\n\\n\");": "static void usage(void)\n{\n\tif (is_clx_n_platform()) {\n\t\tfprintf(stderr, \"\\nThere is limited support of Intel Speed Select features on this platform.\\n\");\n\t\tfprintf(stderr, \"Everything is pre-configured using BIOS options, this tool can't enable any feature in the hardware.\\n\\n\");\n\t}\n\n\tprintf(\"\\nUsage:\\n\");\n\tprintf(\"intel-speed-select [OPTIONS] FEATURE COMMAND COMMAND_ARGUMENTS\\n\");\n\tprintf(\"\\nUse this tool to enumerate and control the Intel Speed Select Technology features:\\n\");\n\tif (is_clx_n_platform())\n\t\tprintf(\"\\nFEATURE : [perf-profile|base-freq]\\n\");\n\telse\n\t\tprintf(\"\\nFEATURE : [perf-profile|base-freq|turbo-freq|core-power|turbo-mode]\\n\");\n\tprintf(\"\\nFor help on each feature, use -h|--help\\n\");\n\tprintf(\"\\tFor example:  intel-speed-select perf-profile -h\\n\");\n\n\tprintf(\"\\nFor additional help on each command for a feature, use --h|--help\\n\");\n\tprintf(\"\\tFor example:  intel-speed-select perf-profile get-lock-status -h\\n\");\n\tprintf(\"\\t\\t This will print help for the command \\\"get-lock-status\\\" for the feature \\\"perf-profile\\\"\\n\");\n\n\tprintf(\"\\nOPTIONS\\n\");\n\tprintf(\"\\t[-c|--cpu] : logical cpu number\\n\");\n\tprintf(\"\\t\\tDefault: Die scoped for all dies in the system with multiple dies/package\\n\");\n\tprintf(\"\\t\\t\\t Or Package scoped for all Packages when each package contains one die\\n\");\n\tprintf(\"\\t[-d|--debug] : Debug mode\\n\");\n\tprintf(\"\\t[-f|--format] : output format [json|text]. Default: text\\n\");\n\tprintf(\"\\t[-h|--help] : Print help\\n\");\n\tprintf(\"\\t[-i|--info] : Print platform information\\n\");\n\tprintf(\"\\t[-a|--all-cpus-online] : Force online every CPU in the system\\n\");\n\tprintf(\"\\t[-o|--out] : Output file\\n\");\n\tprintf(\"\\t\\t\\tDefault : stderr\\n\");\n\tprintf(\"\\t[-p|--pause] : Delay between two mail box commands in milliseconds\\n\");\n\tprintf(\"\\t[-r|--retry] : Retry count for mail box commands on failure, default 3\\n\");\n\tprintf(\"\\t[-v|--version] : Print version\\n\");\n\tprintf(\"\\t[-b|--oob : Start a daemon to process HFI events for perf profile change from Out of Band agent.\\n\");\n\tprintf(\"\\t[-n|--no-daemon : Don't run as daemon. By default --oob will turn on daemon mode\\n\");\n\tprintf(\"\\t[-w|--delay : Delay for reading config level state change in OOB poll mode.\\n\");\n\tprintf(\"\\nResult format\\n\");\n\tprintf(\"\\tResult display uses a common format for each command:\\n\");\n\tprintf(\"\\tResults are formatted in text/JSON with\\n\");\n\tprintf(\"\\t\\tPackage, Die, CPU, and command specific results.\\n\");\n\n\tprintf(\"\\nExamples\\n\");\n\tprintf(\"\\tTo get platform information:\\n\");\n\tprintf(\"\\t\\tintel-speed-select --info\\n\");\n\tprintf(\"\\tTo get full perf-profile information dump:\\n\");\n\tprintf(\"\\t\\tintel-speed-select perf-profile info\\n\");\n\tprintf(\"\\tTo get full base-freq information dump:\\n\");\n\tprintf(\"\\t\\tintel-speed-select base-freq info -l 0\\n\");\n\tif (!is_clx_n_platform()) {\n\t\tprintf(\"\\tTo get full turbo-freq information dump:\\n\");\n\t\tprintf(\"\\t\\tintel-speed-select turbo-freq info -l 0\\n\");\n\t}\n\texit(1);\n}",
        "static int decode_MOSDBackoff(const struct ceph_msg *msg, struct MOSDBackoff *m)\n{\n\tvoid *p = msg->front.iov_base;\n\tvoid *const end = p + msg->front.iov_len;\n\tu8 struct_v;": "static int decode_MOSDBackoff(const struct ceph_msg *msg, struct MOSDBackoff *m)\n{\n\tvoid *p = msg->front.iov_base;\n\tvoid *const end = p + msg->front.iov_len;\n\tu8 struct_v;\n\tu32 struct_len;\n\tint ret;\n\n\tret = ceph_start_decoding(&p, end, 1, \"spg_t\", &struct_v, &struct_len);\n\tif (ret)\n\t\treturn ret;\n\n\tret = ceph_decode_pgid(&p, end, &m->spgid.pgid);\n\tif (ret)\n\t\treturn ret;\n\n\tceph_decode_8_safe(&p, end, m->spgid.shard, e_inval);\n\tceph_decode_32_safe(&p, end, m->map_epoch, e_inval);\n\tceph_decode_8_safe(&p, end, m->op, e_inval);\n\tceph_decode_64_safe(&p, end, m->id, e_inval);\n\n\tm->begin = kzalloc(sizeof(*m->begin), GFP_NOIO);\n\tif (!m->begin)\n\t\treturn -ENOMEM;\n\n\tret = decode_hoid(&p, end, m->begin);\n\tif (ret) {\n\t\tfree_hoid(m->begin);\n\t\treturn ret;\n\t}\n\n\tm->end = kzalloc(sizeof(*m->end), GFP_NOIO);\n\tif (!m->end) {\n\t\tfree_hoid(m->begin);\n\t\treturn -ENOMEM;\n\t}\n\n\tret = decode_hoid(&p, end, m->end);\n\tif (ret) {\n\t\tfree_hoid(m->begin);\n\t\tfree_hoid(m->end);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n\ne_inval:\n\treturn -EINVAL;\n}",
        "static void test_lru_sanity1(int map_type, int map_flags, unsigned int tgt_free)\n{\n\tunsigned long long key, end_key, value[nr_cpus];\n\tint lru_map_fd, expected_map_fd;\n\tunsigned int batch_size;": "static void test_lru_sanity1(int map_type, int map_flags, unsigned int tgt_free)\n{\n\tunsigned long long key, end_key, value[nr_cpus];\n\tint lru_map_fd, expected_map_fd;\n\tunsigned int batch_size;\n\tunsigned int map_size;\n\tint next_cpu = 0;\n\n\tif (map_flags & BPF_F_NO_COMMON_LRU)\n\t\t/* This test is only applicable to common LRU list */\n\t\treturn;\n\n\tprintf(\"%s (map_type:%d map_flags:0x%X): \", __func__, map_type,\n\t       map_flags);\n\n\tassert(sched_next_online(0, &next_cpu) != -1);\n\n\tbatch_size = tgt_free / 2;\n\tassert(batch_size * 2 == tgt_free);\n\n\tmap_size = tgt_free + batch_size;\n\tlru_map_fd = create_map(map_type, map_flags, map_size);\n\tassert(lru_map_fd != -1);\n\n\texpected_map_fd = create_map(BPF_MAP_TYPE_HASH, 0, map_size);\n\tassert(expected_map_fd != -1);\n\n\tvalue[0] = 1234;\n\n\t/* Insert 1 to tgt_free (+tgt_free keys) */\n\tend_key = 1 + tgt_free;\n\tfor (key = 1; key < end_key; key++)\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\n\t/* Lookup 1 to tgt_free/2 */\n\tend_key = 1 + batch_size;\n\tfor (key = 1; key < end_key; key++) {\n\t\tassert(!bpf_map_lookup_elem_with_ref_bit(lru_map_fd, key, value));\n\t\tassert(!bpf_map_update_elem(expected_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t}\n\n\t/* Insert 1+tgt_free to 2*tgt_free\n\t * => 1+tgt_free/2 to LOCALFREE_TARGET will be\n\t * removed by LRU\n\t */\n\tkey = 1 + tgt_free;\n\tend_key = key + tgt_free;\n\tfor (; key < end_key; key++) {\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t\tassert(!bpf_map_update_elem(expected_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t}\n\n\tassert(map_equal(lru_map_fd, expected_map_fd));\n\n\tclose(expected_map_fd);\n\tclose(lru_map_fd);\n\n\tprintf(\"Pass\\n\");\n}",
        "static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])\n{\n\tu32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;\n\tu32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;\n\tunsigned long time_left;": "static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])\n{\n\tu32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;\n\tu32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;\n\tunsigned long time_left;\n\n\taxxia_i2c_set_addr(idev, &msgs[0]);\n\n\twritel(msgs[0].len, idev->base + MST_TX_XFER);\n\twritel(rlen, idev->base + MST_RX_XFER);\n\n\tidev->msg = &msgs[0];\n\tidev->msg_r = &msgs[1];\n\tidev->msg_xfrd = 0;\n\tidev->msg_xfrd_r = 0;\n\tidev->last = true;\n\taxxia_i2c_fill_tx_fifo(idev);\n\n\twritel(CMD_SEQUENCE, idev->base + MST_COMMAND);\n\n\treinit_completion(&idev->msg_complete);\n\ti2c_int_enable(idev, int_mask);\n\n\ttime_left = wait_for_completion_timeout(&idev->msg_complete,\n\t\t\t\t\t\tI2C_XFER_TIMEOUT);\n\n\tif (idev->msg_err == -ENXIO) {\n\t\tif (axxia_i2c_handle_seq_nak(idev))\n\t\t\taxxia_i2c_init(idev);\n\t} else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {\n\t\tdev_warn(idev->dev, \"busy after xfer\\n\");\n\t}\n\n\tif (time_left == 0) {\n\t\tidev->msg_err = -ETIMEDOUT;\n\t\ti2c_recover_bus(&idev->adapter);\n\t\taxxia_i2c_init(idev);\n\t}\n\n\tif (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)\n\t\taxxia_i2c_init(idev);\n\n\treturn idev->msg_err;\n}",
        "static unsigned int psp_get_capability(struct psp_device *psp)\n{\n\tunsigned int val = ioread32(psp->io_regs + psp->vdata->feature_reg);\n\n\t/*": "static unsigned int psp_get_capability(struct psp_device *psp)\n{\n\tunsigned int val = ioread32(psp->io_regs + psp->vdata->feature_reg);\n\n\t/*\n\t * Check for a access to the registers.  If this read returns\n\t * 0xffffffff, it's likely that the system is running a broken\n\t * BIOS which disallows access to the device. Stop here and\n\t * fail the PSP initialization (but not the load, as the CCP\n\t * could get properly initialized).\n\t */\n\tif (val == 0xffffffff) {\n\t\tdev_notice(psp->dev, \"psp: unable to access the device: you might be running a broken BIOS.\\n\");\n\t\treturn -ENODEV;\n\t}\n\tpsp->capability = val;\n\n\t/* Detect if TSME and SME are both enabled */\n\tif (psp->capability & PSP_CAPABILITY_PSP_SECURITY_REPORTING &&\n\t    psp->capability & (PSP_SECURITY_TSME_STATUS << PSP_CAPABILITY_PSP_SECURITY_OFFSET) &&\n\t    cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT))\n\t\tdev_notice(psp->dev, \"psp: Both TSME and SME are active, SME is unnecessary when TSME is active.\\n\");\n\n\treturn 0;\n}",
        "static int mspro_block_read_attributes(struct memstick_dev *card)\n{\n\tstruct mspro_block_data *msb = memstick_get_drvdata(card);\n\tstruct mspro_attribute *attr = NULL;\n\tstruct mspro_sys_attr *s_attr = NULL;": "static int mspro_block_read_attributes(struct memstick_dev *card)\n{\n\tstruct mspro_block_data *msb = memstick_get_drvdata(card);\n\tstruct mspro_attribute *attr = NULL;\n\tstruct mspro_sys_attr *s_attr = NULL;\n\tunsigned char *buffer = NULL;\n\tint cnt, rc, attr_count;\n\t/* While normally physical device offsets, represented here by\n\t * attr_offset and attr_len will be of large numeric types, we can be\n\t * sure, that attributes are close enough to the beginning of the\n\t * device, to save ourselves some trouble.\n\t */\n\tunsigned int addr, attr_offset = 0, attr_len = msb->page_size;\n\n\tattr = kmalloc(msb->page_size, GFP_KERNEL);\n\tif (!attr)\n\t\treturn -ENOMEM;\n\n\tsg_init_one(&msb->req_sg[0], attr, msb->page_size);\n\tmsb->seg_count = 1;\n\tmsb->current_seg = 0;\n\tmsb->current_page = 0;\n\tmsb->data_dir = READ;\n\tmsb->transfer_cmd = MSPRO_CMD_READ_ATRB;\n\n\tmsb->setup_transfer(card, attr_offset, attr_len);\n\n\tmemstick_new_req(card->host);\n\twait_for_completion(&card->mrq_complete);\n\tif (card->current_mrq.error) {\n\t\trc = card->current_mrq.error;\n\t\tgoto out_free_attr;\n\t}\n\n\tif (be16_to_cpu(attr->signature) != MSPRO_BLOCK_SIGNATURE) {\n\t\tprintk(KERN_ERR \"%s: unrecognized device signature %x\\n\",\n\t\t       dev_name(&card->dev), be16_to_cpu(attr->signature));\n\t\trc = -ENODEV;\n\t\tgoto out_free_attr;\n\t}\n\n\tif (attr->count > MSPRO_BLOCK_MAX_ATTRIBUTES) {\n\t\tprintk(KERN_WARNING \"%s: way too many attribute entries\\n\",\n\t\t       dev_name(&card->dev));\n\t\tattr_count = MSPRO_BLOCK_MAX_ATTRIBUTES;\n\t} else\n\t\tattr_count = attr->count;\n\n\tmsb->attr_group.attrs = kcalloc(attr_count + 1,\n\t\t\t\t\tsizeof(*msb->attr_group.attrs),\n\t\t\t\t\tGFP_KERNEL);\n\tif (!msb->attr_group.attrs) {\n\t\trc = -ENOMEM;\n\t\tgoto out_free_attr;\n\t}\n\tmsb->attr_group.name = \"media_attributes\";\n\n\tbuffer = kmemdup(attr, attr_len, GFP_KERNEL);\n\tif (!buffer) {\n\t\trc = -ENOMEM;\n\t\tgoto out_free_attr;\n\t}\n\n\tfor (cnt = 0; cnt < attr_count; ++cnt) {\n\t\ts_attr = kzalloc(sizeof(struct mspro_sys_attr), GFP_KERNEL);\n\t\tif (!s_attr) {\n\t\t\trc = -ENOMEM;\n\t\t\tgoto out_free_buffer;\n\t\t}\n\n\t\tmsb->attr_group.attrs[cnt] = &s_attr->dev_attr.attr;\n\t\taddr = be32_to_cpu(attr->entries[cnt].address);\n\t\ts_attr->size = be32_to_cpu(attr->entries[cnt].size);\n\t\tdev_dbg(&card->dev, \"adding attribute %d: id %x, address %x, \"\n\t\t\t\"size %zx\\n\", cnt, attr->entries[cnt].id, addr,\n\t\t\ts_attr->size);\n\t\ts_attr->id = attr->entries[cnt].id;\n\t\tif (mspro_block_attr_name(s_attr->id))\n\t\t\tsnprintf(s_attr->name, sizeof(s_attr->name), \"%s\",\n\t\t\t\t mspro_block_attr_name(attr->entries[cnt].id));\n\t\telse\n\t\t\tsnprintf(s_attr->name, sizeof(s_attr->name),\n\t\t\t\t \"attr_x%02x\", attr->entries[cnt].id);\n\n\t\tsysfs_attr_init(&s_attr->dev_attr.attr);\n\t\ts_attr->dev_attr.attr.name = s_attr->name;\n\t\ts_attr->dev_attr.attr.mode = S_IRUGO;\n\t\ts_attr->dev_attr.show = mspro_block_attr_show(s_attr->id);\n\n\t\tif (!s_attr->size)\n\t\t\tcontinue;\n\n\t\ts_attr->data = kmalloc(s_attr->size, GFP_KERNEL);\n\t\tif (!s_attr->data) {\n\t\t\trc = -ENOMEM;\n\t\t\tgoto out_free_buffer;\n\t\t}\n\n\t\tif (((addr / msb->page_size) == (attr_offset / msb->page_size))\n\t\t    && (((addr + s_attr->size - 1) / msb->page_size)\n\t\t\t== (attr_offset / msb->page_size))) {\n\t\t\tmemcpy(s_attr->data, buffer + addr % msb->page_size,\n\t\t\t       s_attr->size);\n\t\t\tcontinue;\n\t\t}\n\n\t\tattr_offset = (addr / msb->page_size) * msb->page_size;\n\n\t\tif ((attr_offset + attr_len) < (addr + s_attr->size)) {\n\t\t\tkfree(buffer);\n\t\t\tattr_len = (((addr + s_attr->size) / msb->page_size)\n\t\t\t\t    + 1 ) * msb->page_size - attr_offset;\n\t\t\tbuffer = kmalloc(attr_len, GFP_KERNEL);\n\t\t\tif (!buffer) {\n\t\t\t\trc = -ENOMEM;\n\t\t\t\tgoto out_free_attr;\n\t\t\t}\n\t\t}\n\n\t\tsg_init_one(&msb->req_sg[0], buffer, attr_len);\n\t\tmsb->seg_count = 1;\n\t\tmsb->current_seg = 0;\n\t\tmsb->current_page = 0;\n\t\tmsb->data_dir = READ;\n\t\tmsb->transfer_cmd = MSPRO_CMD_READ_ATRB;\n\n\t\tdev_dbg(&card->dev, \"reading attribute range %x, %x\\n\",\n\t\t\tattr_offset, attr_len);\n\n\t\tmsb->setup_transfer(card, attr_offset, attr_len);\n\t\tmemstick_new_req(card->host);\n\t\twait_for_completion(&card->mrq_complete);\n\t\tif (card->current_mrq.error) {\n\t\t\trc = card->current_mrq.error;\n\t\t\tgoto out_free_buffer;\n\t\t}\n\n\t\tmemcpy(s_attr->data, buffer + addr % msb->page_size,\n\t\t       s_attr->size);\n\t}\n\n\trc = 0;\nout_free_buffer:\n\tkfree(buffer);\nout_free_attr:\n\tkfree(attr);\n\treturn rc;\n}",
        "static bool tcp_fastopen_queue_check(struct sock *sk)\n{\n\tstruct fastopen_queue *fastopenq;\n\n\t/* Make sure the listener has enabled fastopen, and we don't": "static bool tcp_fastopen_queue_check(struct sock *sk)\n{\n\tstruct fastopen_queue *fastopenq;\n\n\t/* Make sure the listener has enabled fastopen, and we don't\n\t * exceed the max # of pending TFO requests allowed before trying\n\t * to validating the cookie in order to avoid burning CPU cycles\n\t * unnecessarily.\n\t *\n\t * XXX (TFO) - The implication of checking the max_qlen before\n\t * processing a cookie request is that clients can't differentiate\n\t * between qlen overflow causing Fast Open to be disabled\n\t * temporarily vs a server not supporting Fast Open at all.\n\t */\n\tfastopenq = &inet_csk(sk)->icsk_accept_queue.fastopenq;\n\tif (fastopenq->max_qlen == 0)\n\t\treturn false;\n\n\tif (fastopenq->qlen >= fastopenq->max_qlen) {\n\t\tstruct request_sock *req1;\n\t\tspin_lock(&fastopenq->lock);\n\t\treq1 = fastopenq->rskq_rst_head;\n\t\tif (!req1 || time_after(req1->rsk_timer.expires, jiffies)) {\n\t\t\t__NET_INC_STATS(sock_net(sk),\n\t\t\t\t\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW);\n\t\t\tspin_unlock(&fastopenq->lock);\n\t\t\treturn false;\n\t\t}\n\t\tfastopenq->rskq_rst_head = req1->dl_next;\n\t\tfastopenq->qlen--;\n\t\tspin_unlock(&fastopenq->lock);\n\t\treqsk_put(req1);\n\t}\n\treturn true;\n}",
        "static int ceu_hw_config(struct ceu_device *ceudev)\n{\n\tu32 camcr, cdocr, cfzsr, cdwdr, capwr;\n\tstruct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;\n\tstruct ceu_subdev *ceu_sd = ceudev->sd;": "static int ceu_hw_config(struct ceu_device *ceudev)\n{\n\tu32 camcr, cdocr, cfzsr, cdwdr, capwr;\n\tstruct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;\n\tstruct ceu_subdev *ceu_sd = ceudev->sd;\n\tstruct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;\n\tunsigned int mbus_flags = ceu_sd->mbus_flags;\n\n\t/* Start configuring CEU registers */\n\tceu_write(ceudev, CEU_CAIFR, 0);\n\tceu_write(ceudev, CEU_CFWCR, 0);\n\tceu_write(ceudev, CEU_CRCNTR, 0);\n\tceu_write(ceudev, CEU_CRCMPR, 0);\n\n\t/* Set the frame capture period for both image capture and data sync. */\n\tcapwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8;\n\n\t/*\n\t * Swap input data endianness by default.\n\t * In data fetch mode bytes are received in chunks of 8 bytes.\n\t * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first)\n\t * The data is however by default written to memory in reverse order:\n\t * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte)\n\t *\n\t * Use CEU_CDOCR[2:0] to swap data ordering.\n\t */\n\tcdocr = CEU_CDOCR_SWAP_ENDIANNESS;\n\n\t/*\n\t * Configure CAMCR and CDOCR:\n\t * match input components ordering with memory output format and\n\t * handle downsampling to YUV420.\n\t *\n\t * If the memory output planar format is 'swapped' (Cr before Cb) and\n\t * input format is not, use the swapped version of CAMCR.DTARY.\n\t *\n\t * If the memory output planar format is not 'swapped' (Cb before Cr)\n\t * and input format is, use the swapped version of CAMCR.DTARY.\n\t *\n\t * CEU by default downsample to planar YUV420 (CDCOR[4] = 0).\n\t * If output is planar YUV422 set CDOCR[4] = 1\n\t *\n\t * No downsample for data fetch sync mode.\n\t */\n\tswitch (pix->pixelformat) {\n\t/* Data fetch sync mode */\n\tcase V4L2_PIX_FMT_YUYV:\n\tcase V4L2_PIX_FMT_YVYU:\n\tcase V4L2_PIX_FMT_UYVY:\n\tcase V4L2_PIX_FMT_VYUY:\n\t\tcamcr\t= CEU_CAMCR_JPEG;\n\t\tcdocr\t|= CEU_CDOCR_NO_DOWSAMPLE;\n\t\tcfzsr\t= (pix->height << 16) | pix->width;\n\t\tcdwdr\t= pix->plane_fmt[0].bytesperline;\n\t\tbreak;\n\n\t/* Non-swapped planar image capture mode. */\n\tcase V4L2_PIX_FMT_NV16:\n\t\tcdocr\t|= CEU_CDOCR_NO_DOWSAMPLE;\n\t\tfallthrough;\n\tcase V4L2_PIX_FMT_NV12:\n\t\tif (mbus_fmt->swapped)\n\t\t\tcamcr = mbus_fmt->fmt_order_swap;\n\t\telse\n\t\t\tcamcr = mbus_fmt->fmt_order;\n\n\t\tcfzsr\t= (pix->height << 16) | pix->width;\n\t\tcdwdr\t= pix->width;\n\t\tbreak;\n\n\t/* Swapped planar image capture mode. */\n\tcase V4L2_PIX_FMT_NV61:\n\t\tcdocr\t|= CEU_CDOCR_NO_DOWSAMPLE;\n\t\tfallthrough;\n\tcase V4L2_PIX_FMT_NV21:\n\t\tif (mbus_fmt->swapped)\n\t\t\tcamcr = mbus_fmt->fmt_order;\n\t\telse\n\t\t\tcamcr = mbus_fmt->fmt_order_swap;\n\n\t\tcfzsr\t= (pix->height << 16) | pix->width;\n\t\tcdwdr\t= pix->width;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tcamcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0;\n\tcamcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0;\n\n\t/* TODO: handle 16 bit bus width with DTIF bit in CAMCR */\n\tceu_write(ceudev, CEU_CAMCR, camcr);\n\tceu_write(ceudev, CEU_CDOCR, cdocr);\n\tceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256);\n\n\t/*\n\t * TODO: make CAMOR offsets configurable.\n\t * CAMOR wants to know the number of blanks between a VS/HS signal\n\t * and valid data. This value should actually come from the sensor...\n\t */\n\tceu_write(ceudev, CEU_CAMOR, 0);\n\n\t/* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */\n\tceu_write(ceudev, CEU_CAPWR, capwr);\n\tceu_write(ceudev, CEU_CFSZR, cfzsr);\n\tceu_write(ceudev, CEU_CDWDR, cdwdr);\n\n\treturn 0;\n}",
        "static int super_90_validate(struct mddev *mddev, struct md_rdev *rdev)\n{\n\tmdp_disk_t *desc;\n\tmdp_super_t *sb = page_address(rdev->sb_page);\n\t__u64 ev1 = md_event(sb);": "static int super_90_validate(struct mddev *mddev, struct md_rdev *rdev)\n{\n\tmdp_disk_t *desc;\n\tmdp_super_t *sb = page_address(rdev->sb_page);\n\t__u64 ev1 = md_event(sb);\n\n\trdev->raid_disk = -1;\n\tclear_bit(Faulty, &rdev->flags);\n\tclear_bit(In_sync, &rdev->flags);\n\tclear_bit(Bitmap_sync, &rdev->flags);\n\tclear_bit(WriteMostly, &rdev->flags);\n\n\tif (mddev->raid_disks == 0) {\n\t\tmddev->major_version = 0;\n\t\tmddev->minor_version = sb->minor_version;\n\t\tmddev->patch_version = sb->patch_version;\n\t\tmddev->external = 0;\n\t\tmddev->chunk_sectors = sb->chunk_size >> 9;\n\t\tmddev->ctime = sb->ctime;\n\t\tmddev->utime = sb->utime;\n\t\tmddev->level = sb->level;\n\t\tmddev->clevel[0] = 0;\n\t\tmddev->layout = sb->layout;\n\t\tmddev->raid_disks = sb->raid_disks;\n\t\tmddev->dev_sectors = ((sector_t)sb->size) * 2;\n\t\tmddev->events = ev1;\n\t\tmddev->bitmap_info.offset = 0;\n\t\tmddev->bitmap_info.space = 0;\n\t\t/* bitmap can use 60 K after the 4K superblocks */\n\t\tmddev->bitmap_info.default_offset = MD_SB_BYTES >> 9;\n\t\tmddev->bitmap_info.default_space = 64*2 - (MD_SB_BYTES >> 9);\n\t\tmddev->reshape_backwards = 0;\n\n\t\tif (mddev->minor_version >= 91) {\n\t\t\tmddev->reshape_position = sb->reshape_position;\n\t\t\tmddev->delta_disks = sb->delta_disks;\n\t\t\tmddev->new_level = sb->new_level;\n\t\t\tmddev->new_layout = sb->new_layout;\n\t\t\tmddev->new_chunk_sectors = sb->new_chunk >> 9;\n\t\t\tif (mddev->delta_disks < 0)\n\t\t\t\tmddev->reshape_backwards = 1;\n\t\t} else {\n\t\t\tmddev->reshape_position = MaxSector;\n\t\t\tmddev->delta_disks = 0;\n\t\t\tmddev->new_level = mddev->level;\n\t\t\tmddev->new_layout = mddev->layout;\n\t\t\tmddev->new_chunk_sectors = mddev->chunk_sectors;\n\t\t}\n\t\tif (mddev->level == 0)\n\t\t\tmddev->layout = -1;\n\n\t\tif (sb->state & (1<<MD_SB_CLEAN))\n\t\t\tmddev->recovery_cp = MaxSector;\n\t\telse {\n\t\t\tif (sb->events_hi == sb->cp_events_hi &&\n\t\t\t\tsb->events_lo == sb->cp_events_lo) {\n\t\t\t\tmddev->recovery_cp = sb->recovery_cp;\n\t\t\t} else\n\t\t\t\tmddev->recovery_cp = 0;\n\t\t}\n\n\t\tmemcpy(mddev->uuid+0, &sb->set_uuid0, 4);\n\t\tmemcpy(mddev->uuid+4, &sb->set_uuid1, 4);\n\t\tmemcpy(mddev->uuid+8, &sb->set_uuid2, 4);\n\t\tmemcpy(mddev->uuid+12,&sb->set_uuid3, 4);\n\n\t\tmddev->max_disks = MD_SB_DISKS;\n\n\t\tif (sb->state & (1<<MD_SB_BITMAP_PRESENT) &&\n\t\t    mddev->bitmap_info.file == NULL) {\n\t\t\tmddev->bitmap_info.offset =\n\t\t\t\tmddev->bitmap_info.default_offset;\n\t\t\tmddev->bitmap_info.space =\n\t\t\t\tmddev->bitmap_info.default_space;\n\t\t}\n\n\t} else if (mddev->pers == NULL) {\n\t\t/* Insist on good event counter while assembling, except\n\t\t * for spares (which don't need an event count) */\n\t\t++ev1;\n\t\tif (sb->disks[rdev->desc_nr].state & (\n\t\t\t    (1<<MD_DISK_SYNC) | (1 << MD_DISK_ACTIVE)))\n\t\t\tif (ev1 < mddev->events)\n\t\t\t\treturn -EINVAL;\n\t} else if (mddev->bitmap) {\n\t\t/* if adding to array with a bitmap, then we can accept an\n\t\t * older device ... but not too old.\n\t\t */\n\t\tif (ev1 < mddev->bitmap->events_cleared)\n\t\t\treturn 0;\n\t\tif (ev1 < mddev->events)\n\t\t\tset_bit(Bitmap_sync, &rdev->flags);\n\t} else {\n\t\tif (ev1 < mddev->events)\n\t\t\t/* just a hot-add of a new device, leave raid_disk at -1 */\n\t\t\treturn 0;\n\t}\n\n\tif (mddev->level != LEVEL_MULTIPATH) {\n\t\tdesc = sb->disks + rdev->desc_nr;\n\n\t\tif (desc->state & (1<<MD_DISK_FAULTY))\n\t\t\tset_bit(Faulty, &rdev->flags);\n\t\telse if (desc->state & (1<<MD_DISK_SYNC) /* &&\n\t\t\t    desc->raid_disk < mddev->raid_disks */) {\n\t\t\tset_bit(In_sync, &rdev->flags);\n\t\t\trdev->raid_disk = desc->raid_disk;\n\t\t\trdev->saved_raid_disk = desc->raid_disk;\n\t\t} else if (desc->state & (1<<MD_DISK_ACTIVE)) {\n\t\t\t/* active but not in sync implies recovery up to\n\t\t\t * reshape position.  We don't know exactly where\n\t\t\t * that is, so set to zero for now */\n\t\t\tif (mddev->minor_version >= 91) {\n\t\t\t\trdev->recovery_offset = 0;\n\t\t\t\trdev->raid_disk = desc->raid_disk;\n\t\t\t}\n\t\t}\n\t\tif (desc->state & (1<<MD_DISK_WRITEMOSTLY))\n\t\t\tset_bit(WriteMostly, &rdev->flags);\n\t\tif (desc->state & (1<<MD_DISK_FAILFAST))\n\t\t\tset_bit(FailFast, &rdev->flags);\n\t} else /* MULTIPATH are always insync */\n\t\tset_bit(In_sync, &rdev->flags);\n\treturn 0;\n}",
        "static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)\n{\n\tu64 cfg, idx, fidx = 0;\n\n\t/* Get max HW supported format indices */": "static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)\n{\n\tu64 cfg, idx, fidx = 0;\n\n\t/* Get max HW supported format indices */\n\tcfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF;\n\tnix_hw->lso.total = cfg;\n\n\t/* Enable LSO */\n\tcfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG);\n\t/* For TSO, set first and middle segment flags to\n\t * mask out PSH, RST & FIN flags in TCP packet\n\t */\n\tcfg &= ~((0xFFFFULL << 32) | (0xFFFFULL << 16));\n\tcfg |= (0xFFF2ULL << 32) | (0xFFF2ULL << 16);\n\trvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63));\n\n\t/* Setup default static LSO formats\n\t *\n\t * Configure format fields for TCPv4 segmentation offload\n\t */\n\tidx = NIX_LSO_FORMAT_IDX_TSOV4;\n\tnix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx);\n\tnix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx);\n\n\t/* Set rest of the fields to NOP */\n\tfor (; fidx < 8; fidx++) {\n\t\trvu_write64(rvu, blkaddr,\n\t\t\t    NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL);\n\t}\n\tnix_hw->lso.in_use++;\n\n\t/* Configure format fields for TCPv6 segmentation offload */\n\tidx = NIX_LSO_FORMAT_IDX_TSOV6;\n\tfidx = 0;\n\tnix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx);\n\tnix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx);\n\n\t/* Set rest of the fields to NOP */\n\tfor (; fidx < 8; fidx++) {\n\t\trvu_write64(rvu, blkaddr,\n\t\t\t    NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL);\n\t}\n\tnix_hw->lso.in_use++;\n}",
        "static void linger_map_check_cb(struct ceph_mon_generic_request *greq)\n{\n\tstruct ceph_osd_client *osdc = &greq->monc->client->osdc;\n\tstruct ceph_osd_linger_request *lreq;\n\tu64 linger_id = greq->private_data;": "static void linger_map_check_cb(struct ceph_mon_generic_request *greq)\n{\n\tstruct ceph_osd_client *osdc = &greq->monc->client->osdc;\n\tstruct ceph_osd_linger_request *lreq;\n\tu64 linger_id = greq->private_data;\n\n\tWARN_ON(greq->result || !greq->u.newest);\n\n\tdown_write(&osdc->lock);\n\tlreq = lookup_linger_mc(&osdc->linger_map_checks, linger_id);\n\tif (!lreq) {\n\t\tdout(\"%s linger_id %llu dne\\n\", __func__, linger_id);\n\t\tgoto out_unlock;\n\t}\n\n\tdout(\"%s lreq %p linger_id %llu map_dne_bound %u newest %llu\\n\",\n\t     __func__, lreq, lreq->linger_id, lreq->map_dne_bound,\n\t     greq->u.newest);\n\tif (!lreq->map_dne_bound)\n\t\tlreq->map_dne_bound = greq->u.newest;\n\terase_linger_mc(&osdc->linger_map_checks, lreq);\n\tcheck_linger_pool_dne(lreq);\n\n\tlinger_put(lreq);\nout_unlock:\n\tup_write(&osdc->lock);\n}",
        "static void t7xx_dpmaif_irq_cb(struct dpmaif_isr_para *isr_para)\n{\n\tstruct dpmaif_ctrl *dpmaif_ctrl = isr_para->dpmaif_ctrl;\n\tstruct dpmaif_hw_intr_st_para intr_status;\n\tstruct device *dev = dpmaif_ctrl->dev;": "static void t7xx_dpmaif_irq_cb(struct dpmaif_isr_para *isr_para)\n{\n\tstruct dpmaif_ctrl *dpmaif_ctrl = isr_para->dpmaif_ctrl;\n\tstruct dpmaif_hw_intr_st_para intr_status;\n\tstruct device *dev = dpmaif_ctrl->dev;\n\tstruct dpmaif_hw_info *hw_info;\n\tint i;\n\n\tmemset(&intr_status, 0, sizeof(intr_status));\n\thw_info = &dpmaif_ctrl->hw_info;\n\n\tif (t7xx_dpmaif_hw_get_intr_cnt(hw_info, &intr_status, isr_para->dlq_id) < 0) {\n\t\tdev_err(dev, \"Failed to get HW interrupt count\\n\");\n\t\treturn;\n\t}\n\n\tt7xx_pcie_mac_clear_int_status(dpmaif_ctrl->t7xx_dev, isr_para->pcie_int);\n\n\tfor (i = 0; i < intr_status.intr_cnt; i++) {\n\t\tswitch (intr_status.intr_types[i]) {\n\t\tcase DPF_INTR_UL_DONE:\n\t\t\tt7xx_dpmaif_irq_tx_done(dpmaif_ctrl, intr_status.intr_queues[i]);\n\t\t\tbreak;\n\n\t\tcase DPF_INTR_UL_DRB_EMPTY:\n\t\tcase DPF_INTR_UL_MD_NOTREADY:\n\t\tcase DPF_INTR_UL_MD_PWR_NOTREADY:\n\t\t\t/* No need to log an error for these */\n\t\t\tbreak;\n\n\t\tcase DPF_INTR_DL_BATCNT_LEN_ERR:\n\t\t\tdev_err_ratelimited(dev, \"DL interrupt: packet BAT count length error\\n\");\n\t\t\tt7xx_dpmaif_dl_unmask_batcnt_len_err_intr(hw_info);\n\t\t\tbreak;\n\n\t\tcase DPF_INTR_DL_PITCNT_LEN_ERR:\n\t\t\tdev_err_ratelimited(dev, \"DL interrupt: PIT count length error\\n\");\n\t\t\tt7xx_dpmaif_dl_unmask_pitcnt_len_err_intr(hw_info);\n\t\t\tbreak;\n\n\t\tcase DPF_INTR_DL_Q0_PITCNT_LEN_ERR:\n\t\t\tdev_err_ratelimited(dev, \"DL interrupt: DLQ0 PIT count length error\\n\");\n\t\t\tt7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(hw_info, DPF_RX_QNO_DFT);\n\t\t\tbreak;\n\n\t\tcase DPF_INTR_DL_Q1_PITCNT_LEN_ERR:\n\t\t\tdev_err_ratelimited(dev, \"DL interrupt: DLQ1 PIT count length error\\n\");\n\t\t\tt7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(hw_info, DPF_RX_QNO1);\n\t\t\tbreak;\n\n\t\tcase DPF_INTR_DL_DONE:\n\t\tcase DPF_INTR_DL_Q0_DONE:\n\t\tcase DPF_INTR_DL_Q1_DONE:\n\t\t\tt7xx_dpmaif_irq_rx_done(dpmaif_ctrl, intr_status.intr_queues[i]);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tdev_err_ratelimited(dev, \"DL interrupt error: unknown type : %d\\n\",\n\t\t\t\t\t    intr_status.intr_types[i]);\n\t\t}\n\t}\n}",
        "static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)\n{\n\tstruct dw_pcie *pci = &pcie->pci;\n\tu32 val, offset, i;\n": "static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)\n{\n\tstruct dw_pcie *pci = &pcie->pci;\n\tu32 val, offset, i;\n\n\t/* Program init preset */\n\tfor (i = 0; i < pcie->num_lanes; i++) {\n\t\tval = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));\n\t\tval &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;\n\t\tval |= GEN3_GEN4_EQ_PRESET_INIT;\n\t\tval &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;\n\t\tval |= (GEN3_GEN4_EQ_PRESET_INIT <<\n\t\t\t   CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);\n\t\tdw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);\n\n\t\toffset = dw_pcie_find_ext_capability(pci,\n\t\t\t\t\t\t     PCI_EXT_CAP_ID_PL_16GT) +\n\t\t\t\tPCI_PL_16GT_LE_CTRL;\n\t\tval = dw_pcie_readb_dbi(pci, offset + i);\n\t\tval &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;\n\t\tval |= GEN3_GEN4_EQ_PRESET_INIT;\n\t\tval &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;\n\t\tval |= (GEN3_GEN4_EQ_PRESET_INIT <<\n\t\t\tPCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);\n\t\tdw_pcie_writeb_dbi(pci, offset + i, val);\n\t}\n\n\tval = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);\n\tval &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;\n\tdw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);\n\n\tval = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);\n\tval &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;\n\tval |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);\n\tval &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;\n\tdw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);\n\n\tval = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);\n\tval &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;\n\tval |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);\n\tdw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);\n\n\tval = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);\n\tval &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;\n\tval |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);\n\tval &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;\n\tdw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);\n\n\tval = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);\n\tval &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;\n\tdw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);\n}",
        "static int __maybe_unused trace_test_buffer(struct array_buffer *buf, unsigned long *count)\n{\n\tunsigned long flags, cnt = 0;\n\tint cpu, ret = 0;\n": "static int __maybe_unused trace_test_buffer(struct array_buffer *buf, unsigned long *count)\n{\n\tunsigned long flags, cnt = 0;\n\tint cpu, ret = 0;\n\n\t/* Don't allow flipping of max traces now */\n\tlocal_irq_save(flags);\n\tarch_spin_lock(&buf->tr->max_lock);\n\n\tcnt = ring_buffer_entries(buf->buffer);\n\n\t/*\n\t * The trace_test_buffer_cpu runs a while loop to consume all data.\n\t * If the calling tracer is broken, and is constantly filling\n\t * the buffer, this will run forever, and hard lock the box.\n\t * We disable the ring buffer while we do this test to prevent\n\t * a hard lock up.\n\t */\n\ttracing_off();\n\tfor_each_possible_cpu(cpu) {\n\t\tret = trace_test_buffer_cpu(buf, cpu);\n\t\tif (ret)\n\t\t\tbreak;\n\t}\n\ttracing_on();\n\tarch_spin_unlock(&buf->tr->max_lock);\n\tlocal_irq_restore(flags);\n\n\tif (count)\n\t\t*count = cnt;\n\n\treturn ret;\n}",
        "static int bnx2x_init_hw_func(struct bnx2x *bp)\n{\n\tint port = BP_PORT(bp);\n\tint func = BP_FUNC(bp);\n\tint init_phase = PHASE_PF0 + func;": "static int bnx2x_init_hw_func(struct bnx2x *bp)\n{\n\tint port = BP_PORT(bp);\n\tint func = BP_FUNC(bp);\n\tint init_phase = PHASE_PF0 + func;\n\tstruct bnx2x_ilt *ilt = BP_ILT(bp);\n\tu16 cdu_ilt_start;\n\tu32 addr, val;\n\tu32 main_mem_base, main_mem_size, main_mem_prty_clr;\n\tint i, main_mem_width, rc;\n\n\tDP(NETIF_MSG_HW, \"starting func init  func %d\\n\", func);\n\n\t/* FLR cleanup - hmmm */\n\tif (!CHIP_IS_E1x(bp)) {\n\t\trc = bnx2x_pf_flr_clnup(bp);\n\t\tif (rc) {\n\t\t\tbnx2x_fw_dump(bp);\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\t/* set MSI reconfigure capability */\n\tif (bp->common.int_block == INT_BLOCK_HC) {\n\t\taddr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);\n\t\tval = REG_RD(bp, addr);\n\t\tval |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;\n\t\tREG_WR(bp, addr, val);\n\t}\n\n\tbnx2x_init_block(bp, BLOCK_PXP, init_phase);\n\tbnx2x_init_block(bp, BLOCK_PXP2, init_phase);\n\n\tilt = BP_ILT(bp);\n\tcdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;\n\n\tif (IS_SRIOV(bp))\n\t\tcdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;\n\tcdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);\n\n\t/* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes\n\t * those of the VFs, so start line should be reset\n\t */\n\tcdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;\n\tfor (i = 0; i < L2_ILT_LINES(bp); i++) {\n\t\tilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;\n\t\tilt->lines[cdu_ilt_start + i].page_mapping =\n\t\t\tbp->context[i].cxt_mapping;\n\t\tilt->lines[cdu_ilt_start + i].size = bp->context[i].size;\n\t}\n\n\tbnx2x_ilt_init_op(bp, INITOP_SET);\n\n\tif (!CONFIGURE_NIC_MODE(bp)) {\n\t\tbnx2x_init_searcher(bp);\n\t\tREG_WR(bp, PRS_REG_NIC_MODE, 0);\n\t\tDP(NETIF_MSG_IFUP, \"NIC MODE disabled\\n\");\n\t} else {\n\t\t/* Set NIC mode */\n\t\tREG_WR(bp, PRS_REG_NIC_MODE, 1);\n\t\tDP(NETIF_MSG_IFUP, \"NIC MODE configured\\n\");\n\t}\n\n\tif (!CHIP_IS_E1x(bp)) {\n\t\tu32 pf_conf = IGU_PF_CONF_FUNC_EN;\n\n\t\t/* Turn on a single ISR mode in IGU if driver is going to use\n\t\t * INT#x or MSI\n\t\t */\n\t\tif (!(bp->flags & USING_MSIX_FLAG))\n\t\t\tpf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;\n\t\t/*\n\t\t * Timers workaround bug: function init part.\n\t\t * Need to wait 20msec after initializing ILT,\n\t\t * needed to make sure there are no requests in\n\t\t * one of the PXP internal queues with \"old\" ILT addresses\n\t\t */\n\t\tmsleep(20);\n\t\t/*\n\t\t * Master enable - Due to WB DMAE writes performed before this\n\t\t * register is re-initialized as part of the regular function\n\t\t * init\n\t\t */\n\t\tREG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);\n\t\t/* Enable the function in IGU */\n\t\tREG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);\n\t}\n\n\tbp->dmae_ready = 1;\n\n\tbnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);\n\n\tbnx2x_clean_pglue_errors(bp);\n\n\tbnx2x_init_block(bp, BLOCK_ATC, init_phase);\n\tbnx2x_init_block(bp, BLOCK_DMAE, init_phase);\n\tbnx2x_init_block(bp, BLOCK_NIG, init_phase);\n\tbnx2x_init_block(bp, BLOCK_SRC, init_phase);\n\tbnx2x_init_block(bp, BLOCK_MISC, init_phase);\n\tbnx2x_init_block(bp, BLOCK_TCM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_UCM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_CCM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_XCM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_TSEM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_USEM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_CSEM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_XSEM, init_phase);\n\n\tif (!CHIP_IS_E1x(bp))\n\t\tREG_WR(bp, QM_REG_PF_EN, 1);\n\n\tif (!CHIP_IS_E1x(bp)) {\n\t\tREG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t\tREG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t\tREG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t\tREG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t}\n\tbnx2x_init_block(bp, BLOCK_QM, init_phase);\n\n\tbnx2x_init_block(bp, BLOCK_TM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_DORQ, init_phase);\n\tREG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */\n\n\tbnx2x_iov_init_dq(bp);\n\n\tbnx2x_init_block(bp, BLOCK_BRB1, init_phase);\n\tbnx2x_init_block(bp, BLOCK_PRS, init_phase);\n\tbnx2x_init_block(bp, BLOCK_TSDM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_CSDM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_USDM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_XSDM, init_phase);\n\tbnx2x_init_block(bp, BLOCK_UPB, init_phase);\n\tbnx2x_init_block(bp, BLOCK_XPB, init_phase);\n\tbnx2x_init_block(bp, BLOCK_PBF, init_phase);\n\tif (!CHIP_IS_E1x(bp))\n\t\tREG_WR(bp, PBF_REG_DISABLE_PF, 0);\n\n\tbnx2x_init_block(bp, BLOCK_CDU, init_phase);\n\n\tbnx2x_init_block(bp, BLOCK_CFC, init_phase);\n\n\tif (!CHIP_IS_E1x(bp))\n\t\tREG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);\n\n\tif (IS_MF(bp)) {\n\t\tif (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {\n\t\t\tREG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);\n\t\t\tREG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,\n\t\t\t       bp->mf_ov);\n\t\t}\n\t}\n\n\tbnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);\n\n\t/* HC init per function */\n\tif (bp->common.int_block == INT_BLOCK_HC) {\n\t\tif (CHIP_IS_E1H(bp)) {\n\t\t\tREG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);\n\n\t\t\tREG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);\n\t\t\tREG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);\n\t\t}\n\t\tbnx2x_init_block(bp, BLOCK_HC, init_phase);\n\n\t} else {\n\t\tint num_segs, sb_idx, prod_offset;\n\n\t\tREG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);\n\n\t\tif (!CHIP_IS_E1x(bp)) {\n\t\t\tREG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);\n\t\t\tREG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);\n\t\t}\n\n\t\tbnx2x_init_block(bp, BLOCK_IGU, init_phase);\n\n\t\tif (!CHIP_IS_E1x(bp)) {\n\t\t\tint dsb_idx = 0;\n\t\t\t/**\n\t\t\t * Producer memory:\n\t\t\t * E2 mode: address 0-135 match to the mapping memory;\n\t\t\t * 136 - PF0 default prod; 137 - PF1 default prod;\n\t\t\t * 138 - PF2 default prod; 139 - PF3 default prod;\n\t\t\t * 140 - PF0 attn prod;    141 - PF1 attn prod;\n\t\t\t * 142 - PF2 attn prod;    143 - PF3 attn prod;\n\t\t\t * 144-147 reserved.\n\t\t\t *\n\t\t\t * E1.5 mode - In backward compatible mode;\n\t\t\t * for non default SB; each even line in the memory\n\t\t\t * holds the U producer and each odd line hold\n\t\t\t * the C producer. The first 128 producers are for\n\t\t\t * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20\n\t\t\t * producers are for the DSB for each PF.\n\t\t\t * Each PF has five segments: (the order inside each\n\t\t\t * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;\n\t\t\t * 132-135 C prods; 136-139 X prods; 140-143 T prods;\n\t\t\t * 144-147 attn prods;\n\t\t\t */\n\t\t\t/* non-default-status-blocks */\n\t\t\tnum_segs = CHIP_INT_MODE_IS_BC(bp) ?\n\t\t\t\tIGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;\n\t\t\tfor (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {\n\t\t\t\tprod_offset = (bp->igu_base_sb + sb_idx) *\n\t\t\t\t\tnum_segs;\n\n\t\t\t\tfor (i = 0; i < num_segs; i++) {\n\t\t\t\t\taddr = IGU_REG_PROD_CONS_MEMORY +\n\t\t\t\t\t\t\t(prod_offset + i) * 4;\n\t\t\t\t\tREG_WR(bp, addr, 0);\n\t\t\t\t}\n\t\t\t\t/* send consumer update with value 0 */\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,\n\t\t\t\t\t     USTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_igu_clear_sb(bp,\n\t\t\t\t\t\t   bp->igu_base_sb + sb_idx);\n\t\t\t}\n\n\t\t\t/* default-status-blocks */\n\t\t\tnum_segs = CHIP_INT_MODE_IS_BC(bp) ?\n\t\t\t\tIGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;\n\n\t\t\tif (CHIP_MODE_IS_4_PORT(bp))\n\t\t\t\tdsb_idx = BP_FUNC(bp);\n\t\t\telse\n\t\t\t\tdsb_idx = BP_VN(bp);\n\n\t\t\tprod_offset = (CHIP_INT_MODE_IS_BC(bp) ?\n\t\t\t\t       IGU_BC_BASE_DSB_PROD + dsb_idx :\n\t\t\t\t       IGU_NORM_BASE_DSB_PROD + dsb_idx);\n\n\t\t\t/*\n\t\t\t * igu prods come in chunks of E1HVN_MAX (4) -\n\t\t\t * does not matters what is the current chip mode\n\t\t\t */\n\t\t\tfor (i = 0; i < (num_segs * E1HVN_MAX);\n\t\t\t     i += E1HVN_MAX) {\n\t\t\t\taddr = IGU_REG_PROD_CONS_MEMORY +\n\t\t\t\t\t\t\t(prod_offset + i)*4;\n\t\t\t\tREG_WR(bp, addr, 0);\n\t\t\t}\n\t\t\t/* send consumer update with 0 */\n\t\t\tif (CHIP_INT_MODE_IS_BC(bp)) {\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     USTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     CSTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     XSTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     TSTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     ATTENTION_ID, 0, IGU_INT_NOP, 1);\n\t\t\t} else {\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     USTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(bp, bp->igu_dsb_id,\n\t\t\t\t\t     ATTENTION_ID, 0, IGU_INT_NOP, 1);\n\t\t\t}\n\t\t\tbnx2x_igu_clear_sb(bp, bp->igu_dsb_id);\n\n\t\t\t/* !!! These should become driver const once\n\t\t\t   rf-tool supports split-68 const */\n\t\t\tREG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);\n\t\t\tREG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);\n\t\t\tREG_WR(bp, IGU_REG_SB_MASK_LSB, 0);\n\t\t\tREG_WR(bp, IGU_REG_SB_MASK_MSB, 0);\n\t\t\tREG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);\n\t\t\tREG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);\n\t\t}\n\t}\n\n\t/* Reset PCIE errors for debug */\n\tREG_WR(bp, 0x2114, 0xffffffff);\n\tREG_WR(bp, 0x2120, 0xffffffff);\n\n\tif (CHIP_IS_E1x(bp)) {\n\t\tmain_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/\n\t\tmain_mem_base = HC_REG_MAIN_MEMORY +\n\t\t\t\tBP_PORT(bp) * (main_mem_size * 4);\n\t\tmain_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;\n\t\tmain_mem_width = 8;\n\n\t\tval = REG_RD(bp, main_mem_prty_clr);\n\t\tif (val)\n\t\t\tDP(NETIF_MSG_HW,\n\t\t\t   \"Hmmm... Parity errors in HC block during function init (0x%x)!\\n\",\n\t\t\t   val);\n\n\t\t/* Clear \"false\" parity errors in MSI-X table */\n\t\tfor (i = main_mem_base;\n\t\t     i < main_mem_base + main_mem_size * 4;\n\t\t     i += main_mem_width) {\n\t\t\tbnx2x_read_dmae(bp, i, main_mem_width / 4);\n\t\t\tbnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),\n\t\t\t\t\t i, main_mem_width / 4);\n\t\t}\n\t\t/* Clear HC parity attention */\n\t\tREG_RD(bp, main_mem_prty_clr);\n\t}\n\n#ifdef BNX2X_STOP_ON_ERROR\n\t/* Enable STORMs SP logging */\n\tREG_WR8(bp, BAR_USTRORM_INTMEM +\n\t       USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);\n\tREG_WR8(bp, BAR_TSTRORM_INTMEM +\n\t       TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);\n\tREG_WR8(bp, BAR_CSTRORM_INTMEM +\n\t       CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);\n\tREG_WR8(bp, BAR_XSTRORM_INTMEM +\n\t       XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);\n#endif\n\n\tbnx2x_phy_probe(&bp->link_params);\n\n\treturn 0;\n}",
        "static void freeary(struct ipc_namespace *ns, struct kern_ipc_perm *ipcp)\n{\n\tstruct sem_undo *un, *tu;\n\tstruct sem_queue *q, *tq;\n\tstruct sem_array *sma = container_of(ipcp, struct sem_array, sem_perm);": "static void freeary(struct ipc_namespace *ns, struct kern_ipc_perm *ipcp)\n{\n\tstruct sem_undo *un, *tu;\n\tstruct sem_queue *q, *tq;\n\tstruct sem_array *sma = container_of(ipcp, struct sem_array, sem_perm);\n\tint i;\n\tDEFINE_WAKE_Q(wake_q);\n\n\t/* Free the existing undo structures for this semaphore set.  */\n\tipc_assert_locked_object(&sma->sem_perm);\n\tlist_for_each_entry_safe(un, tu, &sma->list_id, list_id) {\n\t\tlist_del(&un->list_id);\n\t\tspin_lock(&un->ulp->lock);\n\t\tun->semid = -1;\n\t\tlist_del_rcu(&un->list_proc);\n\t\tspin_unlock(&un->ulp->lock);\n\t\tkvfree_rcu(un, rcu);\n\t}\n\n\t/* Wake up all pending processes and let them fail with EIDRM. */\n\tlist_for_each_entry_safe(q, tq, &sma->pending_const, list) {\n\t\tunlink_queue(sma, q);\n\t\twake_up_sem_queue_prepare(q, -EIDRM, &wake_q);\n\t}\n\n\tlist_for_each_entry_safe(q, tq, &sma->pending_alter, list) {\n\t\tunlink_queue(sma, q);\n\t\twake_up_sem_queue_prepare(q, -EIDRM, &wake_q);\n\t}\n\tfor (i = 0; i < sma->sem_nsems; i++) {\n\t\tstruct sem *sem = &sma->sems[i];\n\t\tlist_for_each_entry_safe(q, tq, &sem->pending_const, list) {\n\t\t\tunlink_queue(sma, q);\n\t\t\twake_up_sem_queue_prepare(q, -EIDRM, &wake_q);\n\t\t}\n\t\tlist_for_each_entry_safe(q, tq, &sem->pending_alter, list) {\n\t\t\tunlink_queue(sma, q);\n\t\t\twake_up_sem_queue_prepare(q, -EIDRM, &wake_q);\n\t\t}\n\t\tipc_update_pid(&sem->sempid, NULL);\n\t}\n\n\t/* Remove the semaphore set from the IDR */\n\tsem_rmid(ns, sma);\n\tsem_unlock(sma, -1);\n\trcu_read_unlock();\n\n\twake_up_q(&wake_q);\n\tns->used_sems -= sma->sem_nsems;\n\tipc_rcu_putref(&sma->sem_perm, sem_rcu_free);\n}",
        "static void test_fail_cases(void)\n{\n\tLIBBPF_OPTS(bpf_map_create_opts, opts);\n\t__u32 value;\n\tint fd, err;": "static void test_fail_cases(void)\n{\n\tLIBBPF_OPTS(bpf_map_create_opts, opts);\n\t__u32 value;\n\tint fd, err;\n\n\t/* Invalid key size */\n\tfd = bpf_map_create(BPF_MAP_TYPE_BLOOM_FILTER, NULL, 4, sizeof(value), 100, NULL);\n\tif (!ASSERT_LT(fd, 0, \"bpf_map_create bloom filter invalid key size\"))\n\t\tclose(fd);\n\n\t/* Invalid value size */\n\tfd = bpf_map_create(BPF_MAP_TYPE_BLOOM_FILTER, NULL, 0, 0, 100, NULL);\n\tif (!ASSERT_LT(fd, 0, \"bpf_map_create bloom filter invalid value size 0\"))\n\t\tclose(fd);\n\n\t/* Invalid max entries size */\n\tfd = bpf_map_create(BPF_MAP_TYPE_BLOOM_FILTER, NULL, 0, sizeof(value), 0, NULL);\n\tif (!ASSERT_LT(fd, 0, \"bpf_map_create bloom filter invalid max entries size\"))\n\t\tclose(fd);\n\n\t/* Bloom filter maps do not support BPF_F_NO_PREALLOC */\n\topts.map_flags = BPF_F_NO_PREALLOC;\n\tfd = bpf_map_create(BPF_MAP_TYPE_BLOOM_FILTER, NULL, 0, sizeof(value), 100, &opts);\n\tif (!ASSERT_LT(fd, 0, \"bpf_map_create bloom filter invalid flags\"))\n\t\tclose(fd);\n\n\tfd = bpf_map_create(BPF_MAP_TYPE_BLOOM_FILTER, NULL, 0, sizeof(value), 100, NULL);\n\tif (!ASSERT_GE(fd, 0, \"bpf_map_create bloom filter\"))\n\t\treturn;\n\n\t/* Test invalid flags */\n\terr = bpf_map_update_elem(fd, NULL, &value, -1);\n\tASSERT_EQ(err, -EINVAL, \"bpf_map_update_elem bloom filter invalid flags\");\n\n\terr = bpf_map_update_elem(fd, NULL, &value, BPF_EXIST);\n\tASSERT_EQ(err, -EINVAL, \"bpf_map_update_elem bloom filter invalid flags\");\n\n\terr = bpf_map_update_elem(fd, NULL, &value, BPF_F_LOCK);\n\tASSERT_EQ(err, -EINVAL, \"bpf_map_update_elem bloom filter invalid flags\");\n\n\terr = bpf_map_update_elem(fd, NULL, &value, BPF_NOEXIST);\n\tASSERT_EQ(err, -EINVAL, \"bpf_map_update_elem bloom filter invalid flags\");\n\n\terr = bpf_map_update_elem(fd, NULL, &value, 10000);\n\tASSERT_EQ(err, -EINVAL, \"bpf_map_update_elem bloom filter invalid flags\");\n\n\tclose(fd);\n}",
        "static void tick_sched_do_timer(struct tick_sched *ts, ktime_t now)\n{\n\tint cpu = smp_processor_id();\n\n#ifdef CONFIG_NO_HZ_COMMON": "static void tick_sched_do_timer(struct tick_sched *ts, ktime_t now)\n{\n\tint cpu = smp_processor_id();\n\n#ifdef CONFIG_NO_HZ_COMMON\n\t/*\n\t * Check if the do_timer duty was dropped. We don't care about\n\t * concurrency: This happens only when the CPU in charge went\n\t * into a long sleep. If two CPUs happen to assign themselves to\n\t * this duty, then the jiffies update is still serialized by\n\t * jiffies_lock.\n\t *\n\t * If nohz_full is enabled, this should not happen because the\n\t * tick_do_timer_cpu never relinquishes.\n\t */\n\tif (unlikely(tick_do_timer_cpu == TICK_DO_TIMER_NONE)) {\n#ifdef CONFIG_NO_HZ_FULL\n\t\tWARN_ON_ONCE(tick_nohz_full_running);\n#endif\n\t\ttick_do_timer_cpu = cpu;\n\t}\n#endif\n\n\t/* Check, if the jiffies need an update */\n\tif (tick_do_timer_cpu == cpu)\n\t\ttick_do_update_jiffies64(now);\n\n\t/*\n\t * If jiffies update stalled for too long (timekeeper in stop_machine()\n\t * or VMEXIT'ed for several msecs), force an update.\n\t */\n\tif (ts->last_tick_jiffies != jiffies) {\n\t\tts->stalled_jiffies = 0;\n\t\tts->last_tick_jiffies = READ_ONCE(jiffies);\n\t} else {\n\t\tif (++ts->stalled_jiffies == MAX_STALLED_JIFFIES) {\n\t\t\ttick_do_update_jiffies64(now);\n\t\t\tts->stalled_jiffies = 0;\n\t\t\tts->last_tick_jiffies = READ_ONCE(jiffies);\n\t\t}\n\t}\n\n\tif (ts->inidle)\n\t\tts->got_idle_tick = 1;\n}",
        "static void esmt_nand_decode_id(struct nand_chip *chip)\n{\n\tstruct nand_device *base = &chip->base;\n\tstruct nand_ecc_props requirements = {};\n": "static void esmt_nand_decode_id(struct nand_chip *chip)\n{\n\tstruct nand_device *base = &chip->base;\n\tstruct nand_ecc_props requirements = {};\n\n\tnand_decode_ext_id(chip);\n\n\t/* Extract ECC requirements from 5th id byte. */\n\tif (chip->id.len >= 5 && nand_is_slc(chip)) {\n\t\trequirements.step_size = 512;\n\t\tswitch (chip->id.data[4] & 0x3) {\n\t\tcase 0x0:\n\t\t\trequirements.strength = 4;\n\t\t\tbreak;\n\t\tcase 0x1:\n\t\t\trequirements.strength = 2;\n\t\t\tbreak;\n\t\tcase 0x2:\n\t\t\trequirements.strength = 1;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tWARN(1, \"Could not get ECC info\");\n\t\t\trequirements.step_size = 0;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tnanddev_set_ecc_requirements(base, &requirements);\n}",
        "static int dp_altmode_status_update(struct dp_altmode *dp)\n{\n\tbool configured = !!DP_CONF_GET_PIN_ASSIGN(dp->data.conf);\n\tbool hpd = !!(dp->data.status & DP_STATUS_HPD_STATE);\n\tu8 con = DP_STATUS_CONNECTION(dp->data.status);": "static int dp_altmode_status_update(struct dp_altmode *dp)\n{\n\tbool configured = !!DP_CONF_GET_PIN_ASSIGN(dp->data.conf);\n\tbool hpd = !!(dp->data.status & DP_STATUS_HPD_STATE);\n\tu8 con = DP_STATUS_CONNECTION(dp->data.status);\n\tint ret = 0;\n\n\tif (configured && (dp->data.status & DP_STATUS_SWITCH_TO_USB)) {\n\t\tdp->data.conf = 0;\n\t\tdp->state = DP_STATE_CONFIGURE;\n\t} else if (dp->data.status & DP_STATUS_EXIT_DP_MODE) {\n\t\tdp->state = DP_STATE_EXIT;\n\t} else if (!(con & DP_CONF_CURRENTLY(dp->data.conf))) {\n\t\tret = dp_altmode_configure(dp, con);\n\t\tif (!ret)\n\t\t\tdp->state = DP_STATE_CONFIGURE;\n\t} else {\n\t\tif (dp->hpd != hpd) {\n\t\t\tdrm_connector_oob_hotplug_event(dp->connector_fwnode);\n\t\t\tdp->hpd = hpd;\n\t\t}\n\t}\n\n\treturn ret;\n}",
        "static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve)\n{\n\tstruct usb_cdc_ncm_ndp32 *ndp32 = NULL;\n\tstruct usb_cdc_ncm_nth32 *nth32 = (void *)skb->data;\n\tsize_t ndpoffset = le32_to_cpu(nth32->dwNdpIndex);": "static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve)\n{\n\tstruct usb_cdc_ncm_ndp32 *ndp32 = NULL;\n\tstruct usb_cdc_ncm_nth32 *nth32 = (void *)skb->data;\n\tsize_t ndpoffset = le32_to_cpu(nth32->dwNdpIndex);\n\n\t/* If NDP should be moved to the end of the NCM package, we can't follow the\n\t * NTH32 header as we would normally do. NDP isn't written to the SKB yet, and\n\t * the wNdpIndex field in the header is actually not consistent with reality. It will be later.\n\t */\n\tif (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) {\n\t\tif (ctx->delayed_ndp32->dwSignature == sign)\n\t\t\treturn ctx->delayed_ndp32;\n\n\t\t/* We can only push a single NDP to the end. Return\n\t\t * NULL to send what we've already got and queue this\n\t\t * skb for later.\n\t\t */\n\t\telse if (ctx->delayed_ndp32->dwSignature)\n\t\t\treturn NULL;\n\t}\n\n\t/* follow the chain of NDPs, looking for a match */\n\twhile (ndpoffset) {\n\t\tndp32 = (struct usb_cdc_ncm_ndp32 *)(skb->data + ndpoffset);\n\t\tif  (ndp32->dwSignature == sign)\n\t\t\treturn ndp32;\n\t\tndpoffset = le32_to_cpu(ndp32->dwNextNdpIndex);\n\t}\n\n\t/* align new NDP */\n\tif (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END))\n\t\tcdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size);\n\n\t/* verify that there is room for the NDP and the datagram (reserve) */\n\tif ((ctx->tx_curr_size - skb->len - reserve) < ctx->max_ndp_size)\n\t\treturn NULL;\n\n\t/* link to it */\n\tif (ndp32)\n\t\tndp32->dwNextNdpIndex = cpu_to_le32(skb->len);\n\telse\n\t\tnth32->dwNdpIndex = cpu_to_le32(skb->len);\n\n\t/* push a new empty NDP */\n\tif (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END))\n\t\tndp32 = skb_put_zero(skb, ctx->max_ndp_size);\n\telse\n\t\tndp32 = ctx->delayed_ndp32;\n\n\tndp32->dwSignature = sign;\n\tndp32->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32));\n\treturn ndp32;\n}",
        "static bool send_waiting_read(struct sock *sk, u64 room_needed)\n{\n#if defined(VSOCK_OPTIMIZATION_WAITING_NOTIFY)\n\tstruct vsock_sock *vsk;\n\tstruct vmci_transport_waiting_info waiting_info;": "static bool send_waiting_read(struct sock *sk, u64 room_needed)\n{\n#if defined(VSOCK_OPTIMIZATION_WAITING_NOTIFY)\n\tstruct vsock_sock *vsk;\n\tstruct vmci_transport_waiting_info waiting_info;\n\tu64 tail;\n\tu64 head;\n\tu64 room_left;\n\tbool ret;\n\n\tvsk = vsock_sk(sk);\n\n\tif (PKT_FIELD(vsk, sent_waiting_read))\n\t\treturn true;\n\n\tif (PKT_FIELD(vsk, write_notify_window) <\n\t\t\tvmci_trans(vsk)->consume_size)\n\t\tPKT_FIELD(vsk, write_notify_window) =\n\t\t    min(PKT_FIELD(vsk, write_notify_window) + PAGE_SIZE,\n\t\t\tvmci_trans(vsk)->consume_size);\n\n\tvmci_qpair_get_consume_indexes(vmci_trans(vsk)->qpair, &tail, &head);\n\troom_left = vmci_trans(vsk)->consume_size - head;\n\tif (room_needed >= room_left) {\n\t\twaiting_info.offset = room_needed - room_left;\n\t\twaiting_info.generation =\n\t\t    PKT_FIELD(vsk, consume_q_generation) + 1;\n\t} else {\n\t\twaiting_info.offset = head + room_needed;\n\t\twaiting_info.generation = PKT_FIELD(vsk, consume_q_generation);\n\t}\n\n\tret = vmci_transport_send_waiting_read(sk, &waiting_info) > 0;\n\tif (ret)\n\t\tPKT_FIELD(vsk, sent_waiting_read) = true;\n\n\treturn ret;\n#else\n\treturn true;\n#endif\n}",
        "static int damon_sysfs_cmd_request_callback(struct damon_ctx *c)\n{\n\tstruct damon_sysfs_kdamond *kdamond;\n\tint err = 0;\n": "static int damon_sysfs_cmd_request_callback(struct damon_ctx *c)\n{\n\tstruct damon_sysfs_kdamond *kdamond;\n\tint err = 0;\n\n\t/* avoid deadlock due to concurrent state_store('off') */\n\tif (!mutex_trylock(&damon_sysfs_lock))\n\t\treturn 0;\n\tkdamond = damon_sysfs_cmd_request.kdamond;\n\tif (!kdamond || kdamond->damon_ctx != c)\n\t\tgoto out;\n\tswitch (damon_sysfs_cmd_request.cmd) {\n\tcase DAMON_SYSFS_CMD_UPDATE_SCHEMES_STATS:\n\t\terr = damon_sysfs_upd_schemes_stats(kdamond);\n\t\tbreak;\n\tcase DAMON_SYSFS_CMD_COMMIT:\n\t\terr = damon_sysfs_commit_input(kdamond);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\t/* Mark the request as invalid now. */\n\tdamon_sysfs_cmd_request.kdamond = NULL;\nout:\n\tmutex_unlock(&damon_sysfs_lock);\n\treturn err;\n}",
        "static int port100_send_ack(struct port100 *dev)\n{\n\tint rc = 0;\n\n\tmutex_lock(&dev->out_urb_lock);": "static int port100_send_ack(struct port100 *dev)\n{\n\tint rc = 0;\n\n\tmutex_lock(&dev->out_urb_lock);\n\n\t/*\n\t * If prior cancel is in-flight (dev->cmd_cancel == true), we\n\t * can skip to send cancel. Then this will wait the prior\n\t * cancel, or merged into the next cancel rarely if next\n\t * cancel was started before waiting done. In any case, this\n\t * will be waked up soon or later.\n\t */\n\tif (!dev->cmd_cancel) {\n\t\treinit_completion(&dev->cmd_cancel_done);\n\n\t\tusb_kill_urb(dev->out_urb);\n\n\t\tdev->out_urb->transfer_buffer = ack_frame;\n\t\tdev->out_urb->transfer_buffer_length = sizeof(ack_frame);\n\t\trc = usb_submit_urb(dev->out_urb, GFP_KERNEL);\n\n\t\t/*\n\t\t * Set the cmd_cancel flag only if the URB has been\n\t\t * successfully submitted. It will be reset by the out\n\t\t * URB completion callback port100_send_complete().\n\t\t */\n\t\tdev->cmd_cancel = !rc;\n\t}\n\n\tmutex_unlock(&dev->out_urb_lock);\n\n\tif (!rc)\n\t\twait_for_completion(&dev->cmd_cancel_done);\n\n\treturn rc;\n}",
        "static void perf_event__synthesize_guest_os(struct machine *machine, void *data)\n{\n\tint err;\n\tstruct perf_tool *tool = data;\n\t/*": "static void perf_event__synthesize_guest_os(struct machine *machine, void *data)\n{\n\tint err;\n\tstruct perf_tool *tool = data;\n\t/*\n\t *As for guest kernel when processing subcommand record&report,\n\t *we arrange module mmap prior to guest kernel mmap and trigger\n\t *a preload dso because default guest module symbols are loaded\n\t *from guest kallsyms instead of /lib/modules/XXX/XXX. This\n\t *method is used to avoid symbol missing when the first addr is\n\t *in module instead of in guest kernel.\n\t */\n\terr = perf_event__synthesize_modules(tool, process_synthesized_event,\n\t\t\t\t\t     machine);\n\tif (err < 0)\n\t\tpr_err(\"Couldn't record guest kernel [%d]'s reference\"\n\t\t       \" relocation symbol.\\n\", machine->pid);\n\n\t/*\n\t * We use _stext for guest kernel because guest kernel's /proc/kallsyms\n\t * have no _text sometimes.\n\t */\n\terr = perf_event__synthesize_kernel_mmap(tool, process_synthesized_event,\n\t\t\t\t\t\t machine);\n\tif (err < 0)\n\t\tpr_err(\"Couldn't record guest kernel [%d]'s reference\"\n\t\t       \" relocation symbol.\\n\", machine->pid);\n}",
        "static bool virtnet_set_hashflow(struct virtnet_info *vi, struct ethtool_rxnfc *info)\n{\n\tu32 new_hashtypes = vi->rss_hash_types_saved;\n\tbool is_disable = info->data & RXH_DISCARD;\n\tbool is_l4 = info->data == (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3);": "static bool virtnet_set_hashflow(struct virtnet_info *vi, struct ethtool_rxnfc *info)\n{\n\tu32 new_hashtypes = vi->rss_hash_types_saved;\n\tbool is_disable = info->data & RXH_DISCARD;\n\tbool is_l4 = info->data == (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3);\n\n\t/* supports only 'sd', 'sdfn' and 'r' */\n\tif (!((info->data == (RXH_IP_SRC | RXH_IP_DST)) | is_l4 | is_disable))\n\t\treturn false;\n\n\tswitch (info->flow_type) {\n\tcase TCP_V4_FLOW:\n\t\tnew_hashtypes &= ~(VIRTIO_NET_RSS_HASH_TYPE_IPv4 | VIRTIO_NET_RSS_HASH_TYPE_TCPv4);\n\t\tif (!is_disable)\n\t\t\tnew_hashtypes |= VIRTIO_NET_RSS_HASH_TYPE_IPv4\n\t\t\t\t| (is_l4 ? VIRTIO_NET_RSS_HASH_TYPE_TCPv4 : 0);\n\t\tbreak;\n\tcase UDP_V4_FLOW:\n\t\tnew_hashtypes &= ~(VIRTIO_NET_RSS_HASH_TYPE_IPv4 | VIRTIO_NET_RSS_HASH_TYPE_UDPv4);\n\t\tif (!is_disable)\n\t\t\tnew_hashtypes |= VIRTIO_NET_RSS_HASH_TYPE_IPv4\n\t\t\t\t| (is_l4 ? VIRTIO_NET_RSS_HASH_TYPE_UDPv4 : 0);\n\t\tbreak;\n\tcase IPV4_FLOW:\n\t\tnew_hashtypes &= ~VIRTIO_NET_RSS_HASH_TYPE_IPv4;\n\t\tif (!is_disable)\n\t\t\tnew_hashtypes = VIRTIO_NET_RSS_HASH_TYPE_IPv4;\n\t\tbreak;\n\tcase TCP_V6_FLOW:\n\t\tnew_hashtypes &= ~(VIRTIO_NET_RSS_HASH_TYPE_IPv6 | VIRTIO_NET_RSS_HASH_TYPE_TCPv6);\n\t\tif (!is_disable)\n\t\t\tnew_hashtypes |= VIRTIO_NET_RSS_HASH_TYPE_IPv6\n\t\t\t\t| (is_l4 ? VIRTIO_NET_RSS_HASH_TYPE_TCPv6 : 0);\n\t\tbreak;\n\tcase UDP_V6_FLOW:\n\t\tnew_hashtypes &= ~(VIRTIO_NET_RSS_HASH_TYPE_IPv6 | VIRTIO_NET_RSS_HASH_TYPE_UDPv6);\n\t\tif (!is_disable)\n\t\t\tnew_hashtypes |= VIRTIO_NET_RSS_HASH_TYPE_IPv6\n\t\t\t\t| (is_l4 ? VIRTIO_NET_RSS_HASH_TYPE_UDPv6 : 0);\n\t\tbreak;\n\tcase IPV6_FLOW:\n\t\tnew_hashtypes &= ~VIRTIO_NET_RSS_HASH_TYPE_IPv6;\n\t\tif (!is_disable)\n\t\t\tnew_hashtypes = VIRTIO_NET_RSS_HASH_TYPE_IPv6;\n\t\tbreak;\n\tdefault:\n\t\t/* unsupported flow */\n\t\treturn false;\n\t}\n\n\t/* if unsupported hashtype was set */\n\tif (new_hashtypes != (new_hashtypes & vi->rss_hash_types_supported))\n\t\treturn false;\n\n\tif (new_hashtypes != vi->rss_hash_types_saved) {\n\t\tvi->rss_hash_types_saved = new_hashtypes;\n\t\tvi->ctrl->rss.hash_types = vi->rss_hash_types_saved;\n\t\tif (vi->dev->features & NETIF_F_RXHASH)\n\t\t\treturn virtnet_commit_rss_command(vi);\n\t}\n\n\treturn true;\n}",
        "static int cvmx_usb_poll_channel(struct octeon_hcd *usb, int channel)\n{\n\tstruct usb_hcd *hcd = octeon_to_hcd(usb);\n\tstruct device *dev = hcd->self.controller;\n\tunion cvmx_usbcx_hcintx usbc_hcint;": "static int cvmx_usb_poll_channel(struct octeon_hcd *usb, int channel)\n{\n\tstruct usb_hcd *hcd = octeon_to_hcd(usb);\n\tstruct device *dev = hcd->self.controller;\n\tunion cvmx_usbcx_hcintx usbc_hcint;\n\tunion cvmx_usbcx_hctsizx usbc_hctsiz;\n\tunion cvmx_usbcx_hccharx usbc_hcchar;\n\tstruct cvmx_usb_pipe *pipe;\n\tstruct cvmx_usb_transaction *transaction;\n\tint bytes_this_transfer;\n\tint bytes_in_last_packet;\n\tint packets_processed;\n\tint buffer_space_left;\n\n\t/* Read the interrupt status bits for the channel */\n\tusbc_hcint.u32 = cvmx_usb_read_csr32(usb,\n\t\t\t\t\t     CVMX_USBCX_HCINTX(channel, usb->index));\n\n\tif (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {\n\t\tusbc_hcchar.u32 = cvmx_usb_read_csr32(usb,\n\t\t\t\t\t\t      CVMX_USBCX_HCCHARX(channel,\n\t\t\t\t\t\t\t\t\t usb->index));\n\n\t\tif (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {\n\t\t\t/*\n\t\t\t * There seems to be a bug in CN31XX which can cause\n\t\t\t * interrupt IN transfers to get stuck until we do a\n\t\t\t * write of HCCHARX without changing things\n\t\t\t */\n\t\t\tcvmx_usb_write_csr32(usb,\n\t\t\t\t\t     CVMX_USBCX_HCCHARX(channel,\n\t\t\t\t\t\t\t\tusb->index),\n\t\t\t\t\t     usbc_hcchar.u32);\n\t\t\treturn 0;\n\t\t}\n\n\t\t/*\n\t\t * In non DMA mode the channels don't halt themselves. We need\n\t\t * to manually disable channels that are left running\n\t\t */\n\t\tif (!usbc_hcint.s.chhltd) {\n\t\t\tif (usbc_hcchar.s.chena) {\n\t\t\t\tunion cvmx_usbcx_hcintmskx hcintmsk;\n\t\t\t\t/* Disable all interrupts except CHHLTD */\n\t\t\t\thcintmsk.u32 = 0;\n\t\t\t\thcintmsk.s.chhltdmsk = 1;\n\t\t\t\tcvmx_usb_write_csr32(usb,\n\t\t\t\t\t\t     CVMX_USBCX_HCINTMSKX(channel, usb->index),\n\t\t\t\t\t\t     hcintmsk.u32);\n\t\t\t\tusbc_hcchar.s.chdis = 1;\n\t\t\t\tcvmx_usb_write_csr32(usb,\n\t\t\t\t\t\t     CVMX_USBCX_HCCHARX(channel, usb->index),\n\t\t\t\t\t\t     usbc_hcchar.u32);\n\t\t\t\treturn 0;\n\t\t\t} else if (usbc_hcint.s.xfercompl) {\n\t\t\t\t/*\n\t\t\t\t * Successful IN/OUT with transfer complete.\n\t\t\t\t * Channel halt isn't needed.\n\t\t\t\t */\n\t\t\t} else {\n\t\t\t\tdev_err(dev, \"USB%d: Channel %d interrupt without halt\\n\",\n\t\t\t\t\tusb->index, channel);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t} else {\n\t\t/*\n\t\t * There is are no interrupts that we need to process when the\n\t\t * channel is still running\n\t\t */\n\t\tif (!usbc_hcint.s.chhltd)\n\t\t\treturn 0;\n\t}\n\n\t/* Disable the channel interrupts now that it is done */\n\tcvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);\n\tusb->idle_hardware_channels |= (1 << channel);\n\n\t/* Make sure this channel is tied to a valid pipe */\n\tpipe = usb->pipe_for_channel[channel];\n\tprefetch(pipe);\n\tif (!pipe)\n\t\treturn 0;\n\ttransaction = list_first_entry(&pipe->transactions,\n\t\t\t\t       typeof(*transaction),\n\t\t\t\t       node);\n\tprefetch(transaction);\n\n\t/*\n\t * Disconnect this pipe from the HW channel. Later the schedule\n\t * function will figure out which pipe needs to go\n\t */\n\tusb->pipe_for_channel[channel] = NULL;\n\tpipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED;\n\n\t/*\n\t * Read the channel config info so we can figure out how much data\n\t * transferred\n\t */\n\tusbc_hcchar.u32 = cvmx_usb_read_csr32(usb,\n\t\t\t\t\t      CVMX_USBCX_HCCHARX(channel, usb->index));\n\tusbc_hctsiz.u32 = cvmx_usb_read_csr32(usb,\n\t\t\t\t\t      CVMX_USBCX_HCTSIZX(channel, usb->index));\n\n\t/*\n\t * Calculating the number of bytes successfully transferred is dependent\n\t * on the transfer direction\n\t */\n\tpackets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;\n\tif (usbc_hcchar.s.epdir) {\n\t\t/*\n\t\t * IN transactions are easy. For every byte received the\n\t\t * hardware decrements xfersize. All we need to do is subtract\n\t\t * the current value of xfersize from its starting value and we\n\t\t * know how many bytes were written to the buffer\n\t\t */\n\t\tbytes_this_transfer = transaction->xfersize -\n\t\t\tusbc_hctsiz.s.xfersize;\n\t} else {\n\t\t/*\n\t\t * OUT transaction don't decrement xfersize. Instead pktcnt is\n\t\t * decremented on every successful packet send. The hardware\n\t\t * does this when it receives an ACK, or NYET. If it doesn't\n\t\t * receive one of these responses pktcnt doesn't change\n\t\t */\n\t\tbytes_this_transfer = packets_processed * usbc_hcchar.s.mps;\n\t\t/*\n\t\t * The last packet may not be a full transfer if we didn't have\n\t\t * enough data\n\t\t */\n\t\tif (bytes_this_transfer > transaction->xfersize)\n\t\t\tbytes_this_transfer = transaction->xfersize;\n\t}\n\t/* Figure out how many bytes were in the last packet of the transfer */\n\tif (packets_processed)\n\t\tbytes_in_last_packet = bytes_this_transfer -\n\t\t\t(packets_processed - 1) * usbc_hcchar.s.mps;\n\telse\n\t\tbytes_in_last_packet = bytes_this_transfer;\n\n\t/*\n\t * As a special case, setup transactions output the setup header, not\n\t * the user's data. For this reason we don't count setup data as bytes\n\t * transferred\n\t */\n\tif ((transaction->stage == CVMX_USB_STAGE_SETUP) ||\n\t    (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))\n\t\tbytes_this_transfer = 0;\n\n\t/*\n\t * Add the bytes transferred to the running total. It is important that\n\t * bytes_this_transfer doesn't count any data that needs to be\n\t * retransmitted\n\t */\n\ttransaction->actual_bytes += bytes_this_transfer;\n\tif (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)\n\t\tbuffer_space_left = transaction->iso_packets[0].length -\n\t\t\ttransaction->actual_bytes;\n\telse\n\t\tbuffer_space_left = transaction->buffer_length -\n\t\t\ttransaction->actual_bytes;\n\n\t/*\n\t * We need to remember the PID toggle state for the next transaction.\n\t * The hardware already updated it for the next transaction\n\t */\n\tpipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);\n\n\t/*\n\t * For high speed bulk out, assume the next transaction will need to do\n\t * a ping before proceeding. If this isn't true the ACK processing below\n\t * will clear this flag\n\t */\n\tif ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&\n\t    (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&\n\t    (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))\n\t\tpipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING;\n\n\tif (WARN_ON_ONCE(bytes_this_transfer < 0)) {\n\t\t/*\n\t\t * In some rare cases the DMA engine seems to get stuck and\n\t\t * keeps substracting same byte count over and over again. In\n\t\t * such case we just need to fail every transaction.\n\t\t */\n\t\tcvmx_usb_complete(usb, pipe, transaction,\n\t\t\t\t  CVMX_USB_STATUS_ERROR);\n\t\treturn 0;\n\t}\n\n\tif (usbc_hcint.s.stall) {\n\t\t/*\n\t\t * STALL as a response means this transaction cannot be\n\t\t * completed because the device can't process transactions. Tell\n\t\t * the user. Any data that was transferred will be counted on\n\t\t * the actual bytes transferred\n\t\t */\n\t\tpipe->pid_toggle = 0;\n\t\tcvmx_usb_complete(usb, pipe, transaction,\n\t\t\t\t  CVMX_USB_STATUS_STALL);\n\t} else if (usbc_hcint.s.xacterr) {\n\t\t/*\n\t\t * XactErr as a response means the device signaled\n\t\t * something wrong with the transfer. For example, PID\n\t\t * toggle errors cause these.\n\t\t */\n\t\tcvmx_usb_complete(usb, pipe, transaction,\n\t\t\t\t  CVMX_USB_STATUS_XACTERR);\n\t} else if (usbc_hcint.s.bblerr) {\n\t\t/* Babble Error (BblErr) */\n\t\tcvmx_usb_complete(usb, pipe, transaction,\n\t\t\t\t  CVMX_USB_STATUS_BABBLEERR);\n\t} else if (usbc_hcint.s.datatglerr) {\n\t\t/* Data toggle error */\n\t\tcvmx_usb_complete(usb, pipe, transaction,\n\t\t\t\t  CVMX_USB_STATUS_DATATGLERR);\n\t} else if (usbc_hcint.s.nyet) {\n\t\t/*\n\t\t * NYET as a response is only allowed in three cases: as a\n\t\t * response to a ping, as a response to a split transaction, and\n\t\t * as a response to a bulk out. The ping case is handled by\n\t\t * hardware, so we only have splits and bulk out\n\t\t */\n\t\tif (!cvmx_usb_pipe_needs_split(usb, pipe)) {\n\t\t\ttransaction->retries = 0;\n\t\t\t/*\n\t\t\t * If there is more data to go then we need to try\n\t\t\t * again. Otherwise this transaction is complete\n\t\t\t */\n\t\t\tif ((buffer_space_left == 0) ||\n\t\t\t    (bytes_in_last_packet < pipe->max_packet))\n\t\t\t\tcvmx_usb_complete(usb, pipe,\n\t\t\t\t\t\t  transaction,\n\t\t\t\t\t\t  CVMX_USB_STATUS_OK);\n\t\t} else {\n\t\t\t/*\n\t\t\t * Split transactions retry the split complete 4 times\n\t\t\t * then rewind to the start split and do the entire\n\t\t\t * transactions again\n\t\t\t */\n\t\t\ttransaction->retries++;\n\t\t\tif ((transaction->retries & 0x3) == 0) {\n\t\t\t\t/*\n\t\t\t\t * Rewind to the beginning of the transaction by\n\t\t\t\t * anding off the split complete bit\n\t\t\t\t */\n\t\t\t\ttransaction->stage &= ~1;\n\t\t\t\tpipe->split_sc_frame = -1;\n\t\t\t}\n\t\t}\n\t} else if (usbc_hcint.s.ack) {\n\t\ttransaction->retries = 0;\n\t\t/*\n\t\t * The ACK bit can only be checked after the other error bits.\n\t\t * This is because a multi packet transfer may succeed in a\n\t\t * number of packets and then get a different response on the\n\t\t * last packet. In this case both ACK and the last response bit\n\t\t * will be set. If none of the other response bits is set, then\n\t\t * the last packet must have been an ACK\n\t\t *\n\t\t * Since we got an ACK, we know we don't need to do a ping on\n\t\t * this pipe\n\t\t */\n\t\tpipe->flags &= ~CVMX_USB_PIPE_FLAGS_NEED_PING;\n\n\t\tswitch (transaction->type) {\n\t\tcase CVMX_USB_TRANSFER_CONTROL:\n\t\t\tcvmx_usb_transfer_control(usb, pipe, transaction,\n\t\t\t\t\t\t  usbc_hcchar,\n\t\t\t\t\t\t  buffer_space_left,\n\t\t\t\t\t\t  bytes_in_last_packet);\n\t\t\tbreak;\n\t\tcase CVMX_USB_TRANSFER_BULK:\n\t\t\tcvmx_usb_transfer_bulk(usb, pipe, transaction,\n\t\t\t\t\t       usbc_hcint, buffer_space_left,\n\t\t\t\t\t       bytes_in_last_packet);\n\t\t\tbreak;\n\t\tcase CVMX_USB_TRANSFER_INTERRUPT:\n\t\t\tcvmx_usb_transfer_intr(usb, pipe, transaction,\n\t\t\t\t\t       buffer_space_left,\n\t\t\t\t\t       bytes_in_last_packet);\n\t\t\tbreak;\n\t\tcase CVMX_USB_TRANSFER_ISOCHRONOUS:\n\t\t\tcvmx_usb_transfer_isoc(usb, pipe, transaction,\n\t\t\t\t\t       buffer_space_left,\n\t\t\t\t\t       bytes_in_last_packet,\n\t\t\t\t\t       bytes_this_transfer);\n\t\t\tbreak;\n\t\t}\n\t} else if (usbc_hcint.s.nak) {\n\t\t/*\n\t\t * If this was a split then clear our split in progress marker.\n\t\t */\n\t\tif (usb->active_split == transaction)\n\t\t\tusb->active_split = NULL;\n\t\t/*\n\t\t * NAK as a response means the device couldn't accept the\n\t\t * transaction, but it should be retried in the future. Rewind\n\t\t * to the beginning of the transaction by anding off the split\n\t\t * complete bit. Retry in the next interval\n\t\t */\n\t\ttransaction->retries = 0;\n\t\ttransaction->stage &= ~1;\n\t\tpipe->next_tx_frame += pipe->interval;\n\t\tif (pipe->next_tx_frame < usb->frame_number)\n\t\t\tpipe->next_tx_frame = usb->frame_number +\n\t\t\t\tpipe->interval -\n\t\t\t\t(usb->frame_number - pipe->next_tx_frame) %\n\t\t\t\tpipe->interval;\n\t} else {\n\t\tstruct cvmx_usb_port_status port;\n\n\t\tport = cvmx_usb_get_status(usb);\n\t\tif (port.port_enabled) {\n\t\t\t/* We'll retry the exact same transaction again */\n\t\t\ttransaction->retries++;\n\t\t} else {\n\t\t\t/*\n\t\t\t * We get channel halted interrupts with no result bits\n\t\t\t * sets when the cable is unplugged\n\t\t\t */\n\t\t\tcvmx_usb_complete(usb, pipe, transaction,\n\t\t\t\t\t  CVMX_USB_STATUS_ERROR);\n\t\t}\n\t}\n\treturn 0;\n}",
        "static bool tipc_crypto_key_rcv(struct tipc_crypto *rx, struct tipc_msg *hdr)\n{\n\tstruct tipc_crypto *tx = tipc_net(rx->net)->crypto_tx;\n\tstruct tipc_aead_key *skey = NULL;\n\tu16 key_gen = msg_key_gen(hdr);": "static bool tipc_crypto_key_rcv(struct tipc_crypto *rx, struct tipc_msg *hdr)\n{\n\tstruct tipc_crypto *tx = tipc_net(rx->net)->crypto_tx;\n\tstruct tipc_aead_key *skey = NULL;\n\tu16 key_gen = msg_key_gen(hdr);\n\tu32 size = msg_data_sz(hdr);\n\tu8 *data = msg_data(hdr);\n\tunsigned int keylen;\n\n\t/* Verify whether the size can exist in the packet */\n\tif (unlikely(size < sizeof(struct tipc_aead_key) + TIPC_AEAD_KEYLEN_MIN)) {\n\t\tpr_debug(\"%s: message data size is too small\\n\", rx->name);\n\t\tgoto exit;\n\t}\n\n\tkeylen = ntohl(*((__be32 *)(data + TIPC_AEAD_ALG_NAME)));\n\n\t/* Verify the supplied size values */\n\tif (unlikely(size != keylen + sizeof(struct tipc_aead_key) ||\n\t\t     keylen > TIPC_AEAD_KEY_SIZE_MAX)) {\n\t\tpr_debug(\"%s: invalid MSG_CRYPTO key size\\n\", rx->name);\n\t\tgoto exit;\n\t}\n\n\tspin_lock(&rx->lock);\n\tif (unlikely(rx->skey || (key_gen == rx->key_gen && rx->key.keys))) {\n\t\tpr_err(\"%s: key existed <%p>, gen %d vs %d\\n\", rx->name,\n\t\t       rx->skey, key_gen, rx->key_gen);\n\t\tgoto exit_unlock;\n\t}\n\n\t/* Allocate memory for the key */\n\tskey = kmalloc(size, GFP_ATOMIC);\n\tif (unlikely(!skey)) {\n\t\tpr_err(\"%s: unable to allocate memory for skey\\n\", rx->name);\n\t\tgoto exit_unlock;\n\t}\n\n\t/* Copy key from msg data */\n\tskey->keylen = keylen;\n\tmemcpy(skey->alg_name, data, TIPC_AEAD_ALG_NAME);\n\tmemcpy(skey->key, data + TIPC_AEAD_ALG_NAME + sizeof(__be32),\n\t       skey->keylen);\n\n\trx->key_gen = key_gen;\n\trx->skey_mode = msg_key_mode(hdr);\n\trx->skey = skey;\n\trx->nokey = 0;\n\tmb(); /* for nokey flag */\n\nexit_unlock:\n\tspin_unlock(&rx->lock);\n\nexit:\n\t/* Schedule the key attaching on this crypto */\n\tif (likely(skey && queue_delayed_work(tx->wq, &rx->work, 0)))\n\t\treturn true;\n\n\treturn false;\n}",
        "static void test_lru_sanity3(int map_type, int map_flags, unsigned int tgt_free)\n{\n\tunsigned long long key, end_key, value[nr_cpus];\n\tint lru_map_fd, expected_map_fd;\n\tunsigned int batch_size;": "static void test_lru_sanity3(int map_type, int map_flags, unsigned int tgt_free)\n{\n\tunsigned long long key, end_key, value[nr_cpus];\n\tint lru_map_fd, expected_map_fd;\n\tunsigned int batch_size;\n\tunsigned int map_size;\n\tint next_cpu = 0;\n\n\tif (map_flags & BPF_F_NO_COMMON_LRU)\n\t\t/* This test is only applicable to common LRU list */\n\t\treturn;\n\n\tprintf(\"%s (map_type:%d map_flags:0x%X): \", __func__, map_type,\n\t       map_flags);\n\n\tassert(sched_next_online(0, &next_cpu) != -1);\n\n\tbatch_size = tgt_free / 2;\n\tassert(batch_size * 2 == tgt_free);\n\n\tmap_size = tgt_free * 2;\n\tlru_map_fd = create_map(map_type, map_flags, map_size);\n\tassert(lru_map_fd != -1);\n\n\texpected_map_fd = create_map(BPF_MAP_TYPE_HASH, 0, map_size);\n\tassert(expected_map_fd != -1);\n\n\tvalue[0] = 1234;\n\n\t/* Insert 1 to 2*tgt_free (+2*tgt_free keys) */\n\tend_key = 1 + (2 * tgt_free);\n\tfor (key = 1; key < end_key; key++)\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\n\t/* Lookup key 1 to tgt_free*3/2 */\n\tend_key = tgt_free + batch_size;\n\tfor (key = 1; key < end_key; key++) {\n\t\tassert(!bpf_map_lookup_elem_with_ref_bit(lru_map_fd, key, value));\n\t\tassert(!bpf_map_update_elem(expected_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t}\n\n\t/* Add 1+2*tgt_free to tgt_free*5/2\n\t * (+tgt_free/2 keys)\n\t */\n\tkey = 2 * tgt_free + 1;\n\tend_key = key + batch_size;\n\tfor (; key < end_key; key++) {\n\t\tassert(!bpf_map_update_elem(lru_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t\tassert(!bpf_map_update_elem(expected_map_fd, &key, value,\n\t\t\t\t\t    BPF_NOEXIST));\n\t}\n\n\tassert(map_equal(lru_map_fd, expected_map_fd));\n\n\tclose(expected_map_fd);\n\tclose(lru_map_fd);\n\n\tprintf(\"Pass\\n\");\n}",
        "static struct z3fold_header *compact_single_buddy(struct z3fold_header *zhdr)\n{\n\tstruct z3fold_pool *pool = zhdr_to_pool(zhdr);\n\tvoid *p = zhdr;\n\tunsigned long old_handle = 0;": "static struct z3fold_header *compact_single_buddy(struct z3fold_header *zhdr)\n{\n\tstruct z3fold_pool *pool = zhdr_to_pool(zhdr);\n\tvoid *p = zhdr;\n\tunsigned long old_handle = 0;\n\tsize_t sz = 0;\n\tstruct z3fold_header *new_zhdr = NULL;\n\tint first_idx = __idx(zhdr, FIRST);\n\tint middle_idx = __idx(zhdr, MIDDLE);\n\tint last_idx = __idx(zhdr, LAST);\n\tunsigned short *moved_chunks = NULL;\n\n\t/*\n\t * No need to protect slots here -- all the slots are \"local\" and\n\t * the page lock is already taken\n\t */\n\tif (zhdr->first_chunks && zhdr->slots->slot[first_idx]) {\n\t\tp += ZHDR_SIZE_ALIGNED;\n\t\tsz = zhdr->first_chunks << CHUNK_SHIFT;\n\t\told_handle = (unsigned long)&zhdr->slots->slot[first_idx];\n\t\tmoved_chunks = &zhdr->first_chunks;\n\t} else if (zhdr->middle_chunks && zhdr->slots->slot[middle_idx]) {\n\t\tp += zhdr->start_middle << CHUNK_SHIFT;\n\t\tsz = zhdr->middle_chunks << CHUNK_SHIFT;\n\t\told_handle = (unsigned long)&zhdr->slots->slot[middle_idx];\n\t\tmoved_chunks = &zhdr->middle_chunks;\n\t} else if (zhdr->last_chunks && zhdr->slots->slot[last_idx]) {\n\t\tp += PAGE_SIZE - (zhdr->last_chunks << CHUNK_SHIFT);\n\t\tsz = zhdr->last_chunks << CHUNK_SHIFT;\n\t\told_handle = (unsigned long)&zhdr->slots->slot[last_idx];\n\t\tmoved_chunks = &zhdr->last_chunks;\n\t}\n\n\tif (sz > 0) {\n\t\tenum buddy new_bud = HEADLESS;\n\t\tshort chunks = size_to_chunks(sz);\n\t\tvoid *q;\n\n\t\tnew_zhdr = __z3fold_alloc(pool, sz, false);\n\t\tif (!new_zhdr)\n\t\t\treturn NULL;\n\n\t\tif (WARN_ON(new_zhdr == zhdr))\n\t\t\tgoto out_fail;\n\n\t\tnew_bud = get_free_buddy(new_zhdr, chunks);\n\t\tq = new_zhdr;\n\t\tswitch (new_bud) {\n\t\tcase FIRST:\n\t\t\tnew_zhdr->first_chunks = chunks;\n\t\t\tq += ZHDR_SIZE_ALIGNED;\n\t\t\tbreak;\n\t\tcase MIDDLE:\n\t\t\tnew_zhdr->middle_chunks = chunks;\n\t\t\tnew_zhdr->start_middle =\n\t\t\t\tnew_zhdr->first_chunks + ZHDR_CHUNKS;\n\t\t\tq += new_zhdr->start_middle << CHUNK_SHIFT;\n\t\t\tbreak;\n\t\tcase LAST:\n\t\t\tnew_zhdr->last_chunks = chunks;\n\t\t\tq += PAGE_SIZE - (new_zhdr->last_chunks << CHUNK_SHIFT);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tgoto out_fail;\n\t\t}\n\t\tnew_zhdr->foreign_handles++;\n\t\tmemcpy(q, p, sz);\n\t\twrite_lock(&zhdr->slots->lock);\n\t\t*(unsigned long *)old_handle = (unsigned long)new_zhdr +\n\t\t\t__idx(new_zhdr, new_bud);\n\t\tif (new_bud == LAST)\n\t\t\t*(unsigned long *)old_handle |=\n\t\t\t\t\t(new_zhdr->last_chunks << BUDDY_SHIFT);\n\t\twrite_unlock(&zhdr->slots->lock);\n\t\tadd_to_unbuddied(pool, new_zhdr);\n\t\tz3fold_page_unlock(new_zhdr);\n\n\t\t*moved_chunks = 0;\n\t}\n\n\treturn new_zhdr;\n\nout_fail:\n\tif (new_zhdr && !kref_put(&new_zhdr->refcount, release_z3fold_page_locked)) {\n\t\tadd_to_unbuddied(pool, new_zhdr);\n\t\tz3fold_page_unlock(new_zhdr);\n\t}\n\treturn NULL;\n\n}",
        "static void cifs_readahead(struct readahead_control *ractl)\n{\n\tint rc;\n\tstruct cifsFileInfo *open_file = ractl->file->private_data;\n\tstruct cifs_sb_info *cifs_sb = CIFS_FILE_SB(ractl->file);": "static void cifs_readahead(struct readahead_control *ractl)\n{\n\tint rc;\n\tstruct cifsFileInfo *open_file = ractl->file->private_data;\n\tstruct cifs_sb_info *cifs_sb = CIFS_FILE_SB(ractl->file);\n\tstruct TCP_Server_Info *server;\n\tpid_t pid;\n\tunsigned int xid, nr_pages, last_batch_size = 0, cache_nr_pages = 0;\n\tpgoff_t next_cached = ULONG_MAX;\n\tbool caching = fscache_cookie_enabled(cifs_inode_cookie(ractl->mapping->host)) &&\n\t\tcifs_inode_cookie(ractl->mapping->host)->cache_priv;\n\tbool check_cache = caching;\n\n\txid = get_xid();\n\n\tif (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_RWPIDFORWARD)\n\t\tpid = open_file->pid;\n\telse\n\t\tpid = current->tgid;\n\n\trc = 0;\n\tserver = cifs_pick_channel(tlink_tcon(open_file->tlink)->ses);\n\n\tcifs_dbg(FYI, \"%s: file=%p mapping=%p num_pages=%u\\n\",\n\t\t __func__, ractl->file, ractl->mapping, readahead_count(ractl));\n\n\t/*\n\t * Chop the readahead request up into rsize-sized read requests.\n\t */\n\twhile ((nr_pages = readahead_count(ractl) - last_batch_size)) {\n\t\tunsigned int i, got, rsize;\n\t\tstruct page *page;\n\t\tstruct cifs_readdata *rdata;\n\t\tstruct cifs_credits credits_on_stack;\n\t\tstruct cifs_credits *credits = &credits_on_stack;\n\t\tpgoff_t index = readahead_index(ractl) + last_batch_size;\n\n\t\t/*\n\t\t * Find out if we have anything cached in the range of\n\t\t * interest, and if so, where the next chunk of cached data is.\n\t\t */\n\t\tif (caching) {\n\t\t\tif (check_cache) {\n\t\t\t\trc = cifs_fscache_query_occupancy(\n\t\t\t\t\tractl->mapping->host, index, nr_pages,\n\t\t\t\t\t&next_cached, &cache_nr_pages);\n\t\t\t\tif (rc < 0)\n\t\t\t\t\tcaching = false;\n\t\t\t\tcheck_cache = false;\n\t\t\t}\n\n\t\t\tif (index == next_cached) {\n\t\t\t\t/*\n\t\t\t\t * TODO: Send a whole batch of pages to be read\n\t\t\t\t * by the cache.\n\t\t\t\t */\n\t\t\t\tpage = readahead_page(ractl);\n\t\t\t\tlast_batch_size = 1 << thp_order(page);\n\t\t\t\tif (cifs_readpage_from_fscache(ractl->mapping->host,\n\t\t\t\t\t\t\t       page) < 0) {\n\t\t\t\t\t/*\n\t\t\t\t\t * TODO: Deal with cache read failure\n\t\t\t\t\t * here, but for the moment, delegate\n\t\t\t\t\t * that to readpage.\n\t\t\t\t\t */\n\t\t\t\t\tcaching = false;\n\t\t\t\t}\n\t\t\t\tunlock_page(page);\n\t\t\t\tnext_cached++;\n\t\t\t\tcache_nr_pages--;\n\t\t\t\tif (cache_nr_pages == 0)\n\t\t\t\t\tcheck_cache = true;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\tif (open_file->invalidHandle) {\n\t\t\trc = cifs_reopen_file(open_file, true);\n\t\t\tif (rc) {\n\t\t\t\tif (rc == -EAGAIN)\n\t\t\t\t\tcontinue;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (cifs_sb->ctx->rsize == 0)\n\t\t\tcifs_sb->ctx->rsize =\n\t\t\t\tserver->ops->negotiate_rsize(tlink_tcon(open_file->tlink),\n\t\t\t\t\t\t\t     cifs_sb->ctx);\n\n\t\trc = server->ops->wait_mtu_credits(server, cifs_sb->ctx->rsize,\n\t\t\t\t\t\t   &rsize, credits);\n\t\tif (rc)\n\t\t\tbreak;\n\t\tnr_pages = min_t(size_t, rsize / PAGE_SIZE, readahead_count(ractl));\n\t\tnr_pages = min_t(size_t, nr_pages, next_cached - index);\n\n\t\t/*\n\t\t * Give up immediately if rsize is too small to read an entire\n\t\t * page. The VFS will fall back to readpage. We should never\n\t\t * reach this point however since we set ra_pages to 0 when the\n\t\t * rsize is smaller than a cache page.\n\t\t */\n\t\tif (unlikely(!nr_pages)) {\n\t\t\tadd_credits_and_wake_if(server, credits, 0);\n\t\t\tbreak;\n\t\t}\n\n\t\trdata = cifs_readdata_alloc(nr_pages, cifs_readv_complete);\n\t\tif (!rdata) {\n\t\t\t/* best to give up if we're out of mem */\n\t\t\tadd_credits_and_wake_if(server, credits, 0);\n\t\t\tbreak;\n\t\t}\n\n\t\tgot = __readahead_batch(ractl, rdata->pages, nr_pages);\n\t\tif (got != nr_pages) {\n\t\t\tpr_warn(\"__readahead_batch() returned %u/%u\\n\",\n\t\t\t\tgot, nr_pages);\n\t\t\tnr_pages = got;\n\t\t}\n\n\t\trdata->nr_pages = nr_pages;\n\t\trdata->bytes\t= readahead_batch_length(ractl);\n\t\trdata->cfile\t= cifsFileInfo_get(open_file);\n\t\trdata->server\t= server;\n\t\trdata->mapping\t= ractl->mapping;\n\t\trdata->offset\t= readahead_pos(ractl);\n\t\trdata->pid\t= pid;\n\t\trdata->pagesz\t= PAGE_SIZE;\n\t\trdata->tailsz\t= PAGE_SIZE;\n\t\trdata->read_into_pages = cifs_readpages_read_into_pages;\n\t\trdata->copy_into_pages = cifs_readpages_copy_into_pages;\n\t\trdata->credits\t= credits_on_stack;\n\n\t\trc = adjust_credits(server, &rdata->credits, rdata->bytes);\n\t\tif (!rc) {\n\t\t\tif (rdata->cfile->invalidHandle)\n\t\t\t\trc = -EAGAIN;\n\t\t\telse\n\t\t\t\trc = server->ops->async_readv(rdata);\n\t\t}\n\n\t\tif (rc) {\n\t\t\tadd_credits_and_wake_if(server, &rdata->credits, 0);\n\t\t\tfor (i = 0; i < rdata->nr_pages; i++) {\n\t\t\t\tpage = rdata->pages[i];\n\t\t\t\tunlock_page(page);\n\t\t\t\tput_page(page);\n\t\t\t}\n\t\t\t/* Fallback to the readpage in error/reconnect cases */\n\t\t\tkref_put(&rdata->refcount, cifs_readdata_release);\n\t\t\tbreak;\n\t\t}\n\n\t\tkref_put(&rdata->refcount, cifs_readdata_release);\n\t\tlast_batch_size = nr_pages;\n\t}\n\n\tfree_xid(xid);\n}",
        "static void run_core_reloc_tests(bool use_btfgen)\n{\n\tconst size_t mmap_sz = roundup_page(sizeof(struct data));\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, open_opts);\n\tstruct core_reloc_test_case *test_case, test_case_copy;": "static void run_core_reloc_tests(bool use_btfgen)\n{\n\tconst size_t mmap_sz = roundup_page(sizeof(struct data));\n\tDECLARE_LIBBPF_OPTS(bpf_object_open_opts, open_opts);\n\tstruct core_reloc_test_case *test_case, test_case_copy;\n\tconst char *tp_name, *probe_name;\n\tint err, i, equal, fd;\n\tstruct bpf_link *link = NULL;\n\tstruct bpf_map *data_map;\n\tstruct bpf_program *prog;\n\tstruct bpf_object *obj;\n\tuint64_t my_pid_tgid;\n\tstruct data *data;\n\tvoid *mmap_data = NULL;\n\n\tmy_pid_tgid = getpid() | ((uint64_t)syscall(SYS_gettid) << 32);\n\n\tfor (i = 0; i < ARRAY_SIZE(test_cases); i++) {\n\t\tchar btf_file[] = \"/tmp/core_reloc.btf.XXXXXX\";\n\n\t\ttest_case_copy = test_cases[i];\n\t\ttest_case = &test_case_copy;\n\n\t\tif (!test__start_subtest(test_case->case_name))\n\t\t\tcontinue;\n\n\t\tif (test_case->needs_testmod && !env.has_testmod) {\n\t\t\ttest__skip();\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* generate a \"minimal\" BTF file and use it as source */\n\t\tif (use_btfgen) {\n\n\t\t\tif (!test_case->btf_src_file || test_case->fails) {\n\t\t\t\ttest__skip();\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tfd = mkstemp(btf_file);\n\t\t\tif (!ASSERT_GE(fd, 0, \"btf_tmp\"))\n\t\t\t\tcontinue;\n\t\t\tclose(fd); /* we only need the path */\n\t\t\terr = run_btfgen(test_case->btf_src_file, btf_file,\n\t\t\t\t\t test_case->bpf_obj_file);\n\t\t\tif (!ASSERT_OK(err, \"run_btfgen\"))\n\t\t\t\tcontinue;\n\n\t\t\ttest_case->btf_src_file = btf_file;\n\t\t}\n\n\t\tif (test_case->setup) {\n\t\t\terr = test_case->setup(test_case);\n\t\t\tif (CHECK(err, \"test_setup\", \"test #%d setup failed: %d\\n\", i, err))\n\t\t\t\tcontinue;\n\t\t}\n\n\t\tif (test_case->btf_src_file) {\n\t\t\terr = access(test_case->btf_src_file, R_OK);\n\t\t\tif (!ASSERT_OK(err, \"btf_src_file\"))\n\t\t\t\tcontinue;\n\t\t}\n\n\t\topen_opts.btf_custom_path = test_case->btf_src_file;\n\t\tobj = bpf_object__open_file(test_case->bpf_obj_file, &open_opts);\n\t\tif (!ASSERT_OK_PTR(obj, \"obj_open\"))\n\t\t\tgoto cleanup;\n\n\t\tprobe_name = test_case->prog_name;\n\t\ttp_name = test_case->raw_tp_name; /* NULL for tp_btf */\n\t\tprog = bpf_object__find_program_by_name(obj, probe_name);\n\t\tif (CHECK(!prog, \"find_probe\",\n\t\t\t  \"prog '%s' not found\\n\", probe_name))\n\t\t\tgoto cleanup;\n\n\t\terr = bpf_object__load(obj);\n\t\tif (err) {\n\t\t\tif (!test_case->fails)\n\t\t\t\tASSERT_OK(err, \"obj_load\");\n\t\t\tgoto cleanup;\n\t\t}\n\n\t\tdata_map = bpf_object__find_map_by_name(obj, \".bss\");\n\t\tif (CHECK(!data_map, \"find_data_map\", \"data map not found\\n\"))\n\t\t\tgoto cleanup;\n\n\t\tmmap_data = mmap(NULL, mmap_sz, PROT_READ | PROT_WRITE,\n\t\t\t\t MAP_SHARED, bpf_map__fd(data_map), 0);\n\t\tif (CHECK(mmap_data == MAP_FAILED, \"mmap\",\n\t\t\t  \".bss mmap failed: %d\", errno)) {\n\t\t\tmmap_data = NULL;\n\t\t\tgoto cleanup;\n\t\t}\n\t\tdata = mmap_data;\n\n\t\tmemset(mmap_data, 0, sizeof(*data));\n\t\tif (test_case->input_len)\n\t\t\tmemcpy(data->in, test_case->input, test_case->input_len);\n\t\tdata->my_pid_tgid = my_pid_tgid;\n\n\t\tlink = bpf_program__attach_raw_tracepoint(prog, tp_name);\n\t\tif (!ASSERT_OK_PTR(link, \"attach_raw_tp\"))\n\t\t\tgoto cleanup;\n\n\t\t/* trigger test run */\n\t\tif (test_case->trigger) {\n\t\t\tif (!ASSERT_OK(test_case->trigger(test_case), \"test_trigger\"))\n\t\t\t\tgoto cleanup;\n\t\t} else {\n\t\t\tusleep(1);\n\t\t}\n\n\t\tif (data->skip) {\n\t\t\ttest__skip();\n\t\t\tgoto cleanup;\n\t\t}\n\n\t\tif (!ASSERT_FALSE(test_case->fails, \"obj_load_should_fail\"))\n\t\t\tgoto cleanup;\n\n\t\tequal = memcmp(data->out, test_case->output,\n\t\t\t       test_case->output_len) == 0;\n\t\tif (CHECK(!equal, \"check_result\",\n\t\t\t  \"input/output data don't match\\n\")) {\n\t\t\tint j;\n\n\t\t\tfor (j = 0; j < test_case->input_len; j++) {\n\t\t\t\tprintf(\"input byte #%d: 0x%02hhx\\n\",\n\t\t\t\t       j, test_case->input[j]);\n\t\t\t}\n\t\t\tfor (j = 0; j < test_case->output_len; j++) {\n\t\t\t\tprintf(\"output byte #%d: EXP 0x%02hhx GOT 0x%02hhx\\n\",\n\t\t\t\t       j, test_case->output[j], data->out[j]);\n\t\t\t}\n\t\t\tgoto cleanup;\n\t\t}\n\ncleanup:\n\t\tif (mmap_data) {\n\t\t\tCHECK_FAIL(munmap(mmap_data, mmap_sz));\n\t\t\tmmap_data = NULL;\n\t\t}\n\t\tif (use_btfgen)\n\t\t\tremove(test_case->btf_src_file);\n\t\tbpf_link__destroy(link);\n\t\tlink = NULL;\n\t\tbpf_object__close(obj);\n\t}\n}",
        "static int sdsi_certificate_dump(struct sdsi_dev *s)\n{\n\tuint64_t state_certificate[512] = {0};\n\tbool first_instance;\n\tuint64_t previous;": "static int sdsi_certificate_dump(struct sdsi_dev *s)\n{\n\tuint64_t state_certificate[512] = {0};\n\tbool first_instance;\n\tuint64_t previous;\n\tFILE *cert_ptr;\n\tint i, ret, size;\n\n\tret = sdsi_update_registers(s);\n\tif (ret)\n\t\treturn ret;\n\n\tif (!s->regs.en_features.sdsi) {\n\t\tfprintf(stderr, \"SDSi feature is present but not enabled.\");\n\t\tfprintf(stderr, \" Unable to read state certificate\");\n\t\treturn -1;\n\t}\n\n\tret = chdir(s->dev_path);\n\tif (ret == -1) {\n\t\tperror(\"chdir\");\n\t\treturn ret;\n\t}\n\n\tcert_ptr = fopen(\"state_certificate\", \"r\");\n\tif (!cert_ptr) {\n\t\tperror(\"Could not open 'state_certificate' file\");\n\t\treturn -1;\n\t}\n\n\tsize = fread(state_certificate, 1, sizeof(state_certificate), cert_ptr);\n\tif (!size) {\n\t\tfprintf(stderr, \"Could not read 'state_certificate' file\\n\");\n\t\tfclose(cert_ptr);\n\t\treturn -1;\n\t}\n\n\tprintf(\"%3d: 0x%lx\\n\", 0, state_certificate[0]);\n\tprevious = state_certificate[0];\n\tfirst_instance = true;\n\n\tfor (i = 1; i < (int)(round_up(size, sizeof(uint64_t))/sizeof(uint64_t)); i++) {\n\t\tif (state_certificate[i] == previous) {\n\t\t\tif (first_instance) {\n\t\t\t\tputs(\"*\");\n\t\t\t\tfirst_instance = false;\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t\tprintf(\"%3d: 0x%lx\\n\", i, state_certificate[i]);\n\t\tprevious = state_certificate[i];\n\t\tfirst_instance = true;\n\t}\n\tprintf(\"%3d\\n\", i);\n\n\tfclose(cert_ptr);\n\n\treturn 0;\n}",
        "static int da7219_clk_enable(struct snd_pcm_substream *substream)\n{\n\tint ret = 0;\n\tstruct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);\n": "static int da7219_clk_enable(struct snd_pcm_substream *substream)\n{\n\tint ret = 0;\n\tstruct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);\n\n\t/*\n\t * Set wclk to 48000 because the rate constraint of this driver is\n\t * 48000. ADAU7002 spec: \"The ADAU7002 requires a BCLK rate that is\n\t * minimum of 64x the LRCLK sample rate.\" DA7219 is the only clk\n\t * source so for all codecs we have to limit bclk to 64X lrclk.\n\t */\n\tclk_set_rate(da7219_dai_wclk, 48000);\n\tclk_set_rate(da7219_dai_bclk, 48000 * 64);\n\tret = clk_prepare_enable(da7219_dai_bclk);\n\tif (ret < 0) {\n\t\tdev_err(rtd->dev, \"can't enable master clock %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\treturn ret;\n}",
        "static int doc_ecc_decode(struct rs_control *rs, uint8_t *data, uint8_t *ecc)\n{\n\tint i, j, nerr, errpos[8];\n\tuint8_t parity;\n\tuint16_t ds[4], s[5], tmp, errval[8], syn[4];": "static int doc_ecc_decode(struct rs_control *rs, uint8_t *data, uint8_t *ecc)\n{\n\tint i, j, nerr, errpos[8];\n\tuint8_t parity;\n\tuint16_t ds[4], s[5], tmp, errval[8], syn[4];\n\tstruct rs_codec *cd = rs->codec;\n\n\tmemset(syn, 0, sizeof(syn));\n\t/* Convert the ecc bytes into words */\n\tds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8);\n\tds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6);\n\tds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4);\n\tds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2);\n\tparity = ecc[1];\n\n\t/* Initialize the syndrome buffer */\n\tfor (i = 0; i < NROOTS; i++)\n\t\ts[i] = ds[0];\n\t/*\n\t *  Evaluate\n\t *  s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0]\n\t *  where x = alpha^(FCR + i)\n\t */\n\tfor (j = 1; j < NROOTS; j++) {\n\t\tif (ds[j] == 0)\n\t\t\tcontinue;\n\t\ttmp = cd->index_of[ds[j]];\n\t\tfor (i = 0; i < NROOTS; i++)\n\t\t\ts[i] ^= cd->alpha_to[rs_modnn(cd, tmp + (FCR + i) * j)];\n\t}\n\n\t/* Calc syn[i] = s[i] / alpha^(v + i) */\n\tfor (i = 0; i < NROOTS; i++) {\n\t\tif (s[i])\n\t\t\tsyn[i] = rs_modnn(cd, cd->index_of[s[i]] + (NN - FCR - i));\n\t}\n\t/* Call the decoder library */\n\tnerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval);\n\n\t/* Incorrectable errors ? */\n\tif (nerr < 0)\n\t\treturn nerr;\n\n\t/*\n\t * Correct the errors. The bitpositions are a bit of magic,\n\t * but they are given by the design of the de/encoder circuit\n\t * in the DoC ASIC's.\n\t */\n\tfor (i = 0; i < nerr; i++) {\n\t\tint index, bitpos, pos = 1015 - errpos[i];\n\t\tuint8_t val;\n\t\tif (pos >= NB_DATA && pos < 1019)\n\t\t\tcontinue;\n\t\tif (pos < NB_DATA) {\n\t\t\t/* extract bit position (MSB first) */\n\t\t\tpos = 10 * (NB_DATA - 1 - pos) - 6;\n\t\t\t/* now correct the following 10 bits. At most two bytes\n\t\t\t   can be modified since pos is even */\n\t\t\tindex = (pos >> 3) ^ 1;\n\t\t\tbitpos = pos & 7;\n\t\t\tif ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) {\n\t\t\t\tval = (uint8_t) (errval[i] >> (2 + bitpos));\n\t\t\t\tparity ^= val;\n\t\t\t\tif (index < SECTOR_SIZE)\n\t\t\t\t\tdata[index] ^= val;\n\t\t\t}\n\t\t\tindex = ((pos >> 3) + 1) ^ 1;\n\t\t\tbitpos = (bitpos + 10) & 7;\n\t\t\tif (bitpos == 0)\n\t\t\t\tbitpos = 8;\n\t\t\tif ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) {\n\t\t\t\tval = (uint8_t) (errval[i] << (8 - bitpos));\n\t\t\t\tparity ^= val;\n\t\t\t\tif (index < SECTOR_SIZE)\n\t\t\t\t\tdata[index] ^= val;\n\t\t\t}\n\t\t}\n\t}\n\t/* If the parity is wrong, no rescue possible */\n\treturn parity ? -EBADMSG : nerr;\n}",
        "static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)\n{\n\tstruct snd_pcm_runtime *runtime = rec->substream->runtime;\n\tunsigned int reg, val;\n": "static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)\n{\n\tstruct snd_pcm_runtime *runtime = rec->substream->runtime;\n\tunsigned int reg, val;\n\n\tif (rec->needs_silencing && runtime && runtime->dma_area) {\n\t\t/* set up a small silence buffer */\n\t\tmemset(runtime->dma_area, 0, PAGE_SIZE);\n\t\treg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;\n\t\tval = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);\n\t\tsnd_cmipci_write(cm, reg, val);\n\t\n\t\t/* configure for 16 bits, 2 channels, 8 kHz */\n\t\tif (runtime->channels > 2)\n\t\t\tset_dac_channels(cm, rec, 2);\n\t\tspin_lock_irq(&cm->reg_lock);\n\t\tval = snd_cmipci_read(cm, CM_REG_FUNCTRL1);\n\t\tval &= ~(CM_ASFC_MASK << (rec->ch * 3));\n\t\tval |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);\n\t\tsnd_cmipci_write(cm, CM_REG_FUNCTRL1, val);\n\t\tval = snd_cmipci_read(cm, CM_REG_CHFORMAT);\n\t\tval &= ~(CM_CH0FMT_MASK << (rec->ch * 2));\n\t\tval |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);\n\t\tif (cm->can_96k)\n\t\t\tval &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));\n\t\tsnd_cmipci_write(cm, CM_REG_CHFORMAT, val);\n\t\n\t\t/* start stream (we don't need interrupts) */\n\t\tcm->ctrl |= CM_CHEN0 << rec->ch;\n\t\tsnd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);\n\t\tspin_unlock_irq(&cm->reg_lock);\n\n\t\tmsleep(1);\n\n\t\t/* stop and reset stream */\n\t\tspin_lock_irq(&cm->reg_lock);\n\t\tcm->ctrl &= ~(CM_CHEN0 << rec->ch);\n\t\tval = CM_RST_CH0 << rec->ch;\n\t\tsnd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);\n\t\tsnd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);\n\t\tspin_unlock_irq(&cm->reg_lock);\n\n\t\trec->needs_silencing = 0;\n\t}\n}",
        "static int qat_alg_send_message_maybacklog(struct qat_alg_req *req)\n{\n\tstruct qat_instance_backlog *backlog = req->backlog;\n\tstruct adf_etr_ring_data *tx_ring = req->tx_ring;\n\tu32 *fw_req = req->fw_req;": "static int qat_alg_send_message_maybacklog(struct qat_alg_req *req)\n{\n\tstruct qat_instance_backlog *backlog = req->backlog;\n\tstruct adf_etr_ring_data *tx_ring = req->tx_ring;\n\tu32 *fw_req = req->fw_req;\n\n\t/* If any request is already backlogged, then add to backlog list */\n\tif (!list_empty(&backlog->list))\n\t\tgoto enqueue;\n\n\t/* If ring is nearly full, then add to backlog list */\n\tif (adf_ring_nearly_full(tx_ring))\n\t\tgoto enqueue;\n\n\t/* If adding request to HW ring fails, then add to backlog list */\n\tif (adf_send_message(tx_ring, fw_req))\n\t\tgoto enqueue;\n\n\treturn -EINPROGRESS;\n\nenqueue:\n\tqat_alg_backlog_req(req, backlog);\n\n\treturn -EBUSY;\n}",
        "static void check_stack(unsigned long ip, unsigned long *stack)\n{\n\tunsigned long this_size, flags; unsigned long *p, *top, *start;\n\tstatic int tracer_frame;\n\tint frame_size = READ_ONCE(tracer_frame);": "static void check_stack(unsigned long ip, unsigned long *stack)\n{\n\tunsigned long this_size, flags; unsigned long *p, *top, *start;\n\tstatic int tracer_frame;\n\tint frame_size = READ_ONCE(tracer_frame);\n\tint i, x;\n\n\tthis_size = ((unsigned long)stack) & (THREAD_SIZE-1);\n\tthis_size = THREAD_SIZE - this_size;\n\t/* Remove the frame of the tracer */\n\tthis_size -= frame_size;\n\n\tif (this_size <= stack_trace_max_size)\n\t\treturn;\n\n\t/* we do not handle interrupt stacks yet */\n\tif (!object_is_on_stack(stack))\n\t\treturn;\n\n\t/* Can't do this from NMI context (can cause deadlocks) */\n\tif (in_nmi())\n\t\treturn;\n\n\tlocal_irq_save(flags);\n\tarch_spin_lock(&stack_trace_max_lock);\n\n\t/* In case another CPU set the tracer_frame on us */\n\tif (unlikely(!frame_size))\n\t\tthis_size -= tracer_frame;\n\n\t/* a race could have already updated it */\n\tif (this_size <= stack_trace_max_size)\n\t\tgoto out;\n\n\tstack_trace_max_size = this_size;\n\n\tstack_trace_nr_entries = stack_trace_save(stack_dump_trace,\n\t\t\t\t\t       ARRAY_SIZE(stack_dump_trace) - 1,\n\t\t\t\t\t       0);\n\n\t/* Skip over the overhead of the stack tracer itself */\n\tfor (i = 0; i < stack_trace_nr_entries; i++) {\n\t\tif (stack_dump_trace[i] == ip)\n\t\t\tbreak;\n\t}\n\n\t/*\n\t * Some archs may not have the passed in ip in the dump.\n\t * If that happens, we need to show everything.\n\t */\n\tif (i == stack_trace_nr_entries)\n\t\ti = 0;\n\n\t/*\n\t * Now find where in the stack these are.\n\t */\n\tx = 0;\n\tstart = stack;\n\ttop = (unsigned long *)\n\t\t(((unsigned long)start & ~(THREAD_SIZE-1)) + THREAD_SIZE);\n\n\t/*\n\t * Loop through all the entries. One of the entries may\n\t * for some reason be missed on the stack, so we may\n\t * have to account for them. If they are all there, this\n\t * loop will only happen once. This code only takes place\n\t * on a new max, so it is far from a fast path.\n\t */\n\twhile (i < stack_trace_nr_entries) {\n\t\tint found = 0;\n\n\t\tstack_trace_index[x] = this_size;\n\t\tp = start;\n\n\t\tfor (; p < top && i < stack_trace_nr_entries; p++) {\n\t\t\t/*\n\t\t\t * The READ_ONCE_NOCHECK is used to let KASAN know that\n\t\t\t * this is not a stack-out-of-bounds error.\n\t\t\t */\n\t\t\tif ((READ_ONCE_NOCHECK(*p)) == stack_dump_trace[i]) {\n\t\t\t\tstack_dump_trace[x] = stack_dump_trace[i++];\n\t\t\t\tthis_size = stack_trace_index[x++] =\n\t\t\t\t\t(top - p) * sizeof(unsigned long);\n\t\t\t\tfound = 1;\n\t\t\t\t/* Start the search from here */\n\t\t\t\tstart = p + 1;\n\t\t\t\t/*\n\t\t\t\t * We do not want to show the overhead\n\t\t\t\t * of the stack tracer stack in the\n\t\t\t\t * max stack. If we haven't figured\n\t\t\t\t * out what that is, then figure it out\n\t\t\t\t * now.\n\t\t\t\t */\n\t\t\t\tif (unlikely(!tracer_frame)) {\n\t\t\t\t\ttracer_frame = (p - stack) *\n\t\t\t\t\t\tsizeof(unsigned long);\n\t\t\t\t\tstack_trace_max_size -= tracer_frame;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (!found)\n\t\t\ti++;\n\t}\n\n#ifdef ARCH_FTRACE_SHIFT_STACK_TRACER\n\t/*\n\t * Some archs will store the link register before calling\n\t * nested functions. This means the saved return address\n\t * comes after the local storage, and we need to shift\n\t * for that.\n\t */\n\tif (x > 1) {\n\t\tmemmove(&stack_trace_index[0], &stack_trace_index[1],\n\t\t\tsizeof(stack_trace_index[0]) * (x - 1));\n\t\tx--;\n\t}\n#endif\n\n\tstack_trace_nr_entries = x;\n\n\tif (task_stack_end_corrupted(current)) {\n\t\tprint_max_stack();\n\t\tBUG();\n\t}\n\n out:\n\tarch_spin_unlock(&stack_trace_max_lock);\n\tlocal_irq_restore(flags);\n}",
        "static int __init init_kgdboc(void)\n{\n\tint ret;\n\n\t/*": "static int __init init_kgdboc(void)\n{\n\tint ret;\n\n\t/*\n\t * kgdboc is a little bit of an odd \"platform_driver\".  It can be\n\t * up and running long before the platform_driver object is\n\t * created and thus doesn't actually store anything in it.  There's\n\t * only one instance of kgdb so anything is stored as global state.\n\t * The platform_driver is only created so that we can leverage the\n\t * kernel's mechanisms (like -EPROBE_DEFER) to call us when our\n\t * underlying tty is ready.  Here we init our platform driver and\n\t * then create the single kgdboc instance.\n\t */\n\tret = platform_driver_register(&kgdboc_platform_driver);\n\tif (ret)\n\t\treturn ret;\n\n\tkgdboc_pdev = platform_device_alloc(\"kgdboc\", PLATFORM_DEVID_NONE);\n\tif (!kgdboc_pdev) {\n\t\tret = -ENOMEM;\n\t\tgoto err_did_register;\n\t}\n\n\tret = platform_device_add(kgdboc_pdev);\n\tif (!ret)\n\t\treturn 0;\n\n\tplatform_device_put(kgdboc_pdev);\n\nerr_did_register:\n\tplatform_driver_unregister(&kgdboc_platform_driver);\n\treturn ret;\n}",
        "static void coda_setup_iram(struct coda_ctx *ctx)\n{\n\tstruct coda_iram_info *iram_info = &ctx->iram_info;\n\tstruct coda_dev *dev = ctx->dev;\n\tint w64, w128;": "static void coda_setup_iram(struct coda_ctx *ctx)\n{\n\tstruct coda_iram_info *iram_info = &ctx->iram_info;\n\tstruct coda_dev *dev = ctx->dev;\n\tint w64, w128;\n\tint mb_width;\n\tint dbk_bits;\n\tint bit_bits;\n\tint ip_bits;\n\tint me_bits;\n\n\tmemset(iram_info, 0, sizeof(*iram_info));\n\tiram_info->next_paddr = dev->iram.paddr;\n\tiram_info->remaining = dev->iram.size;\n\n\tif (!dev->iram.vaddr)\n\t\treturn;\n\n\tswitch (dev->devtype->product) {\n\tcase CODA_HX4:\n\t\tdbk_bits = CODA7_USE_HOST_DBK_ENABLE;\n\t\tbit_bits = CODA7_USE_HOST_BIT_ENABLE;\n\t\tip_bits = CODA7_USE_HOST_IP_ENABLE;\n\t\tme_bits = CODA7_USE_HOST_ME_ENABLE;\n\t\tbreak;\n\tcase CODA_7541:\n\t\tdbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;\n\t\tbit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;\n\t\tip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;\n\t\tme_bits = CODA7_USE_HOST_ME_ENABLE | CODA7_USE_ME_ENABLE;\n\t\tbreak;\n\tcase CODA_960:\n\t\tdbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;\n\t\tbit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;\n\t\tip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;\n\t\tme_bits = 0;\n\t\tbreak;\n\tdefault: /* CODA_DX6 */\n\t\treturn;\n\t}\n\n\tif (ctx->inst_type == CODA_INST_ENCODER) {\n\t\tstruct coda_q_data *q_data_src;\n\n\t\tq_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);\n\t\tmb_width = DIV_ROUND_UP(q_data_src->rect.width, 16);\n\t\tw128 = mb_width * 128;\n\t\tw64 = mb_width * 64;\n\n\t\t/* Prioritize in case IRAM is too small for everything */\n\t\tif (dev->devtype->product == CODA_HX4 ||\n\t\t    dev->devtype->product == CODA_7541) {\n\t\t\tiram_info->search_ram_size = round_up(mb_width * 16 *\n\t\t\t\t\t\t\t      36 + 2048, 1024);\n\t\t\tiram_info->search_ram_paddr = coda_iram_alloc(iram_info,\n\t\t\t\t\t\tiram_info->search_ram_size);\n\t\t\tif (!iram_info->search_ram_paddr) {\n\t\t\t\tpr_err(\"IRAM is smaller than the search ram size\\n\");\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tiram_info->axi_sram_use |= me_bits;\n\t\t}\n\n\t\t/* Only H.264BP and H.263P3 are considered */\n\t\tiram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);\n\t\tiram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);\n\t\tif (!iram_info->buf_dbk_c_use)\n\t\t\tgoto out;\n\t\tiram_info->axi_sram_use |= dbk_bits;\n\n\t\tiram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);\n\t\tif (!iram_info->buf_bit_use)\n\t\t\tgoto out;\n\t\tiram_info->axi_sram_use |= bit_bits;\n\n\t\tiram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);\n\t\tif (!iram_info->buf_ip_ac_dc_use)\n\t\t\tgoto out;\n\t\tiram_info->axi_sram_use |= ip_bits;\n\n\t\t/* OVL and BTP disabled for encoder */\n\t} else if (ctx->inst_type == CODA_INST_DECODER) {\n\t\tstruct coda_q_data *q_data_dst;\n\n\t\tq_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);\n\t\tmb_width = DIV_ROUND_UP(q_data_dst->width, 16);\n\t\tw128 = mb_width * 128;\n\n\t\tiram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);\n\t\tiram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);\n\t\tif (!iram_info->buf_dbk_c_use)\n\t\t\tgoto out;\n\t\tiram_info->axi_sram_use |= dbk_bits;\n\n\t\tiram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);\n\t\tif (!iram_info->buf_bit_use)\n\t\t\tgoto out;\n\t\tiram_info->axi_sram_use |= bit_bits;\n\n\t\tiram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);\n\t\tif (!iram_info->buf_ip_ac_dc_use)\n\t\t\tgoto out;\n\t\tiram_info->axi_sram_use |= ip_bits;\n\n\t\t/* OVL and BTP unused as there is no VC1 support yet */\n\t}\n\nout:\n\tif (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))\n\t\tcoda_dbg(1, ctx, \"IRAM smaller than needed\\n\");\n\n\tif (dev->devtype->product == CODA_HX4 ||\n\t    dev->devtype->product == CODA_7541) {\n\t\t/* TODO - Enabling these causes picture errors on CODA7541 */\n\t\tif (ctx->inst_type == CODA_INST_DECODER) {\n\t\t\t/* fw 1.4.50 */\n\t\t\tiram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |\n\t\t\t\t\t\t     CODA7_USE_IP_ENABLE);\n\t\t} else {\n\t\t\t/* fw 13.4.29 */\n\t\t\tiram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |\n\t\t\t\t\t\t     CODA7_USE_HOST_DBK_ENABLE |\n\t\t\t\t\t\t     CODA7_USE_IP_ENABLE |\n\t\t\t\t\t\t     CODA7_USE_DBK_ENABLE);\n\t\t}\n\t}\n}",
        "static unsigned int cake_drop(struct Qdisc *sch, struct sk_buff **to_free)\n{\n\tstruct cake_sched_data *q = qdisc_priv(sch);\n\tktime_t now = ktime_get();\n\tu32 idx = 0, tin = 0, len;": "static unsigned int cake_drop(struct Qdisc *sch, struct sk_buff **to_free)\n{\n\tstruct cake_sched_data *q = qdisc_priv(sch);\n\tktime_t now = ktime_get();\n\tu32 idx = 0, tin = 0, len;\n\tstruct cake_heap_entry qq;\n\tstruct cake_tin_data *b;\n\tstruct cake_flow *flow;\n\tstruct sk_buff *skb;\n\n\tif (!q->overflow_timeout) {\n\t\tint i;\n\t\t/* Build fresh max-heap */\n\t\tfor (i = CAKE_MAX_TINS * CAKE_QUEUES / 2; i >= 0; i--)\n\t\t\tcake_heapify(q, i);\n\t}\n\tq->overflow_timeout = 65535;\n\n\t/* select longest queue for pruning */\n\tqq  = q->overflow_heap[0];\n\ttin = qq.t;\n\tidx = qq.b;\n\n\tb = &q->tins[tin];\n\tflow = &b->flows[idx];\n\tskb = dequeue_head(flow);\n\tif (unlikely(!skb)) {\n\t\t/* heap has gone wrong, rebuild it next time */\n\t\tq->overflow_timeout = 0;\n\t\treturn idx + (tin << 16);\n\t}\n\n\tif (cobalt_queue_full(&flow->cvars, &b->cparams, now))\n\t\tb->unresponsive_flow_count++;\n\n\tlen = qdisc_pkt_len(skb);\n\tq->buffer_used      -= skb->truesize;\n\tb->backlogs[idx]    -= len;\n\tb->tin_backlog      -= len;\n\tsch->qstats.backlog -= len;\n\tqdisc_tree_reduce_backlog(sch, 1, len);\n\n\tflow->dropped++;\n\tb->tin_dropped++;\n\tsch->qstats.drops++;\n\n\tif (q->rate_flags & CAKE_FLAG_INGRESS)\n\t\tcake_advance_shaper(q, b, skb, now, true);\n\n\t__qdisc_drop(skb, to_free);\n\tsch->q.qlen--;\n\n\tcake_heapify(q, 0);\n\n\treturn idx + (tin << 16);\n}",
        "static void snd_soc_tplg_test_load_empty_tplg_bad_magic(struct kunit *test)\n{\n\tstruct kunit_soc_component *kunit_comp;\n\tstruct tplg_tmpl_001 *data;\n\tint size;": "static void snd_soc_tplg_test_load_empty_tplg_bad_magic(struct kunit *test)\n{\n\tstruct kunit_soc_component *kunit_comp;\n\tstruct tplg_tmpl_001 *data;\n\tint size;\n\tint ret;\n\n\t/* prepare */\n\tkunit_comp = kunit_kzalloc(test, sizeof(*kunit_comp), GFP_KERNEL);\n\tKUNIT_EXPECT_NOT_ERR_OR_NULL(test, kunit_comp);\n\tkunit_comp->kunit = test;\n\tkunit_comp->expect = -EINVAL; /* expect failure */\n\n\tsize = sizeof(tplg_tmpl_empty);\n\tdata = kunit_kzalloc(kunit_comp->kunit, size, GFP_KERNEL);\n\tKUNIT_EXPECT_NOT_ERR_OR_NULL(kunit_comp->kunit, data);\n\n\tmemcpy(data, &tplg_tmpl_empty, sizeof(tplg_tmpl_empty));\n\t/*\n\t * override abi\n\t * any value != magic number is wrong\n\t */\n\tdata->header.magic = cpu_to_le32(SND_SOC_TPLG_MAGIC + 1);\n\n\tkunit_comp->fw.data = (u8 *)data;\n\tkunit_comp->fw.size = size;\n\n\tkunit_comp->card.dev = test_dev,\n\tkunit_comp->card.name = \"kunit-card\",\n\tkunit_comp->card.owner = THIS_MODULE,\n\tkunit_comp->card.dai_link = kunit_dai_links,\n\tkunit_comp->card.num_links = ARRAY_SIZE(kunit_dai_links),\n\tkunit_comp->card.fully_routed = true,\n\n\t/* run test */\n\tret = snd_soc_register_card(&kunit_comp->card);\n\tif (ret != 0 && ret != -EPROBE_DEFER)\n\t\tKUNIT_FAIL(test, \"Failed to register card\");\n\n\tret = snd_soc_component_initialize(&kunit_comp->comp, &test_component, test_dev);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\tret = snd_soc_add_component(&kunit_comp->comp, NULL, 0);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\t/* cleanup */\n\tret = snd_soc_unregister_card(&kunit_comp->card);\n\tKUNIT_EXPECT_EQ(test, 0, ret);\n\n\tsnd_soc_unregister_component(test_dev);\n}",
        "static int get_device_capabilities(struct drxk_state *state)\n{\n\tu16 sio_pdr_ohw_cfg = 0;\n\tu32 sio_top_jtagid_lo = 0;\n\tint status;": "static int get_device_capabilities(struct drxk_state *state)\n{\n\tu16 sio_pdr_ohw_cfg = 0;\n\tu32 sio_top_jtagid_lo = 0;\n\tint status;\n\tconst char *spin = \"\";\n\n\tdprintk(1, \"\\n\");\n\n\t/* driver 0.9.0 */\n\t/* stop lock indicator process */\n\tstatus = write16(state, SCU_RAM_GPIO__A,\n\t\t\t SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);\n\tif (status < 0)\n\t\tgoto error;\n\tstatus = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);\n\tif (status < 0)\n\t\tgoto error;\n\n\tswitch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {\n\tcase 0:\n\t\t/* ignore (bypass ?) */\n\t\tbreak;\n\tcase 1:\n\t\t/* 27 MHz */\n\t\tstate->m_osc_clock_freq = 27000;\n\t\tbreak;\n\tcase 2:\n\t\t/* 20.25 MHz */\n\t\tstate->m_osc_clock_freq = 20250;\n\t\tbreak;\n\tcase 3:\n\t\t/* 4 MHz */\n\t\tstate->m_osc_clock_freq = 20250;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"Clock Frequency is unknown\\n\");\n\t\treturn -EINVAL;\n\t}\n\t/*\n\t\tDetermine device capabilities\n\t\tBased on pinning v14\n\t\t*/\n\tstatus = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);\n\tif (status < 0)\n\t\tgoto error;\n\n\tpr_info(\"status = 0x%08x\\n\", sio_top_jtagid_lo);\n\n\t/* driver 0.9.0 */\n\tswitch ((sio_top_jtagid_lo >> 29) & 0xF) {\n\tcase 0:\n\t\tstate->m_device_spin = DRXK_SPIN_A1;\n\t\tspin = \"A1\";\n\t\tbreak;\n\tcase 2:\n\t\tstate->m_device_spin = DRXK_SPIN_A2;\n\t\tspin = \"A2\";\n\t\tbreak;\n\tcase 3:\n\t\tstate->m_device_spin = DRXK_SPIN_A3;\n\t\tspin = \"A3\";\n\t\tbreak;\n\tdefault:\n\t\tstate->m_device_spin = DRXK_SPIN_UNKNOWN;\n\t\tstatus = -EINVAL;\n\t\tpr_err(\"Spin %d unknown\\n\", (sio_top_jtagid_lo >> 29) & 0xF);\n\t\tgoto error2;\n\t}\n\tswitch ((sio_top_jtagid_lo >> 12) & 0xFF) {\n\tcase 0x13:\n\t\t/* typeId = DRX3913K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = false;\n\t\tstate->m_has_audio = false;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = true;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = false;\n\t\tstate->m_has_gpio1 = false;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x15:\n\t\t/* typeId = DRX3915K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = false;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = false;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x16:\n\t\t/* typeId = DRX3916K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = false;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = false;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x18:\n\t\t/* typeId = DRX3918K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = true;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = false;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x21:\n\t\t/* typeId = DRX3921K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = true;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = true;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x23:\n\t\t/* typeId = DRX3923K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = true;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = true;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x25:\n\t\t/* typeId = DRX3925K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = true;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = true;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tcase 0x26:\n\t\t/* typeId = DRX3926K_TYPE_ID */\n\t\tstate->m_has_lna = false;\n\t\tstate->m_has_oob = false;\n\t\tstate->m_has_atv = true;\n\t\tstate->m_has_audio = false;\n\t\tstate->m_has_dvbt = true;\n\t\tstate->m_has_dvbc = true;\n\t\tstate->m_has_sawsw = true;\n\t\tstate->m_has_gpio2 = true;\n\t\tstate->m_has_gpio1 = true;\n\t\tstate->m_has_irqn = false;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"DeviceID 0x%02x not supported\\n\",\n\t\t\t((sio_top_jtagid_lo >> 12) & 0xFF));\n\t\tstatus = -EINVAL;\n\t\tgoto error2;\n\t}\n\n\tpr_info(\"detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\\n\",\n\t       ((sio_top_jtagid_lo >> 12) & 0xFF), spin,\n\t       state->m_osc_clock_freq / 1000,\n\t       state->m_osc_clock_freq % 1000);\n\nerror:\n\tif (status < 0)\n\t\tpr_err(\"Error %d on %s\\n\", status, __func__);\n\nerror2:\n\treturn status;\n}",
        "static void lock_zspage(struct zspage *zspage)\n{\n\tstruct page *curr_page, *page;\n\n\t/*": "static void lock_zspage(struct zspage *zspage)\n{\n\tstruct page *curr_page, *page;\n\n\t/*\n\t * Pages we haven't locked yet can be migrated off the list while we're\n\t * trying to lock them, so we need to be careful and only attempt to\n\t * lock each page under migrate_read_lock(). Otherwise, the page we lock\n\t * may no longer belong to the zspage. This means that we may wait for\n\t * the wrong page to unlock, so we must take a reference to the page\n\t * prior to waiting for it to unlock outside migrate_read_lock().\n\t */\n\twhile (1) {\n\t\tmigrate_read_lock(zspage);\n\t\tpage = get_first_page(zspage);\n\t\tif (trylock_page(page))\n\t\t\tbreak;\n\t\tget_page(page);\n\t\tmigrate_read_unlock(zspage);\n\t\twait_on_page_locked(page);\n\t\tput_page(page);\n\t}\n\n\tcurr_page = page;\n\twhile ((page = get_next_page(curr_page))) {\n\t\tif (trylock_page(page)) {\n\t\t\tcurr_page = page;\n\t\t} else {\n\t\t\tget_page(page);\n\t\t\tmigrate_read_unlock(zspage);\n\t\t\twait_on_page_locked(page);\n\t\t\tput_page(page);\n\t\t\tmigrate_read_lock(zspage);\n\t\t}\n\t}\n\tmigrate_read_unlock(zspage);\n}",
        "static int cxd2880_set_ber_per_period_t(struct dvb_frontend *fe)\n{\n\tint ret;\n\tstruct cxd2880_priv *priv;\n\tstruct cxd2880_dvbt_tpsinfo info;": "static int cxd2880_set_ber_per_period_t(struct dvb_frontend *fe)\n{\n\tint ret;\n\tstruct cxd2880_priv *priv;\n\tstruct cxd2880_dvbt_tpsinfo info;\n\tenum cxd2880_dtv_bandwidth bw;\n\tu32 pre_ber_rate = 0;\n\tu32 post_ber_rate = 0;\n\tu32 ucblock_rate = 0;\n\tu32 mes_exp = 0;\n\tstatic const int cr_table[5] = {31500, 42000, 47250, 52500, 55125};\n\tstatic const int denominator_tbl[4] = {125664, 129472, 137088, 152320};\n\n\tif (!fe) {\n\t\tpr_err(\"invalid arg\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tpriv = fe->demodulator_priv;\n\tbw = priv->dvbt_tune_param.bandwidth;\n\n\tret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd,\n\t\t\t\t\t       &info);\n\tif (ret) {\n\t\tpr_err(\"tps monitor error ret = %d\\n\", ret);\n\t\tinfo.hierarchy = CXD2880_DVBT_HIERARCHY_NON;\n\t\tinfo.constellation = CXD2880_DVBT_CONSTELLATION_QPSK;\n\t\tinfo.guard = CXD2880_DVBT_GUARD_1_4;\n\t\tinfo.rate_hp = CXD2880_DVBT_CODERATE_1_2;\n\t\tinfo.rate_lp = CXD2880_DVBT_CODERATE_1_2;\n\t}\n\n\tif (info.hierarchy == CXD2880_DVBT_HIERARCHY_NON) {\n\t\tpre_ber_rate = 63000000 * bw * (info.constellation * 2 + 2) /\n\t\t\t       denominator_tbl[info.guard];\n\n\t\tpost_ber_rate =\t1000 * cr_table[info.rate_hp] * bw *\n\t\t\t\t(info.constellation * 2 + 2) /\n\t\t\t\tdenominator_tbl[info.guard];\n\n\t\tucblock_rate = 875 * cr_table[info.rate_hp] * bw *\n\t\t\t       (info.constellation * 2 + 2) /\n\t\t\t       denominator_tbl[info.guard];\n\t} else {\n\t\tu8 data = 0;\n\t\tstruct cxd2880_tnrdmd *tnrdmd = &priv->tnrdmd;\n\n\t\tret = tnrdmd->io->write_reg(tnrdmd->io,\n\t\t\t\t\t    CXD2880_IO_TGT_DMD,\n\t\t\t\t\t    0x00, 0x10);\n\t\tif (!ret) {\n\t\t\tret = tnrdmd->io->read_regs(tnrdmd->io,\n\t\t\t\t\t\t    CXD2880_IO_TGT_DMD,\n\t\t\t\t\t\t    0x67, &data, 1);\n\t\t\tif (ret)\n\t\t\t\tdata = 0x00;\n\t\t} else {\n\t\t\tdata = 0x00;\n\t\t}\n\n\t\tif (data & 0x01) { /* Low priority */\n\t\t\tpre_ber_rate =\n\t\t\t\t63000000 * bw * (info.constellation * 2 + 2) /\n\t\t\t\tdenominator_tbl[info.guard];\n\n\t\t\tpost_ber_rate = 1000 * cr_table[info.rate_lp] * bw *\n\t\t\t\t\t(info.constellation * 2 + 2) /\n\t\t\t\t\tdenominator_tbl[info.guard];\n\n\t\t\tucblock_rate = (1000 * 7 / 8) *\tcr_table[info.rate_lp] *\n\t\t\t\t       bw * (info.constellation * 2 + 2) /\n\t\t\t\t       denominator_tbl[info.guard];\n\t\t} else { /* High priority */\n\t\t\tpre_ber_rate =\n\t\t\t\t63000000 * bw * 2 / denominator_tbl[info.guard];\n\n\t\t\tpost_ber_rate = 1000 * cr_table[info.rate_hp] * bw * 2 /\n\t\t\t\t\tdenominator_tbl[info.guard];\n\n\t\t\tucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_hp] *\n\t\t\t\t\tbw * 2 / denominator_tbl[info.guard];\n\t\t}\n\t}\n\n\tmes_exp = pre_ber_rate < 8192 ? 8 : intlog2(pre_ber_rate) >> 24;\n\tpriv->pre_ber_interval =\n\t\t((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /\n\t\tpre_ber_rate;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,\n\t\t\t       mes_exp == 8 ? 0 : mes_exp - 12);\n\n\tmes_exp = intlog2(post_ber_rate) >> 24;\n\tpriv->post_ber_interval =\n\t\t((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /\n\t\tpost_ber_rate;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,\n\t\t\t       mes_exp);\n\n\tmes_exp = intlog2(ucblock_rate) >> 24;\n\tpriv->ucblock_interval =\n\t\t((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /\n\t\tucblock_rate;\n\tcxd2880_tnrdmd_set_cfg(&priv->tnrdmd,\n\t\t\t       CXD2880_TNRDMD_CFG_DVBT_PER_MES,\n\t\t\t       mes_exp);\n\n\treturn 0;\n}",
        "static void bnx2x_hc_int_disable(struct bnx2x *bp)\n{\n\tint port = BP_PORT(bp);\n\tu32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;\n\tu32 val = REG_RD(bp, addr);": "static void bnx2x_hc_int_disable(struct bnx2x *bp)\n{\n\tint port = BP_PORT(bp);\n\tu32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;\n\tu32 val = REG_RD(bp, addr);\n\n\t/* in E1 we must use only PCI configuration space to disable\n\t * MSI/MSIX capability\n\t * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block\n\t */\n\tif (CHIP_IS_E1(bp)) {\n\t\t/* Since IGU_PF_CONF_MSI_MSIX_EN still always on\n\t\t * Use mask register to prevent from HC sending interrupts\n\t\t * after we exit the function\n\t\t */\n\t\tREG_WR(bp, HC_REG_INT_MASK + port*4, 0);\n\n\t\tval &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |\n\t\t\t HC_CONFIG_0_REG_INT_LINE_EN_0 |\n\t\t\t HC_CONFIG_0_REG_ATTN_BIT_EN_0);\n\t} else\n\t\tval &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |\n\t\t\t HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |\n\t\t\t HC_CONFIG_0_REG_INT_LINE_EN_0 |\n\t\t\t HC_CONFIG_0_REG_ATTN_BIT_EN_0);\n\n\tDP(NETIF_MSG_IFDOWN,\n\t   \"write %x to HC %d (addr 0x%x)\\n\",\n\t   val, port, addr);\n\n\tREG_WR(bp, addr, val);\n\tif (REG_RD(bp, addr) != val)\n\t\tBNX2X_ERR(\"BUG! Proper val not read from IGU!\\n\");\n}",
        "static int pcnet_config(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct pcnet_dev *info = PRIV(dev);\n    int start_pg, stop_pg, cm_offset;": "static int pcnet_config(struct pcmcia_device *link)\n{\n    struct net_device *dev = link->priv;\n    struct pcnet_dev *info = PRIV(dev);\n    int start_pg, stop_pg, cm_offset;\n    int has_shmem = 0;\n    struct hw_info *local_hw_info;\n\n    dev_dbg(&link->dev, \"pcnet_config\\n\");\n\n    local_hw_info = pcnet_try_config(link, &has_shmem, 0);\n    if (!local_hw_info) {\n\t    /* check whether forcing io_lines to 16 helps... */\n\t    pcmcia_disable_device(link);\n\t    local_hw_info = pcnet_try_config(link, &has_shmem, 1);\n\t    if (local_hw_info == NULL) {\n\t\t    dev_notice(&link->dev, \"unable to read hardware net\"\n\t\t\t    \" address for io base %#3lx\\n\", dev->base_addr);\n\t\t    goto failed;\n\t    }\n    }\n\n    info->flags = local_hw_info->flags;\n    /* Check for user overrides */\n    info->flags |= (delay_output) ? DELAY_OUTPUT : 0;\n    if ((link->manf_id == MANFID_SOCKET) &&\n\t((link->card_id == PRODID_SOCKET_LPE) ||\n\t (link->card_id == PRODID_SOCKET_LPE_CF) ||\n\t (link->card_id == PRODID_SOCKET_EIO)))\n\tinfo->flags &= ~USE_BIG_BUF;\n    if (!use_big_buf)\n\tinfo->flags &= ~USE_BIG_BUF;\n\n    if (info->flags & USE_BIG_BUF) {\n\tstart_pg = SOCKET_START_PG;\n\tstop_pg = SOCKET_STOP_PG;\n\tcm_offset = 0x10000;\n    } else {\n\tstart_pg = PCNET_START_PG;\n\tstop_pg = PCNET_STOP_PG;\n\tcm_offset = 0;\n    }\n\n    /* has_shmem is ignored if use_shmem != -1 */\n    if ((use_shmem == 0) || (!has_shmem && (use_shmem == -1)) ||\n\t(setup_shmem_window(link, start_pg, stop_pg, cm_offset) != 0))\n\tsetup_dma_config(link, start_pg, stop_pg);\n\n    ei_status.name = \"NE2000\";\n    ei_status.word16 = 1;\n    ei_status.reset_8390 = pcnet_reset_8390;\n\n    if (info->flags & (IS_DL10019|IS_DL10022))\n\tmii_phy_probe(dev);\n\n    SET_NETDEV_DEV(dev, &link->dev);\n\n    if (register_netdev(dev) != 0) {\n\tpr_notice(\"register_netdev() failed\\n\");\n\tgoto failed;\n    }\n\n    if (info->flags & (IS_DL10019|IS_DL10022)) {\n\tu_char id = inb(dev->base_addr + 0x1a);\n\tnetdev_info(dev, \"NE2000 (DL100%d rev %02x): \",\n\t\t    (info->flags & IS_DL10022) ? 22 : 19, id);\n\tif (info->pna_phy)\n\t    pr_cont(\"PNA, \");\n    } else {\n\tnetdev_info(dev, \"NE2000 Compatible: \");\n    }\n    pr_cont(\"io %#3lx, irq %d,\", dev->base_addr, dev->irq);\n    if (info->flags & USE_SHMEM)\n\tpr_cont(\" mem %#5lx,\", dev->mem_start);\n    if (info->flags & HAS_MISC_REG)\n\tpr_cont(\" %s xcvr,\", if_names[dev->if_port]);\n    pr_cont(\" hw_addr %pM\\n\", dev->dev_addr);\n    return 0;\n\nfailed:\n    pcnet_release(link);\n    return -ENODEV;\n} /* pcnet_config */\n\nstatic void pcnet_release(struct pcmcia_device *link)\n{\n\tstruct pcnet_dev *info = PRIV(link->priv);\n\n\tdev_dbg(&link->dev, \"pcnet_release\\n\");\n\n\tif (info->flags & USE_SHMEM)\n\t\tiounmap(info->base);\n\n\tpcmcia_disable_device(link);\n}",
        "static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)\n{\n\tconst struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;\n\tint is_isoc = hs_ep->isochronous;\n\tunsigned int maxsize;": "static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)\n{\n\tconst struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;\n\tint is_isoc = hs_ep->isochronous;\n\tunsigned int maxsize;\n\tu32 mps = hs_ep->ep.maxpacket;\n\tint dir_in = hs_ep->dir_in;\n\n\tif (is_isoc)\n\t\tmaxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :\n\t\t\t\t\t   DEV_DMA_ISOC_RX_NBYTES_LIMIT) *\n\t\t\t\t\t   MAX_DMA_DESC_NUM_HS_ISOC;\n\telse\n\t\tmaxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;\n\n\t/* Interrupt OUT EP with mps not multiple of 4 */\n\tif (hs_ep->index)\n\t\tif (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))\n\t\t\tmaxsize = mps * MAX_DMA_DESC_NUM_GENERIC;\n\n\treturn maxsize;\n}",
        "static void stk1135_configure_clock(struct gspca_dev *gspca_dev)\n{\n\t/* configure SCLKOUT */\n\treg_w(gspca_dev, STK1135_REG_TMGEN, 0x12);\n\t/* set 1 clock per pixel */": "static void stk1135_configure_clock(struct gspca_dev *gspca_dev)\n{\n\t/* configure SCLKOUT */\n\treg_w(gspca_dev, STK1135_REG_TMGEN, 0x12);\n\t/* set 1 clock per pixel */\n\t/* and positive edge clocked pulse high when pixel counter = 0 */\n\treg_w(gspca_dev, STK1135_REG_TCP1 + 0, 0x41);\n\treg_w(gspca_dev, STK1135_REG_TCP1 + 1, 0x00);\n\treg_w(gspca_dev, STK1135_REG_TCP1 + 2, 0x00);\n\treg_w(gspca_dev, STK1135_REG_TCP1 + 3, 0x00);\n\n\t/* enable CLKOUT for sensor */\n\treg_w(gspca_dev, STK1135_REG_SENSO + 0, 0x10);\n\t/* disable STOP clock */\n\treg_w(gspca_dev, STK1135_REG_SENSO + 1, 0x00);\n\t/* set lower 8 bits of PLL feedback divider */\n\treg_w(gspca_dev, STK1135_REG_SENSO + 3, 0x07);\n\t/* set other PLL parameters */\n\treg_w(gspca_dev, STK1135_REG_PLLFD, 0x06);\n\t/* enable timing generator */\n\treg_w(gspca_dev, STK1135_REG_TMGEN, 0x80);\n\t/* enable PLL */\n\treg_w(gspca_dev, STK1135_REG_SENSO + 2, 0x04);\n\n\t/* set serial interface clock divider (30MHz/0x1f*16+2) = 60240 kHz) */\n\treg_w(gspca_dev, STK1135_REG_SICTL + 2, 0x1f);\n\n\t/* wait a while for sensor to catch up */\n\tudelay(1000);\n}",
        "static void htab_map_free(struct bpf_map *map)\n{\n\tstruct bpf_htab *htab = container_of(map, struct bpf_htab, map);\n\tint i;\n": "static void htab_map_free(struct bpf_map *map)\n{\n\tstruct bpf_htab *htab = container_of(map, struct bpf_htab, map);\n\tint i;\n\n\t/* bpf_free_used_maps() or close(map_fd) will trigger this map_free callback.\n\t * bpf_free_used_maps() is called after bpf prog is no longer executing.\n\t * There is no need to synchronize_rcu() here to protect map elements.\n\t */\n\n\t/* some of free_htab_elem() callbacks for elements of this map may\n\t * not have executed. Wait for them.\n\t */\n\trcu_barrier();\n\tif (!htab_is_prealloc(htab)) {\n\t\tdelete_all_elements(htab);\n\t} else {\n\t\thtab_free_prealloced_kptrs(htab);\n\t\tprealloc_destroy(htab);\n\t}\n\n\tbpf_map_free_kptr_off_tab(map);\n\tfree_percpu(htab->extra_elems);\n\tbpf_map_area_free(htab->buckets);\n\tfor (i = 0; i < HASHTAB_MAP_LOCK_COUNT; i++)\n\t\tfree_percpu(htab->map_locked[i]);\n\tlockdep_unregister_key(&htab->lockdep_key);\n\tkfree(htab);\n}",
        "static int try_loader(struct gen_loader_opts *gen)\n{\n\tstruct bpf_load_and_run_opts opts = {};\n\tstruct bpf_loader_ctx *ctx;\n\tint ctx_sz = sizeof(*ctx) + 64 * max(sizeof(struct bpf_map_desc),": "static int try_loader(struct gen_loader_opts *gen)\n{\n\tstruct bpf_load_and_run_opts opts = {};\n\tstruct bpf_loader_ctx *ctx;\n\tint ctx_sz = sizeof(*ctx) + 64 * max(sizeof(struct bpf_map_desc),\n\t\t\t\t\t     sizeof(struct bpf_prog_desc));\n\tint log_buf_sz = (1u << 24) - 1;\n\tint err, fds_before, fd_delta;\n\tchar *log_buf = NULL;\n\n\tctx = alloca(ctx_sz);\n\tmemset(ctx, 0, ctx_sz);\n\tctx->sz = ctx_sz;\n\tif (verifier_logs) {\n\t\tctx->log_level = 1 + 2 + 4;\n\t\tctx->log_size = log_buf_sz;\n\t\tlog_buf = malloc(log_buf_sz);\n\t\tif (!log_buf)\n\t\t\treturn -ENOMEM;\n\t\tctx->log_buf = (long) log_buf;\n\t}\n\topts.ctx = ctx;\n\topts.data = gen->data;\n\topts.data_sz = gen->data_sz;\n\topts.insns = gen->insns;\n\topts.insns_sz = gen->insns_sz;\n\tfds_before = count_open_fds();\n\terr = bpf_load_and_run(&opts);\n\tfd_delta = count_open_fds() - fds_before;\n\tif (err < 0 || verifier_logs) {\n\t\tfprintf(stderr, \"err %d\\n%s\\n%s\", err, opts.errstr, log_buf);\n\t\tif (fd_delta && err < 0)\n\t\t\tfprintf(stderr, \"loader prog leaked %d FDs\\n\",\n\t\t\t\tfd_delta);\n\t}\n\tfree(log_buf);\n\treturn err;\n}",
        "static inline void schedule_debug(struct task_struct *prev, bool preempt)\n{\n#ifdef CONFIG_SCHED_STACK_END_CHECK\n\tif (task_stack_end_corrupted(prev))\n\t\tpanic(\"corrupted stack end detected inside scheduler\\n\");": "static inline void schedule_debug(struct task_struct *prev, bool preempt)\n{\n#ifdef CONFIG_SCHED_STACK_END_CHECK\n\tif (task_stack_end_corrupted(prev))\n\t\tpanic(\"corrupted stack end detected inside scheduler\\n\");\n\n\tif (task_scs_end_corrupted(prev))\n\t\tpanic(\"corrupted shadow stack detected inside scheduler\\n\");\n#endif\n\n#ifdef CONFIG_DEBUG_ATOMIC_SLEEP\n\tif (!preempt && READ_ONCE(prev->__state) && prev->non_block_count) {\n\t\tprintk(KERN_ERR \"BUG: scheduling in a non-blocking section: %s/%d/%i\\n\",\n\t\t\tprev->comm, prev->pid, prev->non_block_count);\n\t\tdump_stack();\n\t\tadd_taint(TAINT_WARN, LOCKDEP_STILL_OK);\n\t}\n#endif\n\n\tif (unlikely(in_atomic_preempt_off())) {\n\t\t__schedule_bug(prev);\n\t\tpreempt_count_set(PREEMPT_DISABLED);\n\t}\n\trcu_sleep_check();\n\tSCHED_WARN_ON(ct_state() == CONTEXT_USER);\n\n\tprofile_hit(SCHED_PROFILING, __builtin_return_address(0));\n\n\tschedstat_inc(this_rq()->sched_count);\n}",
        "static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)\n{\n\tint ret = 0;\n\tunsigned int data_len, i;\n\tstruct i2c_msg *msg = qup->msg;": "static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)\n{\n\tint ret = 0;\n\tunsigned int data_len, i;\n\tstruct i2c_msg *msg = qup->msg;\n\tstruct qup_i2c_block *blk = &qup->blk;\n\tu8 *msg_buf = msg->buf;\n\n\tqup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;\n\tqup_i2c_set_blk_data(qup, msg);\n\n\tfor (i = 0; i < blk->count; i++) {\n\t\tdata_len =  qup_i2c_get_data_len(qup);\n\t\tblk->pos = i;\n\t\tblk->cur_tx_tags = blk->tags;\n\t\tblk->cur_blk_len = data_len;\n\t\tblk->tx_tag_len =\n\t\t\tqup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);\n\n\t\tblk->cur_data = msg_buf;\n\n\t\tif (is_rx) {\n\t\t\tblk->total_tx_len = blk->tx_tag_len;\n\t\t\tblk->rx_tag_len = 2;\n\t\t\tblk->total_rx_len = blk->rx_tag_len + data_len;\n\t\t} else {\n\t\t\tblk->total_tx_len = blk->tx_tag_len + data_len;\n\t\t\tblk->total_rx_len = 0;\n\t\t}\n\n\t\tret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,\n\t\t\t\t\t   !qup->is_last || i < blk->count - 1);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/* Handle SMBus block read length */\n\t\tif (qup_i2c_check_msg_len(msg) && msg->len == 1 &&\n\t\t    !qup->is_smbus_read) {\n\t\t\tif (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)\n\t\t\t\treturn -EPROTO;\n\n\t\t\tmsg->len = msg->buf[0];\n\t\t\tqup->is_smbus_read = true;\n\t\t\tret = qup_i2c_xfer_v2_msg(qup, msg_id, true);\n\t\t\tqup->is_smbus_read = false;\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\tmsg->len += 1;\n\t\t}\n\n\t\tmsg_buf += data_len;\n\t\tblk->data_len -= qup->blk_xfer_limit;\n\t}\n\n\treturn ret;\n}",
        "static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)\n{\n\tstruct cmng_init_input input;\n\tmemset(&input, 0, sizeof(struct cmng_init_input));\n": "static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)\n{\n\tstruct cmng_init_input input;\n\tmemset(&input, 0, sizeof(struct cmng_init_input));\n\n\tinput.port_rate = bp->link_vars.line_speed;\n\n\tif (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {\n\t\tint vn;\n\n\t\t/* read mf conf from shmem */\n\t\tif (read_cfg)\n\t\t\tbnx2x_read_mf_cfg(bp);\n\n\t\t/* vn_weight_sum and enable fairness if not 0 */\n\t\tbnx2x_calc_vn_min(bp, &input);\n\n\t\t/* calculate and set min-max rate for each vn */\n\t\tif (bp->port.pmf)\n\t\t\tfor (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)\n\t\t\t\tbnx2x_calc_vn_max(bp, vn, &input);\n\n\t\t/* always enable rate shaping and fairness */\n\t\tinput.flags.cmng_enables |=\n\t\t\t\t\tCMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;\n\n\t\tbnx2x_init_cmng(&input, &bp->cmng);\n\t\treturn;\n\t}\n\n\t/* rate shaping and fairness are disabled */\n\tDP(NETIF_MSG_IFUP,\n\t   \"rate shaping and fairness are disabled\\n\");\n}",
        "static int do_server(struct sock_args *args, int ipc_fd)\n{\n\t/* ipc_fd = -1 if no parent process to signal */\n\tstruct timeval timeout = { .tv_sec = prog_timeout }, *ptval = NULL;\n\tunsigned char addr[sizeof(struct sockaddr_in6)] = {};": "static int do_server(struct sock_args *args, int ipc_fd)\n{\n\t/* ipc_fd = -1 if no parent process to signal */\n\tstruct timeval timeout = { .tv_sec = prog_timeout }, *ptval = NULL;\n\tunsigned char addr[sizeof(struct sockaddr_in6)] = {};\n\tsocklen_t alen = sizeof(addr);\n\tint lsd, csd = -1;\n\n\tfd_set rfds;\n\tint rc;\n\n\tif (args->serverns) {\n\t\tif (switch_ns(args->serverns)) {\n\t\t\tlog_error(\"Could not set server netns to %s\\n\",\n\t\t\t\t  args->serverns);\n\t\t\tgoto err_exit;\n\t\t}\n\t\tlog_msg(\"Switched server netns\\n\");\n\t}\n\n\targs->dev = args->server_dev;\n\targs->expected_dev = args->expected_server_dev;\n\tif (resolve_devices(args) || validate_addresses(args))\n\t\tgoto err_exit;\n\n\tif (prog_timeout)\n\t\tptval = &timeout;\n\n\tif (args->has_grp)\n\t\tlsd = msock_server(args);\n\telse\n\t\tlsd = lsock_init(args);\n\n\tif (lsd < 0)\n\t\tgoto err_exit;\n\n\tif (args->bind_test_only) {\n\t\tclose(lsd);\n\t\tipc_write(ipc_fd, 1);\n\t\treturn 0;\n\t}\n\n\tif (args->type != SOCK_STREAM) {\n\t\tipc_write(ipc_fd, 1);\n\t\trc = msg_loop(0, lsd, (void *) addr, alen, args);\n\t\tclose(lsd);\n\t\treturn rc;\n\t}\n\n\tif (args->password && tcp_md5_remote(lsd, args)) {\n\t\tclose(lsd);\n\t\tgoto err_exit;\n\t}\n\n\tipc_write(ipc_fd, 1);\n\twhile (1) {\n\t\tlog_msg(\"waiting for client connection.\\n\");\n\t\tFD_ZERO(&rfds);\n\t\tFD_SET(lsd, &rfds);\n\n\t\trc = select(lsd+1, &rfds, NULL, NULL, ptval);\n\t\tif (rc == 0) {\n\t\t\trc = 2;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (rc < 0) {\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\n\t\t\tlog_err_errno(\"select failed\");\n\t\t\tbreak;\n\t\t}\n\n\t\tif (FD_ISSET(lsd, &rfds)) {\n\n\t\t\tcsd = accept(lsd, (void *) addr, &alen);\n\t\t\tif (csd < 0) {\n\t\t\t\tlog_err_errno(\"accept failed\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\trc = show_sockstat(csd, args);\n\t\t\tif (rc)\n\t\t\t\tbreak;\n\n\t\t\trc = check_device(csd, args);\n\t\t\tif (rc)\n\t\t\t\tbreak;\n\t\t}\n\n\t\trc = msg_loop(0, csd, (void *) addr, alen, args);\n\t\tclose(csd);\n\n\t\tif (!interactive)\n\t\t\tbreak;\n\t}\n\n\tclose(lsd);\n\n\treturn rc;\nerr_exit:\n\tipc_write(ipc_fd, 0);\n\treturn 1;\n}",
        "static int l2cap_seq_list_init(struct l2cap_seq_list *seq_list, u16 size)\n{\n\tsize_t alloc_size, i;\n\n\t/* Allocated size is a power of 2 to map sequence numbers": "static int l2cap_seq_list_init(struct l2cap_seq_list *seq_list, u16 size)\n{\n\tsize_t alloc_size, i;\n\n\t/* Allocated size is a power of 2 to map sequence numbers\n\t * (which may be up to 14 bits) in to a smaller array that is\n\t * sized for the negotiated ERTM transmit windows.\n\t */\n\talloc_size = roundup_pow_of_two(size);\n\n\tseq_list->list = kmalloc_array(alloc_size, sizeof(u16), GFP_KERNEL);\n\tif (!seq_list->list)\n\t\treturn -ENOMEM;\n\n\tseq_list->mask = alloc_size - 1;\n\tseq_list->head = L2CAP_SEQ_LIST_CLEAR;\n\tseq_list->tail = L2CAP_SEQ_LIST_CLEAR;\n\tfor (i = 0; i < alloc_size; i++)\n\t\tseq_list->list[i] = L2CAP_SEQ_LIST_CLEAR;\n\n\treturn 0;\n}",
        "static int aq_get_rxpages(struct aq_ring_s *self, struct aq_ring_buff_s *rxbuf)\n{\n\tunsigned int order = self->page_order;\n\tu16 page_offset = self->page_offset;\n\tu16 frame_max = self->frame_max;": "static int aq_get_rxpages(struct aq_ring_s *self, struct aq_ring_buff_s *rxbuf)\n{\n\tunsigned int order = self->page_order;\n\tu16 page_offset = self->page_offset;\n\tu16 frame_max = self->frame_max;\n\tu16 tail_size = self->tail_size;\n\tint ret;\n\n\tif (rxbuf->rxdata.page) {\n\t\t/* One means ring is the only user and can reuse */\n\t\tif (page_ref_count(rxbuf->rxdata.page) > 1) {\n\t\t\t/* Try reuse buffer */\n\t\t\trxbuf->rxdata.pg_off += frame_max + page_offset +\n\t\t\t\t\t\ttail_size;\n\t\t\tif (rxbuf->rxdata.pg_off + frame_max + tail_size <=\n\t\t\t    (PAGE_SIZE << order)) {\n\t\t\t\tu64_stats_update_begin(&self->stats.rx.syncp);\n\t\t\t\tself->stats.rx.pg_flips++;\n\t\t\t\tu64_stats_update_end(&self->stats.rx.syncp);\n\n\t\t\t} else {\n\t\t\t\t/* Buffer exhausted. We have other users and\n\t\t\t\t * should release this page and realloc\n\t\t\t\t */\n\t\t\t\taq_free_rxpage(&rxbuf->rxdata,\n\t\t\t\t\t       aq_nic_get_dev(self->aq_nic));\n\t\t\t\tu64_stats_update_begin(&self->stats.rx.syncp);\n\t\t\t\tself->stats.rx.pg_losts++;\n\t\t\t\tu64_stats_update_end(&self->stats.rx.syncp);\n\t\t\t}\n\t\t} else {\n\t\t\trxbuf->rxdata.pg_off = page_offset;\n\t\t\tu64_stats_update_begin(&self->stats.rx.syncp);\n\t\t\tself->stats.rx.pg_reuses++;\n\t\t\tu64_stats_update_end(&self->stats.rx.syncp);\n\t\t}\n\t}\n\n\tif (!rxbuf->rxdata.page) {\n\t\tret = aq_alloc_rxpages(&rxbuf->rxdata, self);\n\t\tif (ret) {\n\t\t\tu64_stats_update_begin(&self->stats.rx.syncp);\n\t\t\tself->stats.rx.alloc_fails++;\n\t\t\tu64_stats_update_end(&self->stats.rx.syncp);\n\t\t}\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}",
        "static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)\n{\n\tenum { MADR_WNR_BIT = 31 };\n\n\twritel(0, &g.dim2->MCTL);   /* clear transfer complete */": "static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)\n{\n\tenum { MADR_WNR_BIT = 31 };\n\n\twritel(0, &g.dim2->MCTL);   /* clear transfer complete */\n\n\tif (mask[0] != 0)\n\t\twritel(value[0], &g.dim2->MDAT0);\n\tif (mask[1] != 0)\n\t\twritel(value[1], &g.dim2->MDAT1);\n\tif (mask[2] != 0)\n\t\twritel(value[2], &g.dim2->MDAT2);\n\tif (mask[3] != 0)\n\t\twritel(value[3], &g.dim2->MDAT3);\n\n\twritel(mask[0], &g.dim2->MDWE0);\n\twritel(mask[1], &g.dim2->MDWE1);\n\twritel(mask[2], &g.dim2->MDWE2);\n\twritel(mask[3], &g.dim2->MDWE3);\n\n\tdim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);\n}",
        "static int mt2063_lockStatus(struct mt2063_state *state)\n{\n\tconst u32 nMaxWait = 100;\t/*  wait a maximum of 100 msec   */\n\tconst u32 nPollRate = 2;\t/*  poll status bits every 2 ms */\n\tconst u32 nMaxLoops = nMaxWait / nPollRate;": "static int mt2063_lockStatus(struct mt2063_state *state)\n{\n\tconst u32 nMaxWait = 100;\t/*  wait a maximum of 100 msec   */\n\tconst u32 nPollRate = 2;\t/*  poll status bits every 2 ms */\n\tconst u32 nMaxLoops = nMaxWait / nPollRate;\n\tconst u8 LO1LK = 0x80;\n\tu8 LO2LK = 0x08;\n\tint status;\n\tu32 nDelays = 0;\n\n\tdprintk(2, \"\\n\");\n\n\t/*  LO2 Lock bit was in a different place for B0 version  */\n\tif (state->tuner_id == MT2063_B0)\n\t\tLO2LK = 0x40;\n\n\tdo {\n\t\tstatus = mt2063_read(state, MT2063_REG_LO_STATUS,\n\t\t\t\t     &state->reg[MT2063_REG_LO_STATUS], 1);\n\n\t\tif (status < 0)\n\t\t\treturn status;\n\n\t\tif ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==\n\t\t    (LO1LK | LO2LK)) {\n\t\t\treturn TUNER_STATUS_LOCKED | TUNER_STATUS_STEREO;\n\t\t}\n\t\tmsleep(nPollRate);\t/*  Wait between retries  */\n\t} while (++nDelays < nMaxLoops);\n\n\t/*\n\t * Got no lock or partial lock\n\t */\n\treturn 0;\n}",
        "static void asc_set_mctrl(struct uart_port *port, unsigned int mctrl)\n{\n\tstruct asc_port *ascport = to_asc_port(port);\n\n\t/*": "static void asc_set_mctrl(struct uart_port *port, unsigned int mctrl)\n{\n\tstruct asc_port *ascport = to_asc_port(port);\n\n\t/*\n\t * This routine is used for seting signals of: DTR, DCD, CTS and RTS.\n\t * We use ASC's hardware for CTS/RTS when hardware flow-control is\n\t * enabled, however if the RTS line is required for another purpose,\n\t * commonly controlled using HUP from userspace, then we need to toggle\n\t * it manually, using GPIO.\n\t *\n\t * Some boards also have DTR and DCD implemented using PIO pins, code to\n\t * do this should be hooked in here.\n\t */\n\n\tif (!ascport->rts)\n\t\treturn;\n\n\t/* If HW flow-control is enabled, we can't fiddle with the RTS line */\n\tif (asc_in(port, ASC_CTL) & ASC_CTL_CTSENABLE)\n\t\treturn;\n\n\tgpiod_set_value(ascport->rts, mctrl & TIOCM_RTS);\n}",
        "static int m_can_echo_tx_event(struct net_device *dev)\n{\n\tu32 txe_count = 0;\n\tu32 m_can_txefs;\n\tu32 fgi = 0;": "static int m_can_echo_tx_event(struct net_device *dev)\n{\n\tu32 txe_count = 0;\n\tu32 m_can_txefs;\n\tu32 fgi = 0;\n\tint i = 0;\n\tunsigned int msg_mark;\n\n\tstruct m_can_classdev *cdev = netdev_priv(dev);\n\n\t/* read tx event fifo status */\n\tm_can_txefs = m_can_read(cdev, M_CAN_TXEFS);\n\n\t/* Get Tx Event fifo element count */\n\ttxe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);\n\n\t/* Get and process all sent elements */\n\tfor (i = 0; i < txe_count; i++) {\n\t\tu32 txe, timestamp = 0;\n\t\tint err;\n\n\t\t/* retrieve get index */\n\t\tfgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_read(cdev, M_CAN_TXEFS));\n\n\t\t/* get message marker, timestamp */\n\t\terr = m_can_txe_fifo_read(cdev, fgi, 4, &txe);\n\t\tif (err) {\n\t\t\tnetdev_err(dev, \"TXE FIFO read returned %d\\n\", err);\n\t\t\treturn err;\n\t\t}\n\n\t\tmsg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);\n\t\ttimestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe);\n\n\t\t/* ack txe element */\n\t\tm_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,\n\t\t\t\t\t\t\t  fgi));\n\n\t\t/* update stats */\n\t\tm_can_tx_update_stats(cdev, msg_mark, timestamp);\n\t}\n\n\treturn 0;\n}",
        "static int map_update_elem(union bpf_attr *attr, bpfptr_t uattr)\n{\n\tbpfptr_t ukey = make_bpfptr(attr->key, uattr.is_kernel);\n\tbpfptr_t uvalue = make_bpfptr(attr->value, uattr.is_kernel);\n\tint ufd = attr->map_fd;": "static int map_update_elem(union bpf_attr *attr, bpfptr_t uattr)\n{\n\tbpfptr_t ukey = make_bpfptr(attr->key, uattr.is_kernel);\n\tbpfptr_t uvalue = make_bpfptr(attr->value, uattr.is_kernel);\n\tint ufd = attr->map_fd;\n\tstruct bpf_map *map;\n\tvoid *key, *value;\n\tu32 value_size;\n\tstruct fd f;\n\tint err;\n\n\tif (CHECK_ATTR(BPF_MAP_UPDATE_ELEM))\n\t\treturn -EINVAL;\n\n\tf = fdget(ufd);\n\tmap = __bpf_map_get(f);\n\tif (IS_ERR(map))\n\t\treturn PTR_ERR(map);\n\tbpf_map_write_active_inc(map);\n\tif (!(map_get_sys_perms(map, f) & FMODE_CAN_WRITE)) {\n\t\terr = -EPERM;\n\t\tgoto err_put;\n\t}\n\n\tif ((attr->flags & BPF_F_LOCK) &&\n\t    !map_value_has_spin_lock(map)) {\n\t\terr = -EINVAL;\n\t\tgoto err_put;\n\t}\n\n\tkey = ___bpf_copy_key(ukey, map->key_size);\n\tif (IS_ERR(key)) {\n\t\terr = PTR_ERR(key);\n\t\tgoto err_put;\n\t}\n\n\tvalue_size = bpf_map_value_size(map);\n\n\terr = -ENOMEM;\n\tvalue = kvmalloc(value_size, GFP_USER | __GFP_NOWARN);\n\tif (!value)\n\t\tgoto free_key;\n\n\terr = -EFAULT;\n\tif (copy_from_bpfptr(value, uvalue, value_size) != 0)\n\t\tgoto free_value;\n\n\terr = bpf_map_update_value(map, f, key, value, attr->flags);\n\nfree_value:\n\tkvfree(value);\nfree_key:\n\tkvfree(key);\nerr_put:\n\tbpf_map_write_active_dec(map);\n\tfdput(f);\n\treturn err;\n}",
        "static int io_iopoll_check(struct io_ring_ctx *ctx, long min)\n{\n\tunsigned int nr_events = 0;\n\tint ret = 0;\n\tunsigned long check_cq;": "static int io_iopoll_check(struct io_ring_ctx *ctx, long min)\n{\n\tunsigned int nr_events = 0;\n\tint ret = 0;\n\tunsigned long check_cq;\n\n\t/*\n\t * Don't enter poll loop if we already have events pending.\n\t * If we do, we can potentially be spinning for commands that\n\t * already triggered a CQE (eg in error).\n\t */\n\tcheck_cq = READ_ONCE(ctx->check_cq);\n\tif (check_cq & BIT(IO_CHECK_CQ_OVERFLOW_BIT))\n\t\t__io_cqring_overflow_flush(ctx, false);\n\tif (io_cqring_events(ctx))\n\t\treturn 0;\n\n\t/*\n\t * Similarly do not spin if we have not informed the user of any\n\t * dropped CQE.\n\t */\n\tif (unlikely(check_cq & BIT(IO_CHECK_CQ_DROPPED_BIT)))\n\t\treturn -EBADR;\n\n\tdo {\n\t\t/*\n\t\t * If a submit got punted to a workqueue, we can have the\n\t\t * application entering polling for a command before it gets\n\t\t * issued. That app will hold the uring_lock for the duration\n\t\t * of the poll right here, so we need to take a breather every\n\t\t * now and then to ensure that the issue has a chance to add\n\t\t * the poll to the issued list. Otherwise we can spin here\n\t\t * forever, while the workqueue is stuck trying to acquire the\n\t\t * very same mutex.\n\t\t */\n\t\tif (wq_list_empty(&ctx->iopoll_list)) {\n\t\t\tu32 tail = ctx->cached_cq_tail;\n\n\t\t\tmutex_unlock(&ctx->uring_lock);\n\t\t\tio_run_task_work();\n\t\t\tmutex_lock(&ctx->uring_lock);\n\n\t\t\t/* some requests don't go through iopoll_list */\n\t\t\tif (tail != ctx->cached_cq_tail ||\n\t\t\t    wq_list_empty(&ctx->iopoll_list))\n\t\t\t\tbreak;\n\t\t}\n\t\tret = io_do_iopoll(ctx, !min);\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t\tnr_events += ret;\n\t\tret = 0;\n\t} while (nr_events < min && !need_resched());\n\n\treturn ret;\n}",
        "static int mmcr1_comb(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\tu64 dummy;": "static int mmcr1_comb(void)\n{\n\tstruct event event;\n\tu64 *intr_regs;\n\tu64 dummy;\n\n\t/* Check for platform support for the test */\n\tSKIP_IF(check_pvr_for_sampling_tests());\n\n\t/* Init the event for the sampling test */\n\tevent_init_sampling(&event, EventCode);\n\tevent.attr.sample_regs_intr = platform_extended_mask;\n\tFAIL_IF(event_open(&event));\n\tevent.mmap_buffer = event_sample_buf_mmap(event.fd, 1);\n\n\tFAIL_IF(event_enable(&event));\n\n\t/* workload to make the event overflow */\n\tthirty_two_instruction_loop_with_ll_sc(10000000, &dummy);\n\n\tFAIL_IF(event_disable(&event));\n\n\t/* Check for sample count */\n\tFAIL_IF(!collect_samples(event.mmap_buffer));\n\n\tintr_regs = get_intr_regs(&event, event.mmap_buffer);\n\n\t/* Check for intr_regs */\n\tFAIL_IF(!intr_regs);\n\n\t/*\n\t * Verify that comb field match with\n\t * corresponding event code fields\n\t */\n\tFAIL_IF(EV_CODE_EXTRACT(event.attr.config, comb) !=\n\t\tget_mmcr1_comb(get_reg_value(intr_regs, \"MMCR1\"), 4));\n\n\tevent_close(&event);\n\treturn 0;\n}",
        "static int smc_pnet_enter(struct net *net, struct nlattr *tb[])\n{\n\tchar pnet_name[SMC_MAX_PNETID_LEN + 1];\n\tstruct smc_pnettable *pnettable;\n\tbool new_netdev = false;": "static int smc_pnet_enter(struct net *net, struct nlattr *tb[])\n{\n\tchar pnet_name[SMC_MAX_PNETID_LEN + 1];\n\tstruct smc_pnettable *pnettable;\n\tbool new_netdev = false;\n\tbool new_ibdev = false;\n\tstruct smc_net *sn;\n\tu8 ibport = 1;\n\tchar *string;\n\tint rc;\n\n\t/* get pnettable for namespace */\n\tsn = net_generic(net, smc_net_id);\n\tpnettable = &sn->pnettable;\n\n\trc = -EINVAL;\n\tif (!tb[SMC_PNETID_NAME])\n\t\tgoto error;\n\tstring = (char *)nla_data(tb[SMC_PNETID_NAME]);\n\tif (!smc_pnetid_valid(string, pnet_name))\n\t\tgoto error;\n\n\tif (tb[SMC_PNETID_ETHNAME]) {\n\t\tstring = (char *)nla_data(tb[SMC_PNETID_ETHNAME]);\n\t\trc = smc_pnet_add_eth(pnettable, net, string, pnet_name);\n\t\tif (!rc)\n\t\t\tnew_netdev = true;\n\t\telse if (rc != -EEXIST)\n\t\t\tgoto error;\n\t}\n\n\t/* if this is not the initial namespace, stop here */\n\tif (net != &init_net)\n\t\treturn new_netdev ? 0 : -EEXIST;\n\n\trc = -EINVAL;\n\tif (tb[SMC_PNETID_IBNAME]) {\n\t\tstring = (char *)nla_data(tb[SMC_PNETID_IBNAME]);\n\t\tstring = strim(string);\n\t\tif (tb[SMC_PNETID_IBPORT]) {\n\t\t\tibport = nla_get_u8(tb[SMC_PNETID_IBPORT]);\n\t\t\tif (ibport < 1 || ibport > SMC_MAX_PORTS)\n\t\t\t\tgoto error;\n\t\t}\n\t\trc = smc_pnet_add_ib(pnettable, string, ibport, pnet_name);\n\t\tif (!rc)\n\t\t\tnew_ibdev = true;\n\t\telse if (rc != -EEXIST)\n\t\t\tgoto error;\n\t}\n\treturn (new_netdev || new_ibdev) ? 0 : -EEXIST;\n\nerror:\n\treturn rc;\n}",
        "static void genesis_init(struct skge_hw *hw)\n{\n\t/* set blink source counter */\n\tskge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);\n\tskge_write8(hw, B2_BSC_CTRL, BSC_START);": "static void genesis_init(struct skge_hw *hw)\n{\n\t/* set blink source counter */\n\tskge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);\n\tskge_write8(hw, B2_BSC_CTRL, BSC_START);\n\n\t/* configure mac arbiter */\n\tskge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);\n\n\t/* configure mac arbiter timeout values */\n\tskge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);\n\tskge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);\n\tskge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);\n\tskge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);\n\n\tskge_write8(hw, B3_MA_RCINI_RX1, 0);\n\tskge_write8(hw, B3_MA_RCINI_RX2, 0);\n\tskge_write8(hw, B3_MA_RCINI_TX1, 0);\n\tskge_write8(hw, B3_MA_RCINI_TX2, 0);\n\n\t/* configure packet arbiter timeout */\n\tskge_write16(hw, B3_PA_CTRL, PA_RST_CLR);\n\tskge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);\n\tskge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);\n\tskge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);\n\tskge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);\n}",
        "static void max96712_pattern_enable(struct max96712_priv *priv, bool enable)\n{\n\tconst u32 h_active = 1920;\n\tconst u32 h_fp = 88;\n\tconst u32 h_sw = 44;": "static void max96712_pattern_enable(struct max96712_priv *priv, bool enable)\n{\n\tconst u32 h_active = 1920;\n\tconst u32 h_fp = 88;\n\tconst u32 h_sw = 44;\n\tconst u32 h_bp = 148;\n\tconst u32 h_tot = h_active + h_fp + h_sw + h_bp;\n\n\tconst u32 v_active = 1080;\n\tconst u32 v_fp = 4;\n\tconst u32 v_sw = 5;\n\tconst u32 v_bp = 36;\n\tconst u32 v_tot = v_active + v_fp + v_sw + v_bp;\n\n\tif (!enable) {\n\t\tmax96712_write(priv, 0x1051, 0x00);\n\t\treturn;\n\t}\n\n\t/* PCLK 75MHz. */\n\tmax96712_write(priv, 0x0009, 0x01);\n\n\t/* Configure Video Timing Generator for 1920x1080 @ 30 fps. */\n\tmax96712_write_bulk_value(priv, 0x1052, 0, 3);\n\tmax96712_write_bulk_value(priv, 0x1055, v_sw * h_tot, 3);\n\tmax96712_write_bulk_value(priv, 0x1058,\n\t\t\t\t  (v_active + v_fp + + v_bp) * h_tot, 3);\n\tmax96712_write_bulk_value(priv, 0x105b, 0, 3);\n\tmax96712_write_bulk_value(priv, 0x105e, h_sw, 2);\n\tmax96712_write_bulk_value(priv, 0x1060, h_active + h_fp + h_bp, 2);\n\tmax96712_write_bulk_value(priv, 0x1062, v_tot, 2);\n\tmax96712_write_bulk_value(priv, 0x1064,\n\t\t\t\t  h_tot * (v_sw + v_bp) + (h_sw + h_bp), 3);\n\tmax96712_write_bulk_value(priv, 0x1067, h_active, 2);\n\tmax96712_write_bulk_value(priv, 0x1069, h_fp + h_sw + h_bp, 2);\n\tmax96712_write_bulk_value(priv, 0x106b, v_active, 2);\n\n\t/* Generate VS, HS and DE in free-running mode. */\n\tmax96712_write(priv, 0x1050, 0xfb);\n\n\t/* Configure Video Pattern Generator. */\n\tif (priv->pattern == MAX96712_PATTERN_CHECKERBOARD) {\n\t\t/* Set checkerboard pattern size. */\n\t\tmax96712_write(priv, 0x1074, 0x3c);\n\t\tmax96712_write(priv, 0x1075, 0x3c);\n\t\tmax96712_write(priv, 0x1076, 0x3c);\n\n\t\t/* Set checkerboard pattern colors. */\n\t\tmax96712_write_bulk_value(priv, 0x106e, 0xfecc00, 3);\n\t\tmax96712_write_bulk_value(priv, 0x1071, 0x006aa7, 3);\n\n\t\t/* Generate checkerboard pattern. */\n\t\tmax96712_write(priv, 0x1051, 0x10);\n\t} else {\n\t\t/* Set gradient increment. */\n\t\tmax96712_write(priv, 0x106d, 0x10);\n\n\t\t/* Generate gradient pattern. */\n\t\tmax96712_write(priv, 0x1051, 0x20);\n\t}\n}",
        "static bool HalDetectPwrDownMode(struct adapter *Adapter)\n{\n\tu8 tmpvalue;\n\tstruct hal_com_data *pHalData = GET_HAL_DATA(Adapter);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);": "static bool HalDetectPwrDownMode(struct adapter *Adapter)\n{\n\tu8 tmpvalue;\n\tstruct hal_com_data *pHalData = GET_HAL_DATA(Adapter);\n\tstruct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);\n\n\n\tEFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);\n\n\t/*  2010/08/25 MH INF priority > PDN Efuse value. */\n\tif (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)\n\t\tpHalData->pwrdown = true;\n\telse\n\t\tpHalData->pwrdown = false;\n\n\treturn pHalData->pwrdown;\n}\t/*  HalDetectPwrDownMode */\n\nstatic u32 rtl8723bs_hal_init(struct adapter *padapter)\n{\n\ts32 ret;\n\tstruct hal_com_data *pHalData;\n\tstruct pwrctrl_priv *pwrctrlpriv;\n\tu32 NavUpper = WiFiNavUpperUs;\n\tu8 u1bTmp;\n\n\tpHalData = GET_HAL_DATA(padapter);\n\tpwrctrlpriv = adapter_to_pwrctl(padapter);\n\n\tif (\n\t\tadapter_to_pwrctl(padapter)->bips_processing == true &&\n\t\tadapter_to_pwrctl(padapter)->pre_ips_type == 0\n\t) {\n\t\tunsigned long start_time;\n\t\tu8 cpwm_orig, cpwm_now;\n\t\tu8 val8, bMacPwrCtrlOn = true;\n\n\t\t/* for polling cpwm */\n\t\tcpwm_orig = 0;\n\t\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);\n\n\t\t/* ser rpwm */\n\t\tval8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);\n\t\tval8 &= 0x80;\n\t\tval8 += 0x80;\n\t\tval8 |= BIT(6);\n\t\trtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);\n\t\tadapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;\n\n\t\t/* do polling cpwm */\n\t\tstart_time = jiffies;\n\t\tdo {\n\n\t\t\tmdelay(1);\n\n\t\t\trtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);\n\t\t\tif ((cpwm_orig ^ cpwm_now) & 0x80)\n\t\t\t\tbreak;\n\n\t\t\tif (jiffies_to_msecs(jiffies - start_time) > 100)\n\t\t\t\tbreak;\n\n\t\t} while (1);\n\n\t\trtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);\n\n\t\trtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);\n\n\t\thal_btcoex_InitHwConfig(padapter, false);\n\n\t\treturn _SUCCESS;\n\t}\n\n\t/*  Disable Interrupt first. */\n/* \trtw_hal_disable_interrupt(padapter); */\n\n\tret = _InitPowerOn_8723BS(padapter);\n\tif (ret == _FAIL)\n\t\treturn _FAIL;\n\n\trtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);\n\n\tret = rtl8723b_FirmwareDownload(padapter, false);\n\tif (ret != _SUCCESS) {\n\t\tpadapter->bFWReady = false;\n\t\tpHalData->fw_ractrl = false;\n\t\treturn ret;\n\t} else {\n\t\tpadapter->bFWReady = true;\n\t\tpHalData->fw_ractrl = true;\n\t}\n\n\trtl8723b_InitializeFirmwareVars(padapter);\n\n/* \tSIC_Init(padapter); */\n\n\tif (pwrctrlpriv->reg_rfoff)\n\t\tpwrctrlpriv->rf_pwrstate = rf_off;\n\n\t/*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */\n\t/*  HW GPIO pin. Before PHY_RFConfig8192C. */\n\tHalDetectPwrDownMode(padapter);\n\n\t/*  Set RF type for BB/RF configuration */\n\t_InitRFType(padapter);\n\n\t/*  Save target channel */\n\t/*  <Roger_Notes> Current Channel will be updated again later. */\n\tpHalData->CurrentChannel = 6;\n\n\tret = PHY_MACConfig8723B(padapter);\n\tif (ret != _SUCCESS)\n\t\treturn ret;\n\t/*  */\n\t/* d. Initialize BB related configurations. */\n\t/*  */\n\tret = PHY_BBConfig8723B(padapter);\n\tif (ret != _SUCCESS)\n\t\treturn ret;\n\n\t/*  If RF is on, we need to init RF. Otherwise, skip the procedure. */\n\t/*  We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */\n\t/* if (pHalData->eRFPowerState == eRfOn) */\n\t{\n\t\tret = PHY_RFConfig8723B(padapter);\n\t\tif (ret != _SUCCESS)\n\t\t\treturn ret;\n\t}\n\n\t/*  */\n\t/*  Joseph Note: Keep RfRegChnlVal for later use. */\n\t/*  */\n\tpHalData->RfRegChnlVal[0] =\n\t\tPHY_QueryRFReg(padapter, (enum rf_path)0, RF_CHNLBW, bRFRegOffsetMask);\n\tpHalData->RfRegChnlVal[1] =\n\t\tPHY_QueryRFReg(padapter, (enum rf_path)1, RF_CHNLBW, bRFRegOffsetMask);\n\n\n\t/* if (!pHalData->bMACFuncEnable) { */\n\t_InitQueueReservedPage(padapter);\n\t_InitTxBufferBoundary(padapter);\n\n\t/*  init LLT after tx buffer boundary is defined */\n\tret = rtl8723b_InitLLTTable(padapter);\n\tif (ret != _SUCCESS)\n\t\treturn _FAIL;\n\n\t/*  */\n\t_InitQueuePriority(padapter);\n\t_InitPageBoundary(padapter);\n\t_InitTransferPageSize(padapter);\n\n\t/*  Get Rx PHY status in order to report RSSI and others. */\n\t_InitDriverInfoSize(padapter, DRVINFO_SZ);\n\thal_init_macaddr(padapter);\n\t_InitNetworkType(padapter);\n\t_InitWMACSetting(padapter);\n\t_InitAdaptiveCtrl(padapter);\n\t_InitEDCA(padapter);\n\t_InitRetryFunction(padapter);\n\t_initSdioAggregationSetting(padapter);\n\t_InitOperationMode(padapter);\n\trtl8723b_InitBeaconParameters(padapter);\n\t_InitInterrupt(padapter);\n\t_InitBurstPktLen_8723BS(padapter);\n\n\t/* YJ, TODO */\n\trtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3);\t/*  CCA */\n\trtw_write8(padapter, 0x976, 0);\t/*  hpfan_todo: 2nd CCA related */\n\n\trtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);\t/*  unit: 256us. 256ms */\n\trtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);\t/*  unit: 256us. 256ms */\n\n\tinvalidate_cam_all(padapter);\n\n\trtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,\n\t\tCHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);\n\n\t/*  Record original value for template. This is arough data, we can only use the data */\n\t/*  for power adjust. The value can not be adjustde according to different power!!! */\n/* \tpHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */\n/* \tpHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */\n\n\trtl8723b_InitAntenna_Selection(padapter);\n\n\t/*  */\n\t/*  Disable BAR, suggested by Scott */\n\t/*  2010.04.09 add by hpfan */\n\t/*  */\n\trtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);\n\n\t/*  HW SEQ CTRL */\n\t/*  set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */\n\trtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);\n\n\n\t/*  */\n\t/*  Configure SDIO TxRx Control to enable Rx DMA timer masking. */\n\t/*  2010.02.24. */\n\t/*  */\n\trtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);\n\n\t_RfPowerSave(padapter);\n\n\n\trtl8723b_InitHalDm(padapter);\n\n\t/*  */\n\t/*  Update current Tx FIFO page status. */\n\t/*  */\n\tHalQueryTxBufferStatus8723BSdio(padapter);\n\tHalQueryTxOQTBufferStatus8723BSdio(padapter);\n\tpHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;\n\n\t/*  Enable MACTXEN/MACRXEN block */\n\tu1bTmp = rtw_read8(padapter, REG_CR);\n\tu1bTmp |= (MACTXEN | MACRXEN);\n\trtw_write8(padapter, REG_CR, u1bTmp);\n\n\trtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);\n\n\t/* ack for xmit mgmt frames. */\n\trtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));\n\n/* \tpHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */\n\n\t{\n\t\tpwrctrlpriv->rf_pwrstate = rf_on;\n\n\t\tif (pwrctrlpriv->rf_pwrstate == rf_on) {\n\t\t\tstruct pwrctrl_priv *pwrpriv;\n\t\t\tunsigned long start_time;\n\t\t\tu8 restore_iqk_rst;\n\t\t\tu8 b2Ant;\n\t\t\tu8 h2cCmdBuf;\n\n\t\t\tpwrpriv = adapter_to_pwrctl(padapter);\n\n\t\t\tPHY_LCCalibrate_8723B(&pHalData->odmpriv);\n\n\t\t\t/* Inform WiFi FW that it is the beginning of IQK */\n\t\t\th2cCmdBuf = 1;\n\t\t\tFillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);\n\n\t\t\tstart_time = jiffies;\n\t\t\tdo {\n\t\t\t\tif (rtw_read8(padapter, 0x1e7) & 0x01)\n\t\t\t\t\tbreak;\n\n\t\t\t\tmsleep(50);\n\t\t\t} while (jiffies_to_msecs(jiffies - start_time) <= 400);\n\n\t\t\thal_btcoex_IQKNotify(padapter, true);\n\n\t\t\trestore_iqk_rst = pwrpriv->bips_processing;\n\t\t\tb2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2;\n\t\t\tPHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);\n\t\t\tpHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;\n\n\t\t\thal_btcoex_IQKNotify(padapter, false);\n\n\t\t\t/* Inform WiFi FW that it is the finish of IQK */\n\t\t\th2cCmdBuf = 0;\n\t\t\tFillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);\n\n\t\t\tODM_TXPowerTrackingCheck(&pHalData->odmpriv);\n\t\t}\n\t}\n\n\t/*  Init BT hw config. */\n\thal_btcoex_InitHwConfig(padapter, false);\n\n\treturn _SUCCESS;\n}",
        "static void et8ek8_update_controls(struct et8ek8_sensor *sensor)\n{\n\tstruct v4l2_ctrl *ctrl;\n\tstruct et8ek8_mode *mode = &sensor->current_reglist->mode;\n": "static void et8ek8_update_controls(struct et8ek8_sensor *sensor)\n{\n\tstruct v4l2_ctrl *ctrl;\n\tstruct et8ek8_mode *mode = &sensor->current_reglist->mode;\n\n\tu32 min, max, pixel_rate;\n\tstatic const int S = 8;\n\n\tctrl = sensor->exposure;\n\n\tmin = 1;\n\tmax = mode->max_exp;\n\n\t/*\n\t * Calculate average pixel clock per line. Assume buffers can spread\n\t * the data over horizontal blanking time. Rounding upwards.\n\t * Formula taken from stock Nokia N900 kernel.\n\t */\n\tpixel_rate = ((mode->pixel_clock + (1 << S) - 1) >> S) + mode->width;\n\tpixel_rate = mode->window_width * (pixel_rate - 1) / mode->width;\n\n\t__v4l2_ctrl_modify_range(ctrl, min, max, min, max);\n\t__v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate, pixel_rate << S);\n}",
        "static int imgu_powerup(struct imgu_device *imgu)\n{\n\tint r;\n\tunsigned int pipe;\n\tunsigned int freq = 200;": "static int imgu_powerup(struct imgu_device *imgu)\n{\n\tint r;\n\tunsigned int pipe;\n\tunsigned int freq = 200;\n\tstruct v4l2_mbus_framefmt *fmt;\n\n\t/* input larger than 2048*1152, ask imgu to work on high freq */\n\tfor_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM) {\n\t\tfmt = &imgu->imgu_pipe[pipe].nodes[IMGU_NODE_IN].pad_fmt;\n\t\tdev_dbg(&imgu->pci_dev->dev, \"pipe %u input format = %ux%u\",\n\t\t\tpipe, fmt->width, fmt->height);\n\t\tif ((fmt->width * fmt->height) >= (2048 * 1152))\n\t\t\tfreq = 450;\n\t}\n\n\tr = imgu_css_set_powerup(&imgu->pci_dev->dev, imgu->base, freq);\n\tif (r)\n\t\treturn r;\n\n\timgu_mmu_resume(imgu->mmu);\n\treturn 0;\n}",
        "static int init_child(int nsfd, char *veth, unsigned int src, unsigned int dst)\n{\n\tstruct in_addr intsrc = inet_makeaddr(INADDR_B, src);\n\tstruct in_addr tunsrc = inet_makeaddr(INADDR_A, src);\n\tstruct in_addr tundst = inet_makeaddr(INADDR_A, dst);": "static int init_child(int nsfd, char *veth, unsigned int src, unsigned int dst)\n{\n\tstruct in_addr intsrc = inet_makeaddr(INADDR_B, src);\n\tstruct in_addr tunsrc = inet_makeaddr(INADDR_A, src);\n\tstruct in_addr tundst = inet_makeaddr(INADDR_A, dst);\n\tint route_sock = -1, ret = -1;\n\tuint32_t route_seq;\n\n\tif (switch_ns(nsfd))\n\t\treturn -1;\n\n\tif (netlink_sock(&route_sock, &route_seq, NETLINK_ROUTE)) {\n\t\tprintk(\"Failed to open netlink route socket in child\");\n\t\treturn -1;\n\t}\n\n\tif (ip4_addr_set(route_sock, route_seq++, veth, intsrc, PREFIX_LEN)) {\n\t\tprintk(\"Failed to set ipv4 addr\");\n\t\tgoto err;\n\t}\n\n\tif (link_set_up(route_sock, route_seq++, veth)) {\n\t\tprintk(\"Failed to bring up %s\", veth);\n\t\tgoto err;\n\t}\n\n\tif (tunnel_set_route(route_sock, &route_seq, veth, tunsrc, tundst)) {\n\t\tprintk(\"Failed to add tunnel route on %s\", veth);\n\t\tgoto err;\n\t}\n\tret = 0;\n\nerr:\n\tclose(route_sock);\n\treturn ret;\n}",
        "static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state)\n{\n\tassert(state);\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"last_cmd\", state->last_cmd);\n": "static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state)\n{\n\tassert(state);\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"last_cmd\", state->last_cmd);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"next_cmd\", state->next_cmd);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"last_ack\", state->last_ack);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\", \"next_ack\", state->next_ack);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"top_fsm_state\", state->top_fsm_state);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captA_fsm_state\", state->captA_fsm_state);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captB_fsm_state\", state->captB_fsm_state);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captC_fsm_state\", state->captC_fsm_state);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"acq_fsm_state\", state->acq_fsm_state);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captA_start_addr\", state->captA_start_addr);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captB_start_addr\", state->captB_start_addr);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captC_start_addr\", state->captC_start_addr);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captA_mem_region_size\",\n\t\t\t    state->captA_mem_region_size);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captB_mem_region_size\",\n\t\t\t    state->captB_mem_region_size);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captC_mem_region_size\",\n\t\t\t    state->captC_mem_region_size);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captA_num_mem_regions\",\n\t\t\t    state->captA_num_mem_regions);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captB_num_mem_regions\",\n\t\t\t    state->captB_num_mem_regions);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"captC_num_mem_regions\",\n\t\t\t    state->captC_num_mem_regions);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"acq_start_addr\", state->acq_start_addr);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"acq_mem_region_size\", state->acq_mem_region_size);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"acq_num_mem_regions\", state->acq_num_mem_regions);\n\n\tia_css_debug_dtrace(2, \"\\t\\t%-32s: %d\\n\",\n\t\t\t    \"capt_reserve_one_mem_region\",\n\t\t\t    state->capt_reserve_one_mem_region);\n\n\treturn;\n}",
        "static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)\n{\n\tu32 val, rdmac_mode;\n\tint i, err, limit;\n\tstruct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;": "static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)\n{\n\tu32 val, rdmac_mode;\n\tint i, err, limit;\n\tstruct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;\n\n\ttg3_disable_ints(tp);\n\n\ttg3_stop_fw(tp);\n\n\ttg3_write_sig_pre_reset(tp, RESET_KIND_INIT);\n\n\tif (tg3_flag(tp, INIT_COMPLETE))\n\t\ttg3_abort_hw(tp, 1);\n\n\tif ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&\n\t    !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {\n\t\ttg3_phy_pull_config(tp);\n\t\ttg3_eee_pull_config(tp, NULL);\n\t\ttp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;\n\t}\n\n\t/* Enable MAC control of LPI */\n\tif (tp->phy_flags & TG3_PHYFLG_EEE_CAP)\n\t\ttg3_setup_eee(tp);\n\n\tif (reset_phy)\n\t\ttg3_phy_reset(tp);\n\n\terr = tg3_chip_reset(tp);\n\tif (err)\n\t\treturn err;\n\n\ttg3_write_sig_legacy(tp, RESET_KIND_INIT);\n\n\tif (tg3_chip_rev(tp) == CHIPREV_5784_AX) {\n\t\tval = tr32(TG3_CPMU_CTRL);\n\t\tval &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);\n\t\ttw32(TG3_CPMU_CTRL, val);\n\n\t\tval = tr32(TG3_CPMU_LSPD_10MB_CLK);\n\t\tval &= ~CPMU_LSPD_10MB_MACCLK_MASK;\n\t\tval |= CPMU_LSPD_10MB_MACCLK_6_25;\n\t\ttw32(TG3_CPMU_LSPD_10MB_CLK, val);\n\n\t\tval = tr32(TG3_CPMU_LNK_AWARE_PWRMD);\n\t\tval &= ~CPMU_LNK_AWARE_MACCLK_MASK;\n\t\tval |= CPMU_LNK_AWARE_MACCLK_6_25;\n\t\ttw32(TG3_CPMU_LNK_AWARE_PWRMD, val);\n\n\t\tval = tr32(TG3_CPMU_HST_ACC);\n\t\tval &= ~CPMU_HST_ACC_MACCLK_MASK;\n\t\tval |= CPMU_HST_ACC_MACCLK_6_25;\n\t\ttw32(TG3_CPMU_HST_ACC, val);\n\t}\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_57780) {\n\t\tval = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;\n\t\tval |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |\n\t\t       PCIE_PWR_MGMT_L1_THRESH_4MS;\n\t\ttw32(PCIE_PWR_MGMT_THRESH, val);\n\n\t\tval = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;\n\t\ttw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);\n\n\t\ttw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);\n\n\t\tval = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;\n\t\ttw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);\n\t}\n\n\tif (tg3_flag(tp, L1PLLPD_EN)) {\n\t\tu32 grc_mode = tr32(GRC_MODE);\n\n\t\t/* Access the lower 1K of PL PCIE block registers. */\n\t\tval = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;\n\t\ttw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);\n\n\t\tval = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);\n\t\ttw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,\n\t\t     val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);\n\n\t\ttw32(GRC_MODE, grc_mode);\n\t}\n\n\tif (tg3_flag(tp, 57765_CLASS)) {\n\t\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {\n\t\t\tu32 grc_mode = tr32(GRC_MODE);\n\n\t\t\t/* Access the lower 1K of PL PCIE block registers. */\n\t\t\tval = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;\n\t\t\ttw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);\n\n\t\t\tval = tr32(TG3_PCIE_TLDLPL_PORT +\n\t\t\t\t   TG3_PCIE_PL_LO_PHYCTL5);\n\t\t\ttw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,\n\t\t\t     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);\n\n\t\t\ttw32(GRC_MODE, grc_mode);\n\t\t}\n\n\t\tif (tg3_chip_rev(tp) != CHIPREV_57765_AX) {\n\t\t\tu32 grc_mode;\n\n\t\t\t/* Fix transmit hangs */\n\t\t\tval = tr32(TG3_CPMU_PADRNG_CTL);\n\t\t\tval |= TG3_CPMU_PADRNG_CTL_RDIV2;\n\t\t\ttw32(TG3_CPMU_PADRNG_CTL, val);\n\n\t\t\tgrc_mode = tr32(GRC_MODE);\n\n\t\t\t/* Access the lower 1K of DL PCIE block registers. */\n\t\t\tval = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;\n\t\t\ttw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);\n\n\t\t\tval = tr32(TG3_PCIE_TLDLPL_PORT +\n\t\t\t\t   TG3_PCIE_DL_LO_FTSMAX);\n\t\t\tval &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;\n\t\t\ttw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,\n\t\t\t     val | TG3_PCIE_DL_LO_FTSMAX_VAL);\n\n\t\t\ttw32(GRC_MODE, grc_mode);\n\t\t}\n\n\t\tval = tr32(TG3_CPMU_LSPD_10MB_CLK);\n\t\tval &= ~CPMU_LSPD_10MB_MACCLK_MASK;\n\t\tval |= CPMU_LSPD_10MB_MACCLK_6_25;\n\t\ttw32(TG3_CPMU_LSPD_10MB_CLK, val);\n\t}\n\n\t/* This works around an issue with Athlon chipsets on\n\t * B3 tigon3 silicon.  This bit has no effect on any\n\t * other revision.  But do not set this on PCI Express\n\t * chips and don't even touch the clocks if the CPMU is present.\n\t */\n\tif (!tg3_flag(tp, CPMU_PRESENT)) {\n\t\tif (!tg3_flag(tp, PCI_EXPRESS))\n\t\t\ttp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;\n\t\ttw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);\n\t}\n\n\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&\n\t    tg3_flag(tp, PCIX_MODE)) {\n\t\tval = tr32(TG3PCI_PCISTATE);\n\t\tval |= PCISTATE_RETRY_SAME_DMA;\n\t\ttw32(TG3PCI_PCISTATE, val);\n\t}\n\n\tif (tg3_flag(tp, ENABLE_APE)) {\n\t\t/* Allow reads and writes to the\n\t\t * APE register and memory space.\n\t\t */\n\t\tval = tr32(TG3PCI_PCISTATE);\n\t\tval |= PCISTATE_ALLOW_APE_CTLSPC_WR |\n\t\t       PCISTATE_ALLOW_APE_SHMEM_WR |\n\t\t       PCISTATE_ALLOW_APE_PSPACE_WR;\n\t\ttw32(TG3PCI_PCISTATE, val);\n\t}\n\n\tif (tg3_chip_rev(tp) == CHIPREV_5704_BX) {\n\t\t/* Enable some hw fixes.  */\n\t\tval = tr32(TG3PCI_MSI_DATA);\n\t\tval |= (1 << 26) | (1 << 28) | (1 << 29);\n\t\ttw32(TG3PCI_MSI_DATA, val);\n\t}\n\n\t/* Descriptor ring init may make accesses to the\n\t * NIC SRAM area to setup the TX descriptors, so we\n\t * can only do this after the hardware has been\n\t * successfully reset.\n\t */\n\terr = tg3_init_rings(tp);\n\tif (err)\n\t\treturn err;\n\n\tif (tg3_flag(tp, 57765_PLUS)) {\n\t\tval = tr32(TG3PCI_DMA_RW_CTRL) &\n\t\t      ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;\n\t\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)\n\t\t\tval &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;\n\t\tif (!tg3_flag(tp, 57765_CLASS) &&\n\t\t    tg3_asic_rev(tp) != ASIC_REV_5717 &&\n\t\t    tg3_asic_rev(tp) != ASIC_REV_5762)\n\t\t\tval |= DMA_RWCTRL_TAGGED_STAT_WA;\n\t\ttw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);\n\t} else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&\n\t\t   tg3_asic_rev(tp) != ASIC_REV_5761) {\n\t\t/* This value is determined during the probe time DMA\n\t\t * engine test, tg3_test_dma.\n\t\t */\n\t\ttw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);\n\t}\n\n\ttp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |\n\t\t\t  GRC_MODE_4X_NIC_SEND_RINGS |\n\t\t\t  GRC_MODE_NO_TX_PHDR_CSUM |\n\t\t\t  GRC_MODE_NO_RX_PHDR_CSUM);\n\ttp->grc_mode |= GRC_MODE_HOST_SENDBDS;\n\n\t/* Pseudo-header checksum is done by hardware logic and not\n\t * the offload processers, so make the chip do the pseudo-\n\t * header checksums on receive.  For transmit it is more\n\t * convenient to do the pseudo-header checksum in software\n\t * as Linux does that on transmit for us in all cases.\n\t */\n\ttp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;\n\n\tval = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;\n\tif (tp->rxptpctl)\n\t\ttw32(TG3_RX_PTP_CTL,\n\t\t     tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);\n\n\tif (tg3_flag(tp, PTP_CAPABLE))\n\t\tval |= GRC_MODE_TIME_SYNC_ENABLE;\n\n\ttw32(GRC_MODE, tp->grc_mode | val);\n\n\t/* On one of the AMD platform, MRRS is restricted to 4000 because of\n\t * south bridge limitation. As a workaround, Driver is setting MRRS\n\t * to 2048 instead of default 4096.\n\t */\n\tif (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&\n\t    tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {\n\t\tval = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;\n\t\ttw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);\n\t}\n\n\t/* Setup the timer prescalar register.  Clock is always 66Mhz. */\n\tval = tr32(GRC_MISC_CFG);\n\tval &= ~0xff;\n\tval |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);\n\ttw32(GRC_MISC_CFG, val);\n\n\t/* Initialize MBUF/DESC pool. */\n\tif (tg3_flag(tp, 5750_PLUS)) {\n\t\t/* Do nothing.  */\n\t} else if (tg3_asic_rev(tp) != ASIC_REV_5705) {\n\t\ttw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);\n\t\tif (tg3_asic_rev(tp) == ASIC_REV_5704)\n\t\t\ttw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);\n\t\telse\n\t\t\ttw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);\n\t\ttw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);\n\t\ttw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);\n\t} else if (tg3_flag(tp, TSO_CAPABLE)) {\n\t\tint fw_len;\n\n\t\tfw_len = tp->fw_len;\n\t\tfw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);\n\t\ttw32(BUFMGR_MB_POOL_ADDR,\n\t\t     NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);\n\t\ttw32(BUFMGR_MB_POOL_SIZE,\n\t\t     NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);\n\t}\n\n\tif (tp->dev->mtu <= ETH_DATA_LEN) {\n\t\ttw32(BUFMGR_MB_RDMA_LOW_WATER,\n\t\t     tp->bufmgr_config.mbuf_read_dma_low_water);\n\t\ttw32(BUFMGR_MB_MACRX_LOW_WATER,\n\t\t     tp->bufmgr_config.mbuf_mac_rx_low_water);\n\t\ttw32(BUFMGR_MB_HIGH_WATER,\n\t\t     tp->bufmgr_config.mbuf_high_water);\n\t} else {\n\t\ttw32(BUFMGR_MB_RDMA_LOW_WATER,\n\t\t     tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);\n\t\ttw32(BUFMGR_MB_MACRX_LOW_WATER,\n\t\t     tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);\n\t\ttw32(BUFMGR_MB_HIGH_WATER,\n\t\t     tp->bufmgr_config.mbuf_high_water_jumbo);\n\t}\n\ttw32(BUFMGR_DMA_LOW_WATER,\n\t     tp->bufmgr_config.dma_low_water);\n\ttw32(BUFMGR_DMA_HIGH_WATER,\n\t     tp->bufmgr_config.dma_high_water);\n\n\tval = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;\n\tif (tg3_asic_rev(tp) == ASIC_REV_5719)\n\t\tval |= BUFMGR_MODE_NO_TX_UNDERRUN;\n\tif (tg3_asic_rev(tp) == ASIC_REV_5717 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5762 ||\n\t    tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||\n\t    tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)\n\t\tval |= BUFMGR_MODE_MBLOW_ATTN_ENAB;\n\ttw32(BUFMGR_MODE, val);\n\tfor (i = 0; i < 2000; i++) {\n\t\tif (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)\n\t\t\tbreak;\n\t\tudelay(10);\n\t}\n\tif (i >= 2000) {\n\t\tnetdev_err(tp->dev, \"%s cannot enable BUFMGR\\n\", __func__);\n\t\treturn -ENODEV;\n\t}\n\n\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)\n\t\ttw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);\n\n\ttg3_setup_rxbd_thresholds(tp);\n\n\t/* Initialize TG3_BDINFO's at:\n\t *  RCVDBDI_STD_BD:\tstandard eth size rx ring\n\t *  RCVDBDI_JUMBO_BD:\tjumbo frame rx ring\n\t *  RCVDBDI_MINI_BD:\tsmall frame rx ring (??? does not work)\n\t *\n\t * like so:\n\t *  TG3_BDINFO_HOST_ADDR:\thigh/low parts of DMA address of ring\n\t *  TG3_BDINFO_MAXLEN_FLAGS:\t(rx max buffer size << 16) |\n\t *                              ring attribute flags\n\t *  TG3_BDINFO_NIC_ADDR:\tlocation of descriptors in nic SRAM\n\t *\n\t * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.\n\t * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.\n\t *\n\t * The size of each ring is fixed in the firmware, but the location is\n\t * configurable.\n\t */\n\ttw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,\n\t     ((u64) tpr->rx_std_mapping >> 32));\n\ttw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,\n\t     ((u64) tpr->rx_std_mapping & 0xffffffff));\n\tif (!tg3_flag(tp, 5717_PLUS))\n\t\ttw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,\n\t\t     NIC_SRAM_RX_BUFFER_DESC);\n\n\t/* Disable the mini ring */\n\tif (!tg3_flag(tp, 5705_PLUS))\n\t\ttw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,\n\t\t     BDINFO_FLAGS_DISABLED);\n\n\t/* Program the jumbo buffer descriptor ring control\n\t * blocks on those devices that have them.\n\t */\n\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||\n\t    (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {\n\n\t\tif (tg3_flag(tp, JUMBO_RING_ENABLE)) {\n\t\t\ttw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,\n\t\t\t     ((u64) tpr->rx_jmb_mapping >> 32));\n\t\t\ttw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,\n\t\t\t     ((u64) tpr->rx_jmb_mapping & 0xffffffff));\n\t\t\tval = TG3_RX_JMB_RING_SIZE(tp) <<\n\t\t\t      BDINFO_FLAGS_MAXLEN_SHIFT;\n\t\t\ttw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,\n\t\t\t     val | BDINFO_FLAGS_USE_EXT_RECV);\n\t\t\tif (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||\n\t\t\t    tg3_flag(tp, 57765_CLASS) ||\n\t\t\t    tg3_asic_rev(tp) == ASIC_REV_5762)\n\t\t\t\ttw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,\n\t\t\t\t     NIC_SRAM_RX_JUMBO_BUFFER_DESC);\n\t\t} else {\n\t\t\ttw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,\n\t\t\t     BDINFO_FLAGS_DISABLED);\n\t\t}\n\n\t\tif (tg3_flag(tp, 57765_PLUS)) {\n\t\t\tval = TG3_RX_STD_RING_SIZE(tp);\n\t\t\tval <<= BDINFO_FLAGS_MAXLEN_SHIFT;\n\t\t\tval |= (TG3_RX_STD_DMA_SZ << 2);\n\t\t} else\n\t\t\tval = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;\n\t} else\n\t\tval = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;\n\n\ttw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);\n\n\ttpr->rx_std_prod_idx = tp->rx_pending;\n\ttw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);\n\n\ttpr->rx_jmb_prod_idx =\n\t\ttg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;\n\ttw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);\n\n\ttg3_rings_reset(tp);\n\n\t/* Initialize MAC address and backoff seed. */\n\t__tg3_set_mac_addr(tp, false);\n\n\t/* MTU + ethernet header + FCS + optional VLAN tag */\n\ttw32(MAC_RX_MTU_SIZE,\n\t     tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);\n\n\t/* The slot time is changed by tg3_setup_phy if we\n\t * run at gigabit with half duplex.\n\t */\n\tval = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |\n\t      (6 << TX_LENGTHS_IPG_SHIFT) |\n\t      (32 << TX_LENGTHS_SLOT_TIME_SHIFT);\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5720 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5762)\n\t\tval |= tr32(MAC_TX_LENGTHS) &\n\t\t       (TX_LENGTHS_JMB_FRM_LEN_MSK |\n\t\t\tTX_LENGTHS_CNT_DWN_VAL_MSK);\n\n\ttw32(MAC_TX_LENGTHS, val);\n\n\t/* Receive rules. */\n\ttw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);\n\ttw32(RCVLPC_CONFIG, 0x0181);\n\n\t/* Calculate RDMAC_MODE setting early, we need it to determine\n\t * the RCVLPC_STATE_ENABLE mask.\n\t */\n\trdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |\n\t\t      RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |\n\t\t      RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |\n\t\t      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |\n\t\t      RDMAC_MODE_LNGREAD_ENAB);\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5717)\n\t\trdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5784 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5785 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_57780)\n\t\trdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |\n\t\t\t      RDMAC_MODE_MBUF_RBD_CRPT_ENAB |\n\t\t\t      RDMAC_MODE_MBUF_SBD_CRPT_ENAB;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5705 &&\n\t    tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {\n\t\tif (tg3_flag(tp, TSO_CAPABLE)) {\n\t\t\trdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;\n\t\t} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&\n\t\t\t   !tg3_flag(tp, IS_5788)) {\n\t\t\trdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;\n\t\t}\n\t}\n\n\tif (tg3_flag(tp, PCI_EXPRESS))\n\t\trdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_57766) {\n\t\ttp->dma_limit = 0;\n\t\tif (tp->dev->mtu <= ETH_DATA_LEN) {\n\t\t\trdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;\n\t\t\ttp->dma_limit = TG3_TX_BD_DMA_MAX_2K;\n\t\t}\n\t}\n\n\tif (tg3_flag(tp, HW_TSO_1) ||\n\t    tg3_flag(tp, HW_TSO_2) ||\n\t    tg3_flag(tp, HW_TSO_3))\n\t\trdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;\n\n\tif (tg3_flag(tp, 57765_PLUS) ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5785 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_57780)\n\t\trdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5720 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5762)\n\t\trdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5761 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5784 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5785 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_57780 ||\n\t    tg3_flag(tp, 57765_PLUS)) {\n\t\tu32 tgtreg;\n\n\t\tif (tg3_asic_rev(tp) == ASIC_REV_5762)\n\t\t\ttgtreg = TG3_RDMA_RSRVCTRL_REG2;\n\t\telse\n\t\t\ttgtreg = TG3_RDMA_RSRVCTRL_REG;\n\n\t\tval = tr32(tgtreg);\n\t\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||\n\t\t    tg3_asic_rev(tp) == ASIC_REV_5762) {\n\t\t\tval &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |\n\t\t\t\t TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |\n\t\t\t\t TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);\n\t\t\tval |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |\n\t\t\t       TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |\n\t\t\t       TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;\n\t\t}\n\t\ttw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);\n\t}\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5719 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5720 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5762) {\n\t\tu32 tgtreg;\n\n\t\tif (tg3_asic_rev(tp) == ASIC_REV_5762)\n\t\t\ttgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;\n\t\telse\n\t\t\ttgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;\n\n\t\tval = tr32(tgtreg);\n\t\ttw32(tgtreg, val |\n\t\t     TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |\n\t\t     TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);\n\t}\n\n\t/* Receive/send statistics. */\n\tif (tg3_flag(tp, 5750_PLUS)) {\n\t\tval = tr32(RCVLPC_STATS_ENABLE);\n\t\tval &= ~RCVLPC_STATSENAB_DACK_FIX;\n\t\ttw32(RCVLPC_STATS_ENABLE, val);\n\t} else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&\n\t\t   tg3_flag(tp, TSO_CAPABLE)) {\n\t\tval = tr32(RCVLPC_STATS_ENABLE);\n\t\tval &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;\n\t\ttw32(RCVLPC_STATS_ENABLE, val);\n\t} else {\n\t\ttw32(RCVLPC_STATS_ENABLE, 0xffffff);\n\t}\n\ttw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);\n\ttw32(SNDDATAI_STATSENAB, 0xffffff);\n\ttw32(SNDDATAI_STATSCTRL,\n\t     (SNDDATAI_SCTRL_ENABLE |\n\t      SNDDATAI_SCTRL_FASTUPD));\n\n\t/* Setup host coalescing engine. */\n\ttw32(HOSTCC_MODE, 0);\n\tfor (i = 0; i < 2000; i++) {\n\t\tif (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))\n\t\t\tbreak;\n\t\tudelay(10);\n\t}\n\n\t__tg3_set_coalesce(tp, &tp->coal);\n\n\tif (!tg3_flag(tp, 5705_PLUS)) {\n\t\t/* Status/statistics block address.  See tg3_timer,\n\t\t * the tg3_periodic_fetch_stats call there, and\n\t\t * tg3_get_stats to see how this works for 5705/5750 chips.\n\t\t */\n\t\ttw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,\n\t\t     ((u64) tp->stats_mapping >> 32));\n\t\ttw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,\n\t\t     ((u64) tp->stats_mapping & 0xffffffff));\n\t\ttw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);\n\n\t\ttw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);\n\n\t\t/* Clear statistics and status block memory areas */\n\t\tfor (i = NIC_SRAM_STATS_BLK;\n\t\t     i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;\n\t\t     i += sizeof(u32)) {\n\t\t\ttg3_write_mem(tp, i, 0);\n\t\t\tudelay(40);\n\t\t}\n\t}\n\n\ttw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);\n\n\ttw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);\n\ttw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);\n\tif (!tg3_flag(tp, 5705_PLUS))\n\t\ttw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);\n\n\tif (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {\n\t\ttp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;\n\t\t/* reset to prevent losing 1st rx packet intermittently */\n\t\ttw32_f(MAC_RX_MODE, RX_MODE_RESET);\n\t\tudelay(10);\n\t}\n\n\ttp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |\n\t\t\tMAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |\n\t\t\tMAC_MODE_FHDE_ENABLE;\n\tif (tg3_flag(tp, ENABLE_APE))\n\t\ttp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;\n\tif (!tg3_flag(tp, 5705_PLUS) &&\n\t    !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&\n\t    tg3_asic_rev(tp) != ASIC_REV_5700)\n\t\ttp->mac_mode |= MAC_MODE_LINK_POLARITY;\n\ttw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);\n\tudelay(40);\n\n\t/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().\n\t * If TG3_FLAG_IS_NIC is zero, we should read the\n\t * register to preserve the GPIO settings for LOMs. The GPIOs,\n\t * whether used as inputs or outputs, are set by boot code after\n\t * reset.\n\t */\n\tif (!tg3_flag(tp, IS_NIC)) {\n\t\tu32 gpio_mask;\n\n\t\tgpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |\n\t\t\t    GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |\n\t\t\t    GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;\n\n\t\tif (tg3_asic_rev(tp) == ASIC_REV_5752)\n\t\t\tgpio_mask |= GRC_LCLCTRL_GPIO_OE3 |\n\t\t\t\t     GRC_LCLCTRL_GPIO_OUTPUT3;\n\n\t\tif (tg3_asic_rev(tp) == ASIC_REV_5755)\n\t\t\tgpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;\n\n\t\ttp->grc_local_ctrl &= ~gpio_mask;\n\t\ttp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;\n\n\t\t/* GPIO1 must be driven high for eeprom write protect */\n\t\tif (tg3_flag(tp, EEPROM_WRITE_PROT))\n\t\t\ttp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |\n\t\t\t\t\t       GRC_LCLCTRL_GPIO_OUTPUT1);\n\t}\n\ttw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);\n\tudelay(100);\n\n\tif (tg3_flag(tp, USING_MSIX)) {\n\t\tval = tr32(MSGINT_MODE);\n\t\tval |= MSGINT_MODE_ENABLE;\n\t\tif (tp->irq_cnt > 1)\n\t\t\tval |= MSGINT_MODE_MULTIVEC_EN;\n\t\tif (!tg3_flag(tp, 1SHOT_MSI))\n\t\t\tval |= MSGINT_MODE_ONE_SHOT_DISABLE;\n\t\ttw32(MSGINT_MODE, val);\n\t}\n\n\tif (!tg3_flag(tp, 5705_PLUS)) {\n\t\ttw32_f(DMAC_MODE, DMAC_MODE_ENABLE);\n\t\tudelay(40);\n\t}\n\n\tval = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |\n\t       WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |\n\t       WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |\n\t       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |\n\t       WDMAC_MODE_LNGREAD_ENAB);\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5705 &&\n\t    tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {\n\t\tif (tg3_flag(tp, TSO_CAPABLE) &&\n\t\t    (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||\n\t\t     tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {\n\t\t\t/* nothing */\n\t\t} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&\n\t\t\t   !tg3_flag(tp, IS_5788)) {\n\t\t\tval |= WDMAC_MODE_RX_ACCEL;\n\t\t}\n\t}\n\n\t/* Enable host coalescing bug fix */\n\tif (tg3_flag(tp, 5755_PLUS))\n\t\tval |= WDMAC_MODE_STATUS_TAG_FIX;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5785)\n\t\tval |= WDMAC_MODE_BURST_ALL_DATA;\n\n\ttw32_f(WDMAC_MODE, val);\n\tudelay(40);\n\n\tif (tg3_flag(tp, PCIX_MODE)) {\n\t\tu16 pcix_cmd;\n\n\t\tpci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,\n\t\t\t\t     &pcix_cmd);\n\t\tif (tg3_asic_rev(tp) == ASIC_REV_5703) {\n\t\t\tpcix_cmd &= ~PCI_X_CMD_MAX_READ;\n\t\t\tpcix_cmd |= PCI_X_CMD_READ_2K;\n\t\t} else if (tg3_asic_rev(tp) == ASIC_REV_5704) {\n\t\t\tpcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);\n\t\t\tpcix_cmd |= PCI_X_CMD_READ_2K;\n\t\t}\n\t\tpci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,\n\t\t\t\t      pcix_cmd);\n\t}\n\n\ttw32_f(RDMAC_MODE, rdmac_mode);\n\tudelay(40);\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5719 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5720) {\n\t\tfor (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {\n\t\t\tif (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))\n\t\t\t\tbreak;\n\t\t}\n\t\tif (i < TG3_NUM_RDMA_CHANNELS) {\n\t\t\tval = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);\n\t\t\tval |= tg3_lso_rd_dma_workaround_bit(tp);\n\t\t\ttw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);\n\t\t\ttg3_flag_set(tp, 5719_5720_RDMA_BUG);\n\t\t}\n\t}\n\n\ttw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);\n\tif (!tg3_flag(tp, 5705_PLUS))\n\t\ttw32(MBFREE_MODE, MBFREE_MODE_ENABLE);\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5761)\n\t\ttw32(SNDDATAC_MODE,\n\t\t     SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);\n\telse\n\t\ttw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);\n\n\ttw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);\n\ttw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);\n\tval = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;\n\tif (tg3_flag(tp, LRG_PROD_RING_CAP))\n\t\tval |= RCVDBDI_MODE_LRG_RING_SZ;\n\ttw32(RCVDBDI_MODE, val);\n\ttw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);\n\tif (tg3_flag(tp, HW_TSO_1) ||\n\t    tg3_flag(tp, HW_TSO_2) ||\n\t    tg3_flag(tp, HW_TSO_3))\n\t\ttw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);\n\tval = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;\n\tif (tg3_flag(tp, ENABLE_TSS))\n\t\tval |= SNDBDI_MODE_MULTI_TXQ_EN;\n\ttw32(SNDBDI_MODE, val);\n\ttw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);\n\n\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {\n\t\terr = tg3_load_5701_a0_firmware_fix(tp);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_57766) {\n\t\t/* Ignore any errors for the firmware download. If download\n\t\t * fails, the device will operate with EEE disabled\n\t\t */\n\t\ttg3_load_57766_firmware(tp);\n\t}\n\n\tif (tg3_flag(tp, TSO_CAPABLE)) {\n\t\terr = tg3_load_tso_firmware(tp);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\ttp->tx_mode = TX_MODE_ENABLE;\n\n\tif (tg3_flag(tp, 5755_PLUS) ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5906)\n\t\ttp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5720 ||\n\t    tg3_asic_rev(tp) == ASIC_REV_5762) {\n\t\tval = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;\n\t\ttp->tx_mode &= ~val;\n\t\ttp->tx_mode |= tr32(MAC_TX_MODE) & val;\n\t}\n\n\ttw32_f(MAC_TX_MODE, tp->tx_mode);\n\tudelay(100);\n\n\tif (tg3_flag(tp, ENABLE_RSS)) {\n\t\tu32 rss_key[10];\n\n\t\ttg3_rss_write_indir_tbl(tp);\n\n\t\tnetdev_rss_key_fill(rss_key, 10 * sizeof(u32));\n\n\t\tfor (i = 0; i < 10 ; i++)\n\t\t\ttw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);\n\t}\n\n\ttp->rx_mode = RX_MODE_ENABLE;\n\tif (tg3_flag(tp, 5755_PLUS))\n\t\ttp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5762)\n\t\ttp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;\n\n\tif (tg3_flag(tp, ENABLE_RSS))\n\t\ttp->rx_mode |= RX_MODE_RSS_ENABLE |\n\t\t\t       RX_MODE_RSS_ITBL_HASH_BITS_7 |\n\t\t\t       RX_MODE_RSS_IPV6_HASH_EN |\n\t\t\t       RX_MODE_RSS_TCP_IPV6_HASH_EN |\n\t\t\t       RX_MODE_RSS_IPV4_HASH_EN |\n\t\t\t       RX_MODE_RSS_TCP_IPV4_HASH_EN;\n\n\ttw32_f(MAC_RX_MODE, tp->rx_mode);\n\tudelay(10);\n\n\ttw32(MAC_LED_CTRL, tp->led_ctrl);\n\n\ttw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);\n\tif (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {\n\t\ttw32_f(MAC_RX_MODE, RX_MODE_RESET);\n\t\tudelay(10);\n\t}\n\ttw32_f(MAC_RX_MODE, tp->rx_mode);\n\tudelay(10);\n\n\tif (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {\n\t\tif ((tg3_asic_rev(tp) == ASIC_REV_5704) &&\n\t\t    !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {\n\t\t\t/* Set drive transmission level to 1.2V  */\n\t\t\t/* only if the signal pre-emphasis bit is not set  */\n\t\t\tval = tr32(MAC_SERDES_CFG);\n\t\t\tval &= 0xfffff000;\n\t\t\tval |= 0x880;\n\t\t\ttw32(MAC_SERDES_CFG, val);\n\t\t}\n\t\tif (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)\n\t\t\ttw32(MAC_SERDES_CFG, 0x616000);\n\t}\n\n\t/* Prevent chip from dropping frames when flow control\n\t * is enabled.\n\t */\n\tif (tg3_flag(tp, 57765_CLASS))\n\t\tval = 1;\n\telse\n\t\tval = 2;\n\ttw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);\n\n\tif (tg3_asic_rev(tp) == ASIC_REV_5704 &&\n\t    (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {\n\t\t/* Use hardware link auto-negotiation */\n\t\ttg3_flag_set(tp, HW_AUTONEG);\n\t}\n\n\tif ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&\n\t    tg3_asic_rev(tp) == ASIC_REV_5714) {\n\t\tu32 tmp;\n\n\t\ttmp = tr32(SERDES_RX_CTRL);\n\t\ttw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);\n\t\ttp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;\n\t\ttp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;\n\t\ttw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);\n\t}\n\n\tif (!tg3_flag(tp, USE_PHYLIB)) {\n\t\tif (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)\n\t\t\ttp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;\n\n\t\terr = tg3_setup_phy(tp, false);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&\n\t\t    !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {\n\t\t\tu32 tmp;\n\n\t\t\t/* Clear CRC stats. */\n\t\t\tif (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {\n\t\t\t\ttg3_writephy(tp, MII_TG3_TEST1,\n\t\t\t\t\t     tmp | MII_TG3_TEST1_CRC_EN);\n\t\t\t\ttg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);\n\t\t\t}\n\t\t}\n\t}\n\n\t__tg3_set_rx_mode(tp->dev);\n\n\t/* Initialize receive rules. */\n\ttw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);\n\ttw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);\n\ttw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);\n\ttw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);\n\n\tif (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))\n\t\tlimit = 8;\n\telse\n\t\tlimit = 16;\n\tif (tg3_flag(tp, ENABLE_ASF))\n\t\tlimit -= 4;\n\tswitch (limit) {\n\tcase 16:\n\t\ttw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);\n\t\tfallthrough;\n\tcase 15:\n\t\ttw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);\n\t\tfallthrough;\n\tcase 14:\n\t\ttw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);\n\t\tfallthrough;\n\tcase 13:\n\t\ttw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);\n\t\tfallthrough;\n\tcase 12:\n\t\ttw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);\n\t\tfallthrough;\n\tcase 11:\n\t\ttw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);\n\t\tfallthrough;\n\tcase 10:\n\t\ttw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);\n\t\tfallthrough;\n\tcase 9:\n\t\ttw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);\n\t\tfallthrough;\n\tcase 8:\n\t\ttw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);\n\t\tfallthrough;\n\tcase 7:\n\t\ttw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);\n\t\tfallthrough;\n\tcase 6:\n\t\ttw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);\n\t\tfallthrough;\n\tcase 5:\n\t\ttw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);\n\t\tfallthrough;\n\tcase 4:\n\t\t/* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */\n\tcase 3:\n\t\t/* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */\n\tcase 2:\n\tcase 1:\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (tg3_flag(tp, ENABLE_APE))\n\t\t/* Write our heartbeat update interval to APE. */\n\t\ttg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,\n\t\t\t\tAPE_HOST_HEARTBEAT_INT_5SEC);\n\n\ttg3_write_sig_post_reset(tp, RESET_KIND_INIT);\n\n\treturn 0;\n}",
        "static struct list_head *__ssh_ptl_queue_find_entrypoint(struct ssh_packet *p)\n{\n\tstruct list_head *head;\n\tstruct ssh_packet *q;\n": "static struct list_head *__ssh_ptl_queue_find_entrypoint(struct ssh_packet *p)\n{\n\tstruct list_head *head;\n\tstruct ssh_packet *q;\n\n\tlockdep_assert_held(&p->ptl->queue.lock);\n\n\t/*\n\t * We generally assume that there are less control (ACK/NAK) packets\n\t * and re-submitted data packets as there are normal data packets (at\n\t * least in situations in which many packets are queued; if there\n\t * aren't many packets queued the decision on how to iterate should be\n\t * basically irrelevant; the number of control/data packets is more or\n\t * less limited via the maximum number of pending packets). Thus, when\n\t * inserting a control or re-submitted data packet, (determined by\n\t * their priority), we search from front to back. Normal data packets\n\t * are, usually queued directly at the tail of the queue, so for those\n\t * search from back to front.\n\t */\n\n\tif (p->priority > SSH_PACKET_PRIORITY(DATA, 0)) {\n\t\tlist_for_each(head, &p->ptl->queue.head) {\n\t\t\tq = list_entry(head, struct ssh_packet, queue_node);\n\n\t\t\tif (q->priority < p->priority)\n\t\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tlist_for_each_prev(head, &p->ptl->queue.head) {\n\t\t\tq = list_entry(head, struct ssh_packet, queue_node);\n\n\t\t\tif (q->priority >= p->priority) {\n\t\t\t\thead = head->next;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn head;\n}",
        "static int trie_get_next_key(struct bpf_map *map, void *_key, void *_next_key)\n{\n\tstruct lpm_trie_node *node, *next_node = NULL, *parent, *search_root;\n\tstruct lpm_trie *trie = container_of(map, struct lpm_trie, map);\n\tstruct bpf_lpm_trie_key *key = _key, *next_key = _next_key;": "static int trie_get_next_key(struct bpf_map *map, void *_key, void *_next_key)\n{\n\tstruct lpm_trie_node *node, *next_node = NULL, *parent, *search_root;\n\tstruct lpm_trie *trie = container_of(map, struct lpm_trie, map);\n\tstruct bpf_lpm_trie_key *key = _key, *next_key = _next_key;\n\tstruct lpm_trie_node **node_stack = NULL;\n\tint err = 0, stack_ptr = -1;\n\tunsigned int next_bit;\n\tsize_t matchlen;\n\n\t/* The get_next_key follows postorder. For the 4 node example in\n\t * the top of this file, the trie_get_next_key() returns the following\n\t * one after another:\n\t *   192.168.0.0/24\n\t *   192.168.1.0/24\n\t *   192.168.128.0/24\n\t *   192.168.0.0/16\n\t *\n\t * The idea is to return more specific keys before less specific ones.\n\t */\n\n\t/* Empty trie */\n\tsearch_root = rcu_dereference(trie->root);\n\tif (!search_root)\n\t\treturn -ENOENT;\n\n\t/* For invalid key, find the leftmost node in the trie */\n\tif (!key || key->prefixlen > trie->max_prefixlen)\n\t\tgoto find_leftmost;\n\n\tnode_stack = kmalloc_array(trie->max_prefixlen,\n\t\t\t\t   sizeof(struct lpm_trie_node *),\n\t\t\t\t   GFP_ATOMIC | __GFP_NOWARN);\n\tif (!node_stack)\n\t\treturn -ENOMEM;\n\n\t/* Try to find the exact node for the given key */\n\tfor (node = search_root; node;) {\n\t\tnode_stack[++stack_ptr] = node;\n\t\tmatchlen = longest_prefix_match(trie, node, key);\n\t\tif (node->prefixlen != matchlen ||\n\t\t    node->prefixlen == key->prefixlen)\n\t\t\tbreak;\n\n\t\tnext_bit = extract_bit(key->data, node->prefixlen);\n\t\tnode = rcu_dereference(node->child[next_bit]);\n\t}\n\tif (!node || node->prefixlen != key->prefixlen ||\n\t    (node->flags & LPM_TREE_NODE_FLAG_IM))\n\t\tgoto find_leftmost;\n\n\t/* The node with the exactly-matching key has been found,\n\t * find the first node in postorder after the matched node.\n\t */\n\tnode = node_stack[stack_ptr];\n\twhile (stack_ptr > 0) {\n\t\tparent = node_stack[stack_ptr - 1];\n\t\tif (rcu_dereference(parent->child[0]) == node) {\n\t\t\tsearch_root = rcu_dereference(parent->child[1]);\n\t\t\tif (search_root)\n\t\t\t\tgoto find_leftmost;\n\t\t}\n\t\tif (!(parent->flags & LPM_TREE_NODE_FLAG_IM)) {\n\t\t\tnext_node = parent;\n\t\t\tgoto do_copy;\n\t\t}\n\n\t\tnode = parent;\n\t\tstack_ptr--;\n\t}\n\n\t/* did not find anything */\n\terr = -ENOENT;\n\tgoto free_stack;\n\nfind_leftmost:\n\t/* Find the leftmost non-intermediate node, all intermediate nodes\n\t * have exact two children, so this function will never return NULL.\n\t */\n\tfor (node = search_root; node;) {\n\t\tif (node->flags & LPM_TREE_NODE_FLAG_IM) {\n\t\t\tnode = rcu_dereference(node->child[0]);\n\t\t} else {\n\t\t\tnext_node = node;\n\t\t\tnode = rcu_dereference(node->child[0]);\n\t\t\tif (!node)\n\t\t\t\tnode = rcu_dereference(next_node->child[1]);\n\t\t}\n\t}\ndo_copy:\n\tnext_key->prefixlen = next_node->prefixlen;\n\tmemcpy((void *)next_key + offsetof(struct bpf_lpm_trie_key, data),\n\t       next_node->data, trie->data_size);\nfree_stack:\n\tkfree(node_stack);\n\treturn err;\n}",
        "static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id)\n{\n\tstruct mt8195_afe_private *afe_priv = afe->platform_priv;\n\tstruct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];\n\tint clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);": "static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id)\n{\n\tstruct mt8195_afe_private *afe_priv = afe->platform_priv;\n\tstruct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];\n\tint clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);\n\tint clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);\n\tint apll;\n\tint apll_clk_id;\n\tstruct etdm_con_reg etdm_reg;\n\tunsigned int val = 0;\n\tunsigned int mask = 0;\n\tint ret = 0;\n\n\tif (clk_id < 0 || clkdiv_id < 0)\n\t\treturn 0;\n\n\tret = get_etdm_reg(dai_id, &etdm_reg);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tmask |= ETDM_CON1_MCLK_OUTPUT;\n\tif (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)\n\t\tval |= ETDM_CON1_MCLK_OUTPUT;\n\tregmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);\n\n\tif (etdm_data->mclk_freq) {\n\t\tapll = etdm_data->mclk_apll;\n\t\tapll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll);\n\t\tif (apll_clk_id < 0)\n\t\t\treturn apll_clk_id;\n\n\t\t/* select apll */\n\t\tret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id],\n\t\t\t\t\t\tafe_priv->clk[apll_clk_id]);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/* set rate */\n\t\tret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id],\n\t\t\t\t\t      etdm_data->mclk_freq);\n\t} else {\n\t\tif (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)\n\t\t\tdev_dbg(afe->dev, \"%s mclk freq = 0\\n\", __func__);\n\t}\n\treturn ret;\n}",
        "static void dump_nhm_cst_cfg(void)\n{\n\tunsigned long long msr;\n\n\tget_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);": "static void dump_nhm_cst_cfg(void)\n{\n\tunsigned long long msr;\n\n\tget_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);\n\n\tfprintf(outf, \"cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx\", base_cpu, msr);\n\n\tfprintf(outf, \" (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)\",\n\t\t(msr & SNB_C3_AUTO_UNDEMOTE) ? \"UNdemote-C3, \" : \"\",\n\t\t(msr & SNB_C1_AUTO_UNDEMOTE) ? \"UNdemote-C1, \" : \"\",\n\t\t(msr & NHM_C3_AUTO_DEMOTE) ? \"demote-C3, \" : \"\",\n\t\t(msr & NHM_C1_AUTO_DEMOTE) ? \"demote-C1, \" : \"\",\n\t\t(msr & (1 << 15)) ? \"\" : \"UN\", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);\n\n#define AUTOMATIC_CSTATE_CONVERSION\t\t(1UL << 16)\n\tif (has_automatic_cstate_conversion) {\n\t\tfprintf(outf, \", automatic c-state conversion=%s\", (msr & AUTOMATIC_CSTATE_CONVERSION) ? \"on\" : \"off\");\n\t}\n\n\tfprintf(outf, \")\\n\");\n\n\treturn;\n}",
        "static int brcmnand_revision_init(struct brcmnand_controller *ctrl)\n{\n\tstatic const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };\n\tstatic const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };\n\tstatic const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };": "static int brcmnand_revision_init(struct brcmnand_controller *ctrl)\n{\n\tstatic const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };\n\tstatic const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };\n\tstatic const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };\n\tstatic const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };\n\tstatic const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };\n\tstatic const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };\n\tstatic const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };\n\n\tctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;\n\n\t/* Only support v2.1+ */\n\tif (ctrl->nand_version < 0x0201) {\n\t\tdev_err(ctrl->dev, \"version %#x not supported\\n\",\n\t\t\tctrl->nand_version);\n\t\treturn -ENODEV;\n\t}\n\n\t/* Register offsets */\n\tif (ctrl->nand_version >= 0x0702)\n\t\tctrl->reg_offsets = brcmnand_regs_v72;\n\telse if (ctrl->nand_version == 0x0701)\n\t\tctrl->reg_offsets = brcmnand_regs_v71;\n\telse if (ctrl->nand_version >= 0x0600)\n\t\tctrl->reg_offsets = brcmnand_regs_v60;\n\telse if (ctrl->nand_version >= 0x0500)\n\t\tctrl->reg_offsets = brcmnand_regs_v50;\n\telse if (ctrl->nand_version >= 0x0303)\n\t\tctrl->reg_offsets = brcmnand_regs_v33;\n\telse if (ctrl->nand_version >= 0x0201)\n\t\tctrl->reg_offsets = brcmnand_regs_v21;\n\n\t/* Chip-select stride */\n\tif (ctrl->nand_version >= 0x0701)\n\t\tctrl->reg_spacing = 0x14;\n\telse\n\t\tctrl->reg_spacing = 0x10;\n\n\t/* Per chip-select registers */\n\tif (ctrl->nand_version >= 0x0701) {\n\t\tctrl->cs_offsets = brcmnand_cs_offsets_v71;\n\t} else {\n\t\tctrl->cs_offsets = brcmnand_cs_offsets;\n\n\t\t/* v3.3-5.0 have a different CS0 offset layout */\n\t\tif (ctrl->nand_version >= 0x0303 &&\n\t\t    ctrl->nand_version <= 0x0500)\n\t\t\tctrl->cs0_offsets = brcmnand_cs_offsets_cs0;\n\t}\n\n\t/* Page / block sizes */\n\tif (ctrl->nand_version >= 0x0701) {\n\t\t/* >= v7.1 use nice power-of-2 values! */\n\t\tctrl->max_page_size = 16 * 1024;\n\t\tctrl->max_block_size = 2 * 1024 * 1024;\n\t} else {\n\t\tif (ctrl->nand_version >= 0x0304)\n\t\t\tctrl->page_sizes = page_sizes_v3_4;\n\t\telse if (ctrl->nand_version >= 0x0202)\n\t\t\tctrl->page_sizes = page_sizes_v2_2;\n\t\telse\n\t\t\tctrl->page_sizes = page_sizes_v2_1;\n\n\t\tif (ctrl->nand_version >= 0x0202)\n\t\t\tctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;\n\t\telse\n\t\t\tctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;\n\n\t\tif (ctrl->nand_version >= 0x0600)\n\t\t\tctrl->block_sizes = block_sizes_v6;\n\t\telse if (ctrl->nand_version >= 0x0400)\n\t\t\tctrl->block_sizes = block_sizes_v4;\n\t\telse if (ctrl->nand_version >= 0x0202)\n\t\t\tctrl->block_sizes = block_sizes_v2_2;\n\t\telse\n\t\t\tctrl->block_sizes = block_sizes_v2_1;\n\n\t\tif (ctrl->nand_version < 0x0400) {\n\t\t\tif (ctrl->nand_version < 0x0202)\n\t\t\t\tctrl->max_page_size = 2048;\n\t\t\telse\n\t\t\t\tctrl->max_page_size = 4096;\n\t\t\tctrl->max_block_size = 512 * 1024;\n\t\t}\n\t}\n\n\t/* Maximum spare area sector size (per 512B) */\n\tif (ctrl->nand_version == 0x0702)\n\t\tctrl->max_oob = 128;\n\telse if (ctrl->nand_version >= 0x0600)\n\t\tctrl->max_oob = 64;\n\telse if (ctrl->nand_version >= 0x0500)\n\t\tctrl->max_oob = 32;\n\telse\n\t\tctrl->max_oob = 16;\n\n\t/* v6.0 and newer (except v6.1) have prefetch support */\n\tif (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)\n\t\tctrl->features |= BRCMNAND_HAS_PREFETCH;\n\n\t/*\n\t * v6.x has cache mode, but it's implemented differently. Ignore it for\n\t * now.\n\t */\n\tif (ctrl->nand_version >= 0x0700)\n\t\tctrl->features |= BRCMNAND_HAS_CACHE_MODE;\n\n\tif (ctrl->nand_version >= 0x0500)\n\t\tctrl->features |= BRCMNAND_HAS_1K_SECTORS;\n\n\tif (ctrl->nand_version >= 0x0700)\n\t\tctrl->features |= BRCMNAND_HAS_WP;\n\telse if (of_property_read_bool(ctrl->dev->of_node, \"brcm,nand-has-wp\"))\n\t\tctrl->features |= BRCMNAND_HAS_WP;\n\n\treturn 0;\n}",
        "static void test_atomic_builtins(struct kunit *test)\n{\n\tbool match_never = false;\n\n\tbegin_test_checks(test_kernel_atomic_builtins, test_kernel_atomic_builtins);": "static void test_atomic_builtins(struct kunit *test)\n{\n\tbool match_never = false;\n\n\tbegin_test_checks(test_kernel_atomic_builtins, test_kernel_atomic_builtins);\n\tdo {\n\t\tlong tmp;\n\n\t\tkcsan_enable_current();\n\n\t\t__atomic_store_n(&test_var, 42L, __ATOMIC_RELAXED);\n\t\tKUNIT_EXPECT_EQ(test, 42L, __atomic_load_n(&test_var, __ATOMIC_RELAXED));\n\n\t\tKUNIT_EXPECT_EQ(test, 42L, __atomic_exchange_n(&test_var, 20, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, 20L, test_var);\n\n\t\ttmp = 20L;\n\t\tKUNIT_EXPECT_TRUE(test, __atomic_compare_exchange_n(&test_var, &tmp, 30L,\n\t\t\t\t\t\t\t\t    0, __ATOMIC_RELAXED,\n\t\t\t\t\t\t\t\t    __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, tmp, 20L);\n\t\tKUNIT_EXPECT_EQ(test, test_var, 30L);\n\t\tKUNIT_EXPECT_FALSE(test, __atomic_compare_exchange_n(&test_var, &tmp, 40L,\n\t\t\t\t\t\t\t\t     1, __ATOMIC_RELAXED,\n\t\t\t\t\t\t\t\t     __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, tmp, 30L);\n\t\tKUNIT_EXPECT_EQ(test, test_var, 30L);\n\n\t\tKUNIT_EXPECT_EQ(test, 30L, __atomic_fetch_add(&test_var, 1, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, 31L, __atomic_fetch_sub(&test_var, 1, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, 30L, __atomic_fetch_and(&test_var, 0xf, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, 14L, __atomic_fetch_xor(&test_var, 0xf, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, 1L, __atomic_fetch_or(&test_var, 0xf0, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, 241L, __atomic_fetch_nand(&test_var, 0xf, __ATOMIC_RELAXED));\n\t\tKUNIT_EXPECT_EQ(test, -2L, test_var);\n\n\t\t__atomic_thread_fence(__ATOMIC_SEQ_CST);\n\t\t__atomic_signal_fence(__ATOMIC_SEQ_CST);\n\n\t\tkcsan_disable_current();\n\n\t\tmatch_never = report_available();\n\t} while (!end_test_checks(match_never));\n\tKUNIT_EXPECT_FALSE(test, match_never);\n}",
        "static void ecl_ishtp_cl_event_cb(struct ishtp_cl_device *cl_device)\n{\n\tstruct ishtp_cl *ecl_ishtp_cl = ishtp_get_drvdata(cl_device);\n\tstruct ishtp_opregion_dev *opr_dev;\n\tstruct ecl_message_header *header;": "static void ecl_ishtp_cl_event_cb(struct ishtp_cl_device *cl_device)\n{\n\tstruct ishtp_cl *ecl_ishtp_cl = ishtp_get_drvdata(cl_device);\n\tstruct ishtp_opregion_dev *opr_dev;\n\tstruct ecl_message_header *header;\n\tstruct ishtp_cl_rb *rb;\n\n\topr_dev = ishtp_get_client_data(ecl_ishtp_cl);\n\twhile ((rb = ishtp_cl_rx_get_rb(opr_dev->ecl_ishtp_cl)) != NULL) {\n\t\topr_dev->rb = rb;\n\t\theader = (struct ecl_message_header *)rb->buffer.data;\n\n\t\tif (header->data_type == ECL_MSG_DATA)\n\t\t\tecl_ish_process_rx_data(opr_dev);\n\t\telse if (header->data_type == ECL_MSG_EVENT)\n\t\t\tecl_ish_process_rx_event(opr_dev);\n\t\telse\n\t\t\t/* Got an event with wrong data_type, ignore it */\n\t\t\tdev_err(cl_data_to_dev(opr_dev),\n\t\t\t\t\"[ish_cb] Received wrong data_type\\n\");\n\n\t\tishtp_cl_io_rb_recycle(rb);\n\t}\n}",
        "static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)\n{\n\tint i;\n\tu32 data = 0;\n\tu32 dataBit;": "static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)\n{\n\tint i;\n\tu32 data = 0;\n\tu32 dataBit;\n\tstruct ql3xxx_port_registers __iomem *port_regs =\n\t\t\tqdev->mem_map_registers;\n\t__iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;\n\n\t/* Read the data bits */\n\t/* The first bit is a dummy.  Clock right over it. */\n\tfor (i = 0; i < dataBits; i++) {\n\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t   ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t\t   AUBURN_EEPROM_CLK_RISE);\n\t\tql_write_nvram_reg(qdev, spir,\n\t\t\t\t   ISP_NVRAM_MASK | qdev->eeprom_cmd_data |\n\t\t\t\t   AUBURN_EEPROM_CLK_FALL);\n\t\tdataBit = (ql_read_common_reg(qdev, spir) &\n\t\t\t   AUBURN_EEPROM_DI_1) ? 1 : 0;\n\t\tdata = (data << 1) | dataBit;\n\t}\n\t*value = (u16)data;\n}",
        "static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)\n{\n\tstruct pci_dev *entry, *pdev = adapter->pdev;\n\tint physfns = 0;\n": "static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)\n{\n\tstruct pci_dev *entry, *pdev = adapter->pdev;\n\tint physfns = 0;\n\n\t/* Some cards can not use the generic count PCIe functions method,\n\t * because they are behind a parent switch, so we hardcode these with\n\t * the correct number of functions.\n\t */\n\tif (ixgbe_pcie_from_parent(&adapter->hw))\n\t\tphysfns = 4;\n\n\tlist_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {\n\t\t/* don't count virtual functions */\n\t\tif (entry->is_virtfn)\n\t\t\tcontinue;\n\n\t\t/* When the devices on the bus don't all match our device ID,\n\t\t * we can't reliably determine the correct number of\n\t\t * functions. This can occur if a function has been direct\n\t\t * attached to a virtual machine using VT-d, for example. In\n\t\t * this case, simply return -1 to indicate this.\n\t\t */\n\t\tif ((entry->vendor != pdev->vendor) ||\n\t\t    (entry->device != pdev->device))\n\t\t\treturn -1;\n\n\t\tphysfns++;\n\t}\n\n\treturn physfns;\n}",
        "static int run_test(int cgroup_fd, int server_fd, bool classid)\n{\n\tstruct network_helper_opts opts = {\n\t\t.must_fail = true,\n\t};": "static int run_test(int cgroup_fd, int server_fd, bool classid)\n{\n\tstruct network_helper_opts opts = {\n\t\t.must_fail = true,\n\t};\n\tstruct connect4_dropper *skel;\n\tint fd, err = 0;\n\n\tskel = connect4_dropper__open_and_load();\n\tif (!ASSERT_OK_PTR(skel, \"skel_open\"))\n\t\treturn -1;\n\n\tskel->links.connect_v4_dropper =\n\t\tbpf_program__attach_cgroup(skel->progs.connect_v4_dropper,\n\t\t\t\t\t   cgroup_fd);\n\tif (!ASSERT_OK_PTR(skel->links.connect_v4_dropper, \"prog_attach\")) {\n\t\terr = -1;\n\t\tgoto out;\n\t}\n\n\tif (classid && !ASSERT_OK(join_classid(), \"join_classid\")) {\n\t\terr = -1;\n\t\tgoto out;\n\t}\n\n\tfd = connect_to_fd_opts(server_fd, &opts);\n\tif (fd < 0)\n\t\terr = -1;\n\telse\n\t\tclose(fd);\nout:\n\tconnect4_dropper__destroy(skel);\n\treturn err;\n}",
        "static void mb_buddy_mark_free(struct ext4_buddy *e4b, int first, int last)\n{\n\tint max;\n\tint order = 1;\n\tvoid *buddy = mb_find_buddy(e4b, order, &max);": "static void mb_buddy_mark_free(struct ext4_buddy *e4b, int first, int last)\n{\n\tint max;\n\tint order = 1;\n\tvoid *buddy = mb_find_buddy(e4b, order, &max);\n\n\twhile (buddy) {\n\t\tvoid *buddy2;\n\n\t\t/* Bits in range [first; last] are known to be set since\n\t\t * corresponding blocks were allocated. Bits in range\n\t\t * (first; last) will stay set because they form buddies on\n\t\t * upper layer. We just deal with borders if they don't\n\t\t * align with upper layer and then go up.\n\t\t * Releasing entire group is all about clearing\n\t\t * single bit of highest order buddy.\n\t\t */\n\n\t\t/* Example:\n\t\t * ---------------------------------\n\t\t * |   1   |   1   |   1   |   1   |\n\t\t * ---------------------------------\n\t\t * | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |\n\t\t * ---------------------------------\n\t\t *   0   1   2   3   4   5   6   7\n\t\t *      \\_____________________/\n\t\t *\n\t\t * Neither [1] nor [6] is aligned to above layer.\n\t\t * Left neighbour [0] is free, so mark it busy,\n\t\t * decrease bb_counters and extend range to\n\t\t * [0; 6]\n\t\t * Right neighbour [7] is busy. It can't be coaleasced with [6], so\n\t\t * mark [6] free, increase bb_counters and shrink range to\n\t\t * [0; 5].\n\t\t * Then shift range to [0; 2], go up and do the same.\n\t\t */\n\n\n\t\tif (first & 1)\n\t\t\te4b->bd_info->bb_counters[order] += mb_buddy_adjust_border(&first, buddy, -1);\n\t\tif (!(last & 1))\n\t\t\te4b->bd_info->bb_counters[order] += mb_buddy_adjust_border(&last, buddy, 1);\n\t\tif (first > last)\n\t\t\tbreak;\n\t\torder++;\n\n\t\tif (first == last || !(buddy2 = mb_find_buddy(e4b, order, &max))) {\n\t\t\tmb_clear_bits(buddy, first, last - first + 1);\n\t\t\te4b->bd_info->bb_counters[order - 1] += last - first + 1;\n\t\t\tbreak;\n\t\t}\n\t\tfirst >>= 1;\n\t\tlast >>= 1;\n\t\tbuddy = buddy2;\n\t}\n}",
        "static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pf_vec)\n{\n\tstruct mlx5_irq_table *table = dev->priv.irq_table;\n\tint num_sf_ctrl_by_msix;\n\tint num_sf_ctrl_by_sfs;": "static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pf_vec)\n{\n\tstruct mlx5_irq_table *table = dev->priv.irq_table;\n\tint num_sf_ctrl_by_msix;\n\tint num_sf_ctrl_by_sfs;\n\tint num_sf_ctrl;\n\tint err;\n\n\t/* init pf_pool */\n\ttable->pf_pool = irq_pool_alloc(dev, 0, pf_vec, NULL,\n\t\t\t\t\tMLX5_EQ_SHARE_IRQ_MIN_COMP,\n\t\t\t\t\tMLX5_EQ_SHARE_IRQ_MAX_COMP);\n\tif (IS_ERR(table->pf_pool))\n\t\treturn PTR_ERR(table->pf_pool);\n\tif (!mlx5_sf_max_functions(dev))\n\t\treturn 0;\n\tif (sf_vec < MLX5_IRQ_VEC_COMP_BASE_SF) {\n\t\tmlx5_core_dbg(dev, \"Not enught IRQs for SFs. SF may run at lower performance\\n\");\n\t\treturn 0;\n\t}\n\n\t/* init sf_ctrl_pool */\n\tnum_sf_ctrl_by_msix = DIV_ROUND_UP(sf_vec, MLX5_COMP_EQS_PER_SF);\n\tnum_sf_ctrl_by_sfs = DIV_ROUND_UP(mlx5_sf_max_functions(dev),\n\t\t\t\t\t  MLX5_SFS_PER_CTRL_IRQ);\n\tnum_sf_ctrl = min_t(int, num_sf_ctrl_by_msix, num_sf_ctrl_by_sfs);\n\tnum_sf_ctrl = min_t(int, MLX5_IRQ_CTRL_SF_MAX, num_sf_ctrl);\n\ttable->sf_ctrl_pool = irq_pool_alloc(dev, pf_vec, num_sf_ctrl,\n\t\t\t\t\t     \"mlx5_sf_ctrl\",\n\t\t\t\t\t     MLX5_EQ_SHARE_IRQ_MIN_CTRL,\n\t\t\t\t\t     MLX5_EQ_SHARE_IRQ_MAX_CTRL);\n\tif (IS_ERR(table->sf_ctrl_pool)) {\n\t\terr = PTR_ERR(table->sf_ctrl_pool);\n\t\tgoto err_pf;\n\t}\n\t/* init sf_comp_pool */\n\ttable->sf_comp_pool = irq_pool_alloc(dev, pf_vec + num_sf_ctrl,\n\t\t\t\t\t     sf_vec - num_sf_ctrl, \"mlx5_sf_comp\",\n\t\t\t\t\t     MLX5_EQ_SHARE_IRQ_MIN_COMP,\n\t\t\t\t\t     MLX5_EQ_SHARE_IRQ_MAX_COMP);\n\tif (IS_ERR(table->sf_comp_pool)) {\n\t\terr = PTR_ERR(table->sf_comp_pool);\n\t\tgoto err_sf_ctrl;\n\t}\n\n\ttable->sf_comp_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);\n\tif (!table->sf_comp_pool->irqs_per_cpu) {\n\t\terr = -ENOMEM;\n\t\tgoto err_irqs_per_cpu;\n\t}\n\n\treturn 0;\n\nerr_irqs_per_cpu:\n\tirq_pool_free(table->sf_comp_pool);\nerr_sf_ctrl:\n\tirq_pool_free(table->sf_ctrl_pool);\nerr_pf:\n\tirq_pool_free(table->pf_pool);\n\treturn err;\n}",
        "static void mlxsw_sp_router_xm_cache_flush_work(struct work_struct *work)\n{\n\tstruct mlxsw_sp_router_xm_flush_info *flush_info;\n\tstruct mlxsw_sp_router_xm_flush_node *flush_node;\n\tchar rlcmld_pl[MLXSW_REG_RLCMLD_LEN];": "static void mlxsw_sp_router_xm_cache_flush_work(struct work_struct *work)\n{\n\tstruct mlxsw_sp_router_xm_flush_info *flush_info;\n\tstruct mlxsw_sp_router_xm_flush_node *flush_node;\n\tchar rlcmld_pl[MLXSW_REG_RLCMLD_LEN];\n\tenum mlxsw_reg_rlcmld_select select;\n\tstruct mlxsw_sp *mlxsw_sp;\n\tu32 addr4;\n\tint err;\n\n\tflush_node = container_of(work, struct mlxsw_sp_router_xm_flush_node,\n\t\t\t\t  dw.work);\n\tmlxsw_sp = flush_node->mlxsw_sp;\n\tflush_info = &flush_node->flush_info;\n\n\tif (flush_info->all) {\n\t\tchar rlpmce_pl[MLXSW_REG_RLPMCE_LEN];\n\n\t\tmlxsw_reg_rlpmce_pack(rlpmce_pl, true, false);\n\t\terr = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rlpmce),\n\t\t\t\t      rlpmce_pl);\n\t\tif (err)\n\t\t\tdev_err(mlxsw_sp->bus_info->dev, \"Failed to flush XM cache\\n\");\n\n\t\tif (flush_node->reuses <\n\t\t    MLXSW_SP_ROUTER_XM_CACHE_FLUSH_ALL_MIN_REUSES)\n\t\t\t/* Leaving flush-all mode. */\n\t\t\tmlxsw_sp->router->xm->flush_all_mode = false;\n\t\tgoto out;\n\t}\n\n\tselect = MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES;\n\n\tswitch (flush_info->proto) {\n\tcase MLXSW_SP_L3_PROTO_IPV4:\n\t\taddr4 = *((u32 *) flush_info->addr);\n\t\taddr4 &= mlxsw_sp_router_xm_flush_mask4(flush_info->prefix_len);\n\n\t\t/* In case the flush prefix length is bigger than M-value,\n\t\t * it makes no sense to flush M entries. So just flush\n\t\t * the ML entries.\n\t\t */\n\t\tif (flush_info->prefix_len > MLXSW_SP_ROUTER_XM_M_VAL)\n\t\t\tselect = MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES;\n\n\t\tmlxsw_reg_rlcmld_pack4(rlcmld_pl, select,\n\t\t\t\t       flush_info->virtual_router, addr4,\n\t\t\t\t       mlxsw_sp_router_xm_flush_mask4(flush_info->prefix_len));\n\t\tbreak;\n\tcase MLXSW_SP_L3_PROTO_IPV6:\n\t\tmlxsw_reg_rlcmld_pack6(rlcmld_pl, select,\n\t\t\t\t       flush_info->virtual_router, flush_info->addr,\n\t\t\t\t       mlxsw_sp_router_xm_flush_mask6(flush_info->prefix_len));\n\t\tbreak;\n\tdefault:\n\t\tWARN_ON(true);\n\t\tgoto out;\n\t}\n\terr = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rlcmld), rlcmld_pl);\n\tif (err)\n\t\tdev_err(mlxsw_sp->bus_info->dev, \"Failed to flush XM cache\\n\");\n\nout:\n\tmlxsw_sp_router_xm_cache_flush_node_destroy(mlxsw_sp, flush_node);\n}",
        "static int verify_opcode(struct page *page, unsigned long vaddr, uprobe_opcode_t *new_opcode)\n{\n\tuprobe_opcode_t old_opcode;\n\tbool is_swbp;\n": "static int verify_opcode(struct page *page, unsigned long vaddr, uprobe_opcode_t *new_opcode)\n{\n\tuprobe_opcode_t old_opcode;\n\tbool is_swbp;\n\n\t/*\n\t * Note: We only check if the old_opcode is UPROBE_SWBP_INSN here.\n\t * We do not check if it is any other 'trap variant' which could\n\t * be conditional trap instruction such as the one powerpc supports.\n\t *\n\t * The logic is that we do not care if the underlying instruction\n\t * is a trap variant; uprobes always wins over any other (gdb)\n\t * breakpoint.\n\t */\n\tcopy_from_page(page, vaddr, &old_opcode, UPROBE_SWBP_INSN_SIZE);\n\tis_swbp = is_swbp_insn(&old_opcode);\n\n\tif (is_swbp_insn(new_opcode)) {\n\t\tif (is_swbp)\t\t/* register: already installed? */\n\t\t\treturn 0;\n\t} else {\n\t\tif (!is_swbp)\t\t/* unregister: was it changed by us? */\n\t\t\treturn 0;\n\t}\n\n\treturn 1;\n}",
        "static int rcu_torture_barrier(void *arg)\n{\n\tint i;\n\n\tVERBOSE_TOROUT_STRING(\"rcu_torture_barrier task starting\");": "static int rcu_torture_barrier(void *arg)\n{\n\tint i;\n\n\tVERBOSE_TOROUT_STRING(\"rcu_torture_barrier task starting\");\n\tdo {\n\t\tatomic_set(&barrier_cbs_invoked, 0);\n\t\tatomic_set(&barrier_cbs_count, n_barrier_cbs);\n\t\t/* Ensure barrier_phase ordered after prior assignments. */\n\t\tsmp_store_release(&barrier_phase, !barrier_phase);\n\t\tfor (i = 0; i < n_barrier_cbs; i++)\n\t\t\twake_up(&barrier_cbs_wq[i]);\n\t\twait_event(barrier_wq,\n\t\t\t   atomic_read(&barrier_cbs_count) == 0 ||\n\t\t\t   torture_must_stop());\n\t\tif (torture_must_stop())\n\t\t\tbreak;\n\t\tn_barrier_attempts++;\n\t\tcur_ops->cb_barrier(); /* Implies smp_mb() for wait_event(). */\n\t\tif (atomic_read(&barrier_cbs_invoked) != n_barrier_cbs) {\n\t\t\tn_rcu_torture_barrier_error++;\n\t\t\tpr_err(\"barrier_cbs_invoked = %d, n_barrier_cbs = %d\\n\",\n\t\t\t       atomic_read(&barrier_cbs_invoked),\n\t\t\t       n_barrier_cbs);\n\t\t\tWARN_ON(1);\n\t\t\t// Wait manually for the remaining callbacks\n\t\t\ti = 0;\n\t\t\tdo {\n\t\t\t\tif (WARN_ON(i++ > HZ))\n\t\t\t\t\ti = INT_MIN;\n\t\t\t\tschedule_timeout_interruptible(1);\n\t\t\t\tcur_ops->cb_barrier();\n\t\t\t} while (atomic_read(&barrier_cbs_invoked) !=\n\t\t\t\t n_barrier_cbs &&\n\t\t\t\t !torture_must_stop());\n\t\t\tsmp_mb(); // Can't trust ordering if broken.\n\t\t\tif (!torture_must_stop())\n\t\t\t\tpr_err(\"Recovered: barrier_cbs_invoked = %d\\n\",\n\t\t\t\t       atomic_read(&barrier_cbs_invoked));\n\t\t} else {\n\t\t\tn_barrier_successes++;\n\t\t}\n\t\tschedule_timeout_interruptible(HZ / 10);\n\t} while (!torture_must_stop());\n\ttorture_kthread_stopping(\"rcu_torture_barrier\");\n\treturn 0;\n}",
        "static void query_chip(struct cmipci *cm)\n{\n\tunsigned int detect;\n\n\t/* check reg 0Ch, bit 24-31 */": "static void query_chip(struct cmipci *cm)\n{\n\tunsigned int detect;\n\n\t/* check reg 0Ch, bit 24-31 */\n\tdetect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;\n\tif (! detect) {\n\t\t/* check reg 08h, bit 24-28 */\n\t\tdetect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;\n\t\tswitch (detect) {\n\t\tcase 0:\n\t\t\tcm->chip_version = 33;\n\t\t\tif (cm->do_soft_ac3)\n\t\t\t\tcm->can_ac3_sw = 1;\n\t\t\telse\n\t\t\t\tcm->can_ac3_hw = 1;\n\t\t\tbreak;\n\t\tcase CM_CHIP_037:\n\t\t\tcm->chip_version = 37;\n\t\t\tcm->can_ac3_hw = 1;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tcm->chip_version = 39;\n\t\t\tcm->can_ac3_hw = 1;\n\t\t\tbreak;\n\t\t}\n\t\tcm->max_channels = 2;\n\t} else {\n\t\tif (detect & CM_CHIP_039) {\n\t\t\tcm->chip_version = 39;\n\t\t\tif (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */\n\t\t\t\tcm->max_channels = 6;\n\t\t\telse\n\t\t\t\tcm->max_channels = 4;\n\t\t} else if (detect & CM_CHIP_8768) {\n\t\t\tcm->chip_version = 68;\n\t\t\tcm->max_channels = 8;\n\t\t\tcm->can_96k = 1;\n\t\t} else {\n\t\t\tcm->chip_version = 55;\n\t\t\tcm->max_channels = 6;\n\t\t\tcm->can_96k = 1;\n\t\t}\n\t\tcm->can_ac3_hw = 1;\n\t\tcm->can_multi_ch = 1;\n\t}\n}",
        "static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct iscsi_kwqe_conn_update *req =\n\t\t(struct iscsi_kwqe_conn_update *) kwqe;": "static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct iscsi_kwqe_conn_update *req =\n\t\t(struct iscsi_kwqe_conn_update *) kwqe;\n\tvoid *data;\n\tunion l5cm_specific_data l5_data;\n\tu32 l5_cid, cid = BNX2X_SW_CID(req->context_id);\n\tint ret;\n\n\tif (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)\n\t\treturn -EINVAL;\n\n\tdata = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tmemcpy(data, kwqe, sizeof(struct kwqe));\n\n\tret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,\n\t\t\treq->context_id, ISCSI_CONNECTION_TYPE, &l5_data);\n\treturn ret;\n}",
        "static int nl80211_deauthenticate(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct cfg80211_registered_device *rdev = info->user_ptr[0];\n\tstruct net_device *dev = info->user_ptr[1];\n\tconst u8 *ie = NULL, *bssid;": "static int nl80211_deauthenticate(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct cfg80211_registered_device *rdev = info->user_ptr[0];\n\tstruct net_device *dev = info->user_ptr[1];\n\tconst u8 *ie = NULL, *bssid;\n\tint ie_len = 0, err;\n\tu16 reason_code;\n\tbool local_state_change;\n\n\tif (dev->ieee80211_ptr->conn_owner_nlportid &&\n\t    dev->ieee80211_ptr->conn_owner_nlportid != info->snd_portid)\n\t\treturn -EPERM;\n\n\tif (!info->attrs[NL80211_ATTR_MAC])\n\t\treturn -EINVAL;\n\n\tif (!info->attrs[NL80211_ATTR_REASON_CODE])\n\t\treturn -EINVAL;\n\n\tif (!rdev->ops->deauth)\n\t\treturn -EOPNOTSUPP;\n\n\tif (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_STATION &&\n\t    dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_CLIENT)\n\t\treturn -EOPNOTSUPP;\n\n\tbssid = nla_data(info->attrs[NL80211_ATTR_MAC]);\n\n\treason_code = nla_get_u16(info->attrs[NL80211_ATTR_REASON_CODE]);\n\tif (reason_code == 0) {\n\t\t/* Reason Code 0 is reserved */\n\t\treturn -EINVAL;\n\t}\n\n\tif (info->attrs[NL80211_ATTR_IE]) {\n\t\tie = nla_data(info->attrs[NL80211_ATTR_IE]);\n\t\tie_len = nla_len(info->attrs[NL80211_ATTR_IE]);\n\t}\n\n\tlocal_state_change = !!info->attrs[NL80211_ATTR_LOCAL_STATE_CHANGE];\n\n\twdev_lock(dev->ieee80211_ptr);\n\terr = cfg80211_mlme_deauth(rdev, dev, bssid, ie, ie_len, reason_code,\n\t\t\t\t   local_state_change);\n\twdev_unlock(dev->ieee80211_ptr);\n\treturn err;\n}",
        "static int aq_a2_fw_init(struct aq_hw_s *self)\n{\n\tstruct link_control_s link_control;\n\tu32 mtu;\n\tu32 val;": "static int aq_a2_fw_init(struct aq_hw_s *self)\n{\n\tstruct link_control_s link_control;\n\tu32 mtu;\n\tu32 val;\n\tint err;\n\n\thw_atl2_shared_buffer_get(self, link_control, link_control);\n\tlink_control.mode = AQ_HOST_MODE_ACTIVE;\n\thw_atl2_shared_buffer_write(self, link_control, link_control);\n\n\thw_atl2_shared_buffer_get(self, mtu, mtu);\n\tmtu = HW_ATL2_MTU_JUMBO;\n\thw_atl2_shared_buffer_write(self, mtu, mtu);\n\n\thw_atl2_mif_host_finished_write_set(self, 1U);\n\terr = readx_poll_timeout_atomic(hw_atl2_mif_mcp_finished_read_get,\n\t\t\t\t\tself, val, val == 0U,\n\t\t\t\t\t100, 5000000U);\n\tWARN(err, \"hw_atl2_shared_buffer_finish_ack\");\n\n\treturn err;\n}",
        "static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)\n{\n\tdw_spi_reset_chip(dws);\n\n\t/*": "static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)\n{\n\tdw_spi_reset_chip(dws);\n\n\t/*\n\t * Retrieve the Synopsys component version if it hasn't been specified\n\t * by the platform. CoreKit version ID is encoded as a 3-chars ASCII\n\t * code enclosed with '*' (typical for the most of Synopsys IP-cores).\n\t */\n\tif (!dws->ver) {\n\t\tdws->ver = dw_readl(dws, DW_SPI_VERSION);\n\n\t\tdev_dbg(dev, \"Synopsys DWC%sSSI v%c.%c%c\\n\",\n\t\t\tdw_spi_ip_is(dws, PSSI) ? \" APB \" : \" \",\n\t\t\tDW_SPI_GET_BYTE(dws->ver, 3), DW_SPI_GET_BYTE(dws->ver, 2),\n\t\t\tDW_SPI_GET_BYTE(dws->ver, 1));\n\t}\n\n\t/*\n\t * Try to detect the FIFO depth if not set by interface driver,\n\t * the depth could be from 2 to 256 from HW spec\n\t */\n\tif (!dws->fifo_len) {\n\t\tu32 fifo;\n\n\t\tfor (fifo = 1; fifo < 256; fifo++) {\n\t\t\tdw_writel(dws, DW_SPI_TXFTLR, fifo);\n\t\t\tif (fifo != dw_readl(dws, DW_SPI_TXFTLR))\n\t\t\t\tbreak;\n\t\t}\n\t\tdw_writel(dws, DW_SPI_TXFTLR, 0);\n\n\t\tdws->fifo_len = (fifo == 1) ? 0 : fifo;\n\t\tdev_dbg(dev, \"Detected FIFO size: %u bytes\\n\", dws->fifo_len);\n\t}\n\n\t/*\n\t * Detect CTRLR0.DFS field size and offset by testing the lowest bits\n\t * writability. Note DWC SSI controller also has the extended DFS, but\n\t * with zero offset.\n\t */\n\tif (dw_spi_ip_is(dws, PSSI)) {\n\t\tu32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);\n\n\t\tdw_spi_enable_chip(dws, 0);\n\t\tdw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);\n\t\tcr0 = dw_readl(dws, DW_SPI_CTRLR0);\n\t\tdw_writel(dws, DW_SPI_CTRLR0, tmp);\n\t\tdw_spi_enable_chip(dws, 1);\n\n\t\tif (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) {\n\t\t\tdws->caps |= DW_SPI_CAP_DFS32;\n\t\t\tdws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK);\n\t\t\tdev_dbg(dev, \"Detected 32-bits max data frame size\\n\");\n\t\t}\n\t} else {\n\t\tdws->caps |= DW_SPI_CAP_DFS32;\n\t}\n\n\t/* enable HW fixup for explicit CS deselect for Amazon's alpine chip */\n\tif (dws->caps & DW_SPI_CAP_CS_OVERRIDE)\n\t\tdw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);\n}",
        "static void super_sync(struct mddev *mddev, struct md_rdev *rdev)\n{\n\tbool update_failed_devices = false;\n\tunsigned int i;\n\tuint64_t failed_devices[DISKS_ARRAY_ELEMS];": "static void super_sync(struct mddev *mddev, struct md_rdev *rdev)\n{\n\tbool update_failed_devices = false;\n\tunsigned int i;\n\tuint64_t failed_devices[DISKS_ARRAY_ELEMS];\n\tstruct dm_raid_superblock *sb;\n\tstruct raid_set *rs = container_of(mddev, struct raid_set, md);\n\n\t/* No metadata device, no superblock */\n\tif (!rdev->meta_bdev)\n\t\treturn;\n\n\tBUG_ON(!rdev->sb_page);\n\n\tsb = page_address(rdev->sb_page);\n\n\tsb_retrieve_failed_devices(sb, failed_devices);\n\n\tfor (i = 0; i < rs->raid_disks; i++)\n\t\tif (!rs->dev[i].data_dev || test_bit(Faulty, &rs->dev[i].rdev.flags)) {\n\t\t\tupdate_failed_devices = true;\n\t\t\tset_bit(i, (void *) failed_devices);\n\t\t}\n\n\tif (update_failed_devices)\n\t\tsb_update_failed_devices(sb, failed_devices);\n\n\tsb->magic = cpu_to_le32(DM_RAID_MAGIC);\n\tsb->compat_features = cpu_to_le32(FEATURE_FLAG_SUPPORTS_V190);\n\n\tsb->num_devices = cpu_to_le32(mddev->raid_disks);\n\tsb->array_position = cpu_to_le32(rdev->raid_disk);\n\n\tsb->events = cpu_to_le64(mddev->events);\n\n\tsb->disk_recovery_offset = cpu_to_le64(rdev->recovery_offset);\n\tsb->array_resync_offset = cpu_to_le64(mddev->recovery_cp);\n\n\tsb->level = cpu_to_le32(mddev->level);\n\tsb->layout = cpu_to_le32(mddev->layout);\n\tsb->stripe_sectors = cpu_to_le32(mddev->chunk_sectors);\n\n\t/********************************************************************\n\t * BELOW FOLLOW V1.9.0 EXTENSIONS TO THE PRISTINE SUPERBLOCK FORMAT!!!\n\t *\n\t * FEATURE_FLAG_SUPPORTS_V190 in the compat_features member indicates that those exist\n\t */\n\tsb->new_level = cpu_to_le32(mddev->new_level);\n\tsb->new_layout = cpu_to_le32(mddev->new_layout);\n\tsb->new_stripe_sectors = cpu_to_le32(mddev->new_chunk_sectors);\n\n\tsb->delta_disks = cpu_to_le32(mddev->delta_disks);\n\n\tsmp_rmb(); /* Make sure we access most recent reshape position */\n\tsb->reshape_position = cpu_to_le64(mddev->reshape_position);\n\tif (le64_to_cpu(sb->reshape_position) != MaxSector) {\n\t\t/* Flag ongoing reshape */\n\t\tsb->flags |= cpu_to_le32(SB_FLAG_RESHAPE_ACTIVE);\n\n\t\tif (mddev->delta_disks < 0 || mddev->reshape_backwards)\n\t\t\tsb->flags |= cpu_to_le32(SB_FLAG_RESHAPE_BACKWARDS);\n\t} else {\n\t\t/* Clear reshape flags */\n\t\tsb->flags &= ~(cpu_to_le32(SB_FLAG_RESHAPE_ACTIVE|SB_FLAG_RESHAPE_BACKWARDS));\n\t}\n\n\tsb->array_sectors = cpu_to_le64(mddev->array_sectors);\n\tsb->data_offset = cpu_to_le64(rdev->data_offset);\n\tsb->new_data_offset = cpu_to_le64(rdev->new_data_offset);\n\tsb->sectors = cpu_to_le64(rdev->sectors);\n\tsb->incompat_features = cpu_to_le32(0);\n\n\t/* Zero out the rest of the payload after the size of the superblock */\n\tmemset(sb + 1, 0, rdev->sb_size - sizeof(*sb));\n}",
        "static int parse_usdt_arg(const char *arg_str, int arg_num, struct usdt_arg_spec *arg)\n{\n\tchar *reg_name = NULL;\n\tint arg_sz, len, reg_off;\n\tlong off;": "static int parse_usdt_arg(const char *arg_str, int arg_num, struct usdt_arg_spec *arg)\n{\n\tchar *reg_name = NULL;\n\tint arg_sz, len, reg_off;\n\tlong off;\n\n\tif (sscanf(arg_str, \" %d @ \\[ %m[a-z0-9], %ld ] %n\", &arg_sz, &reg_name, &off, &len) == 3) {\n\t\t/* Memory dereference case, e.g., -4@[sp, 96] */\n\t\targ->arg_type = USDT_ARG_REG_DEREF;\n\t\targ->val_off = off;\n\t\treg_off = calc_pt_regs_off(reg_name);\n\t\tfree(reg_name);\n\t\tif (reg_off < 0)\n\t\t\treturn reg_off;\n\t\targ->reg_off = reg_off;\n\t} else if (sscanf(arg_str, \" %d @ \\[ %m[a-z0-9] ] %n\", &arg_sz, &reg_name, &len) == 2) {\n\t\t/* Memory dereference case, e.g., -4@[sp] */\n\t\targ->arg_type = USDT_ARG_REG_DEREF;\n\t\targ->val_off = 0;\n\t\treg_off = calc_pt_regs_off(reg_name);\n\t\tfree(reg_name);\n\t\tif (reg_off < 0)\n\t\t\treturn reg_off;\n\t\targ->reg_off = reg_off;\n\t} else if (sscanf(arg_str, \" %d @ %ld %n\", &arg_sz, &off, &len) == 2) {\n\t\t/* Constant value case, e.g., 4@5 */\n\t\targ->arg_type = USDT_ARG_CONST;\n\t\targ->val_off = off;\n\t\targ->reg_off = 0;\n\t} else if (sscanf(arg_str, \" %d @ %m[a-z0-9] %n\", &arg_sz, &reg_name, &len) == 2) {\n\t\t/* Register read case, e.g., -8@x4 */\n\t\targ->arg_type = USDT_ARG_REG;\n\t\targ->val_off = 0;\n\t\treg_off = calc_pt_regs_off(reg_name);\n\t\tfree(reg_name);\n\t\tif (reg_off < 0)\n\t\t\treturn reg_off;\n\t\targ->reg_off = reg_off;\n\t} else {\n\t\tpr_warn(\"usdt: unrecognized arg #%d spec '%s'\\n\", arg_num, arg_str);\n\t\treturn -EINVAL;\n\t}\n\n\targ->arg_signed = arg_sz < 0;\n\tif (arg_sz < 0)\n\t\targ_sz = -arg_sz;\n\n\tswitch (arg_sz) {\n\tcase 1: case 2: case 4: case 8:\n\t\targ->arg_bitshift = 64 - arg_sz * 8;\n\t\tbreak;\n\tdefault:\n\t\tpr_warn(\"usdt: unsupported arg #%d (spec '%s') size: %d\\n\",\n\t\t\targ_num, arg_str, arg_sz);\n\t\treturn -EINVAL;\n\t}\n\n\treturn len;\n}",
        "static int __init test_c1(void)\n{\n\tconst u8 k[16] = {\n\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };": "static int __init test_c1(void)\n{\n\tconst u8 k[16] = {\n\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\tconst u8 r[16] = {\n\t\t\t0xe0, 0x2e, 0x70, 0xc6, 0x4e, 0x27, 0x88, 0x63,\n\t\t\t0x0e, 0x6f, 0xad, 0x56, 0x21, 0xd5, 0x83, 0x57 };\n\tconst u8 preq[7] = { 0x01, 0x01, 0x00, 0x00, 0x10, 0x07, 0x07 };\n\tconst u8 pres[7] = { 0x02, 0x03, 0x00, 0x00, 0x08, 0x00, 0x05 };\n\tconst u8 _iat = 0x01;\n\tconst u8 _rat = 0x00;\n\tconst bdaddr_t ra = { { 0xb6, 0xb5, 0xb4, 0xb3, 0xb2, 0xb1 } };\n\tconst bdaddr_t ia = { { 0xa6, 0xa5, 0xa4, 0xa3, 0xa2, 0xa1 } };\n\tconst u8 exp[16] = {\n\t\t\t0x86, 0x3b, 0xf1, 0xbe, 0xc5, 0x4d, 0xa7, 0xd2,\n\t\t\t0xea, 0x88, 0x89, 0x87, 0xef, 0x3f, 0x1e, 0x1e };\n\tu8 res[16];\n\tint err;\n\n\terr = smp_c1(k, r, preq, pres, _iat, &ia, _rat, &ra, res);\n\tif (err)\n\t\treturn err;\n\n\tif (crypto_memneq(res, exp, 16))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}",
        "static int prepare_read_control(struct ceph_connection *con)\n{\n\tint ctrl_len = con->v2.in_desc.fd_lens[0];\n\tint head_len;\n\tvoid *buf;": "static int prepare_read_control(struct ceph_connection *con)\n{\n\tint ctrl_len = con->v2.in_desc.fd_lens[0];\n\tint head_len;\n\tvoid *buf;\n\n\treset_in_kvecs(con);\n\tif (con->state == CEPH_CON_S_V2_HELLO ||\n\t    con->state == CEPH_CON_S_V2_AUTH) {\n\t\thead_len = head_onwire_len(ctrl_len, false);\n\t\tbuf = alloc_conn_buf(con, head_len);\n\t\tif (!buf)\n\t\t\treturn -ENOMEM;\n\n\t\t/* preserve preamble */\n\t\tmemcpy(buf, con->v2.in_buf, CEPH_PREAMBLE_LEN);\n\n\t\tadd_in_kvec(con, CTRL_BODY(buf), ctrl_len);\n\t\tadd_in_kvec(con, CTRL_BODY(buf) + ctrl_len, CEPH_CRC_LEN);\n\t\tadd_in_sign_kvec(con, buf, head_len);\n\t} else {\n\t\tif (ctrl_len > CEPH_PREAMBLE_INLINE_LEN) {\n\t\t\tbuf = alloc_conn_buf(con, ctrl_len);\n\t\t\tif (!buf)\n\t\t\t\treturn -ENOMEM;\n\n\t\t\tadd_in_kvec(con, buf, ctrl_len);\n\t\t} else {\n\t\t\tadd_in_kvec(con, CTRL_BODY(con->v2.in_buf), ctrl_len);\n\t\t}\n\t\tadd_in_kvec(con, con->v2.in_buf, CEPH_CRC_LEN);\n\t}\n\tcon->v2.in_state = IN_S_HANDLE_CONTROL;\n\treturn 0;\n}",
        "static void nfdi_decompose(void)\n{\n\tunsigned int unichar;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */\n\tunsigned int *um;": "static void nfdi_decompose(void)\n{\n\tunsigned int unichar;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */\n\tunsigned int *um;\n\tunsigned int *dc;\n\tint count;\n\tint i;\n\tint j;\n\tint ret;\n\n\tif (verbose > 0)\n\t\tprintf(\"Decomposing nfdi\\n\");\n\n\tcount = 0;\n\tfor (unichar = 0; unichar != 0x110000; unichar++) {\n\t\tif (!unicode_data[unichar].utf32nfdi)\n\t\t\tcontinue;\n\t\tfor (;;) {\n\t\t\tret = 1;\n\t\t\ti = 0;\n\t\t\tum = unicode_data[unichar].utf32nfdi;\n\t\t\twhile (*um) {\n\t\t\t\tdc = unicode_data[*um].utf32nfdi;\n\t\t\t\tif (dc) {\n\t\t\t\t\tfor (j = 0; dc[j]; j++)\n\t\t\t\t\t\tmapping[i++] = dc[j];\n\t\t\t\t\tret = 0;\n\t\t\t\t} else {\n\t\t\t\t\tmapping[i++] = *um;\n\t\t\t\t}\n\t\t\t\tum++;\n\t\t\t}\n\t\t\tmapping[i++] = 0;\n\t\t\tif (ret)\n\t\t\t\tbreak;\n\t\t\tfree(unicode_data[unichar].utf32nfdi);\n\t\t\tum = malloc(i * sizeof(unsigned int));\n\t\t\tmemcpy(um, mapping, i * sizeof(unsigned int));\n\t\t\tunicode_data[unichar].utf32nfdi = um;\n\t\t}\n\t\t/* Add this decomposition to nfdicf if there is no entry. */\n\t\tif (!unicode_data[unichar].utf32nfdicf) {\n\t\t\tum = malloc(i * sizeof(unsigned int));\n\t\t\tmemcpy(um, mapping, i * sizeof(unsigned int));\n\t\t\tunicode_data[unichar].utf32nfdicf = um;\n\t\t}\n\t\tif (verbose > 1)\n\t\t\tprint_utf32nfdi(unichar);\n\t\tcount++;\n\t}\n\tif (verbose > 0)\n\t\tprintf(\"Processed %d entries\\n\", count);\n}",
        "static int qp_get_mtt_size(struct mlx4_qp_context *qpc)\n{\n\tint page_shift = (qpc->log_page_size & 0x3f) + 12;\n\tint log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;\n\tint log_sq_sride = qpc->sq_size_stride & 7;": "static int qp_get_mtt_size(struct mlx4_qp_context *qpc)\n{\n\tint page_shift = (qpc->log_page_size & 0x3f) + 12;\n\tint log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;\n\tint log_sq_sride = qpc->sq_size_stride & 7;\n\tint log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;\n\tint log_rq_stride = qpc->rq_size_stride & 7;\n\tint srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;\n\tint rss = (be32_to_cpu(qpc->flags) >> 13) & 1;\n\tu32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;\n\tint xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;\n\tint sq_size;\n\tint rq_size;\n\tint total_pages;\n\tint total_mem;\n\tint page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;\n\tint tot;\n\n\tsq_size = 1 << (log_sq_size + log_sq_sride + 4);\n\trq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));\n\ttotal_mem = sq_size + rq_size;\n\ttot = (total_mem + (page_offset << 6)) >> page_shift;\n\ttotal_pages = !tot ? 1 : roundup_pow_of_two(tot);\n\n\treturn total_pages;\n}",
        "static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)\n{\n\tstruct cnic_dev *dev = csk->dev;\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];": "static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)\n{\n\tstruct cnic_dev *dev = csk->dev;\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];\n\tunion l5cm_specific_data l5_data;\n\tu32 cmd = 0;\n\tint close_complete = 0;\n\n\tswitch (opcode) {\n\tcase L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:\n\tcase L4_KCQE_OPCODE_VALUE_CLOSE_COMP:\n\tcase L4_KCQE_OPCODE_VALUE_RESET_COMP:\n\t\tif (cnic_ready_to_close(csk, opcode)) {\n\t\t\tif (test_bit(SK_F_HW_ERR, &csk->flags))\n\t\t\t\tclose_complete = 1;\n\t\t\telse if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))\n\t\t\t\tcmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;\n\t\t\telse\n\t\t\t\tclose_complete = 1;\n\t\t}\n\t\tbreak;\n\tcase L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:\n\t\tcmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;\n\t\tbreak;\n\tcase L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:\n\t\tclose_complete = 1;\n\t\tbreak;\n\t}\n\tif (cmd) {\n\t\tmemset(&l5_data, 0, sizeof(l5_data));\n\n\t\tcnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,\n\t\t\t\t    &l5_data);\n\t} else if (close_complete) {\n\t\tctx->timestamp = jiffies;\n\t\tcnic_close_conn(csk);\n\t\tcnic_cm_upcall(cp, csk, csk->state);\n\t}\n}",
        "static void test_getsockopt_get(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_getsockopt *obj;\n\tstruct bpf_link *link_get_retval = NULL;\n\tint buf;": "static void test_getsockopt_get(int cgroup_fd, int sock_fd)\n{\n\tstruct cgroup_getset_retval_getsockopt *obj;\n\tstruct bpf_link *link_get_retval = NULL;\n\tint buf;\n\tsocklen_t optlen = sizeof(buf);\n\n\tobj = cgroup_getset_retval_getsockopt__open_and_load();\n\tif (!ASSERT_OK_PTR(obj, \"skel-load\"))\n\t\treturn;\n\n\t/* Attach getsockopt that gets previously set errno. Assert that the\n\t * error from kernel is in both ctx_retval_value and retval_value.\n\t */\n\tlink_get_retval = bpf_program__attach_cgroup(obj->progs.get_retval,\n\t\t\t\t\t\t     cgroup_fd);\n\tif (!ASSERT_OK_PTR(link_get_retval, \"cg-attach-get_retval\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_ERR(getsockopt(sock_fd, SOL_CUSTOM, 0,\n\t\t\t\t   &buf, &optlen), \"getsockopt\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(errno, EOPNOTSUPP, \"getsockopt-errno\"))\n\t\tgoto close_bpf_object;\n\n\tif (!ASSERT_EQ(obj->bss->invocations, 1, \"invocations\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_FALSE(obj->bss->assertion_error, \"assertion_error\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->retval_value, -EOPNOTSUPP, \"retval_value\"))\n\t\tgoto close_bpf_object;\n\tif (!ASSERT_EQ(obj->bss->ctx_retval_value, -EOPNOTSUPP, \"ctx_retval_value\"))\n\t\tgoto close_bpf_object;\n\nclose_bpf_object:\n\tbpf_link__destroy(link_get_retval);\n\n\tcgroup_getset_retval_getsockopt__destroy(obj);\n}",
        "static int io_read(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_rw_state __s, *s = &__s;\n\tstruct iovec *iovec;\n\tstruct kiocb *kiocb = &req->rw.kiocb;": "static int io_read(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tstruct io_rw_state __s, *s = &__s;\n\tstruct iovec *iovec;\n\tstruct kiocb *kiocb = &req->rw.kiocb;\n\tbool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;\n\tstruct io_async_rw *rw;\n\tssize_t ret, ret2;\n\tloff_t *ppos;\n\n\tif (!req_has_async_data(req)) {\n\t\tret = io_import_iovec(READ, req, &iovec, s, issue_flags);\n\t\tif (unlikely(ret < 0))\n\t\t\treturn ret;\n\t} else {\n\t\t/*\n\t\t * Safe and required to re-import if we're using provided\n\t\t * buffers, as we dropped the selected one before retry.\n\t\t */\n\t\tif (req->flags & REQ_F_BUFFER_SELECT) {\n\t\t\tret = io_import_iovec(READ, req, &iovec, s, issue_flags);\n\t\t\tif (unlikely(ret < 0))\n\t\t\t\treturn ret;\n\t\t}\n\n\t\trw = req->async_data;\n\t\ts = &rw->s;\n\t\t/*\n\t\t * We come here from an earlier attempt, restore our state to\n\t\t * match in case it doesn't. It's cheap enough that we don't\n\t\t * need to make this conditional.\n\t\t */\n\t\tiov_iter_restore(&s->iter, &s->iter_state);\n\t\tiovec = NULL;\n\t}\n\tret = io_rw_init_file(req, FMODE_READ);\n\tif (unlikely(ret)) {\n\t\tkfree(iovec);\n\t\treturn ret;\n\t}\n\treq->cqe.res = iov_iter_count(&s->iter);\n\n\tif (force_nonblock) {\n\t\t/* If the file doesn't support async, just async punt */\n\t\tif (unlikely(!io_file_supports_nowait(req))) {\n\t\t\tret = io_setup_async_rw(req, iovec, s, true);\n\t\t\treturn ret ?: -EAGAIN;\n\t\t}\n\t\tkiocb->ki_flags |= IOCB_NOWAIT;\n\t} else {\n\t\t/* Ensure we clear previously set non-block flag */\n\t\tkiocb->ki_flags &= ~IOCB_NOWAIT;\n\t}\n\n\tppos = io_kiocb_update_pos(req);\n\n\tret = rw_verify_area(READ, req->file, ppos, req->cqe.res);\n\tif (unlikely(ret)) {\n\t\tkfree(iovec);\n\t\treturn ret;\n\t}\n\n\tret = io_iter_do_read(req, &s->iter);\n\n\tif (ret == -EAGAIN || (req->flags & REQ_F_REISSUE)) {\n\t\treq->flags &= ~REQ_F_REISSUE;\n\t\t/* if we can poll, just do that */\n\t\tif (req->opcode == IORING_OP_READ && file_can_poll(req->file))\n\t\t\treturn -EAGAIN;\n\t\t/* IOPOLL retry should happen for io-wq threads */\n\t\tif (!force_nonblock && !(req->ctx->flags & IORING_SETUP_IOPOLL))\n\t\t\tgoto done;\n\t\t/* no retry on NONBLOCK nor RWF_NOWAIT */\n\t\tif (req->flags & REQ_F_NOWAIT)\n\t\t\tgoto done;\n\t\tret = 0;\n\t} else if (ret == -EIOCBQUEUED) {\n\t\tgoto out_free;\n\t} else if (ret == req->cqe.res || ret <= 0 || !force_nonblock ||\n\t\t   (req->flags & REQ_F_NOWAIT) || !need_read_all(req)) {\n\t\t/* read all, failed, already did sync or don't want to retry */\n\t\tgoto done;\n\t}\n\n\t/*\n\t * Don't depend on the iter state matching what was consumed, or being\n\t * untouched in case of error. Restore it and we'll advance it\n\t * manually if we need to.\n\t */\n\tiov_iter_restore(&s->iter, &s->iter_state);\n\n\tret2 = io_setup_async_rw(req, iovec, s, true);\n\tif (ret2)\n\t\treturn ret2;\n\n\tiovec = NULL;\n\trw = req->async_data;\n\ts = &rw->s;\n\t/*\n\t * Now use our persistent iterator and state, if we aren't already.\n\t * We've restored and mapped the iter to match.\n\t */\n\n\tdo {\n\t\t/*\n\t\t * We end up here because of a partial read, either from\n\t\t * above or inside this loop. Advance the iter by the bytes\n\t\t * that were consumed.\n\t\t */\n\t\tiov_iter_advance(&s->iter, ret);\n\t\tif (!iov_iter_count(&s->iter))\n\t\t\tbreak;\n\t\trw->bytes_done += ret;\n\t\tiov_iter_save_state(&s->iter, &s->iter_state);\n\n\t\t/* if we can retry, do so with the callbacks armed */\n\t\tif (!io_rw_should_retry(req)) {\n\t\t\tkiocb->ki_flags &= ~IOCB_WAITQ;\n\t\t\treturn -EAGAIN;\n\t\t}\n\n\t\t/*\n\t\t * Now retry read with the IOCB_WAITQ parts set in the iocb. If\n\t\t * we get -EIOCBQUEUED, then we'll get a notification when the\n\t\t * desired page gets unlocked. We can also get a partial read\n\t\t * here, and if we do, then just retry at the new offset.\n\t\t */\n\t\tret = io_iter_do_read(req, &s->iter);\n\t\tif (ret == -EIOCBQUEUED)\n\t\t\treturn 0;\n\t\t/* we got some bytes, but not all. retry. */\n\t\tkiocb->ki_flags &= ~IOCB_WAITQ;\n\t\tiov_iter_restore(&s->iter, &s->iter_state);\n\t} while (ret > 0);\ndone:\n\tkiocb_done(req, ret, issue_flags);\nout_free:\n\t/* it's faster to check here then delegate to kfree */\n\tif (iovec)\n\t\tkfree(iovec);\n\treturn 0;\n}",
        "static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)\n{\n\tu32 osc_reference, osc_mask;\n\tu8 mode;\n\tint err;": "static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)\n{\n\tu32 osc_reference, osc_mask;\n\tu8 mode;\n\tint err;\n\n\t/* Check for reset defaults of OSC reg.\n\t * This will take care of stabilization period.\n\t */\n\tosc_reference = MCP251XFD_REG_OSC_OSCRDY |\n\t\tFIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,\n\t\t\t   MCP251XFD_REG_OSC_CLKODIV_10);\n\tosc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;\n\terr = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);\n\tif (err)\n\t\treturn err;\n\n\terr = mcp251xfd_chip_get_mode(priv, &mode);\n\tif (err)\n\t\treturn err;\n\n\tif (mode != MCP251XFD_REG_CON_MODE_CONFIG) {\n\t\tnetdev_info(priv->ndev,\n\t\t\t    \"Controller not in Config Mode after reset, but in %s Mode (%u).\\n\",\n\t\t\t    mcp251xfd_get_mode_str(mode), mode);\n\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}",
        "static void corrections_init(void)\n{\n\tFILE *file;\n\tunsigned int unichar;\n\tunsigned int major;": "static void corrections_init(void)\n{\n\tFILE *file;\n\tunsigned int unichar;\n\tunsigned int major;\n\tunsigned int minor;\n\tunsigned int revision;\n\tunsigned int age;\n\tunsigned int *um;\n\tunsigned int mapping[19]; /* Magic - guaranteed not to be exceeded. */\n\tchar *s;\n\tint i;\n\tint count;\n\tint ret;\n\n\tif (verbose > 0)\n\t\tprintf(\"Parsing %s\\n\", norm_name);\n\tfile = fopen(norm_name, \"r\");\n\tif (!file)\n\t\topen_fail(norm_name, errno);\n\n\tcount = 0;\n\twhile (fgets(line, LINESIZE, file)) {\n\t\tret = sscanf(line, \"%X;%[^;];%[^;];%d.%d.%d #\",\n\t\t\t\t&unichar, buf0, buf1,\n\t\t\t\t&major, &minor, &revision);\n\t\tif (ret != 6)\n\t\t\tcontinue;\n\t\tif (!utf32valid(unichar) || !age_valid(major, minor, revision))\n\t\t\tline_fail(norm_name, line);\n\t\tcount++;\n\t}\n\tcorrections = calloc(count, sizeof(struct unicode_data));\n\tcorrections_count = count;\n\trewind(file);\n\n\tcount = 0;\n\twhile (fgets(line, LINESIZE, file)) {\n\t\tret = sscanf(line, \"%X;%[^;];%[^;];%d.%d.%d #\",\n\t\t\t\t&unichar, buf0, buf1,\n\t\t\t\t&major, &minor, &revision);\n\t\tif (ret != 6)\n\t\t\tcontinue;\n\t\tif (!utf32valid(unichar) || !age_valid(major, minor, revision))\n\t\t\tline_fail(norm_name, line);\n\t\tcorrections[count] = unicode_data[unichar];\n\t\tassert(corrections[count].code == unichar);\n\t\tage = UNICODE_AGE(major, minor, revision);\n\t\tcorrections[count].correction = age;\n\n\t\ti = 0;\n\t\ts = buf0;\n\t\twhile (*s) {\n\t\t\tmapping[i] = strtoul(s, &s, 16);\n\t\t\tif (!utf32valid(mapping[i]))\n\t\t\t\tline_fail(norm_name, line);\n\t\t\ti++;\n\t\t}\n\t\tmapping[i++] = 0;\n\n\t\tum = malloc(i * sizeof(unsigned int));\n\t\tmemcpy(um, mapping, i * sizeof(unsigned int));\n\t\tcorrections[count].utf32nfdi = um;\n\n\t\tif (verbose > 1)\n\t\t\tprintf(\" %X -> %s -> %s V%d_%d_%d\\n\",\n\t\t\t\tunichar, buf0, buf1, major, minor, revision);\n\t\tcount++;\n\t}\n\tfclose(file);\n\n\tif (verbose > 0)\n\t        printf(\"Found %d entries\\n\", count);\n\tif (count == 0)\n\t\tfile_fail(norm_name);\n}",
        "static int cxusb_videoradio_open(struct file *f)\n{\n\tstruct dvb_usb_device *dvbdev = video_drvdata(f);\n\tint ret;\n": "static int cxusb_videoradio_open(struct file *f)\n{\n\tstruct dvb_usb_device *dvbdev = video_drvdata(f);\n\tint ret;\n\n\t/*\n\t * no locking needed since this call only modifies analog\n\t * state if there are no other analog handles currenly\n\t * opened so ops done via them cannot create a conflict\n\t */\n\tret = cxusb_medion_get(dvbdev, CXUSB_OPEN_ANALOG);\n\tif (ret != 0)\n\t\treturn ret;\n\n\tret = v4l2_fh_open(f);\n\tif (ret != 0)\n\t\tgoto ret_release;\n\n\tcxusb_vprintk(dvbdev, OPS, \"got open\\n\");\n\n\treturn 0;\n\nret_release:\n\tcxusb_medion_put(dvbdev);\n\n\treturn ret;\n}",
        "static int padding_length(struct tls_prot_info *prot, struct sk_buff *skb)\n{\n\tstruct strp_msg *rxm = strp_msg(skb);\n\tstruct tls_msg *tlm = tls_msg(skb);\n\tint sub = 0;": "static int padding_length(struct tls_prot_info *prot, struct sk_buff *skb)\n{\n\tstruct strp_msg *rxm = strp_msg(skb);\n\tstruct tls_msg *tlm = tls_msg(skb);\n\tint sub = 0;\n\n\t/* Determine zero-padding length */\n\tif (prot->version == TLS_1_3_VERSION) {\n\t\tint offset = rxm->full_len - TLS_TAG_SIZE - 1;\n\t\tchar content_type = 0;\n\t\tint err;\n\n\t\twhile (content_type == 0) {\n\t\t\tif (offset < prot->prepend_size)\n\t\t\t\treturn -EBADMSG;\n\t\t\terr = skb_copy_bits(skb, rxm->offset + offset,\n\t\t\t\t\t    &content_type, 1);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\tif (content_type)\n\t\t\t\tbreak;\n\t\t\tsub++;\n\t\t\toffset--;\n\t\t}\n\t\ttlm->control = content_type;\n\t}\n\treturn sub;\n}",
        "static int gve_rx_alloc_ring_dqo(struct gve_priv *priv, int idx)\n{\n\tstruct gve_rx_ring *rx = &priv->rx[idx];\n\tstruct device *hdev = &priv->pdev->dev;\n\tsize_t size;": "static int gve_rx_alloc_ring_dqo(struct gve_priv *priv, int idx)\n{\n\tstruct gve_rx_ring *rx = &priv->rx[idx];\n\tstruct device *hdev = &priv->pdev->dev;\n\tsize_t size;\n\tint i;\n\n\tconst u32 buffer_queue_slots =\n\t\tpriv->options_dqo_rda.rx_buff_ring_entries;\n\tconst u32 completion_queue_slots = priv->rx_desc_cnt;\n\n\tnetif_dbg(priv, drv, priv->dev, \"allocating rx ring DQO\\n\");\n\n\tmemset(rx, 0, sizeof(*rx));\n\trx->gve = priv;\n\trx->q_num = idx;\n\trx->dqo.bufq.mask = buffer_queue_slots - 1;\n\trx->dqo.complq.num_free_slots = completion_queue_slots;\n\trx->dqo.complq.mask = completion_queue_slots - 1;\n\trx->ctx.skb_head = NULL;\n\trx->ctx.skb_tail = NULL;\n\n\trx->dqo.num_buf_states = min_t(s16, S16_MAX, buffer_queue_slots * 4);\n\trx->dqo.buf_states = kvcalloc(rx->dqo.num_buf_states,\n\t\t\t\t      sizeof(rx->dqo.buf_states[0]),\n\t\t\t\t      GFP_KERNEL);\n\tif (!rx->dqo.buf_states)\n\t\treturn -ENOMEM;\n\n\t/* Set up linked list of buffer IDs */\n\tfor (i = 0; i < rx->dqo.num_buf_states - 1; i++)\n\t\trx->dqo.buf_states[i].next = i + 1;\n\n\trx->dqo.buf_states[rx->dqo.num_buf_states - 1].next = -1;\n\trx->dqo.recycled_buf_states.head = -1;\n\trx->dqo.recycled_buf_states.tail = -1;\n\trx->dqo.used_buf_states.head = -1;\n\trx->dqo.used_buf_states.tail = -1;\n\n\t/* Allocate RX completion queue */\n\tsize = sizeof(rx->dqo.complq.desc_ring[0]) *\n\t\tcompletion_queue_slots;\n\trx->dqo.complq.desc_ring =\n\t\tdma_alloc_coherent(hdev, size, &rx->dqo.complq.bus, GFP_KERNEL);\n\tif (!rx->dqo.complq.desc_ring)\n\t\tgoto err;\n\n\t/* Allocate RX buffer queue */\n\tsize = sizeof(rx->dqo.bufq.desc_ring[0]) * buffer_queue_slots;\n\trx->dqo.bufq.desc_ring =\n\t\tdma_alloc_coherent(hdev, size, &rx->dqo.bufq.bus, GFP_KERNEL);\n\tif (!rx->dqo.bufq.desc_ring)\n\t\tgoto err;\n\n\trx->q_resources = dma_alloc_coherent(hdev, sizeof(*rx->q_resources),\n\t\t\t\t\t     &rx->q_resources_bus, GFP_KERNEL);\n\tif (!rx->q_resources)\n\t\tgoto err;\n\n\tgve_rx_add_to_block(priv, idx);\n\n\treturn 0;\n\nerr:\n\tgve_rx_free_ring_dqo(priv, idx);\n\treturn -ENOMEM;\n}",
        "static int scmi_base_protocol_init(const struct scmi_protocol_handle *ph)\n{\n\tint id, ret;\n\tu8 *prot_imp;\n\tu32 version;": "static int scmi_base_protocol_init(const struct scmi_protocol_handle *ph)\n{\n\tint id, ret;\n\tu8 *prot_imp;\n\tu32 version;\n\tchar name[SCMI_MAX_STR_SIZE];\n\tstruct device *dev = ph->dev;\n\tstruct scmi_revision_info *rev = scmi_revision_area_get(ph);\n\n\tret = ph->xops->version_get(ph, &version);\n\tif (ret)\n\t\treturn ret;\n\n\trev->major_ver = PROTOCOL_REV_MAJOR(version),\n\trev->minor_ver = PROTOCOL_REV_MINOR(version);\n\tph->set_priv(ph, rev);\n\n\tret = scmi_base_attributes_get(ph);\n\tif (ret)\n\t\treturn ret;\n\n\tprot_imp = devm_kcalloc(dev, rev->num_protocols, sizeof(u8),\n\t\t\t\tGFP_KERNEL);\n\tif (!prot_imp)\n\t\treturn -ENOMEM;\n\n\tscmi_base_vendor_id_get(ph, false);\n\tscmi_base_vendor_id_get(ph, true);\n\tscmi_base_implementation_version_get(ph);\n\tscmi_base_implementation_list_get(ph, prot_imp);\n\n\tscmi_setup_protocol_implemented(ph, prot_imp);\n\n\tdev_info(dev, \"SCMI Protocol v%d.%d '%s:%s' Firmware version 0x%x\\n\",\n\t\t rev->major_ver, rev->minor_ver, rev->vendor_id,\n\t\t rev->sub_vendor_id, rev->impl_ver);\n\tdev_dbg(dev, \"Found %d protocol(s) %d agent(s)\\n\", rev->num_protocols,\n\t\trev->num_agents);\n\n\tfor (id = 0; id < rev->num_agents; id++) {\n\t\tscmi_base_discover_agent_get(ph, id, name);\n\t\tdev_dbg(dev, \"Agent %d: %s\\n\", id, name);\n\t}\n\n\treturn 0;\n}",
        "static int venus_shutdown_no_tz(struct venus_core *core)\n{\n\tconst size_t mapped = core->fw.mapped_mem_size;\n\tstruct iommu_domain *iommu;\n\tsize_t unmapped;": "static int venus_shutdown_no_tz(struct venus_core *core)\n{\n\tconst size_t mapped = core->fw.mapped_mem_size;\n\tstruct iommu_domain *iommu;\n\tsize_t unmapped;\n\tu32 reg;\n\tstruct device *dev = core->fw.dev;\n\tvoid __iomem *wrapper_base = core->wrapper_base;\n\tvoid __iomem *wrapper_tz_base = core->wrapper_tz_base;\n\n\tif (IS_V6(core)) {\n\t\t/* Assert the reset to XTSS */\n\t\treg = readl_relaxed(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);\n\t\treg |= WRAPPER_XTSS_SW_RESET_BIT;\n\t\twritel_relaxed(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);\n\t} else {\n\t\t/* Assert the reset to ARM9 */\n\t\treg = readl_relaxed(wrapper_base + WRAPPER_A9SS_SW_RESET);\n\t\treg |= WRAPPER_A9SS_SW_RESET_BIT;\n\t\twritel_relaxed(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);\n\t}\n\t/* Make sure reset is asserted before the mapping is removed */\n\tmb();\n\n\tiommu = core->fw.iommu_domain;\n\n\tif (core->fw.mapped_mem_size && iommu) {\n\t\tunmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped);\n\n\t\tif (unmapped != mapped)\n\t\t\tdev_err(dev, \"failed to unmap firmware\\n\");\n\t\telse\n\t\t\tcore->fw.mapped_mem_size = 0;\n\t}\n\n\treturn 0;\n}",
        "static int cxl_mem_probe(struct device *dev)\n{\n\tstruct cxl_memdev *cxlmd = to_cxl_memdev(dev);\n\tstruct cxl_port *parent_port;\n\tint rc;": "static int cxl_mem_probe(struct device *dev)\n{\n\tstruct cxl_memdev *cxlmd = to_cxl_memdev(dev);\n\tstruct cxl_port *parent_port;\n\tint rc;\n\n\t/*\n\t * Someone is trying to reattach this device after it lost its port\n\t * connection (an endpoint port previously registered by this memdev was\n\t * disabled). This racy check is ok because if the port is still gone,\n\t * no harm done, and if the port hierarchy comes back it will re-trigger\n\t * this probe. Port rescan and memdev detach work share the same\n\t * single-threaded workqueue.\n\t */\n\tif (work_pending(&cxlmd->detach_work))\n\t\treturn -EBUSY;\n\n\trc = devm_cxl_enumerate_ports(cxlmd);\n\tif (rc)\n\t\treturn rc;\n\n\tparent_port = cxl_mem_find_port(cxlmd);\n\tif (!parent_port) {\n\t\tdev_err(dev, \"CXL port topology not found\\n\");\n\t\treturn -ENXIO;\n\t}\n\n\tdevice_lock(&parent_port->dev);\n\tif (!parent_port->dev.driver) {\n\t\tdev_err(dev, \"CXL port topology %s not enabled\\n\",\n\t\t\tdev_name(&parent_port->dev));\n\t\trc = -ENXIO;\n\t\tgoto unlock;\n\t}\n\n\trc = create_endpoint(cxlmd, parent_port);\nunlock:\n\tdevice_unlock(&parent_port->dev);\n\tput_device(&parent_port->dev);\n\tif (rc)\n\t\treturn rc;\n\n\t/*\n\t * The kernel may be operating out of CXL memory on this device,\n\t * there is no spec defined way to determine whether this device\n\t * preserves contents over suspend, and there is no simple way\n\t * to arrange for the suspend image to avoid CXL memory which\n\t * would setup a circular dependency between PCI resume and save\n\t * state restoration.\n\t *\n\t * TODO: support suspend when all the regions this device is\n\t * hosting are locked and covered by the system address map,\n\t * i.e. platform firmware owns restoring the HDM configuration\n\t * that it locked.\n\t */\n\tcxl_mem_active_inc();\n\treturn devm_add_action_or_reset(dev, enable_suspend, NULL);\n}",
        "static int test0_prpw_aligned_1byte(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0x1000) & ~(ADI_BLKSZ - 1);": "static int test0_prpw_aligned_1byte(int fd)\n{\n\t/* somewhat arbitrarily chosen address */\n\tunsigned long paddr =\n\t\t(end_addr[range_count - 1] - 0x1000) & ~(ADI_BLKSZ - 1);\n\tunsigned char version[1], expected_version;\n\tloff_t offset;\n\tint ret;\n\n\tversion[0] = random_version();\n\texpected_version = version[0];\n\n\toffset = paddr / ADI_BLKSZ;\n\n\tret = pwrite_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tret = pread_adi(fd, version, sizeof(version), offset);\n\tif (ret != sizeof(version))\n\t\tTEST_STEP_FAILURE(ret);\n\n\tif (expected_version != version[0]) {\n\t\tDEBUG_PRINT_L2(\"\\tExpected version %d but read version %d\\n\",\n\t\t\t       expected_version, version[0]);\n\t\tTEST_STEP_FAILURE(-expected_version);\n\t}\n\n\tret = 0;\nout:\n\tRETURN_FROM_TEST(ret);\n}",
        "static int apl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)\n{\n\tstruct apl_log_buffer_layout layout;\n\tvoid __iomem *addr, *buf;\n\tsize_t dump_size;": "static int apl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)\n{\n\tstruct apl_log_buffer_layout layout;\n\tvoid __iomem *addr, *buf;\n\tsize_t dump_size;\n\tu16 offset = 0;\n\tu8 *dump, *pos;\n\n\tdump_size = AVS_FW_REGS_SIZE + msg->ext.coredump.stack_dump_size;\n\tdump = vzalloc(dump_size);\n\tif (!dump)\n\t\treturn -ENOMEM;\n\n\tmemcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);\n\n\tif (!msg->ext.coredump.stack_dump_size)\n\t\tgoto exit;\n\n\t/* Dump the registers even if an external error prevents gathering the stack. */\n\taddr = avs_log_buffer_addr(adev, msg->ext.coredump.core_id);\n\tif (!addr)\n\t\tgoto exit;\n\n\tbuf = apl_log_payload_addr(addr);\n\tmemcpy_fromio(&layout, addr, sizeof(layout));\n\tif (!apl_is_entry_stackdump(buf + layout.read_ptr)) {\n\t\t/*\n\t\t * DSP awaits the remaining logs to be\n\t\t * gathered before dumping stack\n\t\t */\n\t\tmsg->log.core = msg->ext.coredump.core_id;\n\t\tavs_dsp_op(adev, log_buffer_status, msg);\n\t}\n\n\tpos = dump + AVS_FW_REGS_SIZE;\n\t/* gather the stack */\n\tdo {\n\t\tu32 count;\n\n\t\tif (apl_wait_log_entry(adev, msg->ext.coredump.core_id, &layout))\n\t\t\tbreak;\n\n\t\tif (layout.read_ptr > layout.write_ptr) {\n\t\t\tcount = apl_log_payload_size(adev) - layout.read_ptr;\n\t\t\tmemcpy_fromio(pos + offset, buf + layout.read_ptr, count);\n\t\t\tlayout.read_ptr = 0;\n\t\t\toffset += count;\n\t\t}\n\t\tcount = layout.write_ptr - layout.read_ptr;\n\t\tmemcpy_fromio(pos + offset, buf + layout.read_ptr, count);\n\t\toffset += count;\n\n\t\t/* update read pointer */\n\t\twritel(layout.write_ptr, addr);\n\t} while (offset < msg->ext.coredump.stack_dump_size);\n\nexit:\n\tdev_coredumpv(adev->dev, dump, dump_size, GFP_KERNEL);\n\n\treturn 0;\n}",
        "static int __check_active_hdr_in(struct bpf_sock_ops *skops, bool check_syn)\n{\n\tunion {\n\t\tstruct tcphdr th;\n\t\tstruct ipv6hdr ip6;": "static int __check_active_hdr_in(struct bpf_sock_ops *skops, bool check_syn)\n{\n\tunion {\n\t\tstruct tcphdr th;\n\t\tstruct ipv6hdr ip6;\n\t\tstruct tcp_exprm_opt exprm_opt;\n\t\tstruct tcp_opt reg_opt;\n\t\t__u8 data[100]; /* IPv6 (40) + Max TCP hdr (60) */\n\t} hdr = {};\n\t__u64 load_flags = check_syn ? BPF_LOAD_HDR_OPT_TCP_SYN : 0;\n\tstruct tcphdr *pth;\n\tint ret;\n\n\thdr.reg_opt.kind = 0xB9;\n\n\t/* The option is 4 bytes long instead of 2 bytes */\n\tret = bpf_load_hdr_opt(skops, &hdr.reg_opt, 2, load_flags);\n\tif (ret != -ENOSPC)\n\t\tRET_CG_ERR(ret);\n\n\t/* Test searching magic with regular kind */\n\thdr.reg_opt.len = 4;\n\tret = bpf_load_hdr_opt(skops, &hdr.reg_opt, sizeof(hdr.reg_opt),\n\t\t\t       load_flags);\n\tif (ret != -EINVAL)\n\t\tRET_CG_ERR(ret);\n\n\thdr.reg_opt.len = 0;\n\tret = bpf_load_hdr_opt(skops, &hdr.reg_opt, sizeof(hdr.reg_opt),\n\t\t\t       load_flags);\n\tif (ret != 4 || hdr.reg_opt.len != 4 || hdr.reg_opt.kind != 0xB9 ||\n\t    hdr.reg_opt.data[0] != 0xfa || hdr.reg_opt.data[1] != 0xce)\n\t\tRET_CG_ERR(ret);\n\n\t/* Test searching experimental option with invalid kind length */\n\thdr.exprm_opt.kind = TCPOPT_EXP;\n\thdr.exprm_opt.len = 5;\n\thdr.exprm_opt.magic = 0;\n\tret = bpf_load_hdr_opt(skops, &hdr.exprm_opt, sizeof(hdr.exprm_opt),\n\t\t\t       load_flags);\n\tif (ret != -EINVAL)\n\t\tRET_CG_ERR(ret);\n\n\t/* Test searching experimental option with 0 magic value */\n\thdr.exprm_opt.len = 4;\n\tret = bpf_load_hdr_opt(skops, &hdr.exprm_opt, sizeof(hdr.exprm_opt),\n\t\t\t       load_flags);\n\tif (ret != -ENOMSG)\n\t\tRET_CG_ERR(ret);\n\n\thdr.exprm_opt.magic = __bpf_htons(0xeB9F);\n\tret = bpf_load_hdr_opt(skops, &hdr.exprm_opt, sizeof(hdr.exprm_opt),\n\t\t\t       load_flags);\n\tif (ret != 4 || hdr.exprm_opt.len != 4 ||\n\t    hdr.exprm_opt.kind != TCPOPT_EXP ||\n\t    hdr.exprm_opt.magic != __bpf_htons(0xeB9F))\n\t\tRET_CG_ERR(ret);\n\n\tif (!check_syn)\n\t\treturn CG_OK;\n\n\t/* Test loading from skops->syn_skb if sk_state == TCP_NEW_SYN_RECV\n\t *\n\t * Test loading from tp->saved_syn for other sk_state.\n\t */\n\tret = bpf_getsockopt(skops, SOL_TCP, TCP_BPF_SYN_IP, &hdr.ip6,\n\t\t\t     sizeof(hdr.ip6));\n\tif (ret != -ENOSPC)\n\t\tRET_CG_ERR(ret);\n\n\tif (hdr.ip6.saddr.s6_addr16[7] != last_addr16_n ||\n\t    hdr.ip6.daddr.s6_addr16[7] != last_addr16_n)\n\t\tRET_CG_ERR(0);\n\n\tret = bpf_getsockopt(skops, SOL_TCP, TCP_BPF_SYN_IP, &hdr, sizeof(hdr));\n\tif (ret < 0)\n\t\tRET_CG_ERR(ret);\n\n\tpth = (struct tcphdr *)(&hdr.ip6 + 1);\n\tif (pth->dest != passive_lport_n || pth->source != active_lport_n)\n\t\tRET_CG_ERR(0);\n\n\tret = bpf_getsockopt(skops, SOL_TCP, TCP_BPF_SYN, &hdr, sizeof(hdr));\n\tif (ret < 0)\n\t\tRET_CG_ERR(ret);\n\n\tif (hdr.th.dest != passive_lport_n || hdr.th.source != active_lport_n)\n\t\tRET_CG_ERR(0);\n\n\treturn CG_OK;\n}",
        "static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)\n{\n\tsport->port.dev = &dev->dev;\n\tsport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE);\n": "static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)\n{\n\tsport->port.dev = &dev->dev;\n\tsport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE);\n\n\t// mctrl_gpio_init() requires that the GPIO driver supports interrupts,\n\t// but we need to support GPIO drivers for hardware that has no such\n\t// interrupts.  Use mctrl_gpio_init_noauto() instead.\n\tsport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);\n\tif (IS_ERR(sport->gpios)) {\n\t\tint err = PTR_ERR(sport->gpios);\n\n\t\tdev_err(sport->port.dev, \"failed to get mctrl gpios: %d\\n\",\n\t\t\terr);\n\n\t\tif (err == -EPROBE_DEFER)\n\t\t\treturn err;\n\n\t\tsport->gpios = NULL;\n\t}\n\n\tplatform_set_drvdata(dev, sport);\n\n\treturn uart_add_one_port(&sa1100_reg, &sport->port);\n}",
        "static int qlge_wol(struct qlge_adapter *qdev)\n{\n\tint status = 0;\n\tu32 wol = MB_WOL_DISABLE;\n": "static int qlge_wol(struct qlge_adapter *qdev)\n{\n\tint status = 0;\n\tu32 wol = MB_WOL_DISABLE;\n\n\t/* The CAM is still intact after a reset, but if we\n\t * are doing WOL, then we may need to program the\n\t * routing regs. We would also need to issue the mailbox\n\t * commands to instruct the MPI what to do per the ethtool\n\t * settings.\n\t */\n\n\tif (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |\n\t\t\t WAKE_MCAST | WAKE_BCAST)) {\n\t\tnetif_err(qdev, ifdown, qdev->ndev,\n\t\t\t  \"Unsupported WOL parameter. qdev->wol = 0x%x.\\n\",\n\t\t\t  qdev->wol);\n\t\treturn -EINVAL;\n\t}\n\n\tif (qdev->wol & WAKE_MAGIC) {\n\t\tstatus = qlge_mb_wol_set_magic(qdev, 1);\n\t\tif (status) {\n\t\t\tnetif_err(qdev, ifdown, qdev->ndev,\n\t\t\t\t  \"Failed to set magic packet on %s.\\n\",\n\t\t\t\t  qdev->ndev->name);\n\t\t\treturn status;\n\t\t}\n\t\tnetif_info(qdev, drv, qdev->ndev,\n\t\t\t   \"Enabled magic packet successfully on %s.\\n\",\n\t\t\t   qdev->ndev->name);\n\n\t\twol |= MB_WOL_MAGIC_PKT;\n\t}\n\n\tif (qdev->wol) {\n\t\twol |= MB_WOL_MODE_ON;\n\t\tstatus = qlge_mb_wol_mode(qdev, wol);\n\t\tnetif_err(qdev, drv, qdev->ndev,\n\t\t\t  \"WOL %s (wol code 0x%x) on %s\\n\",\n\t\t\t  (status == 0) ? \"Successfully set\" : \"Failed\",\n\t\t\t  wol, qdev->ndev->name);\n\t}\n\n\treturn status;\n}",
        "static int stfsm_w25q_config(struct stfsm *fsm)\n{\n\tuint32_t data_pads;\n\tuint8_t sr1, sr2;\n\tuint16_t sr_wr;": "static int stfsm_w25q_config(struct stfsm *fsm)\n{\n\tuint32_t data_pads;\n\tuint8_t sr1, sr2;\n\tuint16_t sr_wr;\n\tint update_sr = 0;\n\tint ret;\n\n\tret = stfsm_prepare_rwe_seqs_default(fsm);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Check status of 'QE' bit, update if required. */\n\tstfsm_read_status(fsm, SPINOR_OP_RDCR, &sr2, 1);\n\tdata_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;\n\tif (data_pads == 4) {\n\t\tif (!(sr2 & W25Q_STATUS_QE)) {\n\t\t\t/* Set 'QE' */\n\t\t\tsr2 |= W25Q_STATUS_QE;\n\t\t\tupdate_sr = 1;\n\t\t}\n\t} else {\n\t\tif (sr2 & W25Q_STATUS_QE) {\n\t\t\t/* Clear 'QE' */\n\t\t\tsr2 &= ~W25Q_STATUS_QE;\n\t\t\tupdate_sr = 1;\n\t\t}\n\t}\n\tif (update_sr) {\n\t\t/* Write status register */\n\t\tstfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);\n\t\tsr_wr = ((uint16_t)sr2 << 8) | sr1;\n\t\tstfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1);\n\t}\n\n\treturn 0;\n}",
        "static void rkvdec_init_v4l2_vp9_count_tbl(struct rkvdec_ctx *ctx)\n{\n\tstruct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;\n\tstruct rkvdec_vp9_intra_frame_symbol_counts *intra_cnts = vp9_ctx->count_tbl.cpu;\n\tstruct rkvdec_vp9_inter_frame_symbol_counts *inter_cnts = vp9_ctx->count_tbl.cpu;": "static void rkvdec_init_v4l2_vp9_count_tbl(struct rkvdec_ctx *ctx)\n{\n\tstruct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;\n\tstruct rkvdec_vp9_intra_frame_symbol_counts *intra_cnts = vp9_ctx->count_tbl.cpu;\n\tstruct rkvdec_vp9_inter_frame_symbol_counts *inter_cnts = vp9_ctx->count_tbl.cpu;\n\tint i, j, k, l, m;\n\n\tvp9_ctx->inter_cnts.partition = &inter_cnts->partition;\n\tvp9_ctx->inter_cnts.skip = &inter_cnts->skip;\n\tvp9_ctx->inter_cnts.intra_inter = &inter_cnts->inter;\n\tvp9_ctx->inter_cnts.tx32p = &inter_cnts->tx32p;\n\tvp9_ctx->inter_cnts.tx16p = &inter_cnts->tx16p;\n\tvp9_ctx->inter_cnts.tx8p = &inter_cnts->tx8p;\n\n\tvp9_ctx->intra_cnts.partition = (u32 (*)[16][4])(&intra_cnts->partition);\n\tvp9_ctx->intra_cnts.skip = &intra_cnts->skip;\n\tvp9_ctx->intra_cnts.intra_inter = &intra_cnts->intra;\n\tvp9_ctx->intra_cnts.tx32p = &intra_cnts->tx32p;\n\tvp9_ctx->intra_cnts.tx16p = &intra_cnts->tx16p;\n\tvp9_ctx->intra_cnts.tx8p = &intra_cnts->tx8p;\n\n\tvp9_ctx->inter_cnts.y_mode = &inter_cnts->y_mode;\n\tvp9_ctx->inter_cnts.uv_mode = &inter_cnts->uv_mode;\n\tvp9_ctx->inter_cnts.comp = &inter_cnts->comp;\n\tvp9_ctx->inter_cnts.comp_ref = &inter_cnts->comp_ref;\n\tvp9_ctx->inter_cnts.single_ref = &inter_cnts->single_ref;\n\tvp9_ctx->inter_cnts.mv_mode = &inter_cnts->mv_mode;\n\tvp9_ctx->inter_cnts.filter = &inter_cnts->filter;\n\tvp9_ctx->inter_cnts.mv_joint = &inter_cnts->mv_joint;\n\tvp9_ctx->inter_cnts.sign = &inter_cnts->sign;\n\t/*\n\t * rk hardware actually uses \"u32 classes[2][11 + 1];\"\n\t * instead of \"u32 classes[2][11];\", so this must be explicitly\n\t * copied into vp9_ctx->classes when passing the data to the\n\t * vp9 library function\n\t */\n\tvp9_ctx->inter_cnts.class0 = &inter_cnts->class0;\n\tvp9_ctx->inter_cnts.bits = &inter_cnts->bits;\n\tvp9_ctx->inter_cnts.class0_fp = &inter_cnts->class0_fp;\n\tvp9_ctx->inter_cnts.fp = &inter_cnts->fp;\n\tvp9_ctx->inter_cnts.class0_hp = &inter_cnts->class0_hp;\n\tvp9_ctx->inter_cnts.hp = &inter_cnts->hp;\n\n#define INNERMOST_LOOP \\\n\tdo {\t\t\t\t\t\t\t\t\t\t\\\n\t\tfor (m = 0; m < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0][0][0]); ++m) {\\\n\t\t\tvp9_ctx->inter_cnts.coeff[i][j][k][l][m] =\t\t\t\\\n\t\t\t\t&inter_cnts->ref_cnt[k][i][j][l][m].coeff;\t\t\\\n\t\t\tvp9_ctx->inter_cnts.eob[i][j][k][l][m][0] =\t\t\t\\\n\t\t\t\t&inter_cnts->ref_cnt[k][i][j][l][m].eob[0];\t\t\\\n\t\t\tvp9_ctx->inter_cnts.eob[i][j][k][l][m][1] =\t\t\t\\\n\t\t\t\t&inter_cnts->ref_cnt[k][i][j][l][m].eob[1];\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvp9_ctx->intra_cnts.coeff[i][j][k][l][m] =\t\t\t\\\n\t\t\t\t&intra_cnts->ref_cnt[k][i][j][l][m].coeff;\t\t\\\n\t\t\tvp9_ctx->intra_cnts.eob[i][j][k][l][m][0] =\t\t\t\\\n\t\t\t\t&intra_cnts->ref_cnt[k][i][j][l][m].eob[0];\t\t\\\n\t\t\tvp9_ctx->intra_cnts.eob[i][j][k][l][m][1] =\t\t\t\\\n\t\t\t\t&intra_cnts->ref_cnt[k][i][j][l][m].eob[1];\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\\\n\t} while (0)\n\n\tfor (i = 0; i < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff); ++i)\n\t\tfor (j = 0; j < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0]); ++j)\n\t\t\tfor (k = 0; k < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0]); ++k)\n\t\t\t\tfor (l = 0; l < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0][0]); ++l)\n\t\t\t\t\tINNERMOST_LOOP;\n#undef INNERMOST_LOOP\n}",
        "static int MoxaPortReadData(struct moxa_port *port)\n{\n\tstruct tty_struct *tty = port->port.tty;\n\tunsigned char *dst;\n\tvoid __iomem *baseAddr, *ofsAddr, *ofs;": "static int MoxaPortReadData(struct moxa_port *port)\n{\n\tstruct tty_struct *tty = port->port.tty;\n\tunsigned char *dst;\n\tvoid __iomem *baseAddr, *ofsAddr, *ofs;\n\tunsigned int count, len, total;\n\tu16 tail, rx_mask, spage, epage;\n\tu16 pageno, pageofs, bufhead, head;\n\n\tofsAddr = port->tableAddr;\n\tbaseAddr = port->board->basemem;\n\thead = readw(ofsAddr + RXrptr);\n\ttail = readw(ofsAddr + RXwptr);\n\trx_mask = readw(ofsAddr + RX_mask);\n\tspage = readw(ofsAddr + Page_rxb);\n\tepage = readw(ofsAddr + EndPage_rxb);\n\tcount = (tail >= head) ? (tail - head) : (tail - head + rx_mask + 1);\n\tif (count == 0)\n\t\treturn 0;\n\n\ttotal = count;\n\tmoxaLog.rxcnt[tty->index] += total;\n\tif (spage == epage) {\n\t\tbufhead = readw(ofsAddr + Ofs_rxb);\n\t\twritew(spage, baseAddr + Control_reg);\n\t\twhile (count > 0) {\n\t\t\tofs = baseAddr + DynPage_addr + bufhead + head;\n\t\t\tlen = (tail >= head) ? (tail - head) :\n\t\t\t\t\t(rx_mask + 1 - head);\n\t\t\tlen = tty_prepare_flip_string(&port->port, &dst,\n\t\t\t\t\tmin(len, count));\n\t\t\tmemcpy_fromio(dst, ofs, len);\n\t\t\thead = (head + len) & rx_mask;\n\t\t\tcount -= len;\n\t\t}\n\t} else {\n\t\tpageno = spage + (head >> 13);\n\t\tpageofs = head & Page_mask;\n\t\twhile (count > 0) {\n\t\t\twritew(pageno, baseAddr + Control_reg);\n\t\t\tofs = baseAddr + DynPage_addr + pageofs;\n\t\t\tlen = tty_prepare_flip_string(&port->port, &dst,\n\t\t\t\t\tmin(Page_size - pageofs, count));\n\t\t\tmemcpy_fromio(dst, ofs, len);\n\n\t\t\tcount -= len;\n\t\t\tpageofs = (pageofs + len) & Page_mask;\n\t\t\tif (pageofs == 0 && ++pageno == epage)\n\t\t\t\tpageno = spage;\n\t\t}\n\t\thead = (head + total) & rx_mask;\n\t}\n\twritew(head, ofsAddr + RXrptr);\n\tif (readb(ofsAddr + FlagStat) & Xoff_state) {\n\t\tmoxaLowWaterChk = 1;\n\t\tport->lowChkFlag = 1;\n\t}\n\treturn total;\n}",
        "static int pciefd_can_probe(struct pciefd_board *pciefd)\n{\n\tstruct net_device *ndev;\n\tstruct pciefd_can *priv;\n\tu32 clk;": "static int pciefd_can_probe(struct pciefd_board *pciefd)\n{\n\tstruct net_device *ndev;\n\tstruct pciefd_can *priv;\n\tu32 clk;\n\tint err;\n\n\t/* allocate the candev object with default isize of echo skbs ring */\n\tndev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count,\n\t\t\t\t    PCIEFD_ECHO_SKB_MAX);\n\tif (!ndev) {\n\t\tdev_err(&pciefd->pci_dev->dev,\n\t\t\t\"failed to alloc candev object\\n\");\n\t\tgoto failure;\n\t}\n\n\tpriv = netdev_priv(ndev);\n\n\t/* fill-in candev private object: */\n\n\t/* setup PCIe-FD own callbacks */\n\tpriv->ucan.pre_cmd = pciefd_pre_cmd;\n\tpriv->ucan.write_cmd = pciefd_write_cmd;\n\tpriv->ucan.post_cmd = pciefd_post_cmd;\n\tpriv->ucan.enable_tx_path = pciefd_enable_tx_path;\n\tpriv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg;\n\tpriv->ucan.write_tx_msg = pciefd_write_tx_msg;\n\n\t/* setup PCIe-FD own command buffer */\n\tpriv->ucan.cmd_buffer = &priv->pucan_cmd;\n\tpriv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd);\n\n\tpriv->board = pciefd;\n\n\t/* CAN config regs block address */\n\tpriv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index);\n\n\t/* allocate non-cacheable DMA'able 4KB memory area for Rx */\n\tpriv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,\n\t\t\t\t\t\t PCIEFD_RX_DMA_SIZE,\n\t\t\t\t\t\t &priv->rx_dma_laddr,\n\t\t\t\t\t\t GFP_KERNEL);\n\tif (!priv->rx_dma_vaddr) {\n\t\tdev_err(&pciefd->pci_dev->dev,\n\t\t\t\"Rx dmam_alloc_coherent(%u) failure\\n\",\n\t\t\tPCIEFD_RX_DMA_SIZE);\n\t\tgoto err_free_candev;\n\t}\n\n\t/* allocate non-cacheable DMA'able 4KB memory area for Tx */\n\tpriv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,\n\t\t\t\t\t\t PCIEFD_TX_DMA_SIZE,\n\t\t\t\t\t\t &priv->tx_dma_laddr,\n\t\t\t\t\t\t GFP_KERNEL);\n\tif (!priv->tx_dma_vaddr) {\n\t\tdev_err(&pciefd->pci_dev->dev,\n\t\t\t\"Tx dmam_alloc_coherent(%u) failure\\n\",\n\t\t\tPCIEFD_TX_DMA_SIZE);\n\t\tgoto err_free_candev;\n\t}\n\n\t/* CAN clock in RST mode */\n\tpciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC);\n\n\t/* read current clock value */\n\tclk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL);\n\tswitch (clk) {\n\tcase CANFD_CLK_SEL_20MHZ:\n\t\tpriv->ucan.can.clock.freq = 20 * 1000 * 1000;\n\t\tbreak;\n\tcase CANFD_CLK_SEL_24MHZ:\n\t\tpriv->ucan.can.clock.freq = 24 * 1000 * 1000;\n\t\tbreak;\n\tcase CANFD_CLK_SEL_30MHZ:\n\t\tpriv->ucan.can.clock.freq = 30 * 1000 * 1000;\n\t\tbreak;\n\tcase CANFD_CLK_SEL_40MHZ:\n\t\tpriv->ucan.can.clock.freq = 40 * 1000 * 1000;\n\t\tbreak;\n\tcase CANFD_CLK_SEL_60MHZ:\n\t\tpriv->ucan.can.clock.freq = 60 * 1000 * 1000;\n\t\tbreak;\n\tdefault:\n\t\tpciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ,\n\t\t\t\t    PCIEFD_REG_CAN_CLK_SEL);\n\n\t\tfallthrough;\n\tcase CANFD_CLK_SEL_80MHZ:\n\t\tpriv->ucan.can.clock.freq = 80 * 1000 * 1000;\n\t\tbreak;\n\t}\n\n\tndev->irq = pciefd->pci_dev->irq;\n\n\tSET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev);\n\n\terr = register_candev(ndev);\n\tif (err) {\n\t\tdev_err(&pciefd->pci_dev->dev,\n\t\t\t\"couldn't register CAN device: %d\\n\", err);\n\t\tgoto err_free_candev;\n\t}\n\n\tspin_lock_init(&priv->tx_lock);\n\n\t/* save the object address in the board structure */\n\tpciefd->can[pciefd->can_count] = priv;\n\n\tdev_info(&pciefd->pci_dev->dev, \"%s at reg_base=0x%p irq=%d\\n\",\n\t\t ndev->name, priv->reg_base, ndev->irq);\n\n\treturn 0;\n\nerr_free_candev:\n\tfree_candev(ndev);\n\nfailure:\n\treturn -ENOMEM;\n}",
        "static int io_issue_sqe(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\tconst struct cred *creds = NULL;\n\tint ret;": "static int io_issue_sqe(struct io_kiocb *req, unsigned int issue_flags)\n{\n\tconst struct io_op_def *def = &io_op_defs[req->opcode];\n\tconst struct cred *creds = NULL;\n\tint ret;\n\n\tif (unlikely(!io_assign_file(req, issue_flags)))\n\t\treturn -EBADF;\n\n\tif (unlikely((req->flags & REQ_F_CREDS) && req->creds != current_cred()))\n\t\tcreds = override_creds(req->creds);\n\n\tif (!def->audit_skip)\n\t\taudit_uring_entry(req->opcode);\n\n\tswitch (req->opcode) {\n\tcase IORING_OP_NOP:\n\t\tret = io_nop(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_READV:\n\tcase IORING_OP_READ_FIXED:\n\tcase IORING_OP_READ:\n\t\tret = io_read(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_WRITEV:\n\tcase IORING_OP_WRITE_FIXED:\n\tcase IORING_OP_WRITE:\n\t\tret = io_write(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_FSYNC:\n\t\tret = io_fsync(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_POLL_ADD:\n\t\tret = io_poll_add(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_POLL_REMOVE:\n\t\tret = io_poll_remove(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SYNC_FILE_RANGE:\n\t\tret = io_sync_file_range(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SENDMSG:\n\t\tret = io_sendmsg(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SEND:\n\t\tret = io_send(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_RECVMSG:\n\t\tret = io_recvmsg(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_RECV:\n\t\tret = io_recv(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_TIMEOUT:\n\t\tret = io_timeout(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_TIMEOUT_REMOVE:\n\t\tret = io_timeout_remove(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_ACCEPT:\n\t\tret = io_accept(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_CONNECT:\n\t\tret = io_connect(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_ASYNC_CANCEL:\n\t\tret = io_async_cancel(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_FALLOCATE:\n\t\tret = io_fallocate(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_OPENAT:\n\t\tret = io_openat(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_CLOSE:\n\t\tret = io_close(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_FILES_UPDATE:\n\t\tret = io_files_update(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_STATX:\n\t\tret = io_statx(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_FADVISE:\n\t\tret = io_fadvise(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_MADVISE:\n\t\tret = io_madvise(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_OPENAT2:\n\t\tret = io_openat2(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_EPOLL_CTL:\n\t\tret = io_epoll_ctl(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SPLICE:\n\t\tret = io_splice(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_PROVIDE_BUFFERS:\n\t\tret = io_provide_buffers(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_REMOVE_BUFFERS:\n\t\tret = io_remove_buffers(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_TEE:\n\t\tret = io_tee(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SHUTDOWN:\n\t\tret = io_shutdown(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_RENAMEAT:\n\t\tret = io_renameat(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_UNLINKAT:\n\t\tret = io_unlinkat(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_MKDIRAT:\n\t\tret = io_mkdirat(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SYMLINKAT:\n\t\tret = io_symlinkat(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_LINKAT:\n\t\tret = io_linkat(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_MSG_RING:\n\t\tret = io_msg_ring(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_FSETXATTR:\n\t\tret = io_fsetxattr(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SETXATTR:\n\t\tret = io_setxattr(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_FGETXATTR:\n\t\tret = io_fgetxattr(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_GETXATTR:\n\t\tret = io_getxattr(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_SOCKET:\n\t\tret = io_socket(req, issue_flags);\n\t\tbreak;\n\tcase IORING_OP_URING_CMD:\n\t\tret = io_uring_cmd(req, issue_flags);\n\t\tbreak;\n\tdefault:\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\tif (!def->audit_skip)\n\t\taudit_uring_exit(!ret, ret);\n\n\tif (creds)\n\t\trevert_creds(creds);\n\tif (ret)\n\t\treturn ret;\n\t/* If the op doesn't have a file, we're not polling for it */\n\tif ((req->ctx->flags & IORING_SETUP_IOPOLL) && req->file)\n\t\tio_iopoll_req_issued(req, issue_flags);\n\n\treturn 0;\n}",
        "static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)\n{\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tunsigned int link_id = sdw->instance;\n\tint ret = 0;": "static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)\n{\n\tvoid __iomem *shim = sdw->link_res->shim;\n\tunsigned int link_id = sdw->instance;\n\tint ret = 0;\n\tu16 ioctl = 0, act = 0;\n\n\tmutex_lock(sdw->link_res->shim_lock);\n\n\t/* Initialize Shim */\n\tioctl |= SDW_SHIM_IOCTL_BKE;\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tioctl |= SDW_SHIM_IOCTL_WPDD;\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tioctl |= SDW_SHIM_IOCTL_DO;\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tioctl |= SDW_SHIM_IOCTL_DOE;\n\tintel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);\n\tusleep_range(10, 15);\n\n\tintel_shim_glue_to_master_ip(sdw);\n\n\tu16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);\n\tact |= SDW_SHIM_CTMCTL_DACTQE;\n\tact |= SDW_SHIM_CTMCTL_DODS;\n\tintel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);\n\tusleep_range(10, 15);\n\n\tmutex_unlock(sdw->link_res->shim_lock);\n\n\treturn ret;\n}",
        "static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)\n{\n\tstruct r820t_sect_type compare_iq[3];\n\tint rc;\n\tu8 x_direction = 0;  /* 1:x, 0:y */": "static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)\n{\n\tstruct r820t_sect_type compare_iq[3];\n\tint rc;\n\tu8 x_direction = 0;  /* 1:x, 0:y */\n\tu8 dir_reg, other_reg;\n\n\tr820t_vga_adjust(priv);\n\n\trc = r820t_imr_cross(priv, compare_iq, &x_direction);\n\tif (rc < 0)\n\t\treturn rc;\n\n\tif (x_direction == 1) {\n\t\tdir_reg   = 0x08;\n\t\tother_reg = 0x09;\n\t} else {\n\t\tdir_reg   = 0x09;\n\t\tother_reg = 0x08;\n\t}\n\n\t/* compare and find min of 3 points. determine i/q direction */\n\tr820t_compre_cor(compare_iq);\n\n\t/* increase step to find min value of this direction */\n\trc = r820t_compre_step(priv, compare_iq, dir_reg);\n\tif (rc < 0)\n\t\treturn rc;\n\n\t/* the other direction */\n\trc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,\n\t\t\t\tcompare_iq[0].phase_y, dir_reg);\n\tif (rc < 0)\n\t\treturn rc;\n\n\t/* compare and find min of 3 points. determine i/q direction */\n\tr820t_compre_cor(compare_iq);\n\n\t/* increase step to find min value on this direction */\n\trc = r820t_compre_step(priv, compare_iq, other_reg);\n\tif (rc < 0)\n\t\treturn rc;\n\n\t/* check 3 points again */\n\trc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,\n\t\t\t\tcompare_iq[0].phase_y, other_reg);\n\tif (rc < 0)\n\t\treturn rc;\n\n\tr820t_compre_cor(compare_iq);\n\n\t/* section-9 check */\n\trc = r820t_section(priv, compare_iq);\n\n\t*iq_pont = compare_iq[0];\n\n\t/* reset gain/phase control setting */\n\trc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);\n\tif (rc < 0)\n\t\treturn rc;\n\n\trc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);\n\n\treturn rc;\n}",
        "static int isotp_rcv_ff(struct sock *sk, struct canfd_frame *cf, int ae)\n{\n\tstruct isotp_sock *so = isotp_sk(sk);\n\tint i;\n\tint off;": "static int isotp_rcv_ff(struct sock *sk, struct canfd_frame *cf, int ae)\n{\n\tstruct isotp_sock *so = isotp_sk(sk);\n\tint i;\n\tint off;\n\tint ff_pci_sz;\n\n\thrtimer_cancel(&so->rxtimer);\n\tso->rx.state = ISOTP_IDLE;\n\n\t/* get the used sender LL_DL from the (first) CAN frame data length */\n\tso->rx.ll_dl = padlen(cf->len);\n\n\t/* the first frame has to use the entire frame up to LL_DL length */\n\tif (cf->len != so->rx.ll_dl)\n\t\treturn 1;\n\n\t/* get the FF_DL */\n\tso->rx.len = (cf->data[ae] & 0x0F) << 8;\n\tso->rx.len += cf->data[ae + 1];\n\n\t/* Check for FF_DL escape sequence supporting 32 bit PDU length */\n\tif (so->rx.len) {\n\t\tff_pci_sz = FF_PCI_SZ12;\n\t} else {\n\t\t/* FF_DL = 0 => get real length from next 4 bytes */\n\t\tso->rx.len = cf->data[ae + 2] << 24;\n\t\tso->rx.len += cf->data[ae + 3] << 16;\n\t\tso->rx.len += cf->data[ae + 4] << 8;\n\t\tso->rx.len += cf->data[ae + 5];\n\t\tff_pci_sz = FF_PCI_SZ32;\n\t}\n\n\t/* take care of a potential SF_DL ESC offset for TX_DL > 8 */\n\toff = (so->rx.ll_dl > CAN_MAX_DLEN) ? 1 : 0;\n\n\tif (so->rx.len + ae + off + ff_pci_sz < so->rx.ll_dl)\n\t\treturn 1;\n\n\tif (so->rx.len > MAX_MSG_LENGTH) {\n\t\t/* send FC frame with overflow status */\n\t\tisotp_send_fc(sk, ae, ISOTP_FC_OVFLW);\n\t\treturn 1;\n\t}\n\n\t/* copy the first received data bytes */\n\tso->rx.idx = 0;\n\tfor (i = ae + ff_pci_sz; i < so->rx.ll_dl; i++)\n\t\tso->rx.buf[so->rx.idx++] = cf->data[i];\n\n\t/* initial setup for this pdu reception */\n\tso->rx.sn = 1;\n\tso->rx.state = ISOTP_WAIT_DATA;\n\n\t/* no creation of flow control frames */\n\tif (so->opt.flags & CAN_ISOTP_LISTEN_MODE)\n\t\treturn 0;\n\n\t/* send our first FC frame */\n\tisotp_send_fc(sk, ae, ISOTP_FC_CTS);\n\treturn 0;\n}",
        "static int __maybe_unused intel_resume_runtime(struct device *dev)\n{\n\tstruct sdw_cdns *cdns = dev_get_drvdata(dev);\n\tstruct sdw_intel *sdw = cdns_to_intel(cdns);\n\tstruct sdw_bus *bus = &cdns->bus;": "static int __maybe_unused intel_resume_runtime(struct device *dev)\n{\n\tstruct sdw_cdns *cdns = dev_get_drvdata(dev);\n\tstruct sdw_intel *sdw = cdns_to_intel(cdns);\n\tstruct sdw_bus *bus = &cdns->bus;\n\tu32 clock_stop_quirks;\n\tbool clock_stop0;\n\tint link_flags;\n\tbool multi_link;\n\tint status;\n\tint ret;\n\n\tif (bus->prop.hw_disabled || !sdw->startup_done) {\n\t\tdev_dbg(dev, \"SoundWire master %d is disabled or not-started, ignoring\\n\",\n\t\t\tbus->link_id);\n\t\treturn 0;\n\t}\n\n\t/* unconditionally disable WAKEEN interrupt */\n\tintel_shim_wake(sdw, false);\n\n\tlink_flags = md_flags >> (bus->link_id * 8);\n\tmulti_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);\n\n\tclock_stop_quirks = sdw->link_res->clock_stop_quirks;\n\n\tif (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {\n\t\tret = intel_init(sdw);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"%s failed: %d\\n\", __func__, ret);\n\t\t\treturn ret;\n\t\t}\n\n\t\t/*\n\t\t * make sure all Slaves are tagged as UNATTACHED and provide\n\t\t * reason for reinitialization\n\t\t */\n\t\tsdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);\n\n\t\tret = sdw_cdns_enable_interrupt(cdns, true);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"cannot enable interrupts during resume\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\t/*\n\t\t * follow recommended programming flows to avoid\n\t\t * timeouts when gsync is enabled\n\t\t */\n\t\tif (multi_link)\n\t\t\tintel_shim_sync_arm(sdw);\n\n\t\tret = sdw_cdns_init(&sdw->cdns);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"unable to initialize Cadence IP during resume\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tret = sdw_cdns_exit_reset(cdns);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"unable to exit bus reset sequence during resume\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (multi_link) {\n\t\t\tret = intel_shim_sync_go(sdw);\n\t\t\tif (ret < 0) {\n\t\t\t\tdev_err(dev, \"sync go failed during resume\\n\");\n\t\t\t\treturn ret;\n\t\t\t}\n\t\t}\n\t\tsdw_cdns_check_self_clearing_bits(cdns, \"intel_resume_runtime TEARDOWN\",\n\t\t\t\t\t\t  true, INTEL_MASTER_RESET_ITERATIONS);\n\n\t} else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {\n\t\tret = intel_init(sdw);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"%s failed: %d\\n\", __func__, ret);\n\t\t\treturn ret;\n\t\t}\n\n\t\t/*\n\t\t * An exception condition occurs for the CLK_STOP_BUS_RESET\n\t\t * case if one or more masters remain active. In this condition,\n\t\t * all the masters are powered on for they are in the same power\n\t\t * domain. Master can preserve its context for clock stop0, so\n\t\t * there is no need to clear slave status and reset bus.\n\t\t */\n\t\tclock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);\n\n\t\tif (!clock_stop0) {\n\n\t\t\t/*\n\t\t\t * make sure all Slaves are tagged as UNATTACHED and\n\t\t\t * provide reason for reinitialization\n\t\t\t */\n\n\t\t\tstatus = SDW_UNATTACH_REQUEST_MASTER_RESET;\n\t\t\tsdw_clear_slave_status(bus, status);\n\n\t\t\tret = sdw_cdns_enable_interrupt(cdns, true);\n\t\t\tif (ret < 0) {\n\t\t\t\tdev_err(dev, \"cannot enable interrupts during resume\\n\");\n\t\t\t\treturn ret;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * follow recommended programming flows to avoid\n\t\t\t * timeouts when gsync is enabled\n\t\t\t */\n\t\t\tif (multi_link)\n\t\t\t\tintel_shim_sync_arm(sdw);\n\n\t\t\t/*\n\t\t\t * Re-initialize the IP since it was powered-off\n\t\t\t */\n\t\t\tsdw_cdns_init(&sdw->cdns);\n\n\t\t} else {\n\t\t\tret = sdw_cdns_enable_interrupt(cdns, true);\n\t\t\tif (ret < 0) {\n\t\t\t\tdev_err(dev, \"cannot enable interrupts during resume\\n\");\n\t\t\t\treturn ret;\n\t\t\t}\n\t\t}\n\n\t\tret = sdw_cdns_clock_restart(cdns, !clock_stop0);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"unable to restart clock during resume\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (!clock_stop0) {\n\t\t\tret = sdw_cdns_exit_reset(cdns);\n\t\t\tif (ret < 0) {\n\t\t\t\tdev_err(dev, \"unable to exit bus reset sequence during resume\\n\");\n\t\t\t\treturn ret;\n\t\t\t}\n\n\t\t\tif (multi_link) {\n\t\t\t\tret = intel_shim_sync_go(sdw);\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tdev_err(sdw->cdns.dev, \"sync go failed during resume\\n\");\n\t\t\t\t\treturn ret;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tsdw_cdns_check_self_clearing_bits(cdns, \"intel_resume_runtime BUS_RESET\",\n\t\t\t\t\t\t  true, INTEL_MASTER_RESET_ITERATIONS);\n\n\t} else if (!clock_stop_quirks) {\n\n\t\tclock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);\n\t\tif (!clock_stop0)\n\t\t\tdev_err(dev, \"%s invalid configuration, clock was not stopped\", __func__);\n\n\t\tret = intel_init(sdw);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"%s failed: %d\\n\", __func__, ret);\n\t\t\treturn ret;\n\t\t}\n\n\t\tret = sdw_cdns_enable_interrupt(cdns, true);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"cannot enable interrupts during resume\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tret = sdw_cdns_clock_restart(cdns, false);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"unable to resume master during resume\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\tsdw_cdns_check_self_clearing_bits(cdns, \"intel_resume_runtime no_quirks\",\n\t\t\t\t\t\t  true, INTEL_MASTER_RESET_ITERATIONS);\n\t} else {\n\t\tdev_err(dev, \"%s clock_stop_quirks %x unsupported\\n\",\n\t\t\t__func__, clock_stop_quirks);\n\t\tret = -EINVAL;\n\t}\n\n\treturn ret;\n}",
        "static void *ocfs2_dlm_seq_start(struct seq_file *m, loff_t *pos)\n{\n\tstruct ocfs2_dlm_seq_priv *priv = m->private;\n\tstruct ocfs2_lock_res *iter;\n": "static void *ocfs2_dlm_seq_start(struct seq_file *m, loff_t *pos)\n{\n\tstruct ocfs2_dlm_seq_priv *priv = m->private;\n\tstruct ocfs2_lock_res *iter;\n\n\tspin_lock(&ocfs2_dlm_tracking_lock);\n\titer = ocfs2_dlm_next_res(&priv->p_iter_res, priv);\n\tif (iter) {\n\t\t/* Since lockres' have the lifetime of their container\n\t\t * (which can be inodes, ocfs2_supers, etc) we want to\n\t\t * copy this out to a temporary lockres while still\n\t\t * under the spinlock. Obviously after this we can't\n\t\t * trust any pointers on the copy returned, but that's\n\t\t * ok as the information we want isn't typically held\n\t\t * in them. */\n\t\tpriv->p_tmp_res = *iter;\n\t\titer = &priv->p_tmp_res;\n\t}\n\tspin_unlock(&ocfs2_dlm_tracking_lock);\n\n\treturn iter;\n}",
        "static int trace_ctxwake_raw(struct trace_iterator *iter, char S)\n{\n\tstruct ctx_switch_entry *field;\n\tint T;\n": "static int trace_ctxwake_raw(struct trace_iterator *iter, char S)\n{\n\tstruct ctx_switch_entry *field;\n\tint T;\n\n\ttrace_assign_type(field, iter->ent);\n\n\tif (!S)\n\t\tS = task_index_to_char(field->prev_state);\n\tT = task_index_to_char(field->next_state);\n\ttrace_seq_printf(&iter->seq, \"%d %d %c %d %d %d %c\\n\",\n\t\t\t field->prev_pid,\n\t\t\t field->prev_prio,\n\t\t\t S,\n\t\t\t field->next_cpu,\n\t\t\t field->next_pid,\n\t\t\t field->next_prio,\n\t\t\t T);\n\n\treturn trace_handle_return(&iter->seq);\n}",
        "static int imx274_set_exposure(struct stimx274 *priv, int val)\n{\n\tint err;\n\tu32 hmax;\n\tu32 coarse_time; /* exposure time in unit of line (HMAX)*/": "static int imx274_set_exposure(struct stimx274 *priv, int val)\n{\n\tint err;\n\tu32 hmax;\n\tu32 coarse_time; /* exposure time in unit of line (HMAX)*/\n\n\tdev_dbg(&priv->client->dev,\n\t\t\"%s : EXPOSURE control input = %d\\n\", __func__, val);\n\n\t/* step 1: convert input exposure_time (val) into number of 1[HMAX] */\n\n\terr = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);\n\tif (err)\n\t\tgoto fail;\n\n\tif (hmax == 0) {\n\t\terr = -EINVAL;\n\t\tgoto fail;\n\t}\n\n\tcoarse_time = (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2 * val\n\t\t\t- priv->mode->nocpiop) / hmax;\n\n\t/* step 2: convert exposure_time into SHR value */\n\n\t/* set SHR */\n\terr = imx274_set_coarse_time(priv, &coarse_time);\n\tif (err)\n\t\tgoto fail;\n\n\tpriv->ctrls.exposure->val =\n\t\t\t(coarse_time * hmax + priv->mode->nocpiop)\n\t\t\t/ (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2);\n\n\tdev_dbg(&priv->client->dev,\n\t\t\"%s : EXPOSURE control success\\n\", __func__);\n\treturn 0;\n\nfail:\n\tdev_err(&priv->client->dev, \"%s error = %d\\n\", __func__, err);\n\n\treturn err;\n}",
        "static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)\n{\n\tstatic u8 rss_key[AQ_CFG_RSS_HASHKEY_SIZE] = {\n\t\t0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d,\n\t\t0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18,": "static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)\n{\n\tstatic u8 rss_key[AQ_CFG_RSS_HASHKEY_SIZE] = {\n\t\t0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d,\n\t\t0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18,\n\t\t0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8,\n\t\t0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70,\n\t\t0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c\n\t};\n\tstruct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;\n\tstruct aq_rss_parameters *rss_params;\n\tint i = 0;\n\n\trss_params = &cfg->aq_rss;\n\n\trss_params->hash_secret_key_size = sizeof(rss_key);\n\tmemcpy(rss_params->hash_secret_key, rss_key, sizeof(rss_key));\n\trss_params->indirection_table_size = AQ_CFG_RSS_INDIRECTION_TABLE_MAX;\n\n\tfor (i = rss_params->indirection_table_size; i--;)\n\t\trss_params->indirection_table[i] = i & (num_rss_queues - 1);\n}",
        "static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)\n{\n\tu32 support, control = 0, requested = 0;\n\tu32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;\n\tacpi_status status;": "static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)\n{\n\tu32 support, control = 0, requested = 0;\n\tu32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;\n\tacpi_status status;\n\tstruct acpi_device *device = root->device;\n\tacpi_handle handle = device->handle;\n\n\t/*\n\t * Apple always return failure on _OSC calls when _OSI(\"Darwin\") has\n\t * been called successfully. We know the feature set supported by the\n\t * platform, so avoid calling _OSC at all\n\t */\n\tif (x86_apple_machine) {\n\t\troot->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;\n\t\tdecode_osc_control(root, \"OS assumes control of\",\n\t\t\t\t   root->osc_control_set);\n\t\treturn;\n\t}\n\n\tsupport = calculate_support();\n\n\tdecode_osc_support(root, \"OS supports\", support);\n\n\tif (os_control_query_checks(root, support))\n\t\trequested = control = calculate_control();\n\n\tif (is_cxl(root)) {\n\t\tcxl_support = calculate_cxl_support();\n\t\tdecode_cxl_osc_support(root, \"OS supports\", cxl_support);\n\t\tcxl_requested = cxl_control = calculate_cxl_control();\n\t}\n\n\tstatus = acpi_pci_osc_control_set(handle, &control, support,\n\t\t\t\t\t  &cxl_control, cxl_support);\n\tif (ACPI_SUCCESS(status)) {\n\t\tif (control)\n\t\t\tdecode_osc_control(root, \"OS now controls\", control);\n\t\tif (cxl_control)\n\t\t\tdecode_cxl_osc_control(root, \"OS now controls\",\n\t\t\t\t\t   cxl_control);\n\n\t\tif (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {\n\t\t\t/*\n\t\t\t * We have ASPM control, but the FADT indicates that\n\t\t\t * it's unsupported. Leave existing configuration\n\t\t\t * intact and prevent the OS from touching it.\n\t\t\t */\n\t\t\tdev_info(&device->dev, \"FADT indicates ASPM is unsupported, using BIOS configuration\\n\");\n\t\t\t*no_aspm = 1;\n\t\t}\n\t} else {\n\t\t/*\n\t\t * We want to disable ASPM here, but aspm_disabled\n\t\t * needs to remain in its state from boot so that we\n\t\t * properly handle PCIe 1.1 devices.  So we set this\n\t\t * flag here, to defer the action until after the ACPI\n\t\t * root scan.\n\t\t */\n\t\t*no_aspm = 1;\n\n\t\t/* _OSC is optional for PCI host bridges */\n\t\tif (status == AE_NOT_FOUND && !is_pcie(root))\n\t\t\treturn;\n\n\t\tif (control) {\n\t\t\tdecode_osc_control(root, \"OS requested\", requested);\n\t\t\tdecode_osc_control(root, \"platform willing to grant\", control);\n\t\t}\n\t\tif (cxl_control) {\n\t\t\tdecode_cxl_osc_control(root, \"OS requested\", cxl_requested);\n\t\t\tdecode_cxl_osc_control(root, \"platform willing to grant\",\n\t\t\t\t\t   cxl_control);\n\t\t}\n\n\t\tdev_info(&device->dev, \"_OSC: platform retains control of PCIe features (%s)\\n\",\n\t\t\t acpi_format_exception(status));\n\t}\n}",
        "static struct sk_buff *lan9303_xmit(struct sk_buff *skb, struct net_device *dev)\n{\n\tstruct dsa_port *dp = dsa_slave_to_port(dev);\n\t__be16 *lan9303_tag;\n\tu16 tag;": "static struct sk_buff *lan9303_xmit(struct sk_buff *skb, struct net_device *dev)\n{\n\tstruct dsa_port *dp = dsa_slave_to_port(dev);\n\t__be16 *lan9303_tag;\n\tu16 tag;\n\n\t/* provide 'LAN9303_TAG_LEN' bytes additional space */\n\tskb_push(skb, LAN9303_TAG_LEN);\n\n\t/* make room between MACs and Ether-Type */\n\tdsa_alloc_etype_header(skb, LAN9303_TAG_LEN);\n\n\tlan9303_tag = dsa_etype_header_pos_tx(skb);\n\n\ttag = lan9303_xmit_use_arl(dp, skb->data) ?\n\t\tLAN9303_TAG_TX_USE_ALR :\n\t\tdp->index | LAN9303_TAG_TX_STP_OVERRIDE;\n\tlan9303_tag[0] = htons(ETH_P_8021Q);\n\tlan9303_tag[1] = htons(tag);\n\n\treturn skb;\n}",
        "static int smc_lgr_create(struct smc_sock *smc, struct smc_init_info *ini)\n{\n\tstruct smc_link_group *lgr;\n\tstruct list_head *lgr_list;\n\tstruct smc_link *lnk;": "static int smc_lgr_create(struct smc_sock *smc, struct smc_init_info *ini)\n{\n\tstruct smc_link_group *lgr;\n\tstruct list_head *lgr_list;\n\tstruct smc_link *lnk;\n\tspinlock_t *lgr_lock;\n\tu8 link_idx;\n\tint rc = 0;\n\tint i;\n\n\tif (ini->is_smcd && ini->vlan_id) {\n\t\tif (smc_ism_get_vlan(ini->ism_dev[ini->ism_selected],\n\t\t\t\t     ini->vlan_id)) {\n\t\t\trc = SMC_CLC_DECL_ISMVLANERR;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tlgr = kzalloc(sizeof(*lgr), GFP_KERNEL);\n\tif (!lgr) {\n\t\trc = SMC_CLC_DECL_MEM;\n\t\tgoto ism_put_vlan;\n\t}\n\tlgr->tx_wq = alloc_workqueue(\"smc_tx_wq-%*phN\", 0, 0,\n\t\t\t\t     SMC_LGR_ID_SIZE, &lgr->id);\n\tif (!lgr->tx_wq) {\n\t\trc = -ENOMEM;\n\t\tgoto free_lgr;\n\t}\n\tlgr->is_smcd = ini->is_smcd;\n\tlgr->sync_err = 0;\n\tlgr->terminating = 0;\n\tlgr->freeing = 0;\n\tlgr->vlan_id = ini->vlan_id;\n\trefcount_set(&lgr->refcnt, 1); /* set lgr refcnt to 1 */\n\tmutex_init(&lgr->sndbufs_lock);\n\tmutex_init(&lgr->rmbs_lock);\n\trwlock_init(&lgr->conns_lock);\n\tfor (i = 0; i < SMC_RMBE_SIZES; i++) {\n\t\tINIT_LIST_HEAD(&lgr->sndbufs[i]);\n\t\tINIT_LIST_HEAD(&lgr->rmbs[i]);\n\t}\n\tlgr->next_link_id = 0;\n\tsmc_lgr_list.num += SMC_LGR_NUM_INCR;\n\tmemcpy(&lgr->id, (u8 *)&smc_lgr_list.num, SMC_LGR_ID_SIZE);\n\tINIT_DELAYED_WORK(&lgr->free_work, smc_lgr_free_work);\n\tINIT_WORK(&lgr->terminate_work, smc_lgr_terminate_work);\n\tlgr->conns_all = RB_ROOT;\n\tif (ini->is_smcd) {\n\t\t/* SMC-D specific settings */\n\t\tget_device(&ini->ism_dev[ini->ism_selected]->dev);\n\t\tlgr->peer_gid = ini->ism_peer_gid[ini->ism_selected];\n\t\tlgr->smcd = ini->ism_dev[ini->ism_selected];\n\t\tlgr_list = &ini->ism_dev[ini->ism_selected]->lgr_list;\n\t\tlgr_lock = &lgr->smcd->lgr_lock;\n\t\tlgr->smc_version = ini->smcd_version;\n\t\tlgr->peer_shutdown = 0;\n\t\tatomic_inc(&ini->ism_dev[ini->ism_selected]->lgr_cnt);\n\t} else {\n\t\t/* SMC-R specific settings */\n\t\tstruct smc_ib_device *ibdev;\n\t\tint ibport;\n\n\t\tlgr->role = smc->listen_smc ? SMC_SERV : SMC_CLNT;\n\t\tlgr->smc_version = ini->smcr_version;\n\t\tmemcpy(lgr->peer_systemid, ini->peer_systemid,\n\t\t       SMC_SYSTEMID_LEN);\n\t\tif (lgr->smc_version == SMC_V2) {\n\t\t\tibdev = ini->smcrv2.ib_dev_v2;\n\t\t\tibport = ini->smcrv2.ib_port_v2;\n\t\t\tlgr->saddr = ini->smcrv2.saddr;\n\t\t\tlgr->uses_gateway = ini->smcrv2.uses_gateway;\n\t\t\tmemcpy(lgr->nexthop_mac, ini->smcrv2.nexthop_mac,\n\t\t\t       ETH_ALEN);\n\t\t} else {\n\t\t\tibdev = ini->ib_dev;\n\t\t\tibport = ini->ib_port;\n\t\t}\n\t\tmemcpy(lgr->pnet_id, ibdev->pnetid[ibport - 1],\n\t\t       SMC_MAX_PNETID_LEN);\n\t\tif (smc_wr_alloc_lgr_mem(lgr))\n\t\t\tgoto free_wq;\n\t\tsmc_llc_lgr_init(lgr, smc);\n\n\t\tlink_idx = SMC_SINGLE_LINK;\n\t\tlnk = &lgr->lnk[link_idx];\n\t\trc = smcr_link_init(lgr, lnk, link_idx, ini);\n\t\tif (rc) {\n\t\t\tsmc_wr_free_lgr_mem(lgr);\n\t\t\tgoto free_wq;\n\t\t}\n\t\tlgr->net = smc_ib_net(lnk->smcibdev);\n\t\tlgr_list = &smc_lgr_list.list;\n\t\tlgr_lock = &smc_lgr_list.lock;\n\t\tatomic_inc(&lgr_cnt);\n\t}\n\tsmc->conn.lgr = lgr;\n\tspin_lock_bh(lgr_lock);\n\tlist_add_tail(&lgr->list, lgr_list);\n\tspin_unlock_bh(lgr_lock);\n\treturn 0;\n\nfree_wq:\n\tdestroy_workqueue(lgr->tx_wq);\nfree_lgr:\n\tkfree(lgr);\nism_put_vlan:\n\tif (ini->is_smcd && ini->vlan_id)\n\t\tsmc_ism_put_vlan(ini->ism_dev[ini->ism_selected], ini->vlan_id);\nout:\n\tif (rc < 0) {\n\t\tif (rc == -ENOMEM)\n\t\t\trc = SMC_CLC_DECL_MEM;\n\t\telse\n\t\t\trc = SMC_CLC_DECL_INTERR;\n\t}\n\treturn rc;\n}",
        "static int receive_data(enum port_type index, struct nozomi *dc)\n{\n\tu8 buf[RECEIVE_BUF_MAX] = { 0 };\n\tint size;\n\tu32 offset = 4;": "static int receive_data(enum port_type index, struct nozomi *dc)\n{\n\tu8 buf[RECEIVE_BUF_MAX] = { 0 };\n\tint size;\n\tu32 offset = 4;\n\tstruct port *port = &dc->port[index];\n\tvoid __iomem *addr = port->dl_addr[port->toggle_dl];\n\tstruct tty_struct *tty = tty_port_tty_get(&port->port);\n\tint i, ret;\n\n\tsize = __le32_to_cpu(readl(addr));\n\n\tif (tty && tty_throttled(tty)) {\n\t\tDBG1(\"No room in tty, don't read data, don't ack interrupt, \"\n\t\t\t\"disable interrupt\");\n\n\t\t/* disable interrupt in downlink... */\n\t\tdisable_transmit_dl(index, dc);\n\t\tret = 0;\n\t\tgoto put;\n\t}\n\n\tif (unlikely(size == 0)) {\n\t\tdev_err(&dc->pdev->dev, \"size == 0?\\n\");\n\t\tret = 1;\n\t\tgoto put;\n\t}\n\n\twhile (size > 0) {\n\t\tread_mem32((u32 *) buf, addr + offset, RECEIVE_BUF_MAX);\n\n\t\tif (size == 1) {\n\t\t\ttty_insert_flip_char(&port->port, buf[0], TTY_NORMAL);\n\t\t\tsize = 0;\n\t\t} else if (size < RECEIVE_BUF_MAX) {\n\t\t\tsize -= tty_insert_flip_string(&port->port,\n\t\t\t\t\t(char *)buf, size);\n\t\t} else {\n\t\t\ti = tty_insert_flip_string(&port->port,\n\t\t\t\t\t(char *)buf, RECEIVE_BUF_MAX);\n\t\t\tsize -= i;\n\t\t\toffset += i;\n\t\t}\n\t}\n\n\tset_bit(index, &dc->flip);\n\tret = 1;\nput:\n\ttty_kref_put(tty);\n\treturn ret;\n}",
        "static int prepare_read_data(struct ceph_connection *con)\n{\n\tstruct bio_vec bv;\n\n\tcon->in_data_crc = -1;": "static int prepare_read_data(struct ceph_connection *con)\n{\n\tstruct bio_vec bv;\n\n\tcon->in_data_crc = -1;\n\tceph_msg_data_cursor_init(&con->v2.in_cursor, con->in_msg,\n\t\t\t\t  data_len(con->in_msg));\n\n\tget_bvec_at(&con->v2.in_cursor, &bv);\n\tif (ceph_test_opt(from_msgr(con->msgr), RXBOUNCE)) {\n\t\tif (unlikely(!con->bounce_page)) {\n\t\t\tcon->bounce_page = alloc_page(GFP_NOIO);\n\t\t\tif (!con->bounce_page) {\n\t\t\t\tpr_err(\"failed to allocate bounce page\\n\");\n\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\t\t}\n\n\t\tbv.bv_page = con->bounce_page;\n\t\tbv.bv_offset = 0;\n\t}\n\tset_in_bvec(con, &bv);\n\tcon->v2.in_state = IN_S_PREPARE_READ_DATA_CONT;\n\treturn 0;\n}",
        "static int stv090x_sw_algo(struct stv090x_state *state)\n{\n\tint no_signal, zigzag, lock = 0;\n\tu32 reg;\n": "static int stv090x_sw_algo(struct stv090x_state *state)\n{\n\tint no_signal, zigzag, lock = 0;\n\tu32 reg;\n\n\ts32 dvbs2_fly_wheel;\n\ts32 inc, timeout_step, trials, steps_max;\n\n\t/* get params */\n\tstv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);\n\n\tswitch (state->search_mode) {\n\tcase STV090x_SEARCH_DVBS1:\n\tcase STV090x_SEARCH_DSS:\n\t\t/* accelerate the frequency detector */\n\t\tif (state->internal->dev_ver >= 0x20) {\n\t\t\tif (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)\n\t\t\t\tgoto err;\n\t\t}\n\n\t\tif (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)\n\t\t\tgoto err;\n\t\tzigzag = 0;\n\t\tbreak;\n\n\tcase STV090x_SEARCH_DVBS2:\n\t\tif (state->internal->dev_ver >= 0x20) {\n\t\t\tif (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)\n\t\t\t\tgoto err;\n\t\t}\n\n\t\tif (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)\n\t\t\tgoto err;\n\t\tzigzag = 1;\n\t\tbreak;\n\n\tcase STV090x_SEARCH_AUTO:\n\tdefault:\n\t\t/* accelerate the frequency detector */\n\t\tif (state->internal->dev_ver >= 0x20) {\n\t\t\tif (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)\n\t\t\t\tgoto err;\n\t\t\tif (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)\n\t\t\t\tgoto err;\n\t\t}\n\n\t\tif (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)\n\t\t\tgoto err;\n\t\tzigzag = 0;\n\t\tbreak;\n\t}\n\n\ttrials = 0;\n\tdo {\n\t\tlock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);\n\t\tno_signal = stv090x_chk_signal(state);\n\t\ttrials++;\n\n\t\t/*run the SW search 2 times maximum*/\n\t\tif (lock || no_signal || (trials == 2)) {\n\t\t\t/*Check if the demod is not losing lock in DVBS2*/\n\t\t\tif (state->internal->dev_ver >= 0x20) {\n\t\t\t\tif (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)\n\t\t\t\t\tgoto err;\n\t\t\t\tif (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)\n\t\t\t\t\tgoto err;\n\t\t\t}\n\n\t\t\treg = STV090x_READ_DEMOD(state, DMDSTATE);\n\t\t\tif ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {\n\t\t\t\t/*Check if the demod is not losing lock in DVBS2*/\n\t\t\t\tmsleep(timeout_step);\n\t\t\t\treg = STV090x_READ_DEMOD(state, DMDFLYW);\n\t\t\t\tdvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);\n\t\t\t\tif (dvbs2_fly_wheel < 0xd) {\t /*if correct frames is decrementing */\n\t\t\t\t\tmsleep(timeout_step);\n\t\t\t\t\treg = STV090x_READ_DEMOD(state, DMDFLYW);\n\t\t\t\t\tdvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);\n\t\t\t\t}\n\t\t\t\tif (dvbs2_fly_wheel < 0xd) {\n\t\t\t\t\t/*FALSE lock, The demod is losing lock */\n\t\t\t\t\tlock = 0;\n\t\t\t\t\tif (trials < 2) {\n\t\t\t\t\t\tif (state->internal->dev_ver >= 0x20) {\n\t\t\t\t\t\t\tif (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)\n\t\t\t\t\t\t\t\tgoto err;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tif (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)\n\t\t\t\t\t\t\tgoto err;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} while ((!lock) && (trials < 2) && (!no_signal));\n\n\treturn lock;\nerr:\n\tdprintk(FE_ERROR, 1, \"I/O error\");\n\treturn -1;\n}",
        "static void mptcp_token_test_destroyed(struct kunit *test)\n{\n\tstruct mptcp_subflow_request_sock *req = build_req_sock(test);\n\tstruct mptcp_sock *msk = build_msk(test);\n\tstruct mptcp_sock *null_msk = NULL;": "static void mptcp_token_test_destroyed(struct kunit *test)\n{\n\tstruct mptcp_subflow_request_sock *req = build_req_sock(test);\n\tstruct mptcp_sock *msk = build_msk(test);\n\tstruct mptcp_sock *null_msk = NULL;\n\tstruct sock *sk;\n\n\tsk = (struct sock *)msk;\n\n\tKUNIT_ASSERT_EQ(test, 0,\n\t\t\tmptcp_token_new_request((struct request_sock *)req));\n\tmsk->token = req->token;\n\tmptcp_token_accept(req, msk);\n\n\t/* simulate race on removal */\n\trefcount_set(&sk->sk_refcnt, 0);\n\tKUNIT_EXPECT_PTR_EQ(test, null_msk, mptcp_token_get_sock(&init_net, msk->token));\n\n\t/* cleanup */\n\tmptcp_token_destroy(msk);\n}",
        "static int optee_ffa_probe(struct ffa_device *ffa_dev)\n{\n\tconst struct ffa_dev_ops *ffa_ops;\n\tunsigned int rpc_param_count;\n\tstruct tee_shm_pool *pool;": "static int optee_ffa_probe(struct ffa_device *ffa_dev)\n{\n\tconst struct ffa_dev_ops *ffa_ops;\n\tunsigned int rpc_param_count;\n\tstruct tee_shm_pool *pool;\n\tstruct tee_device *teedev;\n\tstruct tee_context *ctx;\n\tu32 arg_cache_flags = 0;\n\tstruct optee *optee;\n\tu32 sec_caps;\n\tint rc;\n\n\tffa_ops = ffa_dev_ops_get(ffa_dev);\n\tif (!ffa_ops) {\n\t\tpr_warn(\"failed \\\"method\\\" init: ffa\\n\");\n\t\treturn -ENOENT;\n\t}\n\n\tif (!optee_ffa_api_is_compatbile(ffa_dev, ffa_ops))\n\t\treturn -EINVAL;\n\n\tif (!optee_ffa_exchange_caps(ffa_dev, ffa_ops, &sec_caps,\n\t\t\t\t     &rpc_param_count))\n\t\treturn -EINVAL;\n\tif (sec_caps & OPTEE_FFA_SEC_CAP_ARG_OFFSET)\n\t\targ_cache_flags |= OPTEE_SHM_ARG_SHARED;\n\n\toptee = kzalloc(sizeof(*optee), GFP_KERNEL);\n\tif (!optee)\n\t\treturn -ENOMEM;\n\n\tpool = optee_ffa_shm_pool_alloc_pages();\n\tif (IS_ERR(pool)) {\n\t\trc = PTR_ERR(pool);\n\t\tgoto err_free_optee;\n\t}\n\toptee->pool = pool;\n\n\toptee->ops = &optee_ffa_ops;\n\toptee->ffa.ffa_dev = ffa_dev;\n\toptee->ffa.ffa_ops = ffa_ops;\n\toptee->rpc_param_count = rpc_param_count;\n\n\tteedev = tee_device_alloc(&optee_ffa_clnt_desc, NULL, optee->pool,\n\t\t\t\t  optee);\n\tif (IS_ERR(teedev)) {\n\t\trc = PTR_ERR(teedev);\n\t\tgoto err_free_pool;\n\t}\n\toptee->teedev = teedev;\n\n\tteedev = tee_device_alloc(&optee_ffa_supp_desc, NULL, optee->pool,\n\t\t\t\t  optee);\n\tif (IS_ERR(teedev)) {\n\t\trc = PTR_ERR(teedev);\n\t\tgoto err_unreg_teedev;\n\t}\n\toptee->supp_teedev = teedev;\n\n\trc = tee_device_register(optee->teedev);\n\tif (rc)\n\t\tgoto err_unreg_supp_teedev;\n\n\trc = tee_device_register(optee->supp_teedev);\n\tif (rc)\n\t\tgoto err_unreg_supp_teedev;\n\n\trc = rhashtable_init(&optee->ffa.global_ids, &shm_rhash_params);\n\tif (rc)\n\t\tgoto err_unreg_supp_teedev;\n\tmutex_init(&optee->ffa.mutex);\n\tmutex_init(&optee->call_queue.mutex);\n\tINIT_LIST_HEAD(&optee->call_queue.waiters);\n\toptee_supp_init(&optee->supp);\n\toptee_shm_arg_cache_init(optee, arg_cache_flags);\n\tffa_dev_set_drvdata(ffa_dev, optee);\n\tctx = teedev_open(optee->teedev);\n\tif (IS_ERR(ctx)) {\n\t\trc = PTR_ERR(ctx);\n\t\tgoto err_rhashtable_free;\n\t}\n\toptee->ctx = ctx;\n\trc = optee_notif_init(optee, OPTEE_DEFAULT_MAX_NOTIF_VALUE);\n\tif (rc)\n\t\tgoto err_close_ctx;\n\n\trc = optee_enumerate_devices(PTA_CMD_GET_DEVICES);\n\tif (rc)\n\t\tgoto err_unregister_devices;\n\n\tpr_info(\"initialized driver\\n\");\n\treturn 0;\n\nerr_unregister_devices:\n\toptee_unregister_devices();\n\toptee_notif_uninit(optee);\nerr_close_ctx:\n\tteedev_close_context(ctx);\nerr_rhashtable_free:\n\trhashtable_free_and_destroy(&optee->ffa.global_ids, rh_free_fn, NULL);\n\toptee_supp_uninit(&optee->supp);\n\tmutex_destroy(&optee->call_queue.mutex);\n\tmutex_destroy(&optee->ffa.mutex);\nerr_unreg_supp_teedev:\n\ttee_device_unregister(optee->supp_teedev);\nerr_unreg_teedev:\n\ttee_device_unregister(optee->teedev);\nerr_free_pool:\n\ttee_shm_pool_free(pool);\nerr_free_optee:\n\tkfree(optee);\n\treturn rc;\n}",
        "static void fu740_pcie_init_phy(struct fu740_pcie *afp)\n{\n\t/* Enable phy cr_para_sel interfaces */\n\twritel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);\n\twritel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);": "static void fu740_pcie_init_phy(struct fu740_pcie *afp)\n{\n\t/* Enable phy cr_para_sel interfaces */\n\twritel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);\n\twritel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);\n\n\t/*\n\t * Wait 10 cr_para cycles to guarantee that the registers are ready\n\t * to be edited.\n\t */\n\tndelay(10);\n\n\t/* Set PHY AC termination mode */\n\tfu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n\tfu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);\n}",
        "static void *worker_testapp_validate_tx(void *arg)\n{\n\tstruct test_spec *test = (struct test_spec *)arg;\n\tstruct ifobject *ifobject = test->ifobj_tx;\n\tint err;": "static void *worker_testapp_validate_tx(void *arg)\n{\n\tstruct test_spec *test = (struct test_spec *)arg;\n\tstruct ifobject *ifobject = test->ifobj_tx;\n\tint err;\n\n\tif (test->current_step == 1)\n\t\tthread_common_ops(test, ifobject);\n\n\tprint_verbose(\"Sending %d packets on interface %s\\n\", ifobject->pkt_stream->nb_pkts,\n\t\t      ifobject->ifname);\n\terr = send_pkts(test, ifobject);\n\n\tif (!err && ifobject->validation_func)\n\t\terr = ifobject->validation_func(ifobject);\n\tif (err)\n\t\treport_failure(test);\n\n\tif (test->total_steps == test->current_step || err)\n\t\ttestapp_cleanup_xsk_res(ifobject);\n\tpthread_exit(NULL);\n}",
        "static int active_load_balance_cpu_stop(void *data)\n{\n\tstruct rq *busiest_rq = data;\n\tint busiest_cpu = cpu_of(busiest_rq);\n\tint target_cpu = busiest_rq->push_cpu;": "static int active_load_balance_cpu_stop(void *data)\n{\n\tstruct rq *busiest_rq = data;\n\tint busiest_cpu = cpu_of(busiest_rq);\n\tint target_cpu = busiest_rq->push_cpu;\n\tstruct rq *target_rq = cpu_rq(target_cpu);\n\tstruct sched_domain *sd;\n\tstruct task_struct *p = NULL;\n\tstruct rq_flags rf;\n\n\trq_lock_irq(busiest_rq, &rf);\n\t/*\n\t * Between queueing the stop-work and running it is a hole in which\n\t * CPUs can become inactive. We should not move tasks from or to\n\t * inactive CPUs.\n\t */\n\tif (!cpu_active(busiest_cpu) || !cpu_active(target_cpu))\n\t\tgoto out_unlock;\n\n\t/* Make sure the requested CPU hasn't gone down in the meantime: */\n\tif (unlikely(busiest_cpu != smp_processor_id() ||\n\t\t     !busiest_rq->active_balance))\n\t\tgoto out_unlock;\n\n\t/* Is there any task to move? */\n\tif (busiest_rq->nr_running <= 1)\n\t\tgoto out_unlock;\n\n\t/*\n\t * This condition is \"impossible\", if it occurs\n\t * we need to fix it. Originally reported by\n\t * Bjorn Helgaas on a 128-CPU setup.\n\t */\n\tBUG_ON(busiest_rq == target_rq);\n\n\t/* Search for an sd spanning us and the target CPU. */\n\trcu_read_lock();\n\tfor_each_domain(target_cpu, sd) {\n\t\tif (cpumask_test_cpu(busiest_cpu, sched_domain_span(sd)))\n\t\t\tbreak;\n\t}\n\n\tif (likely(sd)) {\n\t\tstruct lb_env env = {\n\t\t\t.sd\t\t= sd,\n\t\t\t.dst_cpu\t= target_cpu,\n\t\t\t.dst_rq\t\t= target_rq,\n\t\t\t.src_cpu\t= busiest_rq->cpu,\n\t\t\t.src_rq\t\t= busiest_rq,\n\t\t\t.idle\t\t= CPU_IDLE,\n\t\t\t.flags\t\t= LBF_ACTIVE_LB,\n\t\t};\n\n\t\tschedstat_inc(sd->alb_count);\n\t\tupdate_rq_clock(busiest_rq);\n\n\t\tp = detach_one_task(&env);\n\t\tif (p) {\n\t\t\tschedstat_inc(sd->alb_pushed);\n\t\t\t/* Active balancing done, reset the failure counter. */\n\t\t\tsd->nr_balance_failed = 0;\n\t\t} else {\n\t\t\tschedstat_inc(sd->alb_failed);\n\t\t}\n\t}\n\trcu_read_unlock();\nout_unlock:\n\tbusiest_rq->active_balance = 0;\n\trq_unlock(busiest_rq, &rf);\n\n\tif (p)\n\t\tattach_one_task(target_rq, p);\n\n\tlocal_irq_enable();\n\n\treturn 0;\n}",
        "static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)\n{\n\tu32 tx_fifo_avail;\n\tunsigned int tx_left;\n\tconst void *tx_buf;": "static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)\n{\n\tu32 tx_fifo_avail;\n\tunsigned int tx_left;\n\tconst void *tx_buf;\n\n\t/* if events is zero transfer has not started and tx fifo is empty */\n\ttx_fifo_avail = events ? SPIE_TXCNT(events) :  FSL_ESPI_FIFO_SIZE;\nstart:\n\ttx_left = espi->tx_t->len - espi->tx_pos;\n\ttx_buf = espi->tx_t->tx_buf;\n\twhile (tx_fifo_avail >= min(4U, tx_left) && tx_left) {\n\t\tif (tx_left >= 4) {\n\t\t\tif (!tx_buf)\n\t\t\t\tfsl_espi_write_reg(espi, ESPI_SPITF, 0);\n\t\t\telse if (espi->swab)\n\t\t\t\tfsl_espi_write_reg(espi, ESPI_SPITF,\n\t\t\t\t\tswahb32p(tx_buf + espi->tx_pos));\n\t\t\telse\n\t\t\t\tfsl_espi_write_reg(espi, ESPI_SPITF,\n\t\t\t\t\t*(u32 *)(tx_buf + espi->tx_pos));\n\t\t\tespi->tx_pos += 4;\n\t\t\ttx_left -= 4;\n\t\t\ttx_fifo_avail -= 4;\n\t\t} else if (tx_left >= 2 && tx_buf && espi->swab) {\n\t\t\tfsl_espi_write_reg16(espi, ESPI_SPITF,\n\t\t\t\t\tswab16p(tx_buf + espi->tx_pos));\n\t\t\tespi->tx_pos += 2;\n\t\t\ttx_left -= 2;\n\t\t\ttx_fifo_avail -= 2;\n\t\t} else {\n\t\t\tif (!tx_buf)\n\t\t\t\tfsl_espi_write_reg8(espi, ESPI_SPITF, 0);\n\t\t\telse\n\t\t\t\tfsl_espi_write_reg8(espi, ESPI_SPITF,\n\t\t\t\t\t*(u8 *)(tx_buf + espi->tx_pos));\n\t\t\tespi->tx_pos += 1;\n\t\t\ttx_left -= 1;\n\t\t\ttx_fifo_avail -= 1;\n\t\t}\n\t}\n\n\tif (!tx_left) {\n\t\t/* Last transfer finished, in rxskip mode only one is needed */\n\t\tif (list_is_last(&espi->tx_t->transfer_list,\n\t\t    espi->m_transfers) || espi->rxskip) {\n\t\t\tespi->tx_done = true;\n\t\t\treturn;\n\t\t}\n\t\tespi->tx_t = list_next_entry(espi->tx_t, transfer_list);\n\t\tespi->tx_pos = 0;\n\t\t/* continue with next transfer if tx fifo is not full */\n\t\tif (tx_fifo_avail)\n\t\t\tgoto start;\n\t}\n}",
        "static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)\n{\n\tstruct tty_port *tport;\n\tstruct qcom_geni_serial_port *port = to_dev_port(uport, uport);\n\tu32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;": "static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)\n{\n\tstruct tty_port *tport;\n\tstruct qcom_geni_serial_port *port = to_dev_port(uport, uport);\n\tu32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;\n\tu32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;\n\tint ret;\n\n\ttport = &uport->state->port;\n\tioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);\n\tif (drop)\n\t\treturn 0;\n\n\tret = tty_insert_flip_string(tport, port->rx_fifo, bytes);\n\tif (ret != bytes) {\n\t\tdev_err(uport->dev, \"%s:Unable to push data ret %d_bytes %d\\n\",\n\t\t\t\t__func__, ret, bytes);\n\t\tWARN_ON_ONCE(1);\n\t}\n\tuport->icount.rx += ret;\n\ttty_flip_buffer_push(tport);\n\treturn ret;\n}",
        "static void ice_request_fw(struct ice_pf *pf)\n{\n\tchar *opt_fw_filename = ice_get_opt_fw_name(pf);\n\tconst struct firmware *firmware = NULL;\n\tstruct device *dev = ice_pf_to_dev(pf);": "static void ice_request_fw(struct ice_pf *pf)\n{\n\tchar *opt_fw_filename = ice_get_opt_fw_name(pf);\n\tconst struct firmware *firmware = NULL;\n\tstruct device *dev = ice_pf_to_dev(pf);\n\tint err = 0;\n\n\t/* optional device-specific DDP (if present) overrides the default DDP\n\t * package file. kernel logs a debug message if the file doesn't exist,\n\t * and warning messages for other errors.\n\t */\n\tif (opt_fw_filename) {\n\t\terr = firmware_request_nowarn(&firmware, opt_fw_filename, dev);\n\t\tif (err) {\n\t\t\tkfree(opt_fw_filename);\n\t\t\tgoto dflt_pkg_load;\n\t\t}\n\n\t\t/* request for firmware was successful. Download to device */\n\t\tice_load_pkg(firmware, pf);\n\t\tkfree(opt_fw_filename);\n\t\trelease_firmware(firmware);\n\t\treturn;\n\t}\n\ndflt_pkg_load:\n\terr = request_firmware(&firmware, ICE_DDP_PKG_FILE, dev);\n\tif (err) {\n\t\tdev_err(dev, \"The DDP package file was not found or could not be read. Entering Safe Mode\\n\");\n\t\treturn;\n\t}\n\n\t/* request for firmware was successful. Download to device */\n\tice_load_pkg(firmware, pf);\n\trelease_firmware(firmware);\n}",
        "static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf)\n{\n\tconst struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;\n\tconst struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;\n\tconst struct v4l2_ctrl_h264_sps *sps = ctrls->sps;": "static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf)\n{\n\tconst struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;\n\tconst struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;\n\tconst struct v4l2_ctrl_h264_sps *sps = ctrls->sps;\n\tconst struct v4l2_ctrl_h264_pps *pps = ctrls->pps;\n\tstruct hantro_dev *vpu = ctx->dev;\n\tu32 reg;\n\n\treg = VDPU_REG_DEC_ADV_PRE_DIS(0) |\n\t      VDPU_REG_DEC_SCMD_DIS(0) |\n\t      VDPU_REG_FILTERING_DIS(0) |\n\t      VDPU_REG_PIC_FIXED_QUANT(0) |\n\t      VDPU_REG_DEC_LATENCY(0);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));\n\n\treg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) |\n\t      VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));\n\n\treg = VDPU_REG_APF_THRESHOLD(8) |\n\t      VDPU_REG_STARTMB_X(0) |\n\t      VDPU_REG_STARTMB_Y(0);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));\n\n\treg = VDPU_REG_DEC_MODE(0);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));\n\n\treg = VDPU_REG_DEC_STRENDIAN_E(1) |\n\t      VDPU_REG_DEC_STRSWAP32_E(1) |\n\t      VDPU_REG_DEC_OUTSWAP32_E(1) |\n\t      VDPU_REG_DEC_INSWAP32_E(1) |\n\t      VDPU_REG_DEC_OUT_ENDIAN(1) |\n\t      VDPU_REG_DEC_IN_ENDIAN(0);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));\n\n\treg = VDPU_REG_DEC_DATA_DISC_E(0) |\n\t      VDPU_REG_DEC_MAX_BURST(16) |\n\t      VDPU_REG_DEC_AXI_WR_ID(0) |\n\t      VDPU_REG_DEC_AXI_RD_ID(0xff);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));\n\n\treg = VDPU_REG_START_CODE_E(1) |\n\t      VDPU_REG_CH_8PIX_ILEAV_E(0) |\n\t      VDPU_REG_RLC_MODE_E(0) |\n\t      VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) &&\n\t\t\t\t       (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD ||\n\t\t\t\t\tdec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) |\n\t      VDPU_REG_PIC_FIELDMODE_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) |\n\t      VDPU_REG_PIC_TOPFIELD_E(!(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)) |\n\t      VDPU_REG_WRITE_MVS_E((sps->profile_idc > 66) && dec_param->nal_ref_idc) |\n\t      VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) |\n\t      VDPU_REG_PICORD_COUNT_E(sps->profile_idc > 66) |\n\t      VDPU_REG_DEC_TIMEOUT_E(1) |\n\t      VDPU_REG_DEC_CLK_GATE_E(1);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));\n\n\treg = VDPU_REG_PRED_BC_TAP_0_0(1) |\n\t      VDPU_REG_PRED_BC_TAP_0_1((u32)-5) |\n\t      VDPU_REG_PRED_BC_TAP_0_2(20);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(59));\n\n\treg = VDPU_REG_REFBU_E(0);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(65));\n\n\treg = VDPU_REG_STRM_START_BIT(0);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(109));\n\n\treg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) |\n\t      VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) |\n\t      VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |\n\t      VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width));\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(110));\n\n\treg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) |\n\t      VDPU_REG_REF_FRAMES(sps->max_num_ref_frames);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(111));\n\n\treg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) |\n\t      VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) |\n\t      VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) |\n\t      VDPU_REG_FRAMENUM(dec_param->frame_num);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(112));\n\n\treg = VDPU_REG_REFPIC_MK_LEN(dec_param->dec_ref_pic_marking_bit_size) |\n\t      VDPU_REG_IDR_PIC_ID(dec_param->idr_pic_id);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(113));\n\n\treg = VDPU_REG_PPS_ID(pps->pic_parameter_set_id) |\n\t      VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |\n\t      VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |\n\t      VDPU_REG_POC_LENGTH(dec_param->pic_order_cnt_bit_size);\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(114));\n\n\treg = VDPU_REG_IDR_PIC_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) |\n\t      VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) |\n\t      VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) |\n\t      VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) |\n\t      VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) |\n\t      VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) |\n\t      VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) |\n\t      VDPU_REG_TYPE1_QUANT_E(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) |\n\t      VDPU_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY));\n\tvdpu_write_relaxed(vpu, reg, VDPU_SWREG(115));\n}",
        "static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)\n{\n\tu8 adr = state->demod_address, mm[8], len;\n\n\tif (state->single_master)": "static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)\n{\n\tu8 adr = state->demod_address, mm[8], len;\n\n\tif (state->single_master)\n\t\tflags |= 0xC0;\n\tif (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {\n\t\tmm[0] = (((reg << 1) & 0xFF) | 0x01);\n\t\tmm[1] = ((reg >> 16) & 0xFF);\n\t\tmm[2] = ((reg >> 24) & 0xFF) | flags;\n\t\tmm[3] = ((reg >> 7) & 0xFF);\n\t\tlen = 4;\n\t} else {\n\t\tmm[0] = ((reg << 1) & 0xFF);\n\t\tmm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));\n\t\tlen = 2;\n\t}\n\tmm[len] = data & 0xff;\n\tmm[len + 1] = (data >> 8) & 0xff;\n\tmm[len + 2] = (data >> 16) & 0xff;\n\tmm[len + 3] = (data >> 24) & 0xff;\n\tdprintk(2, \"(0x%08x, 0x%08x, 0x%02x)\\n\", reg, data, flags);\n\n\treturn i2c_write(state, adr, mm, len + 4);\n}",
        "static void ww_test_edeadlk_acquire_more_edeadlk_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);": "static void ww_test_edeadlk_acquire_more_edeadlk_slow(void)\n{\n\tint ret;\n\n\tww_mutex_base_lock(&o2.base);\n\tmutex_release(&o2.base.dep_map, _THIS_IP_);\n\to2.ctx = &t2;\n\n\tww_mutex_base_lock(&o3.base);\n\tmutex_release(&o3.base.dep_map, _THIS_IP_);\n\to3.ctx = &t2;\n\n\tWWAI(&t);\n\tt2 = t;\n\tt2.stamp--;\n\n\tret = WWL(&o, &t);\n\tWARN_ON(ret);\n\n\tret = WWL(&o2, &t);\n\tWARN_ON(ret != -EDEADLK);\n\n\tww_mutex_lock_slow(&o3, &t);\n}",
        "static int apple_mbox_chan_startup(struct mbox_chan *chan)\n{\n\tstruct apple_mbox *apple_mbox = chan->con_priv;\n\n\t/*": "static int apple_mbox_chan_startup(struct mbox_chan *chan)\n{\n\tstruct apple_mbox *apple_mbox = chan->con_priv;\n\n\t/*\n\t * Only some variants of this mailbox HW provide interrupt control\n\t * at the mailbox level. We therefore need to handle enabling/disabling\n\t * interrupts at the main interrupt controller anyway for hardware that\n\t * doesn't. Just always keep the interrupts we care about enabled at\n\t * the mailbox level so that both hardware revisions behave almost\n\t * the same.\n\t */\n\tif (apple_mbox->hw->has_irq_controls) {\n\t\twritel_relaxed(apple_mbox->hw->irq_bit_recv_not_empty |\n\t\t\t\t       apple_mbox->hw->irq_bit_send_empty,\n\t\t\t       apple_mbox->regs + apple_mbox->hw->irq_enable);\n\t}\n\n\tenable_irq(apple_mbox->irq_recv_not_empty);\n\treturn 0;\n}",
        "static int pb0100_set_autogain_target(struct gspca_dev *gspca_dev, __s32 val)\n{\n\tint err, totalpixels, brightpixels, darkpixels;\n\tstruct sd *sd = (struct sd *) gspca_dev;\n": "static int pb0100_set_autogain_target(struct gspca_dev *gspca_dev, __s32 val)\n{\n\tint err, totalpixels, brightpixels, darkpixels;\n\tstruct sd *sd = (struct sd *) gspca_dev;\n\n\t/* Number of pixels counted by the sensor when subsampling the pixels.\n\t * Slightly larger than the real value to avoid oscillation */\n\ttotalpixels = gspca_dev->pixfmt.width * gspca_dev->pixfmt.height;\n\ttotalpixels = totalpixels/(8*8) + totalpixels/(64*64);\n\n\tbrightpixels = (totalpixels * val) >> 8;\n\tdarkpixels   = totalpixels - brightpixels;\n\terr = stv06xx_write_sensor(sd, PB_R21, brightpixels);\n\tif (!err)\n\t\terr = stv06xx_write_sensor(sd, PB_R22, darkpixels);\n\n\tgspca_dbg(gspca_dev, D_CONF, \"Set autogain target to %d, status: %d\\n\",\n\t\t  val, err);\n\n\treturn err;\n}",
        "static void bfq_dispatch_remove(struct request_queue *q, struct request *rq)\n{\n\tstruct bfq_queue *bfqq = RQ_BFQQ(rq);\n\n\t/*": "static void bfq_dispatch_remove(struct request_queue *q, struct request *rq)\n{\n\tstruct bfq_queue *bfqq = RQ_BFQQ(rq);\n\n\t/*\n\t * For consistency, the next instruction should have been\n\t * executed after removing the request from the queue and\n\t * dispatching it.  We execute instead this instruction before\n\t * bfq_remove_request() (and hence introduce a temporary\n\t * inconsistency), for efficiency.  In fact, should this\n\t * dispatch occur for a non in-service bfqq, this anticipated\n\t * increment prevents two counters related to bfqq->dispatched\n\t * from risking to be, first, uselessly decremented, and then\n\t * incremented again when the (new) value of bfqq->dispatched\n\t * happens to be taken into account.\n\t */\n\tbfqq->dispatched++;\n\tbfq_update_peak_rate(q->elevator->elevator_data, rq);\n\n\tbfq_remove_request(q, rq);\n}",
        "static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)\n{\n\tint current_rate;\n\tint rate_bits;\n\tint not_set = 0;": "static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)\n{\n\tint current_rate;\n\tint rate_bits;\n\tint not_set = 0;\n\tint current_speed, target_speed;\n\n\t/* ASSUMPTION: hdspm->lock is either set, or there is no need for\n\t   it (e.g. during module initialization).\n\t */\n\n\tif (!(hdspm->control_register & HDSPM_ClockModeMaster)) {\n\n\t\t/* SLAVE --- */\n\t\tif (called_internally) {\n\n\t\t\t/* request from ctl or card initialization\n\t\t\t   just make a warning an remember setting\n\t\t\t   for future master mode switching */\n\n\t\t\tdev_warn(hdspm->card->dev,\n\t\t\t\t \"Warning: device is not running as a clock master.\\n\");\n\t\t\tnot_set = 1;\n\t\t} else {\n\n\t\t\t/* hw_param request while in AutoSync mode */\n\t\t\tint external_freq =\n\t\t\t    hdspm_external_sample_rate(hdspm);\n\n\t\t\tif (hdspm_autosync_ref(hdspm) ==\n\t\t\t    HDSPM_AUTOSYNC_FROM_NONE) {\n\n\t\t\t\tdev_warn(hdspm->card->dev,\n\t\t\t\t\t \"Detected no External Sync\\n\");\n\t\t\t\tnot_set = 1;\n\n\t\t\t} else if (rate != external_freq) {\n\n\t\t\t\tdev_warn(hdspm->card->dev,\n\t\t\t\t\t \"Warning: No AutoSync source for requested rate\\n\");\n\t\t\t\tnot_set = 1;\n\t\t\t}\n\t\t}\n\t}\n\n\tcurrent_rate = hdspm->system_sample_rate;\n\n\t/* Changing between Singe, Double and Quad speed is not\n\t   allowed if any substreams are open. This is because such a change\n\t   causes a shift in the location of the DMA buffers and a reduction\n\t   in the number of available buffers.\n\n\t   Note that a similar but essentially insoluble problem exists for\n\t   externally-driven rate changes. All we can do is to flag rate\n\t   changes in the read/write routines.\n\t */\n\n\tif (current_rate <= 48000)\n\t\tcurrent_speed = HDSPM_SPEED_SINGLE;\n\telse if (current_rate <= 96000)\n\t\tcurrent_speed = HDSPM_SPEED_DOUBLE;\n\telse\n\t\tcurrent_speed = HDSPM_SPEED_QUAD;\n\n\tif (rate <= 48000)\n\t\ttarget_speed = HDSPM_SPEED_SINGLE;\n\telse if (rate <= 96000)\n\t\ttarget_speed = HDSPM_SPEED_DOUBLE;\n\telse\n\t\ttarget_speed = HDSPM_SPEED_QUAD;\n\n\tswitch (rate) {\n\tcase 32000:\n\t\trate_bits = HDSPM_Frequency32KHz;\n\t\tbreak;\n\tcase 44100:\n\t\trate_bits = HDSPM_Frequency44_1KHz;\n\t\tbreak;\n\tcase 48000:\n\t\trate_bits = HDSPM_Frequency48KHz;\n\t\tbreak;\n\tcase 64000:\n\t\trate_bits = HDSPM_Frequency64KHz;\n\t\tbreak;\n\tcase 88200:\n\t\trate_bits = HDSPM_Frequency88_2KHz;\n\t\tbreak;\n\tcase 96000:\n\t\trate_bits = HDSPM_Frequency96KHz;\n\t\tbreak;\n\tcase 128000:\n\t\trate_bits = HDSPM_Frequency128KHz;\n\t\tbreak;\n\tcase 176400:\n\t\trate_bits = HDSPM_Frequency176_4KHz;\n\t\tbreak;\n\tcase 192000:\n\t\trate_bits = HDSPM_Frequency192KHz;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tif (current_speed != target_speed\n\t    && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {\n\t\tdev_err(hdspm->card->dev,\n\t\t\t\"cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\\n\",\n\t\t\thdspm_speed_names[current_speed],\n\t\t\thdspm_speed_names[target_speed],\n\t\t\thdspm->capture_pid, hdspm->playback_pid);\n\t\treturn -EBUSY;\n\t}\n\n\thdspm->control_register &= ~HDSPM_FrequencyMask;\n\thdspm->control_register |= rate_bits;\n\thdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);\n\n\t/* For AES32, need to set DDS value in FREQ register\n\t   For MADI, also apparently */\n\thdspm_set_dds_value(hdspm, rate);\n\n\tif (AES32 == hdspm->io_type && rate != current_rate)\n\t\thdspm_write(hdspm, HDSPM_eeprom_wr, 0);\n\n\thdspm->system_sample_rate = rate;\n\n\tif (rate <= 48000) {\n\t\thdspm->channel_map_in = hdspm->channel_map_in_ss;\n\t\thdspm->channel_map_out = hdspm->channel_map_out_ss;\n\t\thdspm->max_channels_in = hdspm->ss_in_channels;\n\t\thdspm->max_channels_out = hdspm->ss_out_channels;\n\t\thdspm->port_names_in = hdspm->port_names_in_ss;\n\t\thdspm->port_names_out = hdspm->port_names_out_ss;\n\t} else if (rate <= 96000) {\n\t\thdspm->channel_map_in = hdspm->channel_map_in_ds;\n\t\thdspm->channel_map_out = hdspm->channel_map_out_ds;\n\t\thdspm->max_channels_in = hdspm->ds_in_channels;\n\t\thdspm->max_channels_out = hdspm->ds_out_channels;\n\t\thdspm->port_names_in = hdspm->port_names_in_ds;\n\t\thdspm->port_names_out = hdspm->port_names_out_ds;\n\t} else {\n\t\thdspm->channel_map_in = hdspm->channel_map_in_qs;\n\t\thdspm->channel_map_out = hdspm->channel_map_out_qs;\n\t\thdspm->max_channels_in = hdspm->qs_in_channels;\n\t\thdspm->max_channels_out = hdspm->qs_out_channels;\n\t\thdspm->port_names_in = hdspm->port_names_in_qs;\n\t\thdspm->port_names_out = hdspm->port_names_out_qs;\n\t}\n\n\tif (not_set != 0)\n\t\treturn -1;\n\n\treturn 0;\n}",
        "static int mtip_block_initialize(struct driver_data *dd)\n{\n\tint rv = 0, wait_for_rebuild = 0;\n\tsector_t capacity;\n\tunsigned int index = 0;": "static int mtip_block_initialize(struct driver_data *dd)\n{\n\tint rv = 0, wait_for_rebuild = 0;\n\tsector_t capacity;\n\tunsigned int index = 0;\n\n\tif (dd->disk)\n\t\tgoto skip_create_disk; /* hw init done, before rebuild */\n\n\tif (mtip_hw_init(dd)) {\n\t\trv = -EINVAL;\n\t\tgoto protocol_init_error;\n\t}\n\n\tmemset(&dd->tags, 0, sizeof(dd->tags));\n\tdd->tags.ops = &mtip_mq_ops;\n\tdd->tags.nr_hw_queues = 1;\n\tdd->tags.queue_depth = MTIP_MAX_COMMAND_SLOTS;\n\tdd->tags.reserved_tags = 1;\n\tdd->tags.cmd_size = sizeof(struct mtip_cmd);\n\tdd->tags.numa_node = dd->numa_node;\n\tdd->tags.flags = BLK_MQ_F_SHOULD_MERGE;\n\tdd->tags.driver_data = dd;\n\tdd->tags.timeout = MTIP_NCQ_CMD_TIMEOUT_MS;\n\n\trv = blk_mq_alloc_tag_set(&dd->tags);\n\tif (rv) {\n\t\tdev_err(&dd->pdev->dev,\n\t\t\t\"Unable to allocate request queue\\n\");\n\t\tgoto block_queue_alloc_tag_error;\n\t}\n\n\tdd->disk = blk_mq_alloc_disk(&dd->tags, dd);\n\tif (IS_ERR(dd->disk)) {\n\t\tdev_err(&dd->pdev->dev,\n\t\t\t\"Unable to allocate request queue\\n\");\n\t\trv = -ENOMEM;\n\t\tgoto block_queue_alloc_init_error;\n\t}\n\tdd->queue\t\t= dd->disk->queue;\n\n\trv = ida_alloc(&rssd_index_ida, GFP_KERNEL);\n\tif (rv < 0)\n\t\tgoto ida_get_error;\n\tindex = rv;\n\n\trv = rssd_disk_name_format(\"rssd\",\n\t\t\t\tindex,\n\t\t\t\tdd->disk->disk_name,\n\t\t\t\tDISK_NAME_LEN);\n\tif (rv)\n\t\tgoto disk_index_error;\n\n\tdd->disk->major\t\t= dd->major;\n\tdd->disk->first_minor\t= index * MTIP_MAX_MINORS;\n\tdd->disk->minors \t= MTIP_MAX_MINORS;\n\tdd->disk->fops\t\t= &mtip_block_ops;\n\tdd->disk->private_data\t= dd;\n\tdd->index\t\t= index;\n\n\tmtip_hw_debugfs_init(dd);\n\nskip_create_disk:\n\t/* Initialize the protocol layer. */\n\twait_for_rebuild = mtip_hw_get_identify(dd);\n\tif (wait_for_rebuild < 0) {\n\t\tdev_err(&dd->pdev->dev,\n\t\t\t\"Protocol layer initialization failed\\n\");\n\t\trv = -EINVAL;\n\t\tgoto init_hw_cmds_error;\n\t}\n\n\t/*\n\t * if rebuild pending, start the service thread, and delay the block\n\t * queue creation and device_add_disk()\n\t */\n\tif (wait_for_rebuild == MTIP_FTL_REBUILD_MAGIC)\n\t\tgoto start_service_thread;\n\n\t/* Set device limits. */\n\tblk_queue_flag_set(QUEUE_FLAG_NONROT, dd->queue);\n\tblk_queue_flag_clear(QUEUE_FLAG_ADD_RANDOM, dd->queue);\n\tblk_queue_max_segments(dd->queue, MTIP_MAX_SG);\n\tblk_queue_physical_block_size(dd->queue, 4096);\n\tblk_queue_max_hw_sectors(dd->queue, 0xffff);\n\tblk_queue_max_segment_size(dd->queue, 0x400000);\n\tdma_set_max_seg_size(&dd->pdev->dev, 0x400000);\n\tblk_queue_io_min(dd->queue, 4096);\n\n\t/* Set the capacity of the device in 512 byte sectors. */\n\tif (!(mtip_hw_get_capacity(dd, &capacity))) {\n\t\tdev_warn(&dd->pdev->dev,\n\t\t\t\"Could not read drive capacity\\n\");\n\t\trv = -EIO;\n\t\tgoto read_capacity_error;\n\t}\n\tset_capacity(dd->disk, capacity);\n\n\t/* Enable the block device and add it to /dev */\n\trv = device_add_disk(&dd->pdev->dev, dd->disk, mtip_disk_attr_groups);\n\tif (rv)\n\t\tgoto read_capacity_error;\n\n\tif (dd->mtip_svc_handler) {\n\t\tset_bit(MTIP_DDF_INIT_DONE_BIT, &dd->dd_flag);\n\t\treturn rv; /* service thread created for handling rebuild */\n\t}\n\nstart_service_thread:\n\tdd->mtip_svc_handler = kthread_create_on_node(mtip_service_thread,\n\t\t\t\t\t\tdd, dd->numa_node,\n\t\t\t\t\t\t\"mtip_svc_thd_%02d\", index);\n\n\tif (IS_ERR(dd->mtip_svc_handler)) {\n\t\tdev_err(&dd->pdev->dev, \"service thread failed to start\\n\");\n\t\tdd->mtip_svc_handler = NULL;\n\t\trv = -EFAULT;\n\t\tgoto kthread_run_error;\n\t}\n\twake_up_process(dd->mtip_svc_handler);\n\tif (wait_for_rebuild == MTIP_FTL_REBUILD_MAGIC)\n\t\trv = wait_for_rebuild;\n\n\treturn rv;\n\nkthread_run_error:\n\t/* Delete our gendisk. This also removes the device from /dev */\n\tdel_gendisk(dd->disk);\nread_capacity_error:\ninit_hw_cmds_error:\n\tmtip_hw_debugfs_exit(dd);\ndisk_index_error:\n\tida_free(&rssd_index_ida, index);\nida_get_error:\n\tblk_cleanup_disk(dd->disk);\nblock_queue_alloc_init_error:\n\tblk_mq_free_tag_set(&dd->tags);\nblock_queue_alloc_tag_error:\n\tmtip_hw_exit(dd); /* De-initialize the protocol layer. */\nprotocol_init_error:\n\treturn rv;\n}",
        "static bool copy_data(struct channel *channel, struct mbo *mbo)\n{\n\tstruct snd_pcm_runtime *const runtime = channel->substream->runtime;\n\tunsigned int const frame_bytes = channel->cfg->subbuffer_size;\n\tunsigned int const buffer_size = runtime->buffer_size;": "static bool copy_data(struct channel *channel, struct mbo *mbo)\n{\n\tstruct snd_pcm_runtime *const runtime = channel->substream->runtime;\n\tunsigned int const frame_bytes = channel->cfg->subbuffer_size;\n\tunsigned int const buffer_size = runtime->buffer_size;\n\tunsigned int frames;\n\tunsigned int fr0;\n\n\tif (channel->cfg->direction & MOST_CH_RX)\n\t\tframes = mbo->processed_length / frame_bytes;\n\telse\n\t\tframes = mbo->buffer_length / frame_bytes;\n\tfr0 = min(buffer_size - channel->buffer_pos, frames);\n\n\tchannel->copy_fn(runtime->dma_area + channel->buffer_pos * frame_bytes,\n\t\t\t mbo->virt_address,\n\t\t\t fr0 * frame_bytes);\n\n\tif (frames > fr0) {\n\t\t/* wrap around at end of ring buffer */\n\t\tchannel->copy_fn(runtime->dma_area,\n\t\t\t\t mbo->virt_address + fr0 * frame_bytes,\n\t\t\t\t (frames - fr0) * frame_bytes);\n\t}\n\n\tchannel->buffer_pos += frames;\n\tif (channel->buffer_pos >= buffer_size)\n\t\tchannel->buffer_pos -= buffer_size;\n\tchannel->period_pos += frames;\n\tif (channel->period_pos >= runtime->period_size) {\n\t\tchannel->period_pos -= runtime->period_size;\n\t\treturn true;\n\t}\n\treturn false;\n}",
        "static void __mptcp_check_send_data_fin(struct sock *sk)\n{\n\tstruct mptcp_subflow_context *subflow;\n\tstruct mptcp_sock *msk = mptcp_sk(sk);\n": "static void __mptcp_check_send_data_fin(struct sock *sk)\n{\n\tstruct mptcp_subflow_context *subflow;\n\tstruct mptcp_sock *msk = mptcp_sk(sk);\n\n\tpr_debug(\"msk=%p snd_data_fin_enable=%d pending=%d snd_nxt=%llu write_seq=%llu\",\n\t\t msk, msk->snd_data_fin_enable, !!mptcp_send_head(sk),\n\t\t msk->snd_nxt, msk->write_seq);\n\n\t/* we still need to enqueue subflows or not really shutting down,\n\t * skip this\n\t */\n\tif (!msk->snd_data_fin_enable || msk->snd_nxt + 1 != msk->write_seq ||\n\t    mptcp_send_head(sk))\n\t\treturn;\n\n\tWRITE_ONCE(msk->snd_nxt, msk->write_seq);\n\n\t/* fallback socket will not get data_fin/ack, can move to the next\n\t * state now\n\t */\n\tif (__mptcp_check_fallback(msk)) {\n\t\tWRITE_ONCE(msk->snd_una, msk->write_seq);\n\t\tif ((1 << sk->sk_state) & (TCPF_CLOSING | TCPF_LAST_ACK)) {\n\t\t\tinet_sk_state_store(sk, TCP_CLOSE);\n\t\t\tmptcp_close_wake_up(sk);\n\t\t} else if (sk->sk_state == TCP_FIN_WAIT1) {\n\t\t\tinet_sk_state_store(sk, TCP_FIN_WAIT2);\n\t\t}\n\t}\n\n\tmptcp_for_each_subflow(msk, subflow) {\n\t\tstruct sock *tcp_sk = mptcp_subflow_tcp_sock(subflow);\n\n\t\tmptcp_subflow_shutdown(sk, tcp_sk, SEND_SHUTDOWN);\n\t}\n}",
        "static void tcp_update_pacing_rate(struct sock *sk)\n{\n\tconst struct tcp_sock *tp = tcp_sk(sk);\n\tu64 rate;\n": "static void tcp_update_pacing_rate(struct sock *sk)\n{\n\tconst struct tcp_sock *tp = tcp_sk(sk);\n\tu64 rate;\n\n\t/* set sk_pacing_rate to 200 % of current rate (mss * cwnd / srtt) */\n\trate = (u64)tp->mss_cache * ((USEC_PER_SEC / 100) << 3);\n\n\t/* current rate is (cwnd * mss) / srtt\n\t * In Slow Start [1], set sk_pacing_rate to 200 % the current rate.\n\t * In Congestion Avoidance phase, set it to 120 % the current rate.\n\t *\n\t * [1] : Normal Slow Start condition is (tp->snd_cwnd < tp->snd_ssthresh)\n\t *\t If snd_cwnd >= (tp->snd_ssthresh / 2), we are approaching\n\t *\t end of slow start and should slow down.\n\t */\n\tif (tcp_snd_cwnd(tp) < tp->snd_ssthresh / 2)\n\t\trate *= sock_net(sk)->ipv4.sysctl_tcp_pacing_ss_ratio;\n\telse\n\t\trate *= sock_net(sk)->ipv4.sysctl_tcp_pacing_ca_ratio;\n\n\trate *= max(tcp_snd_cwnd(tp), tp->packets_out);\n\n\tif (likely(tp->srtt_us))\n\t\tdo_div(rate, tp->srtt_us);\n\n\t/* WRITE_ONCE() is needed because sch_fq fetches sk_pacing_rate\n\t * without any lock. We want to make sure compiler wont store\n\t * intermediate values in this location.\n\t */\n\tWRITE_ONCE(sk->sk_pacing_rate, min_t(u64, rate,\n\t\t\t\t\t     sk->sk_max_pacing_rate));\n}",
        "static void srcu_gp_end(struct srcu_struct *ssp)\n{\n\tunsigned long cbdelay;\n\tbool cbs;\n\tbool last_lvl;": "static void srcu_gp_end(struct srcu_struct *ssp)\n{\n\tunsigned long cbdelay;\n\tbool cbs;\n\tbool last_lvl;\n\tint cpu;\n\tunsigned long flags;\n\tunsigned long gpseq;\n\tint idx;\n\tunsigned long mask;\n\tstruct srcu_data *sdp;\n\tunsigned long sgsne;\n\tstruct srcu_node *snp;\n\tint ss_state;\n\n\t/* Prevent more than one additional grace period. */\n\tmutex_lock(&ssp->srcu_cb_mutex);\n\n\t/* End the current grace period. */\n\tspin_lock_irq_rcu_node(ssp);\n\tidx = rcu_seq_state(ssp->srcu_gp_seq);\n\tWARN_ON_ONCE(idx != SRCU_STATE_SCAN2);\n\tcbdelay = !!srcu_get_delay(ssp);\n\tWRITE_ONCE(ssp->srcu_last_gp_end, ktime_get_mono_fast_ns());\n\trcu_seq_end(&ssp->srcu_gp_seq);\n\tgpseq = rcu_seq_current(&ssp->srcu_gp_seq);\n\tif (ULONG_CMP_LT(ssp->srcu_gp_seq_needed_exp, gpseq))\n\t\tWRITE_ONCE(ssp->srcu_gp_seq_needed_exp, gpseq);\n\tspin_unlock_irq_rcu_node(ssp);\n\tmutex_unlock(&ssp->srcu_gp_mutex);\n\t/* A new grace period can start at this point.  But only one. */\n\n\t/* Initiate callback invocation as needed. */\n\tss_state = smp_load_acquire(&ssp->srcu_size_state);\n\tif (ss_state < SRCU_SIZE_WAIT_BARRIER) {\n\t\tsrcu_schedule_cbs_sdp(per_cpu_ptr(ssp->sda, 0), cbdelay);\n\t} else {\n\t\tidx = rcu_seq_ctr(gpseq) % ARRAY_SIZE(snp->srcu_have_cbs);\n\t\tsrcu_for_each_node_breadth_first(ssp, snp) {\n\t\t\tspin_lock_irq_rcu_node(snp);\n\t\t\tcbs = false;\n\t\t\tlast_lvl = snp >= ssp->level[rcu_num_lvls - 1];\n\t\t\tif (last_lvl)\n\t\t\t\tcbs = ss_state < SRCU_SIZE_BIG || snp->srcu_have_cbs[idx] == gpseq;\n\t\t\tsnp->srcu_have_cbs[idx] = gpseq;\n\t\t\trcu_seq_set_state(&snp->srcu_have_cbs[idx], 1);\n\t\t\tsgsne = snp->srcu_gp_seq_needed_exp;\n\t\t\tif (srcu_invl_snp_seq(sgsne) || ULONG_CMP_LT(sgsne, gpseq))\n\t\t\t\tWRITE_ONCE(snp->srcu_gp_seq_needed_exp, gpseq);\n\t\t\tif (ss_state < SRCU_SIZE_BIG)\n\t\t\t\tmask = ~0;\n\t\t\telse\n\t\t\t\tmask = snp->srcu_data_have_cbs[idx];\n\t\t\tsnp->srcu_data_have_cbs[idx] = 0;\n\t\t\tspin_unlock_irq_rcu_node(snp);\n\t\t\tif (cbs)\n\t\t\t\tsrcu_schedule_cbs_snp(ssp, snp, mask, cbdelay);\n\t\t}\n\t}\n\n\t/* Occasionally prevent srcu_data counter wrap. */\n\tif (!(gpseq & counter_wrap_check))\n\t\tfor_each_possible_cpu(cpu) {\n\t\t\tsdp = per_cpu_ptr(ssp->sda, cpu);\n\t\t\tspin_lock_irqsave_rcu_node(sdp, flags);\n\t\t\tif (ULONG_CMP_GE(gpseq, sdp->srcu_gp_seq_needed + 100))\n\t\t\t\tsdp->srcu_gp_seq_needed = gpseq;\n\t\t\tif (ULONG_CMP_GE(gpseq, sdp->srcu_gp_seq_needed_exp + 100))\n\t\t\t\tsdp->srcu_gp_seq_needed_exp = gpseq;\n\t\t\tspin_unlock_irqrestore_rcu_node(sdp, flags);\n\t\t}\n\n\t/* Callback initiation done, allow grace periods after next. */\n\tmutex_unlock(&ssp->srcu_cb_mutex);\n\n\t/* Start a new grace period if needed. */\n\tspin_lock_irq_rcu_node(ssp);\n\tgpseq = rcu_seq_current(&ssp->srcu_gp_seq);\n\tif (!rcu_seq_state(gpseq) &&\n\t    ULONG_CMP_LT(gpseq, ssp->srcu_gp_seq_needed)) {\n\t\tsrcu_gp_start(ssp);\n\t\tspin_unlock_irq_rcu_node(ssp);\n\t\tsrcu_reschedule(ssp, 0);\n\t} else {\n\t\tspin_unlock_irq_rcu_node(ssp);\n\t}\n\n\t/* Transition to big if needed. */\n\tif (ss_state != SRCU_SIZE_SMALL && ss_state != SRCU_SIZE_BIG) {\n\t\tif (ss_state == SRCU_SIZE_ALLOC)\n\t\t\tinit_srcu_struct_nodes(ssp, GFP_KERNEL);\n\t\telse\n\t\t\tsmp_store_release(&ssp->srcu_size_state, ss_state + 1);\n\t}\n}",
        "static int vdec_output_conf(struct venus_inst *inst)\n{\n\tstruct venus_core *core = inst->core;\n\tstruct hfi_enable en = { .enable = 1 };\n\tstruct hfi_buffer_requirements bufreq;": "static int vdec_output_conf(struct venus_inst *inst)\n{\n\tstruct venus_core *core = inst->core;\n\tstruct hfi_enable en = { .enable = 1 };\n\tstruct hfi_buffer_requirements bufreq;\n\tu32 width = inst->width;\n\tu32 height = inst->height;\n\tu32 out_fmt, out2_fmt;\n\tbool ubwc = false;\n\tu32 ptype;\n\tint ret;\n\n\tret = venus_helper_set_work_mode(inst);\n\tif (ret)\n\t\treturn ret;\n\n\tif (core->res->hfi_version == HFI_VERSION_1XX) {\n\t\tptype = HFI_PROPERTY_PARAM_VDEC_CONTINUE_DATA_TRANSFER;\n\t\tret = hfi_session_set_property(inst, ptype, &en);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\t/* Force searching UBWC formats for bigger then HD resolutions */\n\tif (width > 1920 && height > ALIGN(1080, 32))\n\t\tubwc = true;\n\n\t/* For Venus v4/v6 UBWC format is mandatory */\n\tif (IS_V4(core) || IS_V6(core))\n\t\tubwc = true;\n\n\tret = venus_helper_get_out_fmts(inst, inst->fmt_cap->pixfmt, &out_fmt,\n\t\t\t\t\t&out2_fmt, ubwc);\n\tif (ret)\n\t\treturn ret;\n\n\tinst->output_buf_size =\n\t\t\tvenus_helper_get_framesz_raw(out_fmt, width, height);\n\tinst->output2_buf_size =\n\t\t\tvenus_helper_get_framesz_raw(out2_fmt, width, height);\n\n\tif (is_ubwc_fmt(out_fmt)) {\n\t\tinst->opb_buftype = HFI_BUFFER_OUTPUT2;\n\t\tinst->opb_fmt = out2_fmt;\n\t\tinst->dpb_buftype = HFI_BUFFER_OUTPUT;\n\t\tinst->dpb_fmt = out_fmt;\n\t} else if (is_ubwc_fmt(out2_fmt)) {\n\t\tinst->opb_buftype = HFI_BUFFER_OUTPUT;\n\t\tinst->opb_fmt = out_fmt;\n\t\tinst->dpb_buftype = HFI_BUFFER_OUTPUT2;\n\t\tinst->dpb_fmt = out2_fmt;\n\t} else {\n\t\tinst->opb_buftype = HFI_BUFFER_OUTPUT;\n\t\tinst->opb_fmt = out_fmt;\n\t\tinst->dpb_buftype = 0;\n\t\tinst->dpb_fmt = 0;\n\t}\n\n\tret = venus_helper_set_raw_format(inst, inst->opb_fmt,\n\t\t\t\t\t  inst->opb_buftype);\n\tif (ret)\n\t\treturn ret;\n\n\tret = venus_helper_set_format_constraints(inst);\n\tif (ret)\n\t\treturn ret;\n\n\tif (inst->dpb_fmt) {\n\t\tret = venus_helper_set_multistream(inst, false, true);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = venus_helper_set_raw_format(inst, inst->dpb_fmt,\n\t\t\t\t\t\t  inst->dpb_buftype);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = venus_helper_set_output_resolution(inst, width, height,\n\t\t\t\t\t\t\t HFI_BUFFER_OUTPUT2);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tif (IS_V3(core) || IS_V4(core) || IS_V6(core)) {\n\t\tret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tif (bufreq.size > inst->output_buf_size)\n\t\t\treturn -EINVAL;\n\n\t\tif (inst->dpb_fmt) {\n\t\t\tret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT2,\n\t\t\t\t\t\t      &bufreq);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\n\t\t\tif (bufreq.size > inst->output2_buf_size)\n\t\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (inst->output2_buf_size) {\n\t\t\tret = venus_helper_set_bufsize(inst,\n\t\t\t\t\t\t       inst->output2_buf_size,\n\t\t\t\t\t\t       HFI_BUFFER_OUTPUT2);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\t\t}\n\n\t\tif (inst->output_buf_size) {\n\t\t\tret = venus_helper_set_bufsize(inst,\n\t\t\t\t\t\t       inst->output_buf_size,\n\t\t\t\t\t\t       HFI_BUFFER_OUTPUT);\n\t\t\tif (ret)\n\t\t\t\treturn ret;\n\t\t}\n\t}\n\n\tret = venus_helper_set_dyn_bufmode(inst);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}",
        "static int trigger_bulk_read(struct w1_master *dev_master)\n{\n\tstruct w1_slave *sl = NULL; /* used to iterate through slaves */\n\tint max_trying = W1_THERM_MAX_TRY;\n\tint t_conv = 0;": "static int trigger_bulk_read(struct w1_master *dev_master)\n{\n\tstruct w1_slave *sl = NULL; /* used to iterate through slaves */\n\tint max_trying = W1_THERM_MAX_TRY;\n\tint t_conv = 0;\n\tint ret = -ENODEV;\n\tbool strong_pullup = false;\n\n\t/*\n\t * Check whether there are parasite powered device on the bus,\n\t * and compute duration of conversion for these devices\n\t * so we can apply a strong pullup if required\n\t */\n\tlist_for_each_entry(sl, &dev_master->slist, w1_slave_entry) {\n\t\tif (!sl->family_data)\n\t\t\tgoto error;\n\t\tif (bulk_read_support(sl)) {\n\t\t\tint t_cur = conversion_time(sl);\n\n\t\t\tt_conv = t_cur > t_conv ? t_cur : t_conv;\n\t\t\tstrong_pullup = strong_pullup ||\n\t\t\t\t\t(w1_strong_pullup == 2 ||\n\t\t\t\t\t(!SLAVE_POWERMODE(sl) &&\n\t\t\t\t\tw1_strong_pullup));\n\t\t}\n\t}\n\n\t/*\n\t * t_conv is the max conversion time required on the bus\n\t * If its 0, no device support the bulk read feature\n\t */\n\tif (!t_conv)\n\t\tgoto error;\n\n\tif (!bus_mutex_lock(&dev_master->bus_mutex)) {\n\t\tret = -EAGAIN;\t/* Didn't acquire the mutex */\n\t\tgoto error;\n\t}\n\n\twhile ((max_trying--) && (ret < 0)) { /* ret should be either 0 */\n\n\t\tif (!w1_reset_bus(dev_master)) {\t/* Just reset the bus */\n\t\t\tunsigned long sleep_rem;\n\n\t\t\tw1_write_8(dev_master, W1_SKIP_ROM);\n\n\t\t\tif (strong_pullup)\t/* Apply pullup if required */\n\t\t\t\tw1_next_pullup(dev_master, t_conv);\n\n\t\t\tw1_write_8(dev_master, W1_CONVERT_TEMP);\n\n\t\t\t/* set a flag to instruct that converT pending */\n\t\t\tlist_for_each_entry(sl,\n\t\t\t\t&dev_master->slist, w1_slave_entry) {\n\t\t\t\tif (bulk_read_support(sl))\n\t\t\t\t\tSLAVE_CONVERT_TRIGGERED(sl) = -1;\n\t\t\t}\n\n\t\t\tif (strong_pullup) { /* some device need pullup */\n\t\t\t\tsleep_rem = msleep_interruptible(t_conv);\n\t\t\t\tif (sleep_rem != 0) {\n\t\t\t\t\tret = -EINTR;\n\t\t\t\t\tgoto mt_unlock;\n\t\t\t\t}\n\t\t\t\tmutex_unlock(&dev_master->bus_mutex);\n\t\t\t} else {\n\t\t\t\tmutex_unlock(&dev_master->bus_mutex);\n\t\t\t\tsleep_rem = msleep_interruptible(t_conv);\n\t\t\t\tif (sleep_rem != 0) {\n\t\t\t\t\tret = -EINTR;\n\t\t\t\t\tgoto set_flag;\n\t\t\t\t}\n\t\t\t}\n\t\t\tret = 0;\n\t\t\tgoto set_flag;\n\t\t}\n\t}\n\nmt_unlock:\n\tmutex_unlock(&dev_master->bus_mutex);\nset_flag:\n\t/* set a flag to register convsersion is done */\n\tlist_for_each_entry(sl, &dev_master->slist, w1_slave_entry) {\n\t\tif (bulk_read_support(sl))\n\t\t\tSLAVE_CONVERT_TRIGGERED(sl) = 1;\n\t}\nerror:\n\treturn ret;\n}",
        "static void pex_ep_event_hot_rst_done(struct tegra194_pcie *pcie)\n{\n\tu32 val;\n\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);": "static void pex_ep_event_hot_rst_done(struct tegra194_pcie *pcie)\n{\n\tu32 val;\n\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);\n\tappl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);\n\n\tval = appl_readl(pcie, APPL_CTRL);\n\tval |= APPL_CTRL_LTSSM_EN;\n\tappl_writel(pcie, val, APPL_CTRL);\n}",
        "static int cnic_start_bnx2_hw(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_eth_dev *ethdev = cp->ethdev;\n\tstruct status_block *sblk = cp->status_blk.gen;": "static int cnic_start_bnx2_hw(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tstruct cnic_eth_dev *ethdev = cp->ethdev;\n\tstruct status_block *sblk = cp->status_blk.gen;\n\tu32 val, kcq_cid_addr, kwq_cid_addr;\n\tint err;\n\n\tcnic_set_bnx2_mac(dev);\n\n\tval = CNIC_RD(dev, BNX2_MQ_CONFIG);\n\tval &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;\n\tif (CNIC_PAGE_BITS > 12)\n\t\tval |= (12 - 8)  << 4;\n\telse\n\t\tval |= (CNIC_PAGE_BITS - 8)  << 4;\n\n\tCNIC_WR(dev, BNX2_MQ_CONFIG, val);\n\n\tCNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);\n\tCNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);\n\tCNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);\n\n\terr = cnic_setup_5709_context(dev, 1);\n\tif (err)\n\t\treturn err;\n\n\tcnic_init_context(dev, KWQ_CID);\n\tcnic_init_context(dev, KCQ_CID);\n\n\tkwq_cid_addr = GET_CID_ADDR(KWQ_CID);\n\tcp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;\n\n\tcp->max_kwq_idx = MAX_KWQ_IDX;\n\tcp->kwq_prod_idx = 0;\n\tcp->kwq_con_idx = 0;\n\tset_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);\n\n\tif (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)\n\t\tcp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;\n\telse\n\t\tcp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;\n\n\t/* Initialize the kernel work queue context. */\n\tval = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |\n\t      (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;\n\tcnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);\n\n\tval = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;\n\tcnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);\n\n\tval = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;\n\tcnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);\n\n\tval = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);\n\tcnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);\n\n\tval = (u32) cp->kwq_info.pgtbl_map;\n\tcnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);\n\n\tkcq_cid_addr = GET_CID_ADDR(KCQ_CID);\n\tcp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;\n\n\tcp->kcq1.sw_prod_idx = 0;\n\tcp->kcq1.hw_prod_idx_ptr =\n\t\t&sblk->status_completion_producer_index;\n\n\tcp->kcq1.status_idx_ptr = &sblk->status_idx;\n\n\t/* Initialize the kernel complete queue context. */\n\tval = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |\n\t      (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;\n\tcnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);\n\n\tval = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;\n\tcnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);\n\n\tval = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;\n\tcnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);\n\n\tval = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);\n\tcnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);\n\n\tval = (u32) cp->kcq1.dma.pgtbl_map;\n\tcnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);\n\n\tcp->int_num = 0;\n\tif (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {\n\t\tstruct status_block_msix *msblk = cp->status_blk.bnx2;\n\t\tu32 sb_id = cp->status_blk_num;\n\t\tu32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);\n\n\t\tcp->kcq1.hw_prod_idx_ptr =\n\t\t\t&msblk->status_completion_producer_index;\n\t\tcp->kcq1.status_idx_ptr = &msblk->status_idx;\n\t\tcp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;\n\t\tcp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;\n\t\tcnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);\n\t\tcnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);\n\t}\n\n\t/* Enable Commnad Scheduler notification when we write to the\n\t * host producer index of the kernel contexts. */\n\tCNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);\n\n\t/* Enable Command Scheduler notification when we write to either\n\t * the Send Queue or Receive Queue producer indexes of the kernel\n\t * bypass contexts. */\n\tCNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);\n\tCNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);\n\n\t/* Notify COM when the driver post an application buffer. */\n\tCNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);\n\n\t/* Set the CP and COM doorbells.  These two processors polls the\n\t * doorbell for a non zero value before running.  This must be done\n\t * after setting up the kernel queue contexts. */\n\tcnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);\n\tcnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);\n\n\tcnic_init_bnx2_tx_ring(dev);\n\tcnic_init_bnx2_rx_ring(dev);\n\n\terr = cnic_init_bnx2_irq(dev);\n\tif (err) {\n\t\tnetdev_err(dev->netdev, \"cnic_init_irq failed\\n\");\n\t\tcnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);\n\t\tcnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);\n\t\treturn err;\n\t}\n\n\tethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;\n\n\treturn 0;\n}",
        "static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)\n{\n\tuint16_t word = byte;\n\n\t/*": "static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)\n{\n\tuint16_t word = byte;\n\n\t/*\n\t * It's not entirely clear what should happen to I/O[15:8] when writing\n\t * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:\n\t *\n\t *    When the host supports a 16-bit bus width, only data is\n\t *    transferred at the 16-bit width. All address and command line\n\t *    transfers shall use only the lower 8-bits of the data bus. During\n\t *    command transfers, the host may place any value on the upper\n\t *    8-bits of the data bus. During address transfers, the host shall\n\t *    set the upper 8-bits of the data bus to 00h.\n\t *\n\t * One user of the write_byte callback is nand_set_features. The\n\t * four parameters are specified to be written to I/O[7:0], but this is\n\t * neither an address nor a command transfer. Let's assume a 0 on the\n\t * upper I/O lines is OK.\n\t */\n\tchip->legacy.write_buf(chip, (uint8_t *)&word, 2);\n}",
        "static void t7xx_dpmaif_dl_all_q_en(struct dpmaif_hw_info *hw_info, bool enable)\n{\n\tu32 dl_bat_init, value;\n\tint timeout;\n": "static void t7xx_dpmaif_dl_all_q_en(struct dpmaif_hw_info *hw_info, bool enable)\n{\n\tu32 dl_bat_init, value;\n\tint timeout;\n\n\tvalue = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);\n\n\tif (enable)\n\t\tvalue |= DPMAIF_BAT_EN_MSK;\n\telse\n\t\tvalue &= ~DPMAIF_BAT_EN_MSK;\n\n\tiowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);\n\tdl_bat_init = DPMAIF_DL_BAT_INIT_ONLY_ENABLE_BIT;\n\tdl_bat_init |= DPMAIF_DL_BAT_INIT_EN;\n\n\ttimeout = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT,\n\t\t\t\t\t       value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,\n\t\t\t\t\t       DPMAIF_CHECK_TIMEOUT_US);\n\tif (timeout)\n\t\tdev_err(hw_info->dev, \"Timeout updating BAT setting to HW\\n\");\n\n\tiowrite32(dl_bat_init, hw_info->pcie_base + DPMAIF_DL_BAT_INIT);\n\ttimeout = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT,\n\t\t\t\t\t       value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,\n\t\t\t\t\t       DPMAIF_CHECK_TIMEOUT_US);\n\tif (timeout)\n\t\tdev_err(hw_info->dev, \"Data plane modem DL BAT is not ready\\n\");\n}",
        "static void ccp5other_config(struct ccp_device *ccp)\n{\n\tint i;\n\tu32 rnd;\n": "static void ccp5other_config(struct ccp_device *ccp)\n{\n\tint i;\n\tu32 rnd;\n\n\t/* We own all of the queues on the NTB CCP */\n\n\tiowrite32(0x00012D57, ccp->io_regs + CMD5_TRNG_CTL_OFFSET);\n\tiowrite32(0x00000003, ccp->io_regs + CMD5_CONFIG_0_OFFSET);\n\tfor (i = 0; i < 12; i++) {\n\t\trnd = ioread32(ccp->io_regs + TRNG_OUT_REG);\n\t\tiowrite32(rnd, ccp->io_regs + CMD5_AES_MASK_OFFSET);\n\t}\n\n\tiowrite32(0x0000001F, ccp->io_regs + CMD5_QUEUE_MASK_OFFSET);\n\tiowrite32(0x00005B6D, ccp->io_regs + CMD5_QUEUE_PRIO_OFFSET);\n\tiowrite32(0x00000000, ccp->io_regs + CMD5_CMD_TIMEOUT_OFFSET);\n\n\tiowrite32(0x3FFFFFFF, ccp->io_regs + LSB_PRIVATE_MASK_LO_OFFSET);\n\tiowrite32(0x000003FF, ccp->io_regs + LSB_PRIVATE_MASK_HI_OFFSET);\n\n\tiowrite32(0x00108823, ccp->io_regs + CMD5_CLK_GATE_CTL_OFFSET);\n\n\tccp5_config(ccp);\n}",
        "static void vnt_rxtx_ab(struct vnt_usb_send_context *tx_context)\n{\n\tstruct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_context->skb);\n\tstruct vnt_tx_buffer *tx_buffer = tx_context->tx_buffer;\n\tunion vnt_tx_head *tx_head = &tx_buffer->tx_head;": "static void vnt_rxtx_ab(struct vnt_usb_send_context *tx_context)\n{\n\tstruct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_context->skb);\n\tstruct vnt_tx_buffer *tx_buffer = tx_context->tx_buffer;\n\tunion vnt_tx_head *tx_head = &tx_buffer->tx_head;\n\tstruct vnt_rrv_time_ab *buf = &tx_head->tx_ab.ab;\n\tunion vnt_tx_data_head *head = &tx_head->tx_ab.tx.head;\n\n\tbuf->rrv_time = vnt_rxtx_rsvtime_le16(tx_context);\n\n\tif (info->control.hw_key) {\n\t\tif (vnt_fill_txkey(tx_buffer, tx_context->skb))\n\t\t\thead = &tx_head->tx_ab.tx.mic.head;\n\t}\n\n\tif (info->control.use_rts) {\n\t\tbuf->rts_rrv_time = vnt_get_rts_duration(tx_context);\n\n\t\tvnt_rxtx_rts_ab_head(tx_context, &head->rts_ab);\n\n\t\treturn;\n\t}\n\n\tvnt_rxtx_datahead_ab(tx_context, &head->data_head_ab);\n}",
        "static int mac_sonic_nubus_probe(struct nubus_board *board)\n{\n\tstruct net_device *ndev;\n\tstruct sonic_local *lp;\n\tstruct nubus_rsrc *fres;": "static int mac_sonic_nubus_probe(struct nubus_board *board)\n{\n\tstruct net_device *ndev;\n\tstruct sonic_local *lp;\n\tstruct nubus_rsrc *fres;\n\tint id = -1;\n\tint err;\n\n\t/* The platform driver will handle a PDS or Comm Slot card (even if\n\t * it has a pseudoslot declaration ROM).\n\t */\n\tif (macintosh_config->expansion_type == MAC_EXP_PDS_COMM)\n\t\treturn -ENODEV;\n\n\tfor_each_board_func_rsrc(board, fres) {\n\t\tif (fres->category != NUBUS_CAT_NETWORK ||\n\t\t    fres->type != NUBUS_TYPE_ETHERNET)\n\t\t\tcontinue;\n\n\t\tid = macsonic_ident(fres);\n\t\tif (id != -1)\n\t\t\tbreak;\n\t}\n\tif (!fres)\n\t\treturn -ENODEV;\n\n\tndev = alloc_etherdev(sizeof(struct sonic_local));\n\tif (!ndev)\n\t\treturn -ENOMEM;\n\n\tlp = netdev_priv(ndev);\n\tlp->device = &board->dev;\n\tSET_NETDEV_DEV(ndev, &board->dev);\n\n\terr = mac_sonic_nubus_probe_board(board, id, ndev);\n\tif (err)\n\t\tgoto out;\n\n\tsonic_msg_init(ndev);\n\n\terr = register_netdev(ndev);\n\tif (err)\n\t\tgoto undo_probe;\n\n\tnubus_set_drvdata(board, ndev);\n\n\treturn 0;\n\nundo_probe:\n\tdma_free_coherent(lp->device,\n\t\t\t  SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),\n\t\t\t  lp->descriptors, lp->descriptors_laddr);\nout:\n\tfree_netdev(ndev);\n\treturn err;\n}",
        "static int wdm_wait_for_response(struct file *file, long timeout)\n{\n\tstruct wdm_device *desc = file->private_data;\n\tlong rv; /* Use long here because (int) MAX_SCHEDULE_TIMEOUT < 0. */\n": "static int wdm_wait_for_response(struct file *file, long timeout)\n{\n\tstruct wdm_device *desc = file->private_data;\n\tlong rv; /* Use long here because (int) MAX_SCHEDULE_TIMEOUT < 0. */\n\n\t/*\n\t * Needs both flags. We cannot do with one because resetting it would\n\t * cause a race with write() yet we need to signal a disconnect.\n\t */\n\trv = wait_event_interruptible_timeout(desc->wait,\n\t\t\t      !test_bit(WDM_IN_USE, &desc->flags) ||\n\t\t\t      test_bit(WDM_DISCONNECTING, &desc->flags),\n\t\t\t      timeout);\n\n\t/*\n\t * To report the correct error. This is best effort.\n\t * We are inevitably racing with the hardware.\n\t */\n\tif (test_bit(WDM_DISCONNECTING, &desc->flags))\n\t\treturn -ENODEV;\n\tif (!rv)\n\t\treturn -EIO;\n\tif (rv < 0)\n\t\treturn -EINTR;\n\n\tspin_lock_irq(&desc->iuspin);\n\trv = desc->werr;\n\tdesc->werr = 0;\n\tspin_unlock_irq(&desc->iuspin);\n\n\treturn usb_translate_errors(rv);\n\n}",
        "static void rio_txcq_handler(struct cm_dev *cm, int slot)\n{\n\tint ack_slot;\n\n\t/* ATTN: Add TX completion notification if/when direct buffer": "static void rio_txcq_handler(struct cm_dev *cm, int slot)\n{\n\tint ack_slot;\n\n\t/* ATTN: Add TX completion notification if/when direct buffer\n\t * transfer is implemented. At this moment only correct tracking\n\t * of tx_count is important.\n\t */\n\triocm_debug(TX_EVENT, \"for mport_%d slot %d tx_cnt %d\",\n\t\t    cm->mport->id, slot, cm->tx_cnt);\n\n\tspin_lock(&cm->tx_lock);\n\tack_slot = cm->tx_ack_slot;\n\n\tif (ack_slot == slot)\n\t\triocm_debug(TX_EVENT, \"slot == ack_slot\");\n\n\twhile (cm->tx_cnt && ((ack_slot != slot) ||\n\t       (cm->tx_cnt == RIOCM_TX_RING_SIZE))) {\n\n\t\tcm->tx_buf[ack_slot] = NULL;\n\t\t++ack_slot;\n\t\tack_slot &= (RIOCM_TX_RING_SIZE - 1);\n\t\tcm->tx_cnt--;\n\t}\n\n\tif (cm->tx_cnt < 0 || cm->tx_cnt > RIOCM_TX_RING_SIZE)\n\t\triocm_error(\"tx_cnt %d out of sync\", cm->tx_cnt);\n\n\tWARN_ON((cm->tx_cnt < 0) || (cm->tx_cnt > RIOCM_TX_RING_SIZE));\n\n\tcm->tx_ack_slot = ack_slot;\n\n\t/*\n\t * If there are pending requests, insert them into transmit queue\n\t */\n\tif (!list_empty(&cm->tx_reqs) && (cm->tx_cnt < RIOCM_TX_RING_SIZE)) {\n\t\tstruct tx_req *req, *_req;\n\t\tint rc;\n\n\t\tlist_for_each_entry_safe(req, _req, &cm->tx_reqs, node) {\n\t\t\tlist_del(&req->node);\n\t\t\tcm->tx_buf[cm->tx_slot] = req->buffer;\n\t\t\trc = rio_add_outb_message(cm->mport, req->rdev, cmbox,\n\t\t\t\t\t\t  req->buffer, req->len);\n\t\t\tkfree(req->buffer);\n\t\t\tkfree(req);\n\n\t\t\t++cm->tx_cnt;\n\t\t\t++cm->tx_slot;\n\t\t\tcm->tx_slot &= (RIOCM_TX_RING_SIZE - 1);\n\t\t\tif (cm->tx_cnt == RIOCM_TX_RING_SIZE)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tspin_unlock(&cm->tx_lock);\n}",
        "static void test_detach_bpf(int type, sa_family_t family)\n{\n#ifdef SO_DETACH_REUSEPORT_BPF\n\t__u32 nr_run_before = 0, nr_run_after = 0, tmp, i;\n\tstruct epoll_event ev;": "static void test_detach_bpf(int type, sa_family_t family)\n{\n#ifdef SO_DETACH_REUSEPORT_BPF\n\t__u32 nr_run_before = 0, nr_run_after = 0, tmp, i;\n\tstruct epoll_event ev;\n\tint cli_fd, err, nev;\n\tstruct cmd cmd = {};\n\tint optvalue = 0;\n\n\terr = setsockopt(sk_fds[0], SOL_SOCKET, SO_DETACH_REUSEPORT_BPF,\n\t\t\t &optvalue, sizeof(optvalue));\n\tRET_IF(err == -1, \"setsockopt(SO_DETACH_REUSEPORT_BPF)\",\n\t       \"err:%d errno:%d\\n\", err, errno);\n\n\terr = setsockopt(sk_fds[1], SOL_SOCKET, SO_DETACH_REUSEPORT_BPF,\n\t\t\t &optvalue, sizeof(optvalue));\n\tRET_IF(err == 0 || errno != ENOENT,\n\t       \"setsockopt(SO_DETACH_REUSEPORT_BPF)\",\n\t       \"err:%d errno:%d\\n\", err, errno);\n\n\tfor (i = 0; i < NR_RESULTS; i++) {\n\t\terr = bpf_map_lookup_elem(result_map, &i, &tmp);\n\t\tRET_IF(err < 0, \"lookup_elem(result_map)\",\n\t\t       \"i:%u err:%d errno:%d\\n\", i, err, errno);\n\t\tnr_run_before += tmp;\n\t}\n\n\tcli_fd = send_data(type, family, &cmd, sizeof(cmd), PASS);\n\tif (cli_fd < 0)\n\t\treturn;\n\tnev = epoll_wait(epfd, &ev, 1, 5);\n\tRET_IF(nev <= 0, \"nev <= 0\",\n\t       \"nev:%d expected:1 type:%d family:%d data:(0, 0)\\n\",\n\t       nev,  type, family);\n\n\tfor (i = 0; i < NR_RESULTS; i++) {\n\t\terr = bpf_map_lookup_elem(result_map, &i, &tmp);\n\t\tRET_IF(err < 0, \"lookup_elem(result_map)\",\n\t\t       \"i:%u err:%d errno:%d\\n\", i, err, errno);\n\t\tnr_run_after += tmp;\n\t}\n\n\tRET_IF(nr_run_before != nr_run_after,\n\t       \"nr_run_before != nr_run_after\",\n\t       \"nr_run_before:%u nr_run_after:%u\\n\",\n\t       nr_run_before, nr_run_after);\n\n\tclose(cli_fd);\n#else\n\ttest__skip();\n#endif\n}",
        "static int init_display(struct fbtft_par *par)\n{\n\tpar->fbtftops.reset(par);\n\n\twrite_reg(par, 0xEF, 0x03, 0x80, 0x02);": "static int init_display(struct fbtft_par *par)\n{\n\tpar->fbtftops.reset(par);\n\n\twrite_reg(par, 0xEF, 0x03, 0x80, 0x02);\n\twrite_reg(par, 0xCF, 0x00, 0XC1, 0X30);\n\twrite_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81);\n\twrite_reg(par, 0xE8, 0x85, 0x00, 0x78);\n\twrite_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02);\n\twrite_reg(par, 0xF7, 0x20);\n\twrite_reg(par, 0xEA, 0x00, 0x00);\n\n\t/* Power Control 1 */\n\twrite_reg(par, 0xC0, 0x23);\n\n\t/* Power Control 2 */\n\twrite_reg(par, 0xC1, 0x10);\n\n\t/* VCOM Control 1 */\n\twrite_reg(par, 0xC5, 0x3e, 0x28);\n\n\t/* VCOM Control 2 */\n\twrite_reg(par, 0xC7, 0x86);\n\n\t/* COLMOD: Pixel Format Set */\n\t/* 16 bits/pixel */\n\twrite_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);\n\n\t/* Frame Rate Control */\n\t/* Division ratio = fosc, Frame Rate = 79Hz */\n\twrite_reg(par, 0xB1, 0x00, 0x18);\n\n\t/* Display Function Control */\n\twrite_reg(par, 0xB6, 0x08, 0x82, 0x27);\n\n\t/* Gamma Function Disable */\n\twrite_reg(par, 0xF2, 0x00);\n\n\t/* Gamma curve selection */\n\twrite_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x01);\n\n\t/* Positive Gamma Correction */\n\twrite_reg(par, 0xE0,\n\t\t  0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1,\n\t\t  0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00);\n\n\t/* Negative Gamma Correction */\n\twrite_reg(par, 0xE1,\n\t\t  0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1,\n\t\t  0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F);\n\n\twrite_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);\n\n\tmdelay(120);\n\n\twrite_reg(par, MIPI_DCS_SET_DISPLAY_ON);\n\n\treturn 0;\n}",
        "static inline void nullb_complete_cmd(struct nullb_cmd *cmd)\n{\n\t/*\n\t * Since root privileges are required to configure the null_blk\n\t * driver, it is fine that this driver does not initialize the": "static inline void nullb_complete_cmd(struct nullb_cmd *cmd)\n{\n\t/*\n\t * Since root privileges are required to configure the null_blk\n\t * driver, it is fine that this driver does not initialize the\n\t * data buffers of read commands. Zero-initialize these buffers\n\t * anyway if KMSAN is enabled to prevent that KMSAN complains\n\t * about null_blk not initializing read data buffers.\n\t */\n\tif (IS_ENABLED(CONFIG_KMSAN))\n\t\tnullb_zero_read_cmd_buffer(cmd);\n\n\t/* Complete IO by inline, softirq or timer */\n\tswitch (cmd->nq->dev->irqmode) {\n\tcase NULL_IRQ_SOFTIRQ:\n\t\tswitch (cmd->nq->dev->queue_mode) {\n\t\tcase NULL_Q_MQ:\n\t\t\tif (likely(!blk_should_fake_timeout(cmd->rq->q)))\n\t\t\t\tblk_mq_complete_request(cmd->rq);\n\t\t\tbreak;\n\t\tcase NULL_Q_BIO:\n\t\t\t/*\n\t\t\t * XXX: no proper submitting cpu information available.\n\t\t\t */\n\t\t\tend_cmd(cmd);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase NULL_IRQ_NONE:\n\t\tend_cmd(cmd);\n\t\tbreak;\n\tcase NULL_IRQ_TIMER:\n\t\tnull_cmd_end_timer(cmd);\n\t\tbreak;\n\t}\n}",
        "static void cpt_rxc_teardown(struct rvu *rvu, int blkaddr)\n{\n\tstruct cpt_rxc_time_cfg_req req;\n\tint timeout = 2000;\n\tu64 reg;": "static void cpt_rxc_teardown(struct rvu *rvu, int blkaddr)\n{\n\tstruct cpt_rxc_time_cfg_req req;\n\tint timeout = 2000;\n\tu64 reg;\n\n\tif (is_rvu_otx2(rvu))\n\t\treturn;\n\n\t/* Set time limit to minimum values, so that rxc entries will be\n\t * flushed out quickly.\n\t */\n\treq.step = 1;\n\treq.zombie_thres = 1;\n\treq.zombie_limit = 1;\n\treq.active_thres = 1;\n\treq.active_limit = 1;\n\n\tcpt_rxc_time_cfg(rvu, &req, blkaddr);\n\n\tdo {\n\t\treg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS);\n\t\tudelay(1);\n\t\tif (FIELD_GET(RXC_ACTIVE_COUNT, reg))\n\t\t\ttimeout--;\n\t\telse\n\t\t\tbreak;\n\t} while (timeout);\n\n\tif (timeout == 0)\n\t\tdev_warn(rvu->dev, \"Poll for RXC active count hits hard loop counter\\n\");\n\n\ttimeout = 2000;\n\tdo {\n\t\treg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS);\n\t\tudelay(1);\n\t\tif (FIELD_GET(RXC_ZOMBIE_COUNT, reg))\n\t\t\ttimeout--;\n\t\telse\n\t\t\tbreak;\n\t} while (timeout);\n\n\tif (timeout == 0)\n\t\tdev_warn(rvu->dev, \"Poll for RXC zombie count hits hard loop counter\\n\");\n}",
        "static int mxl692_read_ber_ucb(struct dvb_frontend *fe)\n{\n\tstruct mxl692_dev *dev = fe->demodulator_priv;\n\tstruct dtv_frontend_properties *c = &fe->dtv_property_cache;\n\tu8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};": "static int mxl692_read_ber_ucb(struct dvb_frontend *fe)\n{\n\tstruct mxl692_dev *dev = fe->demodulator_priv;\n\tstruct dtv_frontend_properties *c = &fe->dtv_property_cache;\n\tu8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {};\n\tstruct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T *atsc_errors;\n\tenum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type;\n\tint mxl_status = 0;\n\tu32 utmp;\n\n\tdev_dbg(&dev->i2c_client->dev, \"\\n\");\n\n\tatsc_errors = (struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T *)&rx_buf;\n\n\tswitch (demod_type) {\n\tcase MXL_EAGLE_DEMOD_TYPE_ATSC:\n\t\tmxl_status = mxl692_i2c_writeread(dev,\n\t\t\t\t\t\t  MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET,\n\t\t\t\t\t\t  NULL,\n\t\t\t\t\t\t  0,\n\t\t\t\t\t\t  rx_buf,\n\t\t\t\t\t\t  sizeof(struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T));\n\t\tif (!mxl_status) {\n\t\t\tif (atsc_errors->error_packets == 0)\n\t\t\t\tutmp = 0;\n\t\t\telse\n\t\t\t\tutmp = ((atsc_errors->error_bytes / atsc_errors->error_packets) *\n\t\t\t\t\tatsc_errors->total_packets);\n\t\t\t/* ber */\n\t\t\tc->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;\n\t\t\tc->post_bit_error.stat[0].uvalue += atsc_errors->error_bytes;\n\t\t\tc->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;\n\t\t\tc->post_bit_count.stat[0].uvalue += utmp;\n\t\t\t/* ucb */\n\t\t\tc->block_error.stat[0].scale = FE_SCALE_COUNTER;\n\t\t\tc->block_error.stat[0].uvalue += atsc_errors->error_packets;\n\n\t\t\tdev_dbg(&dev->i2c_client->dev, \"%llu   %llu\\n\",\n\t\t\t\tc->post_bit_count.stat[0].uvalue, c->block_error.stat[0].uvalue);\n\t\t}\n\t\tbreak;\n\tcase MXL_EAGLE_DEMOD_TYPE_QAM:\n\tcase MXL_EAGLE_DEMOD_TYPE_OOB:\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (mxl_status)\n\t\tdev_dbg(&dev->i2c_client->dev, \"err %d\\n\", mxl_status);\n\n\treturn mxl_status;\n}",
        "static inline bool can_skip_action(enum NTFS_LOG_OPERATION op)\n{\n\tswitch (op) {\n\tcase Noop:\n\tcase DeleteDirtyClusters:": "static inline bool can_skip_action(enum NTFS_LOG_OPERATION op)\n{\n\tswitch (op) {\n\tcase Noop:\n\tcase DeleteDirtyClusters:\n\tcase HotFix:\n\tcase EndTopLevelAction:\n\tcase PrepareTransaction:\n\tcase CommitTransaction:\n\tcase ForgetTransaction:\n\tcase CompensationLogRecord:\n\tcase OpenNonresidentAttribute:\n\tcase OpenAttributeTableDump:\n\tcase AttributeNamesDump:\n\tcase DirtyPageTableDump:\n\tcase TransactionTableDump:\n\t\treturn true;\n\tdefault:\n\t\treturn false;\n\t}\n}",
        "static int prepare_message_secure(struct ceph_connection *con)\n{\n\tvoid *zerop = page_address(ceph_zero_page);\n\tstruct sg_table enc_sgt = {};\n\tstruct sg_table sgt = {};": "static int prepare_message_secure(struct ceph_connection *con)\n{\n\tvoid *zerop = page_address(ceph_zero_page);\n\tstruct sg_table enc_sgt = {};\n\tstruct sg_table sgt = {};\n\tstruct page **enc_pages;\n\tint enc_page_cnt;\n\tint tail_len;\n\tint ret;\n\n\tret = prepare_head_secure_small(con, con->v2.out_buf,\n\t\t\t\t\tsizeof(struct ceph_msg_header2));\n\tif (ret)\n\t\treturn ret;\n\n\ttail_len = tail_onwire_len(con->out_msg, true);\n\tif (!tail_len) {\n\t\t/*\n\t\t * Empty message: once the head is written,\n\t\t * we are done -- there is no epilogue.\n\t\t */\n\t\tcon->v2.out_state = OUT_S_FINISH_MESSAGE;\n\t\treturn 0;\n\t}\n\n\tencode_epilogue_secure(con, false);\n\tret = setup_message_sgs(&sgt, con->out_msg, zerop, zerop, zerop,\n\t\t\t\t&con->v2.out_epil, false);\n\tif (ret)\n\t\tgoto out;\n\n\tenc_page_cnt = calc_pages_for(0, tail_len);\n\tenc_pages = ceph_alloc_page_vector(enc_page_cnt, GFP_NOIO);\n\tif (IS_ERR(enc_pages)) {\n\t\tret = PTR_ERR(enc_pages);\n\t\tgoto out;\n\t}\n\n\tWARN_ON(con->v2.out_enc_pages || con->v2.out_enc_page_cnt);\n\tcon->v2.out_enc_pages = enc_pages;\n\tcon->v2.out_enc_page_cnt = enc_page_cnt;\n\tcon->v2.out_enc_resid = tail_len;\n\tcon->v2.out_enc_i = 0;\n\n\tret = sg_alloc_table_from_pages(&enc_sgt, enc_pages, enc_page_cnt,\n\t\t\t\t\t0, tail_len, GFP_NOIO);\n\tif (ret)\n\t\tgoto out;\n\n\tret = gcm_crypt(con, true, sgt.sgl, enc_sgt.sgl,\n\t\t\ttail_len - CEPH_GCM_TAG_LEN);\n\tif (ret)\n\t\tgoto out;\n\n\tdout(\"%s con %p msg %p sg_cnt %d enc_page_cnt %d\\n\", __func__, con,\n\t     con->out_msg, sgt.orig_nents, enc_page_cnt);\n\tcon->v2.out_state = OUT_S_QUEUE_ENC_PAGE;\n\nout:\n\tsg_free_table(&sgt);\n\tsg_free_table(&enc_sgt);\n\treturn ret;\n}",
        "static void run_test(void)\n{\n\tint fdr, fds, total_len;\n\n\tfdr = setup_rx();": "static void run_test(void)\n{\n\tint fdr, fds, total_len;\n\n\tfdr = setup_rx();\n\tfds = setup_sniffer();\n\n\ttotal_len = do_tx();\n\n\t/* BPF filter accepts only this length, vlan changes MAC */\n\tif (cfg_payload_len == DATA_LEN && !cfg_use_vlan)\n\t\tdo_rx(fds, total_len - sizeof(struct virtio_net_hdr),\n\t\t      tbuf + sizeof(struct virtio_net_hdr));\n\n\tdo_rx(fdr, cfg_payload_len, tbuf + total_len - cfg_payload_len);\n\n\tif (close(fds))\n\t\terror(1, errno, \"close s\");\n\tif (close(fdr))\n\t\terror(1, errno, \"close r\");\n}",
        "static int cvmx_usb_poll(struct octeon_hcd *usb)\n{\n\tunion cvmx_usbcx_hfnum usbc_hfnum;\n\tunion cvmx_usbcx_gintsts usbc_gintsts;\n": "static int cvmx_usb_poll(struct octeon_hcd *usb)\n{\n\tunion cvmx_usbcx_hfnum usbc_hfnum;\n\tunion cvmx_usbcx_gintsts usbc_gintsts;\n\n\tprefetch_range(usb, sizeof(*usb));\n\n\t/* Update the frame counter */\n\tusbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));\n\tif ((usb->frame_number & 0x3fff) > usbc_hfnum.s.frnum)\n\t\tusb->frame_number += 0x4000;\n\tusb->frame_number &= ~0x3fffull;\n\tusb->frame_number |= usbc_hfnum.s.frnum;\n\n\t/* Read the pending interrupts */\n\tusbc_gintsts.u32 = cvmx_usb_read_csr32(usb,\n\t\t\t\t\t       CVMX_USBCX_GINTSTS(usb->index));\n\n\t/* Clear the interrupts now that we know about them */\n\tcvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index),\n\t\t\t     usbc_gintsts.u32);\n\n\tif (usbc_gintsts.s.rxflvl) {\n\t\t/*\n\t\t * RxFIFO Non-Empty (RxFLvl)\n\t\t * Indicates that there is at least one packet pending to be\n\t\t * read from the RxFIFO.\n\t\t *\n\t\t * In DMA mode this is handled by hardware\n\t\t */\n\t\tif (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)\n\t\t\tcvmx_usb_poll_rx_fifo(usb);\n\t}\n\tif (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {\n\t\t/* Fill the Tx FIFOs when not in DMA mode */\n\t\tif (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)\n\t\t\tcvmx_usb_poll_tx_fifo(usb);\n\t}\n\tif (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {\n\t\tunion cvmx_usbcx_hprt usbc_hprt;\n\t\t/*\n\t\t * Disconnect Detected Interrupt (DisconnInt)\n\t\t * Asserted when a device disconnect is detected.\n\t\t *\n\t\t * Host Port Interrupt (PrtInt)\n\t\t * The core sets this bit to indicate a change in port status of\n\t\t * one of the O2P USB core ports in Host mode. The application\n\t\t * must read the Host Port Control and Status (HPRT) register to\n\t\t * determine the exact event that caused this interrupt. The\n\t\t * application must clear the appropriate status bit in the Host\n\t\t * Port Control and Status register to clear this bit.\n\t\t *\n\t\t * Call the user's port callback\n\t\t */\n\t\tocteon_usb_port_callback(usb);\n\t\t/* Clear the port change bits */\n\t\tusbc_hprt.u32 =\n\t\t\tcvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));\n\t\tusbc_hprt.s.prtena = 0;\n\t\tcvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index),\n\t\t\t\t     usbc_hprt.u32);\n\t}\n\tif (usbc_gintsts.s.hchint) {\n\t\t/*\n\t\t * Host Channels Interrupt (HChInt)\n\t\t * The core sets this bit to indicate that an interrupt is\n\t\t * pending on one of the channels of the core (in Host mode).\n\t\t * The application must read the Host All Channels Interrupt\n\t\t * (HAINT) register to determine the exact number of the channel\n\t\t * on which the interrupt occurred, and then read the\n\t\t * corresponding Host Channel-n Interrupt (HCINTn) register to\n\t\t * determine the exact cause of the interrupt. The application\n\t\t * must clear the appropriate status bit in the HCINTn register\n\t\t * to clear this bit.\n\t\t */\n\t\tunion cvmx_usbcx_haint usbc_haint;\n\n\t\tusbc_haint.u32 = cvmx_usb_read_csr32(usb,\n\t\t\t\t\t\t     CVMX_USBCX_HAINT(usb->index));\n\t\twhile (usbc_haint.u32) {\n\t\t\tint channel;\n\n\t\t\tchannel = __fls(usbc_haint.u32);\n\t\t\tcvmx_usb_poll_channel(usb, channel);\n\t\t\tusbc_haint.u32 ^= 1 << channel;\n\t\t}\n\t}\n\n\tcvmx_usb_schedule(usb, usbc_gintsts.s.sof);\n\n\treturn 0;\n}",
        "static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)\n{\n\tswitch (index) {\n\tcase 0:\n\t\tchannel->dpll_tod_cnfg = DPLL1_TOD_CNFG;": "static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)\n{\n\tswitch (index) {\n\tcase 0:\n\t\tchannel->dpll_tod_cnfg = DPLL1_TOD_CNFG;\n\t\tchannel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;\n\t\tchannel->dpll_tod_sts = DPLL1_TOD_STS;\n\t\tchannel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;\n\t\tchannel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;\n\t\tchannel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;\n\t\tchannel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;\n\t\tchannel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;\n\t\tbreak;\n\tcase 1:\n\t\tchannel->dpll_tod_cnfg = DPLL2_TOD_CNFG;\n\t\tchannel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;\n\t\tchannel->dpll_tod_sts = DPLL2_TOD_STS;\n\t\tchannel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;\n\t\tchannel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;\n\t\tchannel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;\n\t\tchannel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;\n\t\tchannel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tchannel->current_freq_ppb = 0;\n\n\treturn 0;\n}",
        "static int serdes_init_1g_serdes(struct niu *np)\n{\n\tstruct niu_link_config *lp = &np->link_config;\n\tunsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;\n\tu64 ctrl_val, test_cfg_val, sig, mask, val;": "static int serdes_init_1g_serdes(struct niu *np)\n{\n\tstruct niu_link_config *lp = &np->link_config;\n\tunsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;\n\tu64 ctrl_val, test_cfg_val, sig, mask, val;\n\tint err;\n\tu64 reset_val, val_rd;\n\n\tval = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |\n\t\tENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |\n\t\tENET_SERDES_PLL_FBDIV0;\n\tswitch (np->port) {\n\tcase 0:\n\t\treset_val =  ENET_SERDES_RESET_0;\n\t\tctrl_reg = ENET_SERDES_0_CTRL_CFG;\n\t\ttest_cfg_reg = ENET_SERDES_0_TEST_CFG;\n\t\tpll_cfg = ENET_SERDES_0_PLL_CFG;\n\t\tbreak;\n\tcase 1:\n\t\treset_val =  ENET_SERDES_RESET_1;\n\t\tctrl_reg = ENET_SERDES_1_CTRL_CFG;\n\t\ttest_cfg_reg = ENET_SERDES_1_TEST_CFG;\n\t\tpll_cfg = ENET_SERDES_1_PLL_CFG;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\tctrl_val = (ENET_SERDES_CTRL_SDET_0 |\n\t\t    ENET_SERDES_CTRL_SDET_1 |\n\t\t    ENET_SERDES_CTRL_SDET_2 |\n\t\t    ENET_SERDES_CTRL_SDET_3 |\n\t\t    (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |\n\t\t    (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |\n\t\t    (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |\n\t\t    (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |\n\t\t    (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |\n\t\t    (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |\n\t\t    (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |\n\t\t    (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));\n\ttest_cfg_val = 0;\n\n\tif (lp->loopback_mode == LOOPBACK_PHY) {\n\t\ttest_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<\n\t\t\t\t  ENET_SERDES_TEST_MD_0_SHIFT) |\n\t\t\t\t (ENET_TEST_MD_PAD_LOOPBACK <<\n\t\t\t\t  ENET_SERDES_TEST_MD_1_SHIFT) |\n\t\t\t\t (ENET_TEST_MD_PAD_LOOPBACK <<\n\t\t\t\t  ENET_SERDES_TEST_MD_2_SHIFT) |\n\t\t\t\t (ENET_TEST_MD_PAD_LOOPBACK <<\n\t\t\t\t  ENET_SERDES_TEST_MD_3_SHIFT));\n\t}\n\n\tnw64(ENET_SERDES_RESET, reset_val);\n\tmdelay(20);\n\tval_rd = nr64(ENET_SERDES_RESET);\n\tval_rd &= ~reset_val;\n\tnw64(pll_cfg, val);\n\tnw64(ctrl_reg, ctrl_val);\n\tnw64(test_cfg_reg, test_cfg_val);\n\tnw64(ENET_SERDES_RESET, val_rd);\n\tmdelay(2000);\n\n\t/* Initialize all 4 lanes of the SERDES.  */\n\tfor (i = 0; i < 4; i++) {\n\t\tu32 rxtx_ctrl, glue0;\n\n\t\terr = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);\n\t\tif (err)\n\t\t\treturn err;\n\t\terr = esr_read_glue0(np, i, &glue0);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\trxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);\n\t\trxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |\n\t\t\t      (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));\n\n\t\tglue0 &= ~(ESR_GLUE_CTRL0_SRATE |\n\t\t\t   ESR_GLUE_CTRL0_THCNT |\n\t\t\t   ESR_GLUE_CTRL0_BLTIME);\n\t\tglue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |\n\t\t\t  (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |\n\t\t\t  (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |\n\t\t\t  (BLTIME_300_CYCLES <<\n\t\t\t   ESR_GLUE_CTRL0_BLTIME_SHIFT));\n\n\t\terr = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);\n\t\tif (err)\n\t\t\treturn err;\n\t\terr = esr_write_glue0(np, i, glue0);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\n\tsig = nr64(ESR_INT_SIGNALS);\n\tswitch (np->port) {\n\tcase 0:\n\t\tval = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);\n\t\tmask = val;\n\t\tbreak;\n\n\tcase 1:\n\t\tval = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);\n\t\tmask = val;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tif ((sig & mask) != val) {\n\t\tnetdev_err(np->dev, \"Port %u signal bits [%08x] are not [%08x]\\n\",\n\t\t\t   np->port, (int)(sig & mask), (int)val);\n\t\treturn -ENODEV;\n\t}\n\n\treturn 0;\n}",
        "static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)\n{\n\tstruct bcm4908_enet *enet = netdev_priv(netdev);\n\tstruct bcm4908_enet_dma_ring *ring = &enet->tx_ring;\n\tstruct bcm4908_enet_dma_ring_slot *slot;": "static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)\n{\n\tstruct bcm4908_enet *enet = netdev_priv(netdev);\n\tstruct bcm4908_enet_dma_ring *ring = &enet->tx_ring;\n\tstruct bcm4908_enet_dma_ring_slot *slot;\n\tstruct device *dev = enet->dev;\n\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n\tint free_buf_descs;\n\tu32 tmp;\n\n\t/* Free transmitted skbs */\n\tif (enet->irq_tx < 0 &&\n\t    !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN))\n\t\tnapi_schedule(&enet->tx_ring.napi);\n\n\t/* Don't use the last empty buf descriptor */\n\tif (ring->read_idx <= ring->write_idx)\n\t\tfree_buf_descs = ring->read_idx - ring->write_idx + ring->length;\n\telse\n\t\tfree_buf_descs = ring->read_idx - ring->write_idx;\n\tif (free_buf_descs < 2) {\n\t\tnetif_stop_queue(netdev);\n\t\treturn NETDEV_TX_BUSY;\n\t}\n\n\t/* Hardware removes OWN bit after sending data */\n\tbuf_desc = &ring->buf_desc[ring->write_idx];\n\tif (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {\n\t\tnetif_stop_queue(netdev);\n\t\treturn NETDEV_TX_BUSY;\n\t}\n\n\tslot = &ring->slots[ring->write_idx];\n\tslot->skb = skb;\n\tslot->len = skb->len;\n\tslot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);\n\tif (unlikely(dma_mapping_error(dev, slot->dma_addr)))\n\t\treturn NETDEV_TX_BUSY;\n\n\ttmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n\ttmp |= DMA_CTL_STATUS_OWN;\n\ttmp |= DMA_CTL_STATUS_SOP;\n\ttmp |= DMA_CTL_STATUS_EOP;\n\ttmp |= DMA_CTL_STATUS_APPEND_CRC;\n\tif (ring->write_idx + 1 == ring->length - 1)\n\t\ttmp |= DMA_CTL_STATUS_WRAP;\n\n\tbuf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);\n\tbuf_desc->ctl = cpu_to_le32(tmp);\n\n\tbcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring);\n\n\tif (++ring->write_idx == ring->length - 1)\n\t\tring->write_idx = 0;\n\tenet->netdev->stats.tx_bytes += skb->len;\n\tenet->netdev->stats.tx_packets++;\n\n\treturn NETDEV_TX_OK;\n}",
        "static int __init light_init(struct ibm_init_struct *iibm)\n{\n\tint rc;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing light subdriver\\n\");": "static int __init light_init(struct ibm_init_struct *iibm)\n{\n\tint rc;\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"initializing light subdriver\\n\");\n\n\tif (tpacpi_is_ibm()) {\n\t\tTPACPI_ACPIHANDLE_INIT(ledb);\n\t\tTPACPI_ACPIHANDLE_INIT(lght);\n\t}\n\tTPACPI_ACPIHANDLE_INIT(cmos);\n\n\t/* light not supported on 570, 600e/x, 770e, 770x, G4x, R30, R31 */\n\ttp_features.light = (cmos_handle || lght_handle) && !ledb_handle;\n\n\tif (tp_features.light)\n\t\t/* light status not supported on\n\t\t   570, 600e/x, 770e, 770x, G4x, R30, R31, R32, X20 */\n\t\ttp_features.light_status =\n\t\t\tacpi_evalf(ec_handle, NULL, \"KBLT\", \"qv\");\n\n\tvdbg_printk(TPACPI_DBG_INIT, \"light is %s, light status is %s\\n\",\n\t\tstr_supported(tp_features.light),\n\t\tstr_supported(tp_features.light_status));\n\n\tif (!tp_features.light)\n\t\treturn -ENODEV;\n\n\trc = led_classdev_register(&tpacpi_pdev->dev,\n\t\t\t\t   &tpacpi_led_thinklight.led_classdev);\n\n\tif (rc < 0) {\n\t\ttp_features.light = 0;\n\t\ttp_features.light_status = 0;\n\t} else  {\n\t\trc = 0;\n\t}\n\n\treturn rc;\n}",
        "static int t7xx_pcie_mac_atr_cfg(struct t7xx_pci_dev *t7xx_dev, struct t7xx_atr_config *cfg)\n{\n\tstruct device *dev = &t7xx_dev->pdev->dev;\n\tvoid __iomem *pbase = IREG_BASE(t7xx_dev);\n\tint atr_size, pos, offset;": "static int t7xx_pcie_mac_atr_cfg(struct t7xx_pci_dev *t7xx_dev, struct t7xx_atr_config *cfg)\n{\n\tstruct device *dev = &t7xx_dev->pdev->dev;\n\tvoid __iomem *pbase = IREG_BASE(t7xx_dev);\n\tint atr_size, pos, offset;\n\tvoid __iomem *reg;\n\tu64 value;\n\n\tif (cfg->transparent) {\n\t\t/* No address conversion is performed */\n\t\tatr_size = ATR_TRANSPARENT_SIZE;\n\t} else {\n\t\tif (cfg->src_addr & (cfg->size - 1)) {\n\t\t\tdev_err(dev, \"Source address is not aligned to size\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (cfg->trsl_addr & (cfg->size - 1)) {\n\t\t\tdev_err(dev, \"Translation address %llx is not aligned to size %llx\\n\",\n\t\t\t\tcfg->trsl_addr, cfg->size - 1);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tpos = __ffs64(cfg->size);\n\n\t\t/* HW calculates the address translation space as 2^(atr_size + 1) */\n\t\tatr_size = pos - 1;\n\t}\n\n\toffset = ATR_PORT_OFFSET * cfg->port + ATR_TABLE_OFFSET * cfg->table;\n\n\treg = pbase + ATR_PCIE_WIN0_T0_TRSL_ADDR + offset;\n\tvalue = cfg->trsl_addr & ATR_PCIE_WIN0_ADDR_ALGMT;\n\tiowrite64(value, reg);\n\n\treg = pbase + ATR_PCIE_WIN0_T0_TRSL_PARAM + offset;\n\tiowrite32(cfg->trsl_id, reg);\n\n\treg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;\n\tvalue = (cfg->src_addr & ATR_PCIE_WIN0_ADDR_ALGMT) | (atr_size << 1) | BIT(0);\n\tiowrite64(value, reg);\n\n\t/* Ensure ATR is set */\n\tioread64(reg);\n\treturn 0;\n}",
        "static int mport_cdev_release(struct inode *inode, struct file *filp)\n{\n\tstruct mport_cdev_priv *priv = filp->private_data;\n\tstruct mport_dev *chdev;\n\tstruct rio_mport_pw_filter *pw_filter, *pw_filter_next;": "static int mport_cdev_release(struct inode *inode, struct file *filp)\n{\n\tstruct mport_cdev_priv *priv = filp->private_data;\n\tstruct mport_dev *chdev;\n\tstruct rio_mport_pw_filter *pw_filter, *pw_filter_next;\n\tstruct rio_mport_db_filter *db_filter, *db_filter_next;\n\tstruct rio_mport_mapping *map, *_map;\n\tunsigned long flags;\n\n\trmcd_debug(EXIT, \"%s filp=%p\", dev_name(&priv->md->dev), filp);\n\n\tchdev = priv->md;\n\tmport_cdev_release_dma(filp);\n\n\tpriv->event_mask = 0;\n\n\tspin_lock_irqsave(&chdev->pw_lock, flags);\n\tif (!list_empty(&priv->pw_filters)) {\n\t\tlist_for_each_entry_safe(pw_filter, pw_filter_next,\n\t\t\t\t\t &priv->pw_filters, priv_node)\n\t\t\trio_mport_delete_pw_filter(pw_filter);\n\t}\n\tspin_unlock_irqrestore(&chdev->pw_lock, flags);\n\n\tspin_lock_irqsave(&chdev->db_lock, flags);\n\tlist_for_each_entry_safe(db_filter, db_filter_next,\n\t\t\t\t &priv->db_filters, priv_node) {\n\t\trio_mport_delete_db_filter(db_filter);\n\t}\n\tspin_unlock_irqrestore(&chdev->db_lock, flags);\n\n\tkfifo_free(&priv->event_fifo);\n\n\tmutex_lock(&chdev->buf_mutex);\n\tlist_for_each_entry_safe(map, _map, &chdev->mappings, node) {\n\t\tif (map->filp == filp) {\n\t\t\trmcd_debug(EXIT, \"release mapping %p filp=%p\",\n\t\t\t\t   map->virt_addr, filp);\n\t\t\tkref_put(&map->ref, mport_release_mapping);\n\t\t}\n\t}\n\tmutex_unlock(&chdev->buf_mutex);\n\n\tmport_cdev_fasync(-1, filp, 0);\n\tfilp->private_data = NULL;\n\tmutex_lock(&chdev->file_mutex);\n\tlist_del(&priv->list);\n\tmutex_unlock(&chdev->file_mutex);\n\tput_device(&chdev->dev);\n\tkfree(priv);\n\treturn 0;\n}",
        "static void brcmuart_init_dma_hardware(struct brcmuart_priv *priv)\n{\n\tu32 daddr;\n\tu32 value;\n\tint x;": "static void brcmuart_init_dma_hardware(struct brcmuart_priv *priv)\n{\n\tu32 daddr;\n\tu32 value;\n\tint x;\n\n\t/* Start with all interrupts disabled */\n\tudma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, 0xffffffff);\n\n\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_SIZE, RX_BUF_SIZE);\n\n\t/*\n\t * Setup buffer close to happen when 32 character times have\n\t * elapsed since the last character was received.\n\t */\n\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_CLOSE, 16*10*32);\n\tvalue = (RX_BUFS_COUNT << UDMA_RX_CTRL_NUM_BUF_USED_SHIFT)\n\t\t| UDMA_RX_CTRL_BUF_CLOSE_MODE\n\t\t| UDMA_RX_CTRL_BUF_CLOSE_ENA;\n\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_CTRL, value);\n\n\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_BLOCKOUT_COUNTER, 0);\n\tdaddr = priv->rx_addr;\n\tfor (x = 0; x < RX_BUFS_COUNT; x++) {\n\n\t\t/* Set RX transfer length to 0 for unknown */\n\t\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_TRANSFER_LEN, 0);\n\n\t\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_LO(x),\n\t\t\t    lower_32_bits(daddr));\n\t\tudma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_HI(x),\n\t\t\t    upper_32_bits(daddr));\n\t\tdaddr += RX_BUF_SIZE;\n\t}\n\n\tdaddr = priv->tx_addr;\n\tudma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_LO(0),\n\t\t    lower_32_bits(daddr));\n\tudma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_HI(0),\n\t\t    upper_32_bits(daddr));\n\tudma_writel(priv, REGS_DMA_TX, UDMA_TX_CTRL,\n\t\t    UDMA_TX_CTRL_NUM_BUF_USED_1);\n\n\t/* clear all interrupts then enable them */\n\tudma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, 0xffffffff);\n\tudma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,\n\t\tUDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);\n\n}",
        "static void nv_restore_phy(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu16 phy_reserved, mii_control;\n": "static void nv_restore_phy(struct net_device *dev)\n{\n\tstruct fe_priv *np = netdev_priv(dev);\n\tu16 phy_reserved, mii_control;\n\n\tif (np->phy_oui == PHY_OUI_REALTEK &&\n\t    np->phy_model == PHY_MODEL_REALTEK_8201 &&\n\t    phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {\n\t\tmii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);\n\t\tphy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);\n\t\tphy_reserved &= ~PHY_REALTEK_INIT_MSK1;\n\t\tphy_reserved |= PHY_REALTEK_INIT8;\n\t\tmii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);\n\t\tmii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);\n\n\t\t/* restart auto negotiation */\n\t\tmii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);\n\t\tmii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);\n\t\tmii_rw(dev, np->phyaddr, MII_BMCR, mii_control);\n\t}\n}",
        "static void test_txmsg_skb(int cgrp, struct sockmap_options *opt)\n{\n\tbool data = opt->data_test;\n\tint k = ktls;\n": "static void test_txmsg_skb(int cgrp, struct sockmap_options *opt)\n{\n\tbool data = opt->data_test;\n\tint k = ktls;\n\n\topt->data_test = true;\n\tktls = 1;\n\n\ttxmsg_pass = txmsg_drop = 0;\n\ttxmsg_ingress = txmsg_redir = 0;\n\ttxmsg_ktls_skb = 1;\n\ttxmsg_pass = 1;\n\n\t/* Using data verification so ensure iov layout is\n\t * expected from test receiver side. e.g. has enough\n\t * bytes to write test code.\n\t */\n\topt->iov_length = 100;\n\topt->iov_count = 1;\n\topt->rate = 1;\n\ttest_exec(cgrp, opt);\n\n\ttxmsg_ktls_skb_drop = 1;\n\ttest_exec(cgrp, opt);\n\n\ttxmsg_ktls_skb_drop = 0;\n\ttxmsg_ktls_skb_redir = 1;\n\ttest_exec(cgrp, opt);\n\ttxmsg_ktls_skb_redir = 0;\n\n\t/* Tests that omit skb_parser */\n\ttxmsg_omit_skb_parser = 1;\n\tktls = 0;\n\ttxmsg_ktls_skb = 0;\n\ttest_exec(cgrp, opt);\n\n\ttxmsg_ktls_skb_drop = 1;\n\ttest_exec(cgrp, opt);\n\ttxmsg_ktls_skb_drop = 0;\n\n\ttxmsg_ktls_skb_redir = 1;\n\ttest_exec(cgrp, opt);\n\n\tktls = 1;\n\ttest_exec(cgrp, opt);\n\ttxmsg_omit_skb_parser = 0;\n\n\topt->data_test = data;\n\tktls = k;\n}",
        "static void sched_change_group(struct task_struct *tsk, int type)\n{\n\tstruct task_group *tg;\n\n\t/*": "static void sched_change_group(struct task_struct *tsk, int type)\n{\n\tstruct task_group *tg;\n\n\t/*\n\t * All callers are synchronized by task_rq_lock(); we do not use RCU\n\t * which is pointless here. Thus, we pass \"true\" to task_css_check()\n\t * to prevent lockdep warnings.\n\t */\n\ttg = container_of(task_css_check(tsk, cpu_cgrp_id, true),\n\t\t\t  struct task_group, css);\n\ttg = autogroup_task_group(tsk, tg);\n\ttsk->sched_task_group = tg;\n\n#ifdef CONFIG_FAIR_GROUP_SCHED\n\tif (tsk->sched_class->task_change_group)\n\t\ttsk->sched_class->task_change_group(tsk, type);\n\telse\n#endif\n\t\tset_task_rq(tsk, task_cpu(tsk));\n}",
        "static struct kvm_vm *test_vm_create(void)\n{\n\tstruct kvm_vm *vm;\n\tunsigned int i;\n\tint nr_vcpus = test_args.nr_vcpus;": "static struct kvm_vm *test_vm_create(void)\n{\n\tstruct kvm_vm *vm;\n\tunsigned int i;\n\tint nr_vcpus = test_args.nr_vcpus;\n\n\tvm = vm_create_default_with_vcpus(nr_vcpus, 0, 0, guest_code, NULL);\n\n\tvm_init_descriptor_tables(vm);\n\tvm_install_exception_handler(vm, VECTOR_IRQ_CURRENT, guest_irq_handler);\n\n\tfor (i = 0; i < nr_vcpus; i++) {\n\t\tvcpu_init_descriptor_tables(vm, i);\n\n\t\ttest_vcpu[i].vcpuid = i;\n\t\ttest_vcpu[i].vm = vm;\n\t}\n\n\tucall_init(vm, NULL);\n\ttest_init_timer_irq(vm);\n\tgic_fd = vgic_v3_setup(vm, nr_vcpus, 64, GICD_BASE_GPA, GICR_BASE_GPA);\n\tif (gic_fd < 0) {\n\t\tprint_skip(\"Failed to create vgic-v3\");\n\t\texit(KSFT_SKIP);\n\t}\n\n\t/* Make all the test's cmdline args visible to the guest */\n\tsync_global_to_guest(vm, test_args);\n\n\treturn vm;\n}",
        "static int rt_cpu_seq_show(struct seq_file *seq, void *v)\n{\n\tstruct rt_cache_stat *st = v;\n\n\tif (v == SEQ_START_TOKEN) {": "static int rt_cpu_seq_show(struct seq_file *seq, void *v)\n{\n\tstruct rt_cache_stat *st = v;\n\n\tif (v == SEQ_START_TOKEN) {\n\t\tseq_puts(seq, \"entries  in_hit   in_slow_tot in_slow_mc in_no_route in_brd   in_martian_dst in_martian_src out_hit  out_slow_tot out_slow_mc gc_total gc_ignored gc_goal_miss gc_dst_overflow in_hlist_search out_hlist_search\\n\");\n\t\treturn 0;\n\t}\n\n\tseq_printf(seq, \"%08x %08x %08x    %08x   %08x    %08x %08x       \"\n\t\t\t\"%08x       %08x %08x     %08x    %08x %08x   \"\n\t\t\t\"%08x     %08x        %08x        %08x\\n\",\n\t\t   dst_entries_get_slow(&ipv4_dst_ops),\n\t\t   0, /* st->in_hit */\n\t\t   st->in_slow_tot,\n\t\t   st->in_slow_mc,\n\t\t   st->in_no_route,\n\t\t   st->in_brd,\n\t\t   st->in_martian_dst,\n\t\t   st->in_martian_src,\n\n\t\t   0, /* st->out_hit */\n\t\t   st->out_slow_tot,\n\t\t   st->out_slow_mc,\n\n\t\t   0, /* st->gc_total */\n\t\t   0, /* st->gc_ignored */\n\t\t   0, /* st->gc_goal_miss */\n\t\t   0, /* st->gc_dst_overflow */\n\t\t   0, /* st->in_hlist_search */\n\t\t   0  /* st->out_hlist_search */\n\t\t);\n\treturn 0;\n}",
        "static int mt2063_init(struct dvb_frontend *fe)\n{\n\tint status;\n\tstruct mt2063_state *state = fe->tuner_priv;\n\tu8 all_resets = 0xF0;\t/* reset/load bits */": "static int mt2063_init(struct dvb_frontend *fe)\n{\n\tint status;\n\tstruct mt2063_state *state = fe->tuner_priv;\n\tu8 all_resets = 0xF0;\t/* reset/load bits */\n\tconst u8 *def = NULL;\n\tchar *step;\n\tu32 FCRUN;\n\ts32 maxReads;\n\tu32 fcu_osc;\n\tu32 i;\n\n\tdprintk(2, \"\\n\");\n\n\tstate->rcvr_mode = MT2063_CABLE_QAM;\n\n\t/*  Read the Part/Rev code from the tuner */\n\tstatus = mt2063_read(state, MT2063_REG_PART_REV,\n\t\t\t     &state->reg[MT2063_REG_PART_REV], 1);\n\tif (status < 0) {\n\t\tprintk(KERN_ERR \"Can't read mt2063 part ID\\n\");\n\t\treturn status;\n\t}\n\n\t/* Check the part/rev code */\n\tswitch (state->reg[MT2063_REG_PART_REV]) {\n\tcase MT2063_B0:\n\t\tstep = \"B0\";\n\t\tbreak;\n\tcase MT2063_B1:\n\t\tstep = \"B1\";\n\t\tbreak;\n\tcase MT2063_B2:\n\t\tstep = \"B2\";\n\t\tbreak;\n\tcase MT2063_B3:\n\t\tstep = \"B3\";\n\t\tbreak;\n\tdefault:\n\t\tprintk(KERN_ERR \"mt2063: Unknown mt2063 device ID (0x%02x)\\n\",\n\t\t       state->reg[MT2063_REG_PART_REV]);\n\t\treturn -ENODEV;\t/*  Wrong tuner Part/Rev code */\n\t}\n\n\t/*  Check the 2nd byte of the Part/Rev code from the tuner */\n\tstatus = mt2063_read(state, MT2063_REG_RSVD_3B,\n\t\t\t     &state->reg[MT2063_REG_RSVD_3B], 1);\n\n\t/* b7 != 0 ==> NOT MT2063 */\n\tif (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) {\n\t\tprintk(KERN_ERR \"mt2063: Unknown part ID (0x%02x%02x)\\n\",\n\t\t       state->reg[MT2063_REG_PART_REV],\n\t\t       state->reg[MT2063_REG_RSVD_3B]);\n\t\treturn -ENODEV;\t/*  Wrong tuner Part/Rev code */\n\t}\n\n\tprintk(KERN_INFO \"mt2063: detected a mt2063 %s\\n\", step);\n\n\t/*  Reset the tuner  */\n\tstatus = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);\n\tif (status < 0)\n\t\treturn status;\n\n\t/* change all of the default values that vary from the HW reset values */\n\t/*  def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */\n\tswitch (state->reg[MT2063_REG_PART_REV]) {\n\tcase MT2063_B3:\n\t\tdef = MT2063B3_defaults;\n\t\tbreak;\n\n\tcase MT2063_B1:\n\t\tdef = MT2063B1_defaults;\n\t\tbreak;\n\n\tcase MT2063_B0:\n\t\tdef = MT2063B0_defaults;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -ENODEV;\n\t}\n\n\twhile (status >= 0 && *def) {\n\t\tu8 reg = *def++;\n\t\tu8 val = *def++;\n\t\tstatus = mt2063_write(state, reg, &val, 1);\n\t}\n\tif (status < 0)\n\t\treturn status;\n\n\t/*  Wait for FIFF location to complete.  */\n\tFCRUN = 1;\n\tmaxReads = 10;\n\twhile (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {\n\t\tmsleep(2);\n\t\tstatus = mt2063_read(state,\n\t\t\t\t\t MT2063_REG_XO_STATUS,\n\t\t\t\t\t &state->\n\t\t\t\t\t reg[MT2063_REG_XO_STATUS], 1);\n\t\tFCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;\n\t}\n\n\tif (FCRUN != 0 || status < 0)\n\t\treturn -ENODEV;\n\n\tstatus = mt2063_read(state,\n\t\t\t   MT2063_REG_FIFFC,\n\t\t\t   &state->reg[MT2063_REG_FIFFC], 1);\n\tif (status < 0)\n\t\treturn status;\n\n\t/* Read back all the registers from the tuner */\n\tstatus = mt2063_read(state,\n\t\t\t\tMT2063_REG_PART_REV,\n\t\t\t\tstate->reg, MT2063_REG_END_REGS);\n\tif (status < 0)\n\t\treturn status;\n\n\t/*  Initialize the tuner state.  */\n\tstate->tuner_id = state->reg[MT2063_REG_PART_REV];\n\tstate->AS_Data.f_ref = MT2063_REF_FREQ;\n\tstate->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *\n\t\t\t\t      ((u32) state->reg[MT2063_REG_FIFFC] + 640);\n\tstate->AS_Data.f_if1_bw = MT2063_IF1_BW;\n\tstate->AS_Data.f_out = 43750000UL;\n\tstate->AS_Data.f_out_bw = 6750000UL;\n\tstate->AS_Data.f_zif_bw = MT2063_ZIF_BW;\n\tstate->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;\n\tstate->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;\n\tstate->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;\n\tstate->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;\n\tstate->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;\n\tstate->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;\n\tstate->AS_Data.f_LO1 = 2181000000UL;\n\tstate->AS_Data.f_LO2 = 1486249786UL;\n\tstate->f_IF1_actual = state->AS_Data.f_if1_Center;\n\tstate->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;\n\tstate->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;\n\tstate->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;\n\tstate->num_regs = MT2063_REG_END_REGS;\n\tstate->AS_Data.avoidDECT = MT2063_AVOID_BOTH;\n\tstate->ctfilt_sw = 0;\n\n\tstate->CTFiltMax[0] = 69230000;\n\tstate->CTFiltMax[1] = 105770000;\n\tstate->CTFiltMax[2] = 140350000;\n\tstate->CTFiltMax[3] = 177110000;\n\tstate->CTFiltMax[4] = 212860000;\n\tstate->CTFiltMax[5] = 241130000;\n\tstate->CTFiltMax[6] = 274370000;\n\tstate->CTFiltMax[7] = 309820000;\n\tstate->CTFiltMax[8] = 342450000;\n\tstate->CTFiltMax[9] = 378870000;\n\tstate->CTFiltMax[10] = 416210000;\n\tstate->CTFiltMax[11] = 456500000;\n\tstate->CTFiltMax[12] = 495790000;\n\tstate->CTFiltMax[13] = 534530000;\n\tstate->CTFiltMax[14] = 572610000;\n\tstate->CTFiltMax[15] = 598970000;\n\tstate->CTFiltMax[16] = 635910000;\n\tstate->CTFiltMax[17] = 672130000;\n\tstate->CTFiltMax[18] = 714840000;\n\tstate->CTFiltMax[19] = 739660000;\n\tstate->CTFiltMax[20] = 770410000;\n\tstate->CTFiltMax[21] = 814660000;\n\tstate->CTFiltMax[22] = 846950000;\n\tstate->CTFiltMax[23] = 867820000;\n\tstate->CTFiltMax[24] = 915980000;\n\tstate->CTFiltMax[25] = 947450000;\n\tstate->CTFiltMax[26] = 983110000;\n\tstate->CTFiltMax[27] = 1021630000;\n\tstate->CTFiltMax[28] = 1061870000;\n\tstate->CTFiltMax[29] = 1098330000;\n\tstate->CTFiltMax[30] = 1138990000;\n\n\t/*\n\t **   Fetch the FCU osc value and use it and the fRef value to\n\t **   scale all of the Band Max values\n\t */\n\n\tstate->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;\n\tstatus = mt2063_write(state, MT2063_REG_CTUNE_CTRL,\n\t\t\t      &state->reg[MT2063_REG_CTUNE_CTRL], 1);\n\tif (status < 0)\n\t\treturn status;\n\n\t/*  Read the ClearTune filter calibration value  */\n\tstatus = mt2063_read(state, MT2063_REG_FIFFC,\n\t\t\t     &state->reg[MT2063_REG_FIFFC], 1);\n\tif (status < 0)\n\t\treturn status;\n\n\tfcu_osc = state->reg[MT2063_REG_FIFFC];\n\n\tstate->reg[MT2063_REG_CTUNE_CTRL] = 0x00;\n\tstatus = mt2063_write(state, MT2063_REG_CTUNE_CTRL,\n\t\t\t      &state->reg[MT2063_REG_CTUNE_CTRL], 1);\n\tif (status < 0)\n\t\treturn status;\n\n\t/*  Adjust each of the values in the ClearTune filter cross-over table  */\n\tfor (i = 0; i < 31; i++)\n\t\tstate->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640);\n\n\tstatus = MT2063_SoftwareShutdown(state, 1);\n\tif (status < 0)\n\t\treturn status;\n\tstatus = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);\n\tif (status < 0)\n\t\treturn status;\n\n\tstate->init = true;\n\n\treturn 0;\n}",
        "static struct fwtty_port *fwserial_find_port(struct fwtty_peer *peer)\n{\n\tstruct fwtty_port **ports = peer->serial->ports;\n\tint i;\n": "static struct fwtty_port *fwserial_find_port(struct fwtty_peer *peer)\n{\n\tstruct fwtty_port **ports = peer->serial->ports;\n\tint i;\n\n\t/* must guarantee that previous port releases have completed */\n\tsynchronize_rcu();\n\n\t/* TODO: implement optional GUID-to-specific port # matching */\n\n\t/* find an unattached port (but not the loopback port, if present) */\n\tfor (i = 0; i < num_ttys; ++i) {\n\t\tspin_lock_bh(&ports[i]->lock);\n\t\tif (!ports[i]->peer) {\n\t\t\t/* claim port */\n\t\t\trcu_assign_pointer(ports[i]->peer, peer);\n\t\t\tspin_unlock_bh(&ports[i]->lock);\n\t\t\treturn ports[i];\n\t\t}\n\t\tspin_unlock_bh(&ports[i]->lock);\n\t}\n\treturn NULL;\n}",
        "static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\tu32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };\n\tixgbe_link_speed speed;": "static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\tu32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\t/* AN should have completed when the cable was plugged in.\n\t * Look for reasons to bail out.  Bail out if:\n\t * - FC autoneg is disabled, or if\n\t * - link is not up.\n\t */\n\tif (hw->fc.disable_fc_autoneg)\n\t\tgoto out;\n\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\tif (!link_up)\n\t\tgoto out;\n\n\t/* Check if auto-negotiation has completed */\n\tstatus = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);\n\tif (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {\n\t\tstatus = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\t\tgoto out;\n\t}\n\n\t/* Negotiate the flow control */\n\tstatus = ixgbe_negotiate_fc(hw, info[0], info[0],\n\t\t\t\t    FW_PHY_ACT_GET_LINK_INFO_FC_RX,\n\t\t\t\t    FW_PHY_ACT_GET_LINK_INFO_FC_TX,\n\t\t\t\t    FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,\n\t\t\t\t    FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);\n\nout:\n\tif (!status) {\n\t\thw->fc.fc_was_autonegged = true;\n\t} else {\n\t\thw->fc.fc_was_autonegged = false;\n\t\thw->fc.current_mode = hw->fc.requested_mode;\n\t}\n}",
        "static bool encrypt_packet(struct sk_buff *skb, struct noise_keypair *keypair)\n{\n\tunsigned int padding_len, plaintext_len, trailer_len;\n\tstruct scatterlist sg[MAX_SKB_FRAGS + 8];\n\tstruct message_data *header;": "static bool encrypt_packet(struct sk_buff *skb, struct noise_keypair *keypair)\n{\n\tunsigned int padding_len, plaintext_len, trailer_len;\n\tstruct scatterlist sg[MAX_SKB_FRAGS + 8];\n\tstruct message_data *header;\n\tstruct sk_buff *trailer;\n\tint num_frags;\n\n\t/* Force hash calculation before encryption so that flow analysis is\n\t * consistent over the inner packet.\n\t */\n\tskb_get_hash(skb);\n\n\t/* Calculate lengths. */\n\tpadding_len = calculate_skb_padding(skb);\n\ttrailer_len = padding_len + noise_encrypted_len(0);\n\tplaintext_len = skb->len + padding_len;\n\n\t/* Expand data section to have room for padding and auth tag. */\n\tnum_frags = skb_cow_data(skb, trailer_len, &trailer);\n\tif (unlikely(num_frags < 0 || num_frags > ARRAY_SIZE(sg)))\n\t\treturn false;\n\n\t/* Set the padding to zeros, and make sure it and the auth tag are part\n\t * of the skb.\n\t */\n\tmemset(skb_tail_pointer(trailer), 0, padding_len);\n\n\t/* Expand head section to have room for our header and the network\n\t * stack's headers.\n\t */\n\tif (unlikely(skb_cow_head(skb, DATA_PACKET_HEAD_ROOM) < 0))\n\t\treturn false;\n\n\t/* Finalize checksum calculation for the inner packet, if required. */\n\tif (unlikely(skb->ip_summed == CHECKSUM_PARTIAL &&\n\t\t     skb_checksum_help(skb)))\n\t\treturn false;\n\n\t/* Only after checksumming can we safely add on the padding at the end\n\t * and the header.\n\t */\n\tskb_set_inner_network_header(skb, 0);\n\theader = (struct message_data *)skb_push(skb, sizeof(*header));\n\theader->header.type = cpu_to_le32(MESSAGE_DATA);\n\theader->key_idx = keypair->remote_index;\n\theader->counter = cpu_to_le64(PACKET_CB(skb)->nonce);\n\tpskb_put(skb, trailer, trailer_len);\n\n\t/* Now we can encrypt the scattergather segments */\n\tsg_init_table(sg, num_frags);\n\tif (skb_to_sgvec(skb, sg, sizeof(struct message_data),\n\t\t\t noise_encrypted_len(plaintext_len)) <= 0)\n\t\treturn false;\n\treturn chacha20poly1305_encrypt_sg_inplace(sg, plaintext_len, NULL, 0,\n\t\t\t\t\t\t   PACKET_CB(skb)->nonce,\n\t\t\t\t\t\t   keypair->sending.key);\n}",
        "static int do_format(int drive, struct format_descr *tmp_format_req)\n{\n\tint ret;\n\n\tif (lock_fdc(drive))": "static int do_format(int drive, struct format_descr *tmp_format_req)\n{\n\tint ret;\n\n\tif (lock_fdc(drive))\n\t\treturn -EINTR;\n\n\tset_floppy(drive);\n\tif (!_floppy ||\n\t    _floppy->track > drive_params[current_drive].tracks ||\n\t    tmp_format_req->track >= _floppy->track ||\n\t    tmp_format_req->head >= _floppy->head ||\n\t    (_floppy->sect << 2) % (1 << FD_SIZECODE(_floppy)) ||\n\t    !_floppy->fmt_gap) {\n\t\tprocess_fd_request();\n\t\treturn -EINVAL;\n\t}\n\tformat_req = *tmp_format_req;\n\tcont = &format_cont;\n\tfloppy_errors = 0;\n\tret = wait_til_done(redo_format, true);\n\tif (ret == -EINTR)\n\t\treturn -EINTR;\n\tprocess_fd_request();\n\treturn ret;\n}",
        "static int hci_set_event_mask_page_2_sync(struct hci_dev *hdev)\n{\n\tu8 events[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\tbool changed = false;\n": "static int hci_set_event_mask_page_2_sync(struct hci_dev *hdev)\n{\n\tu8 events[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };\n\tbool changed = false;\n\n\t/* Set event mask page 2 if the HCI command for it is supported */\n\tif (!(hdev->commands[22] & 0x04))\n\t\treturn 0;\n\n\t/* If Connectionless Peripheral Broadcast central role is supported\n\t * enable all necessary events for it.\n\t */\n\tif (lmp_cpb_central_capable(hdev)) {\n\t\tevents[1] |= 0x40;\t/* Triggered Clock Capture */\n\t\tevents[1] |= 0x80;\t/* Synchronization Train Complete */\n\t\tevents[2] |= 0x10;\t/* Peripheral Page Response Timeout */\n\t\tevents[2] |= 0x20;\t/* CPB Channel Map Change */\n\t\tchanged = true;\n\t}\n\n\t/* If Connectionless Peripheral Broadcast peripheral role is supported\n\t * enable all necessary events for it.\n\t */\n\tif (lmp_cpb_peripheral_capable(hdev)) {\n\t\tevents[2] |= 0x01;\t/* Synchronization Train Received */\n\t\tevents[2] |= 0x02;\t/* CPB Receive */\n\t\tevents[2] |= 0x04;\t/* CPB Timeout */\n\t\tevents[2] |= 0x08;\t/* Truncated Page Complete */\n\t\tchanged = true;\n\t}\n\n\t/* Enable Authenticated Payload Timeout Expired event if supported */\n\tif (lmp_ping_capable(hdev) || hdev->le_features[0] & HCI_LE_PING) {\n\t\tevents[2] |= 0x80;\n\t\tchanged = true;\n\t}\n\n\t/* Some Broadcom based controllers indicate support for Set Event\n\t * Mask Page 2 command, but then actually do not support it. Since\n\t * the default value is all bits set to zero, the command is only\n\t * required if the event mask has to be changed. In case no change\n\t * to the event mask is needed, skip this command.\n\t */\n\tif (!changed)\n\t\treturn 0;\n\n\treturn __hci_cmd_sync_status(hdev, HCI_OP_SET_EVENT_MASK_PAGE_2,\n\t\t\t\t     sizeof(events), events, HCI_CMD_TIMEOUT);\n}",
        "static void ioc_refresh_vrate(struct ioc *ioc, struct ioc_now *now)\n{\n\ts64 pleft = ioc->period_at + ioc->period_us - now->now;\n\ts64 vperiod = ioc->period_us * ioc->vtime_base_rate;\n\ts64 vcomp, vcomp_min, vcomp_max;": "static void ioc_refresh_vrate(struct ioc *ioc, struct ioc_now *now)\n{\n\ts64 pleft = ioc->period_at + ioc->period_us - now->now;\n\ts64 vperiod = ioc->period_us * ioc->vtime_base_rate;\n\ts64 vcomp, vcomp_min, vcomp_max;\n\n\tlockdep_assert_held(&ioc->lock);\n\n\t/* we need some time left in this period */\n\tif (pleft <= 0)\n\t\tgoto done;\n\n\t/*\n\t * Calculate how much vrate should be adjusted to offset the error.\n\t * Limit the amount of adjustment and deduct the adjusted amount from\n\t * the error.\n\t */\n\tvcomp = -div64_s64(ioc->vtime_err, pleft);\n\tvcomp_min = -(ioc->vtime_base_rate >> 1);\n\tvcomp_max = ioc->vtime_base_rate;\n\tvcomp = clamp(vcomp, vcomp_min, vcomp_max);\n\n\tioc->vtime_err += vcomp * pleft;\n\n\tatomic64_set(&ioc->vtime_rate, ioc->vtime_base_rate + vcomp);\ndone:\n\t/* bound how much error can accumulate */\n\tioc->vtime_err = clamp(ioc->vtime_err, -vperiod, vperiod);\n}",
        "static int test_hints_case(const struct hints_case *hints_case)\n{\n\tstruct objagg_obj *objagg_obj;\n\tstruct objagg_hints *hints;\n\tstruct world world2 = {};": "static int test_hints_case(const struct hints_case *hints_case)\n{\n\tstruct objagg_obj *objagg_obj;\n\tstruct objagg_hints *hints;\n\tstruct world world2 = {};\n\tstruct world world = {};\n\tstruct objagg *objagg2;\n\tstruct objagg *objagg;\n\tconst char *errmsg;\n\tint i;\n\tint err;\n\n\tobjagg = objagg_create(&delta_ops, NULL, &world);\n\tif (IS_ERR(objagg))\n\t\treturn PTR_ERR(objagg);\n\n\tfor (i = 0; i < hints_case->key_ids_count; i++) {\n\t\tobjagg_obj = world_obj_get(&world, objagg,\n\t\t\t\t\t   hints_case->key_ids[i]);\n\t\tif (IS_ERR(objagg_obj)) {\n\t\t\terr = PTR_ERR(objagg_obj);\n\t\t\tgoto err_world_obj_get;\n\t\t}\n\t}\n\n\tpr_debug_stats(objagg);\n\terr = check_expect_stats(objagg, &hints_case->expect_stats, &errmsg);\n\tif (err) {\n\t\tpr_err(\"Stats: %s\\n\", errmsg);\n\t\tgoto err_check_expect_stats;\n\t}\n\n\thints = objagg_hints_get(objagg, OBJAGG_OPT_ALGO_SIMPLE_GREEDY);\n\tif (IS_ERR(hints)) {\n\t\terr = PTR_ERR(hints);\n\t\tgoto err_hints_get;\n\t}\n\n\tpr_debug_hints_stats(hints);\n\terr = check_expect_hints_stats(hints, &hints_case->expect_stats_hints,\n\t\t\t\t       &errmsg);\n\tif (err) {\n\t\tpr_err(\"Hints stats: %s\\n\", errmsg);\n\t\tgoto err_check_expect_hints_stats;\n\t}\n\n\tobjagg2 = objagg_create(&delta_ops, hints, &world2);\n\tif (IS_ERR(objagg2))\n\t\treturn PTR_ERR(objagg2);\n\n\tfor (i = 0; i < hints_case->key_ids_count; i++) {\n\t\tobjagg_obj = world_obj_get(&world2, objagg2,\n\t\t\t\t\t   hints_case->key_ids[i]);\n\t\tif (IS_ERR(objagg_obj)) {\n\t\t\terr = PTR_ERR(objagg_obj);\n\t\t\tgoto err_world2_obj_get;\n\t\t}\n\t}\n\n\tpr_debug_stats(objagg2);\n\terr = check_expect_stats(objagg2, &hints_case->expect_stats_hints,\n\t\t\t\t &errmsg);\n\tif (err) {\n\t\tpr_err(\"Stats2: %s\\n\", errmsg);\n\t\tgoto err_check_expect_stats2;\n\t}\n\n\terr = 0;\n\nerr_check_expect_stats2:\nerr_world2_obj_get:\n\tfor (i--; i >= 0; i--)\n\t\tworld_obj_put(&world2, objagg, hints_case->key_ids[i]);\n\ti = hints_case->key_ids_count;\n\tobjagg_destroy(objagg2);\nerr_check_expect_hints_stats:\n\tobjagg_hints_put(hints);\nerr_hints_get:\nerr_check_expect_stats:\nerr_world_obj_get:\n\tfor (i--; i >= 0; i--)\n\t\tworld_obj_put(&world, objagg, hints_case->key_ids[i]);\n\n\tobjagg_destroy(objagg);\n\treturn err;\n}",
        "static int record__aio_push(struct record *rec, struct mmap *map, off_t *off)\n{\n\tint ret, idx;\n\tint trace_fd = rec->session->data->file.fd;\n\tstruct record_aio aio = { .rec = rec, .size = 0 };": "static int record__aio_push(struct record *rec, struct mmap *map, off_t *off)\n{\n\tint ret, idx;\n\tint trace_fd = rec->session->data->file.fd;\n\tstruct record_aio aio = { .rec = rec, .size = 0 };\n\n\t/*\n\t * Call record__aio_sync() to wait till map->aio.data[] buffer\n\t * becomes available after previous aio write operation.\n\t */\n\n\tidx = record__aio_sync(map, false);\n\taio.data = map->aio.data[idx];\n\tret = perf_mmap__push(map, &aio, record__aio_pushfn);\n\tif (ret != 0) /* ret > 0 - no data, ret < 0 - error */\n\t\treturn ret;\n\n\trec->samples++;\n\tret = record__aio_write(&(map->aio.cblocks[idx]), trace_fd, aio.data, aio.size, *off);\n\tif (!ret) {\n\t\t*off += aio.size;\n\t\trec->bytes_written += aio.size;\n\t\tif (switch_output_size(rec))\n\t\t\ttrigger_hit(&switch_output_trigger);\n\t} else {\n\t\t/*\n\t\t * Decrement map->refcount incremented in record__aio_pushfn()\n\t\t * back if record__aio_write() operation failed to start, otherwise\n\t\t * map->refcount is decremented in record__aio_complete() after\n\t\t * aio write operation finishes successfully.\n\t\t */\n\t\tperf_mmap__put(&map->core);\n\t}\n\n\treturn ret;\n}",
        "static void timerlat_dump_stack(u64 latency)\n{\n\tstruct osnoise_instance *inst;\n\tstruct trace_buffer *buffer;\n\tstruct trace_stack *fstack;": "static void timerlat_dump_stack(u64 latency)\n{\n\tstruct osnoise_instance *inst;\n\tstruct trace_buffer *buffer;\n\tstruct trace_stack *fstack;\n\tunsigned int size;\n\n\t/*\n\t * trace only if latency > print_stack config, if enabled.\n\t */\n\tif (!osnoise_data.print_stack || osnoise_data.print_stack > latency)\n\t\treturn;\n\n\tpreempt_disable_notrace();\n\tfstack = this_cpu_ptr(&trace_stack);\n\tsize = fstack->stack_size;\n\n\trcu_read_lock();\n\tlist_for_each_entry_rcu(inst, &osnoise_instances, list) {\n\t\tbuffer = inst->tr->array_buffer.buffer;\n\t\t__timerlat_dump_stack(buffer, fstack, size);\n\n\t}\n\trcu_read_unlock();\n\tpreempt_enable_notrace();\n}",
        "static int INIT read_bunzip(struct bunzip_data *bd, char *outbuf, int len)\n{\n\tconst unsigned int *dbuf;\n\tint pos, xcurrent, previous, gotcount;\n": "static int INIT read_bunzip(struct bunzip_data *bd, char *outbuf, int len)\n{\n\tconst unsigned int *dbuf;\n\tint pos, xcurrent, previous, gotcount;\n\n\t/* If last read was short due to end of file, return last block now */\n\tif (bd->writeCount < 0)\n\t\treturn bd->writeCount;\n\n\tgotcount = 0;\n\tdbuf = bd->dbuf;\n\tpos = bd->writePos;\n\txcurrent = bd->writeCurrent;\n\n\t/* We will always have pending decoded data to write into the output\n\t   buffer unless this is the very first call (in which case we haven't\n\t   Huffman-decoded a block into the intermediate buffer yet). */\n\n\tif (bd->writeCopies) {\n\t\t/* Inside the loop, writeCopies means extra copies (beyond 1) */\n\t\t--bd->writeCopies;\n\t\t/* Loop outputting bytes */\n\t\tfor (;;) {\n\t\t\t/* If the output buffer is full, snapshot\n\t\t\t * state and return */\n\t\t\tif (gotcount >= len) {\n\t\t\t\tbd->writePos = pos;\n\t\t\t\tbd->writeCurrent = xcurrent;\n\t\t\t\tbd->writeCopies++;\n\t\t\t\treturn len;\n\t\t\t}\n\t\t\t/* Write next byte into output buffer, updating CRC */\n\t\t\toutbuf[gotcount++] = xcurrent;\n\t\t\tbd->writeCRC = (((bd->writeCRC) << 8)\n\t\t\t\t^bd->crc32Table[((bd->writeCRC) >> 24)\n\t\t\t\t^xcurrent]);\n\t\t\t/* Loop now if we're outputting multiple\n\t\t\t * copies of this byte */\n\t\t\tif (bd->writeCopies) {\n\t\t\t\t--bd->writeCopies;\n\t\t\t\tcontinue;\n\t\t\t}\ndecode_next_byte:\n\t\t\tif (!bd->writeCount--)\n\t\t\t\tbreak;\n\t\t\t/* Follow sequence vector to undo\n\t\t\t * Burrows-Wheeler transform */\n\t\t\tprevious = xcurrent;\n\t\t\tpos = dbuf[pos];\n\t\t\txcurrent = pos&0xff;\n\t\t\tpos >>= 8;\n\t\t\t/* After 3 consecutive copies of the same\n\t\t\t   byte, the 4th is a repeat count.  We count\n\t\t\t   down from 4 instead *of counting up because\n\t\t\t   testing for non-zero is faster */\n\t\t\tif (--bd->writeRunCountdown) {\n\t\t\t\tif (xcurrent != previous)\n\t\t\t\t\tbd->writeRunCountdown = 4;\n\t\t\t} else {\n\t\t\t\t/* We have a repeated run, this byte\n\t\t\t\t * indicates the count */\n\t\t\t\tbd->writeCopies = xcurrent;\n\t\t\t\txcurrent = previous;\n\t\t\t\tbd->writeRunCountdown = 5;\n\t\t\t\t/* Sometimes there are just 3 bytes\n\t\t\t\t * (run length 0) */\n\t\t\t\tif (!bd->writeCopies)\n\t\t\t\t\tgoto decode_next_byte;\n\t\t\t\t/* Subtract the 1 copy we'd output\n\t\t\t\t * anyway to get extras */\n\t\t\t\t--bd->writeCopies;\n\t\t\t}\n\t\t}\n\t\t/* Decompression of this block completed successfully */\n\t\tbd->writeCRC = ~bd->writeCRC;\n\t\tbd->totalCRC = ((bd->totalCRC << 1) |\n\t\t\t\t(bd->totalCRC >> 31)) ^ bd->writeCRC;\n\t\t/* If this block had a CRC error, force file level CRC error. */\n\t\tif (bd->writeCRC != bd->headerCRC) {\n\t\t\tbd->totalCRC = bd->headerCRC+1;\n\t\t\treturn RETVAL_LAST_BLOCK;\n\t\t}\n\t}\n\n\t/* Refill the intermediate buffer by Huffman-decoding next\n\t * block of input */\n\t/* (previous is just a convenient unused temp variable here) */\n\tprevious = get_next_block(bd);\n\tif (previous) {\n\t\tbd->writeCount = previous;\n\t\treturn (previous != RETVAL_LAST_BLOCK) ? previous : gotcount;\n\t}\n\tbd->writeCRC = 0xffffffffUL;\n\tpos = bd->writePos;\n\txcurrent = bd->writeCurrent;\n\tgoto decode_next_byte;\n}",
        "static int fixup_call_args(struct bpf_verifier_env *env)\n{\n#ifndef CONFIG_BPF_JIT_ALWAYS_ON\n\tstruct bpf_prog *prog = env->prog;\n\tstruct bpf_insn *insn = prog->insnsi;": "static int fixup_call_args(struct bpf_verifier_env *env)\n{\n#ifndef CONFIG_BPF_JIT_ALWAYS_ON\n\tstruct bpf_prog *prog = env->prog;\n\tstruct bpf_insn *insn = prog->insnsi;\n\tbool has_kfunc_call = bpf_prog_has_kfunc_call(prog);\n\tint i, depth;\n#endif\n\tint err = 0;\n\n\tif (env->prog->jit_requested &&\n\t    !bpf_prog_is_dev_bound(env->prog->aux)) {\n\t\terr = jit_subprogs(env);\n\t\tif (err == 0)\n\t\t\treturn 0;\n\t\tif (err == -EFAULT)\n\t\t\treturn err;\n\t}\n#ifndef CONFIG_BPF_JIT_ALWAYS_ON\n\tif (has_kfunc_call) {\n\t\tverbose(env, \"calling kernel functions are not allowed in non-JITed programs\\n\");\n\t\treturn -EINVAL;\n\t}\n\tif (env->subprog_cnt > 1 && env->prog->aux->tail_call_reachable) {\n\t\t/* When JIT fails the progs with bpf2bpf calls and tail_calls\n\t\t * have to be rejected, since interpreter doesn't support them yet.\n\t\t */\n\t\tverbose(env, \"tail_calls are not allowed in non-JITed programs with bpf-to-bpf calls\\n\");\n\t\treturn -EINVAL;\n\t}\n\tfor (i = 0; i < prog->len; i++, insn++) {\n\t\tif (bpf_pseudo_func(insn)) {\n\t\t\t/* When JIT fails the progs with callback calls\n\t\t\t * have to be rejected, since interpreter doesn't support them yet.\n\t\t\t */\n\t\t\tverbose(env, \"callbacks are not allowed in non-JITed programs\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (!bpf_pseudo_call(insn))\n\t\t\tcontinue;\n\t\tdepth = get_callee_stack_depth(env, insn, i);\n\t\tif (depth < 0)\n\t\t\treturn depth;\n\t\tbpf_patch_call_args(insn, depth);\n\t}\n\terr = 0;\n#endif\n\treturn err;\n}",
        "static int alloc_try_nid_min_reserved_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;": "static int alloc_try_nid_min_reserved_generic_check(void)\n{\n\tstruct memblock_region *rgn = &memblock.reserved.regions[0];\n\tvoid *allocated_ptr = NULL;\n\tchar *b;\n\n\tphys_addr_t r1_size = SZ_128;\n\tphys_addr_t r2_size = SZ_64;\n\tphys_addr_t total_size = r1_size + r2_size;\n\tphys_addr_t min_addr;\n\tphys_addr_t max_addr;\n\tphys_addr_t reserved_base;\n\n\tsetup_memblock();\n\n\tmax_addr = memblock_end_of_DRAM();\n\tmin_addr = max_addr - r2_size;\n\treserved_base = min_addr - r1_size;\n\n\tmemblock_reserve(reserved_base, r1_size);\n\n\tallocated_ptr = memblock_alloc_try_nid(r2_size, SMP_CACHE_BYTES,\n\t\t\t\t\t       min_addr, max_addr, NUMA_NO_NODE);\n\tb = (char *)allocated_ptr;\n\n\tassert(allocated_ptr);\n\tassert(*b == 0);\n\n\tassert(rgn->size == total_size);\n\tassert(rgn->base == reserved_base);\n\n\tassert(memblock.reserved.cnt == 1);\n\tassert(memblock.reserved.total_size == total_size);\n\n\treturn 0;\n}",
        "static void cas_netpoll(struct net_device *dev)\n{\n\tstruct cas *cp = netdev_priv(dev);\n\n\tcas_disable_irq(cp, 0);": "static void cas_netpoll(struct net_device *dev)\n{\n\tstruct cas *cp = netdev_priv(dev);\n\n\tcas_disable_irq(cp, 0);\n\tcas_interrupt(cp->pdev->irq, dev);\n\tcas_enable_irq(cp, 0);\n\n#ifdef USE_PCI_INTB\n\tif (N_RX_COMP_RINGS > 1) {\n\t\t/* cas_interrupt1(); */\n\t}\n#endif\n#ifdef USE_PCI_INTC\n\tif (N_RX_COMP_RINGS > 2) {\n\t\t/* cas_interruptN(); */\n\t}\n#endif\n#ifdef USE_PCI_INTD\n\tif (N_RX_COMP_RINGS > 3) {\n\t\t/* cas_interruptN(); */\n\t}\n#endif\n}",
        "static int rt6245_init_device_properties(struct device *dev)\n{\n\tconst struct {\n\t\tconst char *name;\n\t\tunsigned int reg;": "static int rt6245_init_device_properties(struct device *dev)\n{\n\tconst struct {\n\t\tconst char *name;\n\t\tunsigned int reg;\n\t} rt6245_props[] = {\n\t\t{ \"richtek,oc-level-select\",  RT6245_VIRT_OCLIMIT },\n\t\t{ \"richtek,ot-level-select\", RT6245_VIRT_OTLEVEL },\n\t\t{ \"richtek,pgdly-time-select\", RT6245_VIRT_PGDLYTIME },\n\t\t{ \"richtek,switch-freq-select\", RT6245_VIRT_SWFREQ }\n\t};\n\tstruct regmap *regmap = dev_get_regmap(dev, NULL);\n\tu8 propval;\n\tint i, ret;\n\n\tfor (i = 0; i < ARRAY_SIZE(rt6245_props); i++) {\n\t\tret = device_property_read_u8(dev, rt6245_props[i].name, &propval);\n\t\tif (ret)\n\t\t\tcontinue;\n\n\t\tret = regmap_write(regmap, rt6245_props[i].reg, propval);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"Fail to apply [%s:%d]\\n\", rt6245_props[i].name, propval);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\treturn 0;\n}",
        "static bool tcpm_ams_interruptible(struct tcpm_port *port)\n{\n\tswitch (port->ams) {\n\t/* Interruptible AMS */\n\tcase NONE_AMS:": "static bool tcpm_ams_interruptible(struct tcpm_port *port)\n{\n\tswitch (port->ams) {\n\t/* Interruptible AMS */\n\tcase NONE_AMS:\n\tcase SECURITY:\n\tcase FIRMWARE_UPDATE:\n\tcase DISCOVER_IDENTITY:\n\tcase SOURCE_STARTUP_CABLE_PLUG_DISCOVER_IDENTITY:\n\tcase DISCOVER_SVIDS:\n\tcase DISCOVER_MODES:\n\tcase DFP_TO_UFP_ENTER_MODE:\n\tcase DFP_TO_UFP_EXIT_MODE:\n\tcase DFP_TO_CABLE_PLUG_ENTER_MODE:\n\tcase DFP_TO_CABLE_PLUG_EXIT_MODE:\n\tcase UNSTRUCTURED_VDMS:\n\tcase STRUCTURED_VDMS:\n\tcase COUNTRY_INFO:\n\tcase COUNTRY_CODES:\n\t\tbreak;\n\t/* Non-Interruptible AMS */\n\tdefault:\n\t\tif (port->in_ams)\n\t\t\treturn false;\n\t\tbreak;\n\t}\n\n\treturn true;\n}",
        "static int mlxsw_sp_mp_hash_init(struct mlxsw_sp *mlxsw_sp)\n{\n\tbool old_inc_parsing_depth, new_inc_parsing_depth;\n\tstruct mlxsw_sp_mp_hash_config config = {};\n\tchar recr2_pl[MLXSW_REG_RECR2_LEN];": "static int mlxsw_sp_mp_hash_init(struct mlxsw_sp *mlxsw_sp)\n{\n\tbool old_inc_parsing_depth, new_inc_parsing_depth;\n\tstruct mlxsw_sp_mp_hash_config config = {};\n\tchar recr2_pl[MLXSW_REG_RECR2_LEN];\n\tunsigned long bit;\n\tu32 seed;\n\tint err;\n\n\tseed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 0);\n\tmlxsw_reg_recr2_pack(recr2_pl, seed);\n\tmlxsw_sp_mp4_hash_init(mlxsw_sp, &config);\n\tmlxsw_sp_mp6_hash_init(mlxsw_sp, &config);\n\n\told_inc_parsing_depth = mlxsw_sp->router->inc_parsing_depth;\n\tnew_inc_parsing_depth = config.inc_parsing_depth;\n\terr = mlxsw_sp_mp_hash_parsing_depth_adjust(mlxsw_sp,\n\t\t\t\t\t\t    old_inc_parsing_depth,\n\t\t\t\t\t\t    new_inc_parsing_depth);\n\tif (err)\n\t\treturn err;\n\n\tfor_each_set_bit(bit, config.headers, __MLXSW_REG_RECR2_HEADER_CNT)\n\t\tmlxsw_reg_recr2_outer_header_enables_set(recr2_pl, bit, 1);\n\tfor_each_set_bit(bit, config.fields, __MLXSW_REG_RECR2_FIELD_CNT)\n\t\tmlxsw_reg_recr2_outer_header_fields_enable_set(recr2_pl, bit, 1);\n\tfor_each_set_bit(bit, config.inner_headers, __MLXSW_REG_RECR2_HEADER_CNT)\n\t\tmlxsw_reg_recr2_inner_header_enables_set(recr2_pl, bit, 1);\n\tfor_each_set_bit(bit, config.inner_fields, __MLXSW_REG_RECR2_INNER_FIELD_CNT)\n\t\tmlxsw_reg_recr2_inner_header_fields_enable_set(recr2_pl, bit, 1);\n\n\terr = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(recr2), recr2_pl);\n\tif (err)\n\t\tgoto err_reg_write;\n\n\treturn 0;\n\nerr_reg_write:\n\tmlxsw_sp_mp_hash_parsing_depth_adjust(mlxsw_sp, new_inc_parsing_depth,\n\t\t\t\t\t      old_inc_parsing_depth);\n\treturn err;\n}",
        "static int ite_tx_ir(struct rc_dev *rcdev, unsigned *txbuf, unsigned n)\n{\n\tunsigned long flags;\n\tstruct ite_dev *dev = rcdev->priv;\n\tbool is_pulse = false;": "static int ite_tx_ir(struct rc_dev *rcdev, unsigned *txbuf, unsigned n)\n{\n\tunsigned long flags;\n\tstruct ite_dev *dev = rcdev->priv;\n\tbool is_pulse = false;\n\tint remaining_us, fifo_avail, fifo_remaining, last_idx = 0;\n\tint max_rle_us, next_rle_us;\n\tint ret = n;\n\tu8 last_sent[ITE_TX_FIFO_LEN];\n\tu8 val;\n\n\t/* clear the array just in case */\n\tmemset(last_sent, 0, sizeof(last_sent));\n\n\tspin_lock_irqsave(&dev->lock, flags);\n\n\t/* let everybody know we're now transmitting */\n\tdev->transmitting = true;\n\n\t/* and set the carrier values for transmission */\n\tite_set_carrier_params(dev);\n\n\t/* calculate how much time we can send in one byte */\n\tmax_rle_us =\n\t    (ITE_BAUDRATE_DIVISOR * sample_period *\n\t     ITE_TX_MAX_RLE) / 1000;\n\n\t/* disable the receiver */\n\tdev->params->disable_rx(dev);\n\n\t/* this is where we'll begin filling in the FIFO, until it's full.\n\t * then we'll just activate the interrupt, wait for it to wake us up\n\t * again, disable it, continue filling the FIFO... until everything\n\t * has been pushed out */\n\tfifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev);\n\n\twhile (n > 0) {\n\t\t/* transmit the next sample */\n\t\tis_pulse = !is_pulse;\n\t\tremaining_us = *(txbuf++);\n\t\tn--;\n\n\t\tdev_dbg(&dev->rdev->dev, \"%s: %d\\n\",\n\t\t\tis_pulse ? \"pulse\" : \"space\", remaining_us);\n\n\t\t/* repeat while the pulse is non-zero length */\n\t\twhile (remaining_us > 0) {\n\t\t\tif (remaining_us > max_rle_us)\n\t\t\t\tnext_rle_us = max_rle_us;\n\n\t\t\telse\n\t\t\t\tnext_rle_us = remaining_us;\n\n\t\t\tremaining_us -= next_rle_us;\n\n\t\t\t/* check what's the length we have to pump out */\n\t\t\tval = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us;\n\n\t\t\t/* put it into the sent buffer */\n\t\t\tlast_sent[last_idx++] = val;\n\t\t\tlast_idx &= (ITE_TX_FIFO_LEN);\n\n\t\t\t/* encode it for 7 bits */\n\t\t\tval = (val - 1) & ITE_TX_RLE_MASK;\n\n\t\t\t/* take into account pulse/space prefix */\n\t\t\tif (is_pulse)\n\t\t\t\tval |= ITE_TX_PULSE;\n\n\t\t\telse\n\t\t\t\tval |= ITE_TX_SPACE;\n\n\t\t\t/*\n\t\t\t * if we get to 0 available, read again, just in case\n\t\t\t * some other slot got freed\n\t\t\t */\n\t\t\tif (fifo_avail <= 0)\n\t\t\t\tfifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev);\n\n\t\t\t/* if it's still full */\n\t\t\tif (fifo_avail <= 0) {\n\t\t\t\t/* enable the tx interrupt */\n\t\t\t\tdev->params->enable_tx_interrupt(dev);\n\n\t\t\t\t/* drop the spinlock */\n\t\t\t\tspin_unlock_irqrestore(&dev->lock, flags);\n\n\t\t\t\t/* wait for the FIFO to empty enough */\n\t\t\t\twait_event_interruptible(dev->tx_queue,\n\t\t\t\t\t(fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev)) >= 8);\n\n\t\t\t\t/* get the spinlock again */\n\t\t\t\tspin_lock_irqsave(&dev->lock, flags);\n\n\t\t\t\t/* disable the tx interrupt again. */\n\t\t\t\tdev->params->disable_tx_interrupt(dev);\n\t\t\t}\n\n\t\t\t/* now send the byte through the FIFO */\n\t\t\tdev->params->put_tx_byte(dev, val);\n\t\t\tfifo_avail--;\n\t\t}\n\t}\n\n\t/* wait and don't return until the whole FIFO has been sent out;\n\t * otherwise we could configure the RX carrier params instead of the\n\t * TX ones while the transmission is still being performed! */\n\tfifo_remaining = dev->params->get_tx_used_slots(dev);\n\tremaining_us = 0;\n\twhile (fifo_remaining > 0) {\n\t\tfifo_remaining--;\n\t\tlast_idx--;\n\t\tlast_idx &= (ITE_TX_FIFO_LEN - 1);\n\t\tremaining_us += last_sent[last_idx];\n\t}\n\tremaining_us = (remaining_us * max_rle_us) / (ITE_TX_MAX_RLE);\n\n\t/* drop the spinlock while we sleep */\n\tspin_unlock_irqrestore(&dev->lock, flags);\n\n\t/* sleep remaining_us microseconds */\n\tmdelay(DIV_ROUND_UP(remaining_us, 1000));\n\n\t/* reacquire the spinlock */\n\tspin_lock_irqsave(&dev->lock, flags);\n\n\t/* now we're not transmitting anymore */\n\tdev->transmitting = false;\n\n\t/* and set the carrier values for reception */\n\tite_set_carrier_params(dev);\n\n\t/* re-enable the receiver */\n\tdev->params->enable_rx(dev);\n\n\t/* notify transmission end */\n\twake_up_interruptible(&dev->tx_ended);\n\n\tspin_unlock_irqrestore(&dev->lock, flags);\n\n\treturn ret;\n}",
        "static void cnic_set_bnx2_mac(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tu32 val;\n": "static void cnic_set_bnx2_mac(struct cnic_dev *dev)\n{\n\tstruct cnic_local *cp = dev->cnic_priv;\n\tu32 val;\n\n\tval = cp->func << 2;\n\n\tcp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);\n\n\tval = cnic_reg_rd_ind(dev, cp->shmem_base +\n\t\t\t      BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);\n\tdev->mac_addr[0] = (u8) (val >> 8);\n\tdev->mac_addr[1] = (u8) val;\n\n\tCNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);\n\n\tval = cnic_reg_rd_ind(dev, cp->shmem_base +\n\t\t\t      BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);\n\tdev->mac_addr[2] = (u8) (val >> 24);\n\tdev->mac_addr[3] = (u8) (val >> 16);\n\tdev->mac_addr[4] = (u8) (val >> 8);\n\tdev->mac_addr[5] = (u8) val;\n\n\tCNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);\n\n\tval = 4 | BNX2_RPM_SORT_USER2_BC_EN;\n\tif (BNX2_CHIP(cp) != BNX2_CHIP_5709)\n\t\tval |= BNX2_RPM_SORT_USER2_PROM_VLAN;\n\n\tCNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);\n\tCNIC_WR(dev, BNX2_RPM_SORT_USER2, val);\n\tCNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);\n}",
        "static void rkisp1_params_config_parameter(struct rkisp1_params *params)\n{\n\tstruct rkisp1_cif_isp_hst_config hst = rkisp1_hst_params_default_config;\n\n\tparams->ops->awb_meas_config(params, &rkisp1_awb_params_default_config);": "static void rkisp1_params_config_parameter(struct rkisp1_params *params)\n{\n\tstruct rkisp1_cif_isp_hst_config hst = rkisp1_hst_params_default_config;\n\n\tparams->ops->awb_meas_config(params, &rkisp1_awb_params_default_config);\n\tparams->ops->awb_meas_enable(params, &rkisp1_awb_params_default_config,\n\t\t\t\t     true);\n\n\tparams->ops->aec_config(params, &rkisp1_aec_params_default_config);\n\trkisp1_param_set_bits(params, RKISP1_CIF_ISP_EXP_CTRL,\n\t\t\t      RKISP1_CIF_ISP_EXP_ENA);\n\n\tparams->ops->afm_config(params, &rkisp1_afc_params_default_config);\n\trkisp1_param_set_bits(params, RKISP1_CIF_ISP_AFM_CTRL,\n\t\t\t      RKISP1_CIF_ISP_AFM_ENA);\n\n\tmemset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));\n\tparams->ops->hst_config(params, &hst);\n\trkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,\n\t\t\t      rkisp1_hst_params_default_config.mode);\n\n\t/* set the  range */\n\tif (params->quantization == V4L2_QUANTIZATION_FULL_RANGE)\n\t\trkisp1_csm_config(params, true);\n\telse\n\t\trkisp1_csm_config(params, false);\n\n\tspin_lock_irq(&params->config_lock);\n\n\t/* apply the first buffer if there is one already */\n\trkisp1_params_apply_params_cfg(params, 0);\n\n\tspin_unlock_irq(&params->config_lock);\n}",
        "static int w1_f23_write(struct w1_slave *sl, int addr, int len, const u8 *data)\n{\n#ifdef CONFIG_W1_SLAVE_DS2433_CRC\n\tstruct w1_f23_data *f23 = sl->family_data;\n#endif": "static int w1_f23_write(struct w1_slave *sl, int addr, int len, const u8 *data)\n{\n#ifdef CONFIG_W1_SLAVE_DS2433_CRC\n\tstruct w1_f23_data *f23 = sl->family_data;\n#endif\n\tu8 wrbuf[4];\n\tu8 rdbuf[W1_PAGE_SIZE + 3];\n\tu8 es = (addr + len - 1) & 0x1f;\n\n\t/* Write the data to the scratchpad */\n\tif (w1_reset_select_slave(sl))\n\t\treturn -1;\n\n\twrbuf[0] = W1_F23_WRITE_SCRATCH;\n\twrbuf[1] = addr & 0xff;\n\twrbuf[2] = addr >> 8;\n\n\tw1_write_block(sl->master, wrbuf, 3);\n\tw1_write_block(sl->master, data, len);\n\n\t/* Read the scratchpad and verify */\n\tif (w1_reset_select_slave(sl))\n\t\treturn -1;\n\n\tw1_write_8(sl->master, W1_F23_READ_SCRATCH);\n\tw1_read_block(sl->master, rdbuf, len + 3);\n\n\t/* Compare what was read against the data written */\n\tif ((rdbuf[0] != wrbuf[1]) || (rdbuf[1] != wrbuf[2]) ||\n\t    (rdbuf[2] != es) || (memcmp(data, &rdbuf[3], len) != 0))\n\t\treturn -1;\n\n\t/* Copy the scratchpad to EEPROM */\n\tif (w1_reset_select_slave(sl))\n\t\treturn -1;\n\n\twrbuf[0] = W1_F23_COPY_SCRATCH;\n\twrbuf[3] = es;\n\tw1_write_block(sl->master, wrbuf, 4);\n\n\t/* Sleep for 5 ms to wait for the write to complete */\n\tmsleep(5);\n\n\t/* Reset the bus to wake up the EEPROM (this may not be needed) */\n\tw1_reset_bus(sl->master);\n#ifdef CONFIG_W1_SLAVE_DS2433_CRC\n\tf23->validcrc &= ~(1 << (addr >> W1_PAGE_BITS));\n#endif\n\treturn 0;\n}",
        "static void tpacpi_send_radiosw_update(void)\n{\n\tint wlsw;\n\n\t/*": "static void tpacpi_send_radiosw_update(void)\n{\n\tint wlsw;\n\n\t/*\n\t * We must sync all rfkill controllers *before* issuing any\n\t * rfkill input events, or we will race the rfkill core input\n\t * handler.\n\t *\n\t * tpacpi_inputdev_send_mutex works as a synchronization point\n\t * for the above.\n\t *\n\t * We optimize to avoid numerous calls to hotkey_get_wlsw.\n\t */\n\n\twlsw = hotkey_get_wlsw();\n\n\t/* Sync hw blocking state first if it is hw-blocked */\n\tif (wlsw == TPACPI_RFK_RADIO_OFF)\n\t\ttpacpi_rfk_update_hwblock_state(true);\n\n\t/* Sync hw blocking state last if it is hw-unblocked */\n\tif (wlsw == TPACPI_RFK_RADIO_ON)\n\t\ttpacpi_rfk_update_hwblock_state(false);\n\n\t/* Issue rfkill input event for WLSW switch */\n\tif (!(wlsw < 0)) {\n\t\tmutex_lock(&tpacpi_inputdev_send_mutex);\n\n\t\tinput_report_switch(tpacpi_inputdev,\n\t\t\t\t    SW_RFKILL_ALL, (wlsw > 0));\n\t\tinput_sync(tpacpi_inputdev);\n\n\t\tmutex_unlock(&tpacpi_inputdev_send_mutex);\n\t}\n\n\t/*\n\t * this can be unconditional, as we will poll state again\n\t * if userspace uses the notify to read data\n\t */\n\thotkey_radio_sw_notify_change();\n}",
        "static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct qcom_icc_provider *qp;\n\tstruct qcom_icc_node *qn;\n\tstruct icc_provider *provider;": "static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)\n{\n\tstruct qcom_icc_provider *qp;\n\tstruct qcom_icc_node *qn;\n\tstruct icc_provider *provider;\n\tstruct icc_node *n;\n\tu64 sum_bw;\n\tu64 max_peak_bw;\n\tu64 rate;\n\tu32 agg_avg = 0;\n\tu32 agg_peak = 0;\n\tint ret, i;\n\n\tqn = src->data;\n\tprovider = src->provider;\n\tqp = to_qcom_provider(provider);\n\n\tlist_for_each_entry(n, &provider->nodes, node_list)\n\t\tprovider->aggregate(n, 0, n->avg_bw, n->peak_bw,\n\t\t\t\t    &agg_avg, &agg_peak);\n\n\tsum_bw = icc_units_to_bps(agg_avg);\n\tmax_peak_bw = icc_units_to_bps(agg_peak);\n\n\tif (!qn->qos.ap_owned) {\n\t\t/* send bandwidth request message to the RPM processor */\n\t\tret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);\n\t\tif (ret)\n\t\t\treturn ret;\n\t} else if (qn->qos.qos_mode != -1) {\n\t\t/* set bandwidth directly from the AP */\n\t\tret = qcom_icc_qos_set(src, sum_bw);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\trate = max(sum_bw, max_peak_bw);\n\n\tdo_div(rate, qn->buswidth);\n\trate = min_t(u64, rate, LONG_MAX);\n\n\tfor (i = 0; i < qp->num_clks; i++) {\n\t\tif (qp->bus_clk_rate[i] == rate)\n\t\t\tcontinue;\n\n\t\tret = clk_set_rate(qp->bus_clks[i].clk, rate);\n\t\tif (ret) {\n\t\t\tpr_err(\"%s clk_set_rate error: %d\\n\",\n\t\t\t       qp->bus_clks[i].id, ret);\n\t\t\treturn ret;\n\t\t}\n\t\tqp->bus_clk_rate[i] = rate;\n\t}\n\n\treturn 0;\n}",
        "static int choose_times(int msec, int *c1p, int *c2p)\n{\n\t/*\n\t * Choose two timecodes which add to 'msec' as near as\n\t * possible.  The first returned is the 'on' or 'off' time.": "static int choose_times(int msec, int *c1p, int *c2p)\n{\n\t/*\n\t * Choose two timecodes which add to 'msec' as near as\n\t * possible.  The first returned is the 'on' or 'off' time.\n\t * The second is to be used as a 'fade-on' or 'fade-off' time.\n\t * If 'msec' is even, the first will not be smaller than the\n\t * second.  If 'msec' is odd, the first will not be larger\n\t * than the second.\n\t * If we cannot get a sum within 1/8 of 'msec' fail with\n\t * -EINVAL, otherwise return the sum that was achieved, plus 1\n\t * if the first is smaller.\n\t * If two possibilities are equally good (e.g. 512+0,\n\t * 256+256), choose the first pair so there is more\n\t * change-time visible (i.e. it is softer).\n\t */\n\tint c1, c2;\n\tint tmax = msec * 9 / 8;\n\tint tmin = msec * 7 / 8;\n\tint diff = 65536;\n\n\t/* We start at '1' to ensure we never even think of choosing a\n\t * total time of '0'.\n\t */\n\tfor (c1 = 1; c1 < TIMECODES; c1++) {\n\t\tint t = time_codes[c1];\n\t\tif (t*2 < tmin)\n\t\t\tcontinue;\n\t\tif (t > tmax)\n\t\t\tbreak;\n\t\tfor (c2 = 0; c2 <= c1; c2++) {\n\t\t\tint tt = t + time_codes[c2];\n\t\t\tint d;\n\t\t\tif (tt < tmin)\n\t\t\t\tcontinue;\n\t\t\tif (tt > tmax)\n\t\t\t\tbreak;\n\t\t\t/* This works! */\n\t\t\td = abs(msec - tt);\n\t\t\tif (d >= diff)\n\t\t\t\tcontinue;\n\t\t\t/* Best yet */\n\t\t\t*c1p = c1;\n\t\t\t*c2p = c2;\n\t\t\tdiff = d;\n\t\t\tif (d == 0)\n\t\t\t\treturn msec;\n\t\t}\n\t}\n\tif (diff < 65536) {\n\t\tint actual;\n\t\tif (msec & 1) {\n\t\t\tswap(*c2p, *c1p);\n\t\t}\n\t\tactual = time_codes[*c1p] + time_codes[*c2p];\n\t\tif (*c1p < *c2p)\n\t\t\treturn actual + 1;\n\t\telse\n\t\t\treturn actual;\n\t}\n\t/* No close match */\n\treturn -EINVAL;\n}",
        "static int __init fixup_pmc551(struct pci_dev *dev)\n{\n#ifdef CONFIG_MTD_PMC551_BUGFIX\n\tu32 dram_data;\n#endif": "static int __init fixup_pmc551(struct pci_dev *dev)\n{\n#ifdef CONFIG_MTD_PMC551_BUGFIX\n\tu32 dram_data;\n#endif\n\tu32 size, dcmd, cfg, dtmp;\n\tu16 cmd, tmp, i;\n\tu8 bcmd, counter;\n\n\t/* Sanity Check */\n\tif (!dev) {\n\t\treturn -ENODEV;\n\t}\n\n\t/*\n\t * Attempt to reset the card\n\t * FIXME: Stop Spinning registers\n\t */\n\tcounter = 0;\n\t/* unlock registers */\n\tpci_write_config_byte(dev, PMC551_SYS_CTRL_REG, 0xA5);\n\t/* read in old data */\n\tpci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd);\n\t/* bang the reset line up and down for a few */\n\tfor (i = 0; i < 10; i++) {\n\t\tcounter = 0;\n\t\tbcmd &= ~0x80;\n\t\twhile (counter++ < 100) {\n\t\t\tpci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);\n\t\t}\n\t\tcounter = 0;\n\t\tbcmd |= 0x80;\n\t\twhile (counter++ < 100) {\n\t\t\tpci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);\n\t\t}\n\t}\n\tbcmd |= (0x40 | 0x20);\n\tpci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);\n\n\t/*\n\t * Take care and turn off the memory on the device while we\n\t * tweak the configurations\n\t */\n\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n\ttmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);\n\tpci_write_config_word(dev, PCI_COMMAND, tmp);\n\n\t/*\n\t * Disable existing aperture before probing memory size\n\t */\n\tpci_read_config_dword(dev, PMC551_PCI_MEM_MAP0, &dcmd);\n\tdtmp = (dcmd | PMC551_PCI_MEM_MAP_ENABLE | PMC551_PCI_MEM_MAP_REG_EN);\n\tpci_write_config_dword(dev, PMC551_PCI_MEM_MAP0, dtmp);\n\t/*\n\t * Grab old BAR0 config so that we can figure out memory size\n\t * This is another bit of kludge going on.  The reason for the\n\t * redundancy is I am hoping to retain the original configuration\n\t * previously assigned to the card by the BIOS or some previous\n\t * fixup routine in the kernel.  So we read the old config into cfg,\n\t * then write all 1's to the memory space, read back the result into\n\t * \"size\", and then write back all the old config.\n\t */\n\tpci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &cfg);\n#ifndef CONFIG_MTD_PMC551_BUGFIX\n\tpci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ~0);\n\tpci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &size);\n\tsize = (size & PCI_BASE_ADDRESS_MEM_MASK);\n\tsize &= ~(size - 1);\n\tpci_write_config_dword(dev, PCI_BASE_ADDRESS_0, cfg);\n#else\n\t/*\n\t * Get the size of the memory by reading all the DRAM size values\n\t * and adding them up.\n\t *\n\t * KLUDGE ALERT: the boards we are using have invalid column and\n\t * row mux values.  We fix them here, but this will break other\n\t * memory configurations.\n\t */\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK0, &dram_data);\n\tsize = PMC551_DRAM_BLK_GET_SIZE(dram_data);\n\tdram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);\n\tdram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);\n\tpci_write_config_dword(dev, PMC551_DRAM_BLK0, dram_data);\n\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK1, &dram_data);\n\tsize += PMC551_DRAM_BLK_GET_SIZE(dram_data);\n\tdram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);\n\tdram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);\n\tpci_write_config_dword(dev, PMC551_DRAM_BLK1, dram_data);\n\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK2, &dram_data);\n\tsize += PMC551_DRAM_BLK_GET_SIZE(dram_data);\n\tdram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);\n\tdram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);\n\tpci_write_config_dword(dev, PMC551_DRAM_BLK2, dram_data);\n\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK3, &dram_data);\n\tsize += PMC551_DRAM_BLK_GET_SIZE(dram_data);\n\tdram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);\n\tdram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);\n\tpci_write_config_dword(dev, PMC551_DRAM_BLK3, dram_data);\n\n\t/*\n\t * Oops .. something went wrong\n\t */\n\tif ((size &= PCI_BASE_ADDRESS_MEM_MASK) == 0) {\n\t\treturn -ENODEV;\n\t}\n#endif\t\t\t\t/* CONFIG_MTD_PMC551_BUGFIX */\n\n\tif ((cfg & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY) {\n\t\treturn -ENODEV;\n\t}\n\n\t/*\n\t * Precharge Dram\n\t */\n\tpci_write_config_word(dev, PMC551_SDRAM_MA, 0x0400);\n\tpci_write_config_word(dev, PMC551_SDRAM_CMD, 0x00bf);\n\n\t/*\n\t * Wait until command has gone through\n\t * FIXME: register spinning issue\n\t */\n\tdo {\n\t\tpci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd);\n\t\tif (counter++ > 100)\n\t\t\tbreak;\n\t} while ((PCI_COMMAND_IO) & cmd);\n\n\t/*\n\t * Turn on auto refresh\n\t * The loop is taken directly from Ramix's example code.  I assume that\n\t * this must be held high for some duration of time, but I can find no\n\t * documentation refrencing the reasons why.\n\t */\n\tfor (i = 1; i <= 8; i++) {\n\t\tpci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0df);\n\n\t\t/*\n\t\t * Make certain command has gone through\n\t\t * FIXME: register spinning issue\n\t\t */\n\t\tcounter = 0;\n\t\tdo {\n\t\t\tpci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd);\n\t\t\tif (counter++ > 100)\n\t\t\t\tbreak;\n\t\t} while ((PCI_COMMAND_IO) & cmd);\n\t}\n\n\tpci_write_config_word(dev, PMC551_SDRAM_MA, 0x0020);\n\tpci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0ff);\n\n\t/*\n\t * Wait until command completes\n\t * FIXME: register spinning issue\n\t */\n\tcounter = 0;\n\tdo {\n\t\tpci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd);\n\t\tif (counter++ > 100)\n\t\t\tbreak;\n\t} while ((PCI_COMMAND_IO) & cmd);\n\n\tpci_read_config_dword(dev, PMC551_DRAM_CFG, &dcmd);\n\tdcmd |= 0x02000000;\n\tpci_write_config_dword(dev, PMC551_DRAM_CFG, dcmd);\n\n\t/*\n\t * Check to make certain fast back-to-back, if not\n\t * then set it so\n\t */\n\tpci_read_config_word(dev, PCI_STATUS, &cmd);\n\tif ((cmd & PCI_COMMAND_FAST_BACK) == 0) {\n\t\tcmd |= PCI_COMMAND_FAST_BACK;\n\t\tpci_write_config_word(dev, PCI_STATUS, cmd);\n\t}\n\n\t/*\n\t * Check to make certain the DEVSEL is set correctly, this device\n\t * has a tendency to assert DEVSEL and TRDY when a write is performed\n\t * to the memory when memory is read-only\n\t */\n\tif ((cmd & PCI_STATUS_DEVSEL_MASK) != 0x0) {\n\t\tcmd &= ~PCI_STATUS_DEVSEL_MASK;\n\t\tpci_write_config_word(dev, PCI_STATUS, cmd);\n\t}\n\t/*\n\t * Set to be prefetchable and put everything back based on old cfg.\n\t * it's possible that the reset of the V370PDC nuked the original\n\t * setup\n\t */\n\t/*\n\t   cfg |= PCI_BASE_ADDRESS_MEM_PREFETCH;\n\t   pci_write_config_dword( dev, PCI_BASE_ADDRESS_0, cfg );\n\t */\n\n\t/*\n\t * Turn PCI memory and I/O bus access back on\n\t */\n\tpci_write_config_word(dev, PCI_COMMAND,\n\t\t\t      PCI_COMMAND_MEMORY | PCI_COMMAND_IO);\n#ifdef CONFIG_MTD_PMC551_DEBUG\n\t/*\n\t * Some screen fun\n\t */\n\tprintk(KERN_DEBUG \"pmc551: %d%sB (0x%x) of %sprefetchable memory at \"\n\t\t\"0x%llx\\n\", (size < 1024) ? size : (size < 1048576) ?\n\t\tsize >> 10 : size >> 20,\n\t\t(size < 1024) ? \"\" : (size < 1048576) ? \"Ki\" : \"Mi\", size,\n\t\t((dcmd & (0x1 << 3)) == 0) ? \"non-\" : \"\",\n\t\t(unsigned long long)pci_resource_start(dev, 0));\n\n\t/*\n\t * Check to see the state of the memory\n\t */\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK0, &dcmd);\n\tprintk(KERN_DEBUG \"pmc551: DRAM_BLK0 Flags: %s,%s\\n\"\n\t\t\"pmc551: DRAM_BLK0 Size: %d at %d\\n\"\n\t\t\"pmc551: DRAM_BLK0 Row MUX: %d, Col MUX: %d\\n\",\n\t\t(((0x1 << 1) & dcmd) == 0) ? \"RW\" : \"RO\",\n\t\t(((0x1 << 0) & dcmd) == 0) ? \"Off\" : \"On\",\n\t\tPMC551_DRAM_BLK_GET_SIZE(dcmd),\n\t\t((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),\n\t\t((dcmd >> 9) & 0xF));\n\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK1, &dcmd);\n\tprintk(KERN_DEBUG \"pmc551: DRAM_BLK1 Flags: %s,%s\\n\"\n\t\t\"pmc551: DRAM_BLK1 Size: %d at %d\\n\"\n\t\t\"pmc551: DRAM_BLK1 Row MUX: %d, Col MUX: %d\\n\",\n\t\t(((0x1 << 1) & dcmd) == 0) ? \"RW\" : \"RO\",\n\t\t(((0x1 << 0) & dcmd) == 0) ? \"Off\" : \"On\",\n\t\tPMC551_DRAM_BLK_GET_SIZE(dcmd),\n\t\t((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),\n\t\t((dcmd >> 9) & 0xF));\n\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK2, &dcmd);\n\tprintk(KERN_DEBUG \"pmc551: DRAM_BLK2 Flags: %s,%s\\n\"\n\t\t\"pmc551: DRAM_BLK2 Size: %d at %d\\n\"\n\t\t\"pmc551: DRAM_BLK2 Row MUX: %d, Col MUX: %d\\n\",\n\t\t(((0x1 << 1) & dcmd) == 0) ? \"RW\" : \"RO\",\n\t\t(((0x1 << 0) & dcmd) == 0) ? \"Off\" : \"On\",\n\t\tPMC551_DRAM_BLK_GET_SIZE(dcmd),\n\t\t((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),\n\t\t((dcmd >> 9) & 0xF));\n\n\tpci_read_config_dword(dev, PMC551_DRAM_BLK3, &dcmd);\n\tprintk(KERN_DEBUG \"pmc551: DRAM_BLK3 Flags: %s,%s\\n\"\n\t\t\"pmc551: DRAM_BLK3 Size: %d at %d\\n\"\n\t\t\"pmc551: DRAM_BLK3 Row MUX: %d, Col MUX: %d\\n\",\n\t\t(((0x1 << 1) & dcmd) == 0) ? \"RW\" : \"RO\",\n\t\t(((0x1 << 0) & dcmd) == 0) ? \"Off\" : \"On\",\n\t\tPMC551_DRAM_BLK_GET_SIZE(dcmd),\n\t\t((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),\n\t\t((dcmd >> 9) & 0xF));\n\n\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n\tprintk(KERN_DEBUG \"pmc551: Memory Access %s\\n\",\n\t\t(((0x1 << 1) & cmd) == 0) ? \"off\" : \"on\");\n\tprintk(KERN_DEBUG \"pmc551: I/O Access %s\\n\",\n\t\t(((0x1 << 0) & cmd) == 0) ? \"off\" : \"on\");\n\n\tpci_read_config_word(dev, PCI_STATUS, &cmd);\n\tprintk(KERN_DEBUG \"pmc551: Devsel %s\\n\",\n\t\t((PCI_STATUS_DEVSEL_MASK & cmd) == 0x000) ? \"Fast\" :\n\t\t((PCI_STATUS_DEVSEL_MASK & cmd) == 0x200) ? \"Medium\" :\n\t\t((PCI_STATUS_DEVSEL_MASK & cmd) == 0x400) ? \"Slow\" : \"Invalid\");\n\n\tprintk(KERN_DEBUG \"pmc551: %sFast Back-to-Back\\n\",\n\t\t((PCI_COMMAND_FAST_BACK & cmd) == 0) ? \"Not \" : \"\");\n\n\tpci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd);\n\tprintk(KERN_DEBUG \"pmc551: EEPROM is under %s control\\n\"\n\t\t\"pmc551: System Control Register is %slocked to PCI access\\n\"\n\t\t\"pmc551: System Control Register is %slocked to EEPROM access\\n\",\n\t\t(bcmd & 0x1) ? \"software\" : \"hardware\",\n\t\t(bcmd & 0x20) ? \"\" : \"un\", (bcmd & 0x40) ? \"\" : \"un\");\n#endif\n\treturn size;\n}",
        "static void prepare_write_message(struct ceph_connection *con)\n{\n\tstruct ceph_msg *m;\n\tu32 crc;\n": "static void prepare_write_message(struct ceph_connection *con)\n{\n\tstruct ceph_msg *m;\n\tu32 crc;\n\n\tcon_out_kvec_reset(con);\n\tcon->v1.out_msg_done = false;\n\n\t/* Sneak an ack in there first?  If we can get it into the same\n\t * TCP packet that's a good thing. */\n\tif (con->in_seq > con->in_seq_acked) {\n\t\tcon->in_seq_acked = con->in_seq;\n\t\tcon_out_kvec_add(con, sizeof (tag_ack), &tag_ack);\n\t\tcon->v1.out_temp_ack = cpu_to_le64(con->in_seq_acked);\n\t\tcon_out_kvec_add(con, sizeof(con->v1.out_temp_ack),\n\t\t\t&con->v1.out_temp_ack);\n\t}\n\n\tceph_con_get_out_msg(con);\n\tm = con->out_msg;\n\n\tdout(\"prepare_write_message %p seq %lld type %d len %d+%d+%zd\\n\",\n\t     m, con->out_seq, le16_to_cpu(m->hdr.type),\n\t     le32_to_cpu(m->hdr.front_len), le32_to_cpu(m->hdr.middle_len),\n\t     m->data_length);\n\tWARN_ON(m->front.iov_len != le32_to_cpu(m->hdr.front_len));\n\tWARN_ON(m->data_length != le32_to_cpu(m->hdr.data_len));\n\n\t/* tag + hdr + front + middle */\n\tcon_out_kvec_add(con, sizeof (tag_msg), &tag_msg);\n\tcon_out_kvec_add(con, sizeof(con->v1.out_hdr), &con->v1.out_hdr);\n\tcon_out_kvec_add(con, m->front.iov_len, m->front.iov_base);\n\n\tif (m->middle)\n\t\tcon_out_kvec_add(con, m->middle->vec.iov_len,\n\t\t\tm->middle->vec.iov_base);\n\n\t/* fill in hdr crc and finalize hdr */\n\tcrc = crc32c(0, &m->hdr, offsetof(struct ceph_msg_header, crc));\n\tcon->out_msg->hdr.crc = cpu_to_le32(crc);\n\tmemcpy(&con->v1.out_hdr, &con->out_msg->hdr, sizeof(con->v1.out_hdr));\n\n\t/* fill in front and middle crc, footer */\n\tcrc = crc32c(0, m->front.iov_base, m->front.iov_len);\n\tcon->out_msg->footer.front_crc = cpu_to_le32(crc);\n\tif (m->middle) {\n\t\tcrc = crc32c(0, m->middle->vec.iov_base,\n\t\t\t\tm->middle->vec.iov_len);\n\t\tcon->out_msg->footer.middle_crc = cpu_to_le32(crc);\n\t} else\n\t\tcon->out_msg->footer.middle_crc = 0;\n\tdout(\"%s front_crc %u middle_crc %u\\n\", __func__,\n\t     le32_to_cpu(con->out_msg->footer.front_crc),\n\t     le32_to_cpu(con->out_msg->footer.middle_crc));\n\tcon->out_msg->footer.flags = 0;\n\n\t/* is there a data payload? */\n\tcon->out_msg->footer.data_crc = 0;\n\tif (m->data_length) {\n\t\tprepare_message_data(con->out_msg, m->data_length);\n\t\tcon->v1.out_more = 1;  /* data + footer will follow */\n\t} else {\n\t\t/* no, queue up footer too and be done */\n\t\tprepare_write_message_footer(con);\n\t}\n\n\tceph_con_flag_set(con, CEPH_CON_F_WRITE_PENDING);\n}",
        "static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)\n{\n\tstruct tegra_admaif *admaif = dev_get_drvdata(dev);\n\tunsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;\n\tunsigned int num_ch = admaif->soc_data->num_ch;": "static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)\n{\n\tstruct tegra_admaif *admaif = dev_get_drvdata(dev);\n\tunsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;\n\tunsigned int num_ch = admaif->soc_data->num_ch;\n\tunsigned int rx_base = admaif->soc_data->rx_base;\n\tunsigned int tx_base = admaif->soc_data->tx_base;\n\tunsigned int global_base = admaif->soc_data->global_base;\n\tunsigned int reg_max = admaif->soc_data->regmap_conf->max_register;\n\tunsigned int rx_max = rx_base + (num_ch * ch_stride);\n\tunsigned int tx_max = tx_base + (num_ch * ch_stride);\n\n\tif ((reg >= rx_base) && (reg < rx_max)) {\n\t\treg = (reg - rx_base) % ch_stride;\n\t\tif ((reg == TEGRA_ADMAIF_RX_ENABLE) ||\n\t\t    (reg == TEGRA_ADMAIF_RX_FIFO_CTRL) ||\n\t\t    (reg == TEGRA_ADMAIF_RX_SOFT_RESET) ||\n\t\t    (reg == TEGRA_ADMAIF_CH_ACIF_RX_CTRL))\n\t\t\treturn true;\n\t} else if ((reg >= tx_base) && (reg < tx_max)) {\n\t\treg = (reg - tx_base) % ch_stride;\n\t\tif ((reg == TEGRA_ADMAIF_TX_ENABLE) ||\n\t\t    (reg == TEGRA_ADMAIF_TX_FIFO_CTRL) ||\n\t\t    (reg == TEGRA_ADMAIF_TX_SOFT_RESET) ||\n\t\t    (reg == TEGRA_ADMAIF_CH_ACIF_TX_CTRL))\n\t\t\treturn true;\n\t} else if ((reg >= global_base) && (reg < reg_max)) {\n\t\tif (reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE))\n\t\t\treturn true;\n\t}\n\n\treturn false;\n}",
        "static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)\n{\n\tstruct pvr2_hdw *hdw = cptr->hdw;\n\tunsigned int slotId = hdw->freqProgSlot;\n\tif ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {": "static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)\n{\n\tstruct pvr2_hdw *hdw = cptr->hdw;\n\tunsigned int slotId = hdw->freqProgSlot;\n\tif ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {\n\t\thdw->freqTable[slotId-1] = v;\n\t\t/* Handle side effects correctly - if we're tuned to this\n\t\t   slot, then forgot the slot id relation since the stored\n\t\t   frequency has been changed. */\n\t\tif (hdw->freqSelector) {\n\t\t\tif (hdw->freqSlotRadio == slotId) {\n\t\t\t\thdw->freqSlotRadio = 0;\n\t\t\t}\n\t\t} else {\n\t\t\tif (hdw->freqSlotTelevision == slotId) {\n\t\t\t\thdw->freqSlotTelevision = 0;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}",
        "static int mkimage(struct imgchunk *clist, unsigned int *ccnt)\n{\n\tint result = 0;\n\tint i;\n\tint j;": "static int mkimage(struct imgchunk *clist, unsigned int *ccnt)\n{\n\tint result = 0;\n\tint i;\n\tint j;\n\tint currchunk = 0;\n\tu32 nextaddr = 0;\n\tu32 s3start;\n\tu32 s3end;\n\tu32 cstart = 0;\n\tu32 cend;\n\tu32 coffset;\n\n\t/* There may already be data in the chunklist */\n\t*ccnt = 0;\n\n\t/* Establish the location and size of each chunk */\n\tfor (i = 0; i < ns3data; i++) {\n\t\tif (s3data[i].addr == nextaddr) {\n\t\t\t/* existing chunk, grow it */\n\t\t\tclist[currchunk].len += s3data[i].len;\n\t\t\tnextaddr += s3data[i].len;\n\t\t} else {\n\t\t\t/* New chunk */\n\t\t\t(*ccnt)++;\n\t\t\tcurrchunk = *ccnt - 1;\n\t\t\tclist[currchunk].addr = s3data[i].addr;\n\t\t\tclist[currchunk].len = s3data[i].len;\n\t\t\tnextaddr = s3data[i].addr + s3data[i].len;\n\t\t\t/* Expand the chunk if there is a CRC record at */\n\t\t\t/* their beginning bound */\n\t\t\tfor (j = 0; j < ns3crc; j++) {\n\t\t\t\tif (s3crc[j].dowrite &&\n\t\t\t\t    s3crc[j].addr == clist[currchunk].addr) {\n\t\t\t\t\tclist[currchunk].addr -= 2;\n\t\t\t\t\tclist[currchunk].len += 2;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* We're currently assuming there aren't any overlapping chunks */\n\t/*  if this proves false, we'll need to add code to coalesce. */\n\n\t/* Allocate buffer space for chunks */\n\tfor (i = 0; i < *ccnt; i++) {\n\t\tclist[i].data = kzalloc(clist[i].len, GFP_KERNEL);\n\t\tif (!clist[i].data)\n\t\t\treturn 1;\n\n\t\tpr_debug(\"chunk[%d]: addr=0x%06x len=%d\\n\",\n\t\t\t i, clist[i].addr, clist[i].len);\n\t}\n\n\t/* Copy srec data to chunks */\n\tfor (i = 0; i < ns3data; i++) {\n\t\ts3start = s3data[i].addr;\n\t\ts3end = s3start + s3data[i].len - 1;\n\t\tfor (j = 0; j < *ccnt; j++) {\n\t\t\tcstart = clist[j].addr;\n\t\t\tcend = cstart + clist[j].len - 1;\n\t\t\tif (s3start >= cstart && s3end <= cend)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (((unsigned int)j) >= (*ccnt)) {\n\t\t\tpr_err(\"s3rec(a=0x%06x,l=%d), no chunk match, exiting.\\n\",\n\t\t\t       s3start, s3data[i].len);\n\t\t\treturn 1;\n\t\t}\n\t\tcoffset = s3start - cstart;\n\t\tmemcpy(clist[j].data + coffset, s3data[i].data, s3data[i].len);\n\t}\n\n\treturn result;\n}",
        "static int hisi_pcie_alloc_pmu(struct pci_dev *pdev, struct hisi_pcie_pmu *pcie_pmu)\n{\n\tstruct hisi_pcie_reg_pair regs;\n\tu16 sicl_id, core_id;\n\tchar *name;": "static int hisi_pcie_alloc_pmu(struct pci_dev *pdev, struct hisi_pcie_pmu *pcie_pmu)\n{\n\tstruct hisi_pcie_reg_pair regs;\n\tu16 sicl_id, core_id;\n\tchar *name;\n\n\tregs = hisi_pcie_parse_reg_value(pcie_pmu, HISI_PCIE_REG_BDF);\n\tpcie_pmu->bdf_min = regs.lo;\n\tpcie_pmu->bdf_max = regs.hi;\n\n\tregs = hisi_pcie_parse_reg_value(pcie_pmu, HISI_PCIE_REG_INFO);\n\tsicl_id = regs.hi;\n\tcore_id = regs.lo;\n\n\tname = devm_kasprintf(&pdev->dev, GFP_KERNEL, \"hisi_pcie%u_core%u\", sicl_id, core_id);\n\tif (!name)\n\t\treturn -ENOMEM;\n\n\tpcie_pmu->pdev = pdev;\n\tpcie_pmu->on_cpu = -1;\n\tpcie_pmu->identifier = readl(pcie_pmu->base + HISI_PCIE_REG_VERSION);\n\tpcie_pmu->pmu = (struct pmu) {\n\t\t.name\t\t= name,\n\t\t.module\t\t= THIS_MODULE,\n\t\t.event_init\t= hisi_pcie_pmu_event_init,\n\t\t.pmu_enable\t= hisi_pcie_pmu_enable,\n\t\t.pmu_disable\t= hisi_pcie_pmu_disable,\n\t\t.add\t\t= hisi_pcie_pmu_add,\n\t\t.del\t\t= hisi_pcie_pmu_del,\n\t\t.start\t\t= hisi_pcie_pmu_start,\n\t\t.stop\t\t= hisi_pcie_pmu_stop,\n\t\t.read\t\t= hisi_pcie_pmu_read,\n\t\t.task_ctx_nr\t= perf_invalid_context,\n\t\t.attr_groups\t= hisi_pcie_pmu_attr_groups,\n\t\t.capabilities\t= PERF_PMU_CAP_NO_EXCLUDE,\n\t};\n\n\treturn 0;\n}",
        "static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)\n{\n\tconst struct tg3_firmware_hdr *fw_hdr;\n\tint err;\n": "static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)\n{\n\tconst struct tg3_firmware_hdr *fw_hdr;\n\tint err;\n\n\tfw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;\n\n\t/* Firmware blob starts with version numbers, followed by\n\t   start address and length. We are setting complete length.\n\t   length = end_address_of_bss - start_address_of_text.\n\t   Remainder is the blob to be loaded contiguously\n\t   from start address. */\n\n\terr = tg3_load_firmware_cpu(tp, RX_CPU_BASE,\n\t\t\t\t    RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,\n\t\t\t\t    fw_hdr);\n\tif (err)\n\t\treturn err;\n\n\terr = tg3_load_firmware_cpu(tp, TX_CPU_BASE,\n\t\t\t\t    TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,\n\t\t\t\t    fw_hdr);\n\tif (err)\n\t\treturn err;\n\n\t/* Now startup only the RX cpu. */\n\terr = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,\n\t\t\t\t       be32_to_cpu(fw_hdr->base_addr));\n\tif (err) {\n\t\tnetdev_err(tp->dev, \"%s fails to set RX CPU PC, is %08x \"\n\t\t\t   \"should be %08x\\n\", __func__,\n\t\t\t   tr32(RX_CPU_BASE + CPU_PC),\n\t\t\t\tbe32_to_cpu(fw_hdr->base_addr));\n\t\treturn -ENODEV;\n\t}\n\n\ttg3_rxcpu_resume(tp);\n\n\treturn 0;\n}",
        "static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)\n{\n\tu64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;\n\tu32 status;\n\tu32 can_read;": "static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)\n{\n\tu64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;\n\tu32 status;\n\tu32 can_read;\n\n\tdev_dbg(priv->dev, \"Trying to read from idx %d\\n\", idx);\n\n\tdo {\n\t\tstatus = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);\n\t\tcan_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);\n\t} while (!can_read && time_is_after_jiffies64(timeout_time));\n\n\tif (!can_read) {\n\t\tdev_err(priv->dev, \"timeout trying to read idx %d (%.8x)\\n\",\n\t\t\tidx, status);\n\t\treturn -ETIME;\n\t}\n\n\t*val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);\n\tdev_dbg(priv->dev, \"Read %.8x\\n\", *val);\n\n\treturn 0;\n}",
        "static void niu_try_msix(struct niu *np, u8 *ldg_num_map)\n{\n\tstruct msix_entry msi_vec[NIU_NUM_LDG];\n\tstruct niu_parent *parent = np->parent;\n\tstruct pci_dev *pdev = np->pdev;": "static void niu_try_msix(struct niu *np, u8 *ldg_num_map)\n{\n\tstruct msix_entry msi_vec[NIU_NUM_LDG];\n\tstruct niu_parent *parent = np->parent;\n\tstruct pci_dev *pdev = np->pdev;\n\tint i, num_irqs;\n\tu8 first_ldg;\n\n\tfirst_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;\n\tfor (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)\n\t\tldg_num_map[i] = first_ldg + i;\n\n\tnum_irqs = (parent->rxchan_per_port[np->port] +\n\t\t    parent->txchan_per_port[np->port] +\n\t\t    (np->port == 0 ? 3 : 1));\n\tBUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));\n\n\tfor (i = 0; i < num_irqs; i++) {\n\t\tmsi_vec[i].vector = 0;\n\t\tmsi_vec[i].entry = i;\n\t}\n\n\tnum_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);\n\tif (num_irqs < 0) {\n\t\tnp->flags &= ~NIU_FLAGS_MSIX;\n\t\treturn;\n\t}\n\n\tnp->flags |= NIU_FLAGS_MSIX;\n\tfor (i = 0; i < num_irqs; i++)\n\t\tnp->ldg[i].irq = msi_vec[i].vector;\n\tnp->num_ldg = num_irqs;\n}",
        "static int net2272_present(struct net2272 *dev)\n{\n\t/*\n\t * Quick test to see if CPU can communicate properly with the NET2272.\n\t * Verifies connection using writes and reads to write/read and": "static int net2272_present(struct net2272 *dev)\n{\n\t/*\n\t * Quick test to see if CPU can communicate properly with the NET2272.\n\t * Verifies connection using writes and reads to write/read and\n\t * read-only registers.\n\t *\n\t * This routine is strongly recommended especially during early bring-up\n\t * of new hardware, however for designs that do not apply Power On System\n\t * Tests (POST) it may discarded (or perhaps minimized).\n\t */\n\tunsigned int ii;\n\tu8 val, refval;\n\n\t/* Verify NET2272 write/read SCRATCH register can write and read */\n\trefval = net2272_read(dev, SCRATCH);\n\tfor (ii = 0; ii < 0x100; ii += 7) {\n\t\tnet2272_write(dev, SCRATCH, ii);\n\t\tval = net2272_read(dev, SCRATCH);\n\t\tif (val != ii) {\n\t\t\tdev_dbg(dev->dev,\n\t\t\t\t\"%s: write/read SCRATCH register test failed: \"\n\t\t\t\t\"wrote:0x%2.2x, read:0x%2.2x\\n\",\n\t\t\t\t__func__, ii, val);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\t/* To be nice, we write the original SCRATCH value back: */\n\tnet2272_write(dev, SCRATCH, refval);\n\n\t/* Verify NET2272 CHIPREV register is read-only: */\n\trefval = net2272_read(dev, CHIPREV_2272);\n\tfor (ii = 0; ii < 0x100; ii += 7) {\n\t\tnet2272_write(dev, CHIPREV_2272, ii);\n\t\tval = net2272_read(dev, CHIPREV_2272);\n\t\tif (val != refval) {\n\t\t\tdev_dbg(dev->dev,\n\t\t\t\t\"%s: write/read CHIPREV register test failed: \"\n\t\t\t\t\"wrote 0x%2.2x, read:0x%2.2x expected:0x%2.2x\\n\",\n\t\t\t\t__func__, ii, val, refval);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\t/*\n\t * Verify NET2272's \"NET2270 legacy revision\" register\n\t *  - NET2272 has two revision registers. The NET2270 legacy revision\n\t *    register should read the same value, regardless of the NET2272\n\t *    silicon revision.  The legacy register applies to NET2270\n\t *    firmware being applied to the NET2272.\n\t */\n\tval = net2272_read(dev, CHIPREV_LEGACY);\n\tif (val != NET2270_LEGACY_REV) {\n\t\t/*\n\t\t * Unexpected legacy revision value\n\t\t * - Perhaps the chip is a NET2270?\n\t\t */\n\t\tdev_dbg(dev->dev,\n\t\t\t\"%s: WARNING: UNEXPECTED NET2272 LEGACY REGISTER VALUE:\\n\"\n\t\t\t\" - CHIPREV_LEGACY: expected 0x%2.2x, got:0x%2.2x. (Not NET2272?)\\n\",\n\t\t\t__func__, NET2270_LEGACY_REV, val);\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * Verify NET2272 silicon revision\n\t *  - This revision register is appropriate for the silicon version\n\t *    of the NET2272\n\t */\n\tval = net2272_read(dev, CHIPREV_2272);\n\tswitch (val) {\n\tcase CHIPREV_NET2272_R1:\n\t\t/*\n\t\t * NET2272 Rev 1 has DMA related errata:\n\t\t *  - Newer silicon (Rev 1A or better) required\n\t\t */\n\t\tdev_dbg(dev->dev,\n\t\t\t\"%s: Rev 1 detected: newer silicon recommended for DMA support\\n\",\n\t\t\t__func__);\n\t\tbreak;\n\tcase CHIPREV_NET2272_R1A:\n\t\tbreak;\n\tdefault:\n\t\t/* NET2272 silicon version *may* not work with this firmware */\n\t\tdev_dbg(dev->dev,\n\t\t\t\"%s: unexpected silicon revision register value: \"\n\t\t\t\" CHIPREV_2272: 0x%2.2x\\n\",\n\t\t\t__func__, val);\n\t\t/*\n\t\t * Return Success, even though the chip rev is not an expected value\n\t\t *  - Older, pre-built firmware can attempt to operate on newer silicon\n\t\t *  - Often, new silicon is perfectly compatible\n\t\t */\n\t}\n\n\t/* Success: NET2272 checks out OK */\n\treturn 0;\n}",
        "static long ssam_cdev_request(struct ssam_cdev_client *client, struct ssam_cdev_request __user *r)\n{\n\tstruct ssam_cdev_request rqst;\n\tstruct ssam_request spec = {};\n\tstruct ssam_response rsp = {};": "static long ssam_cdev_request(struct ssam_cdev_client *client, struct ssam_cdev_request __user *r)\n{\n\tstruct ssam_cdev_request rqst;\n\tstruct ssam_request spec = {};\n\tstruct ssam_response rsp = {};\n\tconst void __user *plddata;\n\tvoid __user *rspdata;\n\tint status = 0, ret = 0, tmp;\n\n\tlockdep_assert_held_read(&client->cdev->lock);\n\n\tret = copy_struct_from_user(&rqst, sizeof(rqst), r, sizeof(*r));\n\tif (ret)\n\t\tgoto out;\n\n\tplddata = u64_to_user_ptr(rqst.payload.data);\n\trspdata = u64_to_user_ptr(rqst.response.data);\n\n\t/* Setup basic request fields. */\n\tspec.target_category = rqst.target_category;\n\tspec.target_id = rqst.target_id;\n\tspec.command_id = rqst.command_id;\n\tspec.instance_id = rqst.instance_id;\n\tspec.flags = 0;\n\tspec.length = rqst.payload.length;\n\tspec.payload = NULL;\n\n\tif (rqst.flags & SSAM_CDEV_REQUEST_HAS_RESPONSE)\n\t\tspec.flags |= SSAM_REQUEST_HAS_RESPONSE;\n\n\tif (rqst.flags & SSAM_CDEV_REQUEST_UNSEQUENCED)\n\t\tspec.flags |= SSAM_REQUEST_UNSEQUENCED;\n\n\trsp.capacity = rqst.response.length;\n\trsp.length = 0;\n\trsp.pointer = NULL;\n\n\t/* Get request payload from user-space. */\n\tif (spec.length) {\n\t\tif (!plddata) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/*\n\t\t * Note: spec.length is limited to U16_MAX bytes via struct\n\t\t * ssam_cdev_request. This is slightly larger than the\n\t\t * theoretical maximum (SSH_COMMAND_MAX_PAYLOAD_SIZE) of the\n\t\t * underlying protocol (note that nothing remotely this size\n\t\t * should ever be allocated in any normal case). This size is\n\t\t * validated later in ssam_request_sync(), for allocation the\n\t\t * bound imposed by u16 should be enough.\n\t\t */\n\t\tspec.payload = kzalloc(spec.length, GFP_KERNEL);\n\t\tif (!spec.payload) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (copy_from_user((void *)spec.payload, plddata, spec.length)) {\n\t\t\tret = -EFAULT;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/* Allocate response buffer. */\n\tif (rsp.capacity) {\n\t\tif (!rspdata) {\n\t\t\tret = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/*\n\t\t * Note: rsp.capacity is limited to U16_MAX bytes via struct\n\t\t * ssam_cdev_request. This is slightly larger than the\n\t\t * theoretical maximum (SSH_COMMAND_MAX_PAYLOAD_SIZE) of the\n\t\t * underlying protocol (note that nothing remotely this size\n\t\t * should ever be allocated in any normal case). In later use,\n\t\t * this capacity does not have to be strictly bounded, as it\n\t\t * is only used as an output buffer to be written to. For\n\t\t * allocation the bound imposed by u16 should be enough.\n\t\t */\n\t\trsp.pointer = kzalloc(rsp.capacity, GFP_KERNEL);\n\t\tif (!rsp.pointer) {\n\t\t\tret = -ENOMEM;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/* Perform request. */\n\tstatus = ssam_request_sync(client->cdev->ctrl, &spec, &rsp);\n\tif (status)\n\t\tgoto out;\n\n\t/* Copy response to user-space. */\n\tif (rsp.length && copy_to_user(rspdata, rsp.pointer, rsp.length))\n\t\tret = -EFAULT;\n\nout:\n\t/* Always try to set response-length and status. */\n\ttmp = put_user(rsp.length, &r->response.length);\n\tif (tmp)\n\t\tret = tmp;\n\n\ttmp = put_user(status, &r->status);\n\tif (tmp)\n\t\tret = tmp;\n\n\t/* Cleanup. */\n\tkfree(spec.payload);\n\tkfree(rsp.pointer);\n\n\treturn ret;\n}",
        "static void gdb_cmd_reg_set(struct kgdb_state *ks)\n{\n\tunsigned long regnum;\n\tchar *ptr = &remcom_in_buffer[1];\n\tint i = 0;": "static void gdb_cmd_reg_set(struct kgdb_state *ks)\n{\n\tunsigned long regnum;\n\tchar *ptr = &remcom_in_buffer[1];\n\tint i = 0;\n\n\tkgdb_hex2long(&ptr, &regnum);\n\tif (*ptr++ != '=' ||\n\t    !(!kgdb_usethread || kgdb_usethread == current) ||\n\t    !dbg_get_reg(regnum, gdb_regs, ks->linux_regs)) {\n\t\terror_packet(remcom_out_buffer, -EINVAL);\n\t\treturn;\n\t}\n\tmemset(gdb_regs, 0, sizeof(gdb_regs));\n\twhile (i < sizeof(gdb_regs) * 2)\n\t\tif (hex_to_bin(ptr[i]) >= 0)\n\t\t\ti++;\n\t\telse\n\t\t\tbreak;\n\ti = i / 2;\n\tkgdb_hex2mem(ptr, (char *)gdb_regs, i);\n\tdbg_set_reg(regnum, gdb_regs, ks->linux_regs);\n\tstrcpy(remcom_out_buffer, \"OK\");\n}",
        "static int rt1719_dr_set(struct typec_port *port, enum typec_data_role role)\n{\n\tstruct rt1719_data *data = typec_get_drvdata(port);\n\tenum typec_data_role cur_role;\n\tint ret;": "static int rt1719_dr_set(struct typec_port *port, enum typec_data_role role)\n{\n\tstruct rt1719_data *data = typec_get_drvdata(port);\n\tenum typec_data_role cur_role;\n\tint ret;\n\n\tif (!data->attached || !data->pd_capable || !data->drswap_support)\n\t\treturn -EOPNOTSUPP;\n\n\tif (data->spdo_num > 0 && !(data->spdos[0] & PDO_FIXED_DATA_SWAP))\n\t\treturn -EINVAL;\n\n\tcur_role = rt1719_get_data_role(data->conn_info);\n\tif (cur_role == role)\n\t\treturn 0;\n\n\tret = regmap_update_bits(data->regmap, RT1719_REG_TXCTRL1,\n\t\t\t\t RT1719_REQDRSWAP_MASK, RT1719_REQDRSWAP_MASK);\n\tif (ret)\n\t\treturn ret;\n\n\treinit_completion(&data->req_completion);\n\tret = wait_for_completion_timeout(&data->req_completion,\n\t\t\t\t\t  msecs_to_jiffies(400));\n\tif (ret == 0)\n\t\treturn -ETIMEDOUT;\n\n\tcur_role = rt1719_get_data_role(data->conn_info);\n\tif (cur_role != role)\n\t\treturn -EAGAIN;\n\n\trt1719_set_data_role(data, role, true);\n\treturn 0;\n}",
        "static int load_low_light_binaries(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_frame_info pre_in_info, anr_in_info,\n\t\t\tpost_in_info, post_out_info,\n\t\t\tvf_info, *pipe_vf_out_info, *pipe_out_info,": "static int load_low_light_binaries(struct ia_css_pipe *pipe)\n{\n\tstruct ia_css_frame_info pre_in_info, anr_in_info,\n\t\t\tpost_in_info, post_out_info,\n\t\t\tvf_info, *pipe_vf_out_info, *pipe_out_info,\n\t\t\t*vf_pp_in_info;\n\tbool need_pp;\n\tbool need_isp_copy = true;\n\tint err = 0;\n\n\tIA_CSS_ENTER_PRIVATE(\"\");\n\tassert(pipe);\n\tassert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE ||\n\t       pipe->mode == IA_CSS_PIPE_ID_COPY);\n\n\tif (pipe->pipe_settings.capture.pre_isp_binary.info)\n\t\treturn 0;\n\tpipe_vf_out_info = &pipe->vf_output_info[0];\n\tpipe_out_info = &pipe->output_info[0];\n\n\tvf_info = *pipe_vf_out_info;\n\terr = ia_css_util_check_vf_out_info(pipe_out_info,\n\t\t\t\t\t    &vf_info);\n\tif (err)\n\t\treturn err;\n\tneed_pp = need_capture_pp(pipe);\n\n\tia_css_frame_info_set_format(&vf_info,\n\t\t\t\t     IA_CSS_FRAME_FORMAT_YUV_LINE);\n\n\t/* we build up the pipeline starting at the end */\n\t/* Capture post-processing */\n\tif (need_pp) {\n\t\tstruct ia_css_binary_descr capture_pp_descr;\n\n\t\tia_css_pipe_get_capturepp_binarydesc(pipe, &capture_pp_descr,\n\t\t\t\t\t\t     &post_out_info,\n\t\t\t\t\t\t     pipe_out_info, &vf_info);\n\t\terr = ia_css_binary_find(&capture_pp_descr,\n\t\t\t\t\t &pipe->pipe_settings.capture.capture_pp_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t} else {\n\t\tpost_out_info = *pipe_out_info;\n\t}\n\n\t/* Post-anr */\n\t{\n\t\tstruct ia_css_binary_descr post_anr_descr;\n\n\t\tia_css_pipe_get_post_anr_binarydesc(pipe,\n\t\t\t\t\t\t    &post_anr_descr, &post_in_info, &post_out_info, &vf_info);\n\t\terr = ia_css_binary_find(&post_anr_descr,\n\t\t\t\t\t &pipe->pipe_settings.capture.post_isp_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* Anr */\n\t{\n\t\tstruct ia_css_binary_descr anr_descr;\n\n\t\tia_css_pipe_get_anr_binarydesc(pipe, &anr_descr, &anr_in_info,\n\t\t\t\t\t       &pipe->pipe_settings.capture.post_isp_binary.in_frame_info);\n\t\terr = ia_css_binary_find(&anr_descr,\n\t\t\t\t\t &pipe->pipe_settings.capture.anr_gdc_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\tpipe->pipe_settings.capture.anr_gdc_binary.left_padding =\n\t    pipe->pipe_settings.capture.post_isp_binary.left_padding;\n\n\t/* Pre-anr */\n\t{\n\t\tstruct ia_css_binary_descr pre_anr_descr;\n\n\t\tia_css_pipe_get_pre_anr_binarydesc(pipe, &pre_anr_descr, &pre_in_info,\n\t\t\t\t\t\t   &pipe->pipe_settings.capture.anr_gdc_binary.in_frame_info);\n\t\terr = ia_css_binary_find(&pre_anr_descr,\n\t\t\t\t\t &pipe->pipe_settings.capture.pre_isp_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\tpipe->pipe_settings.capture.pre_isp_binary.left_padding =\n\t    pipe->pipe_settings.capture.anr_gdc_binary.left_padding;\n\n\t/* Viewfinder post-processing */\n\tif (need_pp) {\n\t\tvf_pp_in_info =\n\t\t    &pipe->pipe_settings.capture.capture_pp_binary.vf_frame_info;\n\t} else {\n\t\tvf_pp_in_info =\n\t\t    &pipe->pipe_settings.capture.post_isp_binary.vf_frame_info;\n\t}\n\n\t{\n\t\tstruct ia_css_binary_descr vf_pp_descr;\n\n\t\tia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr,\n\t\t\t\t\t\tvf_pp_in_info, pipe_vf_out_info);\n\t\terr = ia_css_binary_find(&vf_pp_descr,\n\t\t\t\t\t &pipe->pipe_settings.capture.vf_pp_binary);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* Copy */\n#ifdef ISP2401\n\t/* For CSI2+, only the direct sensor mode/online requires ISP copy */\n\tneed_isp_copy = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR;\n#endif\n\tif (need_isp_copy)\n\t\terr = load_copy_binary(pipe,\n\t\t\t\t       &pipe->pipe_settings.capture.copy_binary,\n\t\t\t\t       &pipe->pipe_settings.capture.pre_isp_binary);\n\n\treturn err;\n}",
        "static void sctp_generate_iftsn(struct sctp_outq *q, __u32 ctsn)\n{\n\tstruct sctp_ifwdtsn_skip ftsn_skip_arr[10];\n\tstruct sctp_association *asoc = q->asoc;\n\tstruct sctp_chunk *ftsn_chunk = NULL;": "static void sctp_generate_iftsn(struct sctp_outq *q, __u32 ctsn)\n{\n\tstruct sctp_ifwdtsn_skip ftsn_skip_arr[10];\n\tstruct sctp_association *asoc = q->asoc;\n\tstruct sctp_chunk *ftsn_chunk = NULL;\n\tstruct list_head *lchunk, *temp;\n\tint nskips = 0, skip_pos;\n\tstruct sctp_chunk *chunk;\n\t__u32 tsn;\n\n\tif (!asoc->peer.prsctp_capable)\n\t\treturn;\n\n\tif (TSN_lt(asoc->adv_peer_ack_point, ctsn))\n\t\tasoc->adv_peer_ack_point = ctsn;\n\n\tlist_for_each_safe(lchunk, temp, &q->abandoned) {\n\t\tchunk = list_entry(lchunk, struct sctp_chunk, transmitted_list);\n\t\ttsn = ntohl(chunk->subh.data_hdr->tsn);\n\n\t\tif (TSN_lte(tsn, ctsn)) {\n\t\t\tlist_del_init(lchunk);\n\t\t\tsctp_chunk_free(chunk);\n\t\t} else if (TSN_lte(tsn, asoc->adv_peer_ack_point + 1)) {\n\t\t\t__be16 sid = chunk->subh.idata_hdr->stream;\n\t\t\t__be32 mid = chunk->subh.idata_hdr->mid;\n\t\t\t__u8 flags = 0;\n\n\t\t\tif (chunk->chunk_hdr->flags & SCTP_DATA_UNORDERED)\n\t\t\t\tflags |= SCTP_FTSN_U_BIT;\n\n\t\t\tasoc->adv_peer_ack_point = tsn;\n\t\t\tskip_pos = sctp_get_skip_pos(&ftsn_skip_arr[0], nskips,\n\t\t\t\t\t\t     sid, flags);\n\t\t\tftsn_skip_arr[skip_pos].stream = sid;\n\t\t\tftsn_skip_arr[skip_pos].reserved = 0;\n\t\t\tftsn_skip_arr[skip_pos].flags = flags;\n\t\t\tftsn_skip_arr[skip_pos].mid = mid;\n\t\t\tif (skip_pos == nskips)\n\t\t\t\tnskips++;\n\t\t\tif (nskips == 10)\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (asoc->adv_peer_ack_point > ctsn)\n\t\tftsn_chunk = sctp_make_ifwdtsn(asoc, asoc->adv_peer_ack_point,\n\t\t\t\t\t       nskips, &ftsn_skip_arr[0]);\n\n\tif (ftsn_chunk) {\n\t\tlist_add_tail(&ftsn_chunk->list, &q->control_chunk_list);\n\t\tSCTP_INC_STATS(asoc->base.net, SCTP_MIB_OUTCTRLCHUNKS);\n\t}\n}",
        "static int iso14443_config_fdt(struct st95hf_context *st95context, int wtxm)\n{\n\tint result = 0;\n\tstruct device *dev = &st95context->spicontext.spidev->dev;\n\tstruct nfc_digital_dev *nfcddev = st95context->ddev;": "static int iso14443_config_fdt(struct st95hf_context *st95context, int wtxm)\n{\n\tint result = 0;\n\tstruct device *dev = &st95context->spicontext.spidev->dev;\n\tstruct nfc_digital_dev *nfcddev = st95context->ddev;\n\tunsigned char pp_typeb;\n\tstruct param_list new_params[2];\n\n\tpp_typeb = cmd_array[CMD_ISO14443B_PROTOCOL_SELECT].cmd_params[2];\n\n\tif (nfcddev->curr_protocol == NFC_PROTO_ISO14443 &&\n\t    st95context->fwi < 4)\n\t\tst95context->fwi = 4;\n\n\tnew_params[0].param_offset = 2;\n\tif (nfcddev->curr_protocol == NFC_PROTO_ISO14443)\n\t\tnew_params[0].new_param_val = st95context->fwi;\n\telse if (nfcddev->curr_protocol == NFC_PROTO_ISO14443_B)\n\t\tnew_params[0].new_param_val = pp_typeb;\n\n\tnew_params[1].param_offset = 3;\n\tnew_params[1].new_param_val = wtxm;\n\n\tswitch (nfcddev->curr_protocol) {\n\tcase NFC_PROTO_ISO14443:\n\t\tresult = st95hf_send_recv_cmd(st95context,\n\t\t\t\t\t      CMD_ISO14443A_PROTOCOL_SELECT,\n\t\t\t\t\t      2,\n\t\t\t\t\t      new_params,\n\t\t\t\t\t      true);\n\t\tif (result) {\n\t\t\tdev_err(dev, \"WTX type a sel proto, err = 0x%x\\n\",\n\t\t\t\tresult);\n\t\t\treturn result;\n\t\t}\n\n\t\t/* secondary config. for 14443Type 4A after protocol select */\n\t\tresult = secondary_configuration_type4a(st95context);\n\t\tif (result) {\n\t\t\tdev_err(dev, \"WTX type a second. config, err = 0x%x\\n\",\n\t\t\t\tresult);\n\t\t\treturn result;\n\t\t}\n\t\tbreak;\n\tcase NFC_PROTO_ISO14443_B:\n\t\tresult = st95hf_send_recv_cmd(st95context,\n\t\t\t\t\t      CMD_ISO14443B_PROTOCOL_SELECT,\n\t\t\t\t\t      2,\n\t\t\t\t\t      new_params,\n\t\t\t\t\t      true);\n\t\tif (result) {\n\t\t\tdev_err(dev, \"WTX type b sel proto, err = 0x%x\\n\",\n\t\t\t\tresult);\n\t\t\treturn result;\n\t\t}\n\n\t\t/* secondary config. for 14443Type 4B after protocol select */\n\t\tresult = secondary_configuration_type4b(st95context);\n\t\tif (result) {\n\t\t\tdev_err(dev, \"WTX type b second. config, err = 0x%x\\n\",\n\t\t\t\tresult);\n\t\t\treturn result;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}",
        "static int prepare_session_reconnect(struct ceph_connection *con)\n{\n\tstruct ceph_entity_addr *my_addr = &con->msgr->inst.addr;\n\tvoid *buf, *p;\n\tint ctrl_len;": "static int prepare_session_reconnect(struct ceph_connection *con)\n{\n\tstruct ceph_entity_addr *my_addr = &con->msgr->inst.addr;\n\tvoid *buf, *p;\n\tint ctrl_len;\n\n\tWARN_ON(!con->v2.client_cookie);\n\tWARN_ON(!con->v2.server_cookie);\n\tWARN_ON(!con->v2.connect_seq);\n\tWARN_ON(!con->v2.peer_global_seq);\n\n\tdout(\"%s con %p my_addr %s/%u client_cookie 0x%llx server_cookie 0x%llx global_seq %llu connect_seq %llu in_seq %llu\\n\",\n\t     __func__, con, ceph_pr_addr(my_addr), le32_to_cpu(my_addr->nonce),\n\t     con->v2.client_cookie, con->v2.server_cookie, con->v2.global_seq,\n\t     con->v2.connect_seq, con->in_seq);\n\n\tctrl_len = 1 + 4 + ceph_entity_addr_encoding_len(my_addr) + 5 * 8;\n\tbuf = alloc_conn_buf(con, head_onwire_len(ctrl_len, con_secure(con)));\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tp = CTRL_BODY(buf);\n\tceph_encode_8(&p, 2);  /* entity_addrvec_t marker */\n\tceph_encode_32(&p, 1);  /* my_addrs len */\n\tceph_encode_entity_addr(&p, my_addr);\n\tceph_encode_64(&p, con->v2.client_cookie);\n\tceph_encode_64(&p, con->v2.server_cookie);\n\tceph_encode_64(&p, con->v2.global_seq);\n\tceph_encode_64(&p, con->v2.connect_seq);\n\tceph_encode_64(&p, con->in_seq);\n\tWARN_ON(p != CTRL_BODY(buf) + ctrl_len);\n\n\treturn prepare_control(con, FRAME_TAG_SESSION_RECONNECT, buf, ctrl_len);\n}",
        "static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)\n{\n\t/* 0-3byte signature \"DKIF\" */\n\tdst[0] = 0x44;\n\tdst[1] = 0x4b;": "static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)\n{\n\t/* 0-3byte signature \"DKIF\" */\n\tdst[0] = 0x44;\n\tdst[1] = 0x4b;\n\tdst[2] = 0x49;\n\tdst[3] = 0x46;\n\t/* 4-5byte version: should be 0*/\n\tdst[4] = 0x00;\n\tdst[5] = 0x00;\n\t/* 6-7 length of Header */\n\tdst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;\n\tdst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;\n\t/* 8-11 VP8 fourcc */\n\tdst[8] = 0x56;\n\tdst[9] = 0x50;\n\tdst[10] = 0x38;\n\tdst[11] = 0x30;\n\t/* 12-13 width in pixels */\n\tdst[12] = width;\n\tdst[13] = width >> 8;\n\t/* 14-15 height in pixels */\n\tdst[14] = height;\n\tdst[15] = height >> 8;\n\t/* 16-19 frame rate */\n\tdst[16] = 0xe8;\n\tdst[17] = 0x03;\n\tdst[18] = 0x00;\n\tdst[19] = 0x00;\n\t/* 20-23 time scale */\n\tdst[20] = 0x01;\n\tdst[21] = 0x00;\n\tdst[22] = 0x00;\n\tdst[23] = 0x00;\n\t/* 24-27 number frames */\n\tdst[24] = 0xdf;\n\tdst[25] = 0xf9;\n\tdst[26] = 0x09;\n\tdst[27] = 0x00;\n\t/* 28-31 reserved */\n}",
        "static int try_offline_memory_block(struct memory_block *mem, void *arg)\n{\n\tuint8_t online_type = MMOP_ONLINE_KERNEL;\n\tuint8_t **online_types = arg;\n\tstruct page *page;": "static int try_offline_memory_block(struct memory_block *mem, void *arg)\n{\n\tuint8_t online_type = MMOP_ONLINE_KERNEL;\n\tuint8_t **online_types = arg;\n\tstruct page *page;\n\tint rc;\n\n\t/*\n\t * Sense the online_type via the zone of the memory block. Offlining\n\t * with multiple zones within one memory block will be rejected\n\t * by offlining code ... so we don't care about that.\n\t */\n\tpage = pfn_to_online_page(section_nr_to_pfn(mem->start_section_nr));\n\tif (page && zone_idx(page_zone(page)) == ZONE_MOVABLE)\n\t\tonline_type = MMOP_ONLINE_MOVABLE;\n\n\trc = device_offline(&mem->dev);\n\t/*\n\t * Default is MMOP_OFFLINE - change it only if offlining succeeded,\n\t * so try_reonline_memory_block() can do the right thing.\n\t */\n\tif (!rc)\n\t\t**online_types = online_type;\n\n\t(*online_types)++;\n\t/* Ignore if already offline. */\n\treturn rc < 0 ? rc : 0;\n}",
        "static void test_pidfd_fdinfo_nspid(void)\n{\n\tstruct child a, b;\n\tstruct error err = {0, };\n\tconst char *test_name = \"pidfd check for NSpid in fdinfo\";": "static void test_pidfd_fdinfo_nspid(void)\n{\n\tstruct child a, b;\n\tstruct error err = {0, };\n\tconst char *test_name = \"pidfd check for NSpid in fdinfo\";\n\n\t/* Create a new child in a new pid and mount namespace */\n\ta = clone_newns(child_fdinfo_nspid_test, NULL, &err);\n\terror_check(&err, test_name);\n\n\t/* Pass the pidfd representing the first child to the\n\t * second child, which will be in a sibling pid namespace,\n\t * which means that the fdinfo NSpid entry for the pidfd\n\t * should only contain '0'.\n\t */\n\tb = clone_newns(child_fdinfo_nspid_test, &a.fd, &err);\n\terror_check(&err, test_name);\n\n\t/* The children will have pid 1 in the new pid namespace,\n\t * so the line must be 'NSPid:\\t<pid>\\t1'.\n\t */\n\tverify_fdinfo(a.fd, &err, \"NSpid:\", 6, \"\\t%d\\t%d\\n\", a.pid, 1);\n\tverify_fdinfo(b.fd, &err, \"NSpid:\", 6, \"\\t%d\\t%d\\n\", b.pid, 1);\n\n\t/* wait for the process, check the exit status and set\n\t * 'err' accordingly, if it is not already set.\n\t */\n\tchild_join_close(&a, &err);\n\tchild_join_close(&b, &err);\n\n\terror_report(&err, test_name);\n}",
        "static unsigned rb_calculate_event_length(unsigned length)\n{\n\tstruct ring_buffer_event event; /* Used only for sizeof array */\n\n\t/* zero length can cause confusions */": "static unsigned rb_calculate_event_length(unsigned length)\n{\n\tstruct ring_buffer_event event; /* Used only for sizeof array */\n\n\t/* zero length can cause confusions */\n\tif (!length)\n\t\tlength++;\n\n\tif (length > RB_MAX_SMALL_DATA || RB_FORCE_8BYTE_ALIGNMENT)\n\t\tlength += sizeof(event.array[0]);\n\n\tlength += RB_EVNT_HDR_SIZE;\n\tlength = ALIGN(length, RB_ARCH_ALIGNMENT);\n\n\t/*\n\t * In case the time delta is larger than the 27 bits for it\n\t * in the header, we need to add a timestamp. If another\n\t * event comes in when trying to discard this one to increase\n\t * the length, then the timestamp will be added in the allocated\n\t * space of this event. If length is bigger than the size needed\n\t * for the TIME_EXTEND, then padding has to be used. The events\n\t * length must be either RB_LEN_TIME_EXTEND, or greater than or equal\n\t * to RB_LEN_TIME_EXTEND + 8, as 8 is the minimum size for padding.\n\t * As length is a multiple of 4, we only need to worry if it\n\t * is 12 (RB_LEN_TIME_EXTEND + 4).\n\t */\n\tif (length == RB_LEN_TIME_EXTEND + RB_ALIGNMENT)\n\t\tlength += RB_ALIGNMENT;\n\n\treturn length;\n}",
        "static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)\n{\n\tstruct adapter *adapter = dm_odm->Adapter;\n\tu32\tvalue32;\n": "static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)\n{\n\tstruct adapter *adapter = dm_odm->Adapter;\n\tu32\tvalue32;\n\n\t/* MAC Setting */\n\tvalue32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */\n\t/* Pin Settings */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0\tantsel antselb by HW */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);\t/* Reg864[10]=1'b0\tantsel2 by HW */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);\t/* Regb2c[22]=1'b0\tdisable CS/CG switch */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);\t/* Regb2c[31]=1'b1\toutput at CG only */\n\t/* OFDM Settings */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);\n\t/* CCK Settings */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */\n\tODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);\n\trtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);\t/* antenna mapping table */\n}",
        "static void teo_update(struct cpuidle_driver *drv, struct cpuidle_device *dev)\n{\n\tstruct teo_cpu *cpu_data = per_cpu_ptr(&teo_cpus, dev->cpu);\n\tint i, idx_timer = 0, idx_duration = 0;\n\tu64 measured_ns;": "static void teo_update(struct cpuidle_driver *drv, struct cpuidle_device *dev)\n{\n\tstruct teo_cpu *cpu_data = per_cpu_ptr(&teo_cpus, dev->cpu);\n\tint i, idx_timer = 0, idx_duration = 0;\n\tu64 measured_ns;\n\n\tif (cpu_data->time_span_ns >= cpu_data->sleep_length_ns) {\n\t\t/*\n\t\t * One of the safety nets has triggered or the wakeup was close\n\t\t * enough to the closest timer event expected at the idle state\n\t\t * selection time to be discarded.\n\t\t */\n\t\tmeasured_ns = U64_MAX;\n\t} else {\n\t\tu64 lat_ns = drv->states[dev->last_state_idx].exit_latency_ns;\n\n\t\t/*\n\t\t * The computations below are to determine whether or not the\n\t\t * (saved) time till the next timer event and the measured idle\n\t\t * duration fall into the same \"bin\", so use last_residency_ns\n\t\t * for that instead of time_span_ns which includes the cpuidle\n\t\t * overhead.\n\t\t */\n\t\tmeasured_ns = dev->last_residency_ns;\n\t\t/*\n\t\t * The delay between the wakeup and the first instruction\n\t\t * executed by the CPU is not likely to be worst-case every\n\t\t * time, so take 1/2 of the exit latency as a very rough\n\t\t * approximation of the average of it.\n\t\t */\n\t\tif (measured_ns >= lat_ns)\n\t\t\tmeasured_ns -= lat_ns / 2;\n\t\telse\n\t\t\tmeasured_ns /= 2;\n\t}\n\n\tcpu_data->total = 0;\n\n\t/*\n\t * Decay the \"hits\" and \"intercepts\" metrics for all of the bins and\n\t * find the bins that the sleep length and the measured idle duration\n\t * fall into.\n\t */\n\tfor (i = 0; i < drv->state_count; i++) {\n\t\ts64 target_residency_ns = drv->states[i].target_residency_ns;\n\t\tstruct teo_bin *bin = &cpu_data->state_bins[i];\n\n\t\tbin->hits -= bin->hits >> DECAY_SHIFT;\n\t\tbin->intercepts -= bin->intercepts >> DECAY_SHIFT;\n\n\t\tcpu_data->total += bin->hits + bin->intercepts;\n\n\t\tif (target_residency_ns <= cpu_data->sleep_length_ns) {\n\t\t\tidx_timer = i;\n\t\t\tif (target_residency_ns <= measured_ns)\n\t\t\t\tidx_duration = i;\n\t\t}\n\t}\n\n\ti = cpu_data->next_recent_idx++;\n\tif (cpu_data->next_recent_idx >= NR_RECENT)\n\t\tcpu_data->next_recent_idx = 0;\n\n\tif (cpu_data->recent_idx[i] >= 0)\n\t\tcpu_data->state_bins[cpu_data->recent_idx[i]].recent--;\n\n\t/*\n\t * If the measured idle duration falls into the same bin as the sleep\n\t * length, this is a \"hit\", so update the \"hits\" metric for that bin.\n\t * Otherwise, update the \"intercepts\" metric for the bin fallen into by\n\t * the measured idle duration.\n\t */\n\tif (idx_timer == idx_duration) {\n\t\tcpu_data->state_bins[idx_timer].hits += PULSE;\n\t\tcpu_data->recent_idx[i] = -1;\n\t} else {\n\t\tcpu_data->state_bins[idx_duration].intercepts += PULSE;\n\t\tcpu_data->state_bins[idx_duration].recent++;\n\t\tcpu_data->recent_idx[i] = idx_duration;\n\t}\n\n\tcpu_data->total += PULSE;\n}"
    }
}