Position: RTL Design Engineer (Verilog, VHDL)
Company: CapitalRecruiters
Category: C++
Experience required: 2y
English level: intermediate
Published: 2020-03-01T00:00:00+02:00

The project: Verilog-based HW IP Core development which use hundreds of millions of users worldwide. 

Key words would be: RTL Design, Verilog, VHDL, C, UVM.

Position: RTL Design Engineer. Location – Kyiv. Team size: 4 developers.

Responsibilities:

Design, test and develop  RTL code for HW IP Cores;
Research activities and strategic prototyping for future companies products.

Requirements:

3 years of experience on developing HDL (Verilog, VHDL);
1+ year of experience with C language;
Bachelor degree;

Will be a plus:

Knowlage of SystemVerilog/SystemС;
Development and testing FPGA platform;
Shell scripting;
Pseudo-random, functional coverage verification methodologies, UVM;
good technical English.

We offer:

Official employment;
Medical insurance, life insurance;
28 days of paid vacation and you can take 15 days at your own expense;
flexible working hours;
corporate taxi;
ability to get a bonus on the results of work 2 times a year;
bonus for a patent, the ability to realize own projects;
bonus for a wedding, birth of children and other significant events;
external and internal trainings;
foreign language courses;
professional literature;
internships within the company (in other departments);
discounts on Sport Life;
bicycle parking.