Position: Design for Test Engineer
Company: RINF tech
Category: C++
Experience required: 5y
English level: upper
Published: 2020-06-01T00:00:00+03:00

We need a team to make a new chip. 

EDE is a product chip that aims to serve communication applications into cars. Radar is a test chip that aims to sense short Radar wave and to process it. Both projects are targeted the same technology node with system re-use.
It explains why a RFI is performing for both projects.
Tap-out date is still under definition with acquisition phase project.

**Responsibilities:**
 
⬥Understand/review and follow the DFT and in-field self-test strategy for the design (IP, systems or Top level)

⬥Follow SOC DFT and in-field-self test requirements

⬥Fine tune the DFT design Document

⬥Contribute to build the DFT infrastructure and network for Scan test and specific BIST test

⬥Contribute to the integration of previous DFT hardware in the RTL design based on previous DFT strategy and in-field self-test requirements (according design IP Milestones)

⬥Contribute to verification of DFT related topics

⬥Contribute to Test pattern generation at the IP, Systems level or Top level to allow later test pattern porting at SOC level

⬥Support to implementation team to ensure proper design scan insertion in line with the requested test coverage target

**Skills needed:**
Design for Test for IC 
Scan test, ATPG 
IEEE1500, SMS/SHS technology by Synopsys 
AMS / Memory BIST test pattern dev