Position: Field Applications Engineer
Company: Freelance
Category: Other
Experience required: 5y
English level: fluent
Published: 2021-01-01T00:00:00+02:00

A ONCE IN A LIFE TIME OPPORTUNITY!

Are looking for an exciting career move? Find one with a successful startup in the field of Electronic Design Automation! We are looking for an applications engineers to join our client’s team! Come work with a team of top-notch experts in the field of clock verification, RTL sign off and automatic formal. Get an exciting work environment with competitive compensation and benefits!

RESPONSIBILITIES:

The Field Applications Engineer is a vital member of the Applications Engineering Team. The FAE works with customers to provide superb technical consultation and maintain strong customer relationships. The position has primary responsibility for the technical success of software evaluations at prospective customers as well as tool deployment in existing accounts. Candidates must be able to effectively work with Engineering and Marketing departments to define software improvements, address market opportunities, and resolve customer issues with software tools.

QUALIFICATIONS:
Bachelor of Science in Electrical Engineering or equivalent plus 5-8 years of experience or Master of Science in Electrical Engineering with 3-5 years of experience in digital design, hardware verification, or applications engineering, with a proven track record for customer satisfaction;
Detailed working knowledge of Verilog and/or VHDL; System Verilog familiarity required, working knowledge a plus;
Excellent communication and technical presentation skills, both verbal and written;
A self-starter with a history of driving projects to completion under tight schedules;
Hands-on, technical in-depth experience in at least two of the following areas:
Asynchronous clock domain crossing verification on large SoC designs;
Current commercial hardware RTL linting technologies, including detailed knowledge of rule sets;
Hardware static timing analysis (STA) / timing closure flows involving SDC timing files;
Assertion-based formal property hardware verification;
Testbench-driven hardware simulation flows;
Up to 25% travel required, including international;
Fluent English is a must.

QUIRKS & PERKS:
Competitive monthly salary (to be negotiated with a company);
Bonuses and incentives according to company’s policy;
A great opportunity to join a leading international company and collaborate with it’s clients around the world!