page_title: JTAG
section_title: Connectors
hierarchical_section_title: JTAG / Client support / Connectors
caption_attribution_description: English: Netgear FVS336G network appliance inside, revealing JTAG interface.
context_page_description: JTAG is an industry standard for verifying designs and testing printed circuit boards after manufacture.
  JTAG implements standards for on-chip instrumentation in electronic design automation as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses. The interface connects to an on-chip Test Access Port that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts.
  The Joint Test Action Group formed in 1985 to develop a method of verifying designs and testing printed circuit boards after manufacture. In 1990 the Institute of Electrical and Electronics Engineers codified the results of the effort in IEEE Standard 1149.1-1990, entitled Standard Test Access Port and Boundary-Scan Architecture.
  The JTAG standards have been extended by many semiconductor chip manufacturers with specialized variants to provide vendor-specific features.
context_section_description: There are no official standards for JTAG adapter physical connectors.  Development boards usually include a header to support preferred development tools; in some cases they include multiple such headers, because they need to support multiple such tools.  For example, a microcontroller, FPGA, and ARM application processor rarely share tools, so a development board using all of those components might have three or more headers.  Production boards may omit the headers, or when space is limited may provide JTAG signal access using test points.
  Some common pinouts for 2.54 mm (0.100 in) pin headers are:
  ARM 2×10 pin (or sometimes the older 2×7), used by almost all ARM based systems
  MIPS EJTAG (2×7 pin) used for MIPS based systems
  2×5 pin Altera ByteBlaster-compatible JTAG extended by many vendors
  2×5 pin AVR extends Altera JTAG with SRST (and in some cases TRST and an event output)
  2×7 pin Texas Instruments used with DSPs and ARM-based products such as OMAP
  8 pin (single row) generic PLD JTAG compatible with many Lattice ispDOWNLOAD cables
  MIPI10-/20-connectors (1.27 mm 050") for JTAG, cJTAG and SWD
  Those connectors tend to include more than just the four standardized signals (TMS, TCK, TDI, TDO).  Usually reset signals are provided, one or both of TRST (TAP reset) and SRST (system reset).  The connector usually provides the board-under-test's logic supply voltage so that the JTAG adapters use the appropriate logic levels. The board voltage may also serve as a "board present" debugger input.  Other event input or output signals may be provided, or general purpose I/O (GPIO) lines, to support more complex debugging architectures.
  Higher end products frequently use dense connectors (frequently 38-pin MICTOR connectors) to support high-speed tracing in conjunction with JTAG operations.  A recent trend is to have development boards integrate a USB interface to JTAG, where a second channel is used for a serial port.  (Smaller boards can also be powered through USB.  Since modern PCs tend to omit serial ports, such integrated debug links can significantly reduce clutter for developers.)  Production boards often rely on bed-of-nails connections to test points for testing and programming.
caption: A Netgear FVS336G firewall with a 14 pin JTAG header at lower left.
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