page_title: Zilog Z280
hierarchical_section_title: Zilog Z280
caption_attribution_description: English: STEbus Z280 CPU on 100x160mm Eurocard. Designed by Arcom Control Systems. Low quality scan taken from catalogue cover.
context_page_description: The Zilog Z280 is a 16-bit microprocessor, an enhancement of the Zilog Z80 architecture, introduced in July 1987. It is basically the Z800, renamed, with slight improvements such as being fabricated in CMOS. It was a commercial failure. Zilog added a memory management unit to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It is capable of efficiently handling 32-bit data operations including hardware multiply, divide, and sign extension. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes. Its internal clock signal can be configured to run at 1, 2 or 4 times the external clock's speed. Unlike the Z80 the Z280 uses a multiplexed arrangement for its address and data busses. More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others.
context_section_description: The Zilog Z280 is a 16-bit microprocessor, an enhancement of the Zilog Z80 architecture, introduced in July 1987. It is basically the Z800, renamed, with slight improvements such as being fabricated in CMOS.  It was a commercial failure. Zilog added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It is capable of efficiently handling 32-bit data operations including hardware multiply, divide, and sign extension. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes (four total possible address spaces). Its internal clock signal can be configured to run at 1, 2 or 4 times the external clock's speed (e.g. a 12MHz CPU with a 3 MHz bus). Unlike the Z80 the Z280 uses a multiplexed arrangement for its address and data busses. More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others. See further Zilog Z800.
  The Z280 had many advanced features for its time, most of them never seen again on a Zilog processor:
  On-chip instruction and/or data cache, or on-chip RAM
  Instruction Pipelining
  High performance 16-bit Z-BUS interface or 8-bit Z80-compatible bus interface
  Built-in MMU with memory protection
  Ability to determine which register set is in context with instructions JAF and JAR
  Four on-chip 16-bit counter/timers
  Four on-chip DMA channels
  On-chip full duplex UART
  User I/O trap
  Supervisor mode (privileged instructions)
  Illegal instruction trap
  Coprocessor emulation trap
  Burst mode memory access
  Multiprocessor support, with many bus configuration modes
  Support for multiple external coprocessors through an accelerated communication interface
  Multiple I/O pages, which also allows for internal I/O devices without restricting the address range of the I/O ports like on eZ80, or conflicting with existing motherboard devices, like the Z180.
  Stack overflow warning
caption: STEbus Z280 processor
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