page_title: Fully Buffered DIMM
section_title: Technology
hierarchical_section_title: Fully Buffered DIMM / Technology
caption_attribution_description: English: On this photo FB-DIMM DDR2 memory attached to DDR2 memory to show that notch shifted.
context_page_description: Fully Buffered DIMM is a memory technology that can be used to increase reliability and density of memory systems. Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module, i.e. via multidrop buses. As the memory width increases together with the access speed, the signal degrades at the interface between the bus and the device. This limits the speed and memory density, so FB-DIMMs take a different approach to solve the problem.
  240-pin DDR2 FB-DIMMs are neither mechanically nor electrically compatible with conventional 240-pin DDR2 DIMMs. As a result, those two DIMM types are notched differently to prevent using the wrong one.
  As with nearly all RAM specifications, the FB-DIMM specification was published by JEDEC.
context_section_description: Fully buffered DIMM architecture introduces an advanced memory buffer (AMB) between the memory controller and the memory module. Unlike the parallel bus architecture of traditional DRAMs, an FB-DIMM has a serial interface between the memory controller and the AMB. This enables an increase to the width of the memory without increasing the pin count of the memory controller beyond a feasible level. With this architecture, the memory controller does not write to the memory module directly; rather it is done via the AMB.  AMB can thus compensate for signal deterioration by buffering and resending the signal.
  The AMB can also offer error correction, without imposing any additional overhead on the processor or the system's memory controller. It can also use the Bit Lane Failover Correction feature to identify bad data paths and remove them from operation, which dramatically reduces command/address errors. Also, since reads and writes are buffered, they can be done in parallel by the memory controller. This allows simpler interconnects, and (in theory) hardware-agnostic memory controller chips (such as DDR2 and DDR3) that can be used interchangeably.
  The downsides to this approach are; it introduces latency to the memory request, it requires additional power consumption for the buffer chips, and current implementations create a memory write bus significantly narrower than the memory read bus. This means workloads that use many writes (such as high-performance computing) will be significantly slowed. However, this slowdown is nowhere near as bad as not having enough memory capacity to avoid using significant amounts of virtual memory, so workloads that use extreme amounts of memory in irregular patterns might be helped by using fully buffered DIMMs.
caption: FB-DIMM DDR2 vs DIMM DDR2
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