page_title: Floorplan (microelectronics)
section_title: Sliceable floorplans
hierarchical_section_title: Floorplan (microelectronics) / Mathematical models and optimization problems / Sliceable floorplans
caption_attribution_description: An example of sliceable floorplan
context_page_description: In electronic design automation, a floorplan of an integrated circuit is a schematics representation of tentative placement of its major functional blocks.
  In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to integrated circuit design.
  Depending on the design methodology being followed, the actual definition of a floorplan may differ.
context_section_description: A sliceable  floorplan is a floorplan that may be defined recursively as described below. 
  A floorplan that consists of a single rectangular block is sliceable.
  If a block from a sliceable floorplan is cut ("sliced") in two by a vertical or horizontal line, the resulting floorplan is sliceable.
  Sliceable floorplans have been used in a number of  early Electronic Design Automation tools for a number of reasons. Sliceable floorplans may be conveniently represented by binary trees (more specifically, k-d trees), which correspond to the order of slicing. More importantly, a number of NP-hard problems with floorplans have polynomial time algorithms when restricted to sliceable floorplans.
caption: A sliceable floorplan, with a slicing order indicated
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