page_title: Instruction-level parallelism
hierarchical_section_title: Instruction-level parallelism
caption_attribution_description: Atanasoff-Berry Computer at Durhum Center, Iowa State University
context_page_description: Instruction-level parallelism is a measure of how many of the instructions in a computer program can be executed simultaneously.
  ILP must not be confused with concurrency, since the first is about parallel execution of a sequence of instructions belonging to a specific thread of execution of a process. Conversely, concurrency regards with the threads of one or different processes being assigned to a CPU's core in a strict alternance or in true parallelism if there are enough CPU's cores, ideally one core for each runnable thread.
  There are two approaches to instruction level parallelism: Hardware and Software.
  Hardware level works upon dynamic parallelism, whereas the software level works on static parallelism. Dynamic parallelism means the processor decides at run time which instructions to execute in parallel, whereas static parallelism means the compiler decides which instructions to execute in parallel. The Pentium processor works on the dynamic sequence of parallel execution, but the Itanium processor works on the static level parallelism.
  Consider the following program:
  1 e = a + b
  2 f = c + d
  3 m = e * f
context_section_description: Instruction-level parallelism (ILP) is a measure of how many of the instructions in a computer program can be executed simultaneously.
  ILP must not be confused with concurrency, since the first is about parallel execution of a sequence of instructions belonging to a specific thread of execution of a process (that is a running program with its set of  resources - for example its address space, a set of registers, its identifiers, its state, program counter, and more). Conversely,  concurrency regards with the threads of one or different  processes being assigned to a CPU's core in a strict alternance or in true parallelism if there are enough CPU's cores, ideally one core for each runnable thread. 
  There are two approaches to instruction level parallelism: Hardware and Software. 
  Hardware level works upon dynamic parallelism, whereas the software level works on static parallelism. Dynamic parallelism means the processor decides at run time which instructions to execute in parallel, whereas static parallelism means the compiler decides which instructions to execute in parallel. The Pentium processor works on the dynamic sequence of parallel execution, but the Itanium processor works on the static level parallelism.
  Consider the following program:
  1   e = a + b
  2   f = c + d
  3   m = e * f
  Operation 3 depends on the results of operations 1 and 2, so it cannot be calculated until both of them are completed.  However, operations 1 and 2 do not depend on any other operation, so they can be calculated simultaneously.  If we assume that each operation can be completed in one unit of time then these three instructions can be completed in a total of two units of time, giving an ILP of 3/2.
  A goal of compiler and processor designers is to identify and take advantage of as much ILP as possible. Ordinary programs are typically written under a sequential execution model where instructions execute one after the other and in the order specified by the programmer. ILP allows the compiler and the processor to overlap the execution of multiple instructions or even to change the order in which instructions are executed.
  How much ILP exists in programs is very application specific. In certain fields, such as graphics and scientific computing the amount can be very large. However, workloads such as cryptography may exhibit much less parallelism.
  Micro-architectural techniques that are used to exploit ILP include:
  Instruction pipelining where the execution of multiple instructions can be partially overlapped.
  Superscalar execution, VLIW, and the closely related explicitly parallel instruction computing concepts, in which multiple execution units are used to execute multiple instructions in parallel.
  Out-of-order execution where instructions execute in any order that does not violate data dependencies. Note that this technique is independent of both pipelining and superscalar execution. Current implementations of out-of-order execution dynamically (i.e., while the program is executing and without any help from the compiler) extract ILP from ordinary programs. An alternative is to extract this parallelism at compile time and somehow convey this information to the hardware. Due to the complexity of scaling the out-of-order execution technique, the industry has re-examined instruction sets which explicitly encode multiple independent operations per instruction.
  Register renaming which refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations, used to enable out-of-order execution.
  Speculative execution which allows the execution of complete instructions or parts of instructions before being certain whether this execution should take place. A commonly used form of speculative execution is control flow speculation where instructions past a control flow instruction (e.g., a branch) are executed before the target of the control flow instruction is determined. Several other forms of speculative execution have been proposed and are in use including speculative execution drive
caption: Atanasoff–Berry computer, the first computer with parallel processing[1]
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