page_title: Power ISA
hierarchical_section_title: Power ISA
caption_attribution_description: English: A highly schematic diagram of a generic Power Architecture microprocessor.
context_page_description: The Power ISA is an instruction set architecture developed by the OpenPOWER Foundation, led by IBM. It was originally developed by the now defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.
  Power ISA is a RISC load/store architecture. It has multiple sets of registers:
  thirty-two 32-bit or 64-bit general purpose registers for integer operations.
  sixty-four 128-bit vector scalar registers for vector operations and floating point operations.
  thirty-two 64-bit floating-point registers as part of the VSRs for floating point operations.
context_section_description: The Power ISA is an instruction set architecture (ISA) developed by the OpenPOWER Foundation, led by IBM. It was originally developed by the now defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.
  Power ISA is a RISC load/store architecture. It has multiple sets of registers:
  thirty-two 32-bit or 64-bit general purpose registers (GPRs) for integer operations.
  sixty-four 128-bit vector scalar registers (VSRs) for vector operations and floating point operations.
  thirty-two 64-bit floating-point registers (FPRs) as part of the VSRs for floating point operations.
  thirty-two 128-bit vector registers (VRs) as part of the VSRs for vector operations.
  Eight 4-bit condition register fields (CRs) for comparison and control flow.
  Special registers: counter register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).
  Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions.  There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.
  Power ISA has support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, as well as support for both 32-bit and 64-bit addressing.
  Different modes of operation include user, supervisor and hypervisor.
caption: A highly schematic diagram over a generic Power ISA processor.
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