page_title: Integrated circuit design
section_title: Physical design
hierarchical_section_title: Integrated circuit design / Design process / Physical design
caption_attribution_description: English: Major steps in VLSI physical design Deutsch: Die wichtigsten Schritte beim VLSI Layoutentwurf
context_page_description: Integrated circuit design, or IC design, is a subset of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.
  IC design can be divided into the broad categories of digital and analog IC design. Digital IC design is to produce components such as microprocessors, FPGAs, memories and digital ASICs. Digital design focuses on logical correctness, maximizing circuit density, and placing circuits so that clock and timing signals are routed efficiently. Analog IC design also has specializations in power IC design and RF IC design. Analog IC design is used in the design of op-amps, linear regulators, phase locked loops, oscillators and active filters. Analog design is more concerned with the physics of the semiconductor devices such as gain, matching, power dissipation, and resistance.
context_section_description: RTL is only a behavioral model of the actual functionality of what the chip is supposed to operate under. It has no link to a physical aspect of how the chip would operate in real life at the materials, physics, and electrical engineering side. For this reason, the next step in the IC design process, physical design stage, is to map the RTL into actual geometric representations of all electronics devices, such as capacitors, resistors, logic gates, and transistors that will go on the chip.
  The main steps of physical design are listed below. In practice there is not a straightforward progression - considerable iteration is required to ensure all objectives are met simultaneously.  This is a difficult problem in its own right, called design closure.
  Logic synthesis:  The RTL is mapped into a gate-level netlist in the target technology of the chip.
  Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned and large objects (arrays, cores, etc.) are placed.
  Placement:  The gates in the netlist are assigned to nonoverlapping locations on the die area.
  Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints.
  Clock insertion: Clock signal wiring is (commonly, clock trees)  introduced into the design.
  Routing: The wires that connect the gates in the netlist are added.
  Postwiring optimization:  Performance (timing closure), noise (signal integrity), and yield (Design for manufacturability) violations are removed.
  Design for manufacturability:  The design is modified, where possible, to make it as easy and efficient as possible to produce. This is achieved by adding extra vias or adding dummy metal/diffusion/poly layers wherever possible while complying to the design rules set by the foundry.
  Final checking: Since errors are expensive, time consuming and hard to spot, extensive error checking is the rule, making sure the mapping to logic was done correctly, and checking that the manufacturing rules were followed faithfully.
  Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.
caption: Physical design steps within the digital design flow
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