page_title: CDC Cyber
section_title: Cyber 70 and 170 series
hierarchical_section_title: CDC Cyber / Models / Cyber 70 and 170 series
caption_attribution_description: English: Control Data Corporation twenty-two-ring binder for documentation on their computers
context_page_description: The CDC Cyber range of mainframe-class supercomputers were the primary products of Control Data Corporation during the 1970s and 1980s. In their day, they were the computer architecture of choice for scientific and mathematically intensive computing. They were used for modeling fluid flow, material science stress analysis, electrochemical machining analysis, probabilistic analysis, energy and academic computing, radiation shielding modeling, and other applications. The lineup also included the Cyber 18 and Cyber 1000 minicomputers. Like their predecessor, the CDC 6600, they were unusual in using the ones' complement binary representation.
context_section_description: The Cyber 70 and 170 architectures were successors to the earlier CDC 6600 and CDC 7600 series and therefore shared almost all of the earlier architecture's characteristics.  The Cyber-70 series is a minor upgrade from the earlier systems.  The Cyber-170 series represented CDCs move from discrete electronic components and core memory to integrated circuits and semiconductor memory.  The 172, 173, and 174 use integrated circuits and semiconductor memory whereas the 175 uses high-speed discrete transistors.  The Cyber-170/700 series is a late-1970s refresh of the Cyber-170 line.
  The central processor (CPU) and central memory (CM) operated in units of 60-bit words.  In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors).  Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits.
  The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which is semiconductor memory in this series.  The central processor has no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.
  A Cyber 170-series system consists of one or two CPUs that run at either 25 or 40 MHz, and is equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed I/O. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating-point divides), the higher-end CPUs (e.g., Cyber-74, Cyber-76, Cyber-175, and Cyber-176) are equipped with eight or twelve words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which is usually called in-stack) runs very fast, without referencing main memory for instruction fetch.  The lower-end models do not contain an instruction stack.  However, since up to four instructions are packed into each 60-bit word, some degree of prefetching is inherent in the design.
  As with predecessor systems, the Cyber 170 series has eight 18-bit address registers (A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7).  Seven of the A registers are tied to their corresponding X register.  Setting A1 through A5 reads that address and fetches it into the corresponding X1 through X5 register.  Likewise, setting register A6 or A7 writes the corresponding X6 or X7 register to central memory at the address written to the A register.  A0 is effectively a scratch register.
  The higher-end CPUs consisted of multiple functional units (e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions.  This parallelism allows assembly programmers to minimize the effects of the system's slow memory fetch time by pre-fetching data from central memory well before that data is needed.  By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch can be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer can write extremely efficient code that makes the most of the power of the hardware.
  The peripheral processor subsystem uses a technique known as barrel and slot to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware multiprogramming. The peripheral processors have 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP has access to all I/O channels and all of the system's central memory (CM) in addition to the PP's own memory.  The PP instruction set lacks, for example, extensive arithmetic capabilities and does not run user code; the peripheral processor subsystem's purpose is to process 
caption: CDC documentation came in single sheets punched for three-ring- or twenty-two-ring binders, so updates were easily accomplished.
exif: {"Image ImageWidth": "6000", "Image ImageLength": "4000", "Image BitsPerSample": "[8, 8, 8]", "Image PhotometricInterpretation": "2", "Image Make": "NIKON CORPORATION", "Image Model": "NIKON D7100", "Image Orientation": "Horizontal (normal)", "Image SamplesPerPixel": "3", "Image XResolution": "300", "Image YResolution": "300", "Image ResolutionUnit": "Pixels/Inch", "Image Software": "Adobe Photoshop Elements 13.0 (Windows)", "Image DateTime": "2015:02:03 20:19:15", "Image Artist": "Judson McCranie, jud@judmccranie.com", "Image YCbCrPositioning": "Co-sited", "Image Copyright": "Copyright Judson McCranie 2015", "Image ExifOffset": "412", "GPS GPSVersionID": "[2, 3, 0, 0]", "Image GPSInfo": "1120", "Thumbnail Compression": "JPEG (old-style)", "Thumbnail XResolution": "72", "Thumbnail YResolution": "72", "Thumbnail ResolutionUnit": "Pixels/Inch", "Thumbnail JPEGInterchangeFormat": "1234", "Thumbnail JPEGInterchangeFormatLength": "3746", "EXIF ExposureTime": "1/60", "EXIF FNumber": "5", "EXIF ExposureProgram": "Program Normal", "EXIF ISOSpeedRatings": "800", "EXIF SensitivityType": "Recommended Exposure Index", "EXIF ExifVersion": "0230", "EXIF DateTimeOriginal": "2015:02:03 20:16:14", "EXIF DateTimeDigitized": "2015:02:03 20:16:14", "EXIF ComponentsConfiguration": "YCbCr", "EXIF CompressedBitsPerPixel": "4", "EXIF ShutterSpeedValue": "5906891/1000000", "EXIF ApertureValue": "290241/62500", "EXIF ExposureBiasValue": "1/3", "EXIF MaxApertureValue": "43/10", "EXIF MeteringMode": "Pattern", "EXIF LightSource": "Unknown", "EXIF Flash": "Flash fired, compulsory flash mode, return light detected", "EXIF FocalLength": "40", "EXIF SubSecTime": "60", "EXIF SubSecTimeOriginal": "60", "EXIF SubSecTimeDigitized": "60", "EXIF FlashPixVersion": "0100", "EXIF ColorSpace": "sRGB", "EXIF ExifImageWidth": "3602", "EXIF ExifImageLength": "4000", "Interoperability InteroperabilityIndex": "R98", "Interoperability InteroperabilityVersion": "[48, 49, 48, 48]", "EXIF InteroperabilityOffset": "1088", "EXIF SensingMethod": "One-chip color area", "EXIF FileSource": "Digital Camera", "EXIF SceneType": "Directly Photographed", "EXIF CVAPattern": "[2, 0, 2, 0, 0, 1, 1, 2]", "EXIF CustomRendered": "Normal", "EXIF ExposureMode": "Auto Exposure", "EXIF WhiteBalance": "Auto", "EXIF DigitalZoomRatio": "1", "EXIF FocalLengthIn35mmFilm": "60", "EXIF SceneCaptureType": "Standard", "EXIF GainControl": "Low gain up", "EXIF Contrast": "Normal", "EXIF Saturation": "Normal", "EXIF Sharpness": "Normal", "EXIF SubjectDistanceRange": "0"}