page_title: Synchronous Serial Interface
section_title: Single transmission
hierarchical_section_title: Synchronous Serial Interface / SSI timing and transmission / Single transmission
caption_attribution_description: English: Timing diagram for SSI single transmission
context_page_description: Synchronous Serial Interface is a widely used serial interface standard for industrial applications between a master and a slave. SSI is based on RS-422 standards and has a high protocol efficiency in addition to its implementation over various hardware platforms, making it very popular among sensor manufacturers. SSI was originally developed by Max Stegmann GmbH in 1984 for transmitting the position data of absolute encoders – for this reason, some servo/drive equipment manufacturers refer to their SSI port as a "Stegmann Interface".
  It was formerly covered by the German patent DE 34 45 617 which expired in 1990. It is very suitable for applications demanding reliability and robustness in measurements under varying industrial environments.
  It is different from the Serial Peripheral Interface Bus: An SSI bus is differential, simplex, non-multiplexed, and relies on a time-out to frame the data. An SPI bus is single-ended, duplex, and uses a select-line to frame the data. However, SPI peripherals on microcontrollers can implement SSI with external differential driver-ICs and program-controlled timing.
context_section_description: The diagram illustrates the single data transmission using SSI protocol:
  The SSI is initially in the idle mode, where both the data and clock lines stay HIGH and the slave keeps updating its current data.
  The transmission mode is evoked when the master initiates a train of clock pulses. Once the slave receives the beginning of the clock signal (1), it automatically freezes its current data. With the first rising edge (2) of the clock sequence, the MSB of the sensor’s value is transmitted and with consequent rising edges, the bits are sequentially transmitted to the output.
  After the transmission of complete data word (3) (i.e. LSB is transmitted), an additional rising edge of the clock sets the clock line HIGH. The data line is set to LOW and remains there for a period of time, tm, to recognize the transfer timeout . If a clock signal (data-output request) is received within that time, the same data will be transmitted again (multiple transmission).
  The slave starts updating its value and the data line is set to HIGH (idle mode) if there are no clock pulses within time, tm. This marks the end of single transmission of the data word. Once the slave receives a clock signal at a time, tp (>=tm), the updated position value is frozen and the transmission of the value begins as described earlier.
caption: Single Transmission of the SSI Interface: 1. Freezing of the data. 2. Transmission of the first Databit. 3. End of transmission. 4. after the pause time the SSI went back to idle state – is ready for new transmission.
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