page_title: TopoR
section_title: Features
hierarchical_section_title: TopoR / Features
caption_attribution_description: English: Single-layer routing in TopoR autorouter Русский: Пример трассировки однослойной печатной платы в САПР TopoR
context_page_description: TopoR is an EDA program developed and maintained by the Russian company Eremex. It is dedicated to laying out a printed circuit board. The current version is 6.3.17875 as of 2017-09-20.
  It features a powerful autorouter and a set of tools intended to reduce the amount of effort needed for manual routing of a PCB. The most recognizable feature of TopoR is the absence of preferred routing directions, which results in unusual looking PCBs.
context_section_description: TopoR can be used as an external autorouter for third-party layout editors or in conjunction with Eremex's own schematic capture and layout editor Delta Design (DD). TopoR imports input in Delta Design's FST format, as Specctra-/ELECTRA-compatible DSN design files, or in P-CAD PCB ASCII (2000, 2002, 2004), PADS PCB ASCII (3.5, 4.0, 5.0, 2005.0), or EAGLE BRD XML formats (6.x). The resulting boards can be exported into Specctra/ELECTRA SES session files, DXF, Gerber, P-CAD PCB ASCII (2000, 2002, 2004), PADS PCB ASCII (3.5, 4.0, 5.0, 2005.0).
  Routing of the wiring topology is done automatically and flexibly; angles are not limited to 90° and 45°.
  Efficient use of PCB space and absence of preferred routing directions in layers considerably reduces electromagnetic crosstalk.
  TopoR routes all connections, even if this entails violating design constraints. Such violations can be automatically corrected later.
  When objects (such as components and vias) are moved around, wire length and shape are optimized automatically with appropriate clearance.
  The user is free to choose from two ways to calculate the wire shape: with or without arcs. The first method involves wires consisting of lines only. The other makes wires keep appropriate clearance when circling around pads; it consists of arcs and lines.
  TopoR simultaneously optimizes several alternative variants of the layout. Variants with the worst parameters (per total wire length and number of vias) will be removed.
  TopoR has an automatic component placement feature. The procedure can be used both for all components of the board and only for components in a specific area. It is not comparable to the quality of the manual placement, but it can be used as a preparation step for manual placement.
  The minimum and desired clearances for each net can be specified.
  TopoR automatically supports trace necking, that is, it reduces the width of a wire that approaches a narrow pad (or one with a diameter that is less than the width of the wire), or when it passes through bottlenecks (for example, between the pads of a component).
  Wire-to-pad transitions use teardrop-style smoothing. The use of this procedure at the design stage helps avoid violations in design-rule checking when teardrops are added in the CAM editor.
  TopoR can recognize ball grid array (BGA) component areas and apply a special strategy for routing them. This helps reduce the number of vias, the density of connections, and in some cases the number of routing layers.
  A special algorithm is used for routing single-layer boards minimizing the number of interlayer junctions or to find a single-layer routing.
caption: Single-layer printed circuit board sample
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