page_title: VIA Nano
section_title: Architecture overview
hierarchical_section_title: VIA Nano / Architecture overview
caption_attribution_description: English: Photograph of the die of a VIA Isaiah, see also Floorplan (microelectronics).
context_page_description: The VIA Nano is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development by its CPU division, Centaur Technology. This new Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008, and launched on May 29, including low-voltage variants and the Nano brand name. The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.
context_section_description: Out-of-order and superscalar design: Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with same year offerings from AMD and Intel.
  Instructions fusion: Allows the processor to combine some instructions as a single instruction, reducing power requirements and giving higher performance (the Atom uses a similar strategy in processing x86 instructions in a more 'whole' manner, rather than breaking them into RISC-like micro-ops).
  Improved branch prediction: Uses eight predictors in two pipeline stages.
  CPU cache design: An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
  Data prefetch: Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
  Fetches 4 x86 instructions per cycle as opposed to Intel's 3-5
  Issues 3 micro-operations/clock to execution units
  Memory access: Merging of smaller stores into larger load data.
  Execution units: Seven execution units are available, that allows up to seven micro-ops being executed per clock.
  2 Integer units (ALU1 and ALU2)
  ALU1 is feature complete, while ALU2 lacks some low usage instructions and therefore is more suited for tasks like address calculations.
  2 Store units, one for Address Store and one for Data Store according to VIA.
  1 Load unit
  2 Media units (MEDIA-A and MEDIA-B) with a 128-bit wide datapath, supporting 4 single precision or 2 double-precision operations. Media computation refers to the use of the 2 Media units.
  MEDIA-A executes floating-point "add" instructions (2-clock latency for single-precision and double-precision), integer SIMD, encryption, divide and square root.
  MEDIA-B executes floating-point "multiply" instructions (2-clock latency for single-precision, 3-clock latency for double-precision).
  Because of the parallelism introduced with the 2 Media units, Media computation can provide four "add" and four "multiply" instructions per clock.
  A new implementation of FP-addition with the lowest clock-latency for a x86 processor so far.
  Almost all integer SIMD instructions execute in one clock.
  Implements MMX, SSE, SSE2, SSE3, SSSE3 multimedia instruction sets
  Implements SSE4.1 multimedia instruction set (VIA Nano 3000 series)
  Implements SSE4.1 multimedia instruction set (VIA Nano x2 series)
  Power Management: Besides requiring very low power, many new features are included.
  Includes a new C6 power state (Caches are flushed, internal state saved, and core voltage is turned off).
  Adaptive P-State Control: Transition between performance and voltage states without stopping execution.
  Adaptive Overclocking: Automatic overclocking if there is low temperature in the processor core.
  Adaptive Thermal Limit: Adjusting of the processor to maintain a user predefined temperature.
  Encryption: Includes the VIA PadLock engine
  Hardware support for AES encryption, secure hash algorithm SHA-1 and SHA-256 and Random Number Generation
  Around 2014/8/31 rumors appeared about a potential Isaiah II refresh.
caption: VIA Isaiah Architecture die floor-plan
exif: {"Image Orientation": "Horizontal (normal)", "Image XResolution": "300", "Image YResolution": "300", "Image ResolutionUnit": "Pixels/Inch", "Image Software": "Adobe Photoshop CS2 Windows", "Image DateTime": "2008:01:24 10:50:57", "Image ExifOffset": "164", "Thumbnail Compression": "JPEG (old-style)", "Thumbnail XResolution": "72", "Thumbnail YResolution": "72", "Thumbnail ResolutionUnit": "Pixels/Inch", "Thumbnail JPEGInterchangeFormat": "302", "Thumbnail JPEGInterchangeFormatLength": "12796", "EXIF ColorSpace": "sRGB", "EXIF ExifImageWidth": "809", "EXIF ExifImageLength": "803"}