page_title: OpenRISC
section_title: Implementations
hierarchical_section_title: OpenRISC / Implementations
caption_attribution_description: English: OpenRISC prototyped on a Flextronics FPGA dev board. It shows running uClinux. The image has been taken at Flextronics Ljubljana in 2002.
context_page_description: OpenRISC is a project to develop a series of open-source hardware based central processing units on established reduced instruction set computer principles. It includes an instruction set architecture using an open-source license. It is the original flagship project of the OpenCores community.
  The first architectural description is for the OpenRISC 1000, describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support, and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language.
  The hardware design was released under the GNU Lesser General Public License, while the models and firmware were released under the GNU General Public License.
  A reference system on a chip implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip. Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays, and there have been several commercial derivatives produced.
context_section_description: Most implementations are on field-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance.
  By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a crowdfunding project to build a cost-efficient application-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community. The project did not reach the goal.
  As of July 2020, no open-source ASIC had been produced.
caption: OpenRISC prototyped on Flextronics (Flex) FPGA dev board, running uClinux
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