page_title: Emitter-coupled logic
section_title: Implementation
hierarchical_section_title: Emitter-coupled logic / Implementation
caption_attribution_description: Emitter-coupled circuit (structure)
context_page_description: In electronics, emitter-coupled logic is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven BJT differential amplifier with single-ended input and limited emitter current to avoid the saturated region of operation and its slow turn-off behavior.
  As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic, current-mode logic
  or current-switch emitter-follower logic.
  In ECL, the transistors are never in saturation, the input/output voltages have a small swing, the input impedance is high and the output impedance is low. As a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. In addition, the essentially constant current draw of the differential amplifiers minimises delays and glitches due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.
  ECL's major disadvantage is that each gate continuously draws current, which means that it requires significantly more power than those of other logic families, especially when quiescent.
context_section_description: ECL is based on an emitter-coupled (long-tailed) pair, shaded red in the figure on the right. The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed  by a reference voltage source, shaded light green: the voltage divider with a diode thermal compensation (R1, R2, D1 and D2) and sometimes a buffering emitter follower (not shown on the picture); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor RE acts nearly as a current source. The output voltages at the collector load resistors RC1 and RC3 are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors RE4 and RE5 do not exist in all versions of ECL. In some cases 50 Ω line termination resistors connected between the bases of the input transistors and −2 V act as emitter resistors.
caption: The picture represents a typical ECL circuit diagram based on Motorola's MECL. In this schematic, transistor T5′ represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and Y. Additional pictures illustrate the circuit operation by visualizing the voltage relief and current topology at low input voltage (logical "0"), during the transition and at high input voltage (logical "1").
exif: {}