page_title: IBM 1401
section_title: Architecture
hierarchical_section_title: IBM 1401 / Architecture
caption_attribution_description: Operators Control Panel on a restored IBM 1401 computer at the Computer History Museum in Mountain View, CA. Photo by Michael Holley, November 2007. Taken with a Canon PowerShot A630 (1/13 second and F/2.8) with existing light.
context_page_description: The IBM 1401 is a variable-wordlength decimal computer that was announced by IBM on October 5, 1959. The first member of the highly successful IBM 1400 series, it was aimed at replacing unit record equipment for processing data stored on punched cards and at providing peripheral services for larger computers. The 1401 is considered to be the Model-T Ford of the computer industry, because it was mass-produced and because of its sales volume. Over 12,000 units were produced and many were leased or resold after they were replaced with newer technology. The 1401 was withdrawn on February 8, 1971.
context_section_description: Each alphanumeric character in the 1401 was encoded by six bits, called B,A,8,4,2,1.  The B,A bits were called zone bits and the 8,4,2,1 bits were called numeric bits, terms taken from the IBM 80 column punched card.
  For digits 1 through 9, the bits B,A were zero, the digit BCD encoded in bits 8,4,2,1.  Digit 0 was encoded 8,2.
  For alphabetic characters the setting of bits was derived from the zone and digit punches of the IBM 80 column punched card character code: B,A from 12, B from 11, and A from 0; the setting of bits 8,4,2,1 from BCD encoding of the 1 through 9 punches. Thus the letter A, 12,1 in the punched card character code, was encoded B,A,1.
  Encodings of punched card characters with two or more digit punches can be found in the Character and op codes table.
  IBM called the 1401's character code BCD, even though that term describes only the decimal digit encoding.  The 1401's alphanumeric collating sequence was compatible with the punched card collating sequence.
  Associated with each memory location were two other bits, called C for odd parity check and M for word mark.
  Each memory location then, had the following bits:
  C B A 8 4 2 1 M
  The 1401 was available in six memory configurations: 1400, 2000, 4000, 8000, 12000, or 16000 characters. Each character was addressable, addresses ranging from 0 through 15999. A very small number of 1401s were expanded to 32,000 characters by special request.
  Some operations used specific memory locations (those locations were not reserved and could be used for other purposes).  Read a card stored the 80 columns of data from a card into memory locations 001-080.  Index registers 1, 2 and 3 were in memory locations 087-089, 092-094 and 097-099 respectively. Punch a card punched the contents of memory locations 101-180 into a card. Write a line printed the contents of memory locations 201-332.
  The 1401's instruction format was
    Opcode
     with   [A-or-I-or-unit-address [B-address]] [modifier]
   word mark
  Opcodes were one character.  Memory addresses ("I" a branch target, "A" and "B" data) and unit address were three characters.  The opcode modifier was one character.  Instruction length was then 1, 2, 4, 5, 7, or 8 characters.  Most instructions had to be followed by a word mark (a requirement commonly met by the word mark with the opcode of the next instruction).
  See Character and op codes for a list of operations.
  A three-character memory address in an instruction was an encoding of a five-digit memory address.  The three low-order digits of the five-digit address, 000 to 999, were specified by the numeric bits of the three characters.  The zone bits of the high-order character specified an increment as follows: A 1000, B 2000, B and A together 3000, giving an addressability of 4,000 memory locations.  The zone bits of the low-order character specified increments of 4000, 8000, or 12000, to address 16,000 memory locations (with an IBM 1406 Storage Unit).  For example, the three-character address "I99" was a reference to memory location 3000 + 999, or 3999.
  The zone bits of the middle character of a three-character memory address could specify one of three index registers, one of many optional features.
  Operands referenced by the A-address and B-address were: a single memory location, a variable-length field, or a variable-length record.  Variable-length fields were addressed at their low-order (highest-addressed) position, their length defined by a word mark set at their high-order (lowest-addressed) position. When an operation such as addition was performed, the processor began at the low-order position of the two fields and worked its way to the high-order, just as a person would when adding with pencil and paper.
  The only limit on the length of such fields was the available memory.  Instructions applicable to variable-length fields included: Add, Subtract, Multiply, Divide, Compare, Move Characters to A or B Word Mark, Move Characters and Edit.  One or more adjacent variable-length fields could make up a variable-length record.  A variable-length record was addressed at its hig
caption: 1401 Console and, below, the Auxiliary Console.
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