Document:

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                                                                   EXHIBIT 10.13

*CERTAIN INFORMATION WITHIN THIS EXHIBIT HAS BEEN OMITTED AND THE NON-PUBLIC
INFORMATION HAS BEEN FILED SEPARATELY WITH THE SEC. CONFIDENTIAL TREATMENT HAS
BEEN REQUESTED WITH RESPECT TO THE OMITTED PORTIONS.

                       DEVELOPMENT AND LICENSING AGREEMENT

This agreement ("Agreement") is entered into and effective as of March 3, 1999
("Effective Date") by and between Taiwan Semiconductor Manufacturing Co., Ltd.,
a company duly incorporated under the laws of the Republic of China ("ROC"),
having its principal place of business at No. 121, Park Avenue 3, Science Based
Industrial Park, Hsin-Chu, Taiwan, ROC ("TSMC"), and VIRAGE LOGIC, Corp.,
("VIRAGE"), a company duly incorporated under the laws of Delaware, USA, having
its principal place of business at 46824 Lakeview Blvd., Fremont, California
94538 USA.

WHEREAS, VIRAGE has the expertise in developing capability in designing
sub-micron memory bit cells, memory compilers, and other silicon intellectual
property; and

WHEREAS, TSMC desires to have VIRAGE license to TSMC and TSMC's customers an
existing and/or future development of sub-micron memory bit cells and memory
compilers, including, but not limited to, based on TSMC 0.25um and 0.18um
technologies (the "Library") for TSMC's manufacturing services, and to have
VIRAGE extend the Library to its customers;

WHEREAS, Parties desire to jointly determine the manufacturability of
TSMC's Bit Cells ("TBC");

This Agreement shall serve to:

        (i)     confirm certain agreements that TSMC and VIRAGE have reached
                over the past several months regarding certain elements of the
                TSMC library Program. The TSMC Library Program shall mean the
                design, maintenance, sales, distribution and support by VIRAGE
                of certain library cells (the "Licensed Product"). TSMC Cells
                are defined as certain library cells contained in the Licensed
                Product, including but not limited to Exhibits A & B, which are
                solely owned by TSMC as listed in Exhibit D. The Licensed
                Library contains the Licensed Products and TSMC Cells ("Licensed
                Library").

        (ii)    identify a) the legally binding terms which are as provided
                below in this Agreement; and b) certain non-binding and open
                issues relating to the TSMC Library Program (as listed in the
                Exhibit F), and the parties agree to work together in good faith
                to find mutually satisfactory resolutions to open issues
                identified herein.

NOW, THEREFORE, the parties hereto agree as follows:

I.      DEVELOPMENT AND DELIVERY OF THE LIBRARY EXTENSIONS

1.1     VIRAGE agrees to use good faith and reasonable efforts to develop for
        TSMC the Library according to specifications as provided in Exhibit B
        ("Specifications") of this document. VIRAGE agrees to use good faith and
        reasonable efforts to provide to TSMC the set of deliverables outlined
        in Exhibit A and Exhibit B Specifications ("Deliverables"). The scope of
        this Agreement shall include 0.25um and 0.18um
<PAGE>   2
        technologies, which may be extended to future technologies by mutual
        agreement in writing.

1.2     VIRAGE agrees to use good faith and reasonable efforts to provide the
        set of Deliverables according to the schedule and milestones as provided
        in the Exhibit C ("Schedule"). Both TSMC and VIRAGE shall conduct
        engineering reviews to track the progress on a weekly basis. For every
        milestone set forth in Exhibit C, VIRAGE commits to allocate resources
        to meet the Schedule.

1.3     TSMC agrees to use good faith and reasonable efforts to provide early
        access to the technical information, including Design Rules and SPICE
        Models to VIRAGE for the purpose of developing the Library. TSMC will
        also provide when available, the DRC command file for the given process,
        if appropriate, to VIRAGE for verification of design rule
        interpretations. VIRAGE understands that there may be potential changes
        to information provided, and TSMC agrees to use good faith and
        reasonable efforts to keep VIRAGE continuously updated on the most
        current version of information. Provided, however, that both parties
        understand that the scope of such changes may result in VIRAGE being
        unable to meet the Schedule.

1.4     Library Deliverables will be an integration of (but not limited to)
        TSMC-specific memory compilers using the single-port TSMC-supplied bit
        cells (only after VIRAGE has reviewed the TSMC bit cell and finds it
        technically superior to VIRAGE's bit cells from an electrical and layout
        standpoint), and TSMC-specific memory compilers for dual-port, two-port
        and ROM compilers which contain bit cells developed by VIRAGE. Library
        Deliverables shall also pass TSMC's design rule check (DRC) procedure.
        TSMC will consider VIRAGE's suggestions with respect to design rule
        modifications and interpretations.

1.5     VIRAGE and TSMC shall hold joint periodic technical discussions in order
        to improve the probability that TSMC-specific library versions are
        industry-competitive. The objectives and schedules of such technical
        discussions are set forth in Exhibit G.

1.6     Parties shall mutually agree on an auditable quality assurance ("QA")
        procedure to ascertain that VIRAGE's deliverables meet the Specification
        prior to the delivery of the Library Products. VIRAGE agrees to perform
        the QA Procedure on the Library Deliverables and promptly provide the
        results to TSMC for its review. TSMC will review the Library
        Deliverables, then provide authorization for customer release. Both
        Parties agree to make the QA Procedure and results thereof available to
        either party's potential customers promptly upon request.

1.7     The Schedule shall be appropriately and equitably extended to account
        for any delays resulting from changes due to either party, and the
        non-changing party shall have no liability as a result of Schedule
        change.

II.     MODIFICATION AND REVISION

2.1     VIRAGE shall revise the Library at its own expense and at no charge to
        TSMC in the event that TSMC makes changes (not limited to) to design
        rules and process parameters

                                      -2-
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        which TSMC at its discretion deems significant. The adjusted VIRAGE
        Deliverables shall be shipped to TSMC after QA verification, upon a
        mutually agreed-upon schedule as set forth in Exhibit G.

2.2     VIRAGE shall revise the design kits in the Library at its own expense in
        the event of design tool revisions and changes which are deemed
        significant but customer demand and/or after technical review as set
        forth in Exhibit G and agreed to by VIRAGE and TSMC. The adjusted VIRAGE
        Deliverables shall be shipped to TSMC after VIRAGE's QA verification,
        upon a mutually agreed Schedule.

2.3     VIRAGE shall have no right to modify, alter or improve any cell in TSMC
        Cells and TSMC shall remain the sole owner to all rights to such TSMC
        Cells. TSMC grants VIRAGE the non-exclusive, non-transferable,
        worldwide, royalty-free right and license to reproduce, and distribute
        TSMC Cells, under the terms set forth in Section 5.1, for the term of
        this Agreement, solely for the purpose of evaluation and for the design,
        place-and-route and tape-out of integrated circuits to be manufactured
        at TSMC owned or controlled manufacturing facilities. Such distribution
        of TSMC Cells by VIRAGE shall be consistent with the manner in which
        VIRAGE distributes the Licensed Products under TSMC Library Program
        (e.g., provided under the same License Agreements, etc.). TSMC will use
        good faith and reasonable efforts and reasonable efforts to correct any
        bugs as necessary to have VIRAGE meet its Support Agreement(s).

III.    OWNERSHIP AND LICENSE

3.1     As between the parties, VIRAGE exclusively shall have all right, title
        and interest [including all patent rights, copyrights, trade secret
        rights, mask work rights and other rights throughout the world
        (collectively "Intellectual Property Rights")] in any inventions,
        intellectual property, trademarks, works-of-authorship, mask works,
        ideas or information made or conceived or reduced to practice by VIRAGE
        or by VIRAGE jointly with TSMC and/or other third parties in the course
        of development of memory bit cells, memory compilers, excepting only
        those TSMC Cells listed in Exhibit D, or others as listed in Exhibit B
        under this Agreement.

3.2     As between the parties, TSMC exclusively shall have all right, title and
        interest [including all patent rights, copyrights, trade secret rights,
        mask work rights and other rights throughout the world (collectively
        "Intellectual Property Rights")] in any inventions, works-of-authorship,
        processes, mask works, ideas or information made or conceived or reduced
        to practice by TSMC or by TSMC jointly with third parties in the course
        of development of those specifically identified library cells as listed
        in Exhibit D, including but not limited to the TSMC single port memory
        bit cells under this Agreement. Exhibit D shall be modified from time to
        time upon mutual agreement between parties.

IV.     CONSIDERATION

4.1     In consideration of the 0.18um Licensed Products developed herein, TSMC
        shall pay to VIRAGE             ****
        which shall be net of

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        any taxes and withholdings, excepting only any taxes due on VIRAGE's
        income, and where the payment terms are as follows:

                                      ****

4.2     TSMC shall also pay to VIRAGE a Pay-for-Performance compensation rate as
        specified herein. Pay-for-Performance compensation payments will be
        strictly limited based on the wafers shipped and accepted through TSMC
        that contain third party libraries from vendors participating in the
        TSMC Library Program where these libraries conform to the specifications
        identified by TSMC as part of this Agreement. TSMC shall not pay any
        Pay-for-Performance compensation for either engineering lots or any test
        chip wafers.

4.3     Parties understand and agree that TSMC is in the process of evaluating
        Pay-for-Performance compensation methods such as area-based
        partitioning. This evaluation may alter the
        Pay-for-Performance/compensation methods stated herein. Notwithstanding
        the above, both Parties agree that the method of Pay-for-Performance
        compensation payments will be as determined below:

        A)     1/N x applicable percentage, where N = number of third party
               library supplies identified on one tape-out.

        B)     Area-based partitioning model where the percentage of the
               Pay-for-Performance compensation is based directly upon the
               percent of the core die are occupied by the Library.

4.4     Pay-for-Performance Table. Parties agree that the total TSMC
        Pay-for-Performance percentage compensation is based upon accounts
        receivables of wafers ordered through TSMC that contains third party
        libraries from vendors participating in the TSMC Library Program where
        these libraries conform to the specifications identified by TSMC as part
        of this Agreement. VIRAGE shall receive compensation for TSMC for TSMC
        cells that contain the Library Program. Pay-for-Performance compensation
        percentage rates are applicable to Licensed Library products which are
        TSMC-specific libraries for both 0.25um and 0.18um technologies.

        Pay-for-Performance TABLE for 0.25um technology:

<TABLE>
<CAPTION>
        Year               1998     1999     2000     2001     2002    2003     2004     2005
        ----               ----     ----     ----     ----     ----    ----     ----     ----
<S>                        <C>      <C>      <C>      <C>      <C>     <C>      <C>      <C>
        Compensation        **       **       **       **       **      **       **       **
</TABLE>

                                      -4-
<PAGE>   5
        Pay-for-Performance TABLE for 0.18um technology:

<TABLE>
<CAPTION>
        Year               1998     1999     2000     2001     2002    2003     2004     2005
        ----               ----     ----     ----     ----     ----    ----     ----     ----
<S>                        <C>      <C>      <C>      <C>     <C>      <C>      <C>      <C>
        Compensation        **       **       **       **       **      **       **       **
</TABLE>

4.5     TSMC shall be obligated to pay royalties as stated herein to VIRAGE for
        any TSMC customer design that is: (a) designated at time of production
        release to TSMC to TSMC's customer as containing VIRAGE's Library
        Products that have been so licensed under TSMC's Library Program, and
        (b) where such designs are manufactured by TSMC. In the event that a
        customer designates to TSMC that multiple Licensed Products vendors
        contributed to the design, the royalties shall be distributed among
        these multiple Licensed Products vendors as stated in Section 4.3

4.6     TSMC agrees to use good faith and reasonable efforts to require that
        customers declare all designs as either "containing such Licensed
        Products" or "NOT contained such Licensed Products." TSMC's sole
        liability shall be limited to recording its customers' assertions
        regarding such Licensed Products. Notwithstanding the above, if any of
        TSMC's customers notifies TSMC of errors or omissions discovered, TSMC
        shall pay VIRAGE the owed applicable royalties as stated under the terms
        of this Agreement.

4.7     TSMC and VIRAGE shall work together to develop an auditing system to
        verify the Pay-for-Performance compensation structure without violating
        the confidentiality of TSMC's and VIRAGE's customers.

V.      DISTRIBUTION OF THE LIBRARY

5.1     During the terms of this Agreement, VIRAGE shall have non-exclusive and
        non-transferable rights to reproduce and distribute the Licensed Library
        to third party entities ("Licensed Library Recipients") without any
        payment of royalties or other fees to TSMC. VIRAGE agrees that Tm bit
        cells may only be shipped with memory compilers developed specifically
        for the TSMC bit cell and shall not be distributed by themselves.

5.2     VIRAGE agrees to sign "License Agreements" with the Licensed Library
        Recipients' use of the Licensed Library. VIRAGE understands and agrees
        to inform Licensed Library Recipients in the License Agreements that the
        relationship between TSMC and the Licensed Library Recipients will be
        purely for foundry services provided by TSMC, and the Licensed Library
        Recipients must enter into a separate agreement with TSMC to obtain
        foundry services from TSMC.

5.3     TSMC and VIRAGE shall use their best efforts to reach a mutual agreement
        on the forms of the License Agreements immediately upon signing of this
        Agreement. VIRAGE shall have the right to make changes from time to time
        to the License Agreements so long as any such changes do not materially
        alter (1) the terms and conditions provided in the mutually agreed
        version of the License Agreements approved by TSMC, and (2) the basic
        license restriction that the Licensed Library Recipients may use the
        Licensed Library

                                      -5-
<PAGE>   6
        only for evaluation and for the design, place-and-route and tape-out of
        integrated circuits to be manufactured solely at TSMC or its designated
        manufacturing facilities.

5.4     Parties agree that VIRAGE may make changes to the License Agreements on
        a case-by-case basis for particular Licensed Library Recipients that do
        materially alter the terms and conditions set forth; provided that
        TSMC's consent has been obtained in writing (Email with appropriate
        acknowledgment and facsimile will be acceptable forms of writing for
        such consents).

5.5     VIRAGE shall be responsible for providing Licensed Library Recipients
        the support for the Licensed Library distributed by VIRAGE. VIRAGE shall
        be free to set all terms and conditions for support, maintenance,
        engineering and customization services provided by VIRAGE to any
        Licensed Library Recipients with no accounting to TSMC of any such fees.

5.6     TSMC shall have the right to distribute the Licensed Library for TSMC or
        its designated subcontractors' internal designs, including ASIC's;
        provided that TSMC shall execute a standard VIRAGE License Agreement as
        described in this Agreement. If required, support for TSMC's internal
        ASIC use of the Licensed Library can be purchased at VIRAGE's standard
        fees.

5.7     Upon written request by TSMC, VIRAGE will license and distribute the
        Licensed Library to (a) other third party design service providers
        creating designs that will be manufactured solely at TSMC or TSMC
        designated facilities; (b) distribute as necessary to Licensed Products
        developers; or (c) distribute to fulfill TSMC's current contractual
        obligations and to facilitate future contractual obligations. The terms
        of these aforementioned licenses will be mutually agreeable to TSMC,
        VIRAGE and the third party on a case-by-case basis.

5.8     Both VIRAGE and TSMC shall actively promote the Library to customers of
        both parties ("Customers") using VIRAGE as the distributor. All Library
        licensees will be granted a license for unlimited and/or limited use of
        the Licensed Library and Deliverables solely for tape-out to TSMC.

5.9     VIRAGE shall provide TSMC a monthly update of all Licensed Library
        Recipients who receive Front-End Views and/or Back-End Views. VIRAGE
        shall not directly or knowingly indirectly make available the Licensed
        Library to any company on the list provided in Exhibit E without first
        obtaining TSMC's consent in writing (Email and facsimile will be
        acceptable forms of writing for such consents).

5.10    Both parties will jointly hold quarterly meetings to review performance
        as a participant in the TSMC Library Program beginning from the
        Effective Date. The Parties will assign liaison representatives at both
        corporate and regional levels.

5.11    TSMC, as the sponsor of the TSMC Library Program, agrees to use good
        faith and reasonable efforts to manage the program for the useful life
        of the 0l25 and 0.18 processes in the Licensed Libraries. VIRAGE will
        incur large, uncompensated, up-front costs, and possible loss of
        short-term business that can only be recovered through the

                                      -6-
<PAGE>   7
        aforementioned long-term Pay-for-Performance payments. If, due to
        changes in the business environment or other reasons, TSMC chooses to
        alter the terms of this Agreement, then TSMC agrees to use good faith
        and reasonable efforts to give VIRAGE at least one year's notice before
        any of the terms in Section IV of this Agreement can be altered so that
        VIRAGE can renegotiate its agreements with Customers. Notwithstanding
        the above, the one-year notice period will be waived due to any
        unforeseen circumstances to TSMC.

VI.     TERMS AND TERMINATION

6.1     This Agreement shall have an initial term of five (5) years from the
        Effective Date, and shall automatically be renewed for successive one
        (1) year terms, unless either Party gives sixty (60) days' written
        notice of cancellation to the other Party prior to the expiration of the
        term (including the initial term) then in effect.

6.2     This Agreement may be terminated early by either Party if the other
        Party (1) breaches any material provision of this Agreement and does not
        cure or remedy such breach within thirty (30) days after receipt of the
        written notice of the breach from the other Party; (2) becomes the
        subject of a voluntary or involuntary petition in bankruptcy or any
        proceeding relating to insolvency, receivership, liquidation, or
        composition for the benefits of creditors if such petition or proceeding
        is not dismissed with prejudice within sixty (60) days after filing.
        Termination of this Agreement shall be effective thirty (30) days after
        issuance of a written notice of termination to the other Party by the
        non-defaulting party.

6.3     Either Party without any cause may also terminate this Agreement early
        by giving a ninety (90) day written notice to the other Party prior to
        the desired termination date.

6.4     Termination of this Agreement for any reason shall not affect (1) the
        obligations accruing prior to the effective date of termination; and (2)
        any obligations under Sections 3, 4, 7, 8, 9, 10 and current customer
        engagements hereof, all of which shall survive termination or expiration
        of this Agreement.

6.5     Upon the effective date of termination, VIRAGE shall cease to use and
        shall either destroy or return to TSMC all of the TBC documentation and
        data in VIRAGE's possession or under VIRAGE's control. Any related
        documentation and copies thereof, in whole or in part, in all forms of
        media, together with VIRAGE's written certification by a duly authorized
        officer, that the TBC documentation and data stored in any kind of forms
        in VIRAGE's possession or under VIRAGE's control, and all related
        documentation and all copies thereof in whole or in part are no longer
        in use and have been returned to TSMC or destroyed.

                                      -7-
<PAGE>   8
6.6     Termination of this Agreement under this Section shall be in addition
        to, and not a waiver of, any remedy at law or in equity available to
        either Party arising from the other Party's breach of this Agreement.

VII.    DISCLAIMER OF WARRANTEE

7.1     Limited Warranty. VIRAGE warrants for a period of twelve (12) months
        from delivery of the Licensed Library to TSMC that such Licensed
        Library, as delivered, will be free from defects in the media and will
        substantially conform to the Specifications. In the event of
        nonconformance of the Licensed Library, TSMC shall promptly notify
        VIRAGE and provide VIRAGE with all available information in written or
        electronic form so that VIRAGE can reproduce the Error. VIRAGE's sole
        obligation is to undertake reasonable commercial efforts to correct the
        Errors reported to VIRAGE in writing, or in electronic form during the
        warranty period. VIRAGE'S SOLE LIABILITY AND LICENSEE'S EXCLUSIVE REMEDY
        WITH RESPECT TO BREACH OF THE FOREGOING LIMITED WARRANTY WILL BE LIMITED
        TO ERROR CORRECTION AND PRODUCT REPLACEMENT, OR IF NEITHER IS IN
        VIRAGE'S OPINION COMMERCIAL FEASIBLE, REFUND OF THE NRE DEVELOPMENT FEE
        AND PAY-FOR-PERFORMANCE COMPENSATION PAYMENTS RECEIVED BY VIRAGE BY
        TSMC.

7.2     DISCLAIMER. EXCEPT FOR THE ABOVE EXPRESS LIMITED WARRANTY, THE LICENSED
        LIBRARY, KNOW-HOW, AND DOCUMENTATION ARE LICENSED "AS IS," AND VIRAGE
        MAKES NO OTHER WARRANTIES EXPRESS, IMPLIED, OR STATUTORY OR OTHERWISE
        REGARDING THE LICENSED PRODUCT, DESIGN TECHNIQUES OR DOCUMENTATION.
        VIRAGE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY
        AND FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF
        DEALING OR USAGE OF TRADE.

VIII.   LIMITATIONS OF LIABILITY

8.1     Direct Damages. VIRAGE'S TOTAL LIABILITY FOR DIRECT DAMAGES UNDER THIS
        AGREEMENT SHALL NOT EXCEED THE NRE DEVELOPMENT FEE AND
        PAY-FOR-PERFORMANCE COMPENSATION PAYMENTS RECEIVED BY VIRAGE FROM TSMC.
        TSMC'S TOTAL LIABILITY FOR DIRECT DAMAGES UNDER THIS AGREEMENT SHALL NOT
        EXCEED $50,000 AS STATED IN THIS AGREEMENT.

8.2     Consequential Damages. EXCEPT AS PROVIDED IN SECTION 7 ABOVE, UNDER NO
        CIRCUMSTANCES, SHALL EITHER PARTY BE LIABLE FOR ANY SPECIAL, INCIDENTAL
        OR CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THIS AGREEMENT OR IN
        THE USE OF THE LICENSED PRODUCT, DESIGN TECHNIQUES AND DOCUMENTATION,
        HOWEVER CAUSES (WHETHER ARISING UNDER A THEORY OF CONTRACT, TORT
        (INCLUDING NEGLIGENCE); OR OTHERWISE); INCLUDING, WITHOUT LIMITATION,
        DAMAGES FOR LOST PROFITS, LOSS OF DATA, OR COSTS OF

                                      -8-
<PAGE>   9
        PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES. THE LIMITATIONS ON EITHER
        PARTY'S LIABILITY SET FORTH IN THIS SECTION VIII SHALL APPLY,
        NOTWITHSTANDING THE FAILURE OF ESSENTIAL PURPOSE OF ANY OF THE LIMITED
        REMEDIES SET FORTH IN SECTION 8.1 ABOVE.

IX.     PROPRIETARY INFORMATION

9.1     Both Parties agree to maintain Property Information in confidence, not
        to make use thereof other than for the performance of this Agreement, to
        release it only to employees who have a reasonable need to know the
        same, and to release or disclose it to any third parties, without prior
        written consent of the disclosing Party. Each Party hereto shall provide
        proper and secured storage for papers, return the original and all
        copies of tangible Proprietary Information.

9.2     All Proprietary Information and any copies thereof remain the property
        of the disclosing Party, and no license or other rights is granted or
        implied hereby. The receiving Party shall, upon the disclosing Party's
        request, return the original and all copies of tangible Proprietary
        information.

9.3     This Section shall survive the termination or expiration of this
        Agreement for a period of three (3) years.

X.      PATENT AND COPYRIGHT INFRINGEMENT

10.1    TSMC represents that TSMC Cells are and will be developed by TSMC or its
        subcontractors and such TSMC Cells shall not infringe upon or
        misappropriate the patents, mask work rights, copyrights, trade secrets
        or other proprietary rights of other intellectual property of third
        parties and that it has the right and authority to convey the TSMC Cells
        as set forth herein.

10.2    TSMC shall, at its own expense, indemnify, hold harmless, and defend or
        at its option, settle any claim, suit or proceeding brought by a third
        party against VIRAGE for infringement of any third party's proprietary
        rights or other intellectual property right issued in the United States,
        Taiwan, Japan or the European Union, by virtue of VIRAGE's authorized
        use, reproduction, distribution and sublicensing of any of the TSMC
        Cells pursuant to the terms of this Agreement and shall pay any
        settlement amounts or damages finally awarded in such claim, suit or
        proceeding; provided that VIRAGE: (a) promptly notifies TSMC in writing
        of such claim, suit or proceeding; (b) gives TSMC sole control over the
        defense and/or settlement of such claim, suit or proceeding; and (c)
        fully cooperates and provides all available information, assistance and
        authority to defend or settle the claim, suit or proceeding. TSMC shall
        not be liable for any costs, expenses, damages or fees incurred by
        VIRAGE in defending such action or claim unless authorized in advance in
        writing by TSMC.

10.3    Any action to be brought to prevent or enjoin any third party from
        infringement of any patent, copyright or other proprietary rights of
        TSMC with respect to TSMC Cells shall be brought exclusively by TSMC or
        TSMC's designee, in TSMC's sole discretion and as between TSMC and
        VIRAGE, at TSMC's sole cost and expense.

                                      -9-
<PAGE>   10
10.4    If the TSMC Cells are, or in TSMC's opinion are likely to become the
        subject of a claim, suit or proceeding alleging infringement, TSMC will
        use good faith and reasonable efforts: (a) to procure at not cost to
        VIRAGE, the right to continue using, reproducing, distributing and
        sublicensing the TSMC Cells; (b) to replace or modify the TSMC Cells, at
        not cost to VIRAGE, to make them non-infringing, provided that
        substantially the same function is performed by the replacement of
        modified TSMC Cells; or (c) if the right to continue using, reproducing,
        distributing and sublicensing the TSMC Cells cannot be reasonably
        procured for VIRAGE or the TSMC Cells cannot be replaced or modified to
        make them non-infringing, terminate the license of such TSMC Cells
        hereunder; provided that TSMC's indemnity obligations shall continue
        indefinitely as to all use, reproduction, distribution and sublicensing
        of the TSMC Cells prior to such termination.

10.5    The foregoing states TSMC's sole obligations and entire liability with
        respect to any claim infringement of the TSMC Cells of any intellectual
        property or other rights of any third party.

10.6    VIRAGE warrants and represents that the Library will be developed by
        VIRAGE or appropriate subcontractors and that as such the Library shall
        not infringe upon or misappropriate the patents, mask work rights,
        copyrights, trade secrets, or other proprietary rights of other
        intellectual property of third parties and that it has the right and
        authority to convey the Library as set forth herein.

10.7    VIRAGE shall, at its own expense, indemnify, hold harmless, and defend
        at its option, settle any claim, suit or proceeding brought by a third
        party against TSMC for infringement of any third party's proprietary
        rights or other intellectual property including but not limited to any
        claim based upon a patent, copyright or other intellectual property
        right issued in the United States, Taiwan, Japan or the European Union,
        by virtue of TSMC's authorized use, reproduction, distribution and
        sublicensing of any of the Library pursuant to the terms of this
        Agreement and shall pay any settlement amounts or damages finally
        awarded in such claim, suit or proceeding; provided that TSMC: (a)
        promptly notifies VIRAGE in writing of such claim, suit or proceeding;
        (b) gives VIRAGE sole control over the defense and/or settlement of such
        claim, suit or proceeding; and ( ) reasonably cooperates and provides
        all available information, assistance and authority to defend or settle
        the claim, suit or proceeding. VIRAGE shall not be liable for any costs,
        expenses, damages or fees incurred by TSMC in defending such action or
        claim unless authorized in advance in writing by VIRAGE.

10.8    Any action to be brought to prevent or enjoin any third party from
        infringement of any patent, copyright or other proprietary rights of
        VIRAGE with respect to the Library shall be brought exclusively by
        VIRAGE or VIRAGE's designee, in VIRAGE's sole discretion and as between
        VIRAGE and TSMC, at VIRAGE's sole cost and expense.

10.9    If the Library, or in VIRAGE's opinion is likely to become the subject
        of a claim, suit or proceeding alleging infringement, VIRAGE will use
        good faith and reasonable efforts: (a) to procure at not cost to TSMC,
        the right to continue using, reproducing, distributing and sublicensing
        the Library; (b) to replace or modify the Library, at no cost to TSMC,
        to

                                      -10-
<PAGE>   11
        make them non-infringing, provided that substantially the same function
        is performed by the replacement of modified the Library, or (c) if the
        right to continue using, reproducing, distributing and sublicensing the
        VIRAGE Cells cannot be reasonably procured for TSMC or the Library
        cannot be replaced or modified to make them non-infringing, terminate
        the license of such VIRAGE products hereunder; provided that VIRAGE's
        indemnity obligations shall continue indefinitely as to all use,
        reproduction, distribution and sublicensing of the Library prior to such
        termination.

10.10   The foregoing states VIRAGE's sole obligations and entire liability with
        respect to any claim infringement of the Library of any intellectual
        property or other rights of any third party.

XI.     GENERAL TERMS

11.1    Choice of Law. This Agreement shall be governed by and construed in
        accordance with the laws of the State of California. In the event of any
        dispute arising out of or in connection with this Agreement which cannot
        be amicably settled by the Parties hereto, the Parties agree to submit
        any such dispute to binding arbitration in accordance with the Rules of
        American Arbitration Association. All information relating to or
        disclosed by either Party in connection with the arbitration shall be
        treated by the Parties as confidential information and no disclosure of
        such information shall be made by either Party without prior written
        consent of the other party.

11.2    Export Controls. Both Parties agree and certify that neither the
        Licensed Library, not any other technical data received from VIRAGE, nor
        the direct product thereof, will be exported or reexported outside the
        United States except as authorized and as permitted by the laws and
        regulations of the United States.

11.3    Assignment. This Agreement may not be assigned by either Party without
        the prior written consent from the other party.

11.4    Audit. TSMC shall keep full and accurate books and records pertaining to
        TSMC's performance under this Agreement for a period of at least one (1)
        year after the date a given quarterly payment is made by TSMC to VIRAGE.
        TSMC shall permit a mutually appointed third party, on behalf of VIRAGE,
        to examine such books and records, at VIRAGE's sole cost and expense,
        upon reasonable prior written notice during normal working hours, but
        not later than one (1) year following the payment in question, for the
        sole purpose of verifying the compensation payments and reports and
        accountings related thereto. Prompt adjustments shall be made to
        compensate for any errors or omissions disclosed by such examination. In
        the event such examination shows underreporting and underpayments in
        excess of five percent (5%) for any twelve (12) month period ending
        three (3) months prior to the date of such examination, then TSMC shall
        pay VIRAGE the reasonable costs of any such examination as well as the
        unpaid compensation payments.

11.5    Notices. Any notice, report, approval or consent required or permitted
        hereunder shall be in writing (allowing 5 days for mailing) and will be
        deemed to have been duly given if

                                      -11-
<PAGE>   12
        delivered personally, by facsimile, or mailed by first-class, registered
        or certified mail, postage prepaid to the respective addresses of the
        Parties as set forth in this Agreement. If to VIRAGE, Attention:
        Corporate Controller. If to TSMC: Attention: Corporate Counsel.

        George Rassam: CFO
        Telephone:     510-360-8020
        gra@virlog.com

11.6    No Waiver. Failure by either party to enforce any provision of this
        Agreement will not be deemed a waiver of future endorsement of that or
        any other provision.

11.7    Independent Contractors. The relationship of VIRAGE and Licensee
        established by this Agreement is that of independent contractors, and
        nothing contained in this Agreement shall be construed (i) to give
        either party the power to direct or control the day-to-day activities of
        the other or (ii) to constitute the Parties as partners, joint
        venturers, co-owners or otherwise as participants in a joint or common
        undertaking.

11.8    Severability. If for any reason a court of competent jurisdiction finds
        any provision of this Agreement, or portion thereof, to be
        unenforceable, that provision of the Agreement will be enforced to the
        maximum extent permissible so as to effect the intent of the Parties,
        and the remainder of this Agreement will continue in full force and
        effect.

11.9    Attorneys' Fees. The prevailing party in any action to enforce this
        Agreement shall be entitled to recover the costs and expenses including,
        without limitation, reasonable attorneys' fees.

11.10   Injunctive Relief. The parties agree that a material breach of this
        Agreement adversely affecting both Parties' Intellectual Property Rights
        which would cause irreparable injury to the non-breaching Party for
        which monetary damages would not be an adequate remedy. Therefore, the
        Parties agree that the non-breaching Party shall be entitled to
        equitable relief in addition to any remedies it may have hereunder or at
        law.

11.11   Force Majeure. Except for the obligation to make payments hereunder,
        nonperformance of either Party shall be excused to the extent that
        performance is rendered impossible by strike, fire, flood, governmental
        action, failure of suppliers, earthquake, or any other reason where
        failure to perform is beyond the reasonable control of the nonperforming
        Party.

11.12   Entire Agreement. This Agreement, including all Supplements, constitutes
        the entire agreement between the Parties with respect to the subject
        matter hereof, and supersedes all prior agreements or representations,
        oral or written, regarding such subject matter. This Agreement may not
        be modified or amended except in writing, signed by a duly authorized
        representative of both parties.

                                      -12-
<PAGE>   13
IN WITNESS WHEREOF, the Parties hereto have caused this Agreement to be duly
executed in duplicate on their behalf by their duly authorized officers and
representatives on the date given above.

TAIWAN SEMICONDUCTOR MANUFACTURING         VIRAGE LOGIC CORPORATION
CO., LTD.

By: /s/ MAGNUS RYDE                         /s/ ADAM KABLANIAN
   ------------------------------          -------------------------------------

Magnus Ryde for Ron Norris                 Adam Kablanian
---------------------------------          -------------------------------------
(Print Name)                               (Print Name)

Sr. VP TSMC Ltd.                           President & CEO
---------------------------------          -------------------------------------
(Title)                                    (Title)

                                      -13-
<PAGE>   14
                  EXHIBIT A VIRAGE 0.18um DELIVERABLES TO TSMC

The contents of this Exhibit shall be modified from time to time as mutually
agreed to by both parties:

DEFINITION OF TSMC 0.18um DELIVERABLES:

Models and User Documentation ("Front-End Views"):

1.      Verilog Models with SDF Support

2.      VCS Models with SDF Support (in Stamp format)

3.      -VHDL (VITAL) Models with SDF Support

4.      Symbols for compose (RAM support not required)

5.      Symbols for Synopsys (RAM support not required)

6.      Symbols for EDIF 200 (RAM support not required)

7.      Schematic for special cell design (TSMC internal use only)
        **Schematics in composer format for TSMC core cell
        **Hard copy for memory compilers (models include core cell & memory
          compiler models)

8.      Motive Models with SDF Support

9.      Primetime Models with SDF Support

10.     IKOS models with SDF Support

11.     Ambit models

12.     Fastscan models

13.     Sunrise models

14.     Quickturn models

15.     Synopsys Synthesis Models (.lib file) - including power information for
        power design, wire-load model (options for customer to choose)
        constructed by place & route results.

16.     Cadence TLF 3.0 Models

17.     Star-RC timing models

18.     Star-DC timing models

19.     LEF/Abstracts for Silicon Ensemble/Cell3/Aquarius/Apollo

20.     Memory compiler abstract for Aquarius & Apollo:  manual and
        automated approach

21.     CLF models for Avanti

22.     Derating factors (including pin-to-pin delay time. Timing constraints:
        setup time, hold time, recovery time, min. pulse width).
        **Process derating factor when typical is set to 1
        **Temp. derating factor when 25 degrees V is set to 1
        **Voltage derating factor when VDD = 1.8V is set to 1

23.     Automatic Data Sheet Generator

24.     Customer Documentation*

*       Note that item 1, 3, 9, 15, 16, 19, 22, 23 are the standard
        deliverables, other items are delivered upon customer request

<PAGE>   15
Physical Views ("Back-End" Views):

1.      -GDSII

2.      Place & Route technology file for Silicon

Ensemble/Cell3/Aquarius/Apollo

        **Provide sample solution in deliverable (TSMC needs to review and run
          test case).

3.      -SPICE netlist for LVS

Note that Item 2 will be shipped as per customer request.

<PAGE>   16
                  EXHIBIT A: TSMC 0.18UM DELIVERABLES (cont'd)

CUSTOMER DOCUMENTATION

- Documentation Describing Characterization and Verification Methodology

*Note:   Customer Documentation includes:

1)      Standard Cell Databook (if provided by Virage) (including power route
        guide)

2)      Users Manual for Custom-Touch Memory Compilers which may include

        1.      Installation and usage instructions

        2.      Process Optimization for TSMC 0.18 process

        3.      Memory architecture

                Optimizing clock-to-wordline driver performance Optimizing
                wordline driver-to-sensing performance Optimizing
                sensing-to-output drive performance Optimizing sense
                amplifier recovery time Self-timing and duty-cycle
                independence

        4.      Memory Compiler

USER OPTIONS - .glb PARAMETERS

                Performance metrics
                Design specifications
                Run-time configuration
                Model views
                Functional description
                Timing diagrams
                Characterization conditions

        5.      Test Interface

                BIST
                Parallel test
                Scan test
                Serial test

<PAGE>   17
                        EXHIBIT B: VIRAGE LOGIC BIT CELLS

The contents of this Exhibit shall be modified from time to time as mutually
agreed to by both Parties:

        Please see 0.18um TSMC memory Compiler Data Sheet
        1)     Dual Port Bit Cell
        2)     ROM Bit Cell
        3)     Register File Bit Cell one and two ports
        4)     Virage Logic Bit Cell for Single port High Density

<PAGE>   18
                     EXHIBIT C: 0.25uM DELIVERABLE SCHEDULE

Exhibit C1

0.25um TSMC-Specific Library - PHASE I

<TABLE>
<CAPTION>
TSMC SPECIFICATIONS                           VERSION    DATE     DELIVERY      TSMC CONTROL #
-------------------------------------         -------  --------   --------     ---------------
<S>                                           <C>      <C>        <C>          <C>
Spice Models - TSMC 0.25uM LOGIC                1.7    8/7/98     8/24/98      TA-1099-6001
SALICIDE (1P5M, 2.5V, 2.5V/3.3V)

Design Rules - 0.25uM LOGIC SALICIDE            1.3    9/25/98    11/21/98     TA-1099-4003
2.5V/3.3V PROCESS DESIGN RULE

DRC runset - 0.25uM LOGIC SALICIDE              3      8/04/98    11/21/98     TA-1099-4003-D2
2.5V/3.3V DESIGN RULE COMMAND FILE

TSMC Single-Port Memory Bit Cell                1.0    11/04/98   12/17/98     TA-10A0-4101

Sizing Equation

Layer Mapping
</TABLE>

KEY MILESTONES (D1 + RELATIVE TIMES)

<TABLE>
<CAPTION>
                                                                          DELIVERY TIME
         REQ. ACTIVITY                         WHO                       (RELATIVE TO D1)
-------------------------------   -----------------------------   -------------------------------
<S>                               <C>                             <C>
Tech file 0.25um data including   TSMC                            Done
Dracula runset

Tech file calibration & sample    VIRAGE                          D1 + 2 weeks
set

Tech file review & sign-off       TSMC                            D1 + 4 weeks

Create synchronous single-port    VIRAGE                          Bitcell delivery + 16 weeks
memory compiler using TSMC
bit cell for large memories
</TABLE>

<PAGE>   19
                     EXHIBIT C: 0.18um DELIVERABLE SCHEDULE

Exhibit C2

0.18um TSMC Specific Library --- PHASE I

<TABLE>
<CAPTION>
TSMC SPECIFICATIONS                         VERSION     DATE     DELIVERY      TSMC CONTROL #
-------------------                         -------   --------   --------      --------------
<S>                                         <C>       <C>        <C>           <C>
Spice Models - TSMC 0.18uM LOGIC              1.1     11/06/98   11/16/98      TA-10A5-6001
SALICIDE (1.8V/3.3V)

Design Rules - 0.18uM LOGIC SALICIDE          1.1     11/05/98   11/16/98      TA-10A5-4001
1.8V/3.3V PROCESS DESIGN RULE

DRC runset - 0.18uM LOGIC SALICIDE            2       10/21/98   11/24/98      TA-10A5-4001-D1
1.8V/3.3V PROCESS DESIGN RULE COMMAND
FILE

TSMC Single-Port RAM Bit Cell                 0.1     10/09/98   12/17/98      TA-10A5-4101

Sizing Equation

Layer Mapping
</TABLE>

KEY MILESTONES (D2 + RELATIVE TIMES)

<TABLE>
<CAPTION>
                                                                          DELIVERY TIME
         REQ. ACTIVITY                         WHO                       (RELATIVE TO D1)
-------------------------------   -----------------------------   -------------------------------
<S>                               <C>                             <C>
Tech file 0.18um data including   TSMC                            Done
Dracula runset

Tech file calibration & sample    VIRAGE                          D2 + 2 weeks
set

Tech file review & sign-off       TSMC                            D2 + 4 weeks

Create synchronous single-port    VIRAGE                          Bitcell delivery + 18 weeks
memory compiler using TSMC or
Virage Logic bit cell for large
memories
</TABLE>

                                      -16-
<PAGE>   20
                              EXHIBIT D: TSMC CELLS

The contents of this Exhibit shall be modified from time to time as mutually
agreed to by both Parties:

<TABLE>
<CAPTION>
PART NUMBER                         DESCRIPTION
-----------                         -----------
<S>                                 <C>
0.18um                              4.6552um2 Single-Port SRAM bit cell
                                    (Borderless)

0.25um                              7.5 um2 Single-Port SRAM bit cell
                                    (Borderless)
                                    10.95 um2 Single-Port SRAM bit cell
                                    (Borderless)
</TABLE>

<PAGE>   21
                                    EXHIBIT E

List to be updated as appropriate. Companies on this list shall not receive
Licensed Library from VIRAGE unless first approved by TSMC:

****
<PAGE>   22
                             EXHIBIT F: OPEN ISSUES

1.      Review End-User License Agreement from VIRAGE, to review for TSMC
        related Terms and Conditions.

2.      1/N based Pay-for-Performance/compensation calculation model versus
        Area-based royalty/compensation calculation model decision.

<PAGE>   23
                   EXHIBIT G: TECHNICAL REVIEWS OR DISCUSSIONS

<PAGE>   24
                                    EXHIBIT H
                        CUSTOM TOUCH STAR MEMORY COMPILER

This Exhibit H to the Development and Licensing Agreement between TSMC and
VIRAGE, dated March 3, 1999 ("DLA") constitutes the agreement between TSMC and
VIRAGE for the development, distribution and sale of the Custom Touch STAR
Memory Compiler developed by VIRAGE. Except as modified herein, the DLA is
hereby ratified and confirmed and remains in full force and effect. In the event
of a conflict between the terms of this Exhibit H and the DLA, the terms of this
Exhibit shall govern.

I.      DEVELOPMENT DELIVERY OF THE CUSTOM TOUCH STAR COMPILER

1.1     VIRAGE agrees to develop for TSMC the Custom Touch STAR memory compiler
        as specified in Attachment Number One ("Specifications") to this
        Exhibit. VIRAGE agrees to provide to TSMC the set of deliverable
        ("Deliverables") outlined in the Attachment Number One to this Exhibit,
        and to provide these Deliverables according to the Schedule and
        milestones as provided in Attachment Number Two to this Exhibit
        ("Schedule"). The scope of this Agreement shall only include 0.18um
        technologies and may be extended to future technologies by mutual
        agreement in writing.

1.2     All terms of Section I of the DLA apply to the Deliverables of this
        Exhibit.

II.     MODIFICATION AND REVISION

        All terms of Section II of the DLA apply to the Deliverables of this
        Exhibit with the exception that the Schedule for the Custom Touch STAR
        Deliverables is provided in Attachment Number Two to this Exhibit.

III.    OWNERSHIP AND LICENSE

        All terms of Section III of the DLA apply to the Deliverables of this
        Exhibit.

IV.     CONSIDERATION

4.1     In consideration for the development of the 0.18um Custom Touch STAR
        memory compiler and Deliverables developed herein, TSMC shall pay to
        VIRAGE US$**** as a non-refundable, Non-Recurring Engineering (NRE)
        development fee, which shall include any taxes and withholdings,
        excepting only any taxes due on VIRAGE's income. If upon receipt of the
        final deliverable, the Custom Touch STAR Compiler is non-functional
        (meaning the inability to generate any memory instances)k, and the
        problems are unrecoverable, VIRAGE will credit Tm for the NRE paid. The
        credit will be applied to any new project development between VIRAGE and
        TSMC. If TSMC does not identify a project in which to apply the credit
        within one (1) year, the credit will be rolled over to VIRAGE as
        pre-paid royalty income. The payment terms are net 30 days upon receipt
        of invoice from VIRAGE, which will be generated upon notification of
        receipt from TSMC. TSMC shall be invoiced as follows:

<PAGE>   25

        ****

        TSMC shall pay to VIRAGE Pay-for-Performance compensation as specified
        in Sections 4.2 through 4l7 in the DLA. For those wafers that include a
        Custom Touch STARinstance, **% of the Pay-for-Performance royalty amount
        paid by TSMC to VIRAGE, to a maximum of $****, shall be kept in
        reserve, to be utilized in funding VIRAGE to perform subsequent
        technology developments for joint TSMC/VIRAGE memory products.
        Developments funded with these funds must be mutually agreed to between
        VIRAGE and TSMC, and must be in accordance with VIRAGE's published
        product/technology roadmap. TSMC shall not unreasonably withhold
        agreement to fund future developments in accordance with this section.
        If TSMC does not utilize the royalty pool to fund future developments
        within one (1) year of accumulating up to $**** in accordance with
        the terms of this section, then VIRAGE will rollover the accumulated
        funds and accept the $**** as royalty revenue. The one (1) year
        period may be extended in twelve (12) month increments if mutually
        agreed upon by both Parties.

4.2     VIRAGE will insert a paragraph in their Licensing Agreement, which when
        signed by VIRAGE's and TSMC's customer, will provide authorization for
        TSMC to release information that will assist VIRAGE in the collection of
        royalties from the Custom Touch STAR memory compiler customers. The
        authorization will allow TSMC to collect information on the usage of the
        resulting Custom Touch STAR memory compiler instances and provide that
        information to VIRAGE in order to assist in the collection of the
        royalties. The information that VIRAGE will obtain permission from
        Custom Touch STARcustomers for TSMC to collect and provide to VIRAGE
        shall include but not be limited to: (i) specific data on wafers where
        Custom Touch STAR instances are utilized, including customer name and
        tape-out information, number of wafers manufactured and price per wafer
        for that customer, and (ii) any other information deemed necessary to
        ensure VIRAGE can charge and collect royalties for the Custom Touch STAR
        instances.

        For any actual customers of the Custom Touch STAR memory compiler,
        VIRAGE shall mandate that these customers enter into appropriate
        Licensing Agreements with VIRAGE directly, whereby the customers shall
        pay to VIRAGE Licensing fees and/or Royalty fees. All distribution and
        licensing will occur between the Custom Touch STAR customer and VIRAGE
        unless authorized by VIRAGE to TSMC on a case-by-case basis. TSMC shall
        clearly communicate to their customers the proper engagement method with
        VIRAGE for obtaining said technology.

V.      SILICON VERIFICATION AND CUSTOM TOUCH STAR CUSTOMER DELIVERABLES

5.1     All deliverables listed in Attachment Number Two must be
        compliant with TSMC9000 specification.

                                      -2-
<PAGE>   26
5.2     VIRAGE and TSMC will work together to define and develop a manufacturing
        and yield analysis plan for redundancy & repair.

5.3     VIRAGE shall make available to their Custom Touch STAR
        customers the following deliverables:

               Front-end models
               GDSII files
               Custom Touch STAR specifications
               Custom Touch STAR application notes
               Test flow and test methodology
               Built-in self test (BIST) or diagnostic circuitry description
               BIST interface
               BIST Option for testability

5.4     After receiving VIRAGE's deliverables (Attachment number Two), TSMC
        will, free of any charges to VIRAGE, start the fabrication procedure by
        running test instances developed by VIRAGE, and produce the Prototype
        for VIRAGE. The number of lots and units supplied to VIRAGE by TSMC will
        be determined mutually with Deliverables and Schedule. VIRAGE agrees to
        start its own verification and qualification procedure on the Prototype
        produced by TSMC, and within 45 calendar days after receiving Prototype,
        VIRAGE shall provide a silicon verification report which shall include
        information as outlined in the TSMC9000 specification.

VI.     OTHER TERMS

6.1     All other terms in the DLA, including Sections 5, 6, 7, 8, 9, 10 and 11
        in their entirety, shall apply to the Custom Touch STAR memory compiler
        and Deliverables developed under this Exhibit unless specifically
        modified by this Exhibit.

6.2     The rights and obligations of the parties contained in section 9 of the
        DLA shall survive the termination or expiration of this Exhibit for a
        period of five (5) years.

6.3     All rights and obligations of the parties under this Exhibit shall not
        survive the expiration or termination of the DLA.

TAIWAN SEMICONDUCTOR MANUFACTURING           VIRAGE LOGIC CORPORATION
COMPANY, LTD.

/s/ MICHAEL M. PAWLIK                        /s/ ADAM KABLANIAN
------------------------------------------   -----------------------------------
NAME:  Michael M. Pawlik                     NAME:  Adam Kablanian
TITLE: Vice President, Corporate Marketing   TITLE:  President & CEO
DATE:                                        DATE:

                                      -3-<PAGE>   1
                                                                   EXHIBIT 10.14

*CERTAIN INFORMATION WITHIN THIS EXHIBIT HAS BEEN OMITTED AND THE NON-PUBLIC
INFORMATION HAS BEEN FILED SEPARATELY WITH THE SEC. CONFIDENTIAL TREATMENT HAS
BEEN REQUESTED WITH RESPECT TO THE OMITTED PORTIONS.

                JOINT MARKETING AND TECHNICAL SUPPORT AGREEMENT

This agreement is entered into and effective November 14, 1997, (the "Effective
Date") by and between VIRAGE LOGIC, with a place of business at 1641A South Main
Street Milpitas CA, 95025, USA ("VIRAGE LOGIC"), and Chartered Semiconductor
Manufacturing Ltd., with a place of business at 60 Woodlands Industrial Park D,
Street 2, Singapore 738406 ("CHARTERED").

Whereas, the parties hereto desire to work together to develop and promote
customer benefits of the joint use of CHARTERED foundry and VIRAGE LOGIC
products and services.

Whereas, the parties hereto desire to enter into a worldwide non-exclusive
agreement that defines the technical and marketing support that each party will
provide to the other in support of mutual customers and prospects.

BACKGROUND

VIRAGE LOGIC is a full service VLSI design and ASIC Company and a leader in
ultra low power and high performance integrated circuit design. VIRAGE LOGIC
provides design and test solution to ASIC and COT customers.

CHARTERED is a dedicated foundry providing quality manufacturing service for
semiconductor companies worldwide. CHARTERED business focus is in wafer
fabrication for implementing the customer designs in silicon.

This agreement serves to clarify the strong cooperative relationship between
VIRAGE LOGIC and CHARTERED to coordinate areas of mutual interest in the future
offering and promotion of libraries and foundry service for the benefit of
mutual customers.

1. JOINT MARKETING

It is the intention of both parties to provide the greatest value to mutual
customers through the delivery of compatible and complementary products and
services. Both parties agree to start cooperation in the area of compiler, BIST,
and SRAM, potentially EEPROM and Flash in the future. In order to achieve these
ends, both parties agree to work together in the following area:

1.1     Provide the other party and mutual customers with technical, marketing,
        and sales support.

1.2     Introduce its customers to the products of the other party, when
        appropriate.

1.3     Use each other's logos in marketing literature described in this
        Agreement and upon the prior written approval of the other party.

<PAGE>   2
1.4     Issue press releases on significant achievements of this relationship.
        All formal press releases must be approved by both VIRAGE LOGIC and
        CHARTERED before they are issued. Both parties may comment on this
        relationship to customers, third party and the press without prior
        approval by the other party.

1.5     Promote each other's services in the COT market place. CHARTERED would
        promote VIRAGE LOGIC libraries as having been manufactured at CHARTERED
        and VIRAGE LOGIC would promote CHARTERED as foundry manufacturer meeting
        VIRAGE LOGIC standard.

2.      JOINT TEST CHIP AND SILICON VERIFICATION PROGRAM

CHARTERED and VIRAGE LOGIC will share the costs of model extraction and spice to
silicon correlation using the CHARTERED test chip or the VIRAGE LOGIC test chip.
The CHARTERED test chip would include a BSIM extract module for DC analysis, and
a performance module for AC characterization.

2.1     CHARTERED will be responsible for providing CHARTERED's test chip layout
        and test plans to VIRAGE LOGIC. VIRAGE LOGIC is free to adapt CHARTERED
        test chip, or design a new test chip at VIRAGE LOGIC's expense that best
        meet VIRAGE LOGIC's needs in silicon verifications.

2.2     For each new process technology, VIRAGE LOGIC can take advantage of
        riding on CHARTERED's test chip for such technology provided that VIRAGE
        LOGIC is able to tape-out before CHARTERED's pre-determined cut-off
        date. In the event VIRAGE LOGIC is unable to tape out by such date,
        VIRAGE LOGIC shall be responsible for the costs of mask and CHARTERED
        shall provide the silicon. If VIRAGE LOGIC is able to tape out before
        such date, CHARTERED shall include VIRAGE LOGIC's test chip of a
        reasonable size on CHARTERED's test chip without incurring masks or
        silicon costs to VIRAGE LOGIC. VIRAGE LOGIC hereby acknowledges that
        CHARTERED may make available such test chip to CHARTERED's customers and
        technology partners upon their request.

2.3     VIRAGE LOGIC will be responsible for the engineering and test costs for
        model extraction, performance characterization, and Spice to silicon
        correlation. All resulting records, reports and data are shared between
        VIRAGE LOGIC and CHARTERED.

2.4     CHARTERED will be responsible for running internal CHARTERED process
        monitoring modules on as needed basis to assure that the CHARTERED
        process is meeting CHARTERED specifications. If there are material
        changes to the process that warrant new model extraction and/or silicon
        verification, then the above model extraction and correlation sequence
        will, if agreed by both parties, be repeated as described above.

                                       2
<PAGE>   3
3.      CHARTERED RESPONSIBILITIES

To ensure the highest probability of success for our mutual customers, CHARTERED
hereby accepts the following responsibilities:

3.1     CHARTERED will provide VIRAGE LOGIC with the most updated CHARTERED
        Design Rules, Spice Models, Parasitic Extraction tables, and Biasing
        tables for production processes on the same schedule that it provides
        for its best customers based on CHARTERED test chip. CHARTERED reserves
        the right to make changes as needed but will consider the ramifications
        to VIRAGE LOGIC of such a change. It will be VIRAGE LOGIC discretion to
        decide if a re-generation of model and/or silicon verification at VIRAGE
        LOGIC's expense, is needed.

3.2     CHARTERED will support VIRAGE LOGIC through designated technical
        contacts, usually CHARTERED account managers, to facilitate the orderly
        flow of customer design data for mask making and wafer manufacturing.

3.3     CHARTERED will equip its sales channel with standard approved VIRAGE
        LOGIC sales and marketing collateral for promoting VIRAGE LOGIC offers
        to mutual customers and prospects.

3.4     CHARTERED will develop a press release which outlines the basic terms of
        this agreement. Final approval of this press release will be with VIRAGE
        LOGIC.

3.5     CHARTERED will support VIRAGE LOGIC's customers in the same manner as
        CHARTERED supports its customers in similar locations.

4.      VIRAGE LOGIC RESPONSIBILITIES

To ensure the highest probability of success for our mutual customers, VIRAGE
LOGIC hereby accepts the following responsibilities:

4.1     VIRAGE LOGIC will develop physical and logical design libraries based on
        CHARTERED rules. Based on market demand, CHARTERED will advise and
        VIRAGE LOGIC will choose which libraries to build using these rules.
        VIRAGE LOGIC will make all reasonable efforts to keep these libraries
        current with the CHARTERED Design Rules, and support mutual customers
        with such libraries.

4.2     VIRAGE LOGIC will equip its sales channel with approved CHARTERED sales
        and marketing collateral for promoting CHARTERED offers to mutual
        customers and prospects.

                                       3
<PAGE>   4
5.      CONTACTS AND REVIEWS

5.1     Quarterly review meeting will be held at a mutually agreed time and
        venue between CHARTERED and VIRAGE LOGIC to address any concerns or
        issues affecting mutual customers, and to assess the effectiveness of
        the sales effort and co-operative relationship.

5.2     VIRAGE LOGIC and CHARTERED Contacts

               VIRAGE LOGIC                 CHARTERED

        Engineering   Alex Shubat           Dong Khong / Bob Kwong

        Sales         Adam Kablanian

        Marketing     Adam Kablanian        S.Y. Tan - Stahel

6.      TERMS OF AGREEMENT AND CONFIDENTIALITY

6.1     This agreement shall remain in force for a period of three years from
        the Effective Date.

6.2     Either party hereto may terminate this Agreement without cause or reason
        by 90 days prior written notice to the other party during the term of
        this Agreement provided that the terminating party will fully cooperate
        with the other party to enable the customers to complete the tasks that
        were started prior to termination.

6.3     Both parties hereto agree to treat all information, materials, and
        documents, except for characterization data, provided by the other party
        in accordance with Non-Disclosure Agreement executed separately by both
        parties.

7.      TRADEMARKS AND USE OF NAMES

7.1     The use of the name or products of the other party or indication of this
        Agreement in the marketing and/or publicity materials of either party
        shall be subject to written approval of the other party, and such
        approval should not be unreasonably withheld or delayed. The requirement
        of written approval shall not apply to accurate factual listings of
        products publicly offered or supported by either party.

8.      GENERAL PROVISIONS

8.1     Neither party may assign its rights or obligations, or assign or
        sublicense any licenses granted under this Agreement without the prior
        written consent of the other party.

                                       4
<PAGE>   5
8.2     Neither party is authorized to act for or on behalf of the other party
        under this Agreement. Each party is an independent contractor. No
        commitments to customers on VIRAGE LOGIC library pricing, availability,
        routed density, quality, or reliability may be made by CHARTERED. No
        commitments to customers on CHARTERED wafer pricing wafer capacity,
        delivery dates, quality, or yield may be made by VIRAGE LOGIC.

8.3     The validity, performance and construction of this Agreement shall be
        governed by the Laws of the State of California.

8.4     If either party is challenged by a third party to be infringing the
        intellectual property rights of such third party with respect to the
        material or documents jointly developed or consented to by both parties,
        then the other party shall provide all reasonable assistance to the
        challenged party in defending against those claims. Such reasonable
        assistance shall include providing relevant documents, materials, and
        consulting.

8.5     No failure or delay by either party to enforce or take advantage of any
        provision or right under this Agreement shall constitute a subsequent
        waiver of that provision or right, nor shall it be deemed to be a waiver
        of any of the other terms and conditions of this Agreement.

8.6     In the event that any provision of this Agreement is prohibited by any
        law governing its construction, performance and enforcement, such
        provision shall be ineffective to the extent of such prohibition without
        invalidating thereby any of the remaining provisions of the Agreement.
        The captions of sections herein are intended for convenience only, and
        the same shall not be interpretive of the content of such section.

8.7     All notices and communications to be given under this Agreement shall be
        in writing and shall be deemed delivered upon hand delivery, upon
        acknowledged facsimile communication, or seven (7) days after deposit in
        the mail of the home country of the party, postage prepaid, by
        certified, registered or first class mail, addressed to the parties at
        the addresses set forth above.

9.      COPYRIGHT, PATENT, AND INDEMNITY

9.1     Indemnification by VIRAGE LOGIC

        VIRAGE LOGIC shall indemnify and defend (including attorney fees)
        CHARTERED and hold it harmless against any and all damages awarded by a
        court or payable in settlement (whether or not a legal proceeding is
        commenced) resulting from a claim against CHARTERED based upon an actual
        or alleged infringement of a third party's patent, mask work right,
        copyright trade secrets or other intellectual property right arising
        from CHARTERED's use of design

                                       5
<PAGE>   6
        modules, spice models, or testchips provided by VIRAGE LOGIC under this
        Agreement.

9.2     Indemnification by CHARTERED

        CHARTERED shall indemnify and defend (including attorney fees) VIRAGE
        LOGIC and hold it harmless against any and all damages awarded by a
        court or payable in settlement (whether or not a legal proceeding is
        commenced) resulting from a claim against VIRAGE LOGIC based upon an
        actual or alleged infringement of a third party's patent, mask work
        right, copyright, trade secrets or other intellectual property right
        arising from VIRAGE LOGIC's use of CHARTERED's design rules, Spice
        models, testchips, material, techniques, or process provided by
        CHARTERED under this Agreement.

9.3     Procedure

Neither party shall have any liability under this section 9 unless:

        (a)    the indemnifying party is promptly notified in writing of each
               notice and communication regarding such claim and given (at the
               indemnifying party's expense) the authority, information, and
               assistance necessary to present a defense; and

        (b)    The indemnifying party is offered sole control of the defense of
               such claim and of all negotiations for its settlement or
               compromise. The indemnified party may, at its expense,
               participate in the defense of such claim and in all negotiations
               for its settlement or compromise. If the indemnifying party does
               not assume control of the defense promptly after notice of the
               claim it shall be bound by the results obtained by the
               indemnified party with respect to such claim.

9.4     In no event shall either party's liability to each other arising out of
        sections 9.1 and 9.2, or out of any other provision in this Agreement
        exceed an aggregate of United States Dollars One Hundred Thousand
        (US$100,000).

9.5     Disclaimer

        THE FOREGOING STATES EACH PARTY'S ENTIRE LIABILITY AND OBLIGATION
        (EXPRESS, IMPLIED, STATUTORY OR OTHERWISE) WITH RESPECT TO INTELLECTUAL
        PROPERTY INFRINGEMENT OR CLAIMS THEREFOR REGARDING ANY OF THE
        INFORMATION EXCHANGED PURSUANT TO THIS AGREEMENT.

Acknowledged and agreed:

For VIRAGE LOGIC     /s/            For CHARTERED     /s/
                  -----------                    --------------

                                       6
<PAGE>   7
Title          President                    Title         SVP
               ---------------------                      ---

Date           10/27/97                     Date          11/4/97
               ---------------------                      -------

                                       7
<PAGE>   8
        ADDENDUM NO. 1 TO JOINT MARKETING AND TECHNICAL SUPPORT AGREEMENT

THIS ADDENDUM NO. 1, TOGETHER WITH EXHIBIT A is entered into and effective on
___________ 1999 (the "Effective Date") by and between Virage Logic Corporation
("Virage Logic"), a California corporation having its principal place of
business 46824 Lakeview Blvd., Fremont, CA 94538, USA and Chartered
Semiconductor Manufacturing Ltd. ("Chartered"), a Singapore company having, its
principal place of business at 60 Woodlands Industrial Park D, Street 2,
Singapore 738406, and is supplemental to a Joint Marketing and Technical Support
Agreement dated 4 November 1997 (the "Agreement").

WHEREAS:

In response to the market demand, the Parties have discussed and agreed to
revise the business model on which the Joint Marketing and Technical Support
Agreement was based. In accordance with those discussions, the Parties now
desire to incorporate the additional provisions to the Agreement.

IT IS AGREED AS FOLLOWS:

1. LIBRARIES

The terms of this Addendum No. 1 are only applicable to the following Virage
Logic Memory Compilers libraries that Virage Logic has developed for Chartered's
0.35um and 0.25um processes (the "Chartered/Virage Logic 0.35um/0.25um memory
compilers") pursuant to the Agreement:

-  0.35um PROCESS:

(i)     1 port High density compiler

-  0.25um PROCESS:

(i)     1 port High Density compiler (HD-Family)

(ii)    2 port High density compiler (HD-Family)

(iii)   1 port Register file

(iv)    2 port Register file

2. PRICING OPTION AND PAYMENTS

(a) Virage Logic agrees to grant twenty (20) compiler tokens to Chartered. The
compiler tokens may be exercised by Chartered to require Virage Logic to license
to Chartered customers any Chartered/Virage Logic 0.35um/0.25um memory compilers
on the payment by Chartered or customer of **% of Virage Logic's COT list prices
set out in Exhibit A together with Virage Logic's end-user maintenance fees
which shall not

<PAGE>   9
exceed 12% of the relevant list price per annum per site (all references to "$"
in this Addendum No. 1 shall mean United States dollars).

(b) In consideration of the receipt of the twenty (20) compiler tokens referred
to in Clause 2(a), Chartered agrees to pay the following royalties to Virage
Logic:

(i)     Subject to Clause 2(b)(vii) below, for each revenue bearing wafer
        manufactured at Chartered that incorporates any Chartered/Virage Logic
        0.35um/0.25um memory compilers ("Wafer"), Chartered shall pay to Virage
        Logic the following royalties, up to a maximum of **** per process ****
        Technology:

        (aa) **% of the Net Selling Price of each Wafer up to ****; and
             thereafter,

        (bb) **% of the Net Selling Price of each Wafer up to ****.

               In this Agreement, "Net Selling Price" shall mean the gross
               consideration (whether in cash or kind) received by Chartered
               from sales of Wafers less (i) normal and customary rebates, and
               cash and trade discounts actually taken, (ii) sales, use and/or
               other excise taxes or duties actually paid, (iii) the cost of any
               packages and packaging, (iv) insurance costs and outbound
               transportation charges prepaid or allowed, (v) import and/or
               export duties actually paid, and (vi) amounts allowed or credited
               due to returns. In addition, when a Wafer is sold in a packaged
               or tested form, the gross consideration (whether in cash or kind)
               received by Chartered for the purposes of calculating the Net
               Selling Price shall be less the costs of packaging and testing.

(ii)    The total amount of royalties that Chartered shall pay to Virage Logic
        pursuant to Clause 2(b)(i) above, over the life of the design using any
        Chartered/Virage Logic 0.35um/0.25um memory compiler shall be limited to
        **** per process technology and Chartered shall not be required to pay
        Virage Logic any royalties in excess of **** per process technology.

(iii)   Notwithstanding Clause 2(b)(i) above, in the event that a Wafer
        incorporates any libraries or other foundation IPs (i.e. Standard cells,
        I/0 and memories), of other vendors in addition to any Chartered/Virage
        Logic 0.35um/0.25um memory compilers. Virage Logic agrees that the
        percentages in Clause 2(b)(i)(aa) and 2(b)(i)(bb) above shall be reduced
        proportionately in accordance with the total number of vendors whose
        libraries and/or foundation IPs (i.e. standard cells, I/O and memories)
        are incorporated into the same wafer.

                                       2
<PAGE>   10
        By way of an example, if a Wafer incorporates any Chartered/Virage Logic
        0.35um/0.25um memory compiler and libraries or other foundation IPs
        (i.e. standard cells, I/O and memories), of two (2) other vendors, the
        percentages set out in Clauses 2(b)(i)(aa) and 2(b)(i)(bb) above shall
        each be reduced by two thirds.

(iv)    All royalty payments to be made by Chartered pursuant to Clause 2(b)(i)
        above shall be computed according to the actual amounts received by
        Chartered from customers as payment for the purchase of Wafers, and
        shall be paid by Chartered on a quarterly basis.

(v)     Payments to Virage Logic hereunder shall be made without deduction or
        withholding except that Chartered shall have the right to withhold from
        payments to Virage Logic any taxes that Chartered is required to
        withhold under any applicable law. Chartered shall provide Virage Logic
        with a certificate from the applicable tax authorities or other evidence
        reasonably required by Virage Logic to evidence such tax payment.

(vi)    Chartered shall keep for a period of two (2) years after each royalty
        payment hereunder records as may be necessary to determine and verify
        the royalty payments hereunder. Virage Logic is entitled at Virago
        Logic's cost to have such records of Chartered inspected by independent
        public accountant firms acceptable to Chartered, upon reasonable notice
        and not more than once a year.

(vii)   The foregoing provisions in Clauses 2(b)(i) to (vii) shall only apply to
        mutual customers' designs that incorporate the Chartered/Virage Logic
        0.35um/0.25um memory compilers that are taped-out to Chartered on or
        after the Effective Date.

(viii)  Virage Logic will make available the Chartered/Virage Logic
        0.35um/0.25um memory compilers and Chartered/Virage Logic 0.35um/0.25um
        Instances (and all Virage Logic's standard EDA views) by licensing the
        same directly to customers.

(ix)    Thc merging of physical libraries for customers using the libraries will
        be done by customers. Chartered, or Chartered appointed design houses
        (Rights to access subject to business terms agreed herein, but without
        rights to sub-license).

3.      TERM AND TERMINATION

(a)     This Addendum No. 1 shall remain in force for a period of three (3)
        years from the Effective Date.

(b)     Notwithstanding the foregoing, this Addendum No. 1 shall terminate if
        the Agreement is terminated, or either party terminates this Addendum
        No. 1, without cause or reason, by 90 days' written notice of
        termination to the other party. However, notwithstanding the termination
        of this Addendum, Chartered shall

                                       3
<PAGE>   11
        continue to pay royalties under the terms of this Addendum in respect of
        Wafers manufactured and sold to customers that have licensed the
        Chartered/Virage Logic 0.35um/0.25um memory compilers during the term of
        this Addendum No. 1.

(c)     The termination of this Addendum however caused shall be without
        prejudice to any obligations or rights of either party which have
        accrued prior to such termination and shall not affect any provision of
        this Addendum which is expressly or by implication provided to come into
        effect on or to continue in affect after such termination.

4.      SAVING AND INCORPORATION

(a)     Clause 6.1 of the Agreement is hereby deleted and substituted with the
        following provision:

        "6.1 This Agreement shall remain in force for a period of three (3)
        years from the Effective Date of this Addendum No. 1".

(b)     Save as expressly varied by the terms of this Addendum No. 1, the terms
        and conditions of the Agreement shall remain with full force and effect
        in all other respects.

(c)     The Agreement and this Addendum No. 1 shall be construed as one document
        and this Addendum No. 1 shall be deemed to be part of the Agreement.

5.      GOVERNING LAW

The validity, enforceability and construction of this Addendum No. 1 shall be
governed by the Laws of the State of California.

IN WITNESS WHEREOF the parties have entered into this Addendum No. 1 as of the
date first above written:

VIRAGE LOGIC                                CHARTERED SEMICONDUCTOR
                                            MANUFACTURING LTD.

/s/ ALEX SHUBAT                             /s/  ROB BAXTER
  ----------------------------------          ----------------------------------

Name: Alex Shubat for Adam Kablanian        Name: Rob Baxter

Title: President & CEO                      Title: Senior Vice President,
                                            Business Operations

                                       4
<PAGE>   12
                                    EXHIBIT A

LIST PRICES FOR CHARTERED/VIRAGE 0.35um/0.25um MEMORY COMPILERS AS OF 31 MARCH
1999 (REF. CLOSE 2)

(All references to $ shall mean United States Dollars)

-      0.35um PROCESS:

        (i)    1 port High density compiler:       ****

-      0.25um PROCESS:

        (i)    1 port High Density compiler:       ****
        (ii)   2 port High density compiler:       ****
        (iii)  1 port Register file:               ****
        (iv)   2 port Register file:               ****

For the purpose of this Addendum No. 1. compilers will be offered regardless of
whether the customer needs one instance or the complete compiler.

Acknowledged and agreed by:

VIRAGE LOGIC:                       CHARTERED:

/s/ ALEX SHUBAT                     /s/   ROB BAXTER
   -------------------------           --------------------------------
<PAGE>   13
            ADDENDUM NO. 2 TO JOINT MARKETING AND TECHNICAL SUPPORT
                                   AGREEMENT

THIS ADDENDUM NO. 2 is entered into and effective on ___________ 1999 (the
"Effective Date") by and between Virage Logic Corporation ("Virage Logic"), a
California corporation having its principal place of business at 46824 Lakeview
Blvd. Fremont, CA 94538, USA and Chartered Semiconductor Manufacturing Ltd
("Chartered"), a Singapore company having its principal place of business at 60
Woodlands Industrial Park D, Street 2, Singapore 738406, and is supplemental to
a Joint Marketing and Technical Support Agreement dated 4 November 1997 (the
"Agreement").

WHEREAS:-

In response to the market demand, Virage Logic and Chartered have entered into
Addendum No. 1 to the Agreement dated [   ] and have further agreed to extend
their cooperation as set out in the Agreement to the development of 0.18um
memory compliers, including but not limited to SRAMs. In connection with this
further agreement, the Parties have agreed to modify and supplement the
provisions of the Agreement.

IT IS AGREED AS FOLLOWS:-

1. CHARTERED RESPONSIBILITIES

To ensure that highest probability of success for mutual customers of Chartered
and Virage Logic, Chartered hereby accepts the following responsibilities:

1.1  In connection with the marketing of Virage Logic's products and services
to mutual and prospective customers, Chartered will promote Virage Logic as a
premier SRAM provider.

1.2  To support the development of the 0.18um memory compliers by Virage Logic,
Chartered agrees to pay a development fee of United States Dollars One Hundred
Thousand (US$100,000/-). The fee shall be paid as follows:

(a)  ****-to be paid within 30 days from the Effective Date
(b)  ****-to be paid within 30 days of first test chip tape out.

1.3  In addition to the development fee referred to in Section 1.2 of this
Addendum No. 2, Chartered agrees to pay Virage Logic royalties for the use of
any Chartered/Virage Logic 0.18um memory complier by mutual customers, on the
following terms and conditions:

(a)  Royalties will be based on **% of the Net Selling Price of each
revenue-bearing Wafer manufactured by Chartered that incorporates a
Chartered/Virage Logic memory complier.

                                       1

<PAGE>   14
In this Addendum, "Net Selling Price" shall mean the gross consideration
(whether in cash or kind) received by Chartered from sales of Wafers less (i)
normal and customary rebates, and cash and trade discounts actually taken, (ii)
sales, use and/or other excise taxes or duties actually paid, (iii) the cost of
any packages and packaging, (iv) insurance costs and outbound transportation
charges prepaid or allowed, (v) import and/or export duties actually paid, and
(vi) amounts allowed or credited due to returns. In addition, when a Wafer is
sold in a packaged or tested form, the gross consideration (whether in cash or
kind) received by Chartered for the purposes of calculating the Net Selling
Price shall be less the costs of packaging and testing.

(b)  Notwithstanding 1.3(a) above, in the event that a Wafer incorporates any
libraries or other foundation IP's; i.e., standard cells, I/O's and memories of
other vendors, in addition to any Chartered/Virage Logic 0.18um memory
compilers, Virage Logic agrees that the percentages in Section 1.3(a) above
shall be reduced proportionately in accordance with the total number of vendors
whose libraries and/or IPs are incorporated into the same wafer.

By way of an example, if a Wafer incorporates any Chartered/Virage Logic 0.18um
memory compiler and libraries or other foundation IPs of two (2) other vendors,
the percentages set out in Section 1.3(a) above shall each be reduced by two
thirds.

(c)  All royalties to be paid by Chartered pursuant to Section 1.3(a) above
shall be computed according to the actual amounts received by Chartered from
mutual customers as payment for the purchase of Wafers, and shall be paid by
Chartered on a quarterly basis.

(d)  Payments to Virage Logic hereunder shall be made without deduction or
withholding, except that Chartered shall have the right to withhold from
payments to Virage Logic any taxes that Chartered is required to withhold under
any applicable law. Chartered shall provide Virage Logic with a certificate
from the applicable tax authorities or other evidence reasonably required by
Virage Logic to evidence such tax payment.

2. VIRAGE LOGIC RESPONSIBILITIES

To ensure that highest probability of success for mutual customers of Chartered
and Virage Logic, Virage Logic hereby accepts the following responsibilities:

2.1  Virage Logic will develop and deliver all 0.18um memory compilers to
Chartered. In order to facilitate the tapeout of the test chip, Virage will
deliver a test chip with the memory compilers below to Chartered for silicon
validation by 30 September 1999.

(a)  Single Port Synchronous memory compiler
(b)  Dual Port Synchronous memory compiler

                                       2

<PAGE>   15
3.  Term and Termination

(a) This Addendum No. 2 shall remain in force for a period of three (3) years
from the Effective Date.

(b) Notwithstanding the foregoing, this Addendum No. 2 shall terminate if the
Agreement is terminated or expired and not renewed, or either party terminates
this Addendum No. 2, without cause or reason, by 90 days' notice of termination
to the other party.

4.  Saving and Incorporation

(a) Section 6.1 of the Agreement is hereby deleted and substituted with the
following provision:

    "6.1 This Agreement shall remain in force for a period of three (3) years
         from the Effective Date of Addendum No. 2 to this Agreement."

(b) Save as expressly varied by the terms of this Addendum No. 2, the terms and
conditions of the Agreement shall remain with full force and effect in all
other respects.

(c) The Agreement, Addendum No. 1 to the Agreement and this Addendum No. 2
shall be construed as one document and this Addendum No. 2 shall be deemed to
be part of the Agreement.

5.  Governing Law

The validity, enforceability and construction of this Addendum No. 2 shall be
governed by the Laws of the State of California.

IN WITNESS WHEREOF the parties have entered into this Addendum No. 2 as of the
date first above written:

VIRAGE LOGIC                               CHARTERED SEMICONDUCTOR
                                           MANUFACTURING LTD.

/s/ ADAM KABLANIAN                         /s/ ROB BAXTER
-----------------------------------       -------------------------------------

NAME: Adam Kablanian                      NAME: Rob Baxter

TITLE: President & CEO                    TITLE: Senior Vice President,Business
                                                 Operations

DATE:                                     DATE:

                                       3
<PAGE>   16
        ADDENDUM NO. 3 TO JOINT MARKETING AND TECHNICAL SUPPORT AGREEMENT

THIS ADDENDUM NO. 3 is entered into and effective on June 7 1999 by and between
Virage Logic Corporation ("Virage Logic"), a California corporation having its
principal place of business at 46824 Lakeview Blvd. Fremont, CA 94538, USA and
Chartered Semiconductor Manufacturing Ltd ("Chartered"), a Singapore company
having its principal place of business at 60 Woodlands Industrial Park D, Street
2, Singapore 738406, and is supplemental to a Joint Marketing and Technical
Support Agreement dated 4 November 1997 (the "Agreement") and an Addendum No. 2
to the Agreement dated 12 April 1999 (the "Addendum No. 2").

WHEREAS:-

In response to the market demand, Virage Logic and Chartered had entered into
Addendum No. 2 to modify and supplement the provisions of the Agreement. The
parties now desire to amend the term and termination provisions of Addendum No.
2 on the following terms and conditions.

IT IS AGREED AS FOLLOWS:-

1. Clause 3 of Addendum No. 2 is deleted in its entirety and replaced with the
following provision:

"3. Term and Termination

3.1 Unless otherwise terminated by the parties in accordance with Clause 3.2
hereof, this Addendum No. 2 shall remain in force for a period of three (3)
years from the Effective Date. However, notwithstanding the termination of this
Addendum No. 2, Chartered shall continue to pay royalties under the terms of
this Addendum in respect of wafers manufactured and sold to customers that have
licensed the Chartered/Virage Logic 0.18um memory compilers during the term of
this Addendum No. 2.

3.2 Notwithstanding the foregoing, this Addendum No. 2 shall terminate

        (a)    by the agreement of the Parties in writing;

        (b)    forthwith by either Party if the other commits any material
               breach of any term of this Addendum No. 2 or the Agreement and
               which in the case of a breach capable of being remedied shall not
               have been remedied within thirty (30) days of a written request
               to remedy the same.

        (c)    at the option of either Party, in any of the following events:

<PAGE>   17
               (i)    the inability of the other Party to pay its debts in the
                      normal course of business; or

               (ii)   the other Party ceasing or threatening to cease wholly or
                      substantially to carry on its business, otherwise than for
                      the purpose of a reconstruction or amalgamation without
                      insolvency; or

               (iii)  any encumbrancer taking possession of or a receiver,
                      trustee or judicial manager being appointed over the whole
                      or any substantial part of the undertaking, property or
                      assets of the other Party; or

               (iv)   the making of an order by a court of competent
                      jurisdiction or the passing of a resolution for the
                      winding-up of the other Party or any company controlling
                      the other Party, otherwise than for the purpose of a
                      reconstruction or amalgamation without insolvency.

3.3 The termination of this Addendum No. 2 pursuant to this Clause 3.2 shall
take effect immediately upon the issue of a written notice to that effect by the
Party terminating the Addendum to the other. The termination of this Addendum
No. 2 however caused shall be without prejudice to any obligations or rights of
either Party which have accrued prior to such termination and shall not affect
any provision of this Addendum No. 2 and/or any provision of the Agreement which
is expressly or by implication provided to come into effect on or to continue in
effect after such termination."

2. Term and Termination

This Addendum No. 3 shall terminate at the same time that Addendum No. 2 is
terminated or has expired and is not renewed.

3. Saving and Incorporation

(a)     Save as expressly varied by the terms of this Addendum No. 3, the
        provisions of Addendum No. 2 shall remain with full force and effect in
        all other respects.

(b)     The Agreement, Addendum No. 1 to the Agreement, Addendum No. 2 to the
        Agreement and this Addendum No. 3 shall be construed as one document and
        this Addendum No. 3 shall be deemed to be a part of the Agreement.

4.      Governing Law

The validity, enforceability and construction of this Addendum No. 3 shall be
governed by the Laws of the State of California.

                                       2
<PAGE>   18
IN WITNESS WHEREOF the parties have entered into this Addendum No. 3 as of the
date first above written:

VIRAGE LOGIC                           CHARTERED SEMICONDUCTOR
                                       MANUFACTURING LTD.

/s/  ALEX SHUBAT                         /s/  ROB BAXTER
   ------------------------------        ---------------------------------
Name:    Alex Shubat                   Name: Rob Baxter

Title: VP Engineering, CTO             Title: Senior Vice President,
                                       Business Operations

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