迷你浮點數

迷你浮點（minifloats）是用少位元浮點數值。不太適合通用數值計算。通常用於特殊目的，像電腦圖形學，迭代很小並且精度具有美學效果。機器學習也使用類似格式，如bfloat16。 Minifloats按照IEEE 754標準設計。必須遵守次正規數和正規數之間邊界規則（未明確寫入的），且具無限大和 NaN 特殊模式。標準化數字以有偏差的指數儲存。該標準的新修訂版 IEEE 754-2008 具有 16 位元二進位小型浮點數。 迷你浮點通常使用四個數字的元組（S、E、M、B）來描述： S是符號欄位的長度。通常為 0 或 1。 E是指數欄位的長度。 M是尾數（有效數字）欄位的長度。 B是指數偏差。 因此，以 (S, E, M, B) 表示的小型浮點格式為 S + E + M 位元。 (S, E, M, B) 表示法可以轉換為 (B, P, L, U) 格式，如 (2, M + 1, B + 1, 2 S − B) (IEEE指數）。 具有1個符號位元、4個指數位元和3個有效位元對於大多數值指數x是2x−7。所有IEEE 754原則都應該有效。 0 0000 000 = 0 1 0000 000 = −0 有效數用0.擴展： 0 0000 001 = 0.0012 × 21 - 7 = 0.125 × 2-6 = 0.001953125 (最小次正規數) ... 0 0000 111 = 0.1112 × 21 - 7 = 0.875 × 2-6 = 0.013671875 (最大次正規數) 有效數用1.擴展： 0 0001 000 = 1.0002 × 21 - 7 = 1 × 2-6 = 0.015625 (least normalized number) 0 0001 001 = 1.0012 × 21 - 7 = 1.125 × 2-6 = 0.017578125 ... 0 0111 000 = 1.0002 × 27 - 7 = 1 × 20 = 1 0 0111 001 = 1.0012 × 27 - 7 = 1.125 × 20 = 1.125 (最小值大於 1) ... 0 1110 000 = 1.0002 × 214 - 7 = 1.000 × 27 = 128 0 1110 001 = 1.0012 × 214 - 7 = 1.125 × 27 = 144 ... 0 1110 110 = 1.1102 × 214 - 7 = 1.750 × 27 = 224 0 1110 111 = 1.1112 × 214 - 7 = 1.875 × 27 = 240 (最大標準數) 0 1111 000 = +∞ 1 1111 000 = −∞ s 1111 mmm = NaN (if mmm ≠ 000) 這是此範例 8 位元浮點的所有可能值的圖表。 只有 242 個不同的非 NaN 值（如果 +0 和 -0 視為不同），因為 14 個位元模式代表 NaN。 可以使用腳本為 SEMB 值的任意組合產生如上所述的表格Python 或GDScript. 在這些小尺寸下，其它偏差值可能會很有趣，例如 -2 的偏差將使數字 0-16 具有與整數 0-16 相同的位表示形式，但會導致無法表示非整數值。 0 0000 000 = 0.0002 × 21 - (-2) = 0.0 × 23 = 0 (subnormal number) 0 0000 001 = 0.0012 × 21 - (-2) = 0.125 × 23 = 1 (subnormal number) 0 0000 111 = 0.1112 × 21 - (-2) = 0.875 × 23 = 7 (subnormal number) 0 0001 000 = 1.0002 × 21 - (-2) = 1.000 × 23 = 8 (normalized number) 0 0001 111 = 1.1112 × 21 - (-2) = 1.875 × 23 = 15 (normalized number) 0 0010 000 = 1.0002 × 22 - (-2) = 1.000 × 24 = 16 (normalized number) 此圖示範了增加較小的 (1.3.2.3)-6 位元迷你浮點。 此浮點系統完全遵循IEEE 754規則。 NaN作為運算元始終產生NaN結果。 ∞−∞和 (−∞) +∞會產生 NaN（綠）。∞可以按有限值增減而不會發生變化。 有限操作數的和可以給出無限結果（即 14.0 + 3.0 = +∞，因為結果是青，-∞紅）。 算術運算可以類似地說明： 減法 乘法 除法 已隱藏部分未翻譯内容，歡迎參與翻譯。 The Radeon R300 and R420 GPUs used an "fp24" floating-point format with 7 bits of exponent and 16 bits (+1 implicit) of mantissa. "Full Precision" in Direct3D 9.0 is a proprietary 24-bit floating-point format. Microsoft's D3D9 (Shader Model 2.0) graphics API initially supported both FP24 (as in ATI's R300 chip) and FP32 (as in Nvidia's NV30 chip) as "Full Precision", as well as FP16 as "Partial Precision" for vertex and pixel shader calculations performed by the graphics hardware. Khronos defines 10-bit and 11-bit float formats for use with Vulkan. Both formats have no sign bit and a 5-bit exponent. The 10-bit format has a 5-bit mantissa, and the 11-bit format has a 6-bit mantissa. The smallest possible float size that follows all IEEE principles, including normalized numbers, subnormal numbers, signed zero, signed infinity, and multiple NaN values, is a 4-bit float with 1-bit sign, 2-bit exponent, and 1-bit mantissa. In the table below, the columns have different values for the sign and mantissa bits, and the rows are different values for the exponent bits. If normalized numbers are not required, the size can be reduced to 3-bit by reducing the exponent down to 1. In situations where the sign bit can be excluded, each of the above examples can be reduced by 1 bit further, keeping only the left half of the above tables. A 2-bit float with 1-bit exponent and 1-bit mantissa would only have 0, 1, Inf, NaN values. If the mantissa is allowed to be 0-bit, a 1-bit float format would have a 1-bit exponent, and the only two values would be 0 and Inf. The exponent must be at least 1 bit or else it no longer makes sense as a float (it would just be a signed number). Minifloats are also commonly used in embedded devices,[來源請求] especially on microcontrollers where floating-point will need to be emulated in software. To speed up the computation, the mantissa typically occupies exactly half of the bits, so the register boundary automatically addresses the parts without shifting. 定點數運算 半精度浮点数 G.711 A-Law Mocerino, Luca; Calimera, Andrea. AxP: A HW-SW Co-Design Pipeline for Energy-Efficient Approximated ConvNets via Associative Matching. Applied Sciences. 24 November 2021, 11 (23): 11164. doi:10.3390/app112311164 .  IEEE half-precision has 5 exponent bits with bias 15 ( 2 5 − 1 − 1 = 15 {\displaystyle 2^{5-1}-1=15} ), IEEE single-precision has 8 exponent bits with bias 127 ( 2 8 − 1 − 1 = 127 {\displaystyle 2^{8-1}-1=127} ), IEEE double-precision has 11 exponent bits with bias 1023 ( 2 11 − 1 − 1 = 1023 {\displaystyle 2^{11-1}-1=1023} ), and IEEE quadruple-precision has 15 exponent bits with bias 16383 ( 2 15 − 1 − 1 = 16383 {\displaystyle 2^{15-1}-1=16383} ). See the Exponent bias article for more detail. O'Hallaron, David R.; Bryant, Randal E. Computer systems: a programmer's perspective 2. Boston, Massachusetts, USA: Prentice Hall. 2010. ISBN 978-0-13-610804-7.  Burch, Carl. Floating-point representation. Hendrix College. [2023-08-29].  Buck, Ian, Chapter 32. Taking the Plunge into GPU Computing, Pharr, Matt (编), GPU Gems, 2005-03-13 [2018-04-05], ISBN 0-321-33559-7 . Garrard, Andrew. 10.3. Unsigned 10-bit floating-point numbers. Khronos Data Format Specification v1.2 rev 1. Khronos Group. [2023-08-10].  Garrard, Andrew. 10.2. Unsigned 11-bit floating-point numbers. Khronos Data Format Specification v1.2 rev 1. Khronos Group. [2023-08-10].  Shaneyfelt, Dr. Ted. Dr. Shaneyfelt's Floating Point Consruction Gizmo. Dr. Ted Shaneyfelt. [2023-08-29].  Munafo, Robert. Survey of Floating-Point Formats. 15 May 2016 [8 August 2016].  OpenGL half float pixel