net: ethoc: don't advertise gigabit speed on attached PHY

OpenCores 10/100 Mbps MAC does not support speeds above 100 Mbps, but does
not disable advertisement when PHY supports them. This results in
non-functioning network when the MAC is connected to a gigabit PHY connected
to a gigabit switch.

The fix is to disable gigabit speed advertisement on attached PHY
unconditionally.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
net: ethoc: set up MII management bus clock

MII management bus clock is derived from the MAC clock by dividing it by
MIIMODER register CLKDIV field value. This value may need to be set up
in case it is undefined or its default value is too high (and
communication with PHY is too slow) or too low (and communication with
PHY is impossible). The value of CLKDIV is not specified directly, but
as a pair of MAC frequency and desired MII management bus frequency, as
these parameters are natural.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
net: ethoc: document OF bindings

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: xtfpga: set up MII management bus frequency

Without this setup OpenCores MAC can read PHY registers on KC705 running
at 50MHz, but cannot write there. Initial CLKDIV value appears to be 2,
making MII management bus run at 25MHz, while Marvell 88E1111 PHY
requires minimum 120ns MDC cycle, which is ~8.3MHz.

Request 2MHz MDC frequency to make even slower PHYs from older boards
work.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>