GitHub PushEvent at 2014-12-18 03:16:18
Repository: forked_pink
Actor: pattyboi
Payload: {"shas":[["98606fa3773f8ca88f06344668c70e3a56a34518","aa00819e304141d872f2e4b1c4be422ea3abbfe1@calxeda.com","ARM: 7587/1: implement optimized percpu variable access\n\nUse the previously unused TPIDRPRW register to store percpu offsets.\nTPIDRPRW is only accessible in PL1, so it can only be used in the\nkernel.\n\nThis replaces 2 loads with a mrc instruction for each percpu variable\naccess. With hackbench, the performance improvement is 1.4% on Cortex-A9\n(highbank). Taking an average of 30 runs of \"hackbench -l 1000\" yields:\n\nBefore: 6.2191\nAfter: 6.1348\n\nWill Deacon reported similar delta on v6 with 11MPCore.\n\nThe asm \"memory clobber\" are needed here to ensure the percpu offset\ngets reloaded. Testing by Will found that this would not happen in\n__schedule() which is a bit of a special case as preemption is disabled\nbut the execution can move cores.\n\nSigned-off-by: Rob Herring <rob.herring@calxeda.com>\nAcked-by: Will Deacon <will.deacon@arm.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>\n\nConflicts:\n\tarch/arm/kernel/smp.c","Rob Herring",true],["97839ad2ccc2ddc624161c80fbe2e0a903f189de","b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","ARM: 7747/1: pcpu: ensure __my_cpu_offset cannot be re-ordered across barrier()\n\n__my_cpu_offset is non-volatile, since we want its value to be cached\nwhen we access several per-cpu variables in a row with preemption\ndisabled. This means that we rely on preempt_{en,dis}able to hazard\nwith the operation via the barrier() macro, so that we can't end up\nmigrating CPUs without reloading the per-cpu offset.\n\nUnfortunately, GCC doesn't treat a \"memory\" clobber on a non-volatile\nasm block as a side-effect, and will happily re-order it before other\nmemory clobbers (including those in prempt_disable()) and cache the\nvalue. This has been observed to break the cmpxchg logic in the slub\nallocator, leading to livelock in kmem_cache_alloc in mainline kernels.\n\nThis patch adds a dummy memory input operand to __my_cpu_offset,\nforcing it to be ordered with respect to the barrier() macro.\n\nCc: <stable@vger.kernel.org>\nCc: Rob Herring <rob.herring@calxeda.com>\nReviewed-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","Will Deacon",true]],"size":2,"ref":"refs/heads/lolipop","head":"97839ad2ccc2ddc624161c80fbe2e0a903f189de"}