GitHub PushEvent at 2014-07-25 06:28:29
Repository: openPOWERLINK_V2
Actor: vinodpa
Payload: {"shas":[["2432c0d45887c8592842bf0f285028ffcaaf1197","4e9d7e295764d632dd4cf2fc8e232a254e4ac3d1@kalycito.com","[FEATURE] Add host-interface ipcore for Xilinx designs\n\nAdd host-interface ipcore for parallel-interface and dual-axi design","John",false],["ce6f2b227a798d7a8f6f0275bfa1ce8b68ba6040","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[FEATURE] Add support for Microblaze in host-interface driver library\n\nAdd support for Microblaze processor in host-interface driver library","Vinod PA",false],["5666b95bbd127ce712adda9499910d561045a703","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Update CMake project for hostif driver library on Microblaze\n\nAdd support to compile host-interface driver library for Microblaze\nusing cmake.","Vinod PA",false],["cec3d8f62997f3c046eb309ea91ae8d0135c7475","ec37468091780c52c6e1dac1ea2e5d1a7b738a0e@br-automation.com","[TASK] Rework hardware cmake integration for dual processor systems\n\nRework hardware cmake work flow enabling dual processor designs.\n- Introduce settings for PCP and HOST processor instance\n- Adapt drivers and embedded CN demo\n- Revise Xilinx eclipse project files","Joerg Zelenka",false],["0bf4c25ee51cca774ee3eba83738ebba3937b713","49c2398aae2e85db56ab1407c3ab1f7679e796f3@kalycito.com","[FIX] Fix bsp eclipse project reference\n\nRename generated bsp eclipse project to avoid conflict for\ndual processor designs.","Gaurav Kumar Singh",false],["247ea67afbd33d131e6e228fe070c1b967d02155","4e9d7e295764d632dd4cf2fc8e232a254e4ac3d1@kalycito.com","[FEATURE] Add support in stack for Microblaze designs\n\nUpdate Microblaze architecture sources for possible dual processor designs","Chidrupaya",false],["41fb4deb71114fb0719f8713b2d7808ffd780441","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[FEATURE] Add design files for parallel interface MN on Avnet PLK eval board\n\n- Add PCP and HOST design files for parallel interface MN on\n  Xilinx POWERLINK evaluation board\n- Add software developmemt support files like linker scripts and mss\n  files for PCP and HOST","Vinod PA",false],["de8e13a8f7d62c3fd65c8b11418f169fb2c78a6e","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Add cache coherency for shared memory regions\n\nAdd target independent cache handling macros for\nflushing and invalidating cache in circular buffer and\ntriple buffer region, to maintain cache coherency","Vinod PA",false],["ce4994c71aefbbd641ea7da1bb246ce5e0a18619","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Add cmake support for parallel interface hardware projects\n\nAdd cmake support for  for parallel interface hardware projects on\nAvnet PLK eval board","Vinod PA",false],["3c3f2eb3492baf3413749d708a6a8431a4d36211","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[FEATURE] Add design files for dual-axi bus interface MN on LX150t board\n\n- Add dual-axi inteface design for Xilinx MN on POWERLINK evaluation board\n- Add software developmemt support files like linker scripts and mss\n  files for PCP and HOST processor","Vinod PA",false],["db95dd48d766710b740f35f1f9219b8f80545cdc","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Enable user callback for phy-specific configuration in LX150t\n\nAdd useomethPhyCfgUser function for phy-specific configuration in\nLX150t board","Vinod PA",false],["05e7e15807fe5ddbed7dd3aae1908228e33c7f6e","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Add cmake support for LX150T board compilation\n\nAdd cmake support for dual-axi design in LX150t board","Vinod PA",false],["1412c0b47e6918bed795c6edd0ec0e605b8b7ff0","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Update the source file list for embedded designs\n\nUpdate the source file list for embedded designs.","Vinod PA",false],["dd4ecbbe049835e5175df07feaa7b43bcb031d29","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Add CMake project files for Xiliinx cn-gpio design on Microblaze\n\nAdd CMake project files for Xiliinx cn-gpio design on Microblaze.","Vinod PA",false],["8dc15a5cc52af99f4109698bdebe5003f4fb6405","4e9d7e295764d632dd4cf2fc8e232a254e4ac3d1@kalycito.com","[TASK] Add CMake project files for Xiliinx MN-hostif designs on Microblaze\n\nAdd CMake project files for Xiliinx MN-hostif designs on Microblaze.","Chidrupaya",false],["a29dcda0c825b04c7a01fdd480901e37879417c2","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Update CMake build file for available Microblaze demos\n\n- Add MN-hostif demo to the avilable Microblaze demos.\n- Update CN demo.","Vinod PA",false],["5561d72284995cccd15754d9fd5127b0563047f6","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Update download-elf script to download two elf\n\nUpdate download-elf scripts to download host and pcp application\nfor dual processor design (lx150t board)","Vinod PA",false],["06bec5976fe9dc23b2a517117a2dcd0c481062ac","4780b6bebbcb371e1d1242af858d45d7da863d8b@kalycito.com","[TASK] Update modules to be placed in local memory for Microblaze\n\nUpdate modules to be placed in local memory for Microblaze.","Vinod PA",false],["2dc000be4307121289b39827e9f9dfebf2e35b74","4e9d7e295764d632dd4cf2fc8e232a254e4ac3d1@kalycito.com","[TASK] Add Microblaze MN demo apps\n\n- Add CMake project for demo_mn_embedded on Microblaze\n- Add Microblaze MN-hostif demos to the list of available demos","Chidrupaya",false],["db451221454bbaf383d5377d2c52b0a6ba7964b5","4e9d7e295764d632dd4cf2fc8e232a254e4ac3d1@kalycito.com","[TASK] Add driver daemon application for Microblaze PCP driver\n\n- Add daemon.c for Xilinx Microblaze","Chidrupaya",false]],"size":43,"ref":"refs/heads/zynq-intermediate-commits","head":"7b7c47f8205d11f8c328569c1e94570d4a3385b9"}