GitHub PushEvent at 2014-07-09 10:16:57
Repository: llvm-project
Actor: chapuni
Payload: {"shas":[["774df4753e21fa1d1c54a2665e875ed942421594","420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","[x86] Re-apply a variant of the x86 side of r212324 now that the rest\nhas settled without incident, removing the x86-specific and overly\nstrict 'isVectorSplat' routine in favor of generic and more powerful\nsplat detection.\n\nThe primary motivation and result of this is that the x86 backend can\nnow see through splats which contain undef elements. This is essential\nif we are using a widening form of legalization and I've updated a test\ncase to also run in that mode as before this change the generated code\nfor the test case was completely scalarized.\n\nThis version of the patch much more carefully handles the undef lanes.\n- We aren't overly conservative about them in the shift lowering\n  (where we will never use the splat itself).\n- One place where the splat would have been re-used by the existing code\n  now explicitly constructs a new constant splat that will be safe.\n- The broadcast lowering is much more reasonable with undefs by doing\n  a correct check of whether the splat is the only user of a loaded\n  value, checking that the splat actually crosses multiple lanes before\n  using a broadcast, and handling broadcasts of non-constant splats.\n\nAs a consequence of the last bullet, the weird usage of vpshufd instead\nof vbroadcast is gone, and we actually can lower an AVX splat with\nvbroadcastss where before we emitted a really strange pattern of\na vector load and a manual splat across the vector.","Chandler Carruth",true],["38857f3916f602488926cc45efe98a038f17dffc","157f0aa387af74e0e19b139f9b56b9a20fc05454@imgtec.com","Add ability to emit internal instruction representation to CodeGen assembly output.\n\nSummary:\nThis patch re-uses the implementation of 'llvm-mc -show-inst' and makes it\navailable to llc as 'llc -asm-show-inst'.\n\nThis is necessary to test parts of MIPS32r6/MIPS64r6 without resorting to\n'llc -filetype=obj' tests. For example, on MIPS32r2 and earlier we use the\n'jr $rs' instruction for indirect branches and returns. On MIPS32r6, we no\nlonger have 'jr $rs' and use 'jalr $zero, $rs' instead. The catch is that,\non MIPS32r6, 'jr $rs' is an alias for 'jalr $zero, $rs' and is the preferred\nway of writing this instruction. As a result, all MIPS ISA's emit 'jr $rs' in\ntheir assembly output and the assembler encodes this to different opcodes\naccording to the ISA.\n\nUsing this option, we can check that the MCInst really is a JR or a JALR by\nmatching the emitted comment. This removes the need for a 'llc -filetype=obj'\ntest.\n\nReviewers: rafael, dsanders\n\nReviewed By: dsanders\n\nSubscribers: zoran.jovanovic, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D4267","Daniel Sanders",true]],"size":2,"ref":"refs/heads/master","head":"38857f3916f602488926cc45efe98a038f17dffc"}