hdl/modules/*/generated/virtex6/*: (2/3) use 560 CE instead of 1120 for FOFB CORDIC

This would give an additional ADC clock cycle for
timing slack, easing the timing closure
hdl/modules/*/generated/artix7/*: (3/3) use 560 CE instead of 1120 for FOFB CORDIC

This would give an additional ADC clock cycle for
timing slack, easing the timing closure