Modify base/core classes to enable collection of transmission timing data.
Compute throughput in base.py.
Modify BaseModule._sync() to use slightly less time consuming check when receiving data from other modules, remove unnecessary scipy import from base.py.
Add unit test for Pattern.from_concat().
Reverse order of data and selector in PortMapper constructor to facilitate creation of mappers with no data array; don't attempt to seed rng with module ID in core.py demo.
Create BasePortMapper class that maps integer indices to port identifiers without any associated data array; make PortMapper a child of BasePortMapper.
Add get_map, set_map methods to BasePortMapper.
Fix handling of empty selectors in PathLikeSelector.count_ports().
Add from_index method to BasePortMapper.
Add equals() methods to *PortMapper classes.
Tweak port map classes __repr__ methods.
Add equals(), gpot_pm(), and spike_pm() methods to Interface class.
Rename base.Manager -> base.BaseManager, create new core.Manager class with connect() method that ensures that the integer indices associated with a pattern's interface ports match those of the connected modules' port mappers.
Add test to catch issue #27.
Modify Module.{_put_out_data,_get_in_data} to reduce transmission bandwidth by sending the integer indices mapped to spike ports rather than the port identifiers.
Merge latest port_ids into port_ids_with_timing.
Fix class name in base.py demo.
Another small tweak.
Rename *Module.steps property -> max_steps, remove several unused imports from base.py.
Minor tweaks to get port_ids and ports_id_with_timing branches closer.