GitHub PushEvent at 2014-08-29 21:52:14
Repository: android_kernel_htc_msm8974
Actor: xboxfanj
Payload: {"shas":[["183186b0194c95387467183f5c9a8ab9fa45ca48","010521127f513270fe503d86ab8316ac5147f4b7@codeaurora.org","ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register\n\nThe ISAR0 register indicates support for the SDIV and UDIV\ninstructions in both the Thumb and ARM instruction set. Read the\nregister to detect the supported instructions and update the\nelf_hwcap mask as appropriate. This is better than adding more\nand more cpuid checks in proc-v7.S for each new cpu variant that\nsupports these instructions.\n\nAcked-by: Will Deacon <will.deacon@arm.com>\nCc: Stepan Moskovchenko <stepanm@codeaurora.org>\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: franciscofranco <franciscofranco.1990@gmail.com>","Stephen Boyd",false],["6829dd505ba26fa890b0d7e11fce7c386c0b5b40","42480b5f4d505650064e5081b85d867a03559887@gmail.com","Disable perf events. We don't really need these for production.\n\nSigned-off-by: franciscofranco <franciscofranco.1990@gmail.com>","franciscofranco",false],["5b08c71824751c06f060192b827d3999d7cec069","8cdc8b3d191e9035ee0467e8a2559c0e099975ec@gmail.com","Makefile optimizations","Jake Weinstein",true],["dc74cea06ae98e6f08298b6f74e9f61c5356966d","aa00819e304141d872f2e4b1c4be422ea3abbfe1@calxeda.com","ARM: 7587/1: implement optimized percpu variable access\n\nUse the previously unused TPIDRPRW register to store percpu offsets.\nTPIDRPRW is only accessible in PL1, so it can only be used in the kernel.\n\nThis replaces 2 loads with a mrc instruction for each percpu variable\naccess. With hackbench, the performance improvement is 1.4% on Cortex-A9\n(highbank). Taking an average of 30 runs of \"hackbench -l 1000\" yields:\n\nBefore: 6.2191\nAfter: 6.1348\n\nWill Deacon reported similar delta on v6 with 11MPCore.\n\nThe asm \"memory clobber\" are needed here to ensure the percpu offset\ngets reloaded. Testing by Will found that this would not happen in\n__schedule() which is a bit of a special case as preemption is disabled\nbut the execution can move cores.\n\nSigned-off-by: Rob Herring <rob.herring@calxeda.com>\nAcked-by: Will Deacon <will.deacon@arm.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nConflicts:\n\tarch/arm/include/asm/Kbuild\n\tarch/arm/kernel/smp.c\n\nChange-Id: Ie143b692a5eea090e615e86e22df90f6ecd7fc2c","Rob Herring",true]],"size":4,"ref":"refs/heads/o3","head":"dc74cea06ae98e6f08298b6f74e9f61c5356966d"}