GitHub PushEvent at 2014-10-11 00:24:00
Repository: iverilog
Actor: steveicarus
Payload: {"shas":[["fddb3ec1291924133ce726498401bc5dd874f675","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.\n\nUnfortunately without evaluation it is not possible to warn against\ndegenerated loops, so it had to be removed.","Maciej Suminski",true],["1333bc54a2ecb36ab0d494e0022869e3a1b8b5eb","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Support for 'left & 'right attributes.","Maciej Suminski",true],["6887c8254042e4e25b614ee96620eb4f85b84ff5","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Added ExpAttribute::write_to_stream().","Maciej Suminski",true],["44da7de651dce8e348256a5d24e6e3866c548264","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: prange_t may have the direction determined automatically.","Maciej Suminski",true],["c7beef907d3ac9c33be768f48b0e39ad00b4a8af","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Support for 'range and 'reverse_range attributes.","Maciej Suminski",true],["4b60d2737ec0fca637c355a5c5ff06cf022d0d08","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Skip signed & unsigned in types dump in packages.","Maciej Suminski",true],["7f6100be2a9706178f4a77f19791be7343dea146","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.","Maciej Suminski",true],["8cac72192f8fafb7fde5459aa3519f863532e9b9","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Fix array typedefs in packages.","Maciej Suminski",true],["1a4edcac48b1972ddedd90bf3a2daf8d2f7de293","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vvp: Accepts continuous assignment for 2-state nets.","Maciej Suminski",true],["a992f3ce7c6d83805bff69eaa74f111e22ecf4e3","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Evaluation for 'left and 'right attributes.","Maciej Suminski",true],["9ff9cbf4aaaec76397cc2b408aa048030e08e865","d86f65e7f0d5077c0b676bb93d5bf6ae41a7f301@cern.ch","vhdlpp: Smarter determining the direction in for loops.","Maciej Suminski",true],["d6685f40a16da7908fd48baff0f2abcada12dae9","9ce5770b3bb4b2a1d59be2d97e34379cd192299f@icarus.com","Merge pull request #46 from orsonmmz/range\n\nVHDL attributes: 'range, 'reverse_range, 'left & 'right","Stephen Williams",true]],"size":12,"ref":"refs/heads/master","head":"d6685f40a16da7908fd48baff0f2abcada12dae9"}