GitHub PushEvent at 2014-06-30 15:13:03
Repository: steamos_kernel
Actor: courtney-lunarg
Payload: {"shas":[["e02221c11aebd1cb216c05af0829fd327324e1f0","a17fed27eaa842282862ff7c1b9c8395a26ac320@LunarG.com","Revert drm i915 Workaround of LLC incoherence\n\nRevert drm i915 Workaround incoherence between fences and LLC across multiple CPUs\nThe workaround was obsoleted by a faster, better fix that uses 32 bit write instead of 64-bit writes.","Mike Stroyan",false],["8ca351ae72a2eeb60fae9b9a755c1923c0fab22e","5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","drm/i915/hsw: Disable L3 caching of atomic memory operations.\n\nOtherwise using any atomic memory operation will lock up the GPU due\nto a Haswell hardware bug.\n\nv2: Use the _MASKED_BIT_ENABLE macro.  Drop drm parameter definition.\n\nSigned-off-by: Francisco Jerez <currojerez@riseup.net>\nReviewed-by: Ben Widawsky <ben@bwidawsk.net>\nCc: Daniel Vetter <daniel@ffwll.ch>\nCc: <stable@vger.kernel.org>\n[danvet: Fix checkpatch fail.]\nSigned-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>\n\nConflicts:\n\tdrivers/gpu/drm/i915/intel_pm.c","Francisco Jerez",false],["5309cdab7c2623ae25fa88c79d603b74109a9128","c2208abde9668e8e9815c3690855edd1e63abeac@plagman.net","Merge pull request #2 from LunarG/fix-hsw-atomic-hang\n\ndrm/i915/hsw: Disable L3 caching of atomic memory operations.","Pierre-Loup A. Griffais",true],["72628714e0fe9f19d73174beb0a44fa243675b7e","c2208abde9668e8e9815c3690855edd1e63abeac@plagman.net","Merge pull request #3 from LunarG/revert_25ff119\n\nRevert drm i915 Workaround of LLC incoherence","Pierre-Loup A. Griffais",true]],"size":4,"ref":"refs/heads/alchemist-3.10","head":"72628714e0fe9f19d73174beb0a44fa243675b7e"}