GitHub PushEvent at 2014-07-29 10:04:07
Repository: u-boot-yamada
Actor: masahir0y
Payload: {"shas":[["605714f66998e02cbe3666139a48d83e85fcdc0f","1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@freescale.com","powerpc/85xx: add fdt_fixup_dma3\n\nOn some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is\nchosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Shengzhou Liu",true],["1155d8d853ff8639062651a903ae3062f483dc70","62600720218a1513c3faf8ad88f05a18ec74c9d8@freescale.com","net/fm: call fm_port_to_index() with proper checks\n\nSome of the fm_port_to_index() callers did not check for -1 return value and\nused -1 as an array index.\n\nSigned-off-by: Marian Rotariu <marian.rotariu@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Rotariu Marian-Cristian",true],["09c2046ff651a0d47bb2834d775991ba2c607130","1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@freescale.com","board/t2080qds: enable sst and eon spi flash for nor boot\n\nRemove unnecessary condition CONFIG_RAMBOOT_PBL to\nhave SST and EON SPI flash work in case of NOR boot.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Shengzhou Liu",true],["38d67a4e552ac991f21c2d3e442a38fb0098fda6","d625eca35bf73a7ead1e7970443030cd40d2da25@freescale.com","qe: move immap_qe.h from arch directory into common directory\n\nls1021 is arm-core and supports qe too.\nMove immap_qe.h into common directory for both arm and powerpc.\n\nSigned-off-by: Zhao Qiang <B45475@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Zhao Qiang",true],["d43a386a91379816a6c26458daf3de92cc901b52","ad9280c159074d9ec90899b584f520606e83d10e@freescale.com","powerpc/mpc85xx: Removed support for G4060\n\nG4060 has no PA cores, hence removing its support.\n\nSigned-off-by: Sandeep Singh <Sandeep@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Sandeep Singh",true],["d0bc51407cb1a10bdc0025fb58524c6d13658b83","0e706e5e01a6637ea571a357a533f6af12e6926a@FREESCALE.COM","powerpc/mpc85xx: Remove P1023 RDS support\n\nSince P1023RDS is no longer supported/manufactured by Freescale,\nwe clean up P1023RDS related code.\nSince P1023RDB is still supported by Freescale,\nwe keep P1023RDB releated code.\n\nSigned-off-by: Lijun Pan <Lijun.Pan@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Lijun Pan",true],["3bab3d8324874604501ff9154e68732fb986057a","2fbe35bf2a56078116f98b30b2b493844cc201e1@freescale.com","driver/nand:Define MAX_BANKS same as SoC defined for IFC\n\nThe number of chip select used by IFC controller vary from one SoC to other.\nFor eg. P1010 has 4, T4240 has 8.\n\nUpdate MAX_BANKS same as SoC defined\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Prabhakar Kushwaha",true],["04818bbdc34cb02b2590af8e5f77118ed8a8d755","2fbe35bf2a56078116f98b30b2b493844cc201e1@freescale.com","driver/nand: Update SRAM initialize logic for IFC.\n\nIFC controller v1.1.0 requires internal SRAM initialize by reading\nNAND flash. Higher controller versions have provided \"SRAM init\" bit in\nNCFGR register space.\n\nupdate SRAM initialize logic to reflect the same.\n\nAlso print error message in case of Page read error.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Prabhakar Kushwaha",true],["32514d259bf37cc92872aeb0624b75f600e7fb3a","92ed1c14064887f35fb7c11647aa298140d4f700@freescale.com","fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint\n\nEven u-boot boots up, the pcie link may not setup correctly when\nFreescale SOC acts as endpoint.\nSo change the link status from 'no link' to 'undetermined' to\nreduce the confusion.\nThe link status can check from host side eventually.\n\nSigned-off-by: Roy Zang <tie-fei.zang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Zang Roy-R61911",true],["591dd192307d81cf8f8705b06854e973c53d4c4d","2fbe35bf2a56078116f98b30b2b493844cc201e1@freescale.com","driver/nand: Add support of 16K SRAM for IFC 2.0\n\nInternal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.\n\nUpdate the page offset calculation logic to support the same.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Prabhakar Kushwaha",true],["6666017f44e39ec0385e3c7736b8c9af46cf4f08","dfea4b5ee7d236e001c4e76fe11a89f168c93a94@freescale.com","powerpc/t1040qds: Initialize EPHY2 clock to RGMII only\n\nSetting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.\n\nSigned-off-by: Vijay Rai <vijay.rai@freescale.com>\nSigned-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","vijay rai",true],["8340e7ac86ad3c59956e8f0bd627b741e5209439","44c377796b04a476428a0fa0782ddb7fe1581969@freescale.com","driver/ddr: Fix DDR4 driver for ARM\n\nPreviously the driver was only tested on Power SoCs. Different barrier\ninstructions are needed for ARM SoCs.\n\nSigned-off-by: York Sun <yorksun@freescale.com>","York Sun",true],["9d0456822c4fec302608d4161ae9d9cfe81100b1","44c377796b04a476428a0fa0782ddb7fe1581969@freescale.com","powerpc/mpc85xx: Check return value of find_tlb_idx\n\nfind_tlb_idx() is called in board_early_init_r() on multiple boards.\nThe return value is not checked before being used to disable a TLB.\nIn normal case the return value wouldn't be -1. In case of a mis-\nconfiguration during porting to a new board, checking the return value\nmay be helpful to reveal some user errors.\n\nSigned-off-by: York Sun <yorksun@freescale.com>","York Sun",true],["de5191631088e71ba8ed28bb491dafa776058008","61f8d37dc3334b2eb149cb87f7fe47d17bf78413@freescale.com","powerpc/ifc: fix invalid CSn FTIM2.TCH setting\n\nOn some platforms, CSn FTIM2.TCH is set to zero which is invalid,\nan invalid hold time makes DUT timing variances, whether it works\nor not on luck.\n\nSigned-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Shaohui Xie",true],["3d75ec95f57224995210db5c5dea8d458cf862fb","44c377796b04a476428a0fa0782ddb7fe1581969@freescale.com","driver/ddr: Fix DDR register timing_cfg_8\n\nThe field wrtord_bg should add 2 clocks if on the fly chop is enabled,\naccording to DDR controller manual for DDR4.\n\nSigned-off-by: York Sun <yorksun@freescale.com>","York Sun",true],["e55782ecccadc196a4f9d8e5e8b456e200ea9727","61f8d37dc3334b2eb149cb87f7fe47d17bf78413@freescale.com","powerpc/t4240qds: fix offset of serdes when checking reference clock\n\nT4240 has 4 serdes, each serdes has 4k memory space, two PLLs.\nWe use PLL1CR0 to check the serdes reference clock.\n\nSigned-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Shaohui Xie",true],["a1399a918720337ad14053cf6185786aa33b58b2","6b93aae55d442a6fe311472252044f8dd0bdff22@freescale.com","powerpc/chassis2: Configure and enable L2 cache for PPC clusters only\n\nSigned-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>\nSigned-off-by: Shaveta Leekha <shaveta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Shaveta Leekha",true],["7cb7272365983e3a1eedf18a9f688c825e1cf95e","f0f0f083f68b706cd18f391b0700a5338c91d425@freescale.com","mpc85xx/t104x: Enable L2 and CPC cache when resume\n\nWhen resume from deep sleep, uboot needs to enable L2 and CPC\ncache, or they would be keeping unusable in kernel because\nkernel didn't enble or initialized them.\nThis patch didn't change the existing L2 cache enabling code,\njust put them in a function.\n\nSigned-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Tang Yuantian",true],["b0d97cd2ed8533f98a6c8a12103eddf07ff7bbff","1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@freescale.com","powerpc/t1040: update i2c for t1040qds and t104xrdb\n\n- Fix base address of I2C2 as 0x118100 instead of 0x119000.\n- Add definitions for I2C3 & I2C4.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","Shengzhou Liu",true],["fb5368789a45ca5ee4396cbbf563a8f16ab24f9c","1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@freescale.com","board/freescale: use generic board architecture for t2080qds and t2080rdb\n\nTested with NOR boot and NAND boot on T2080QDS and T2080RDB.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>","Shengzhou Liu",true]],"size":24,"ref":"refs/heads/master","head":"d5f8a6ddd41dee0de17888f8b5334fe1b636c4ca"}