GitHub PushEvent at 2014-05-23 23:46:03
Repository: android_kernel_huawai_Y300-J1
Actor: moddingg33k
Payload: {"shas":[["d4edc7589571ebd99577e4c1479918a0fad6ade7","322faa2212623d0ee1c1d3a3679453c711b009e4@t-online.de","Frandom: adding FRANDOM v1.1 (Credits to: Eli billauer)\n\nhttp://billauer.co.il/frandom.html","moddingg33k",true],["2bbfb928ef7829839874852e32808c5879f10721","322faa2212623d0ee1c1d3a3679453c711b009e4@t-online.de","Makefile: GCC Flags: *enabled unaligned-access code generation*","moddingg33k",true],["ac26334f6cee0a22abecc848805e1e45ec490b04","b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","*enabling DCACHE_WORD_ACCESS for ARMv6+*\n\nARM: 7450/1: dcache: select DCACHE_WORD_ACCESS for little-endian ARMv6+ CPUs\n\nDCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string\ncomparisons in the vfs layer.\n\nThis patch implements support for load_unaligned_zeropad for ARM CPUs\nwith native support for unaligned memory accesses (v6+) when running\nlittle-endian.\n\nReviewed-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nword-at-a-time: provide generic big-endian zero_bytemask implementation\n\nWhilst architectures may be able to do better than this (which they can,\nby simply defining their own macro), this is a generic stab at a\nzero_bytemask implementation for the asm-generic, big-endian\nword-at-a-time implementation.\n\nOn arm64, a clz instruction is used to implement the fls efficiently.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Linus Torvalds <torvalds@linux-foundation.org>\n\nARM: 7927/1: dcache: select DCACHE_WORD_ACCESS for big-endian CPUs\n\nWith commit 11ec50caedb5 (\"word-at-a-time: provide generic big-endian\nzero_bytemask implementation\"), the asm-generic word-at-a-time code now\nprovides a zero_bytemask implementation, allowing us to make use of\nDCACHE_WORD_ACCESS on big-endian CPUs, providing our\nload_unaligned_zeropad function is endianness-clean.\n\nThis patch reworks the load_unaligned_zeropad fixup code to work for\nboth big- and little-endian CPUs, then removes the !CPU_BIG_ENDIAN check\nwhen selecting DCACHE_WORD_ACCESS.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nword-at-a-time: avoid undefined behaviour in zero_bytemask macro\n\nThe asm-generic, big-endian version of zero_bytemask creates a mask of\nbytes preceding the first zero-byte by left shifting ~0ul based on the\nposition of the first zero byte.\n\nUnfortunately, if the first (top) byte is zero, the output of\nprep_zero_mask has only the top bit set, resulting in undefined C\nbehaviour as we shift left by an amount equal to the width of the type.\nAs it happens, GCC doesn't manage to spot this through the call to fls(),\nbut the issue remains if architectures choose to implement their shift\ninstructions differently.\n\nAn example would be arch/arm/ (AArch32), where LSL Rd, Rn, #32 results\nin Rd == 0x0, whilst on arch/arm64 (AArch64) LSL Xd, Xn, #64 results in\nXd == Xn.\n\nRather than check explicitly for the problematic shift, this patch adds\nan extra shift by 1, replacing fls with __fls. Since zero_bytemask is\nnever called with a zero argument (has_zero() is used to check the data\nfirst), we don't need to worry about calling __fls(0), which is\nundefined.\n\nCc: <stable@vger.kernel.org>\nCc: Victor Kamensky <victor.kamensky@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Linus Torvalds <torvalds@linux-foundation.org>\n\nARM: 7928/1: kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS for CPUv6+ && MMU\n\nModern ARM CPUs can perform efficient unaligned memory accesses in\nhardware and this feature is relied up on by code such as the dcache\nword-at-a-time name hashing.\n\nThis patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS for these cores and\nreworks the kconfig select logic for DCACHE_WORD_ACCESS to use the new\nsymbol.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Will Deacon",true],["6dfaacc2dc708f11863d144ac41882af4315d4df","322faa2212623d0ee1c1d3a3679453c711b009e4@t-online.de","ARM: armv7 no need update SCTLR for alignment\n\nIn Armv7, cr_alignment and cr_no_alignment are always same, in alignment_init both\ncr_alignment and cr_no_alignment will be updated by clearing A bit. So there is no\nmeaning to update SCTLR if interrupt and exception disturbs the user-space.\n\nSigned-off-by: Wuqixuan <wuqixuan@huawei.com>","moddingg33k",true],["f6a43b3d104c61cfc25342da485ce87d264e1457","a21938f5d463ddf41aa718934c205ca2cce8ebbc@redhat.com","add extra free kbytes tunable\n\nAdd a userspace visible knob to tell the VM to keep an extra amount\nof memory free, by increasing the gap between each zone's min and\nlow watermarks.\n\nThis is useful for realtime applications that call system\ncalls and have a bound on the number of allocations that happen\nin any short time period.  In this application, extra_free_kbytes\nwould be left at an amount equal to or larger than than the\nmaximum number of allocations that happen in any burst.\n\nIt may also be useful to reduce the memory use of virtual\nmachines (temporarily?), in a way that does not cause memory\nfragmentation like ballooning does.\n\n[ccross]\nRevived for use on old kernels where no other solution exists.\nThe tunable will be removed on kernels that do better at avoiding\ndirect reclaim.\n\nChange-Id: I765a42be8e964bfd3e2886d1ca85a29d60c3bb3e\nSigned-off-by: Rik van Riel<riel@redhat.com>\nSigned-off-by: Colin Cross <ccross@android.com>\nGit-commit: 92189d47f66c67e5fd92eafaa287e153197a454f\nGit-repo: https://android.googlesource.com/kernel/common/\n[bhargavuln@codeaurora.org: resolve trivial merge conflicts]\nSigned-off-by: Bhargav Upperla <bhargavuln@codeaurora.org>","Rik van Riel",true]],"size":5,"ref":"refs/heads/master","head":"f6a43b3d104c61cfc25342da485ce87d264e1457"}