GitHub PushEvent at 2014-06-26 21:54:11
Repository: gcc
Actor: Lucretia
Payload: {"shas":[["17c31e6ab523e66a269c876ac3fccac9c794abe5","c3086f39b419b7609cc15a9ed42435593e1f94e9@archeia.com","Added --enable-cross-gnattools to enable GNAT's cross tools to be built for bare metal.","Luke A. Guest",true],["4e8773e102c973b6e23a603bc24a931a982212e8","c3086f39b419b7609cc15a9ed42435593e1f94e9@archeia.com","Fix to allow gnattools/configure to select the correct mlib-tgt-specific files for bare metal compilers.","Luke A. Guest",true],["4c1d6598f2006bb64257ec6f5f66a24e298f6284","18e847a8b9ebeb5f228dbfc5aa2371894e947a9d@138bc75d-0d04-0410-961f-82ee72b054a4","2014-06-21  Jan-Benedict Glaw  <jbglaw@lug-owl.de>\n\ngcc/\n\t* config/nios2/nios2.c: Include \"builtins.h\".\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211868 138bc75d-0d04-0410-961f-82ee72b054a4","jbglaw",true],["6e7430cf327281d32b4763e438cde72c5c59d2b8","14e5b275235559d1ccf7e802f391c6d3c95ca63d@138bc75d-0d04-0410-961f-82ee72b054a4","\t* gcc.dg/localalias.c: Fix broken commit.\n\t* gcc.dg/globalalias.c: Likewise.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211869 138bc75d-0d04-0410-961f-82ee72b054a4","hubicka",true],["762bc62e484bf8601029a4162b53829231ce4eaa","2aa286f04500e4a7a9254cbd74d9060dce58402c@138bc75d-0d04-0410-961f-82ee72b054a4","Daily bump.\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211872 138bc75d-0d04-0410-961f-82ee72b054a4","gccadmin",true],["9edd7e4c549093a59cf5110766be84b1d97bd221","47b530adcd050575ed412d3f2784e8e3d4010bc1@138bc75d-0d04-0410-961f-82ee72b054a4","2014-06-22  Marc Glisse  <marc.glisse@inria.fr>\n\n\tPR target/61503\n\t* config/i386/i386.md (x86_64_shrd, x86_shrd,\n\tix86_rotr<dwi>3_doubleword): Replace ashiftrt with lshiftrt.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211873 138bc75d-0d04-0410-961f-82ee72b054a4","glisse",true],["f2a532ebadd7e4f8cf1c31799b0e9975cbc64b5e","d14feb13b187709a6a8e3489dc080708170d5b05@138bc75d-0d04-0410-961f-82ee72b054a4","gcc/\n\t* config/mips/mips.c (mips_move_to_gpr_cost): Remove mode argument.\n\t(mips_move_from_gpr_cost): Likewise.\n\t(mips_register_move_cost): Update accordingly.\n\t(mips_secondary_reload_class): Remove name of in_p.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211874 138bc75d-0d04-0410-961f-82ee72b054a4","rsandifo",true],["b06d4b4df5835f34632b7bdfc8c90d40f714fc8e","2343885bc648d4446d043d3be1cd7c9dbde217a3@138bc75d-0d04-0410-961f-82ee72b054a4","rs6000: Remove \"O\" alternative from lshrsi3\n\nNothing will ever generate RTL matching this alternative.  Maybe long\nago this was needed, but not anymore.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211875 138bc75d-0d04-0410-961f-82ee72b054a4","segher",true],["c0c929b15d41734296ae9d77ca7f629e086b0890","2343885bc648d4446d043d3be1cd7c9dbde217a3@138bc75d-0d04-0410-961f-82ee72b054a4","rs6000: Merge lshrsi3 and lshrdi3\n\nFor this create a new mode_attr \"hH\".\n\nAlso change \"i\" constraints on the shift amount to \"n\", which better\ndescribes what it really is (GCC takes the integer value of these\noperands and does arithmetic on them; symbolic constants will not work\nhere).\n\nAlso merge the \"dot\" insns with the corresponding splitters.  To do\nthis, don't allow the dot insns for CBE non-microcode mode at all\n(it previously would just split it back always).\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211876 138bc75d-0d04-0410-961f-82ee72b054a4","segher",true],["3500f0b20f111df98d701f4c63654eedc0f4fcf2","2343885bc648d4446d043d3be1cd7c9dbde217a3@138bc75d-0d04-0410-961f-82ee72b054a4","Merge ashlsi3 and ashldi3\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211877 138bc75d-0d04-0410-961f-82ee72b054a4","segher",true],["349898937ce9207ba829524fd93103636899fd44","2343885bc648d4446d043d3be1cd7c9dbde217a3@138bc75d-0d04-0410-961f-82ee72b054a4","rs6000: Merge rotlsi3 and rotldi3\n\nThis uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl\nmnemonics, because they are shorter and more importantly they look the\nsame for 32-bit and 64-bit.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211878 138bc75d-0d04-0410-961f-82ee72b054a4","segher",true],["93480a5bed3249e8a11b8e82a8fb10e29139396e","2343885bc648d4446d043d3be1cd7c9dbde217a3@138bc75d-0d04-0410-961f-82ee72b054a4","rs6000: Merge ashrsi3 and ashrdi3\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211879 138bc75d-0d04-0410-961f-82ee72b054a4","segher",true],["5acde2ccade47555187acb7ffa8bd82b93ca31e7","2343885bc648d4446d043d3be1cd7c9dbde217a3@138bc75d-0d04-0410-961f-82ee72b054a4","rs6000: Merge the var_shift yes/no alternatives\n\nAll instructions that are \"var_shift\" for some alternative have the shift\namount as operands[2].\n\nThis patch introduces an attribute \"maybe_var_shift\".  If that is set to\n\"yes\", the default value of \"var_shift\" is set based on the operands[2]\nvalue.\n\nWith that, we can merge the var_shift yes/no cases everywhere.  Do so.\n\nAlso change some more \"i\" to \"n\".\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211880 138bc75d-0d04-0410-961f-82ee72b054a4","segher",true],["88dc3e3ae872a30d541df58256983673863cc9f1","aea4fd857e97ee7d33f60175ba9388a955b9d916@138bc75d-0d04-0410-961f-82ee72b054a4","PR target/61565\n\n* compare-elim.c (struct comparison): Add eh_note.\n(find_comparison_dom_walker::before_dom_children): Don't eliminate\na redundant comparison in a different EH region.  Purge EH edges if\nnecessary.\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211881 138bc75d-0d04-0410-961f-82ee72b054a4","rth",true],["652029efe606fade3a068d528ed7c961e33c6736","2aa286f04500e4a7a9254cbd74d9060dce58402c@138bc75d-0d04-0410-961f-82ee72b054a4","Daily bump.\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211884 138bc75d-0d04-0410-961f-82ee72b054a4","gccadmin",true],["320c04242284af839a6eb972aaaf7c5a9ecbac94","70f0596e33935c033891e61800fb7c234113ecb3@138bc75d-0d04-0410-961f-82ee72b054a4","2014-06-23  Zhenqiang Chen  <zhenqiang.chen@linaro.org>\n\n\t* loop-invariant.c (pre_check_invariant_p): New function.\n\t(find_invariant_insn): Call pre_check_invariant_p.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211885 138bc75d-0d04-0410-961f-82ee72b054a4","zqchen",true],["7adfd79d16e731bbb66fa831725c7fea4e8bf3de","14e5b275235559d1ccf7e802f391c6d3c95ca63d@138bc75d-0d04-0410-961f-82ee72b054a4","\t* lto-cgraph.c (lto_output_node, input_node): Set/get init/fini priority\n\tdirectly.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211886 138bc75d-0d04-0410-961f-82ee72b054a4","hubicka",true],["8fdb74c21e3b7b4ebc69613cffc5dd12c1ba7368","6d7571cf31a6977730f768f8b3cccfef216c9bd7@138bc75d-0d04-0410-961f-82ee72b054a4","[AArch64] Implement ADD in vector registers for 32-bit scalar values.\n\ngcc/\n\n\t* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in\n\tvector registers.\n\ngcc/testsuite/\n\n\t* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211887 138bc75d-0d04-0410-961f-82ee72b054a4","jgreenhalgh",true],["13d8abf43fb9e1503da11bdd177d18e9c46f5400","71b1be2b66a17077a3afcb609973d02ab43136ba@138bc75d-0d04-0410-961f-82ee72b054a4","\t* include/bits/parse_numbers.h (_Number_help): Fix divide-by-zero.\n\t* include/std/chrono (_Checked_integral_constant): Allow zero.\n\t* testsuite/20_util/duration/literals/values.cc: Test non-positive\n\tvalues and digit separators.\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211890 138bc75d-0d04-0410-961f-82ee72b054a4","redi",true],["09d554aa31c8d4ffb2d1e35beb9970b120c1364a","9630a2a6bbdd9133585b9a35d89ffe3bdb7d7f3d@138bc75d-0d04-0410-961f-82ee72b054a4","PR/60825 Make float64x1_t in arm_neon.h a proper vector type\n\ngcc/ChangeLog:\n\tPR target/60825\n\t* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for\n\tV1DFmode.\n\t* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):\n\tadd V1DFmode\n\t(BUILTIN_VD1): New.\n\t(BUILTIN_VD_RE): Remove.\n\t(aarch64_init_simd_builtins): Add V1DF to modes/modenames.\n\t(aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df.\n\t* config/aarch64/aarch64-simd-builtins.def (create): Make a v1df\n\tvariant but not df.\n\t(vreinterpretv1df*, vreinterpret*v1df): New.\n\t(vreinterpretdf*, vreinterpret*df): Remove.\n\t* config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*):\n\tGenerate V1DFmode pattern not DFmode.\n\t* config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF.\n\t(VD1): New.\n\t* config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions.\n\t(vcreate_f64): Remove cast, use v1df builtin.\n\t(vcombine_f64): Remove cast, get elements with gcc vector extensions.\n\t(vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64,\n\tvcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64,\n\tvdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64,\n\tvmov_n_f64, vst1_f64): Use gcc vector extensions.\n\t(vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions,\n\tadd range check using __builtin_aarch64_im_lane_boundsi.\n\t(vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64,\n\tvfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix\n\ttype signature, use gcc vector extensions.\n\t(vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64,\n\tvreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16,\n\tvreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32,\n\tvreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16,\n\tvreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64,\n\tvreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64,\n\tvreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64,\n\tvreinterpret_u64_f64): Use v1df builtin not df.\n\ngcc/testsuite/ChangeLog:\n\t* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.\n\t* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.\n\t* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.\n\t* gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements.\n\t* gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types.\n\t* gcc.target/aarch64/vsub_f64.c: Likewise.\n\t* gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme\n\tas now the same for all variants.\n\t* gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not\n\tfloat64x1_t.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211892 138bc75d-0d04-0410-961f-82ee72b054a4","alalaw01",true]],"size":121,"ref":"refs/heads/master","head":"bf221972a2f3d1d13d932d903f436084f3865763"}