GitHub PushEvent at 2014-12-25 12:17:53
Repository: freebsd
Actor: strejda
Payload: {"shas":[["8a57c3f8f2e0b0a86ad7f56b30a1955f9c375d89","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Don't define CP15 registers that aren't valid for the selected architecture.","Michal Meloun",true],["307f3dee5dd0a112fc67426ed0c0030293bc4cd6","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Implement initial version of cpuinfo.","Michal Meloun",true],["d5cf027170e7f9b0ebdb44ebd8bf359fef5b51d2","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Define new inline TLB and cache functions.","Michal Meloun",true],["25eb8b89b2da0cfc51c3eef87b2938a59e309cc9","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Cleanup exception.S. Prepare for later unification of data_abort_handler() and prefetch_abort_handler().","Michal Meloun",true],["c1a7f073ee504c4a07a958329a408670ee000788","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","First step in cleanup of locore.S. Fix initial stack allocation. Rename initial page table and use it for startup of secondary cores too. Same page table can be used for CPU hot plug and/or power management later.","Michal Meloun",true],["e452236a3872bcd4b261c0b80aed1d9032fa75bf","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Add new ARMv6 specific trap-v6.c.","Michal Meloun",true],["49b04d5908015637fad8fce094300b9f055cc45f","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Add new pmap code.","Michal Meloun",true],["c6793bfc3fe25014415144f879e8f51b393a558b","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Fix handling of direct section unmapping.\n    Use local variant of tlb_fush functions where appropriate","Michal Meloun",true],["1445cefdb9cfc4ecb29d676854c85761117c9f13","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Merge r271716","Michal Meloun",true],["694cf3614e36fedf867ea149b46eae9a8c7c828c","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Rename pmap_tlb_flush_page. Use correct argument type  when calling tlb_flush functions. Minor cleanup nits.","Michal Meloun",true],["7dce4cf6ef7d1c3ffd8c7b462368cc681aa30fcc","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Switch DMA coherent memory to normal uncacheable memory","Michal Meloun",true],["ebbd7cca44ac4ef7d2a2e7875bd78e43b8f1f335","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Major cleanup of new pmap code.","Michal Meloun",true],["309ffa67f940c7d15e4a3998b8a0c80dbb58cf9a","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Fix comments. Use macro for simplify pvh list Add first managed physical address.","Michal Meloun",true],["b26255fe14af40d91aa5220de10d988cb9359346","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Fix style.","Michal Meloun",true],["4615d4c4fd91fd7078b5bef92696c1b3e30903c9","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Use new VM_PHYSSEG_SPARSE infrastructure","Michal Meloun",true],["2d7ce003dd094db009b50f5f22fde6ad4c926a2a","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Use global tlb flush when servicing emulated access and modified bits.","Michal Meloun",true],["8ca51a4d05c401fe29b9d4e7cc4c6552bc4a2f16","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Adjust NKPT2PG. Fix improper usage of ATTR_TO_L2. Add comments in pmap_init().","Michal Meloun",true],["5decb2ea4f0550d9b034794189bc319cd642b3c5","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Remove now useless .arch directive form assembler files.","Michal Meloun",true],["bca85d5abc3f3e69091e8590edb4b4272eb448b0","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Fix checking for current pmap. Remove obsolete header.","Michal Meloun",true],["5d9d2073b041dbb697c4830e7b3781e496869a9f","25a9b0e7106dc4a55ceb4bd4a968a66911b1757f@users.noreply.github.com","Fix bogus constant for shift. Don't set cached flag in TTB for CPUs that not support cached page table walk.","Michal Meloun",true]],"size":28,"ref":"refs/heads/master","head":"5fbe515911396a8901854f04ef4b872c6b9f6a17"}