GitHub PullRequestReviewCommentEvent at 2014-08-13 03:21:12
Repository: manifold
Actor: TysonAndre
Payload: {"action":"created","comment":{"url":"https://api.github.com/repos/manifold-lang/manifold/pulls/comments/16155797","id":16155797,"diff_hunk":"@@ -372,6 +371,214 @@ public void testRegisterProcessGenerationAsynchronousReset()\n   }\n   \n   @Test\n+  public void testANDSignalGeneration() throws SchematicException, IOException {\n+    // Connect two inputs through an AND gate to an output.\n+    Schematic schematic = UtilSchematicConstruction\n+        .instantiateSchematic(\"test\");\n+    NodeValue in0 = UtilSchematicConstruction.instantiateInputPin();\n+    schematic.addNode(\"in0\", in0);\n+    NodeValue in1 = UtilSchematicConstruction.instantiateInputPin();\n+    schematic.addNode(\"in1\", in1);\n+    NodeValue and0 = UtilSchematicConstruction.instantiateAnd();\n+    schematic.addNode(\"and0\", and0);\n+    NodeValue out0 = UtilSchematicConstruction.instantiateOutputPin();\n+    schematic.addNode(\"out0\", out0);\n+    ConnectionValue net0 = UtilSchematicConstruction.instantiateWire(\n+        in0.getPort(\"out\"), and0.getPort(\"in0\"));\n+    schematic.addConnection(\"net0\", net0);\n+    ConnectionValue net1 = UtilSchematicConstruction.instantiateWire(\n+        in1.getPort(\"out\"), and0.getPort(\"in1\"));\n+    schematic.addConnection(\"net1\", net1);\n+    ConnectionValue net2 = UtilSchematicConstruction.instantiateWire(\n+        and0.getPort(\"out\"), out0.getPort(\"in\"));\n+    schematic.addConnection(\"net2\", net2);\n+\n+    VHDLCodeGenerator codegen = new VHDLCodeGenerator(schematic);\n+    File tempdir = folder.getRoot();\n+    String temppath = tempdir.getAbsolutePath();\n+    codegen.setOutputDirectory(temppath);\n+    codegen.generateOutputProducts();\n+    \n+    // open test.vhd\n+    String testOutputFilename = temppath + \"/test.vhd\";\n+    Path testOutputPath = Paths.get(testOutputFilename);\n+    List<String> testLines = Files.readAllLines(testOutputPath);\n+    \n+    Pattern archBegin = Pattern.compile(\"^\\\\s*architecture\",\n+        Pattern.CASE_INSENSITIVE);\n+    Pattern archEnd = Pattern.compile(\"end\\\\s*architecture\",\n+        Pattern.CASE_INSENSITIVE);\n+    Pattern andAssign = Pattern.compile(\"<=.*[aA][nN][dD]\");\n+    \n+    boolean foundArchitecture = false;\n+    boolean foundGate = false;\n+    boolean scanningArchitecture = false;\n+    for (String line : testLines) {\n+      if (scanningArchitecture) {\n+        Matcher mArchEnd = archEnd.matcher(line);\n+        if (mArchEnd.find()) {\n+          scanningArchitecture = false;\n+          break;\n+        }\n+        Matcher mAndAssign = andAssign.matcher(line);\n+        if (mAndAssign.find()) {\n+          if (foundGate) {\n+            fail(\"multiple AND gates found\");\n+          } else {\n+            foundGate = true;\n+          }\n+        }\n+      } else {\n+        Matcher mArchBegin = archBegin.matcher(line);\n+        if (mArchBegin.find()) {\n+          foundArchitecture = true;\n+          scanningArchitecture = true;\n+        }\n+      }\n+    }\n+    assertTrue(\"no architecture block found in generated code\", \n+        foundArchitecture);\n+    assertTrue(\"no AND gate found in generated code\", foundGate);\n+  }\n+  \n+  @Test\n+  public void testORSignalGeneration() throws SchematicException, IOException {\n+    // Connect two inputs through an OR gate to an output.\n+    Schematic schematic = UtilSchematicConstruction\n+        .instantiateSchematic(\"test\");\n+    NodeValue in0 = UtilSchematicConstruction.instantiateInputPin();\n+    schematic.addNode(\"in0\", in0);\n+    NodeValue in1 = UtilSchematicConstruction.instantiateInputPin();\n+    schematic.addNode(\"in1\", in1);\n+    NodeValue or0 = UtilSchematicConstruction.instantiateOr();\n+    schematic.addNode(\"or0\", or0);\n+    NodeValue out0 = UtilSchematicConstruction.instantiateOutputPin();\n+    schematic.addNode(\"out0\", out0);\n+    ConnectionValue net0 = UtilSchematicConstruction.instantiateWire(\n+        in0.getPort(\"out\"), or0.getPort(\"in0\"));\n+    schematic.addConnection(\"net0\", net0);\n+    ConnectionValue net1 = UtilSchematicConstruction.instantiateWire(\n+        in1.getPort(\"out\"), or0.getPort(\"in1\"));\n+    schematic.addConnection(\"net1\", net1);\n+    ConnectionValue net2 = UtilSchematicConstruction.instantiateWire(\n+        or0.getPort(\"out\"), out0.getPort(\"in\"));\n+    schematic.addConnection(\"net2\", net2);\n+\n+    VHDLCodeGenerator codegen = new VHDLCodeGenerator(schematic);\n+    File tempdir = folder.getRoot();\n+    String temppath = tempdir.getAbsolutePath();\n+    codegen.setOutputDirectory(temppath);\n+    codegen.generateOutputProducts();\n+    \n+    // open test.vhd\n+    String testOutputFilename = temppath + \"/test.vhd\";\n+    Path testOutputPath = Paths.get(testOutputFilename);\n+    List<String> testLines = Files.readAllLines(testOutputPath);\n+    \n+    Pattern archBegin = Pattern.compile(\"^\\\\s*architecture\",","path":"src/test/java/org/manifold/compiler/back/TestVHDLCodeGenerator.java","position":116,"original_position":116,"commit_id":"107d03c9ad3c2542f8deabc0a87287e4393bc5c2","original_commit_id":"107d03c9ad3c2542f8deabc0a87287e4393bc5c2","user":{"login":"TysonAndre","id":1904430,"avatar_url":"https://avatars.githubusercontent.com/u/1904430?v=2","gravatar_id":"590d4417185a02635e0065213fb12482","url":"https://api.github.com/users/TysonAndre","html_url":"https://github.com/TysonAndre","followers_url":"https://api.github.com/users/TysonAndre/followers","following_url":"https://api.github.com/users/TysonAndre/following{/other_user}","gists_url":"https://api.github.com/users/TysonAndre/gists{/gist_id}","starred_url":"https://api.github.com/users/TysonAndre/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/TysonAndre/subscriptions","organizations_url":"https://api.github.com/users/TysonAndre/orgs","repos_url":"https://api.github.com/users/TysonAndre/repos","events_url":"https://api.github.com/users/TysonAndre/events{/privacy}","received_events_url":"https://api.github.com/users/TysonAndre/received_events","type":"User","site_admin":false},"body":"Parsing the sublist of the architecture block and checking structure could be done in a separate function.\r\n\r\nPossibly the same comment for generating the List<String> from a Schematic.\r\n\r\nOn a side note, should you empty the temporary directory before each test (It might pass if a different test creates test.vhdl with a single OR statement.","created_at":"2014-08-13T03:21:12Z","updated_at":"2014-08-13T03:21:12Z","html_url":"https://github.com/manifold-lang/manifold/pull/165#discussion_r16155797","pull_request_url":"https://api.github.com/repos/manifold-lang/manifold/pulls/165","_links":{"self":{"href":"https://api.github.com/repos/manifold-lang/manifold/pulls/comments/16155797"},"html":{"href":"https://github.com/manifold-lang/manifold/pull/165#discussion_r16155797"},"pull_request":{"href":"https://api.github.com/repos/manifold-lang/manifold/pulls/165"}}},"pull_request":{"url":"https://api.github.com/repos/manifold-lang/manifold/pulls/165","id":19702589,"html_url":"https://github.com/manifold-lang/manifold/pull/165","diff_url":"https://github.com/manifold-lang/manifold/pull/165.diff","patch_url":"https://github.com/manifold-lang/manifold/pull/165.patch","issue_url":"https://api.github.com/repos/manifold-lang/manifold/issues/165","number":165,"state":"open","title":"Backend tests: AND, OR, NOT","user":{"login":"mtrberzi","id":1020536,"avatar_url":"https://avatars.githubusercontent.com/u/1020536?v=2","gravatar_id":"94b472180c04c7cb56aa314e771af014","url":"https://api.github.com/users/mtrberzi","html_url":"https://github.com/mtrberzi","followers_url":"https://api.github.com/users/mtrberzi/followers","following_url":"https://api.github.com/users/mtrberzi/following{/other_user}","gists_url":"https://api.github.com/users/mtrberzi/gists{/gist_id}","starred_url":"https://api.github.com/users/mtrberzi/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mtrberzi/subscriptions","organizations_url":"https://api.github.com/users/mtrberzi/orgs","repos_url":"https://api.github.com/users/mtrberzi/repos","events_url":"https://api.github.com/users/mtrberzi/events{/privacy}","received_events_url":"https://api.github.com/users/mtrberzi/received_events","type":"User","site_admin":false},"body":"Here are some really easy codegen tests for logic gates in the VHDL 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