GitHub PushEvent at 2014-03-08 11:14:02
Repository: linux
Actor: jhnikula
Payload: {"shas":[["f32ee1a8f7c0ef2c4ddf051e19441e3e805124f5","ed47dfa4cd43d03d92ccc66ffdb9609c96fcf22b@linux.intel.com","ASoC: Intel: Revisit Baytrail reset and boot logic\n\nDebugging DSP double reseting has shown that different delays nor setting\nreset bit after stall bit in sst_byt_reset() seems not to help DSP re-reset\nissues. More over one reference code is doing it in the same way than this\nfunction was doing originally but without any delay.\n\nThen sst_byt_boot() was more interesting. It appeared that CSR register\nreads there are very sensitive after releasing the stall. In current form\nPWAITMODE was zero immediately but turned on somewhere later. If there was\na delay after releasing the stall and then subsequent CSR reads the DSP\nappeared to be lost completely. The same reference is also doing DSP boot\ndifferently: it sets all reset, reset vector and stall bits again and then\nclears reset and stall without a delay between these operations.\n\nTherefore change the sst_byt_reset() and sst_byt_boot() to behave like the\nreference code. It appears DSP sends the FW init complete message now\nwhen doing second reset but IPC commands to DSP will timeout.\n\nSigned-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>","Jarkko Nikula",true],["006131f4673c9c35ed02d539f45ec5b716756609","ed47dfa4cd43d03d92ccc66ffdb9609c96fcf22b@linux.intel.com","ASoC: Intel: Set one extra bit in sst_byt_boot when booting\n\nReference code is setting this at the same time when releasing the reset\nand stall.\n\nSigned-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>","Jarkko Nikula",true]],"size":2,"ref":"refs/heads/intel/test-dsp-reset","head":"006131f4673c9c35ed02d539f45ec5b716756609"}