GitHub PushEvent at 2014-12-17 09:12:53
Repository: optee_os
Actor: jforissier
Payload: {"shas":[["350e12e3efd723ff1661280f5e7d8473e9c96772","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","merge tee_pager*.c and tee_pager*.h files\n\n* Merges tee_pager_unpg.c and tee_pager.c into tee_pager.c\n* Merges tee_pager_unpg.h and tee_pager.h into tee_pager.h\n* Removes some legacy dummy macros\n* Replaces some while(1) with panic()\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["1268781a13a884b41bbbe1f5e5e640d27946c2ef","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: add thread_init_per_cpu()\n\nAdds a thread_init_per_cpu() function that should be called instead of\nthread_init_handlers() by the secondary CPUs. The primary CPU should first\ncall thread_init_handlers() and then thread_init_per_cpu().\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["c5f6df153bd85502db54ec11b2c5ea038b03f883","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: split and enhance core_init_mmu()\n\n* Splits core_init_mmu() into two functions, core_init_mmu_tables() called\n  by primary CPU to create the translation tables and core_init_mmu_regs()\n  called by each CPU to initialize MMU register settings.\n* Adds option to map certain areas in a level 2 translation table instead\n  of only level 1 mapping. Allocation of the level 2 translation tables\n  is implemented in platform specific code, a weak function is provided\n  in case the platform doesn't implement/need the function.\n* Adds L2 translation table for STM and Vexpress.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>\nTested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)\nTested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform)","Jens Wiklander",false],["c0dbcfde1250d904b691e0125998b2292bbdae9a","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: make all TLB invalidations inner sharable\n\n* Makes all TLB invalidations inner sharable\n* Removes deprecated TLB invalidations\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["76d547995486aa59966da74669913cd4bb0e3f31","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","plat-vexpress: clean memory configuration\n\n* Cleans the memory configuration for plat-vexpress to make it easier\n  to add fake and real SRAM.\n* Uses common functions to check if a buffer intersects or is inside\n  a memory area\n* Increases number of cores from 4 to 8 for FVP flavor to support Base\n  model better.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["e3bbec52c001ec97832897c8aa3fa325464f37c8","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: move call to teecore_init_ta_ram()\n\nMoves call to teecore_init_ta_ram() from init_teecore() to be called\ndirectly from platform initialization routines.  It's needed later when\nthe pager allocates secure DDR to store that backing pages. We don't want\nto call init_teecore() until the pager is fully initialized because\ninit_teecore() pulls in many dependencies.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["a14bf579f96d6c0f11ba6a41434c1da345b557c3","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","plat-vexpress: reorganize boot for paging\n\nReorganizes the boot functions to keep primary and secondary boot path\nmore separated as a preparation for the pager.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["f69755b7e7795c4de11ca50530479dbe24224f10","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","tee_mm: remove legacy TEE_MM_POOL_PAGED define\n\nRemoves the legacy TEE_MM_POOL_PAGED define and unsused code\nassociated with it.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["820f30dbf0bb6013e6f61061b91c3a5c5a987741","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: assembly routines in separate sections\n\nMoves some assembly routines into separate sections. This helps the garbage\ncollecting with the linker when separating what's must be unpaged from the\nrest of the code. The garbage collector in the linker works on dependencies\nbetween sections.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["6a8df3c8f35955c0bc836d6cb58d425e7646c66e","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","plat-vexpress: separate sections\n\nPuts functions and data into separate sections\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nTested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP)\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["a446d608c8662828234214dc66817c858af6f729","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","plat-stm: separate sections\n\nPuts functions and data into separate sections\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>\nTested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)","Jens Wiklander",false],["5f1d1af5789dece7af8048643334b7716145bbd9","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","provide hash_sha256_check()\n\nAdds hash_sha256_check() to the tee_crypt_provider interface to be\nused by pager and early initialization code where the complete crypto\nlibrary might not be available.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["6d6ea54c181e3e01ae3a9cc056095b33704b2990","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","separate .rodata sections\n\nPuts each .rodata in a file specific .rodata section\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["d6d47ed9befef3b6c6d6a5e19903a7dd0358aa74","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: clear junk in UL1 table\n\nClears junk in UL1 translation table when setting mapping for a TA in\ntee_mmu_set_ctx().\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>\nTested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)\nTested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt)","Jens Wiklander",false],["467cf45c9e7e5c5d651837ca10f219fe7f008217","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","plat-vexpress: Clean D-cache on reset_primary exit\n\nCleans and invalidates D-cache when primary CPU has initialized\nand is ready to exit to normal world.\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["8f7de3fc92dbdfdc217b83403c64abc0bafb5d31","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","plat-vexpress: linking supports pagable tee.bin\n\n* Adds scripts to create a pagable tee.bin\n* Updates link script and link.mk to support pagable tee.bin\n* Binary format of tee.bin is changed from a raw format to a header\n  followed by the binary data as described by the header. This requires\n  updates in ARM-TF OP-TEE Dispatcher and QEMU virt bios.\n\nfvp:\n* Changes OP-TEE load address to start of TZDRAM_BASE\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["7de955b38ae4c4a572843f3a2893514d6cd57e6b","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","arm32: paging of TEE Core optionally enabled\n\nplat-vexpress-*:\n* Optionally enable paging with CFG_WITH_PAGER=y\n* Uses fake SRAM when paging is enabled\n* Supports partitioning OP-TEE binary in unpaged, init and pagable areas\n\nplat-stm:\n* Displays an error message if compiled with CFG_WITH_PAGER=y\n\narm32:\n* Replaces legacy paging support with new paging support\n* Removes unused tee_pager_unpg.c\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nTested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>\nTested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform - Check the code without the pager is not broken).","Jens Wiklander",false],["b2e89f4322e20381270d32d36a0f967bfa62aeea","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","travis: Add CFG_WITH_PAGER=1 to qemu_virt\n\nAdds CFG_WITH_PAGER=1 compilation for PLATFORM=vexpress-qemu_virt\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["e3850c5efae989f806f1bf6f4cfb326ce7e1c996","7706914404370d7502c27a0eff493dcf491feb51@linaro.org","New stable commits for the setup cripts\n\nSets new stable commits for the FVP and QEMU setup scripts\n\nSigned-off-by: Jens Wiklander <jens.wiklander@linaro.org>\nReviewed-by: Pascal Brand <pascal.brand@linaro.org>","Jens Wiklander",false],["1d06e9717e4157c016f3992d4f5451d59fc1a023","0b55292d2562685bad4ce52d64f802e8f1cd299e@st.com","Shared memory documentation\n\nSigned-off-by: Pascal Brand <pascal.brand@st.com>\nReviewed-by: Joakim Bech <joakim.bech@linaro.org>\nReviewed-by: Jerome Forissier <jerome.forissier@linaro.org>\nReviewed-by: Jens Wiklander <jens.wiklander@linaro.org>","Pascal Brand",false]],"size":21,"ref":"refs/heads/concat-kdf","head":"25c6a74dbb477fb0c5f6fd773b5858f0fa716ed3"}