GitHub PushEvent at 2014-12-16 14:18:34
Repository: chromiumos-third_party-coreboot
Actor: mtk09422
Payload: {"shas":[["cda300961653a23d46913f2667d01a39f0eeaec5","5db40003354dc1c142019712d90bc051b3fe1c17@intel.com","Broadwell FSP: Successful execution of SiliconInit\n\nAdd support to call FspSiliconInit\n\nBRANCH=none\nBUG=None\nTEST=Use the following steps to reproduce:\n1.  Get the private FSP parts\n2.  Copy configs/config.samus.fsp to configs/config.samus\n3.  Build and run on Samus\n4.  After power on, POST code should be 0x35 if successful, hangs in\n    src/soc/intel/broadwell/romstage/romstage.c/romstage_after_car\n\nChange-Id: I80363425df97bf1f1f9b9180f2fd4c625125d33e\nSigned-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>\nReviewed-on: https://chromium-review.googlesource.com/232383\nReviewed-by: Duncan Laurie <dlaurie@chromium.org>\nCommit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>\nTested-by: Leroy P Leahy <leroy.p.leahy@intel.com>","Lee Leahy",true],["1511699b84920728c6ff118d7ecbc01d138f55ee","4d12f06cff3725783b352157673a720bc67c4afe@chromium.org","cbfs: Don't compile LZMA code into romstage if it is not needed\n\n16K of BSS scratchpad buffer is no pocket change for some platforms that\nreally need to count every kilobyte in their SRAM stages. This patch\nmakes sure we don't compile LZMA code into the romstage if we don't need\nit because the ramstage is not compressed anyway.\n\nBRANCH=None\nBUG=None\nTEST=Booted Pinky and Blaze. Confirmed that romstage memsz on Pinky is\nway smaller than before.\n\nChange-Id: Icf04971b8ddafa76052135cd0e44977d44d69486\nSigned-off-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: https://chromium-review.googlesource.com/234539\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","Julius Werner",true],["a20c0570361038c0ae406dcb1f4bc657eea120f6","ad27a54b13f1a6e8a707e652f8f32a2f1e0c72dc@codeaurora.org","ipq806x: modify imem layout\n\nWith introduction of uber-sbl SRAM usage pattern is changing, this\nintroduces the new memory layout.\n\nThis patch overlays DDR initialization code with uber-sbl, as uber-sbl\ngoes out of scope as soon as bootblock starts.\n\nA 4K block at offset 0x3f000 added in the comments, this is a shared\nstructure used by different QCA modules.\n\nThis suggested layout is not final, but will allow to move closer to\nthe production image.\n\nBRANCH=storm\nBUG=chrome-os-partner:34161\nTEST=with other patches applied Storm boots all the way to rombase and\n     initializes DRAM.\n\nChange-Id: I927f6ffc524fc8f0effd7b91d3f5d1e8d6be1530\nSigned-off-by: Deepa Dinamani <deepad@codeaurora.org>\nSigned-off-by: Vadim Bendebury <vbendeb@chromium.org>\nReviewed-on: https://chromium-review.googlesource.com/229023","Deepa Dinamani",true],["48847ab8acfbe4b33d61d3d012c72c025cd8f364","5515d6d2d0829cbe0dd0dcf2094aaded06d58514@chromium.org","storm: prepare to enabling Vboot2\n\nThis change adds to makefiles sources necessary for VBOOT2 verstage\nwithout actually enabling verstage yet.\n\nBRANCH=storm\nBUG=chrome-os-partner:34161\nTEST=not much testing yet, just successful compilation.\n\nChange-Id: I1d7944e681f8a4b113a90ac028a0faba4423be89\nSigned-off-by: Vadim Bendebury <vbendeb@chromium.org>\nReviewed-on: https://chromium-review.googlesource.com/234643","Vadim Bendebury",true],["eab1835c81490670940ec2c88a0142cd97ff2ab0","70662b43bc1a20b57ded72a2b08be88dd0da4841@chromium.org","broadwell: Add 306D4 microcode 0x18\n\nLatest released microcode for F0 stepping.\n\nBUG=chrome-os-partner:28234\nBRANCH=samus,auron\nTEST=build and boot on samus\n\nChange-Id: I2386af147fafb6ff079bf05ff4f41273431d5508\nSigned-off-by: Duncan Laurie <dlaurie@chromium.org>\nReviewed-on: https://chromium-review.googlesource.com/235011\nReviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>","Duncan Laurie",true],["ad87bce3bc22aeaf1eeb8827581c7ce6233f7586","5db40003354dc1c142019712d90bc051b3fe1c17@intel.com","Broadwell FSP: Successful execution of FspNotify\n\nCall FspNotify to finish the platform initialization.  Attempts to\nload the payload.\n\nBRANCH=none\nBUG=None\nTEST=Use the following steps to reproduce:\n1.  Get the private FSP parts\n2.  Copy configs/config.samus.fsp to configs/config.samus\n3.  If running on a non-samus board, in\n    src/mainboard/google/samus/Kconfig:\n    a.  Comment out select EC_GOOGLE_CHROMEEC\n    b.  Comment out select EC_SOFTWARE_SYNC\n4.  If running on a non-samus board, in\n    src/mainboard/google/samus/spd/spd.c comment out the check for\n    valid SPD data at the end of the file\n5.  Build and run on Samus\n6.  Test successful if the code attempts to load the payload\n\nChange-Id: I007bd5481e532e14dca3f158b8eb1d8cb4dc3f47\nSigned-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>\nReviewed-on: https://chromium-review.googlesource.com/232874\nReviewed-by: Duncan Laurie <dlaurie@chromium.org>\nCommit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>\nTested-by: Leroy P Leahy <leroy.p.leahy@intel.com>","Lee Leahy",true],["99bb8a3211efab8b4ecf8e8e7382b4bd767810e1","5db40003354dc1c142019712d90bc051b3fe1c17@intel.com","FSP: Properly display the FSP HOB List pointer in the tables\n\nDefine the signature for the FSP HOB list pointer and add it to the\ntable parser.\n\nBRANCH=none\nBUG=None\nTEST=Use the following steps to reproduce:\n1.  Get the private FSP parts\n2.  Copy configs/config.samus.fsp to configs/config.samus\n3.  Build and run on Samus\n4.  Test successful if the code attempts to load the payload\n\nChange-Id: I3e340289b0ba560147d9766583a82b783adb1605\nSigned-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>\nReviewed-on: https://chromium-review.googlesource.com/234525\nReviewed-by: Duncan Laurie <dlaurie@chromium.org>\nCommit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>\nTested-by: Leroy P Leahy <leroy.p.leahy@intel.com>","Lee Leahy",true],["5d7cb52b2c2dcb2fff0bf83fc168439dade4b1b7","4d12f06cff3725783b352157673a720bc67c4afe@chromium.org","veyron: Trigger hard reset (via GPIO) if last reboot was caused by watchdog\n\nLike Nyan, Veyron boards use a GPIO to reset the system so that we can\nmake the accompanying TPM reset secure and unforgeable. The normal\nkernel reboot driver knows that, but the SoC-internal watchdog doesn't.\n\nThis patch implements a check for the global reset status register in\nthe early bootblock and triggers a hard_reset() when it matches \"first\nglobal watchdog reset\" or \"second global watchdog reset\". Seems that\nthe difference between the two is is a choice controlled by\nwdt_glb_srst_ctrl (unconfirmed), and we want this code to run in both\ncases.\n\nBRANCH=None\nBUG=chrome-os-partner:33141\nTEST=Run 'mem w 0xff800000 0x9' from the command line, watch how you end\nup in recovery without this patch but can boot normally with it.\n\nChange-Id: I2581bde84f0445c15896060544e9acb60de91c8c\nSigned-off-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: https://chromium-review.googlesource.com/231734\nReviewed-by: David Hendricks <dhendrix@chromium.org>","Julius Werner",true],["be3c79b87b81563f744eb885708a52730debaccb","70662b43bc1a20b57ded72a2b08be88dd0da4841@chromium.org","broadwell: Fixes for _SWS support\n\n- These should be 64bit values so when they try to return -1\nit is interpreted properly by the kernel.\n- The GPE value needs to be reset at the start so it does not\nreturn stale data from a previous resume.\n- If a GPE register is zero the value should only be updated\nif it has not yet found a set bit.\n\nBUG=chrome-os-partner:34532\nBRANCH=samus,auron\nTEST=build and boot on samus, suspend/resume with various\nwake sources and ensure the reported _SWS values are correct\nin every case.\n\nChange-Id: Ic6897f20ad2f321f3566694c032b75a3db120556\nSigned-off-by: Duncan Laurie <dlaurie@chromium.org>\nReviewed-on: https://chromium-review.googlesource.com/235012\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","Duncan Laurie",true],["a7ab7225e3419a0fd93894dbb9a959390f29945b","a282a956b2e1198cab1ef264ca97875a5a478d39@nvidia.com","ryu: display: Split dc functions from dsi display code\n\ndc supporting functions can be used for other than dsi display\ninterfaces. This change is preparing for supporting sor display\ninterface.\n\nBUG=chrome-os-partner:34336\nBRANCH=none\nTEST=build ryu and test dev/rec mode, also build rush ok\n\nChange-Id: Id14cbd89457cb91c23526927a432f4eb7cc6291b\nSigned-off-by: Jimmy Zhang <jimmzhang@nvidia.com>\nReviewed-on: https://chromium-review.googlesource.com/234270\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","Jimmy Zhang",true],["36be6b2e35c6246d5384d71b9ab9d4ddbf17764a","a282a956b2e1198cab1ef264ca97875a5a478d39@nvidia.com","ryu: display: Move display api to mainboard\n\nDisplay configuration is board specific. The change here is preparing\nfor supporting other than dsi interface.\n\nBUG=chrome-os-partner:34336\nBRANCH=none\nTEST=build ryu and test dev/rec mode, also build rush ok\n\nChange-Id: I494a04f7d6c0dbad2d472f4c2cd0aabfb23b8c97\nSigned-off-by: Jimmy Zhang <jimmzhang@nvidia.com>\nReviewed-on: https://chromium-review.googlesource.com/234271\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","Jimmy Zhang",true],["7133dfcd1afa221be92c6398221cf210d9eddf17","a282a956b2e1198cab1ef264ca97875a5a478d39@nvidia.com","ryu: Add and select DO_DSI_INIT config option\n\nEnable display supporting functions by select DO_DSI_INIT\n\nBUG=chrome-os-partner:34336\nBRANCH=none\nTEST=build ryu and rush\n\nChange-Id: I3a9f93107333ebf83ff235eb1b1e02fc747df3c6\nSigned-off-by: Jimmy Zhang <jimmzhang@nvidia.com>\nReviewed-on: https://chromium-review.googlesource.com/234272\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","Jimmy Zhang",true],["31492f51c030aeb7a3ac792a02665642ec999405","a282a956b2e1198cab1ef264ca97875a5a478d39@nvidia.com","rush: Add and select DO_SOR_INIT config option\n\nSelect DO_SOR_INIT to enable dp display api\n\nBUG=chrome-os-partner:34336\nBRANCH=none\nTEST=build rush\n\nSigned-off-by: Jimmy Zhang <jimmzhang@nvidia.com>\n\nChange-Id: I4daca43239235ca6d233c4457096d3b98fcaf65c\nReviewed-on: https://chromium-review.googlesource.com/234274\nTested-by: Jimmy Zhang <jimmzhang@nvidia.com>\nReviewed-by: Aaron Durbin <adurbin@chromium.org>\nCommit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>","Jimmy Zhang",true],["4b5515bd00b76332748e4181cdf984c98a83993a","6be5c96c464778f89679b1062a2e0a6af93d2aa5@google.com","panther/beltino/jecht: Fix pointer related errors in lan code\n\nBUG=None\nBRANCH=None\nTEST=Compiles and boots to \"starting kernel\" on panther\n\nChange-Id: I2f890871ad7cddaf132a0fa59a93f05c51d0c00e\nSigned-off-by: Furquan Shaikh <furquan@google.com>\nReviewed-on: https://chromium-review.googlesource.com/234982\nReviewed-by: Aaron Durbin <adurbin@chromium.org>\nTested-by: Furquan Shaikh <furquan@chromium.org>\nCommit-Queue: Furquan Shaikh <furquan@chromium.org>","Furquan Shaikh",true],["2ff7f65134dcf97f97757750eab41dcf8c7765d3","c9fe3c0450a180d111405ace687410d20d0d0895@rock-chips.com","veyron: move backlight gpio control to mainboard.c\n\nwe use the devicetree to pass the backlight control gpio before,\nbut if there have different board version, and use different\nio to control backlight, it will hard to distinguish it. so we\nmove the backlight control to mainboard, and we can through board_id\nto distinguish the backlight control.\n\nBUG=None\nTEST=emerge veyron_pinky and Boot the pinky board\nBRANCH=None\n\nChange-Id: I1ec8e04f4982c3a8c7e31d8dc2c75311b7199ffc\nSigned-off-by: huang lin <hl@rock-chips.com>\nReviewed-on: https://chromium-review.googlesource.com/234711\nReviewed-by: Julius Werner <jwerner@chromium.org>","huang lin",true],["66069927618924af02a4e17503fa49ae2c31fdfc","c9fe3c0450a180d111405ace687410d20d0d0895@rock-chips.com","veyron: support pinky4 hardware\n\nBUG=None\nTEST=emerge veyron_pinky and Boot the pinky board\nBRANCH=None\n\nChange-Id: I06242ade0cabbba56b16b3832a1b4b09bec6f06b\nSigned-off-by: huang lin <hl@rock-chips.com>\nReviewed-on: https://chromium-review.googlesource.com/234712\nReviewed-by: Julius Werner <jwerner@chromium.org>","huang lin",true],["6a061072860f74874f0098062806c01bdcb447bd","c9fe3c0450a180d111405ace687410d20d0d0895@rock-chips.com","veyron: support jerry3 hardware\n\nBUG=None\nTEST=emerge veyron_jerry and Boot the jerry board\nBRANCH=None\n\nChange-Id: I6eb0900516bcd95159c472749c54d356448d2344\nSigned-off-by: huang lin <hl@rock-chips.com>\nReviewed-on: https://chromium-review.googlesource.com/234713\nReviewed-by: Julius Werner <jwerner@chromium.org>","huang lin",true],["49366e5bb3ecdec38c898c936392e5d77a91cd53","c9fe3c0450a180d111405ace687410d20d0d0895@rock-chips.com","veyron: support mighty1 hardware\n\nBUG=None\nTEST=emerge veyron_mighty and Boot the mighty board\nBRANCH=None\n\nChange-Id: I3fcdc837e8d7e62c145850f549662d8260aa1120\nSigned-off-by: huang lin <hl@rock-chips.com>\nReviewed-on: https://chromium-review.googlesource.com/234714\nReviewed-by: Julius Werner <jwerner@chromium.org>","huang lin",true],["1aeb0dc0d323c5f8db7420ed218442a8de1ff4bf","4823cef9c77b3997aeafd408a373a4ac2a720f54@mediatek.com","Add initial Google/Llama board\n\nChange-Id: Ie2cb19787b2a04890f66306da0c51ad894e99e1b","Yidi Lin",true],["5939dfd5da9db1fbf56d0d58a1ae96ce8e7cb3d1","4823cef9c77b3997aeafd408a373a4ac2a720f54@mediatek.com","llama: Add MediaTek Timer driver\n\nChange-Id: Iec8a09340976142abc45068738578ba8f9986e08","Yidi Lin",true]],"size":51,"ref":"refs/heads/tot-dev","head":"3c517c2fc341c106dde5228a7001f60bc4b8346c"}