GitHub PushEvent at 2014-05-28 10:39:51
Repository: linux-pm
Actor: t-kristo
Payload: {"shas":[["a6fe3771d389cc660933509b7dfb945c596636f5","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: DPLL: simplify autoidle register detection logic\n\nAMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s\ndon't have autoidle register. Remove the bit-field value as it is unused,\nalso drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init,\nas we can just simply check against the contents of the autoidle_mask.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["aa76fcf473f6bfa839f37f77b6fdb71f0fb88d8f","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: DPLL: add support for omap2 core dpll\n\nOMAP2 has slightly different DPLL compared to later OMAP generations.\nThis patch adds support for the ti,omap2-dpll-core-clock and also adds\nthe bindings documentation.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["4d008589e271e28eae728eef7f5fb1f658f12b9f","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: APLL: add support for omap2 aplls\n\nThis patch adds support for omap2 type aplls, which have gating and\nautoidle functionality.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["9fa160cb9f2f51ef8274df7b4f390edf6ae491c3","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: gate: fixed DT binding documentation bugs\n\nti,composite-gate-clock documentation was missing, also the register\noffset examples were wrong.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["de742570745e12b53c70130ace958f2a60044000","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: interface: add support for omap2430 specific interface clock\n\nOMAP2430 I2CHS modules require specific hardware ops to be used, so added\na new compatible string for this.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["be67c3bf382c591d8267e0ef12d80041854731d9","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: OMAP2: add clock init support\n\nAdds support for registering the alias clocks, boot time clock-enable list\nand disabling autoidle of clocks.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["61f25ca76ccc7b63371a7a6b0b8b9a8a46745b79","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","ARM: OMAP2: clock: add DT boot support for cpufreq_ck\n\nThe clock and clkdev for this are added manually.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["b3654d703de2ddf5651d2fa959879d586e685376","060a12f1fbc7e2e5d830b72f402ff04fdae8d312@ti.com","CLK: TI: gate: add composite interface clock to OMAP2 only build\n\nComposite interface clock is needed by OMAP2, but it was only built\nin for OMAP3. Fixed the conditional build flag checks for this.\n\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Tero Kristo",true],["0cccd9190009aa6c037aa88a85f2a1b72a6a7963","e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com","ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock\n\nTo allign the name with the other atl clock names:\natlclkin3_ck -> atl_clkin3_ck\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Peter Ujfalusi",true],["2d5e447914722f3c79103ad54baa1170661ac553","e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com","dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings\n\nAudio Tracking Logic is designed to be used by HD Radio applications to\nsynchronize the audio output clocks to the baseband clock. ATL can be also\nused to track errors between two reference clocks (BWS, AWS) and generate a modulated\nclock output which averages to some desired frequency.\nIn essence ATL is generating a clock to be used by an audio codec and also\nto be used by the SoC as MCLK.\n\nTo be able to integrate the ATL provided clocks to the clock tree we need\ntwo types of DT binding:\n- DT clock nodes to represent the ATL clocks towards the CCF\n- binding for the ATL IP itself which is going to handle the hw\n  configuration\n\nThe reason for this type of setup is that ATL itself is a separate device\nin the SoC, it has it's own address space and clock domain. Other IPs can\nuse the ATL generated clock as their functional clock (McASPs for example)\nand external components like audio codecs can also use the very same clock\nas their MCLK.\n\nThe ATL IP in DRA7 contains 4 ATL instences.\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Peter Ujfalusi",true],["9ac33b0ce81fa48dd39e7ddfc1bf4519052181dd","e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com","CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)\n\nAudio Tracking Logic is designed to be used by HD Radio applications to\nsynchronize the audio output clocks to the baseband clock. ATL can be also\nused to track errors between two reference clocks (BWS, AWS) and generate a modulated\nclock output which averages to some desired frequency.\nIn essence ATL is generating a clock to be used by an audio codec and also\nto be used by the SoC as MCLK.\n\nTo be able to integrate the ATL provided clocks to the clock tree we need\ntwo types of DT binding:\n- DT clock nodes to represent the ATL clocks towards the CCF\n- binding for the ATL IP itself which is going to handle the hw\n  configuration\n\nThe reason for this type of setup is that ATL itself is a separate device\nin the SoC, it has it's own address space and clock domain. Other IPs can\nuse the ATL generated clock as their functional clock (McASPs for example)\nand external components like audio codecs can also use the very same clock\nas their MCLK.\n\nThe ATL IP in DRA7 contains 4 ATL instences.\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Peter Ujfalusi",true],["ceb5260bb2ac62a77c8f902c93baa7c39d60ef97","e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com","ARM: dts: dra7/dra7xx-clocks: ATL related changes\n\nModify the clock nodes for the ATL clocks to use the ATL clock driver to\nhandle them.\n\nAdd the ATL device node at the same time for DRA7.\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Peter Ujfalusi",true],["1484ba8bc57115f574a3ff685c90058bc40d09a8","bc6adb8bd543cd78cbfd19863ccab4daed541014@ti.com","ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)\n\nDuty Cycle Correction(DCC) needs to be enabled if the MPU is to run at\nfrequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x.\n\nMPU DPLL has a limitation on the maximum frequency it can be locked\nat. Duty Cycle Correction circuit is used to recover a correct duty\ncycle for achieving higher frequencies (hardware internally switches\noutput to M3 output(CLKOUTHIF) from M2 output (CLKOUT)).\n\nFor further information, See the note on OMAP5432 Technical Reference\nManual(SWPU282U) chapter 3.6.3.3.1 \"DPLLs Output Clocks Parameters\",\nand also the \"OMAP543x ES2.0 DM Operating Conditions Addendum v0.5\"\nchapter 2.1 \"Micro Processor Unit (MPU)\". Equivalent information is\npresent in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P).\n\nSigned-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>\nSigned-off-by: Taras Kondratiuk <taras@ti.com>\nSigned-off-by: J Keerthy <j-keerthy@ti.com>\nSigned-off-by: Nishanth Menon <nm@ti.com>\n[t-kristo@ti.com: added TRM / DM references for DCC clock rate]\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Andrii Tseglytskyi",true],["87ac34dbb06d167d641124dda5c4160a441f3351","50c3c575ce2bb12c45e20736ce59e86fe81915b4@ti.com","CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies\n\nMPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum\nfrequency it can be locked at. Duty Cycle Correction circuit is used\nto recover a correct duty cycle for achieving higher frequencies\n(hardware internally switches output to M3 output(CLKOUTHIF) from M2\noutput (CLKOUT)).\n\nSo provide support to setup required data to handle Duty cycle by\nthe setting up the minimum frequency for DPLL. 1.4GHz is common\nfor all these devices and is based on Technical Reference Manual\ninformation for OMAP5432((SWPU282U) chapter 3.6.3.3.1 \"DPLLs Output\nClocks Parameters\", and equivalent information from DRA75x, DRA72x\ndocumentation(SPRUHP2E, SPRUHI2P).\n\nSigned-off-by: Nishanth Menon <nm@ti.com>\n[t-kristo@ti.com: updated for latest dpll init API call]\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Nishanth Menon",true],["1fb118f8fde12719814c22c5a26ee7ab920f179e","50c3c575ce2bb12c45e20736ce59e86fe81915b4@ti.com","ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies\n\nOMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle\nCorrection(DCC) to operate safely at frequencies >= 1.4GHz.\n\nSwitch to \"ti,omap5-mpu-dpll-clock\" compatible property which provides\nthis support.\n\nSigned-off-by: Nishanth Menon <nm@ti.com>\nSigned-off-by: Tero Kristo <t-kristo@ti.com>","Nishanth Menon",true]],"size":15,"ref":"refs/heads/for-v3.16/ti-clk-drv","head":"1fb118f8fde12719814c22c5a26ee7ab920f179e"}