ARM: kernel: update cpu_suspend code to use cache LoUIS operations

In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.

When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced cache LoUIS function.

The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.

outer_cache management remains unchanged.

Change-Id: Id5a6d34d55d1b0a5ef112cafc3ad21c0da4b0b84
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
ARM: Use -mcpu=cortex-a15 when targeting MSM Krait CPUs

Enable compiler optimizations specific to the Cortex-A15
processor when targeting MSM Krait CPUs. This is necessary
take advantage of the UDIV/SDIV instructions supported by
these processors. To accomplish this, we need to remove the
-march=armv7-a ISA restriction from the compiler options
because 'cortex-a15' is a superset of 'armv7-a'.

Change-Id: I6215aecc11fb4f77c971de7b84f68649ef234357
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm: kgsl: Fix several possible problem spots in the dispatcher

Fix a few spots that the compiler warnings missed. Avoid
dereferencing a pointer that may have returned ERR_PTR() without
first checking to see that if it did return ERR_PTR() and correct
an egregious signed / unsigned mixup. Not sure why the compiler
didn't yell at me for that one.

Change-Id: Ic0dedbadf075b34e51a89ce625d2308c5171a58d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
gpu: msm: Sync with CodeAurora kk_3.5_rb1.15

Change-Id: I3b75d2d4d1aa0d5d14f57a70de2ee19068bab9b0
iommu: msm: Refactor remote spinlock defconfig

Refactor the remote spinlock defconfig to allow it to be used with
subsystems other than GPU. This will enhance the usability of this
feature and minimize the chance of errors when enabling this feature.

CRs-fixed: 517873
Change-Id: I609cd77ece4e8d2e15e1a24d87a23be05a61b60f
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
iommu: msm: Refactor use of remote spinlock

The remote spinlock was originally meant to synchronize access between
GPU and CPU accessing SMMU. However, there are more use cases that
this remote spinlock serves. This change decouples the spinlock from
GPU and adds support for taking the spinlock only for SMMUs that are
specified in the device tree.

CRs-fixed: 517873
Change-Id: Ic50992d0d1a102fbd05855e09e254e627f99ec33
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
iommu: msm: Handle unmapping of PTE properly

The unmap api is currently not handling unmapping of page table
entries (PTE) properly. The generic function that calls the msm
unmap API expects the unmap call to unmap as much as possible
and then return the amount that was unmapped.
In addition the unmap function does not support an arbitrary input
length. However, the function that calls the msm unmap function
assumes that this is supported.

Both these issues can cause mappings to not be unmapped which will
cause subsequent mappings to fail because the mapping already exists.

Change-Id: I638d5c38673abe297a701de9b7209c962564e1f1
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
iommu: msm: Refactor page table code

Move code that is specific to short descriptor page table
format to its own file to allow sharing of header file
between long descriptor format page table and short descriptor
page table format.

Change-Id: Ia072a77a23d21207edb983de47b6fe69029ffdd7
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
msm: kgsl: Restrict the maximum memory entries for bulk cache sync

Restrict the maximum number of memory entries that can be specified
to a single bulk cache sync call to PAGE_SIZE / sizeof(unsigned int)
so that the allocation can always fit within one page.

CRs-fixed: 578062
Change-Id: Ic0dedbad07e1986cd6ccc5b260ffef82b5adb6d3
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: Don't enable VBIF counters for targets that don't use them

Only targets with separate bus control need the VBIF counters enabled
by default.

Change-Id: I3a7fcedebf7a7cc80bc1bec5a7fd298b49b9b165
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
cpufreq: ondemand: Disable freq sync feature in store_powersave_bias

Turn off frequency synchronization of CPUs on thread migrations
when powersave bias is enabled. This is done to prevent re-arming
of the dbs timer work (which is cancelled by store_powersave_bias)
by the sync_thread.

Change-Id: I165dd591845c1d66d01a14e8dfc44c767c677b0d
Signed-off-by: Rohit Gupta <rohgup@codeaurora.org>
cpufreq: ondemand: fix timer-related list corruption in store_powersave_bias()

The dbs_timer_init() call in store_powersave_bias() re-initializes the
dbs_info workqueue, call on dbs_timer_exit() to ensure
outstanding work is cleared prior to making this call. Also, grab the
percpu timer_mutex lock to avoid race conditions with respect to the
dbs timer.

Change-Id: I79f3d43eeb51d2d8e21edd0fe043d6583333951f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
ondemand: add sysfs entry for down_diff_multi_core

This change adds sysfs entry for the ondemand governor's attribute
down_differential_multi_core. This is required to be able to program
this knob to attain better perf/power for use cases like camcorder.

CRs-fixed: 561456
Change-Id: Ib7c1223215c6b714c286c231ed37f3abfae741c6
Signed-off-by: Krishna Vanka <kvanka@codeaurora.org>
PM: devfreq: Fix the fast ramp case in the adreno governor

Expected behavior of GPU DCVS is to immediately bump the frequency
to turbo upon encountering a long block of busy processing.  The
current code just raises the frequency by one level.

Change-Id: Ida953bb7be8a976da5400328a1c91083499e0fa0
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
mm: change freepage state correctly in __isolate_free_page

Commit 2e30abd1730751d58463d88bc0844ab8fd7112a9
(mm: cma: skip watermarks check for already isolated blocks
in split_free_page()) changed the ordering of where the watermark
checks go for isolated pages. There was already an 'enhancement'
present in __isolate_free_page to skip the watermark checks for
CMA pages to increase success. The merging of the enhancment and
the aforementioned commit was done incorrectly, resulting in
the free page state never being modified for CMA pages even if
the CMA page was removed from the free list. Add the enhancement
properly by only checking for CMA pages at the watermark level
and allow the page state to be modfied for CMA pages as well.

Change-Id: Iabea982108d98150f54e5c42b7dbf30f0743653a
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
cpufreq: interactive: Modifying sync_freq implementation

1. Check for up_threshold_any_cpu_freq instead of sync_freq to
   boost the frequency to sync_freq.
2. Change the load threshold name from sync_freq_load_threshold to
   up_threshold_any_cpu_load
3. Do not consider CPUs with load less than up_threshold_any_cpu_load
   while evaluating max load across CPUs

Change-Id: Ia0e537edbf38a5006c1a22f5c472daa0d086ffc9
Signed-off-by: Rohit Gupta <rohgup@codeaurora.org>
cpufreq: interactive: Use default min_sample_time if SDF is zero

Use min_sample_time to step down from max frequencies if
sampling_down_factor is set to zero.

Change-Id: I2e89bef6220557cb95efd20d658e0c05753b4c3c
Signed-off-by: Rohit Gupta <rohgup@codeaurora.org>
gpu: ion: Add pooling of CMA allocations

CMA provides excellent memory utilization but at the cost of
being much slower than permanently reserving the memory. Most
clients of this memory end up needing to do allocations on the
fast path. These clients may be aware of allocations on the slow
path but may not be able to actually make those allocations until
the fast path. Add support for pooling CMA allocations and allowing
prefetching into the heap. This memory may be stored until either
allocated/freed or drained via a shrinker.

Change-Id: I2f15bc9c72e5f79ffa6edbeb454fd41121efd8fc
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
gpu: ion: Add ioctls for prefetching/draining pools

Multiple heaps in Ion are begining to pool large amounts of memory.
This gives a boost on average but clients may still take a hit
if the pool needs to be filled up again. Add an ioctl to give a
'hint' to add memory to the pool. Equivalently, add an ioctl to
drain some of the memory out of the pool to ennsure the memory
isn't hanging around for too long.

Change-Id: I2974322caa1520fd199d9cf2658f2fafceffb65c
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
gpu: ion: Add support for heap walking

Clients may wish to implement custom functions on a particular
heap ID. Add a generic interface to walk all the heaps available
and call a function on the particular heap ID.

Change-Id: I8b3de7a2de74cd9ea1873020ed00ee40100ce923
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>