GitHub PushEvent at 2014-10-10 10:50:04
Repository: Ghost-Kernel-GS4-LTE
Actor: Ghost44
Payload: {"shas":[["47d0c12a0d3f42d67b4c498110a1b9c83131fef4","b07d7e22a002c36e256b78f51f1f0db608e62a13@arm.com","ARM: mm: implement LoUIS API for cache maintenance ops\n\nARM v7 architecture introduced the concept of cache levels and related\ncontrol registers. New processors like A7 and A15 embed an L2 unified\ncache\ncontroller that becomes part of the cache level hierarchy. Some\noperations in\nthe kernel like cpu_suspend and __cpu_disable do not require a flush of\nthe\nentire cache hierarchy to DRAM but just the cache levels belonging to\nthe\nLevel of Unification Inner Shareable (LoUIS), which in most of ARM v7\nsystems\ncorrespond to L1.\n\nThe current cache flushing API used in cpu_suspend and __cpu_disable,\nflush_cache_all(), ends up flushing the whole cache hierarchy since for\nv7 it cleans and invalidates all cache levels up to Level of Coherency\n(LoC) which cripples system performance when used in hot paths like\nhotplug\nand cpuidle.\n\nTherefore a new kernel cache maintenance API must be added to cope with\nlatest ARM system requirements.\n\nThis patch adds flush_cache_louis() to the ARM kernel cache maintenance\nAPI.\n\nThis function cleans and invalidates all data cache levels up to the\nLevel of Unification Inner Shareable (LoUIS) and invalidates the\ninstruction\ncache for processors that support it (> v7).\n\nThis patch also creates an alias of the cache LoUIS function to\nflush_kern_all\nfor all processor versions prior to v7, so that the current cache\nflushing\nbehaviour is unchanged for those processors.\n\nv7 cache maintenance code implements a cache LoUIS function that cleans\nand\ninvalidates the D-cache up to LoUIS and invalidates the I-cache,\naccording\nto the new API.\n\nReviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>\n\nConflicts:\n\tarch/arm/mm/cache-v7.S","Lorenzo Pieralisi",true]],"size":1,"ref":"refs/heads/master","head":"47d0c12a0d3f42d67b4c498110a1b9c83131fef4"}