GitHub PushEvent at 2014-09-08 12:29:21
Repository: ntb
Actor: jonmason
Payload: {"shas":[["82e88bd0e30d0a10cc3cefc4cf4efdb24b46d960","7a72b0ecdf501e4593e842e1a61bf3d5b53699e6@intel.com","ntb: Add alignment check to meet hardware requirement\n\nThe NTB translate register must have the value to be BAR size aligned.\nThis alignment check make sure that the DMA memory allocated has the\nproper alignment. Another requirement for NTB to function properly with\nmemory window BAR size greater or equal to 4M is to use the CMA feature\nin 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and\nCONFIG_CMA_SIZE_MBYTES set.\n\nSigned-off-by: Dave Jiang <dave.jiang@intel.com>\nSigned-off-by: Jon Mason <jdmason@kudzu.us>","Dave Jiang",false],["9c10080792c194958a61370e14f5fda4cb7c6908","c00e29b121b94e623b1edbe38acdfe98ec7dc407@intel.com","NTB: debugfs device entry\n\nCreate a debugfs entry for the NTB device to log the basic device info,\nas well as display the error count on a number of registers.\n\nSigned-off-by: Jon Mason <jon.mason@intel.com>","Jon Mason",false],["58e41d1e730cadcd166bb548ad71cbf1f62a8c67","7a72b0ecdf501e4593e842e1a61bf3d5b53699e6@intel.com","ntb: move platform detection to separate function\n\nMove the platform detection function to separate functions to allow\neasier maintenence.\n\nSigned-off-by: Dave Jiang <dave.jiang@intel.com>\nSigned-off-by: Jon Mason <jdmason@kudzu.us>","Dave Jiang",false],["51bac5a101dbc99cfa93bd6b43bf145ff10fe4cf","7a72b0ecdf501e4593e842e1a61bf3d5b53699e6@intel.com","ntb: conslidate reading of PPD to move platform detection earlier\n\nTo simplify some of the platform detection code. Move the platform detection\nto a function to be called earlier.\n\nSigned-off-by: Dave Jiang <dave.jiang@intel.com>\nSigned-off-by: Jon Mason <jdmason@kudzu.us>","Dave Jiang",false],["144812d01149570000a074a86caa53578a42993b","7a72b0ecdf501e4593e842e1a61bf3d5b53699e6@intel.com","ntb: use errata flag set via DID to implement workaround\n\nInstead of using a module parameter, we should detect the errata via\nPCI DID and then set an appropriate flag. This will be used for additional\nerrata later on.\n\nSigned-off-by: Dave Jiang <dave.jiang@intel.com>\nSigned-off-by: Jon Mason <jdmason@kudzu.us>","Dave Jiang",false],["4e3dc80fa74847e9fc60f874ec73700542428ca1","7a72b0ecdf501e4593e842e1a61bf3d5b53699e6@intel.com","ntb: Adding split BAR support for Haswell platforms\n\nOn the Haswell platform, a split BAR option to allow creation of 2\n32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this\nnew option.\n\nSigned-off-by: Dave Jiang <dave.jiang@intel.com>\nSigned-off-by: Jon Mason <jdmason@kudzu.us>","Dave Jiang",false]],"size":6,"ref":"refs/heads/ntb-next","head":"4e3dc80fa74847e9fc60f874ec73700542428ca1"}