GitHub PushEvent at 2014-09-12 13:50:11
Repository: qemu
Actor: lalrae
Payload: {"shas":[["bcd1ef363358ad5966dbea88d5c03e94b99ebe4a","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","target-mips: fix tlb->PFN to contain actual Page Frame Number\n\nThis modification will prevent >32-bits from being truncated in r4k_fill_tlb\ndue to left shift on MIPS32 target.\n\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","Leon Alrae",true],["7d919261ab8e41a88a2c52ffcf32d757cedebee7","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","target-mips: extend EntryLo0/1, LLAddr and TagLo to 64-bits in MIPS32\n\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","Leon Alrae",true],["1dc5be8e44d8b8174528d540ad90aa6376f2ab95","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","target-mips: update tlb->PFN to contain PFN concatenated with PFNX\n\nPFNX is always 0 on a core without large physical address support.\n\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","Leon Alrae",true],["87261692bf84cb5da7548513122e589832b0812b","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","target-mips: add PageGrain.ELPA and use env->PAMask\n\nPageGrain.ELPA enables support for large physical addresses. This field\nis encoded as follows:\n0: Large physical address support is disabled.\n1: Large physical address support is enabled (XPA).\n\nIf this bit is a 1, the following changes occur to coprocessor 0 registers:\n- The PFNX field of the EntryLo0 and EntryLo1 registers is writable and\n  concatenated with the PFN field to form the full page frame number.\n- Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined.\n\nP5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA\nis disabled (PageGrain.ELPA = 0) then assuming 32-bit Address Mode.\n\nLeaving MIPS64 with default 36 PABITS.\n\nenv->PABITS value is constant and indicates maximum PABITS available on a core,\nwhereas env->PAMask is calculated from env->PABITS and is also affected by\nPageGrain.ELPA (in MIPS32 core PABITS >32 are ignored if ELPA is disabled).\n\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","Leon Alrae",true],["a5b6fc1f2c3429a1776b9f155128126fc2f14bfc","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","target-mips: add MTHC0 and MFHC0 for MIPS32\n\nThe MIPS32r5 architecture adds two new instructions for accessing the upper\n32-bits of the selected 64-bit CP0 register.\n\nThe MFHC0 instruction performs a move-from-high Coprocessor 0 operation which\nmoves the contents from the upper 32-bits of a coprocessor 0 register that has\nbeen extended by 32-bits, to a generate purpose register.\n\nThe MTHC0 instruction performs a move-to-high Coprocessor 0 operation which\nmoves the contents of a general register to the upper 32-bits of a coprocessor 0\nregister that has been extended by 32-bits.\n\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","Leon Alrae",true],["b68303a13b7597a21a96e74824e798ab2f34aa2f","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","target-mips: update mips32r5-generic to support XPA\n\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","Leon Alrae",true],["8f5a2c175965542b4f46e9ae0a04ebba7ae23914","50bfc4094b47c321e251ea8976314ff5ead2a436@imgtec.com","Merge pull request #5 from lalrae/xpa-mips32r5\n\nadd XPA feature","Leon Alrae",true]],"size":7,"ref":"refs/heads/p5600-mips32r5-PRIP3","head":"8f5a2c175965542b4f46e9ae0a04ebba7ae23914"}