Reverted revisions 221351, 221352 and 221353.


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[mips][microMIPS] Mark symbols as microMIPS if necessary
Differential Revision: http://reviews.llvm.org/D6039


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221355 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Remove dead code identified by the Clang static analyzer.

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IR: MDNode => Value: NamedMDNode::addOperand()

Change `NamedMDNode::addOperand()` to take a `Value *` instead of an
`MDNode *`.  This is part of PR21433.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221359 91177308-0d34-0410-b5e6-96231b3b80d8
[dfsan] Abort at runtime on indirect calls to uninstrumented vararg functions.

We currently have no infrastructure to support these correctly.

This is accomplished by generating a call to a runtime library function that
aborts at runtime in place of the regular wrapper for such functions. Direct
calls are rewritten in the usual way during traversal of the caller's IR.

We also remove the "split-stack" attribute from such wrappers, as the code
generator cannot currently handle split-stack vararg functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221360 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Remove redundant assignment.

Found by the Clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221366 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement ANDI16 instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221367 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Remove another redundant assignment.

Found by the Clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221368 91177308-0d34-0410-b5e6-96231b3b80d8
ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221369 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] [NFC] Alphabetizing cmake files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221370 91177308-0d34-0410-b5e6-96231b3b80d8
ps][microMIPS] Implement CodeGen support for ANDI16 instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221371 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Remove more dead code.

Dead code identified by the Clang static analyzer.

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IR: MDNode => Value: AsmWriter SlotTracker API

Change `SlotTracker::CreateMetadataSlot()` and
`SlotTracker::getMetadataSlot()` to use `Value` instead of `MDNode`.
Part of PR21433.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221373 91177308-0d34-0410-b5e6-96231b3b80d8
remove extra breaks; NFC


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IR: MDNode => Value: NamedMDNode::getOperator()

Change `NamedMDNode::getOperator()` from returning `MDNode *` to
returning `Value *`.  To reduce boilerplate at some call sites, add a
`getOperatorAsMDNode()` for named metadata that's expected to only
return `MDNode` -- for now, that's everything, but debug node named
metadata (such as llvm.dbg.cu and llvm.dbg.sp) will soon change.  This
is part of PR21433.

Note that there's a follow-up patch to clang for the API change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221375 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add NVPTXLowerStructArgs pass

This works around the limitation that PTX does not allow .param space
loads/stores with arbitrary pointers.

If a function has a by-val struct ptr arg, say foo(%struct.x *byval %d), then
add the following instructions to the first basic block :

%temp = alloca %struct.x, align 8
%tt1 = bitcast %struct.x * %d to i8 *
%tt2 = llvm.nvvm.cvt.gen.to.param %tt2
%tempd = bitcast i8 addrspace(101) * to %struct.x addrspace(101) *
%tv = load %struct.x addrspace(101) * %tempd
store %struct.x %tv, %struct.x * %temp, align 8

The above code allocates some space in the stack and copies the incoming
struct from param space to local space. Then replace all occurences of %d
by %temp.

Fixes PR21465.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221377 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Remove SI_ADDR64_RSRC

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R600/SI: Move all rsrc building functions to SIISelLowering

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R600/SI: Add testcase I forgot to commit from months ago

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[x86 fast-isel] Materialize allocas with the correct-sized lea for ILP32

Summary:
X86FastISel::fastMaterializeAlloca was incorrectly conditioning its
opcode selection on subtarget bitness rather than pointer size.

Differential Revision: http://reviews.llvm.org/D6136

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