Fixed homepage link

The link was pointing to a page that said:

This page has been moved to http://iverilog.icarus.com, you will be forwarded there automatically in 3 seconds.
Please update your links.

So now it's updated
Fixes for GitHub issues 13 and 15.

The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').

I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
Fix for br947.

When performing the initial assignment for a procedural continuous
assignment, any previous continuous assignment to the destination
signal must be unlinked first, otherwise the initial value for the
assignment will propagate to any other nets that are driven by the
original source signal.
Added width cap for unsized expressions.

Unsized expressions can expand to extremely large widths. Usually this
is actually a mistake in the source code, but it can lead to the compiler
temporarily using extremely large amounts of memory, or in the worst
case, crashing. This adds a cap on the width of unsized expressions (by
default 65536 bits, but overridable by the user), and causes a warning
message to be output when the cap is reached.
Fix for GitHub issue #18 : undef propagation of const multiplies is incorrect.

When an expression is elaborated, the compiler converts multiplies with
one constamt zero operand into a constant zero value. This is only valid
if the other operand is not a 4-state variable.
Fix for GitHub issue 19 : incorrect handling of large shift values.

For shift operations evaluated at compile time, the compiler was converting
the right operand to a native unsigned long value. If the operand exceeded
the size of an unsigned long, excess bits were discarded, which could lead
to an incorrect result.

The fix I've chosen is to add an as_unsigned() function to the verinum class
which returns the maximum unsigned value if the internal verinum value is
wider than the native unsigned type. This then naturally gives the correct
result for shifts, as the verinum bit width is also an unsigned value.

I've changed the as_ulong() and as_ulong64() functions to do likewise, as
this is more likely to either give the correct behaviour or to give some
indication that an overflow has occurred where these functions are used.
Fix invalid optimisations in tgt-vvp.

The vvp code generator was optimising away adds and subtracts where one
operand was a constant zero. This is not valid for 4-state arithmetic.
It was also optimising away multiplies by a constant zero - but in this
case getting it wrong and effectively multiplying by 1.
Fix space issue
Remove compile warning
Merge pull request #10 from kiteflyingmonkey/patch-1

Fixed homepage link
More standard handling of unsized numbers as system task arguments.
Merge branch 'master' into vec4-stack

Conflicts:
	netmisc.cc
	tgt-vvp/eval_expr.c
	vvp/vthread.cc