GitHub CreateEvent at 2014-05-09 17:03:11
Repository: MIPS_PipeLine_Simulator
Actor: AkshayRaj
Payload: ref: master
ref_type: branch
master_branch: master
description: This Project simulates the workings of a 4 stage MIPS PipeLine. The Simulator writes the Cycle Number when an instruction leaves a PipeLine Stage. It detects RAW, WAW, WAR and Structural Hazards Accurately. A two level Memory Hierarchy is also implemented in the PipeLine. Cache hits and Misses for both I-Cache and D-Cache are also written on the Scoreboard. 
pusher_type: user