GitHub PushEvent at 2014-03-04 01:08:48
Repository: linux
Actor: gregnietsky
Payload: {"shas":[["5547fec74a566e1f5e00a937b9a367f7c6a94a8b","ff341aa343d564f9e53e9dcb6996be8c04859a66@oracle.com","UBI: fix some use after free bugs\n\nMove the kmem_cache_free() calls down a couple lines.\n\nSigned-off-by: Dan Carpenter <dan.carpenter@oracle.com>\nSigned-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>","Dan Carpenter",true],["07ad6836fa21b8ae1715d5f82a0d28c4140e1e73","1d402fe89ace836b52164ed4c0f247cb6f80efc1@gmail.com","clk: mvebu: armada-370: maintain clock init order\n\nInit order of CLK_OF_DECLARE'd drivers depends on compile order.\nUnfortunately, clk_of_init does not allow drivers to return errors,\ne.g. -EPROBE_DEFER if parent clocks have not been registered, yet.\n\nTo avoid init order woes for MVEBU clock drivers, we take care of\nproper init order ourselves. This patch joins core-clk and gating-clk\ninit to maintain proper init order.\n\nSigned-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\nTested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>\nSigned-off-by: Jason Cooper <jason@lakedaemon.net>","Sebastian Hesselbarth",true],["0a11a6ae94373f37e738f7dc8f51d60a78d78a58","1d402fe89ace836b52164ed4c0f247cb6f80efc1@gmail.com","clk: mvebu: armada-xp: maintain clock init order\n\nInit order of CLK_OF_DECLARE'd drivers depends on compile order.\nUnfortunately, clk_of_init does not allow drivers to return errors,\ne.g. -EPROBE_DEFER if parent clocks have not been registered, yet.\n\nTo avoid init order woes for MVEBU clock drivers, we take care of\nproper init order ourselves. This patch joins core-clk and gating-clk\ninit to maintain proper init order.\n\nSigned-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\nSigned-off-by: Jason Cooper <jason@lakedaemon.net>","Sebastian Hesselbarth",true],["8f7fc5450b64210b08cb3daabb3473dbad197e54","1d402fe89ace836b52164ed4c0f247cb6f80efc1@gmail.com","clk: mvebu: dove: maintain clock init order\n\nInit order of CLK_OF_DECLARE'd drivers depends on compile order.\nUnfortunately, clk_of_init does not allow drivers to return errors,\ne.g. -EPROBE_DEFER if parent clocks have not been registered, yet.\n\nTo avoid init order woes for MVEBU clock drivers, we take care of\nproper init order ourselves. This patch joins core-clk and gating-clk\ninit to maintain proper init order.\n\nSigned-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\nTested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>\nSigned-off-by: Jason Cooper <jason@lakedaemon.net>","Sebastian Hesselbarth",true],["58d516ae95cbf7eed44f85a01cdfad41f17b4197","1d402fe89ace836b52164ed4c0f247cb6f80efc1@gmail.com","clk: mvebu: kirkwood: maintain clock init order\n\nInit order of CLK_OF_DECLARE'd drivers depends on compile order.\nUnfortunately, clk_of_init does not allow drivers to return errors,\ne.g. -EPROBE_DEFER if parent clocks have not been registered, yet.\n\nTo avoid init order woes for MVEBU clock drivers, we take care of\nproper init order ourselves. This patch joins core-clk and gating-clk\ninit to maintain proper init order.\n\nSigned-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\nTested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>\nSigned-off-by: Jason Cooper <jason@lakedaemon.net>","Sebastian Hesselbarth",true],["a65e0c6a7f14d80e87b82959c7333595cbd3e54e","15ad2a232c436ab54d1b78ef06a09c4cd03911f0@ti.com","clk: keystone: gate: fix clk_init_data initialization\n\nThe clk_init_data struct is allocated in the stack. All members of\nthis struct should be initialized before using otherwise it will\nlead to unpredictable situation as it can contain garbage.\n\nUltimately the clk->flag field contains garbage. In my case it leads\nthat flag CLK_IGNORE_UNUSED is set for most of clocks. As result a\nbunch of unused clocks cannot be disabled.\n\nSo initialize flags in this structure too.\n\nCc: Mike Turquette <mturquette@linaro.org>\nSigned-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>\nSigned-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>","Ivan Khoronzhuk",true],["565bbdcd3b91523b4142587c00206302e091a23e","15ad2a232c436ab54d1b78ef06a09c4cd03911f0@ti.com","ARM: keystone: dts: fix clkvcp3 control register address\n\nThe address for control regs in clkvcp3 node is not correct and should\nbe 0x023500a8 instead of 0x0235000a8.\n\nThis lead to few unexpected behaviors while clocks were turned\nof in absence of clk_ignore_unused\n\nMike Turquette <mturquette@linaro.org>\nSigned-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>\nSigned-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>","Ivan Khoronzhuk",true],["6e60163b9db6d0b203ffc0f0b8ef5a5f1c9d3fb8","0bda9a89324ffe2d19adec61a9f1cd9f8c8e45f0@tiscali.nl","drm/tegra: fix typo 'CONFIG_TEGRA_DRM_FBDEV'\n\nSigned-off-by: Paul Bolle <pebolle@tiscali.nl>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","Paul Bolle",true],["89e6e8c85f21555a763d0e47841b515ede6278d1","2a8ffc07e8f57d80a2934ccc3dd1949354d82b2d@gmail.com","gpu: host1x: do not check previously handled gathers\n\nWhen patching gathers, we don't need to check against\ngathers with lower indices than the current one, as\nthey are guaranteed to already have been handled.\n\nSigned-off-by: Erik Faye-Lund <kusmabite@gmail.com>\nAcked-By: Terje Bergstrom <tbergstrom@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","Erik Faye-Lund",true],["b18915379071b31ea819a36ca67761620decba06","18f1b15824e036419a8ac5255848b0e73a0d30b0@gmail.com","drm/tegra: Add guard to avoid double disable/enable of RGB outputs\n\nAdd guard to check whether RGB output is already enabled in the way it's\ndone for HDMI output. Fixes possible hang on trying to disable output twice\n(first time during driver probe and second on fb registering).\n\nSigned-off-by: Dmitry Osipenko <digetx@gmail.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>","Dmitry Osipenko",true],["e9baa9d9d520fb0e24cca671e430689de2d4a4b2","9cd9d802d23c0ed5e224beabf4ae4a5c478746ef@linaro.org","dma: ste_dma40: don't dereference free:d descriptor\n\nIt appears that in the DMA40 driver the DMA tasklet will very\noften dereference memory for a descriptor just free:d from the\nDMA40 slab. Nothing happens because no other part of the driver\nhas yet had a chance to claim this memory, but it's really\nnasty to dereference free:d memory, so let's check the flag\nbefore the descriptor is free and store it in a bool variable.\n\nCc: stable@vger.kernel.org\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Vinod Koul <vinod.koul@intel.com>","Linus Walleij",true],["e306dfd06fcb44d21c80acb8e5a88d55f3d1cf63","8c69ee23f3f44f8162a64d579c1fa25c2f55298a@lixom.net","ARM64: unwind: Fix PC calculation\n\nThe frame PC value in the unwind code used to just take the saved LR\nvalue and use that.  That's incorrect as a stack trace, since it shows\nthe return path stack, not the call path stack.\n\nIn particular, it shows faulty information in case the bl is done as\nthe very last instruction of one label, since the return point will be\nin the next label. That can easily be seen with tail calls to panic(),\nwhich is marked __noreturn and thus doesn't have anything useful after it.\n\nEasiest here is to just correct the unwind code and do a -4, to get the\nactual call site for the backtrace instead of the return site.\n\nSigned-off-by: Olof Johansson <olof@lixom.net>\nCc: stable@vger.kernel.org\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>","Olof Johansson",true],["cb6448ab0a9ac5f1d1c72a0f573dd9677d8e5418","651dda1e35c6fe8f72c3112540c405a2364bcd71@nvidia.com","clk: tegra: Add missing Tegra20 fuse clks\n\nAdd clocks required for accessing fuses on Tegra20.\n\nSigned-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>\nAcked-by: Stephen Warren <swarren@nvidia.com>","Peter De Schrijver",true],["2edf3e035302776e4756e446baf3b6c7b94c3698","b75a4d02013b0e68ae2c6bb0dcfd4b7bec282dc9@gmail.com","clk: tegra: Correct clock number for UARTE\n\nUARTE has clock number 66. Number 65 is the right one for UARTD.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>","Thierry Reding",true],["2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a","5c8aa1266c03186393d9e7b3b4e3b14239af8201@chromium.org","clk: tegra: Fix PLLP rate table\n\nThis table had settings for 216MHz, but PLLP is (and is supposed to be)\nconfigured at 408MHz.  If that table is used and PLLP_BASE_OVRRIDE is\nnot set, the kernel will panic in clk_pll_recalc_rate().\n\nSigned-off-by: Gabe Black <gabeblack@google.com>\nSigned-off-by: Andrew Bresticker <abrestic@chromium.org>","Gabe Black",true],["67fc26bfd7a265883fd0804f24f6287d16769e3d","9c6f026f68ffecc44f215af186ef513cd72b6ce4@nvidia.com","clk: tegra: Fix PLLD mnp table\n\nPLLD was using the same mnp table as PLLP.  Fix it to use its own\ntable which is different from PLLP's.\n\nSigned-off-by: Rhyland Klein <rklein@nvidia.com>\nSigned-off-by: Andrew Bresticker <abrestic@chromium.org>","Rhyland Klein",true],["0e766c2d9fc8cd2ad0e0fe97ff4e264cb686fc32","b43cfbc9cd647d1eac8c11f6bdfd65c37339a21d@nvidia.com","clk: tegra: PLLD2 fixes for hdmi\n\nSet correct pll_d2_out0 divider and correct the p div values for pll_d2.\n\nSigned-off-by: David Ung <davidu@nvidia.com>\nSigned-off-by: Andrew Bresticker <abrestic@chromium.org>","David Ung",true],["82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874","d0b0cfa77edd7eb83f8b477c09c00a6335d75e71@nvidia.com","clk: tegra: fix host1x clock on Tegra124\n\nThe host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.\nChange thte id to tegra_clk_host1x_8 so that the correct clock gets\nregistered.\n\nSigned-off-by: Mark Zhang <markz@nvidia.com>\nSigned-off-by: Andrew Bresticker <abrestic@chromium.org>","Mark Zhang",true],["20e7c323abac390deb35248705807bd844590048","6f9d97df82107736b1c4f0e11d74242c25499ec8@chromium.org","clk: tegra: fix sdmmc clks on Tegra1x4\n\nThe sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with\n6 parents.  Add support for tegra_clk_sdmmc*_8 and switch Tegra114\nand Tegra124 to use these clocks instead.\n\nSigned-off-by: Andrew Bresticker <abrestic@chromium.org>","Andrew Bresticker",true],["88b4bd7071ac06e321b4bf4bdb8c69db40182c5a","6f9d97df82107736b1c4f0e11d74242c25499ec8@chromium.org","clk: tegra: cclk_lp has a pllx/2 divider\n\nWhen pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines\nwhether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that\nthe clk_super driver is aware of this.\n\nSigned-off-by: Andrew Bresticker <abrestic@chromium.org>","Andrew Bresticker",true]],"size":184,"ref":"refs/heads/master","head":"0c0bd34a142963ca3454f530e47ce1c230d8cc9d"}