GitHub PushEvent at 2014-08-25 00:17:47
Repository: linux-dccp
Actor: grrtrr
Payload: {"shas":[["4b70ac5fd9b58bfaa5f25b4ea48f528aefbf3308","20b70f0af00562e63758b9ee42012ecc96c58590@redhat.com","aio: change exit_aio() to load mm->ioctx_table once and avoid rcu_read_lock()\n\nOn 04/30, Benjamin LaHaise wrote:\n>\n> > -\t\tctx->mmap_size = 0;\n> > -\n> > -\t\tkill_ioctx(mm, ctx, NULL);\n> > +\t\tif (ctx) {\n> > +\t\t\tctx->mmap_size = 0;\n> > +\t\t\tkill_ioctx(mm, ctx, NULL);\n> > +\t\t}\n>\n> Rather than indenting and moving the two lines changing mmap_size and the\n> kill_ioctx() call, why not just do \"if (!ctx) ... continue;\"?  That reduces\n> the number of lines changed and avoid excessive indentation.\n\nOK. To me the code looks better/simpler with \"if (ctx)\", but this is subjective\nof course, I won't argue.\n\nThe patch still removes the empty line between mmap_size = 0 and kill_ioctx(),\nwe reset mmap_size only for kill_ioctx(). But feel free to remove this change.\n\n-------------------------------------------------------------------------------\nSubject: [PATCH v3 1/2] aio: change exit_aio() to load mm->ioctx_table once and avoid rcu_read_lock()\n\n1. We can read ->ioctx_table only once and we do not read rcu_read_lock()\n   or even rcu_dereference().\n\n   This mm has no users, nobody else can play with ->ioctx_table. Otherwise\n   the code is buggy anyway, if we need rcu_read_lock() in a loop because\n   ->ioctx_table can be updated then kfree(table) is obviously wrong.\n\n2. Update the comment. \"exit_mmap(mm) is coming\" is the good reason to avoid\n   munmap(), but another reason is that we simply can't do vm_munmap() unless\n   current->mm == mm and this is not true in general, the caller is mmput().\n\n3. We do not really need to nullify mm->ioctx_table before return, probably\n   the current code does this to catch the potential problems. But in this\n   case RCU_INIT_POINTER(NULL) looks better.\n\nSigned-off-by: Oleg Nesterov <oleg@redhat.com>\nSigned-off-by: Benjamin LaHaise <bcrl@kvack.org>","Oleg Nesterov",false],["855ef0dec7271ff7be7381feaaf3f4aed80bd503","20b70f0af00562e63758b9ee42012ecc96c58590@redhat.com","aio: kill the misleading rcu read locks in ioctx_add_table() and kill_ioctx()\n\nioctx_add_table() is the writer, it does not need rcu_read_lock() to\nprotect ->ioctx_table. It relies on mm->ioctx_lock and rcu locks just\nadd the confusion.\n\nAnd it doesn't need rcu_dereference() by the same reason, it must see\nany updates previously done under the same ->ioctx_lock. We could use\nrcu_dereference_protected() but the patch uses rcu_dereference_raw(),\nthe function is simple enough.\n\nThe same for kill_ioctx(), although it does not update the pointer.\n\nSigned-off-by: Oleg Nesterov <oleg@redhat.com>\nSigned-off-by: Benjamin LaHaise <bcrl@kvack.org>","Oleg Nesterov",false],["9e3754461507147ce5bffba5faaea7c182d64667","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: make memory type detection per memory controller\n\nHaswell has different register, offset to determine memory type and supports\nDDR4 in some models. This patch makes it easier to have a different method\ndepending on the memory controller type.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["f14d6892e4a6086d48fa77ac8e59003d3f4f8e16","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: make node id retrieval per model\n\nHaswell has a different way to retrieve the node id, make so this procedure\ncan be reimplemented.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["b976bcf249f4d3b28963e67b5194bc2690da260c","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: make RIR limit retrieval per model\n\nHaswell has a different way to retrieve RIR limits, make this procedure per\nmodel.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["dbc954ddddaaff0183a21dbd736ec10ca01e9f1a","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: search devices using product id\n\nThis patch changes the way devices are searched by using product id instead of\ndevice/function numbers. Tested in a Sandy Bridge and a Ivy Bridge machine to\nmake sure everything works properly.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["66ca72749166163c4ec9e5ab5416548a40d902d3","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: update Kconfig description\n\nKconfig wasn't updated when Ivy Bridge support was added.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["2ff3a308b5c776bdf4641311b87c843fe1bc3785","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: fix socket detection on Ivy Bridge controllers\n\nThis patch fixes the obvious bug while handling the socket/HA bitmask used in\nIvy Bridge memory controllers.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["d7c660b7dcb2f3c3835432cf733fba03507f4387","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: make minimal use of channel_mask\n\nchannel_mask will be used in the future to determine which group of memory\nmodules is causing the errors since when mirroring, lockstep and close page\nare enabled you can't. While that doesn't happen, use the channel_mask to\ndetermine the channel instead of relying on the MC event/exception.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["adc61bcd91aa8364efaa496e7a4699950c362c21","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: remove bogus assumption on mc ordering\n\nWhen a MC is handled, the correct sbridge_dev is searched based on the node,\nchecking again later with the assumption the first memory controller found is\nthe first socket's memory controller is a bogus assumption. Get rid of it.\n\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["7b8278358cc2b453ca6e75eedb3741cdb7e97236","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","edac: add DDR4 and RDDR4\n\nHaswell memory controller can make use of DDR4 and Registered DDR4\n\nCc: tony.luck@intel.com\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["c41afdca29acfdc78b89f936cdcb8cabc6b08aae","0cae1d1e981e84d16b82ca3d17be8a7f826608d3@samsung.com","sb_edac: Fix mix tab/spaces alignments\n\nWe should not have spaces before ^I on alignments.\n\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Mauro Carvalho Chehab",false],["50d1bb93672fa2f42cec6e06ce799fbe864f57e9","78e305742ac743ecf22d8139502576ac8709e0ad@redhat.com","sb_edac: add support for Haswell based systems\n\nHaswell memory controllers are very similar to Ivy Bridge and Sandy Bridge\nones. This patch adds support to Haswell based systems.\n\n[m.chehab@samsung.com: Fix CodingStyle issues]\nCc: Tony Luck <tony.luck@intel.com>\nSigned-off-by: Aristeu Rozanski <aris@redhat.com>\nSigned-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>","Aristeu Rozanski",false],["6e830d53717cf3d5c30c1afce3773ef97e436cd9","b05c66fa21e46731bb89a779db663748f3df8f6a@kvack.org","Merge ../aio-fixes","Benjamin LaHaise",false],["be6fb451a24582732c66e28cb0beb3f19c4289fd","b05c66fa21e46731bb89a779db663748f3df8f6a@kvack.org","aio: remove no longer needed preempt_disable()\n\nBased on feedback from Jens Axboe on 263782c1c95bbddbb022dc092fd89a36bb8d5577,\nclean up get/put_reqs_available() to remove the no longer needed preempt_disable()\nand preempt_enable() pair.\n\nSigned-off-by: Benjamin LaHaise <bcrl@kvack.org>\nCc: Jens Axboe <axboe@kernel.dk>","Benjamin LaHaise",false],["c27602086d08d22b067a1267e09fb32b4b096aa0","02e0a999c50b1f88df7a8f5a04e1b76b35ea6a88@lunn.ch","PCI: mvebu: Remove ARCH_KIRKWOOD dependency\n\nmach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.\nARCH_MVEBU is sufficient.\n\nSigned-off-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nAcked-by: Jason Cooper <jason@lakedaemon.net>","Andrew Lunn",false],["2cb989f6e99aa84997961fcef516e5cd123b9a78","3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","PCI: tegra: Add debugfs support\n\nProvide a debugfs file (\"pcie/ports\") that shows the current link status\nfor each root port.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nReviewed-by: Stephen Warren <swarren@nvidia.com>","Thierry Reding",false],["4dd964df36d0e548e1806ec2ec275b62d4dc46e8","c224db9378a929ae8338a052bbb1b30fb46cdd39@ti.com","PCI: designware: Look for configuration space in 'reg', not 'ranges'\n\nThe configuration address space has so far been specified in *ranges*,\nhowever it should be specified in *reg* making it a platform MEM resource.\nHence used 'platform_get_resource_*' API to get configuration address space\nin the designware driver.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nAcked-by: Mohit Kumar <mohit.kumar@st.com>\nAcked-by: Jingoo Han <jg1.han@samsung.com>\nCc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\nCc: Marek Vasut <marex@denx.de>\nCc: Arnd Bergmann <arnd@arndb.de>","Kishon Vijay Abraham I",false],["f4c55c5a3f7f68c06cc559ed7af8b2d017cbb0a7","c224db9378a929ae8338a052bbb1b30fb46cdd39@ti.com","PCI: designware: Program ATU with untranslated address\n\nIn DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see\nonly 28-bit addresses.  So whenever the CPU issues a read/write request,\nthe 4 most significant bits are used by L3 to determine the target\ncontroller.  For example, the CPU reserves [mem 0x20000000-0x2fffffff]\nfor the PCIe controller but the PCIe controller will see only\n[0x00000000-0x0fffffff].  For programming the outbound translation\nwindow the *base* should be programmed as 0x00000000.  Whenever we try to\nwrite to, e.g., 0x20000000, it will be translated to whatever we have\nprogrammed in the translation window with base as 0x00000000.\n\nThis is needed when the dt node is modelled something like this:\n\n    axi {\n        compatible = \"simple-bus\";\n        #size-cells = <1>;\n        #address-cells = <1>;\n        ranges = <0x0        0x20000000 0x10000000 // 28-bit bus\n                  0x51000000 0x51000000 0x3000>;\n        pcie@51000000 {\n                reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;\n                reg-names = \"config\", \"ti_conf\", \"rc_dbics\";\n                #address-cells = <3>;\n                #size-cells = <2>;\n                ranges = <0x81000000 0 0          0x03000 0 0x00010000\n                          0x82000000 0 0x20013000 0x13000 0 0xffed000>;\n        };\n    };\n\nHere the CPU address for configuration space is 0x20013000 and the\ncontroller address for configuration space is 0x13000.  The controller\naddress should be used while programming the ATU (in order for translation\nto happen properly in DRA7xx).\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nReviewed-by: Mohit Kumar <mohit.kumar@st.com>\nCc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\nCc: Jingoo Han <jg1.han@samsung.com>\nCc: Marek Vasut <marex@denx.de>\nCc: Arnd Bergmann <arnd@arndb.de>","Kishon Vijay Abraham I",false],["47ff3de911a728cdf9ecc6ad777131902cff62b4","c224db9378a929ae8338a052bbb1b30fb46cdd39@ti.com","PCI: dra7xx: Add TI DRA7xx PCIe driver\n\nAdd support for PCIe controller in DRA7xx.  This driver re-uses the\ndesignware core code that is already present in kernel.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nAcked-by: Jingoo Han <jg1.han@samsung.com>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: Pawel Moll <pawel.moll@arm.com>\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: Ian Campbell <ijc+devicetree@hellion.org.uk>\nCc: Kumar Gala <galak@codeaurora.org>\nCc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\nCc: Mohit Kumar <mohit.kumar@st.com>\nCc: Marek Vasut <marex@denx.de>\nCc: Arnd Bergmann <arnd@arndb.de>","Kishon Vijay Abraham I",false]],"size":295,"ref":"refs/heads/master","head":"a45e92a599e77ee6a850eabdd0141633fde03915"}