superio/nuvoton: Adds a function to route pins 41-48 to UARTD

Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.

Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
superio/nuvoton: Add chip support for setting IRQs to edge/level

Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
superio/smsc/fdc37n972: Trivial cleanup reorder headers

Alphabetise headers and a few trivial cleanups.

Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6042
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>