new module for asynchronous communication
small modification to packages and new module for UART
small change to ease code reading
small modification to get tx and rx more robust. Should work but test showed small error on reception for very long runs ...
adding sseg x4 wishbone module (works with the edu).
new 7seg controller with multiplexing
added modification to 7seg
new util component and added some components to package
updating logipi_ra2_edu ucf
Merge branch 'master' of https://github.com/fpga-logi-dev/logi-hard
small modification to peripherals
Merge branch 'master' of https://github.com/fpga-logi-dev/logi-hard
revering all change to get simple but functionnal fifos
simulation files for some of the components
adding missing watchdog
adding logipi_ra3_edu
Merge branch 'master' of https://github.com/fpga-logi-dev/logi-hard
fixed logi-pi ra3 ucf file.
cleanup
removing some ise noise