Not using the VHDL_Lib
adding the follow lines to XESS_SdramSPInst.vhd
	  NROWS_G       => 4096,  -- Number of rows in SDRAM array.
      NCOLS_G       => 512,  -- Number of columns in SDRAM array.
      HADDR_WIDTH_G => 23,   -- Host-side address width.
      SADDR_WIDTH_G => 12   -- SDRAM-side address width.
This required that several lines to changed from 23 downto 0 to
22 downto 0
It also required changes 12 downto 0 to 11 downto 0
the change that does not make was in XuLA2.ucf which was working
in the simulation. This require a chg
48c48
< #NET sdAddr_o<12>   LOC = H13;
---
> NET sdAddr_o<12>   LOC = H13;
 Volume in drive C is TI10649600G
 Volume Serial Number is 8AED-5E67

 Directory of c:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst

12/09/2014  09:44 AM    <DIR>          .
12/09/2014  09:44 AM    <DIR>          ..
12/09/2014  08:36 AM               163 diff_XuLA2.ucf
12/09/2014  05:57 AM    <DIR>          ex_lib_files
10/13/2014  09:00 AM             2,694 fsmjpeg.py
12/05/2014  02:30 PM               925 jj
12/06/2014  08:44 AM               526 jjj
12/05/2014  06:27 PM                 0 jpeg.vhd
12/05/2014  05:58 PM            20,541 jpeg_top.py
12/06/2014  08:27 AM             4,884 jpeg_top.vhd
12/09/2014  09:33 AM             3,500 pck_myhdl_09.vhd
12/07/2014  04:41 AM             2,383 RamCtrl.vhd
12/09/2014  07:39 AM             1,777 sdram_test.py
12/08/2014  05:03 AM             4,084 simul.vhd
12/07/2014  06:44 PM    <DIR>          simulation
12/07/2014  12:26 PM            14,336 sum_r.xls
12/05/2014  06:31 PM               381 tb_RamCtrl.v
12/06/2014  05:28 AM             1,357 tb_xess_jpeg_top.v
12/09/2014  09:33 AM            27,746 testingxess_jpeg_top.py
12/06/2014  05:46 AM            23,245 testing_jpeg_top.py
12/09/2014  09:46 AM               287 ttt
12/09/2014  09:40 AM            27,746 xess_jpeg_top.py
12/06/2014  05:33 AM             5,113 xess_jpeg_top.v
12/09/2014  09:33 AM            10,123 xess_jpeg_top.vhd
12/09/2014  09:35 AM           340,705 xess_sdramspinst.bit
12/09/2014  05:54 AM            14,228 XESS_SdramSPInst.vhd
12/06/2014  07:15 AM            13,120 XESS_SdramSPInst_testFSM.vhd
09/14/2014  06:58 AM             5,112 XuLA2.ucf
12/09/2014  05:37 AM            24,839 xx
              25 File(s)        549,815 bytes
               4 Dir(s)  568,099,090,432 bytes free

python sdram_test.py results

0x0006 0x0087
The values 1 4 7 10 and 13 written to sdram
:10000000009C000100040007000A000D009C00A4F1