moved where the signal sent to jpeg are in top_level_mod.vhd

3 1 1 -3 -3 633 0x00a3 0x009b 0x009b 0x0003 0x2003 0b1 0b1
3 1 0 313 313 633 0x00a3 0x009b 0x009b 0x0003 0x2003 0b1 0b1
3 0 0 75 75 633 0x00a3 0x009b 0x009b 0x0003 0x2003 0b1 0b1
3 0 1 235 235 633 0x00a3 0x009b 0x009b 0x0003 0x2003 0b1 0b1
The sam is not correct
the values computed for jpeg are correct with local jpeg
00a3	163
009b	155
009b	155
This comparing the local jpeg with the FPGA
1	1 -3
1 	0 313
0	0 75
0	1 235