Enforce 32-bit in 64-bit canonical form
MSRs have read and write hooks now (breaks run_sscalar*)

The MSR space has been much enlargened as a consequence, ISA_NO_REG
moved to -1.  Unfortunately this has broken something in the
Superscalar implementation.
RISCV bugfixing and greatly expanded

- Added a regression test again riscv-tests

- Support the CSR* family of instructions (not in RV32G, but needed
  for riscv-tests)

- Simulate a simple serial slave

- A quick hack to dump the memory needed to initialize the
  YARVI-RV32-V0 implementation