target: msm8226: Add support for new QVGA platform subtype

Add support for new QVGA platform subtype and also modify
MEMBASE, scratch address and size to conform to the
new 128MB memorymap.

CRs-Fixed: 630700
Change-Id: I5dd2cfb5aee431a5aae8fa9ba0474b82417309a6
target: msm8974: Remove GCC_WDOG_DEBUG_DISABLE from the reboot sequence.

WDOG_DEBUG was disabled due to a HW bug during the bringup.
WDOG_DEBUG is XPU protected and disabling it is causing XPU
violations. Remove it from reboot sequence as the HW bug is resolved.

CRs-Fixed: 622426
Change-Id: Ia6ff07fd8ac62b4ad3ab36b42375cdfdc5eeb130
platform: Add new api to get MSM_SHARED_BASE

Add a new api to get MSM_SHARED_BASE address from platform.
MSM_SHARED_BASE address is dependent on platform subtype and
hence is different for some platform variants.

Change-Id: I307d2110984e788aeeac2bcaa9f185ce2e2c92f4
platform: msm8226: Modify MSM_SHARED_BASE based on platform subtype.

Add the MSM_SHARED_BASE address for the new QVGA platform subtype.
Also implement the api which returns MSM_SHARED_BASE based on platform
subtype.

Change-Id: I89cbc6415c030123494fce703a1fa6474ea441ab
platform: msm_shared: Add support for byte addressing

Add support for byte addressing for erase operations.
Change-Id: I553a33e6ac072077b6ffb20348ba327b877c00f1
platform: msm8916: add support for display clocks

Update the 8916 clock header file with display related clock
register offsets. Update 8916 clock driver with the required
display clock structures and register the clocks. Add DSI
clocks, MDP clocks, BUS clocks and GDSC clock enable/disable
APIs for msm8916 target.

Change-Id: I57189ccd7aa62c76a2c019a6c8cc35c5f77373f8
target: msm8916: include display header files for msm8916

Update target location with display header support for
msm8916.

Change-Id: I1c5733586f21c53ac7b595022a451eda32a171dc
platform: 8916: Update iomap header with MDSS offsets

Add the register offsets related to MDP and DSI registers
in the iomap header file for 8916.

Change-Id: If5f3b371ed614c59a9f074e527a8a1c265574dc0
platform: add DSI_PHY and DSI_PLL offsets in iomap headers

The DSI PHY and PLL register base addresses are different for
different targets from the DSI controller base. Update the
iomap header files of the targets with their base address
macros.

Change-Id: Ifd35a0e2195c34d872c7fa6ab7377d22cc06a768
platform: update the DSI PLL APIs to use DSI_PLL base

The PLL register offsets from the DSI controller base
is not same for all targets. Update the auto PLL and
DSI PLL lock APIs to use the DSI_PLL base to handle
these cases.

Change-Id: Ie8aebc1bcc2b63f6825964c3476ce5cb6d0e7732
platform: update the DSI PHY APIs to use DSI_PHY base

The PHY register offsets from the DSI controller base
is not same for all targets. Update the DSI PHY
initialization APIs to use the DSI_PHY base to handle
these cases.

Change-Id: If46ce9dbd81ed7f165944ad58c164a9063fe485b
platform: msm_shared: Update MDP5 for msm8916 support

msm8916 supports MDSS 1.6 version. This change updates MDP5
with the new MDSS_MDP version checks and adds display files for
compilation.

Change-Id: I5fbd9b7140c086c72649c667022ba54ad709f8e8
dev: gcdb: add NULL check before accessing slave panel node

The slave panel node is valid only for dual DSI panels. Add a
NULL check before accessing the slave panel string.

Change-Id: I156dca8e581a3fc2bc9518e35846b53ef70658f5
target: msm8916: Add display support for msm8916 target

Add display support in lk with continuous splash screen
for msm8916 target with GCDB and auto PLL.

Change-Id: Iff03aae0571a385feceab1148cacc74dbd4671b4
platform: uart: disable IRQ while UART sending data

To send some bytes by UART, we program the DM_NO_CHARS_FOR_TX
register to tell UART FSM how many data we have. Then we write
the data to the DM_TF register one by one. Once the number we
write to the DM_TF is equal to DM_NO_CHARS_FOR_TX, TX_RDY signal
will be set. And we send the data successfully.

Consider this scenario, the flow is aborted, by the X IRQ,
in the following position:
...
check TX_RDY signal
...
write DM_NO_CHARS_FOR_TX
...                        ---------->aborted by X IRQ
write DM_TF
...
And the X IRQ handler also wants to send out some data by UART.
Then the IRQ handler will hang at the TX_RDY checking. Because
the TX_RDY never arrives if the previous flow doesn't finish.

CRs-Fixed: 637800
Change-Id: I6d518a503eb23e02e634f64b06a7f9e22e9d4456
Merge "platform: msm8916: add support for display clocks"
Merge "target: msm8916: include display header files for msm8916"
Merge "platform: 8916: Update iomap header with MDSS offsets"
Merge "platform: add DSI_PHY and DSI_PLL offsets in iomap headers"
Merge "platform: update the DSI PLL APIs to use DSI_PLL base"