Default to use 10 seconds as nap interval instead of 1.

Previously, we have a nap interval of 1 second while we have a timeout of
128 seconds by default, which could be an overkill, and for some hardware
the patting action may be expensive.

Note that the choice of nap interval is still arbitrary.  We preferred
a safe value where even when the system is very heavily loaded, the
watchdog should not shoot the system down if it's not really hung.
According to the manual page of Linux's watchdog daemon, the nap interval
time of theirs is 10 seconds, which seems to be a reasonable value --
according to Intel documentation AP-725 (Document Number: 292273-001),
ICH5's maximum timeout is about 37.5 seconds, which the ichwd(4) driver
would set when we requested 128 seconds (although it should probably
feed back this as an error and do not set the timeout).  Since that's
the shortest maximum value, 10 seconds seems to be a right choice for
us too.

Discussed with:	alfred
MFC after:	1 month
Make witness happy: destroy rte lock before free.

MFC after:	2 weeks
drm/radeon: Lower priority of a message related to invalid EDID

Like in r259717, the prority goes from "error" to "debug" to avoid
spamming logs when the connectors are polled.

PR:		194770
Submitted by:	Larry Rosenman <ler@lerctr.org>
MFC after:	1 week
Fix r273112: do not turn DROP_EN by default.

Due to adapter->hw.fc.requested_mode is filled with default value
after ixgbe_initialize_receive_units(), this leads to enabling
DROP_EN in most cases.

Tested by:	ae
MFC after:	1 week
Revert r274585: rte lock is properly destroyed in uma dtor callback.

Pointed by:	glebius
Add freebsd-testing and myself to MAINTAINERS for contrib/netbsd-tests and
contrib/pjdfstest
Convert tools/regression/lib/libc/stdio/test-fmemopen into an ATF testcase and
rename as lib/libc/stdio/fmemopen2_test

Sponsored by: EMC / Isilon Storage Division
Flush out many more static binaries that can be used in a jail for building
pkgs via poudriere.  This removes a significant amount of emulation speeding
up run times.

Phabric:	D1172
Reviewed by:	imp
MFC after:	2 weeks
Convert tools/regression/lib/libc/stdio/test-fpclassify into an ATF testcase and
Rename as lib/libc/stdio/fpclassify2_test

Sponsored by: EMC / Isilon Storage Division
Indent a couple lines properly and expand a comment.  No functional changes.
Skip the long-double epsilon checks on FreeBSD/i386

Sponsored by: EMC / Isilon Storage Division
Reset errno to 0 before running scalbn to be sure that the tested errno is
valid

Sponsored by: EMC / Isilon Storage Division
Alias isinff to isinf on FreeBSD

isinf on FreeBSD automatically picks the appropriate type per math.h

Sponsored by: EMC / Isilon Storage Division
- Expect exp2_powers to fail on FreeBSD/i386
- Expect exp2_values to fail on FreeBSD due to the small epsilon

Sponsored by: EMC / Isilon Storage Division
- Skip over the testcases that call cbrtl on platforms where LDBL_PREC == 53
(arm, mips, powerpc). This fixes the build on these platforms, based on some
ad hoc tinderbox runs I did a while ago
- Skip cast the arguments to powl as long double so powl properly interprets
those arugments at compile-time when picking the type

Sponsored by: EMC / Isilon Storage Division
Do not do a cache invalidate on a PREREAD sync that is also a PREWRITE sync.
The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer.  There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
Do the cache invalidate sequence from the outermost to innermost, required
for correct operation.

Submitted by:	Michal Meloun <meloun@miracle.cz>
Correct the sequence of busdma sync ops involved with PRE/POSTREAD syncs.

We used to invalidate the cache for PREREAD alone, or writeback+invalidate
for PREREAD with PREWRITE, then treat POSTREAD as a no-op.  Prefetching on
modern systems can lead to parts of a DMA buffer getting pulled into the
caches while DMA is in progress (due to access of "nearby" data), so it's
mandatory to invalidate during the POSTREAD sync even if a PREREAD
invalidate also happened.

In the PREREAD case the invalidate is done to ensure that there are no
dirty cache lines that might get automatically evicted during the DMA,
corrupting the buffer.  In a PREREAD+PREWRITE case the writeback which is
required for PREWRITE handling is suffficient to avoid corruption caused
by eviction and no invalidate need be done until POSTREAD time.

Submitted by:	Michal Meloun <meloun@miracle.cz>
No functional changes.  Remove a couple outdated or inane comments and
add new comment blocks describing why the cache maintenance sequences are
done in the order they are for each case.
Add mv, echo and hostname to the native-xtools target.  Missed these
when profiling.

MFC after:	2 weeks