[ARM] arm64: Trap data cache operation by set/way

On SMP host, just upgrading data cache set/way
operations to clean+invalidate operations won't
suffice.

If a VCPU is preempted while it was doing
clean/invalidate/clean+invalidate by set/way
on host CPU A and resumed on host CPU B then
effects of set/way operations will not be
correctly seen by all host CPUs. To take care
of this clean/clean+invalidate entire data cache
by set/way when such a VCPU is resumed on another
host CPU.

This approach is very similar to what we already
for set/way operations on arm32ve port.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Updating the character device API.

As the offset is needed for most of character devices, an offset pointer have
been added to the read and write operations. The character device
implementation is in charge of using and updating it if necessary.

The argument for the IO control has been updated to match Linux's.

Cc: Jimmy Durand Wesolowski <jimmy.durand-wesolowski@openwide.fr>
Signed-off-by: Jimmy Durand Wesolowski <jimmy.durand.wesolowski@gmail.com>
[DRIVERS] Serial drivers updated to use the new chardev API.

Serial driver read and write operations now take an unused argument, an
operation offset pointer, to match the new chardev API.

Cc: Jimmy Durand Wesolowski <jimmy.durand-wesolowski@openwide.fr>
Signed-off-by: Jimmy Durand Wesolowski <jimmy.durand.wesolowski@gmail.com>
[ARM] mmu_lpae: Implement arch_cpu_aspace_memory_xxx() APIs

This patch implements arch_cpu_aspace_memory_xxx() for LPAE MMU
to improve host physical read/write() performance of arm32ve
and arm64 ports.

With this patch, the ping delay is reduced by 0.1 ms on ARM
fast models and Foundation v8 model.

Signed-off-by: Anup Patel <anup@brainfault.org>