baytrail: Update to microcode 31E and fix C-state table

With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.

BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now

Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4984
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
baytrail: Add ACPI code to describe GPIO controller

There are 3 banks of GPIOs that need to be described
with specific _UID and memory/interrupt values.

BUG=chrome-os-partner:24314
BRANCH=none
TEST=build and boot on rambi, check for probed driver:

gpiochip_find_base: found new base at 154
gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00
gpiochip_find_base: found new base at 126
gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01
gpiochip_find_base: found new base at 82
gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02

  fed0c000-fed0cfff : INT33FC:00
    fed0c000-fed0cfff : INT33FC:00
  fed0d000-fed0dfff : INT33FC:01
    fed0d000-fed0dfff : INT33FC:01
  fed0e000-fed0efff : INT33FC:02
    fed0e000-fed0efff : INT33FC:02

Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178601
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4985
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
baytrail: add lpe codec clock configuration

Add device tree option to determine if the LPE
audio codec has a platform clock signal connected
to it from the SoC. If a frequency is selected the
platform clock number is used to enable the
clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted rambi with 25MHz option. Probed pin
     to audio codec. Noted 25MHz clock.

Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178780
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4986
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
rambi: configure the LPE audio codec clock

Rambi has the LPE audio codec connected to PMC_PLT_CLK[0].
Configure it for 25MHz.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Noted message in console output.

Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178781
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4987
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
baytrail: Fix _CRS to build with new IASL

The new IASL is complaining about the PCI memory region not
having consistent base/end/length values because they are
placeholder that are fixed up in the method before returning.

Put in some more valid placeholder values to make it happy.

BUG=chromium:311294
BRANCH=none
TEST=build and boot with IASL 20130117 on rambi

Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4988
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
baytrail: enable lpe resources assigned to device

The enable_resources callback was accidentally populated
with NULL. Make that callback be the generic
pci_dev_enable_resources.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted.

Change-Id: I670b51bd9aff6764e9b549287a737b662572cdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178960
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4989
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
rambi: configure SD card signals

Rambi 1.5 boards use the native SD card controller on baytrail.
Therefore, enable those signals. The CLK, D*, and CMD pins use
2K pulls as these were shown to not exhibit any errors when
doing reads or writes to a DDR50 sd card.

Note that if a servo is connected on needs to enable the
sd_vref_sel rail to pp1800 as this causes issues with card
detect if it is not set to pp1800.

BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Tested sd card read and write works in kernel.
     Also noted that write protect detection works as well.

Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178961
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4990
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
rambi: Change eMMC pin PUs to 2K

Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up
on certain boards.

BUG=chrome-os-partner:24353
TEST=Manual. Burn FW on board that previously failed to boot eMMC,
verify chromeos can now install + boot from eMMC.
BRANCH=none

Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4991
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
baytrail: gpio: Make GPIO inputs MMIO by default

The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the
default input GPIO type MMIO.

BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat
/sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic
jack status.
BRANCH=None

Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179169
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4992
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
rambi: Make ec_in_rw a legacy GPIO

ec_in_rw needs to be read by depthcharge, which only supports legacy
GPIOs.

BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge
detects the proper ec_in_ro state.
BRANCH=None

Change-Id: I25802b445c795eb85580c22d880efee8eeb21318
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4993
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)