Revert "r600g/compute: Fix warnings"

This reverts commit 467f1585e28adba0e94ef593de131bc327f098bb.

This breaks the build on some systems.
freedreno/a3xx/compiler: fix p0 (kill, etc)

Don't assert (debug builds) or assign random uninitialized value for
predicate register (p0).. that screws up kill, etc.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
i965: Don't print WE_normal in disassembly.

Dropping this helps most lines fit in an 80 column terminal.  The
absence of WE_normal also helps call attention to WE_all, where
something unusual is going on.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Save the gl_shader_stage enum in backend_visitor.

This will be useful for INTEL_DEBUG=optimizer in the vec4 backend, which
needs to know whether it's currently processing a VS or GS.  It isn't
worth adding virtual methods for this case.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Port INTEL_DEBUG=optimizer to the vec4 backend.

Largely via copy and paste.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/fs: Set LastRT on the final FB write on Broadwell.

In Piglit's EXT_framebuffer_multisample/alpha-to-coverage-dual-src-blend
test, key->nr_color_regions == 2, but the dual source blend FB write has
ir->target set to 0.  So we failed to set "Last Render Target Select" on
any FB write message.

We only emit one FB write per render target, so my comment about setting
LastRT on every FB write directed at the last color region is a bit...
misinformed.  According to the documentation, depth buffer writes and
scoreboard updates happen on the FB write with LastRT set, so I believe
we want to set it only once.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
glsl: Fix some bad indentation

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
mesa: Fix the name in the error message

Obvious copy-and-paste bug.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Accelerate uploads of RGBA and BGRA GL_UNSIGNED_INT_8_8_8_8_REV textures

Since intel is always going to be little-endian,
GL_UNSIGNED_INT_8_8_8_8_REV is the same as GL_UNSIGNED_BYTE for RGBA and
BGRA textures, so the same acceleration code will work.  We might as well
use it.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
ilo: allow for device-dependent format translation

Pass ilo_dev_info to all format translation functions.
ilo: use native 3-component vertex formats on GEN7.5+

GEN7.5 gains support for those formats natively.
ilo: share some code between {tex,buf}_create_bo

Add resource_get_bo_name() and resource_get_bo_initial_domain() for use by
both functions.
ilo: clean up resource bo renaming

s/alloc_bo/rename_bo/ as that is what the functions do.  Simplify bo
allocation and move the complexity to bo renaming.
ilo: check the tilings of imported handles

Just to be cautious.
mesa: add ARB_clear_texture.xml to file list, remove duplicate decls

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
nvc0: make sure that the local memory allocation is aligned to 0x10

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
nv50/ir: keep track of whether the program uses fp64

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0: mark shader header if fp64 is used

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nv50/ir: fix hard-coded TYPE_U32 sized register

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nv50/ir: fix phi/union sources when their def has been merged

In a situation where double-register values are used, the phi nodes can
still end up being u32 values. They all get merged into one RA node
though. When fixing up the merge (which comes after the phi node), the
phi node's def would get fixed, but not its sources which would remain
at the low register value.

This maintains the invariant that a phi node's defs and sources are
allocated the same register.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>