hdl/modules/*/wb_acq_core/acq_fc_fifo.vhd: fix reset bug

The internal reset logic had a bug in that for slow
acquisition clocks (fs_clk) the reset request from
the upper module (fsm_state = "001") was asserted
after the completion pulse signal from the FIFO.
The modification includes a pulse to level signal
for the completion pulse signal and a 3 clock cycle
delay for deasserting the completion level signal.
hdl/ip_cores/dsp-cores: update submodule reference