ARM: Implement big endian bit-conversion for NEON type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208538 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] Add proper bounds checking/diagnostics to logical shifts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208540 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Replace FeatureFPIdx with FeatureMips4_32r2

Summary:
No functional change.

The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions)

Depends on D3677

Reviewers: rkotler, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208541 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2

Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fold FeatureSEInReg into FeatureMips32r2

Summary: No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208543 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64

Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them

Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
Remove MCUseCFI from TargetMachine.

It was always true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208547 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them

Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the useCFI constructor argument to MCAsmStreamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208551 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Make sure that we have SSE4.1 before we generate insertps nodes.

PR19721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208552 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the always true UseCFI member.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208553 91177308-0d34-0410-b5e6-96231b3b80d8
Remove now empty method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208554 91177308-0d34-0410-b5e6-96231b3b80d8
Remove write only field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208555 91177308-0d34-0410-b5e6-96231b3b80d8
Remove an always true argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208557 91177308-0d34-0410-b5e6-96231b3b80d8
Remove always true argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208558 91177308-0d34-0410-b5e6-96231b3b80d8
Remove always true argument and field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208559 91177308-0d34-0410-b5e6-96231b3b80d8
Remove always true argument and unused field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208561 91177308-0d34-0410-b5e6-96231b3b80d8
Move EH/Debug frame handling to the object streamer.

Now that the asm streamer doesn't use it, the MCStreamer doesn't need to know
about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208562 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: merge "extend" and "shift" addressing-mode enums.

In terms of assembly, these have too much overlap to be neatly modelled as
disjoint classes: in many cases "lsl" is an acceptable alternative to either
"uxtw" or "uxtx".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208563 91177308-0d34-0410-b5e6-96231b3b80d8