Modified FIFO1 write control to allow for L1A's on any clock cycle.
Rearranged pipeline FIFO structure.  Was using three 18Kb FIFOs for
8ch X 12-bits (ADC unit).  This used 12*3 = 36 18Kb FIFOs (18 36Kb FIFOs)
Now using two 36Kb FIFOs in ECC mode per ADC unit.  This uses 12*2 = 24
36Kb FIFOs.
Replaced the 16 FIFO1s with ECC FIFOs.  Added l1a_smp_fifo to store L1A
info per sample (two entries per sample to accomodate L1A's on any clock
cycle.
Corrected 'event_pipe' size,
added transfer_samples state machine and xfer2ringbuf.v
Added ring buffer, changed readout_fifo to chanlink_fifo,
changed mac_fifo to eth_fifo.  Added/changed l1a buffers to match the
ring buffer and new readout fifos.
Ring buffer debugging code added.
Tested ring buffer with this version.  Seems to work well.
Merge branch 'RingBuf' into Pro

Conflicts:
	dcfeb3a.xise
	source/dcfeb3a.v
Resolved conflicts, but need to modify new file eth_fifo to add L1A_CNT,
and L1A_MTCH_CNT.
Manual adjustments to complete merge.  L1A counters now done in fifo16ch_wide.v.