clock/nva3: Parse clock control registers more accurately
clock/nva3: Set PLL refclk
clock/nva3: HOST clock
clock/nva3: Abort when PLL doesn't lock
clock/nva3: For PLL clocks always make sure the PLL is not in use
clock/nva3: Set intermediate core clock on reclocking
clock/nva3: Pause the GPU before reclocking
clock/nva3: Allow user reclocking
fb/ramnv50: Store the number of partitions in the designated fields
fb/ramnva3: WIP NVA8 link training unit

XXX: What ram types, chips use this?
fb/ramnva3: Use ram->base structs instead of local structs

This will ease the use of generic timing and MR generation bits later
fb/ramnva3: Ressurect timing calculation code
fb/sddr3: Expand MR generation with various bits
fb/sddr2: Generate MR values
fb/nva3: WIP Start on some reclocking bits
pwr/memx: WIP Wait for VBLANK if desired
WIP train external hook
fb/ramnva3: WIP support for DDR2 reclocking
fb/ramfuc: Support strided regs
fb/ramnva3: WIP Per-partition regs