Merge pull request #1 from QuickJack/master

Fixes write operation in synchronous burst mode
new set of components to interface in virtual instrument
some changes to save registers
small modification to push buttons and correcting a typo on virtual 7seg
small modification
adding license information to all files
update 7seg to 8 bits rather than 9
Merge branch 'master' of https://github.com/fpga-logi/Logi-hard

Conflicts:
	virtual_instrument/logi_virtual_7seg.vhd
adding wishbone diagram files
new intercon component
adding lvds pin defenitions for 8 pmod lvds pairs.
Merge branch 'master' of https://github.com/fpga-logi/Logi-hard
modifying wishbone files to ensure consistency in naming
forgot to modify intercon description
intercon should now be working, still need to refine addressing options on the memory map
modification for acknowledge computation
adding new gpio components for future test
small modification to remove unused record declaration
new ucf for new revision
adding gpomc wishbone test