sim_core: fix rcall instruction cycles...

Based on the instrtiming.elf code and checking the Avr Instruction
 Manual, RCALL was found to be producing incorrect cycle counts.

Atmega; 3, 16-bit pc; 4, 22-bit pc.

Fixed accordingly.

	modified:   sim/sim_core.c
Merge pull request #68 from bsekisser/master-core-fix-rcall-cycles

sim_core: fix rcall instruction cycles...
sim_core: add ldi, labeling corrections.

in moving the majority of instructions to follow use of register
 macros, ldi was missed.

get_h4_k16() was incorrectly labeled where get_h4_k8() was intended
 as k is an 8 bit quantity not 16.

get_o_12() was changed to get_o12() following the convention set
 forth with the other macros.

several trace statements were missed during the conversion and fixed.

ORI was incorrecly labeled as ANDI in the description and corrected.

	modified:   sim/sim_core.c
sim_core: flag equations refactored.

Most flag equations have been refactored into flag group function
  blocks...  The core passes all provided tests in the tests folder
  and now most especially is able to pass the instruction test code.
  At the same time, the overall average cycles per instruction has
  ticked down.

	modified:   sim/sim_core.c
Merge pull request #69 from bsekisser/master-core-ldi-labeling-misc

sim_core: add ldi, trace and labeling corrections.
Merge pull request #67 from bsekisser/master-core-refactor-flags

sim_core: flag equations refactored.
flash: Add support for TEMPPAGE writing.

The proper way to write to flash on the AVR is to write
to the temp page and then write that temp page to flash.
This allows cancellation with the RWWSRE bit for clearing
out the temp page without writing it to flash.

This fixed a bug where the RWWSRE bit was being set in a
command, but the flash driver was improperly writing whatever
was in r0/r1 to the first address in the page, overwriting
what was already there. In reality, the code running on the
core was trying to just flush the temp page or unlock the read
while write section.