Add lit.local.cfg for MC/Sparc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198536 91177308-0d34-0410-b5e6-96231b3b80d8
Attempt to fix buildbots by XFAILing some architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198537 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug in IRBuilder that's been there for who knows how long. It
failed to correctly propagate the NUW and NSW flags to the constant
folder for two instructions. I've added a unittest to cover flag
propagation for the rest of the instructions and constant expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198538 91177308-0d34-0410-b5e6-96231b3b80d8
Add support to the pattern match library for matching NSW and NUW
instructions. I needed this for a quick experiment I was making, and
while I've no idea if that will ever get committed, I didn't want to
throw away the pattern match code and for anyone else to have to write
it again. I've added unittests to make sure this works correctly.

In fun news, this also uncovered the IRBuilder bug. Doh!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198541 91177308-0d34-0410-b5e6-96231b3b80d8
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
Remove no longer needed x86 disassembler hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198546 91177308-0d34-0410-b5e6-96231b3b80d8
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198547 91177308-0d34-0410-b5e6-96231b3b80d8
Use patterns to remove some duplicate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198550 91177308-0d34-0410-b5e6-96231b3b80d8
Add the other form of movq xmm,xmm for the disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198551 91177308-0d34-0410-b5e6-96231b3b80d8
Add in a unittest for the one-use pattern matcher.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198552 91177308-0d34-0410-b5e6-96231b3b80d8
[PM] Add a definition for the static PassID in the CallGraphAnalysis.
Missed this when adding the skeleton analysis. Caught by a build break
in the next patch I'm working on when trying to use the analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198556 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added more intrinsics for convert and min/max.
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
[Mips] Rename the test case input file. No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198560 91177308-0d34-0410-b5e6-96231b3b80d8
[Mips] Add support for DT_MIPS_RLD_MAP and DT_MIPS_PLTGOT dynamic
section tags to the llvm-readobj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198561 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD;
Optimized a truncate pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: style changes to LDRD, STRD definition

Fix indentation, name registers similar to ARM ARM.

No functionality change!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198563 91177308-0d34-0410-b5e6-96231b3b80d8
Remove opcode from MOV32r0 that I accidentally left when I converted it to Pseudo. Remove FIXME as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198564 91177308-0d34-0410-b5e6-96231b3b80d8
ELF relocation types for sparc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198565 91177308-0d34-0410-b5e6-96231b3b80d8