InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222620 91177308-0d34-0410-b5e6-96231b3b80d8
Reduce size of some tables in tablegen register info output.

Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222621 91177308-0d34-0410-b5e6-96231b3b80d8