[PM] Fix the const-correctness of the generic DominatorTreeBase to
support notionally const queries even though they may trigger DFS
numbering updates.

The updating of DFS numbers and tracking of slow queries do not mutate
the observable state of the domtree. They should be const to
differentiate them from the APIs which mutate the tree directly to do
incremental updates.

This will make it possible in a world where the DominatorTree is not
a pass but merely the result of running a pass to derive DominatorTree
from the base class as it was originally designed, removing a huge
duplication of API in DominatorTree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199101 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Embedded Rounding Control - encoding and printing
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
[PM][cleanup] Clean up comments and use modern doxygen in this file.
This is a precursor to breaking the pass that computes the DominatorTree
apart from the concrete DominatorTree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199103 91177308-0d34-0410-b5e6-96231b3b80d8
[PM] Split DominatorTree into a concrete analysis result object which
can be used by both the new pass manager and the old.

This removes it from any of the virtual mess of the pass interfaces and
lets it derive cleanly from the DominatorTreeBase<> template. In turn,
tons of boilerplate interface can be nuked and it turns into a very
straightforward extension of the base DominatorTree interface.

The old analysis pass is now a simple wrapper. The names and style of
this split should match the split between CallGraph and
CallGraphWrapperPass. All of the users of DominatorTree have been
updated to match using many of the same tricks as with CallGraph. The
goal is that the common type remains the resulting DominatorTree rather
than the pass. This will make subsequent work toward the new pass
manager significantly easier.

Also in numerous places things became cleaner because I switched from
re-running the pass (!!! mid way through some other passes run!!!) to
directly recomputing the domtree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199104 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Fix retq/retl handling in 64-bit mode

This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.

Previously we only used GPR for the destination placeholder in "ldr rD, [pc,
incorrect codegen under the integrated assembler.

This should fix both issues (which probably only affect MachO targets at the
moment).

rdar://problem/15800156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199108 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: add test for r199108. Oops.

rdar://problem/15800156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199109 91177308-0d34-0410-b5e6-96231b3b80d8
fix a -Wdocumentation warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199113 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Optimize (sext (ashr (shl ...), ...))

...into (ashr (shl (anyext X), ...), ...), which requires one fewer
instruction.  The (anyext X) can sometimes be simplified too.

I didn't do this in DAGCombiner because widening shifts isn't a win
on all targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Improve risbg-01.ll test

The old mask in f24 wasn't well chosen because the lshr would always be zero.
CodeGen didn't detect this but InstCombine would.  The new mask ensures
that both shifts are needed.

f26 is specifically testing for a wrap-around mask.  The AND can be applied
to just the shift left, either before or after the shift.  Again, CodeGen
kept it in the original form but InstCombine would mask after the shift
instead.  The exact choice of NILF isn't important for the test so I just
dropped it and kept the rotate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199115 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add "volatile" to a dead store in variable-loc.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199116 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Flesh out stackrestore test (frame-11.ll)

...so that it does something vaguely sensible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199117 91177308-0d34-0410-b5e6-96231b3b80d8
Fix indentation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199118 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Fix assertion failure caused by an invalid comparison between APInt values.

APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.

With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
Update getLazyBitcodeModule to use ErrorOr for error handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199125 91177308-0d34-0410-b5e6-96231b3b80d8
Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks

The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
Hide the pre-RA-sched= option.

This is a very confusing option for a feature that will go away.

-enable-misched is exposed instead to help triage issues with the new
scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199133 91177308-0d34-0410-b5e6-96231b3b80d8
[DAG] Teach DAG to also reassociate vector operations

This commit teaches DAG to reassociate vector ops, which in turn enables
constant folding of vector op chains that appear later on during custom lowering
and DAG combine.

Reviewed by Andrea Di Biagio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199135 91177308-0d34-0410-b5e6-96231b3b80d8
Add a check that the host compiler is modern to CMake, take 1. This is
likely to be reverted and re-applied a few times. The minimum versions
we're aiming at:

  GCC 4.7
  Clang 3.1
  MSVC 17.0 (Visual Studio 2012)

Let me know if something breaks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199145 91177308-0d34-0410-b5e6-96231b3b80d8
[DAG] Refactor ReassociateOps - no functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199146 91177308-0d34-0410-b5e6-96231b3b80d8