[mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction

Summary:
b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias
for 'bgezal $zero, $offset') still remains with the same encoding it had
prior to MIPS32r6/MIPS64r6.

Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the
MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo.

No changes were required to the CodeGen test that looks for BAL
(test/CodeGen/Mips/longbranch.ll) since the new instruction has the same
syntax.

Depends on D4113

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210898 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6

Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4115

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210899 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add cache and pref instructions

Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210901 91177308-0d34-0410-b5e6-96231b3b80d8