ENGR00298393 pcie: rc can access mem of ep

- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
- change the test region size to be 15MB.

NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/platform/imx-pcie/ep_bar0_addr

1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000

0x40000000:  EFE9EDF4 7583FB39 39EAFFEA FBDCFD78

step2:
RC side:
memtool -32 0x01000000=58D454DA
memtool -32 0x01000004=7332095B

step3:
EP side:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000

0x40000000:  58D454DA 7332095B 39EAFFEA FBDCFD78

Signed-off-by: Richard Zhu <r65037@freescale.com>
ENGR00298394 pcie: enable imx pcie ep msi demo

- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system

Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images

- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #

- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
496:          1          0          0          0  PCIe-MSI

- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000

- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
496:          2          0          0          0  PCIe-MSI

Signed-off-by: Richard Zhu <r65037@freescale.com>
Add Xillybus driver to driver/char/ in a separate directory

For more information about Xillybus, see http://xillybus.com

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Xillybus driver added to Kconfig and Makefile in drivers/char/

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
ENGR00300417: [MX6SL] Add 100M and 24M MMDC parameters for MX6SL LPDDR2

Use different MMDC parameters for 100M and 24M of i.MX6SL LPDDR2

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00267929: [MX6SL] Add DDR3 support for MX6SL

Add DDR3 support for MX6SL

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00306276: iMX6: Add workaround for ARM errata 761320 and 794072

These are Category B, hence workaround is essential.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
ENGR00306397 [#1118] use BUG_ON to check if GPU clock is off

Access GPU register will cause system hang(bus lock-up) without log when clock is off,
GPU kernel BUG_ON is added to check if GPU clock is off when read & write GPU registers,

GPU clock issue can be easily identified with the detailed kernel panic log as below:

kernel BUG at drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c:2423!
Unable to handle kernel NULL pointer dereference at virtual address 0000000
...
[<c0050008>] (__bug+0x1c/0x28) from [<c046bb3c>] (gckOS_ReadRegisterEx+0xbc/0xdc)
[<c046bb3c>] (gckOS_ReadRegisterEx+0xbc/0xdc) from [<c047eab4>] (gckHARDWARE_QueryIdle+0x4c/0xbc)
[<c047eab4>] (gckHARDWARE_QueryIdle+0x4c/0xbc) from [<c0475e0c>] (_TryToIdleGPU+0x70/0x12c)

Mutex protection is not necessary for interrupt handling, because GPU clock is only turned off
by interrupt worker thread during clock gating.

Date: Apr 11, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
ENGR00310166 [#1157] disable GPU recovery function

Disable GPU auto recovery so that GPU can dump the stack.
GPU support auto recovery function, when GPU meet some issue
it will try to do recovery, but most of cases GPU can't really
recovery, we do find some cases GPU can recovery for example
some 2D hang, but customer is not accept such recovery, so show
the GPU stack dump and find the root cause is the correct way.

Date: Apr 24, 2014

Signed-off-by: Richard Liu <r66033@freescale.com>
ENGR00309915 [#1087] enhanced video memory mutex

this patch can fix NULL pointer issue in GPU kernel driver with the following log

[<7f240438>] (gckEVENT_AddList+0x0/0x810 [galcore]) from [<7f239ebc>] (gckCOMMAND_Commit+0xf28/0x118c [galcore])
[<7f238f94>] (gckCOMMAND_Commit+0x0/0x118c [galcore]) from [<7f2362dc>] (gckKERNEL_Dispatch+0x120c/0x24e4 [galcore])
[<7f2350d0>] (gckKERNEL_Dispatch+0x0/0x24e4 [galcore]) from [<7f222280>] (drv_ioctl+0x390/0x540 [galcore])
[<7f221ef0>] (drv_ioctl+0x0/0x540 [galcore]) from [<800facd0>] (vfs_ioctl+0x30/0x44)

The false code is at 0x217bc where the 0-pointer happens (r3 = 0)

gcuVIDMEM_NODE_PTR node = (gcuVIDMEM_NODE_PTR)(gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node));
   217b8:                e5953028             ldr           r3, [r5, #40]         ; 0x28

                if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
   217bc:                e5932000             ldr           r2, [r3]
   217c0:                e5922000             ldr           r2, [r2]
   217c4:                e152000a             cmp       r2, sl
                {
                     gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,

Date: Apr 23, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
ENGR00308899 [#1087] enhanced GPU database protection

the potential risk is found in special case when application exit,
deleting record will cause the unexpected issue when process database is destoryed without atom protection

the enhanced database patch should be applied to avoid the unexpected kernel issue

Date: Apr 17, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
ENGR00306335 External SD content cannot refresh upon removal/insertion after suspend

Disable CONFIG_MMC_BLOCK_DEFERRED_RESUME in android configuration

Signed-off-by: Ke Qinghua <qinghua.ke@freescale.com>
ENGR00306992-2 gpu:gpu2d may cause bus hang in some corner case

Vivante patch name:
fix_fsl_2d_base_on_p13.v2.rls.diff

-Updated the outstanding request limit to 12.
-Refined the 2D chip feature check.
-Refine the 2D cache flush operation
(avoid FE and PE access memory through the same port).
-Enable cache flush for filterblt.
-Dynamic enabling SPLIT_RECT by checking chip feature(disable for us)
-Use brush stretch blt for clear operation.
-Enable SplitFilterBlit to workaround the 2d hang issue in filterblit case.
-Refine 2d line operation.

Date: May 05, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
ENGR00312477 [#1162] fixed gpu lower memory killer

mutex operation is performed in gckKERNEL_QueryProcessDB
remove spinlock for gckKERNEL_QueryProcessDB to avoid scheduling issue

Date: May 08, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
ENGR00311724: ARM: mxc: fix system reboot failed if wdog1 have been started

Trigger SRS of watchdog1 on imx6sl-evk instead of timeout event while system
reboot, because watchdog1 sometimes may be used by userspace. In this case,
watchdog driver will set the max timeout value --128 seconds on i.mx6 before
the watchdog driver shutdown. That will cause system report below reboot error
and reboot after 128 seconds:

root@evk_6sl:/ # reboot
SysRq : Emergency Remount R/O
EXT4-fs (mmcblk0p4): re-mounted. Opts: (null)
imx2-wdt imx2-wdt.0: Device shutdown: Expect reboot!
Restarting system with command ''.
Watchdog reset failed to assert reset
Reboot failed -- System halted

Signed-off-by: Robin Gong <b38343@freescale.com>
ENGR00309951 MX6sl EVK: improve PWM bl period based on tests

There is a SEIKO WVGA panel on the MX6sl EVK platform.
PWM1 is used to control the panel's backlight brightness by
connecting the VLED+ and VLED- pins of the panel after some
hardware conversion logic on board.  The panel's spec doesn't
mention if it's backlight brightness can be tuned or not.
Anyway, the brightness can be tuned via the PWM approach,
based on experiments.  An alternative is to add a new GPIO
backlight device driver for this.  But, a panel with a
configurable backlight brightness is necessary for a smart
device, for example, on the Android platform.  The original
PWM backlight period is too short for the panel, which causes
the brightness can not be steadily increased or decreased if
we change the brightness in one direction.  This patch
improves the period from 50000ns to 1000000ns.  The new period
is an value based on tests.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
fbdev: add events for early fb event support

Add FB_EARLY_EVENT_BLANK and FB_R_EARLY_EVENT_BLANK event mode supports.
first, fb_notifier_call_chain() is called with FB_EARLY_EVENT_BLANK and
fb_blank() of specific fb driver is called and then
fb_notifier_call_chain() is called with FB_EVENT_BLANK again at
fb_blank().  and if fb_blank() was failed then fb_nitifier_call_chain()
would be called with FB_R_EARLY_EVENT_BLANK to revert the previous
effects.

Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
(cherry picked from commit bf05929f41d6c3c79ec1961d90d808a634f09dd9)
ENGR00303539-1 MX6sl EVK: Use standard API to register Seiko panel pdev

Instead of using mxc_register_device(), this patch changes to use
the standard API platform_device_register() to register Seiko WVGA
LCD panel platform device.  The original one would overwrite the
device platform data with the second parameter, which makes us have
to provide a non-NULL second parameter if we want to set the device
platform data.  By using the standard API, we can register the
platform device with a platform_device structure directly which
has a real device platform data embedded.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
ENGR00303539-2 video: mxc: Seiko WVGA panel: Add DISP pin logic

The Seiko WVGA LCD panel has a DISP pin to enable or disable the display.
The DISP pin signal could be described by the following graph according
to the panel's spec.
                 _____________________________________
power      _____|                                     |_____
                    ________________________________
DISP       ________|                                |_______
           ________  _____  _______________________  _______
           invalid \/blank\/        valid          \/
data       ________/\_____/\_______________________/\_______
                             ______________________
backlight  _________________|                      |________

This patch adds some logic in FB_EARLY_EVENT_BLANK and FB_EVENT_BLANK
notifier handlers in the panel driver to enable and disable the pin
respectively.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
ENGR00303539-3 MX6sl EVK: Add Seiko WVGA panel platform dev data

This patch adds Seiko WVGA LCD panel platform device data to
provide enable/disable pin hooks.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>