ARM: SPL: do not set gd again

Just before calling board_init_f, crt0.S has already
reserved space for the initial gd on the stack. There
should be no need to allocate it again.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
cc-option: also detect unsupported warnings options

By default clang will echo a warning if a warning option is
unknown. Turning warnings into errors when polling for options
also catches such cases and prevents passing arguments to the
compiler which cause warnings.

cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
ARM: make gd a function for clang

"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]

Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.

[1] http://clang.llvm.org/docs/UsersManual.html

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
eabi_compat: add __aeabi_memcpy __aeabi_memset

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
clang: workaround for generated constants

KBuild abuses the asm statement to write to a file and
clang chokes about these invalid asm statements. Hack it
even more by fooling this is actual valid asm code.

cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
net: fec_mxc: Adjust RX DMA alignment for mx6solox

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
imx: ventana: updated notes regarding NAND boot errata

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
imx: ventana: base SPL MMDC calibration on width and size not board

The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.

This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
imx: ventana: add GW5520 support

The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
 * 2x MiniPCIe sockets
 * 2x USB host sockets
 * 2x i210 GigE
 * HDMI out
 * digital I/O expansion

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
imx: ventana: added cputype env var

There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env
variable that tells you which type you have.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
mx6: add clock enabling functions

Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
compulab: eeprom: add support for defining eeprom i2c bus

Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
sata: dwc_ahsata: implement sata_port_status

Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
i2c: imx: add macros to setup pads for multiple SoC types

Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
arm: mx6: ddr: cleanup

No functional changes.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
arm: mx6: ddr: do not write into reserved bit

Bit 16 in mapsr register is in a reserved field. Don't write to it.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
arm: mx6: ddr: configure MMDC for slow_pd

According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).

Configure MMDC for slow pd.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>
arm: mx6: ddr: fix cs0_end calculation

Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.

This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.

Refactor the calculation.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
arm: mx6: add get_cpu_type()

Define get_cpu_type(). Reuse it in is_cpu_type().

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>