Add i32 vector read/write helpers
disas_simd_3same_int: review fixes

- moved NeonGenFn to top of file, rename to NeonGenTwoOpFn
- used read/write_vec_element_i32 where appropriate
- rename tables to fns(), made static const
disas_simd_3same_logic: fixes from review

- skip tcg_not and use tcg_${logic}c forms instead
target-arm: A64: Add SIMD shift by immediate

This implements a subset of the AdvSIMD shift operations (namely all the
none saturating or narrowing ones). The actual shift generation code
itself is common for both the scalar and vector cases but wrapped with
either vector element iteration or the fp reg access.

The rounding operations need to take special care to correctly reflect
the result of adding rounding bits on high bits as the intermediates do
not truncate.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 (ajb):
   - port to new framework/APIs
   - ensure we correctly sign extend when needed
   - catch all ReservedValues
   - fix unallocated/unsupported ambiguities
   - ensure round_const properly cast to 64bit
   - use 128bit arithmetic to properly handle rounding
   - fix sizes for sshll2/sxtl widening insns
   - catch special cases of shift of #64 (tcg banckend NOP)
   - add SLI

v4 (ajb)
   - new names for vector helper functions

v5 (ajb)
   - clean up wording of comments
   - rm stray trace operation
   - improve codegen for extended case
   - use built in extension helper
   - don't bother calculating ebytes (we have esize)
   - rm pointless check for !immh
   - push calculations as far down a possible
   - only calculate lshift for size == 3
   - remove double shift, either it's zeros or sign bit

v6 (pmm)
   - minor style cleanups

v7 (ajb)
   - common shift code between Scalar and Vector forms
   - split decoder into separate calls for SHR, SHL and SHLL forms
   - added SIMD Scalar shift immediate instructions
   - check patch fixes
   - tidy up header comments

v8 (ajb):
   - rename functions to XXi for consistancy

v9 (ajb):
   - use clear_vec_high()
   - fix comment spacing

v10 (ajb):
   - use deposit instead of shift and mask for insert case
target-arm: A64: Add SIMD two reg misc

This is a sub-set of the whole opcode field including SIMD vector
versions of:

* XTN, XTN2
* FABS, FNEG
* NOT, RBIT
* NEG

The following are additions to the original SUSE tree.

* REV, REV32, REV64
* CNT

---

v2 (ajb):
  - convert to new APIs

v3 (ajb):
  - some fixups for XTN and XTN2
  - fix tcg temp leaks (use auto-free due to exit paths)
  - use neon_cnt helper for CNT
  - add REV16..64 vector versions
  - rm scalar code (not in this leg of decoder)

v4 (ajb):
  - use read/write_vec_element_i32
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 (ajb)
   - checkpatch.pl fixes
rm unused field
scripts/qemu-binfmt-conf.sh: re-factor and clean-up

I was looking to set-up for development but found the script made some
hard-coded assumptions. It doesn't seem the script is used by the
distros but if it had a little more love maybe it would be ;-)

* Add usage() instructions
* Move all registering to a single function
* Check for existence of executable qemu before registering
* Add -d (devel) mode for subscribing in-src tree binaries
* error handling when setting binfmt fails
* add support for aarch64
scripts/qemu-binfmt-check.py: a binfmt checker

This script allows you to check if a given binary will match against any
of the currently registered binfmts on the system.

---

v2 (ajb):
   - cleaned up whitespace and checkpatch fixes
linux-user: Implement sendmmsg syscall

Glibc when built for newer kernels assumes that the sendmmsg syscall is available.
Without it, dns resolution simply fails to work.

Wrap the syscall with existing infrastructure so that we don't have a host dependency
on sendmmsg.

Signed-off-by: Alexander Graf <agraf@suse.de>