genalloc: Correct nbytes calculation on long boundary

In existing code we calculate nbytes based on the byte
boundary, but genalloc uses bitmap for maintaining the
memory allocation aligned to long. So while calculating
nbytes we end up getting wrong nbytes.
example: lets say nbytes comes to 9 bytes for 70 bits when
bytes aligned,but if long aligned we will have 3 long words
i.e 12 bytes. This difference may lead to choosing the
wrong api for freeing the memory i.e Between kfree() and
vfree().
Fix was inspired by an upstream commit
eedce141cd2dad8d0cefc5468ef41898949a7031, bringing same fix
into the gen_pool_detroy path.

Change-Id: I942caf59e25515c780896b328b912604df9e10bf
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
leds: At disable, set the trigger to default instead of wiping it

Change-Id: Ifb4a3b3034c441d29fd1d9f209ed829adfc76a72

Signed-off-by: revjunkie <gadgetjuan@gmail.com>
ARM: dts: msm: add perf-events support for msm8226

Add the device definitions for the Cortex-A7
PMU on msm8226.

Change-Id: I8752ec03ddc3d6d21bf1b996e81eaca7fb57d8b4
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: Fix counts across power collapse

After entry and exit from power collapse, the perf pm_notifier was
calling perf_pmu_disable/enable functions from perf core. Perf core
maintains a counter that it uses to match disable and enable calls but
since pm_notifier is invoked asynchronously, the counter was getting a
non-zero value which prevented the pmu from being enabled. As a result of
this, we were seeing zero counts for some cores across power collapse.

Make the architecture specific calls directly from pm_notifier.

Change-Id: I744e190906a20e70e1e4798235215c385018b121
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
ARM: dts: msm: add perf-events support for msm8x10, msm8x12

Add the device definitions for the Cortex-A7
PMU on msm8x10.

Change-Id: I0e45c01cec2c92e437cc11cee88777bca271b839
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: Make per-process counters configurable

Add feature to enable/disable per-process tracecounters at run-time.

Change-Id: Id6a4c7a0ecd1f5add85464c6ed260860e15c4e3b
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
msm: perf: Add L2 support for tracecounters

Add L2 counter output to the tracecounters implementation.
This enables collection of L2 PMU counter values upon context switch.
Set up filtering based on number of L2 counters and number of cores.
Read L2 counter values and display them along with L1 counter values.

Change-Id: I8bbbd251ee52c66505d22ccf037c601013a916f0
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: keep events across hotplug

Keep event list alive across a CPU hotplug so that perf
can resume when the CPU comes back online. Bring a CPU
online when exiting a perf session so it can be cleaned
up properly.

Change-Id: Ie0e4a43f751beb77afdc84e9d52b21780f279d80
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: bring CPU online if needed when disabling irq

When disabling an irq, check that the CPU is online
before trying to run on that CPU. Bring the CPU
online if necessary.

This fixes a problem where a CPU that was not online
when disabling the irq caused the disable and the
free to fail. A subsequent attempt to request the irq
also failed because it had not been freed.

Change-Id: Ib873b5ded83ab843ea4e609f196a31ef0083a213
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: Support sw events across hotplug

When CPUs are hotplugged off and on, let the various
sw events continue after the hotplug.

Change-Id: Id1aaf30c459c9cf7c9c38967f9ccad56d4062fd3
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
msm: perf: initialise krait perf L2 counter enables

Clear the L2 counter enables at initialisation.
They are undefined out of reset.

Change-Id: I957106012625ae09efec47d4f657381963d87a5a
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: Make per-process counters cumulative

In order to get overall value for performance counters, remove reset during
context switches. Add mechanism to calculate deltas for output to the trace
buffer.

Change-Id: I03d894a1b3bd400d8c256c3068f917ed001fbfd9
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: Make per-process counters cumulative\n
Perf: Fix PID for tracepoints

Make previous value of PID a per_cpu variable.
This is required to get the correct value for previous_pid.

Change-Id: I63baf8164ae9226189c745339b122d806901789d
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: Fix PID for tracepoints"
Perf: preserve registers across hotplug

Preserve the registers with userspace bits in them
across hotplug and power collapse. This allows
userspace applications to use the performance counters.

Change-Id: I391563ab770df9aabb5d717b6bc4725750ad0283
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
Perf: preserve registers across hotplug
msm: perf: fix formatting of trace entry

Remove extraneous comma which breaks processing of
the trace data.

Change-Id: I5fda44cde6a39b16be06c72bc968afc19636b32f
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>
msm: perf: Fix cpu id logic in tracectr notifier

The code in tracecounter context switch notifier was using
smp_processor_id() in order to get cpu number. This was resulting
into following dmesg error: "BUG: using smp_processor_id() in
preemptible [00000000] code".
Use thread_info struct to get the cpu #.

Change-Id: Ic7c995d2c2bc25c4389248854dec91fb84ce3128
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>