basic structure is set up, tools, src, sim, sw, added
src_v2:
 SD Host can read data in 4 Bit mode and audio plays correctly.
 Edited all std_logic(_vector) to std_ulogic(_vector) in design (especially plasma)
 Removed Old RAM HDL descriptions (Inferring stuff...) and replaced them with
 Altera Memory stuff.
 Added QuadSpiIf and InitQuadSpi for interfacing Q-SPI flash memory on ATLYS Board.
 Last version of Altera/Terasic DE0 implementation.
src_v3:
 Changing Terasic DE0 implementations to Digitlent ATLYS implementations.
 From now on, all packages are supposed to have 'Pkg' as postfix in their filenames.
 Added UART implementations
src_v4:
 Removed Cs4334 implementation due to redundancy.
src_v5:
 Replaced ATLYS with Digilent ZedBoard
 Removed:
  - LCD and 7Seg
  - Plasma
  - SdCard
  - UART
  - Memory